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43e9d192 | 1 | ; Machine description for AArch64 architecture. |
99dee823 | 2 | ; Copyright (C) 2009-2021 Free Software Foundation, Inc. |
43e9d192 IB |
3 | ; Contributed by ARM Ltd. |
4 | ; | |
5 | ; This file is part of GCC. | |
6 | ; | |
7 | ; GCC is free software; you can redistribute it and/or modify it | |
8 | ; under the terms of the GNU General Public License as published by | |
9 | ; the Free Software Foundation; either version 3, or (at your option) | |
10 | ; any later version. | |
11 | ; | |
12 | ; GCC is distributed in the hope that it will be useful, but | |
13 | ; WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | ; General Public License for more details. | |
16 | ; | |
17 | ; You should have received a copy of the GNU General Public License | |
18 | ; along with GCC; see the file COPYING3. If not see | |
19 | ; <http://www.gnu.org/licenses/>. | |
20 | ||
21 | HeaderInclude | |
22 | config/aarch64/aarch64-opts.h | |
23 | ||
361fb3ee KT |
24 | TargetVariable |
25 | enum aarch64_processor explicit_tune_core = aarch64_none | |
26 | ||
27 | TargetVariable | |
28 | enum aarch64_arch explicit_arch = aarch64_no_arch | |
29 | ||
30 | TargetSave | |
31 | const char *x_aarch64_override_tune_string | |
32 | ||
33 | TargetVariable | |
28108a53 | 34 | uint64_t aarch64_isa_flags = 0 |
361fb3ee | 35 | |
30afdf34 SD |
36 | TargetVariable |
37 | unsigned aarch64_enable_bti = 2 | |
38 | ||
43e9d192 IB |
39 | ; The TLS dialect names to use with -mtls-dialect. |
40 | ||
41 | Enum | |
42 | Name(tls_type) Type(enum aarch64_tls_type) | |
43 | The possible TLS dialects: | |
44 | ||
45 | EnumValue | |
46 | Enum(tls_type) String(trad) Value(TLS_TRADITIONAL) | |
47 | ||
48 | EnumValue | |
49 | Enum(tls_type) String(desc) Value(TLS_DESCRIPTORS) | |
50 | ||
51 | ; The code model option names for -mcmodel. | |
52 | ||
53 | Enum | |
54 | Name(cmodel) Type(enum aarch64_code_model) | |
55 | The code model option names for -mcmodel: | |
56 | ||
57 | EnumValue | |
58 | Enum(cmodel) String(tiny) Value(AARCH64_CMODEL_TINY) | |
59 | ||
60 | EnumValue | |
61 | Enum(cmodel) String(small) Value(AARCH64_CMODEL_SMALL) | |
62 | ||
63 | EnumValue | |
64 | Enum(cmodel) String(large) Value(AARCH64_CMODEL_LARGE) | |
65 | ||
43e9d192 | 66 | mbig-endian |
eece52b5 | 67 | Target RejectNegative Mask(BIG_END) |
a7b2e184 | 68 | Assume target CPU is configured as big endian. |
43e9d192 IB |
69 | |
70 | mgeneral-regs-only | |
eece52b5 | 71 | Target RejectNegative Mask(GENERAL_REGS_ONLY) Save |
a7b2e184 | 72 | Generate code which uses only the general registers. |
43e9d192 | 73 | |
a9ba2a9b MM |
74 | mharden-sls= |
75 | Target RejectNegative Joined Var(aarch64_harden_sls_string) | |
76 | Generate code to mitigate against straight line speculation. | |
77 | ||
75cf1494 | 78 | mfix-cortex-a53-835769 |
eece52b5 | 79 | Target Var(aarch64_fix_a53_err835769) Init(2) Save |
a7b2e184 | 80 | Workaround for ARM Cortex-A53 Erratum number 835769. |
75cf1494 | 81 | |
bf05ef76 | 82 | mfix-cortex-a53-843419 |
eece52b5 | 83 | Target Var(aarch64_fix_a53_err843419) Init(2) Save |
a7b2e184 | 84 | Workaround for ARM Cortex-A53 Erratum number 843419. |
bf05ef76 | 85 | |
43e9d192 | 86 | mlittle-endian |
eece52b5 | 87 | Target RejectNegative InverseMask(BIG_END) |
a7b2e184 | 88 | Assume target CPU is configured as little endian. |
43e9d192 IB |
89 | |
90 | mcmodel= | |
361fb3ee | 91 | Target RejectNegative Joined Enum(cmodel) Var(aarch64_cmodel_var) Init(AARCH64_CMODEL_SMALL) Save |
a7b2e184 | 92 | Specify the code model. |
43e9d192 IB |
93 | |
94 | mstrict-align | |
eece52b5 | 95 | Target Mask(STRICT_ALIGN) Save |
a7b2e184 | 96 | Don't assume that unaligned accesses are handled by the system. |
43e9d192 IB |
97 | |
98 | momit-leaf-frame-pointer | |
eece52b5 | 99 | Target Var(flag_omit_leaf_frame_pointer) Init(2) Save |
a7b2e184 | 100 | Omit the frame pointer in leaf functions. |
43e9d192 IB |
101 | |
102 | mtls-dialect= | |
361fb3ee | 103 | Target RejectNegative Joined Enum(tls_type) Var(aarch64_tls_dialect) Init(TLS_DESCRIPTORS) Save |
a7b2e184 | 104 | Specify TLS dialect. |
43e9d192 | 105 | |
5eee3c34 JW |
106 | mtls-size= |
107 | Target RejectNegative Joined Var(aarch64_tls_size) Enum(aarch64_tls_size) | |
108 | Specifies bit size of immediate TLS offsets. Valid values are 12, 24, 32, 48. | |
109 | ||
110 | Enum | |
111 | Name(aarch64_tls_size) Type(int) | |
112 | ||
113 | EnumValue | |
114 | Enum(aarch64_tls_size) String(12) Value(12) | |
115 | ||
116 | EnumValue | |
117 | Enum(aarch64_tls_size) String(24) Value(24) | |
118 | ||
119 | EnumValue | |
120 | Enum(aarch64_tls_size) String(32) Value(32) | |
121 | ||
122 | EnumValue | |
123 | Enum(aarch64_tls_size) String(48) Value(48) | |
124 | ||
43e9d192 | 125 | march= |
6fdbe419 | 126 | Target RejectNegative Negative(march=) ToLower Joined Var(aarch64_arch_string) |
266c2b54 | 127 | Use features of architecture ARCH. |
43e9d192 IB |
128 | |
129 | mcpu= | |
6fdbe419 | 130 | Target RejectNegative Negative(mcpu=) ToLower Joined Var(aarch64_cpu_string) |
266c2b54 | 131 | Use features of and optimize for CPU. |
43e9d192 IB |
132 | |
133 | mtune= | |
6fdbe419 | 134 | Target RejectNegative Negative(mtune=) ToLower Joined Var(aarch64_tune_string) |
266c2b54 | 135 | Optimize for CPU. |
17a819cb YZ |
136 | |
137 | mabi= | |
138 | Target RejectNegative Joined Enum(aarch64_abi) Var(aarch64_abi) Init(AARCH64_ABI_DEFAULT) | |
266c2b54 | 139 | Generate code that conforms to the specified ABI. |
17a819cb | 140 | |
8dec06f2 JG |
141 | moverride= |
142 | Target RejectNegative ToLower Joined Var(aarch64_override_tune_string) | |
266c2b54 | 143 | -moverride=<string> Power users only! Override CPU optimization parameters. |
8dec06f2 | 144 | |
17a819cb YZ |
145 | Enum |
146 | Name(aarch64_abi) Type(int) | |
147 | Known AArch64 ABIs (for use with the -mabi= option): | |
148 | ||
149 | EnumValue | |
150 | Enum(aarch64_abi) String(ilp32) Value(AARCH64_ABI_ILP32) | |
151 | ||
152 | EnumValue | |
153 | Enum(aarch64_abi) String(lp64) Value(AARCH64_ABI_LP64) | |
b4f50fd4 RR |
154 | |
155 | mpc-relative-literal-loads | |
eece52b5 | 156 | Target Save Var(pcrelative_literal_loads) Init(2) Save |
b4f50fd4 | 157 | PC relative literal loads. |
a6fc00da | 158 | |
efac62a3 ST |
159 | mbranch-protection= |
160 | Target RejectNegative Joined Var(aarch64_branch_protection_string) Save | |
161 | Use branch-protection features. | |
162 | ||
db58fd89 | 163 | msign-return-address= |
68a57628 | 164 | Target WarnRemoved RejectNegative Joined Enum(aarch64_ra_sign_scope_t) Var(aarch64_ra_sign_scope) Init(AARCH64_FUNCTION_NONE) Save |
db58fd89 JW |
165 | Select return address signing scope. |
166 | ||
167 | Enum | |
168 | Name(aarch64_ra_sign_scope_t) Type(enum aarch64_function_type) | |
169 | Supported AArch64 return address signing scope (for use with -msign-return-address= option): | |
170 | ||
171 | EnumValue | |
172 | Enum(aarch64_ra_sign_scope_t) String(none) Value(AARCH64_FUNCTION_NONE) | |
173 | ||
174 | EnumValue | |
175 | Enum(aarch64_ra_sign_scope_t) String(non-leaf) Value(AARCH64_FUNCTION_NON_LEAF) | |
176 | ||
177 | EnumValue | |
178 | Enum(aarch64_ra_sign_scope_t) String(all) Value(AARCH64_FUNCTION_ALL) | |
179 | ||
a6fc00da | 180 | mlow-precision-recip-sqrt |
88e25f47 | 181 | Target Var(flag_mrecip_low_precision_sqrt) Optimization |
98daafa0 EM |
182 | Enable the reciprocal square root approximation. Enabling this reduces |
183 | precision of reciprocal square root results to about 16 bits for | |
184 | single precision and to 32 bits for double precision. | |
185 | ||
186 | mlow-precision-sqrt | |
88e25f47 | 187 | Target Var(flag_mlow_precision_sqrt) Optimization |
98daafa0 EM |
188 | Enable the square root approximation. Enabling this reduces |
189 | precision of square root results to about 16 bits for | |
190 | single precision and to 32 bits for double precision. | |
191 | If enabled, it implies -mlow-precision-recip-sqrt. | |
79a2bc2d EM |
192 | |
193 | mlow-precision-div | |
88e25f47 | 194 | Target Var(flag_mlow_precision_div) Optimization |
79a2bc2d EM |
195 | Enable the division approximation. Enabling this reduces |
196 | precision of division results to about 16 bits for | |
197 | single precision and to 32 bits for double precision. | |
c10e3d7f | 198 | |
43cacb12 RS |
199 | Enum |
200 | Name(sve_vector_bits) Type(enum aarch64_sve_vector_bits_enum) | |
201 | The possible SVE vector lengths: | |
202 | ||
203 | EnumValue | |
204 | Enum(sve_vector_bits) String(scalable) Value(SVE_SCALABLE) | |
205 | ||
206 | EnumValue | |
207 | Enum(sve_vector_bits) String(128) Value(SVE_128) | |
208 | ||
209 | EnumValue | |
210 | Enum(sve_vector_bits) String(256) Value(SVE_256) | |
211 | ||
212 | EnumValue | |
213 | Enum(sve_vector_bits) String(512) Value(SVE_512) | |
214 | ||
215 | EnumValue | |
216 | Enum(sve_vector_bits) String(1024) Value(SVE_1024) | |
217 | ||
218 | EnumValue | |
219 | Enum(sve_vector_bits) String(2048) Value(SVE_2048) | |
220 | ||
221 | msve-vector-bits= | |
222 | Target RejectNegative Joined Enum(sve_vector_bits) Var(aarch64_sve_vector_bits) Init(SVE_SCALABLE) | |
f499726a | 223 | -msve-vector-bits=<number> Set the number of bits in an SVE vector register. |
43cacb12 | 224 | |
c10e3d7f | 225 | mverbose-cost-dump |
88e25f47 | 226 | Target Undocumented Var(flag_aarch64_verbose_cost) |
d1132c1b | 227 | Enables verbose cost model dumping in the debug dump files. |
3b0c2502 RE |
228 | |
229 | mtrack-speculation | |
230 | Target Var(aarch64_track_speculation) | |
231 | Generate code to track when the CPU might be speculating incorrectly. | |
cd0b2d36 RR |
232 | |
233 | mstack-protector-guard= | |
234 | Target RejectNegative Joined Enum(stack_protector_guard) Var(aarch64_stack_protector_guard) Init(SSP_GLOBAL) | |
235 | Use given stack-protector guard. | |
236 | ||
237 | Enum | |
238 | Name(stack_protector_guard) Type(enum stack_protector_guard) | |
239 | Valid arguments to -mstack-protector-guard=: | |
240 | ||
241 | EnumValue | |
242 | Enum(stack_protector_guard) String(sysreg) Value(SSP_SYSREG) | |
243 | ||
244 | EnumValue | |
245 | Enum(stack_protector_guard) String(global) Value(SSP_GLOBAL) | |
246 | ||
247 | mstack-protector-guard-reg= | |
248 | Target Joined RejectNegative String Var(aarch64_stack_protector_guard_reg_str) | |
249 | Use the system register specified on the command line as the stack protector | |
250 | guard register. This option is for use with fstack-protector-strong and | |
251 | not for use in user-land code. | |
252 | ||
253 | mstack-protector-guard-offset= | |
254 | Target Joined RejectNegative String Var(aarch64_stack_protector_guard_offset_str) | |
255 | Use an immediate to offset from the stack protector guard register, sp_el0. | |
256 | This option is for use with fstack-protector-strong and not for use in | |
257 | user-land code. | |
258 | ||
259 | TargetVariable | |
260 | long aarch64_stack_protector_guard_offset = 0 | |
261 | ||
3950b229 | 262 | moutline-atomics |
eece52b5 | 263 | Target Var(aarch64_flag_outline_atomics) Init(2) Save |
3950b229 | 264 | Generate local calls to out-of-line atomic operations. |
eb23241b RS |
265 | |
266 | -param=aarch64-sve-compare-costs= | |
267 | Target Joined UInteger Var(aarch64_sve_compare_costs) Init(1) IntegerRange(0, 1) Param | |
268 | When vectorizing for SVE, consider using unpacked vectors for smaller elements and use the cost model to pick the cheapest approach. Also use the cost model to choose between SVE and Advanced SIMD vectorization. | |
dbf3dc75 BL |
269 | |
270 | -param=aarch64-float-recp-precision= | |
271 | Target Joined UInteger Var(aarch64_float_recp_precision) Init(1) IntegerRange(1, 5) Param | |
272 | The number of Newton iterations for calculating the reciprocal for float type. The precision of division is proportional to this param when division approximation is enabled. The default value is 1. | |
273 | ||
274 | -param=aarch64-double-recp-precision= | |
275 | Target Joined UInteger Var(aarch64_double_recp_precision) Init(2) IntegerRange(1, 5) Param | |
276 | The number of Newton iterations for calculating the reciprocal for double type. The precision of division is proportional to this param when division approximation is enabled. The default value is 2. | |
277 | ||
5f29f3d5 KT |
278 | -param=aarch64-autovec-preference= |
279 | Target Joined UInteger Var(aarch64_autovec_preference) Init(0) IntegerRange(0, 4) Param |