]>
Commit | Line | Data |
---|---|---|
43e9d192 | 1 | ; Machine description for AArch64 architecture. |
83ffe9cd | 2 | ; Copyright (C) 2009-2023 Free Software Foundation, Inc. |
43e9d192 IB |
3 | ; Contributed by ARM Ltd. |
4 | ; | |
5 | ; This file is part of GCC. | |
6 | ; | |
7 | ; GCC is free software; you can redistribute it and/or modify it | |
8 | ; under the terms of the GNU General Public License as published by | |
9 | ; the Free Software Foundation; either version 3, or (at your option) | |
10 | ; any later version. | |
11 | ; | |
12 | ; GCC is distributed in the hope that it will be useful, but | |
13 | ; WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | ; General Public License for more details. | |
16 | ; | |
17 | ; You should have received a copy of the GNU General Public License | |
18 | ; along with GCC; see the file COPYING3. If not see | |
19 | ; <http://www.gnu.org/licenses/>. | |
20 | ||
21 | HeaderInclude | |
22 | config/aarch64/aarch64-opts.h | |
23 | ||
d8dadbc9 AC |
24 | HeaderInclude |
25 | config/arm/aarch-common.h | |
26 | ||
361fb3ee | 27 | TargetVariable |
ae54c1b0 | 28 | enum aarch64_processor selected_tune = aarch64_none |
361fb3ee KT |
29 | |
30 | TargetVariable | |
ae54c1b0 | 31 | enum aarch64_arch selected_arch = aarch64_no_arch |
361fb3ee | 32 | |
2a269bda RS |
33 | TargetVariable |
34 | aarch64_feature_flags aarch64_asm_isa_flags = 0 | |
35 | ||
361fb3ee | 36 | TargetVariable |
fed55a60 | 37 | aarch64_feature_flags aarch64_isa_flags = 0 |
361fb3ee | 38 | |
30afdf34 | 39 | TargetVariable |
d8dadbc9 | 40 | unsigned aarch_enable_bti = 2 |
30afdf34 | 41 | |
ae54c1b0 | 42 | TargetVariable |
b1d26458 | 43 | enum aarch_key_type aarch_ra_sign_key = AARCH_KEY_A |
ae54c1b0 | 44 | |
43e9d192 IB |
45 | ; The TLS dialect names to use with -mtls-dialect. |
46 | ||
47 | Enum | |
48 | Name(tls_type) Type(enum aarch64_tls_type) | |
49 | The possible TLS dialects: | |
50 | ||
51 | EnumValue | |
52 | Enum(tls_type) String(trad) Value(TLS_TRADITIONAL) | |
53 | ||
54 | EnumValue | |
55 | Enum(tls_type) String(desc) Value(TLS_DESCRIPTORS) | |
56 | ||
57 | ; The code model option names for -mcmodel. | |
58 | ||
59 | Enum | |
60 | Name(cmodel) Type(enum aarch64_code_model) | |
61 | The code model option names for -mcmodel: | |
62 | ||
63 | EnumValue | |
64 | Enum(cmodel) String(tiny) Value(AARCH64_CMODEL_TINY) | |
65 | ||
66 | EnumValue | |
67 | Enum(cmodel) String(small) Value(AARCH64_CMODEL_SMALL) | |
68 | ||
69 | EnumValue | |
70 | Enum(cmodel) String(large) Value(AARCH64_CMODEL_LARGE) | |
71 | ||
43e9d192 | 72 | mbig-endian |
eece52b5 | 73 | Target RejectNegative Mask(BIG_END) |
a7b2e184 | 74 | Assume target CPU is configured as big endian. |
43e9d192 IB |
75 | |
76 | mgeneral-regs-only | |
eece52b5 | 77 | Target RejectNegative Mask(GENERAL_REGS_ONLY) Save |
a7b2e184 | 78 | Generate code which uses only the general registers. |
43e9d192 | 79 | |
a9ba2a9b MM |
80 | mharden-sls= |
81 | Target RejectNegative Joined Var(aarch64_harden_sls_string) | |
82 | Generate code to mitigate against straight line speculation. | |
83 | ||
75cf1494 | 84 | mfix-cortex-a53-835769 |
eece52b5 | 85 | Target Var(aarch64_fix_a53_err835769) Init(2) Save |
a7b2e184 | 86 | Workaround for ARM Cortex-A53 Erratum number 835769. |
75cf1494 | 87 | |
bf05ef76 | 88 | mfix-cortex-a53-843419 |
eece52b5 | 89 | Target Var(aarch64_fix_a53_err843419) Init(2) Save |
a7b2e184 | 90 | Workaround for ARM Cortex-A53 Erratum number 843419. |
bf05ef76 | 91 | |
43e9d192 | 92 | mlittle-endian |
eece52b5 | 93 | Target RejectNegative InverseMask(BIG_END) |
a7b2e184 | 94 | Assume target CPU is configured as little endian. |
43e9d192 IB |
95 | |
96 | mcmodel= | |
361fb3ee | 97 | Target RejectNegative Joined Enum(cmodel) Var(aarch64_cmodel_var) Init(AARCH64_CMODEL_SMALL) Save |
a7b2e184 | 98 | Specify the code model. |
43e9d192 | 99 | |
573624ec KT |
100 | Enum |
101 | Name(tp_reg) Type(enum aarch64_tp_reg) | |
102 | The register used to access the thread pointer: | |
103 | ||
104 | EnumValue | |
105 | Enum(tp_reg) String(el0) Value(AARCH64_TPIDR_EL0) | |
106 | ||
4389a2d2 KT |
107 | EnumValue |
108 | Enum(tp_reg) String(tpidr_el0) Value(AARCH64_TPIDR_EL0) | |
109 | ||
573624ec KT |
110 | EnumValue |
111 | Enum(tp_reg) String(el1) Value(AARCH64_TPIDR_EL1) | |
112 | ||
4389a2d2 KT |
113 | EnumValue |
114 | Enum(tp_reg) String(tpidr_el1) Value(AARCH64_TPIDR_EL1) | |
115 | ||
573624ec KT |
116 | EnumValue |
117 | Enum(tp_reg) String(el2) Value(AARCH64_TPIDR_EL2) | |
118 | ||
4389a2d2 KT |
119 | EnumValue |
120 | Enum(tp_reg) String(tpidr_el2) Value(AARCH64_TPIDR_EL2) | |
121 | ||
573624ec KT |
122 | EnumValue |
123 | Enum(tp_reg) String(el3) Value(AARCH64_TPIDR_EL3) | |
124 | ||
4389a2d2 KT |
125 | EnumValue |
126 | Enum(tp_reg) String(tpidr_el3) Value(AARCH64_TPIDR_EL3) | |
127 | ||
128 | EnumValue | |
129 | Enum(tp_reg) String(tpidrro_el0) Value(AARCH64_TPIDRRO_EL0) | |
130 | ||
573624ec KT |
131 | mtp= |
132 | Target RejectNegative Joined Enum(tp_reg) Var(aarch64_tpidr_reg) Init(AARCH64_TPIDR_EL0) Save | |
133 | Specify the thread pointer register. | |
134 | ||
43e9d192 | 135 | mstrict-align |
eece52b5 | 136 | Target Mask(STRICT_ALIGN) Save |
a7b2e184 | 137 | Don't assume that unaligned accesses are handled by the system. |
43e9d192 IB |
138 | |
139 | momit-leaf-frame-pointer | |
eece52b5 | 140 | Target Var(flag_omit_leaf_frame_pointer) Init(2) Save |
a7b2e184 | 141 | Omit the frame pointer in leaf functions. |
43e9d192 IB |
142 | |
143 | mtls-dialect= | |
361fb3ee | 144 | Target RejectNegative Joined Enum(tls_type) Var(aarch64_tls_dialect) Init(TLS_DESCRIPTORS) Save |
a7b2e184 | 145 | Specify TLS dialect. |
43e9d192 | 146 | |
5eee3c34 JW |
147 | mtls-size= |
148 | Target RejectNegative Joined Var(aarch64_tls_size) Enum(aarch64_tls_size) | |
149 | Specifies bit size of immediate TLS offsets. Valid values are 12, 24, 32, 48. | |
150 | ||
151 | Enum | |
152 | Name(aarch64_tls_size) Type(int) | |
153 | ||
154 | EnumValue | |
155 | Enum(aarch64_tls_size) String(12) Value(12) | |
156 | ||
157 | EnumValue | |
158 | Enum(aarch64_tls_size) String(24) Value(24) | |
159 | ||
160 | EnumValue | |
161 | Enum(aarch64_tls_size) String(32) Value(32) | |
162 | ||
163 | EnumValue | |
164 | Enum(aarch64_tls_size) String(48) Value(48) | |
165 | ||
43e9d192 | 166 | march= |
6fdbe419 | 167 | Target RejectNegative Negative(march=) ToLower Joined Var(aarch64_arch_string) |
266c2b54 | 168 | Use features of architecture ARCH. |
43e9d192 IB |
169 | |
170 | mcpu= | |
6fdbe419 | 171 | Target RejectNegative Negative(mcpu=) ToLower Joined Var(aarch64_cpu_string) |
266c2b54 | 172 | Use features of and optimize for CPU. |
43e9d192 IB |
173 | |
174 | mtune= | |
6fdbe419 | 175 | Target RejectNegative Negative(mtune=) ToLower Joined Var(aarch64_tune_string) |
266c2b54 | 176 | Optimize for CPU. |
17a819cb YZ |
177 | |
178 | mabi= | |
179 | Target RejectNegative Joined Enum(aarch64_abi) Var(aarch64_abi) Init(AARCH64_ABI_DEFAULT) | |
266c2b54 | 180 | Generate code that conforms to the specified ABI. |
17a819cb | 181 | |
8dec06f2 | 182 | moverride= |
ae54c1b0 | 183 | Target RejectNegative ToLower Joined Var(aarch64_override_tune_string) Save |
266c2b54 | 184 | -moverride=<string> Power users only! Override CPU optimization parameters. |
8dec06f2 | 185 | |
17a819cb YZ |
186 | Enum |
187 | Name(aarch64_abi) Type(int) | |
188 | Known AArch64 ABIs (for use with the -mabi= option): | |
189 | ||
190 | EnumValue | |
191 | Enum(aarch64_abi) String(ilp32) Value(AARCH64_ABI_ILP32) | |
192 | ||
193 | EnumValue | |
194 | Enum(aarch64_abi) String(lp64) Value(AARCH64_ABI_LP64) | |
b4f50fd4 RR |
195 | |
196 | mpc-relative-literal-loads | |
eece52b5 | 197 | Target Save Var(pcrelative_literal_loads) Init(2) Save |
b4f50fd4 | 198 | PC relative literal loads. |
a6fc00da | 199 | |
efac62a3 ST |
200 | mbranch-protection= |
201 | Target RejectNegative Joined Var(aarch64_branch_protection_string) Save | |
202 | Use branch-protection features. | |
203 | ||
db58fd89 | 204 | msign-return-address= |
d8dadbc9 | 205 | Target WarnRemoved RejectNegative Joined Enum(aarch_ra_sign_scope_t) Var(aarch_ra_sign_scope) Init(AARCH_FUNCTION_NONE) Save |
db58fd89 JW |
206 | Select return address signing scope. |
207 | ||
208 | Enum | |
d8dadbc9 | 209 | Name(aarch_ra_sign_scope_t) Type(enum aarch_function_type) |
db58fd89 JW |
210 | Supported AArch64 return address signing scope (for use with -msign-return-address= option): |
211 | ||
212 | EnumValue | |
d8dadbc9 | 213 | Enum(aarch_ra_sign_scope_t) String(none) Value(AARCH_FUNCTION_NONE) |
db58fd89 JW |
214 | |
215 | EnumValue | |
d8dadbc9 | 216 | Enum(aarch_ra_sign_scope_t) String(non-leaf) Value(AARCH_FUNCTION_NON_LEAF) |
db58fd89 JW |
217 | |
218 | EnumValue | |
d8dadbc9 | 219 | Enum(aarch_ra_sign_scope_t) String(all) Value(AARCH_FUNCTION_ALL) |
db58fd89 | 220 | |
a6fc00da | 221 | mlow-precision-recip-sqrt |
88e25f47 | 222 | Target Var(flag_mrecip_low_precision_sqrt) Optimization |
98daafa0 EM |
223 | Enable the reciprocal square root approximation. Enabling this reduces |
224 | precision of reciprocal square root results to about 16 bits for | |
225 | single precision and to 32 bits for double precision. | |
226 | ||
227 | mlow-precision-sqrt | |
88e25f47 | 228 | Target Var(flag_mlow_precision_sqrt) Optimization |
98daafa0 EM |
229 | Enable the square root approximation. Enabling this reduces |
230 | precision of square root results to about 16 bits for | |
231 | single precision and to 32 bits for double precision. | |
232 | If enabled, it implies -mlow-precision-recip-sqrt. | |
79a2bc2d EM |
233 | |
234 | mlow-precision-div | |
88e25f47 | 235 | Target Var(flag_mlow_precision_div) Optimization |
79a2bc2d EM |
236 | Enable the division approximation. Enabling this reduces |
237 | precision of division results to about 16 bits for | |
238 | single precision and to 32 bits for double precision. | |
c10e3d7f | 239 | |
9f0f7d80 RS |
240 | Enum |
241 | Name(early_ra_scope) Type(enum aarch64_early_ra_scope) | |
242 | ||
243 | EnumValue | |
244 | Enum(early_ra_scope) String(all) Value(AARCH64_EARLY_RA_ALL) | |
245 | ||
246 | EnumValue | |
247 | Enum(early_ra_scope) String(strided) Value(AARCH64_EARLY_RA_STRIDED) | |
248 | ||
249 | EnumValue | |
250 | Enum(early_ra_scope) String(none) Value(AARCH64_EARLY_RA_NONE) | |
251 | ||
252 | mearly-ra= | |
253 | Target RejectNegative Joined Enum(early_ra_scope) Var(aarch64_early_ra) Init(AARCH64_EARLY_RA_NONE) Save | |
254 | Specify when to enable an early register allocation pass. The possibilities | |
255 | are: all functions, functions that have access to strided multi-register | |
256 | instructions, and no functions. | |
257 | ||
43cacb12 RS |
258 | Enum |
259 | Name(sve_vector_bits) Type(enum aarch64_sve_vector_bits_enum) | |
260 | The possible SVE vector lengths: | |
261 | ||
262 | EnumValue | |
263 | Enum(sve_vector_bits) String(scalable) Value(SVE_SCALABLE) | |
264 | ||
265 | EnumValue | |
266 | Enum(sve_vector_bits) String(128) Value(SVE_128) | |
267 | ||
268 | EnumValue | |
269 | Enum(sve_vector_bits) String(256) Value(SVE_256) | |
270 | ||
271 | EnumValue | |
272 | Enum(sve_vector_bits) String(512) Value(SVE_512) | |
273 | ||
274 | EnumValue | |
275 | Enum(sve_vector_bits) String(1024) Value(SVE_1024) | |
276 | ||
277 | EnumValue | |
278 | Enum(sve_vector_bits) String(2048) Value(SVE_2048) | |
279 | ||
280 | msve-vector-bits= | |
281 | Target RejectNegative Joined Enum(sve_vector_bits) Var(aarch64_sve_vector_bits) Init(SVE_SCALABLE) | |
f499726a | 282 | -msve-vector-bits=<number> Set the number of bits in an SVE vector register. |
43cacb12 | 283 | |
c10e3d7f | 284 | mverbose-cost-dump |
88e25f47 | 285 | Target Undocumented Var(flag_aarch64_verbose_cost) |
d1132c1b | 286 | Enables verbose cost model dumping in the debug dump files. |
3b0c2502 RE |
287 | |
288 | mtrack-speculation | |
289 | Target Var(aarch64_track_speculation) | |
290 | Generate code to track when the CPU might be speculating incorrectly. | |
cd0b2d36 RR |
291 | |
292 | mstack-protector-guard= | |
293 | Target RejectNegative Joined Enum(stack_protector_guard) Var(aarch64_stack_protector_guard) Init(SSP_GLOBAL) | |
294 | Use given stack-protector guard. | |
295 | ||
296 | Enum | |
297 | Name(stack_protector_guard) Type(enum stack_protector_guard) | |
298 | Valid arguments to -mstack-protector-guard=: | |
299 | ||
300 | EnumValue | |
301 | Enum(stack_protector_guard) String(sysreg) Value(SSP_SYSREG) | |
302 | ||
303 | EnumValue | |
304 | Enum(stack_protector_guard) String(global) Value(SSP_GLOBAL) | |
305 | ||
306 | mstack-protector-guard-reg= | |
307 | Target Joined RejectNegative String Var(aarch64_stack_protector_guard_reg_str) | |
308 | Use the system register specified on the command line as the stack protector | |
309 | guard register. This option is for use with fstack-protector-strong and | |
310 | not for use in user-land code. | |
311 | ||
312 | mstack-protector-guard-offset= | |
313 | Target Joined RejectNegative String Var(aarch64_stack_protector_guard_offset_str) | |
314 | Use an immediate to offset from the stack protector guard register, sp_el0. | |
315 | This option is for use with fstack-protector-strong and not for use in | |
316 | user-land code. | |
317 | ||
318 | TargetVariable | |
319 | long aarch64_stack_protector_guard_offset = 0 | |
320 | ||
3950b229 | 321 | moutline-atomics |
eece52b5 | 322 | Target Var(aarch64_flag_outline_atomics) Init(2) Save |
3950b229 | 323 | Generate local calls to out-of-line atomic operations. |
eb23241b RS |
324 | |
325 | -param=aarch64-sve-compare-costs= | |
326 | Target Joined UInteger Var(aarch64_sve_compare_costs) Init(1) IntegerRange(0, 1) Param | |
327 | When vectorizing for SVE, consider using unpacked vectors for smaller elements and use the cost model to pick the cheapest approach. Also use the cost model to choose between SVE and Advanced SIMD vectorization. | |
dbf3dc75 BL |
328 | |
329 | -param=aarch64-float-recp-precision= | |
330 | Target Joined UInteger Var(aarch64_float_recp_precision) Init(1) IntegerRange(1, 5) Param | |
331 | The number of Newton iterations for calculating the reciprocal for float type. The precision of division is proportional to this param when division approximation is enabled. The default value is 1. | |
332 | ||
333 | -param=aarch64-double-recp-precision= | |
334 | Target Joined UInteger Var(aarch64_double_recp_precision) Init(2) IntegerRange(1, 5) Param | |
335 | The number of Newton iterations for calculating the reciprocal for double type. The precision of division is proportional to this param when division approximation is enabled. The default value is 2. | |
336 | ||
5f29f3d5 KT |
337 | -param=aarch64-autovec-preference= |
338 | Target Joined UInteger Var(aarch64_autovec_preference) Init(0) IntegerRange(0, 4) Param | |
1205a8ca RS |
339 | |
340 | -param=aarch64-loop-vect-issue-rate-niters= | |
341 | Target Joined UInteger Var(aarch64_loop_vect_issue_rate_niters) Init(6) IntegerRange(0, 65536) Param | |
0caf592d KT |
342 | |
343 | -param=aarch64-mops-memcpy-size-threshold= | |
344 | Target Joined UInteger Var(aarch64_mops_memcpy_size_threshold) Init(256) Param | |
345 | Constant memcpy size in bytes above which to start using MOPS sequence. | |
bb768f8b KT |
346 | |
347 | -param=aarch64-mops-memmove-size-threshold= | |
bbdb72ba | 348 | Target Joined UInteger Var(aarch64_mops_memmove_size_threshold) Init(256) Param |
bb768f8b | 349 | Constant memmove size in bytes above which to start using MOPS sequence. |
d3bd985e KT |
350 | |
351 | -param=aarch64-mops-memset-size-threshold= | |
352 | Target Joined UInteger Var(aarch64_mops_memset_size_threshold) Init(256) Param | |
353 | Constant memset size in bytes from which to start using MOPS sequence. | |
40d643d8 AV |
354 | |
355 | -param=aarch64-vect-unroll-limit= | |
356 | Target Joined UInteger Var(aarch64_vect_unroll_limit) Init(4) Param | |
357 | Limit how much the autovectorizer may unroll a loop. | |
834fc2bf MA |
358 | |
359 | -param=aarch64-ldp-policy= | |
574cec45 | 360 | Target Joined Var(aarch64_ldp_policy_param) Enum(aarch64_ldp_stp_policy) Init(AARCH64_LDP_STP_POLICY_DEFAULT) Param |
834fc2bf MA |
361 | --param=aarch64-ldp-policy=[default|always|never|aligned] Fine-grained policy for load pairs. |
362 | ||
834fc2bf | 363 | -param=aarch64-stp-policy= |
574cec45 | 364 | Target Joined Var(aarch64_stp_policy_param) Enum(aarch64_ldp_stp_policy) Init(AARCH64_LDP_STP_POLICY_DEFAULT) Param |
834fc2bf MA |
365 | --param=aarch64-stp-policy=[default|always|never|aligned] Fine-grained policy for store pairs. |
366 | ||
367 | Enum | |
574cec45 | 368 | Name(aarch64_ldp_stp_policy) Type(enum aarch64_ldp_stp_policy) UnknownError(unknown LDP/STP policy %qs) |
834fc2bf MA |
369 | |
370 | EnumValue | |
574cec45 | 371 | Enum(aarch64_ldp_stp_policy) String(default) Value(AARCH64_LDP_STP_POLICY_DEFAULT) |
834fc2bf MA |
372 | |
373 | EnumValue | |
574cec45 | 374 | Enum(aarch64_ldp_stp_policy) String(always) Value(AARCH64_LDP_STP_POLICY_ALWAYS) |
834fc2bf MA |
375 | |
376 | EnumValue | |
574cec45 | 377 | Enum(aarch64_ldp_stp_policy) String(never) Value(AARCH64_LDP_STP_POLICY_NEVER) |
834fc2bf MA |
378 | |
379 | EnumValue | |
574cec45 | 380 | Enum(aarch64_ldp_stp_policy) String(aligned) Value(AARCH64_LDP_STP_POLICY_ALIGNED) |