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aarch64: Rewrite non-writeback ldp/stp patterns
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43e9d192 1; Machine description for AArch64 architecture.
83ffe9cd 2; Copyright (C) 2009-2023 Free Software Foundation, Inc.
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3; Contributed by ARM Ltd.
4;
5; This file is part of GCC.
6;
7; GCC is free software; you can redistribute it and/or modify it
8; under the terms of the GNU General Public License as published by
9; the Free Software Foundation; either version 3, or (at your option)
10; any later version.
11;
12; GCC is distributed in the hope that it will be useful, but
13; WITHOUT ANY WARRANTY; without even the implied warranty of
14; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15; General Public License for more details.
16;
17; You should have received a copy of the GNU General Public License
18; along with GCC; see the file COPYING3. If not see
19; <http://www.gnu.org/licenses/>.
20
21HeaderInclude
22config/aarch64/aarch64-opts.h
23
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24HeaderInclude
25config/arm/aarch-common.h
26
361fb3ee 27TargetVariable
ae54c1b0 28enum aarch64_processor selected_tune = aarch64_none
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29
30TargetVariable
ae54c1b0 31enum aarch64_arch selected_arch = aarch64_no_arch
361fb3ee 32
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33TargetVariable
34aarch64_feature_flags aarch64_asm_isa_flags = 0
35
361fb3ee 36TargetVariable
fed55a60 37aarch64_feature_flags aarch64_isa_flags = 0
361fb3ee 38
30afdf34 39TargetVariable
d8dadbc9 40unsigned aarch_enable_bti = 2
30afdf34 41
ae54c1b0 42TargetVariable
b1d26458 43enum aarch_key_type aarch_ra_sign_key = AARCH_KEY_A
ae54c1b0 44
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45; The TLS dialect names to use with -mtls-dialect.
46
47Enum
48Name(tls_type) Type(enum aarch64_tls_type)
49The possible TLS dialects:
50
51EnumValue
52Enum(tls_type) String(trad) Value(TLS_TRADITIONAL)
53
54EnumValue
55Enum(tls_type) String(desc) Value(TLS_DESCRIPTORS)
56
57; The code model option names for -mcmodel.
58
59Enum
60Name(cmodel) Type(enum aarch64_code_model)
61The code model option names for -mcmodel:
62
63EnumValue
64Enum(cmodel) String(tiny) Value(AARCH64_CMODEL_TINY)
65
66EnumValue
67Enum(cmodel) String(small) Value(AARCH64_CMODEL_SMALL)
68
69EnumValue
70Enum(cmodel) String(large) Value(AARCH64_CMODEL_LARGE)
71
43e9d192 72mbig-endian
eece52b5 73Target RejectNegative Mask(BIG_END)
a7b2e184 74Assume target CPU is configured as big endian.
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75
76mgeneral-regs-only
eece52b5 77Target RejectNegative Mask(GENERAL_REGS_ONLY) Save
a7b2e184 78Generate code which uses only the general registers.
43e9d192 79
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80mharden-sls=
81Target RejectNegative Joined Var(aarch64_harden_sls_string)
82Generate code to mitigate against straight line speculation.
83
75cf1494 84mfix-cortex-a53-835769
eece52b5 85Target Var(aarch64_fix_a53_err835769) Init(2) Save
a7b2e184 86Workaround for ARM Cortex-A53 Erratum number 835769.
75cf1494 87
bf05ef76 88mfix-cortex-a53-843419
eece52b5 89Target Var(aarch64_fix_a53_err843419) Init(2) Save
a7b2e184 90Workaround for ARM Cortex-A53 Erratum number 843419.
bf05ef76 91
43e9d192 92mlittle-endian
eece52b5 93Target RejectNegative InverseMask(BIG_END)
a7b2e184 94Assume target CPU is configured as little endian.
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95
96mcmodel=
361fb3ee 97Target RejectNegative Joined Enum(cmodel) Var(aarch64_cmodel_var) Init(AARCH64_CMODEL_SMALL) Save
a7b2e184 98Specify the code model.
43e9d192 99
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100Enum
101Name(tp_reg) Type(enum aarch64_tp_reg)
102The register used to access the thread pointer:
103
104EnumValue
105Enum(tp_reg) String(el0) Value(AARCH64_TPIDR_EL0)
106
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107EnumValue
108Enum(tp_reg) String(tpidr_el0) Value(AARCH64_TPIDR_EL0)
109
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110EnumValue
111Enum(tp_reg) String(el1) Value(AARCH64_TPIDR_EL1)
112
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113EnumValue
114Enum(tp_reg) String(tpidr_el1) Value(AARCH64_TPIDR_EL1)
115
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116EnumValue
117Enum(tp_reg) String(el2) Value(AARCH64_TPIDR_EL2)
118
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119EnumValue
120Enum(tp_reg) String(tpidr_el2) Value(AARCH64_TPIDR_EL2)
121
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122EnumValue
123Enum(tp_reg) String(el3) Value(AARCH64_TPIDR_EL3)
124
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125EnumValue
126Enum(tp_reg) String(tpidr_el3) Value(AARCH64_TPIDR_EL3)
127
128EnumValue
129Enum(tp_reg) String(tpidrro_el0) Value(AARCH64_TPIDRRO_EL0)
130
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131mtp=
132Target RejectNegative Joined Enum(tp_reg) Var(aarch64_tpidr_reg) Init(AARCH64_TPIDR_EL0) Save
133Specify the thread pointer register.
134
43e9d192 135mstrict-align
eece52b5 136Target Mask(STRICT_ALIGN) Save
a7b2e184 137Don't assume that unaligned accesses are handled by the system.
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138
139momit-leaf-frame-pointer
eece52b5 140Target Var(flag_omit_leaf_frame_pointer) Init(2) Save
a7b2e184 141Omit the frame pointer in leaf functions.
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142
143mtls-dialect=
361fb3ee 144Target RejectNegative Joined Enum(tls_type) Var(aarch64_tls_dialect) Init(TLS_DESCRIPTORS) Save
a7b2e184 145Specify TLS dialect.
43e9d192 146
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147mtls-size=
148Target RejectNegative Joined Var(aarch64_tls_size) Enum(aarch64_tls_size)
149Specifies bit size of immediate TLS offsets. Valid values are 12, 24, 32, 48.
150
151Enum
152Name(aarch64_tls_size) Type(int)
153
154EnumValue
155Enum(aarch64_tls_size) String(12) Value(12)
156
157EnumValue
158Enum(aarch64_tls_size) String(24) Value(24)
159
160EnumValue
161Enum(aarch64_tls_size) String(32) Value(32)
162
163EnumValue
164Enum(aarch64_tls_size) String(48) Value(48)
165
43e9d192 166march=
6fdbe419 167Target RejectNegative Negative(march=) ToLower Joined Var(aarch64_arch_string)
266c2b54 168Use features of architecture ARCH.
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169
170mcpu=
6fdbe419 171Target RejectNegative Negative(mcpu=) ToLower Joined Var(aarch64_cpu_string)
266c2b54 172Use features of and optimize for CPU.
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173
174mtune=
6fdbe419 175Target RejectNegative Negative(mtune=) ToLower Joined Var(aarch64_tune_string)
266c2b54 176Optimize for CPU.
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177
178mabi=
179Target RejectNegative Joined Enum(aarch64_abi) Var(aarch64_abi) Init(AARCH64_ABI_DEFAULT)
266c2b54 180Generate code that conforms to the specified ABI.
17a819cb 181
8dec06f2 182moverride=
ae54c1b0 183Target RejectNegative ToLower Joined Var(aarch64_override_tune_string) Save
266c2b54 184-moverride=<string> Power users only! Override CPU optimization parameters.
8dec06f2 185
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186Enum
187Name(aarch64_abi) Type(int)
188Known AArch64 ABIs (for use with the -mabi= option):
189
190EnumValue
191Enum(aarch64_abi) String(ilp32) Value(AARCH64_ABI_ILP32)
192
193EnumValue
194Enum(aarch64_abi) String(lp64) Value(AARCH64_ABI_LP64)
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195
196mpc-relative-literal-loads
eece52b5 197Target Save Var(pcrelative_literal_loads) Init(2) Save
b4f50fd4 198PC relative literal loads.
a6fc00da 199
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200mbranch-protection=
201Target RejectNegative Joined Var(aarch64_branch_protection_string) Save
202Use branch-protection features.
203
db58fd89 204msign-return-address=
d8dadbc9 205Target WarnRemoved RejectNegative Joined Enum(aarch_ra_sign_scope_t) Var(aarch_ra_sign_scope) Init(AARCH_FUNCTION_NONE) Save
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206Select return address signing scope.
207
208Enum
d8dadbc9 209Name(aarch_ra_sign_scope_t) Type(enum aarch_function_type)
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210Supported AArch64 return address signing scope (for use with -msign-return-address= option):
211
212EnumValue
d8dadbc9 213Enum(aarch_ra_sign_scope_t) String(none) Value(AARCH_FUNCTION_NONE)
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214
215EnumValue
d8dadbc9 216Enum(aarch_ra_sign_scope_t) String(non-leaf) Value(AARCH_FUNCTION_NON_LEAF)
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217
218EnumValue
d8dadbc9 219Enum(aarch_ra_sign_scope_t) String(all) Value(AARCH_FUNCTION_ALL)
db58fd89 220
a6fc00da 221mlow-precision-recip-sqrt
88e25f47 222Target Var(flag_mrecip_low_precision_sqrt) Optimization
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223Enable the reciprocal square root approximation. Enabling this reduces
224precision of reciprocal square root results to about 16 bits for
225single precision and to 32 bits for double precision.
226
227mlow-precision-sqrt
88e25f47 228Target Var(flag_mlow_precision_sqrt) Optimization
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229Enable the square root approximation. Enabling this reduces
230precision of square root results to about 16 bits for
231single precision and to 32 bits for double precision.
232If enabled, it implies -mlow-precision-recip-sqrt.
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233
234mlow-precision-div
88e25f47 235Target Var(flag_mlow_precision_div) Optimization
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236Enable the division approximation. Enabling this reduces
237precision of division results to about 16 bits for
238single precision and to 32 bits for double precision.
c10e3d7f 239
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240Enum
241Name(early_ra_scope) Type(enum aarch64_early_ra_scope)
242
243EnumValue
244Enum(early_ra_scope) String(all) Value(AARCH64_EARLY_RA_ALL)
245
246EnumValue
247Enum(early_ra_scope) String(strided) Value(AARCH64_EARLY_RA_STRIDED)
248
249EnumValue
250Enum(early_ra_scope) String(none) Value(AARCH64_EARLY_RA_NONE)
251
252mearly-ra=
253Target RejectNegative Joined Enum(early_ra_scope) Var(aarch64_early_ra) Init(AARCH64_EARLY_RA_NONE) Save
254Specify when to enable an early register allocation pass. The possibilities
255are: all functions, functions that have access to strided multi-register
256instructions, and no functions.
257
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258Enum
259Name(sve_vector_bits) Type(enum aarch64_sve_vector_bits_enum)
260The possible SVE vector lengths:
261
262EnumValue
263Enum(sve_vector_bits) String(scalable) Value(SVE_SCALABLE)
264
265EnumValue
266Enum(sve_vector_bits) String(128) Value(SVE_128)
267
268EnumValue
269Enum(sve_vector_bits) String(256) Value(SVE_256)
270
271EnumValue
272Enum(sve_vector_bits) String(512) Value(SVE_512)
273
274EnumValue
275Enum(sve_vector_bits) String(1024) Value(SVE_1024)
276
277EnumValue
278Enum(sve_vector_bits) String(2048) Value(SVE_2048)
279
280msve-vector-bits=
281Target RejectNegative Joined Enum(sve_vector_bits) Var(aarch64_sve_vector_bits) Init(SVE_SCALABLE)
f499726a 282-msve-vector-bits=<number> Set the number of bits in an SVE vector register.
43cacb12 283
c10e3d7f 284mverbose-cost-dump
88e25f47 285Target Undocumented Var(flag_aarch64_verbose_cost)
d1132c1b 286Enables verbose cost model dumping in the debug dump files.
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287
288mtrack-speculation
289Target Var(aarch64_track_speculation)
290Generate code to track when the CPU might be speculating incorrectly.
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291
292mstack-protector-guard=
293Target RejectNegative Joined Enum(stack_protector_guard) Var(aarch64_stack_protector_guard) Init(SSP_GLOBAL)
294Use given stack-protector guard.
295
296Enum
297Name(stack_protector_guard) Type(enum stack_protector_guard)
298Valid arguments to -mstack-protector-guard=:
299
300EnumValue
301Enum(stack_protector_guard) String(sysreg) Value(SSP_SYSREG)
302
303EnumValue
304Enum(stack_protector_guard) String(global) Value(SSP_GLOBAL)
305
306mstack-protector-guard-reg=
307Target Joined RejectNegative String Var(aarch64_stack_protector_guard_reg_str)
308Use the system register specified on the command line as the stack protector
309guard register. This option is for use with fstack-protector-strong and
310not for use in user-land code.
311
312mstack-protector-guard-offset=
313Target Joined RejectNegative String Var(aarch64_stack_protector_guard_offset_str)
314Use an immediate to offset from the stack protector guard register, sp_el0.
315This option is for use with fstack-protector-strong and not for use in
316user-land code.
317
318TargetVariable
319long aarch64_stack_protector_guard_offset = 0
320
3950b229 321moutline-atomics
eece52b5 322Target Var(aarch64_flag_outline_atomics) Init(2) Save
3950b229 323Generate local calls to out-of-line atomic operations.
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324
325-param=aarch64-sve-compare-costs=
326Target Joined UInteger Var(aarch64_sve_compare_costs) Init(1) IntegerRange(0, 1) Param
327When vectorizing for SVE, consider using unpacked vectors for smaller elements and use the cost model to pick the cheapest approach. Also use the cost model to choose between SVE and Advanced SIMD vectorization.
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328
329-param=aarch64-float-recp-precision=
330Target Joined UInteger Var(aarch64_float_recp_precision) Init(1) IntegerRange(1, 5) Param
331The number of Newton iterations for calculating the reciprocal for float type. The precision of division is proportional to this param when division approximation is enabled. The default value is 1.
332
333-param=aarch64-double-recp-precision=
334Target Joined UInteger Var(aarch64_double_recp_precision) Init(2) IntegerRange(1, 5) Param
335The number of Newton iterations for calculating the reciprocal for double type. The precision of division is proportional to this param when division approximation is enabled. The default value is 2.
336
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337-param=aarch64-autovec-preference=
338Target Joined UInteger Var(aarch64_autovec_preference) Init(0) IntegerRange(0, 4) Param
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339
340-param=aarch64-loop-vect-issue-rate-niters=
341Target Joined UInteger Var(aarch64_loop_vect_issue_rate_niters) Init(6) IntegerRange(0, 65536) Param
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342
343-param=aarch64-mops-memcpy-size-threshold=
344Target Joined UInteger Var(aarch64_mops_memcpy_size_threshold) Init(256) Param
345Constant memcpy size in bytes above which to start using MOPS sequence.
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346
347-param=aarch64-mops-memmove-size-threshold=
bbdb72ba 348Target Joined UInteger Var(aarch64_mops_memmove_size_threshold) Init(256) Param
bb768f8b 349Constant memmove size in bytes above which to start using MOPS sequence.
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350
351-param=aarch64-mops-memset-size-threshold=
352Target Joined UInteger Var(aarch64_mops_memset_size_threshold) Init(256) Param
353Constant memset size in bytes from which to start using MOPS sequence.
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AV
354
355-param=aarch64-vect-unroll-limit=
356Target Joined UInteger Var(aarch64_vect_unroll_limit) Init(4) Param
357Limit how much the autovectorizer may unroll a loop.
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358
359-param=aarch64-ldp-policy=
574cec45 360Target Joined Var(aarch64_ldp_policy_param) Enum(aarch64_ldp_stp_policy) Init(AARCH64_LDP_STP_POLICY_DEFAULT) Param
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361--param=aarch64-ldp-policy=[default|always|never|aligned] Fine-grained policy for load pairs.
362
834fc2bf 363-param=aarch64-stp-policy=
574cec45 364Target Joined Var(aarch64_stp_policy_param) Enum(aarch64_ldp_stp_policy) Init(AARCH64_LDP_STP_POLICY_DEFAULT) Param
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365--param=aarch64-stp-policy=[default|always|never|aligned] Fine-grained policy for store pairs.
366
367Enum
574cec45 368Name(aarch64_ldp_stp_policy) Type(enum aarch64_ldp_stp_policy) UnknownError(unknown LDP/STP policy %qs)
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369
370EnumValue
574cec45 371Enum(aarch64_ldp_stp_policy) String(default) Value(AARCH64_LDP_STP_POLICY_DEFAULT)
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372
373EnumValue
574cec45 374Enum(aarch64_ldp_stp_policy) String(always) Value(AARCH64_LDP_STP_POLICY_ALWAYS)
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375
376EnumValue
574cec45 377Enum(aarch64_ldp_stp_policy) String(never) Value(AARCH64_LDP_STP_POLICY_NEVER)
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378
379EnumValue
574cec45 380Enum(aarch64_ldp_stp_policy) String(aligned) Value(AARCH64_LDP_STP_POLICY_ALIGNED)