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AArch64 - new pass to add conditional-branch speculation tracking
[thirdparty/gcc.git] / gcc / config / aarch64 / iterators.md
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43e9d192 1;; Machine description for AArch64 architecture.
85ec4feb 2;; Copyright (C) 2009-2018 Free Software Foundation, Inc.
43e9d192
IB		 3;; Contributed by ARM Ltd.
4;;
5;; This file is part of GCC.
6;;
7;; GCC is free software; you can redistribute it and/or modify it
8;; under the terms of the GNU General Public License as published by
9;; the Free Software Foundation; either version 3, or (at your option)
10;; any later version.
11;;
12;; GCC is distributed in the hope that it will be useful, but
13;; WITHOUT ANY WARRANTY; without even the implied warranty of
14;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15;; General Public License for more details.
16;;
17;; You should have received a copy of the GNU General Public License
18;; along with GCC; see the file COPYING3. If not see
19;; <http://www.gnu.org/licenses/>.
20
21;; -------------------------------------------------------------------
22;; Mode Iterators
23;; -------------------------------------------------------------------
24
25
26;; Iterator for General Purpose Integer registers (32- and 64-bit modes)
27(define_mode_iterator GPI [SI DI])
28
d7f33f07
JW		 29;; Iterator for HI, SI, DI, some instructions can only work on these modes.
30(define_mode_iterator GPI_I16 [(HI "AARCH64_ISA_F16") SI DI])
31
43e9d192
IB		 32;; Iterator for QI and HI modes
33(define_mode_iterator SHORT [QI HI])
34
35;; Iterator for all integer modes (up to 64-bit)
36(define_mode_iterator ALLI [QI HI SI DI])
37
43e9d192
IB		 38;; Iterator for all integer modes that can be extended (up to 64-bit)
39(define_mode_iterator ALLX [QI HI SI])
40
41;; Iterator for General Purpose Floating-point registers (32- and 64-bit modes)
42(define_mode_iterator GPF [SF DF])
43
d7f33f07
JW		 44;; Iterator for all scalar floating point modes (HF, SF, DF)
45(define_mode_iterator GPF_F16 [(HF "AARCH64_ISA_F16") SF DF])
46
90e6443f
TC		 47;; Iterator for all scalar floating point modes (HF, SF, DF)
48(define_mode_iterator GPF_HF [HF SF DF])
49
09fcd8e1
RR		 50;; Iterator for all scalar floating point modes (HF, SF, DF and TF)
51(define_mode_iterator GPF_TF_F16 [HF SF DF TF])
c2ec330c 52
922f9c25
AL		 53;; Double vector modes.
54(define_mode_iterator VDF [V2SF V4HF])
55
b4f50fd4
RR		 56;; Iterator for all scalar floating point modes (SF, DF and TF)
57(define_mode_iterator GPF_TF [SF DF TF])
58
43cacb12 59;; Integer Advanced SIMD modes.
43e9d192
IB		 60(define_mode_iterator VDQ_I [V8QI V16QI V4HI V8HI V2SI V4SI V2DI])
61
43cacb12 62;; Advanced SIMD and scalar, 64 & 128-bit container, all integer modes.
43e9d192
IB		 63(define_mode_iterator VSDQ_I [V8QI V16QI V4HI V8HI V2SI V4SI V2DI QI HI SI DI])
64
43cacb12
RS		 65;; Advanced SIMD and scalar, 64 & 128-bit container: all Advanced SIMD
66;; integer modes; 64-bit scalar integer mode.
43e9d192
IB		 67(define_mode_iterator VSDQ_I_DI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI DI])
68
69;; Double vector modes.
71a11456 70(define_mode_iterator VD [V8QI V4HI V4HF V2SI V2SF])
43e9d192 71
dfe1da23
JW		 72;; All modes stored in registers d0-d31.
73(define_mode_iterator DREG [V8QI V4HI V4HF V2SI V2SF DF])
74
75;; Copy of the above.
76(define_mode_iterator DREG2 [V8QI V4HI V4HF V2SI V2SF DF])
77
43cacb12 78;; Advanced SIMD, 64-bit container, all integer modes.
43e9d192
IB		 79(define_mode_iterator VD_BHSI [V8QI V4HI V2SI])
80
81;; 128 and 64-bit container; 8, 16, 32-bit vector integer modes
82(define_mode_iterator VDQ_BHSI [V8QI V16QI V4HI V8HI V2SI V4SI])
83
84;; Quad vector modes.
71a11456 85(define_mode_iterator VQ [V16QI V8HI V4SI V2DI V8HF V4SF V2DF])
43e9d192 86
9f5361c8
KT		 87;; Copy of the above.
88(define_mode_iterator VQ2 [V16QI V8HI V4SI V2DI V8HF V4SF V2DF])
89
d21052eb
TC		 90;; Quad integer vector modes.
91(define_mode_iterator VQ_I [V16QI V8HI V4SI V2DI])
92
51437269 93;; VQ without 2 element modes.
71a11456 94(define_mode_iterator VQ_NO2E [V16QI V8HI V4SI V8HF V4SF])
51437269
GW		 95
96;; Quad vector with only 2 element modes.
97(define_mode_iterator VQ_2E [V2DI V2DF])
98
28514dda
YZ		 99;; This mode iterator allows :P to be used for patterns that operate on
100;; addresses in different modes. In LP64, only DI will match, while in
101;; ILP32, either can match.
102(define_mode_iterator P [(SI "ptr_mode == SImode || Pmode == SImode")
103 (DI "ptr_mode == DImode || Pmode == DImode")])
104
43e9d192
IB		 105;; This mode iterator allows :PTR to be used for patterns that operate on
106;; pointer-sized quantities. Exactly one of the two alternatives will match.
28514dda 107(define_mode_iterator PTR [(SI "ptr_mode == SImode") (DI "ptr_mode == DImode")])
43e9d192 108
43cacb12 109;; Advanced SIMD Float modes suitable for moving, loading and storing.
862abc04
AL		 110(define_mode_iterator VDQF_F16 [V4HF V8HF V2SF V4SF V2DF])
111
43cacb12 112;; Advanced SIMD Float modes.
43e9d192 113(define_mode_iterator VDQF [V2SF V4SF V2DF])
daef0a8c
JW		 114(define_mode_iterator VHSDF [(V4HF "TARGET_SIMD_F16INST")
115 (V8HF "TARGET_SIMD_F16INST")
116 V2SF V4SF V2DF])
43e9d192 117
43cacb12 118;; Advanced SIMD Float modes, and DF.
daef0a8c
JW		 119(define_mode_iterator VHSDF_DF [(V4HF "TARGET_SIMD_F16INST")
120 (V8HF "TARGET_SIMD_F16INST")
121 V2SF V4SF V2DF DF])
d7f33f07
JW		 122(define_mode_iterator VHSDF_HSDF [(V4HF "TARGET_SIMD_F16INST")
123 (V8HF "TARGET_SIMD_F16INST")
124 V2SF V4SF V2DF
125 (HF "TARGET_SIMD_F16INST")
126 SF DF])
f421c516 127
43cacb12 128;; Advanced SIMD single Float modes.
828e70c1
JG		 129(define_mode_iterator VDQSF [V2SF V4SF])
130
03873eb9
AL		 131;; Quad vector Float modes with half/single elements.
132(define_mode_iterator VQ_HSF [V8HF V4SF])
133
fc21784d
JG		 134;; Modes suitable to use as the return type of a vcond expression.
135(define_mode_iterator VDQF_COND [V2SF V2SI V4SF V4SI V2DF V2DI])
136
43cacb12 137;; All scalar and Advanced SIMD Float modes.
889b9412
JG		 138(define_mode_iterator VALLF [V2SF V4SF V2DF SF DF])
139
43cacb12 140;; Advanced SIMD Float modes with 2 elements.
43e9d192
IB		 141(define_mode_iterator V2F [V2SF V2DF])
142
43cacb12 143;; All Advanced SIMD modes on which we support any arithmetic operations.
43e9d192
IB		 144(define_mode_iterator VALL [V8QI V16QI V4HI V8HI V2SI V4SI V2DI V2SF V4SF V2DF])
145
43cacb12 146;; All Advanced SIMD modes suitable for moving, loading, and storing.
71a11456
AL		 147(define_mode_iterator VALL_F16 [V8QI V16QI V4HI V8HI V2SI V4SI V2DI
148 V4HF V8HF V2SF V4SF V2DF])
149
88119b46
KT		 150;; The VALL_F16 modes except the 128-bit 2-element ones.
151(define_mode_iterator VALL_F16_NO_V2Q [V8QI V16QI V4HI V8HI V2SI V4SI
152 V4HF V8HF V2SF V4SF])
153
43cacb12 154;; All Advanced SIMD modes barring HF modes, plus DI.
a50344cb
TB		 155(define_mode_iterator VALLDI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI V2SF V4SF V2DF DI])
156
43cacb12 157;; All Advanced SIMD modes and DI.
71a11456
AL		 158(define_mode_iterator VALLDI_F16 [V8QI V16QI V4HI V8HI V2SI V4SI V2DI
159 V4HF V8HF V2SF V4SF V2DF DI])
160
43cacb12 161;; All Advanced SIMD modes, plus DI and DF.
46e778c4 162(define_mode_iterator VALLDIF [V8QI V16QI V4HI V8HI V2SI V4SI
7c369485 163 V2DI V4HF V8HF V2SF V4SF V2DF DI DF])
46e778c4 164
43cacb12 165;; Advanced SIMD modes for Integer reduction across lanes.
92835317
TB		 166(define_mode_iterator VDQV [V8QI V16QI V4HI V8HI V4SI V2DI])
167
43cacb12 168;; Advanced SIMD modes (except V2DI) for Integer reduction across lanes.
92835317 169(define_mode_iterator VDQV_S [V8QI V16QI V4HI V8HI V4SI])
43e9d192
IB		 170
171;; All double integer narrow-able modes.
172(define_mode_iterator VDN [V4HI V2SI DI])
173
174;; All quad integer narrow-able modes.
175(define_mode_iterator VQN [V8HI V4SI V2DI])
176
43cacb12
RS		 177;; Advanced SIMD and scalar 128-bit container: narrowable 16, 32, 64-bit
178;; integer modes
43e9d192
IB		 179(define_mode_iterator VSQN_HSDI [V8HI V4SI V2DI HI SI DI])
180
181;; All quad integer widen-able modes.
182(define_mode_iterator VQW [V16QI V8HI V4SI])
183
184;; Double vector modes for combines.
7c369485 185(define_mode_iterator VDC [V8QI V4HI V4HF V2SI V2SF DI DF])
43e9d192 186
43cacb12 187;; Advanced SIMD modes except double int.
43e9d192 188(define_mode_iterator VDQIF [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF V2DF])
703bbcdf
JW		 189(define_mode_iterator VDQIF_F16 [V8QI V16QI V4HI V8HI V2SI V4SI
190 V4HF V8HF V2SF V4SF V2DF])
43e9d192 191
43cacb12 192;; Advanced SIMD modes for S type.
58a3bd25
FY		 193(define_mode_iterator VDQ_SI [V2SI V4SI])
194
43cacb12 195;; Advanced SIMD modes for S and D.
2644d4d9
JW		 196(define_mode_iterator VDQ_SDI [V2SI V4SI V2DI])
197
43cacb12 198;; Advanced SIMD modes for H, S and D.
33d72b63
JW		 199(define_mode_iterator VDQ_HSDI [(V4HI "TARGET_SIMD_F16INST")
200 (V8HI "TARGET_SIMD_F16INST")
201 V2SI V4SI V2DI])
202
43cacb12 203;; Scalar and Advanced SIMD modes for S and D.
2644d4d9
JW		 204(define_mode_iterator VSDQ_SDI [V2SI V4SI V2DI SI DI])
205
43cacb12 206;; Scalar and Advanced SIMD modes for S and D, Advanced SIMD modes for H.
33d72b63
JW		 207(define_mode_iterator VSDQ_HSDI [(V4HI "TARGET_SIMD_F16INST")
208 (V8HI "TARGET_SIMD_F16INST")
68ad28c3
JW		 209 V2SI V4SI V2DI
210 (HI "TARGET_SIMD_F16INST")
211 SI DI])
33d72b63 212
43cacb12 213;; Advanced SIMD modes for Q and H types.
66adb8eb
JG		 214(define_mode_iterator VDQQH [V8QI V16QI V4HI V8HI])
215
43cacb12 216;; Advanced SIMD modes for H and S types.
43e9d192
IB		 217(define_mode_iterator VDQHS [V4HI V8HI V2SI V4SI])
218
43cacb12 219;; Advanced SIMD modes for H, S and D types.
c7f28cd5
KT		 220(define_mode_iterator VDQHSD [V4HI V8HI V2SI V4SI V2DI])
221
43cacb12 222;; Advanced SIMD and scalar integer modes for H and S.
43e9d192
IB		 223(define_mode_iterator VSDQ_HSI [V4HI V8HI V2SI V4SI HI SI])
224
43cacb12 225;; Advanced SIMD and scalar 64-bit container: 16, 32-bit integer modes.
43e9d192
IB		 226(define_mode_iterator VSD_HSI [V4HI V2SI HI SI])
227
43cacb12 228;; Advanced SIMD 64-bit container: 16, 32-bit integer modes.
43e9d192
IB		 229(define_mode_iterator VD_HSI [V4HI V2SI])
230
231;; Scalar 64-bit container: 16, 32-bit integer modes
232(define_mode_iterator SD_HSI [HI SI])
233
43cacb12 234;; Advanced SIMD 64-bit container: 16, 32-bit integer modes.
43e9d192
IB		 235(define_mode_iterator VQ_HSI [V8HI V4SI])
236
237;; All byte modes.
238(define_mode_iterator VB [V8QI V16QI])
239
5e32e83b
JW		 240;; 2 and 4 lane SI modes.
241(define_mode_iterator VS [V2SI V4SI])
242
43e9d192
IB		 243(define_mode_iterator TX [TI TF])
244
43cacb12 245;; Advanced SIMD opaque structure modes.
43e9d192
IB		 246(define_mode_iterator VSTRUCT [OI CI XI])
247
248;; Double scalar modes
249(define_mode_iterator DX [DI DF])
250
dfe1da23
JW		 251;; Duplicate of the above
252(define_mode_iterator DX2 [DI DF])
253
254;; Single scalar modes
255(define_mode_iterator SX [SI SF])
256
257;; Duplicate of the above
258(define_mode_iterator SX2 [SI SF])
259
260;; Single and double integer and float modes
261(define_mode_iterator DSX [DF DI SF SI])
262
263
43cacb12 264;; Modes available for Advanced SIMD <f>mul lane operations.
ab2e8f01
JW		 265(define_mode_iterator VMUL [V4HI V8HI V2SI V4SI
266 (V4HF "TARGET_SIMD_F16INST")
267 (V8HF "TARGET_SIMD_F16INST")
268 V2SF V4SF V2DF])
779aea46 269
43cacb12
RS		 270;; Modes available for Advanced SIMD <f>mul lane operations changing lane
271;; count.
779aea46
JG		 272(define_mode_iterator VMUL_CHANGE_NLANES [V4HI V8HI V2SI V4SI V2SF V4SF])
273
43cacb12
RS		 274;; All SVE vector modes.
275(define_mode_iterator SVE_ALL [VNx16QI VNx8HI VNx4SI VNx2DI
276 VNx8HF VNx4SF VNx2DF])
277
9f4cbab8
RS		 278;; All SVE vector structure modes.
279(define_mode_iterator SVE_STRUCT [VNx32QI VNx16HI VNx8SI VNx4DI
280 VNx16HF VNx8SF VNx4DF
281 VNx48QI VNx24HI VNx12SI VNx6DI
282 VNx24HF VNx12SF VNx6DF
283 VNx64QI VNx32HI VNx16SI VNx8DI
284 VNx32HF VNx16SF VNx8DF])
285
43cacb12
RS		 286;; All SVE vector modes that have 8-bit or 16-bit elements.
287(define_mode_iterator SVE_BH [VNx16QI VNx8HI VNx8HF])
288
289;; All SVE vector modes that have 8-bit, 16-bit or 32-bit elements.
290(define_mode_iterator SVE_BHS [VNx16QI VNx8HI VNx4SI VNx8HF VNx4SF])
291
292;; All SVE integer vector modes that have 8-bit, 16-bit or 32-bit elements.
293(define_mode_iterator SVE_BHSI [VNx16QI VNx8HI VNx4SI])
294
295;; All SVE integer vector modes that have 16-bit, 32-bit or 64-bit elements.
296(define_mode_iterator SVE_HSDI [VNx16QI VNx8HI VNx4SI])
297
298;; All SVE floating-point vector modes that have 16-bit or 32-bit elements.
299(define_mode_iterator SVE_HSF [VNx8HF VNx4SF])
300
301;; All SVE vector modes that have 32-bit or 64-bit elements.
302(define_mode_iterator SVE_SD [VNx4SI VNx2DI VNx4SF VNx2DF])
303
bfaa08b7
RS		 304;; All SVE vector modes that have 32-bit elements.
305(define_mode_iterator SVE_S [VNx4SI VNx4SF])
306
307;; All SVE vector modes that have 64-bit elements.
308(define_mode_iterator SVE_D [VNx2DI VNx2DF])
309
43cacb12
RS		 310;; All SVE integer vector modes that have 32-bit or 64-bit elements.
311(define_mode_iterator SVE_SDI [VNx4SI VNx2DI])
312
313;; All SVE integer vector modes.
314(define_mode_iterator SVE_I [VNx16QI VNx8HI VNx4SI VNx2DI])
315
316;; All SVE floating-point vector modes.
317(define_mode_iterator SVE_F [VNx8HF VNx4SF VNx2DF])
318
319;; All SVE predicate modes.
320(define_mode_iterator PRED_ALL [VNx16BI VNx8BI VNx4BI VNx2BI])
321
322;; SVE predicate modes that control 8-bit, 16-bit or 32-bit elements.
323(define_mode_iterator PRED_BHS [VNx16BI VNx8BI VNx4BI])
324
43e9d192
IB		 325;; ------------------------------------------------------------------
326;; Unspec enumerations for Advance SIMD. These could well go into
327;; aarch64.md but for their use in int_iterators here.
328;; ------------------------------------------------------------------
329
330(define_c_enum "unspec"
331 [
332 UNSPEC_ASHIFT_SIGNED ; Used in aarch-simd.md.
333 UNSPEC_ASHIFT_UNSIGNED ; Used in aarch64-simd.md.
285398d2 334 UNSPEC_ABS ; Used in aarch64-simd.md.
998eaf97
JG		 335 UNSPEC_FMAX ; Used in aarch64-simd.md.
336 UNSPEC_FMAXNMV ; Used in aarch64-simd.md.
43e9d192 337 UNSPEC_FMAXV ; Used in aarch64-simd.md.
998eaf97
JG		 338 UNSPEC_FMIN ; Used in aarch64-simd.md.
339 UNSPEC_FMINNMV ; Used in aarch64-simd.md.
43e9d192
IB		 340 UNSPEC_FMINV ; Used in aarch64-simd.md.
341 UNSPEC_FADDV ; Used in aarch64-simd.md.
f5156c3e 342 UNSPEC_ADDV ; Used in aarch64-simd.md.
43e9d192
IB		 343 UNSPEC_SMAXV ; Used in aarch64-simd.md.
344 UNSPEC_SMINV ; Used in aarch64-simd.md.
345 UNSPEC_UMAXV ; Used in aarch64-simd.md.
346 UNSPEC_UMINV ; Used in aarch64-simd.md.
347 UNSPEC_SHADD ; Used in aarch64-simd.md.
348 UNSPEC_UHADD ; Used in aarch64-simd.md.
349 UNSPEC_SRHADD ; Used in aarch64-simd.md.
350 UNSPEC_URHADD ; Used in aarch64-simd.md.
351 UNSPEC_SHSUB ; Used in aarch64-simd.md.
352 UNSPEC_UHSUB ; Used in aarch64-simd.md.
353 UNSPEC_SRHSUB ; Used in aarch64-simd.md.
354 UNSPEC_URHSUB ; Used in aarch64-simd.md.
355 UNSPEC_ADDHN ; Used in aarch64-simd.md.
356 UNSPEC_RADDHN ; Used in aarch64-simd.md.
357 UNSPEC_SUBHN ; Used in aarch64-simd.md.
358 UNSPEC_RSUBHN ; Used in aarch64-simd.md.
359 UNSPEC_ADDHN2 ; Used in aarch64-simd.md.
360 UNSPEC_RADDHN2 ; Used in aarch64-simd.md.
361 UNSPEC_SUBHN2 ; Used in aarch64-simd.md.
362 UNSPEC_RSUBHN2 ; Used in aarch64-simd.md.
363 UNSPEC_SQDMULH ; Used in aarch64-simd.md.
364 UNSPEC_SQRDMULH ; Used in aarch64-simd.md.
365 UNSPEC_PMUL ; Used in aarch64-simd.md.
496ea87d 366 UNSPEC_FMULX ; Used in aarch64-simd.md.
43e9d192
IB		 367 UNSPEC_USQADD ; Used in aarch64-simd.md.
368 UNSPEC_SUQADD ; Used in aarch64-simd.md.
369 UNSPEC_SQXTUN ; Used in aarch64-simd.md.
370 UNSPEC_SQXTN ; Used in aarch64-simd.md.
371 UNSPEC_UQXTN ; Used in aarch64-simd.md.
372 UNSPEC_SSRA ; Used in aarch64-simd.md.
373 UNSPEC_USRA ; Used in aarch64-simd.md.
374 UNSPEC_SRSRA ; Used in aarch64-simd.md.
375 UNSPEC_URSRA ; Used in aarch64-simd.md.
376 UNSPEC_SRSHR ; Used in aarch64-simd.md.
377 UNSPEC_URSHR ; Used in aarch64-simd.md.
378 UNSPEC_SQSHLU ; Used in aarch64-simd.md.
379 UNSPEC_SQSHL ; Used in aarch64-simd.md.
380 UNSPEC_UQSHL ; Used in aarch64-simd.md.
381 UNSPEC_SQSHRUN ; Used in aarch64-simd.md.
382 UNSPEC_SQRSHRUN ; Used in aarch64-simd.md.
383 UNSPEC_SQSHRN ; Used in aarch64-simd.md.
384 UNSPEC_UQSHRN ; Used in aarch64-simd.md.
385 UNSPEC_SQRSHRN ; Used in aarch64-simd.md.
386 UNSPEC_UQRSHRN ; Used in aarch64-simd.md.
387 UNSPEC_SSHL ; Used in aarch64-simd.md.
388 UNSPEC_USHL ; Used in aarch64-simd.md.
389 UNSPEC_SRSHL ; Used in aarch64-simd.md.
390 UNSPEC_URSHL ; Used in aarch64-simd.md.
391 UNSPEC_SQRSHL ; Used in aarch64-simd.md.
392 UNSPEC_UQRSHL ; Used in aarch64-simd.md.
43e9d192
IB		 393 UNSPEC_SSLI ; Used in aarch64-simd.md.
394 UNSPEC_USLI ; Used in aarch64-simd.md.
395 UNSPEC_SSRI ; Used in aarch64-simd.md.
396 UNSPEC_USRI ; Used in aarch64-simd.md.
397 UNSPEC_SSHLL ; Used in aarch64-simd.md.
398 UNSPEC_USHLL ; Used in aarch64-simd.md.
399 UNSPEC_ADDP ; Used in aarch64-simd.md.
88b08073 400 UNSPEC_TBL ; Used in vector permute patterns.
9371aecc 401 UNSPEC_TBX ; Used in vector permute patterns.
88b08073 402 UNSPEC_CONCAT ; Used in vector permute patterns.
3f8334a5
RS		 403
404 ;; The following permute unspecs are generated directly by
405 ;; aarch64_expand_vec_perm_const, so any changes to the underlying
406 ;; instructions would need a corresponding change there.
cc4d934f
JG		 407 UNSPEC_ZIP1 ; Used in vector permute patterns.
408 UNSPEC_ZIP2 ; Used in vector permute patterns.
409 UNSPEC_UZP1 ; Used in vector permute patterns.
410 UNSPEC_UZP2 ; Used in vector permute patterns.
411 UNSPEC_TRN1 ; Used in vector permute patterns.
412 UNSPEC_TRN2 ; Used in vector permute patterns.
3f8334a5 413 UNSPEC_EXT ; Used in vector permute patterns.
923fcec3
AL		 414 UNSPEC_REV64 ; Used in vector reverse patterns (permute).
415 UNSPEC_REV32 ; Used in vector reverse patterns (permute).
416 UNSPEC_REV16 ; Used in vector reverse patterns (permute).
3f8334a5 417
5a7a4e80
TB		 418 UNSPEC_AESE ; Used in aarch64-simd.md.
419 UNSPEC_AESD ; Used in aarch64-simd.md.
420 UNSPEC_AESMC ; Used in aarch64-simd.md.
421 UNSPEC_AESIMC ; Used in aarch64-simd.md.
30442682
TB		 422 UNSPEC_SHA1C ; Used in aarch64-simd.md.
423 UNSPEC_SHA1M ; Used in aarch64-simd.md.
424 UNSPEC_SHA1P ; Used in aarch64-simd.md.
425 UNSPEC_SHA1H ; Used in aarch64-simd.md.
426 UNSPEC_SHA1SU0 ; Used in aarch64-simd.md.
427 UNSPEC_SHA1SU1 ; Used in aarch64-simd.md.
b9cb0a44
TB		 428 UNSPEC_SHA256H ; Used in aarch64-simd.md.
429 UNSPEC_SHA256H2 ; Used in aarch64-simd.md.
430 UNSPEC_SHA256SU0 ; Used in aarch64-simd.md.
431 UNSPEC_SHA256SU1 ; Used in aarch64-simd.md.
7baa225d
TB		 432 UNSPEC_PMULL ; Used in aarch64-simd.md.
433 UNSPEC_PMULL2 ; Used in aarch64-simd.md.
668046d1 434 UNSPEC_REV_REGLIST ; Used in aarch64-simd.md.
9c004c58 435 UNSPEC_VEC_SHR ; Used in aarch64-simd.md.
57b26d65
MW		 436 UNSPEC_SQRDMLAH ; Used in aarch64-simd.md.
437 UNSPEC_SQRDMLSH ; Used in aarch64-simd.md.
202d0c11
DS		 438 UNSPEC_FMAXNM ; Used in aarch64-simd.md.
439 UNSPEC_FMINNM ; Used in aarch64-simd.md.
7a08d813
TC		 440 UNSPEC_SDOT ; Used in aarch64-simd.md.
441 UNSPEC_UDOT ; Used in aarch64-simd.md.
27086ea3
MC		 442 UNSPEC_SM3SS1 ; Used in aarch64-simd.md.
443 UNSPEC_SM3TT1A ; Used in aarch64-simd.md.
444 UNSPEC_SM3TT1B ; Used in aarch64-simd.md.
445 UNSPEC_SM3TT2A ; Used in aarch64-simd.md.
446 UNSPEC_SM3TT2B ; Used in aarch64-simd.md.
447 UNSPEC_SM3PARTW1 ; Used in aarch64-simd.md.
448 UNSPEC_SM3PARTW2 ; Used in aarch64-simd.md.
449 UNSPEC_SM4E ; Used in aarch64-simd.md.
450 UNSPEC_SM4EKEY ; Used in aarch64-simd.md.
451 UNSPEC_SHA512H ; Used in aarch64-simd.md.
452 UNSPEC_SHA512H2 ; Used in aarch64-simd.md.
453 UNSPEC_SHA512SU0 ; Used in aarch64-simd.md.
454 UNSPEC_SHA512SU1 ; Used in aarch64-simd.md.
455 UNSPEC_FMLAL ; Used in aarch64-simd.md.
456 UNSPEC_FMLSL ; Used in aarch64-simd.md.
457 UNSPEC_FMLAL2 ; Used in aarch64-simd.md.
458 UNSPEC_FMLSL2 ; Used in aarch64-simd.md.
43cacb12 459 UNSPEC_SEL ; Used in aarch64-sve.md.
898f07b0
RS		 460 UNSPEC_ANDV ; Used in aarch64-sve.md.
461 UNSPEC_IORV ; Used in aarch64-sve.md.
462 UNSPEC_XORV ; Used in aarch64-sve.md.
43cacb12
RS		 463 UNSPEC_ANDF ; Used in aarch64-sve.md.
464 UNSPEC_IORF ; Used in aarch64-sve.md.
465 UNSPEC_XORF ; Used in aarch64-sve.md.
11e9443f
RS		 466 UNSPEC_SMUL_HIGHPART ; Used in aarch64-sve.md.
467 UNSPEC_UMUL_HIGHPART ; Used in aarch64-sve.md.
0972596e
RS		 468 UNSPEC_COND_ADD ; Used in aarch64-sve.md.
469 UNSPEC_COND_SUB ; Used in aarch64-sve.md.
6c4fd4a9
RS		 470 UNSPEC_COND_MUL ; Used in aarch64-sve.md.
471 UNSPEC_COND_DIV ; Used in aarch64-sve.md.
0d2b3bca
RS		 472 UNSPEC_COND_MAX ; Used in aarch64-sve.md.
473 UNSPEC_COND_MIN ; Used in aarch64-sve.md.
b41d1f6e
RS		 474 UNSPEC_COND_FMLA ; Used in aarch64-sve.md.
475 UNSPEC_COND_FMLS ; Used in aarch64-sve.md.
476 UNSPEC_COND_FNMLA ; Used in aarch64-sve.md.
477 UNSPEC_COND_FNMLS ; Used in aarch64-sve.md.
43cacb12
RS		 478 UNSPEC_COND_LT ; Used in aarch64-sve.md.
479 UNSPEC_COND_LE ; Used in aarch64-sve.md.
480 UNSPEC_COND_EQ ; Used in aarch64-sve.md.
481 UNSPEC_COND_NE ; Used in aarch64-sve.md.
482 UNSPEC_COND_GE ; Used in aarch64-sve.md.
483 UNSPEC_COND_GT ; Used in aarch64-sve.md.
43cacb12 484 UNSPEC_LASTB ; Used in aarch64-sve.md.
43e9d192
IB		 485])
486
d81cb613
MW		 487;; ------------------------------------------------------------------
488;; Unspec enumerations for Atomics. They are here so that they can be
489;; used in the int_iterators for atomic operations.
490;; ------------------------------------------------------------------
491
492(define_c_enum "unspecv"
493 [
494 UNSPECV_LX ; Represent a load-exclusive.
495 UNSPECV_SX ; Represent a store-exclusive.
496 UNSPECV_LDA ; Represent an atomic load or load-acquire.
497 UNSPECV_STL ; Represent an atomic store or store-release.
498 UNSPECV_ATOMIC_CMPSW ; Represent an atomic compare swap.
499 UNSPECV_ATOMIC_EXCHG ; Represent an atomic exchange.
500 UNSPECV_ATOMIC_CAS ; Represent an atomic CAS.
501 UNSPECV_ATOMIC_SWP ; Represent an atomic SWP.
502 UNSPECV_ATOMIC_OP ; Represent an atomic operation.
503 UNSPECV_ATOMIC_LDOP ; Represent an atomic load-operation
504 UNSPECV_ATOMIC_LDOP_OR ; Represent an atomic load-or
505 UNSPECV_ATOMIC_LDOP_BIC ; Represent an atomic load-bic
506 UNSPECV_ATOMIC_LDOP_XOR ; Represent an atomic load-xor
507 UNSPECV_ATOMIC_LDOP_PLUS ; Represent an atomic load-add
508])
509
43e9d192
IB		 510;; -------------------------------------------------------------------
511;; Mode attributes
512;; -------------------------------------------------------------------
513
514;; In GPI templates, a string like "%<w>0" will expand to "%w0" in the
515;; 32-bit version and "%x0" in the 64-bit version.
516(define_mode_attr w [(QI "w") (HI "w") (SI "w") (DI "x") (SF "s") (DF "d")])
517
db46a2e6
JG		 518;; The size of access, in bytes.
519(define_mode_attr ldst_sz [(SI "4") (DI "8")])
520;; Likewise for load/store pair.
521(define_mode_attr ldpstp_sz [(SI "8") (DI "16")])
522
0d35c5c2 523;; For inequal width int to float conversion
d7f33f07
JW		 524(define_mode_attr w1 [(HF "w") (SF "w") (DF "x")])
525(define_mode_attr w2 [(HF "x") (SF "x") (DF "w")])
0d35c5c2 526
22be0d08
MC		 527;; For width of fp registers in fcvt instruction
528(define_mode_attr fpw [(DI "s") (SI "d")])
529
2b8568fe
KT		 530(define_mode_attr short_mask [(HI "65535") (QI "255")])
531
051d0e2f
SN		 532;; For constraints used in scalar immediate vector moves
533(define_mode_attr hq [(HI "h") (QI "q")])
534
ef22810a
RH		 535;; For doubling width of an integer mode
536(define_mode_attr DWI [(QI "HI") (HI "SI") (SI "DI") (DI "TI")])
537
22be0d08
MC		 538(define_mode_attr fcvt_change_mode [(SI "df") (DI "sf")])
539
540(define_mode_attr FCVT_CHANGE_MODE [(SI "DF") (DI "SF")])
541
43e9d192
IB		 542;; For scalar usage of vector/FP registers
543(define_mode_attr v [(QI "b") (HI "h") (SI "s") (DI "d")
d7f33f07 544 (HF "h") (SF "s") (DF "d")
43e9d192
IB		 545 (V8QI "") (V16QI "")
546 (V4HI "") (V8HI "")
547 (V2SI "") (V4SI "")
548 (V2DI "") (V2SF "")
daef0a8c
JW		 549 (V4SF "") (V4HF "")
550 (V8HF "") (V2DF "")])
43e9d192
IB		 551
552;; For scalar usage of vector/FP registers, narrowing
553(define_mode_attr vn2 [(QI "") (HI "b") (SI "h") (DI "s")
554 (V8QI "") (V16QI "")
555 (V4HI "") (V8HI "")
556 (V2SI "") (V4SI "")
557 (V2DI "") (V2SF "")
558 (V4SF "") (V2DF "")])
559
560;; For scalar usage of vector/FP registers, widening
561(define_mode_attr vw2 [(DI "") (QI "h") (HI "s") (SI "d")
562 (V8QI "") (V16QI "")
563 (V4HI "") (V8HI "")
564 (V2SI "") (V4SI "")
565 (V2DI "") (V2SF "")
566 (V4SF "") (V2DF "")])
567
89fdc743
IB		 568;; Register Type Name and Vector Arrangement Specifier for when
569;; we are doing scalar for DI and SIMD for SI (ignoring all but
570;; lane 0).
571(define_mode_attr rtn [(DI "d") (SI "")])
572(define_mode_attr vas [(DI "") (SI ".2s")])
573
7ac29c0f
RS		 574;; Map a vector to the number of units in it, if the size of the mode
575;; is constant.
576(define_mode_attr nunits [(V8QI "8") (V16QI "16")
577 (V4HI "4") (V8HI "8")
578 (V2SI "2") (V4SI "4")
579 (V2DI "2")
580 (V4HF "4") (V8HF "8")
581 (V2SF "2") (V4SF "4")
582 (V1DF "1") (V2DF "2")
583 (DI "1") (DF "1")])
584
b187677b
RS		 585;; Map a mode to the number of bits in it, if the size of the mode
586;; is constant.
587(define_mode_attr bitsize [(V8QI "64") (V16QI "128")
588 (V4HI "64") (V8HI "128")
589 (V2SI "64") (V4SI "128")
590 (V2DI "128")])
591
22be0d08
MC		 592;; Map a floating point or integer mode to the appropriate register name prefix
593(define_mode_attr s [(HF "h") (SF "s") (DF "d") (SI "s") (DI "d")])
43e9d192
IB		 594
595;; Give the length suffix letter for a sign- or zero-extension.
596(define_mode_attr size [(QI "b") (HI "h") (SI "w")])
597
598;; Give the number of bits in the mode
599(define_mode_attr sizen [(QI "8") (HI "16") (SI "32") (DI "64")])
600
601;; Give the ordinal of the MSB in the mode
602(define_mode_attr sizem1 [(QI "#7") (HI "#15") (SI "#31") (DI "#63")])
603
604;; Attribute to describe constants acceptable in logical operations
605(define_mode_attr lconst [(SI "K") (DI "L")])
606
43fd192f
MC		 607;; Attribute to describe constants acceptable in logical and operations
608(define_mode_attr lconst2 [(SI "UsO") (DI "UsP")])
609
43e9d192
IB		 610;; Map a mode to a specific constraint character.
611(define_mode_attr cmode [(QI "q") (HI "h") (SI "s") (DI "d")])
612
0603375c
KT		 613;; Map modes to Usg and Usj constraints for SISD right shifts
614(define_mode_attr cmode_simd [(SI "g") (DI "j")])
615
43e9d192
IB		 616(define_mode_attr Vtype [(V8QI "8b") (V16QI "16b")
617 (V4HI "4h") (V8HI "8h")
618 (V2SI "2s") (V4SI "4s")
619 (DI "1d") (DF "1d")
620 (V2DI "2d") (V2SF "2s")
7c369485
AL		 621 (V4SF "4s") (V2DF "2d")
622 (V4HF "4h") (V8HF "8h")])
43e9d192 623
c7f28cd5
KT		 624(define_mode_attr Vrevsuff [(V4HI "16") (V8HI "16") (V2SI "32")
625 (V4SI "32") (V2DI "64")])
626
43e9d192
IB		 627(define_mode_attr Vmtype [(V8QI ".8b") (V16QI ".16b")
628 (V4HI ".4h") (V8HI ".8h")
629 (V2SI ".2s") (V4SI ".4s")
71a11456
AL		 630 (V2DI ".2d") (V4HF ".4h")
631 (V8HF ".8h") (V2SF ".2s")
43e9d192
IB		 632 (V4SF ".4s") (V2DF ".2d")
633 (DI "") (SI "")
634 (HI "") (QI "")
d7f33f07
JW		 635 (TI "") (HF "")
636 (SF "") (DF "")])
43e9d192
IB		 637
638;; Register suffix narrowed modes for VQN.
639(define_mode_attr Vmntype [(V8HI ".8b") (V4SI ".4h")
640 (V2DI ".2s")
641 (DI "") (SI "")
642 (HI "")])
643
644;; Mode-to-individual element type mapping.
43cacb12
RS		 645(define_mode_attr Vetype [(V8QI "b") (V16QI "b") (VNx16QI "b") (VNx16BI "b")
646 (V4HI "h") (V8HI "h") (VNx8HI "h") (VNx8BI "h")
647 (V2SI "s") (V4SI "s") (VNx4SI "s") (VNx4BI "s")
648 (V2DI "d") (VNx2DI "d") (VNx2BI "d")
649 (V4HF "h") (V8HF "h") (VNx8HF "h")
650 (V2SF "s") (V4SF "s") (VNx4SF "s")
651 (V2DF "d") (VNx2DF "d")
d7f33f07 652 (HF "h")
0f686aa9 653 (SF "s") (DF "d")
43e9d192
IB		 654 (QI "b") (HI "h")
655 (SI "s") (DI "d")])
656
43cacb12
RS		 657;; Equivalent of "size" for a vector element.
658(define_mode_attr Vesize [(VNx16QI "b")
9f4cbab8
RS		 659 (VNx8HI "h") (VNx8HF "h")
660 (VNx4SI "w") (VNx4SF "w")
661 (VNx2DI "d") (VNx2DF "d")
662 (VNx32QI "b") (VNx48QI "b") (VNx64QI "b")
663 (VNx16HI "h") (VNx24HI "h") (VNx32HI "h")
664 (VNx16HF "h") (VNx24HF "h") (VNx32HF "h")
665 (VNx8SI "w") (VNx12SI "w") (VNx16SI "w")
666 (VNx8SF "w") (VNx12SF "w") (VNx16SF "w")
667 (VNx4DI "d") (VNx6DI "d") (VNx8DI "d")
668 (VNx4DF "d") (VNx6DF "d") (VNx8DF "d")])
43cacb12 669
daef0a8c
JW		 670;; Vetype is used everywhere in scheduling type and assembly output,
671;; sometimes they are not the same, for example HF modes on some
672;; instructions. stype is defined to represent scheduling type
673;; more accurately.
674(define_mode_attr stype [(V8QI "b") (V16QI "b") (V4HI "s") (V8HI "s")
675 (V2SI "s") (V4SI "s") (V2DI "d") (V4HF "s")
676 (V8HF "s") (V2SF "s") (V4SF "s") (V2DF "d")
677 (HF "s") (SF "s") (DF "d") (QI "b") (HI "s")
678 (SI "s") (DI "d")])
679
43e9d192
IB		 680;; Mode-to-bitwise operation type mapping.
681(define_mode_attr Vbtype [(V8QI "8b") (V16QI "16b")
682 (V4HI "8b") (V8HI "16b")
683 (V2SI "8b") (V4SI "16b")
7c369485
AL		 684 (V2DI "16b") (V4HF "8b")
685 (V8HF "16b") (V2SF "8b")
46e778c4 686 (V4SF "16b") (V2DF "16b")
fe82d1f2
AL		 687 (DI "8b") (DF "8b")
688 (SI "8b")])
43e9d192
IB		 689
690;; Define element mode for each vector mode.
43cacb12
RS		 691(define_mode_attr VEL [(V8QI "QI") (V16QI "QI") (VNx16QI "QI")
692 (V4HI "HI") (V8HI "HI") (VNx8HI "HI")
693 (V2SI "SI") (V4SI "SI") (VNx4SI "SI")
694 (DI "DI") (V2DI "DI") (VNx2DI "DI")
695 (V4HF "HF") (V8HF "HF") (VNx8HF "HF")
696 (V2SF "SF") (V4SF "SF") (VNx4SF "SF")
697 (DF "DF") (V2DF "DF") (VNx2DF "DF")
698 (SI "SI") (HI "HI")
43e9d192
IB		 699 (QI "QI")])
700
ff03930a 701;; Define element mode for each vector mode (lower case).
43cacb12
RS		 702(define_mode_attr Vel [(V8QI "qi") (V16QI "qi") (VNx16QI "qi")
703 (V4HI "hi") (V8HI "hi") (VNx8HI "hi")
704 (V2SI "si") (V4SI "si") (VNx4SI "si")
705 (DI "di") (V2DI "di") (VNx2DI "di")
706 (V4HF "hf") (V8HF "hf") (VNx8HF "hf")
707 (V2SF "sf") (V4SF "sf") (VNx4SF "sf")
708 (V2DF "df") (DF "df") (VNx2DF "df")
ff03930a
JJ		 709 (SI "si") (HI "hi")
710 (QI "qi")])
711
43cacb12
RS		 712;; Element mode with floating-point values replaced by like-sized integers.
713(define_mode_attr VEL_INT [(VNx16QI "QI")
714 (VNx8HI "HI") (VNx8HF "HI")
715 (VNx4SI "SI") (VNx4SF "SI")
716 (VNx2DI "DI") (VNx2DF "DI")])
717
718;; Gives the mode of the 128-bit lowpart of an SVE vector.
719(define_mode_attr V128 [(VNx16QI "V16QI")
720 (VNx8HI "V8HI") (VNx8HF "V8HF")
721 (VNx4SI "V4SI") (VNx4SF "V4SF")
722 (VNx2DI "V2DI") (VNx2DF "V2DF")])
723
724;; ...and again in lower case.
725(define_mode_attr v128 [(VNx16QI "v16qi")
726 (VNx8HI "v8hi") (VNx8HF "v8hf")
727 (VNx4SI "v4si") (VNx4SF "v4sf")
728 (VNx2DI "v2di") (VNx2DF "v2df")])
729
278821f2
KT		 730;; 64-bit container modes the inner or scalar source mode.
731(define_mode_attr VCOND [(HI "V4HI") (SI "V2SI")
732 (V4HI "V4HI") (V8HI "V4HI")
b7d7d917
TB		 733 (V2SI "V2SI") (V4SI "V2SI")
734 (DI "DI") (V2DI "DI")
735 (V2SF "V2SF") (V4SF "V2SF")
736 (V2DF "DF")])
737
278821f2 738;; 128-bit container modes the inner or scalar source mode.
b7d7d917
TB		 739(define_mode_attr VCONQ [(V8QI "V16QI") (V16QI "V16QI")
740 (V4HI "V8HI") (V8HI "V8HI")
741 (V2SI "V4SI") (V4SI "V4SI")
742 (DI "V2DI") (V2DI "V2DI")
71a11456 743 (V4HF "V8HF") (V8HF "V8HF")
b7d7d917
TB		 744 (V2SF "V2SF") (V4SF "V4SF")
745 (V2DF "V2DF") (SI "V4SI")
746 (HI "V8HI") (QI "V16QI")])
747
43e9d192
IB		 748;; Half modes of all vector modes.
749(define_mode_attr VHALF [(V8QI "V4QI") (V16QI "V8QI")
750 (V4HI "V2HI") (V8HI "V4HI")
751 (V2SI "SI") (V4SI "V2SI")
752 (V2DI "DI") (V2SF "SF")
71a11456
AL		 753 (V4SF "V2SF") (V4HF "V2HF")
754 (V8HF "V4HF") (V2DF "DF")])
43e9d192 755
b1b49824
MC		 756;; Half modes of all vector modes, in lower-case.
757(define_mode_attr Vhalf [(V8QI "v4qi") (V16QI "v8qi")
758 (V4HI "v2hi") (V8HI "v4hi")
759 (V2SI "si") (V4SI "v2si")
760 (V2DI "di") (V2SF "sf")
761 (V4SF "v2sf") (V2DF "df")])
762
43e9d192
IB		 763;; Double modes of vector modes.
764(define_mode_attr VDBL [(V8QI "V16QI") (V4HI "V8HI")
71a11456 765 (V4HF "V8HF")
43e9d192
IB		 766 (V2SI "V4SI") (V2SF "V4SF")
767 (SI "V2SI") (DI "V2DI")
768 (DF "V2DF")])
769
922f9c25
AL		 770;; Register suffix for double-length mode.
771(define_mode_attr Vdtype [(V4HF "8h") (V2SF "4s")])
772
43e9d192
IB		 773;; Double modes of vector modes (lower case).
774(define_mode_attr Vdbl [(V8QI "v16qi") (V4HI "v8hi")
7c369485 775 (V4HF "v8hf")
43e9d192 776 (V2SI "v4si") (V2SF "v4sf")
8b033a8a
SN		 777 (SI "v2si") (DI "v2di")
778 (DF "v2df")])
43e9d192 779
b1b49824
MC		 780;; Modes with double-width elements.
781(define_mode_attr VDBLW [(V8QI "V4HI") (V16QI "V8HI")
782 (V4HI "V2SI") (V8HI "V4SI")
783 (V2SI "DI") (V4SI "V2DI")])
784
43e9d192
IB		 785;; Narrowed modes for VDN.
786(define_mode_attr VNARROWD [(V4HI "V8QI") (V2SI "V4HI")
787 (DI "V2SI")])
788
789;; Narrowed double-modes for VQN (Used for XTN).
790(define_mode_attr VNARROWQ [(V8HI "V8QI") (V4SI "V4HI")
791 (V2DI "V2SI")
792 (DI "SI") (SI "HI")
793 (HI "QI")])
794
795;; Narrowed quad-modes for VQN (Used for XTN2).
796(define_mode_attr VNARROWQ2 [(V8HI "V16QI") (V4SI "V8HI")
797 (V2DI "V4SI")])
798
799;; Register suffix narrowed modes for VQN.
800(define_mode_attr Vntype [(V8HI "8b") (V4SI "4h")
801 (V2DI "2s")])
802
803;; Register suffix narrowed modes for VQN.
804(define_mode_attr V2ntype [(V8HI "16b") (V4SI "8h")
805 (V2DI "4s")])
806
807;; Widened modes of vector modes.
43cacb12
RS		 808(define_mode_attr VWIDE [(V8QI "V8HI") (V4HI "V4SI")
809 (V2SI "V2DI") (V16QI "V8HI")
810 (V8HI "V4SI") (V4SI "V2DI")
811 (HI "SI") (SI "DI")
812 (V8HF "V4SF") (V4SF "V2DF")
813 (V4HF "V4SF") (V2SF "V2DF")
814 (VNx8HF "VNx4SF") (VNx4SF "VNx2DF")
815 (VNx16QI "VNx8HI") (VNx8HI "VNx4SI")
816 (VNx4SI "VNx2DI")
817 (VNx16BI "VNx8BI") (VNx8BI "VNx4BI")
818 (VNx4BI "VNx2BI")])
819
820;; Predicate mode associated with VWIDE.
821(define_mode_attr VWIDE_PRED [(VNx8HF "VNx4BI") (VNx4SF "VNx2BI")])
43e9d192 822
03873eb9 823;; Widened modes of vector modes, lowercase
43cacb12
RS		 824(define_mode_attr Vwide [(V2SF "v2df") (V4HF "v4sf")
825 (VNx16QI "vnx8hi") (VNx8HI "vnx4si")
826 (VNx4SI "vnx2di")
827 (VNx8HF "vnx4sf") (VNx4SF "vnx2df")
828 (VNx16BI "vnx8bi") (VNx8BI "vnx4bi")
829 (VNx4BI "vnx2bi")])
03873eb9
AL		 830
831;; Widened mode register suffixes for VD_BHSI/VQW/VQ_HSF.
43e9d192
IB		 832(define_mode_attr Vwtype [(V8QI "8h") (V4HI "4s")
833 (V2SI "2d") (V16QI "8h")
03873eb9
AL		 834 (V8HI "4s") (V4SI "2d")
835 (V8HF "4s") (V4SF "2d")])
43e9d192 836
43cacb12
RS		 837;; SVE vector after widening
838(define_mode_attr Vewtype [(VNx16QI "h")
839 (VNx8HI "s") (VNx8HF "s")
840 (VNx4SI "d") (VNx4SF "d")])
841
43e9d192
IB		 842;; Widened mode register suffixes for VDW/VQW.
843(define_mode_attr Vmwtype [(V8QI ".8h") (V4HI ".4s")
844 (V2SI ".2d") (V16QI ".8h")
845 (V8HI ".4s") (V4SI ".2d")
922f9c25 846 (V4HF ".4s") (V2SF ".2d")
43e9d192
IB		 847 (SI "") (HI "")])
848
03873eb9 849;; Lower part register suffixes for VQW/VQ_HSF.
43e9d192 850(define_mode_attr Vhalftype [(V16QI "8b") (V8HI "4h")
03873eb9
AL		 851 (V4SI "2s") (V8HF "4h")
852 (V4SF "2s")])
43e9d192
IB		 853
854;; Define corresponding core/FP element mode for each vector mode.
43cacb12
RS		 855(define_mode_attr vw [(V8QI "w") (V16QI "w") (VNx16QI "w")
856 (V4HI "w") (V8HI "w") (VNx8HI "w")
857 (V2SI "w") (V4SI "w") (VNx4SI "w")
858 (DI "x") (V2DI "x") (VNx2DI "x")
859 (VNx8HF "h")
860 (V2SF "s") (V4SF "s") (VNx4SF "s")
861 (V2DF "d") (VNx2DF "d")])
43e9d192 862
66adb8eb
JG		 863;; Corresponding core element mode for each vector mode. This is a
864;; variation on <vw> mapping FP modes to GP regs.
43cacb12
RS		 865(define_mode_attr vwcore [(V8QI "w") (V16QI "w") (VNx16QI "w")
866 (V4HI "w") (V8HI "w") (VNx8HI "w")
867 (V2SI "w") (V4SI "w") (VNx4SI "w")
868 (DI "x") (V2DI "x") (VNx2DI "x")
869 (V4HF "w") (V8HF "w") (VNx8HF "w")
870 (V2SF "w") (V4SF "w") (VNx4SF "w")
871 (V2DF "x") (VNx2DF "x")])
66adb8eb 872
43e9d192
IB		 873;; Double vector types for ALLX.
874(define_mode_attr Vallxd [(QI "8b") (HI "4h") (SI "2s")])
875
5f565314
RS		 876;; Mode with floating-point values replaced by like-sized integers.
877(define_mode_attr V_INT_EQUIV [(V8QI "V8QI") (V16QI "V16QI")
878 (V4HI "V4HI") (V8HI "V8HI")
879 (V2SI "V2SI") (V4SI "V4SI")
880 (DI "DI") (V2DI "V2DI")
881 (V4HF "V4HI") (V8HF "V8HI")
882 (V2SF "V2SI") (V4SF "V4SI")
43cacb12 883 (DF "DI") (V2DF "V2DI")
dfe1da23
JW		 884 (SF "SI") (SI "SI")
885 (HF "HI")
43cacb12
RS		 886 (VNx16QI "VNx16QI")
887 (VNx8HI "VNx8HI") (VNx8HF "VNx8HI")
888 (VNx4SI "VNx4SI") (VNx4SF "VNx4SI")
889 (VNx2DI "VNx2DI") (VNx2DF "VNx2DI")
890])
5f565314
RS		 891
892;; Lower case mode with floating-point values replaced by like-sized integers.
893(define_mode_attr v_int_equiv [(V8QI "v8qi") (V16QI "v16qi")
894 (V4HI "v4hi") (V8HI "v8hi")
895 (V2SI "v2si") (V4SI "v4si")
896 (DI "di") (V2DI "v2di")
897 (V4HF "v4hi") (V8HF "v8hi")
898 (V2SF "v2si") (V4SF "v4si")
43cacb12
RS		 899 (DF "di") (V2DF "v2di")
900 (SF "si")
901 (VNx16QI "vnx16qi")
902 (VNx8HI "vnx8hi") (VNx8HF "vnx8hi")
903 (VNx4SI "vnx4si") (VNx4SF "vnx4si")
904 (VNx2DI "vnx2di") (VNx2DF "vnx2di")
905])
906
907;; Floating-point equivalent of selected modes.
908(define_mode_attr V_FP_EQUIV [(VNx4SI "VNx4SF") (VNx4SF "VNx4SF")
909 (VNx2DI "VNx2DF") (VNx2DF "VNx2DF")])
910(define_mode_attr v_fp_equiv [(VNx4SI "vnx4sf") (VNx4SF "vnx4sf")
911 (VNx2DI "vnx2df") (VNx2DF "vnx2df")])
70c67693 912
6c553b76
BC		 913;; Mode for vector conditional operations where the comparison has
914;; different type from the lhs.
915(define_mode_attr V_cmp_mixed [(V2SI "V2SF") (V4SI "V4SF")
916 (V2DI "V2DF") (V2SF "V2SI")
917 (V4SF "V4SI") (V2DF "V2DI")])
918
919(define_mode_attr v_cmp_mixed [(V2SI "v2sf") (V4SI "v4sf")
920 (V2DI "v2df") (V2SF "v2si")
921 (V4SF "v4si") (V2DF "v2di")])
922
cb23a30c
JG		 923;; Lower case element modes (as used in shift immediate patterns).
924(define_mode_attr ve_mode [(V8QI "qi") (V16QI "qi")
925 (V4HI "hi") (V8HI "hi")
926 (V2SI "si") (V4SI "si")
927 (DI "di") (V2DI "di")
928 (QI "qi") (HI "hi")
929 (SI "si")])
930
43e9d192
IB		 931;; Vm for lane instructions is restricted to FP_LO_REGS.
932(define_mode_attr vwx [(V4HI "x") (V8HI "x") (HI "x")
933 (V2SI "w") (V4SI "w") (SI "w")])
934
935(define_mode_attr Vendreg [(OI "T") (CI "U") (XI "V")])
936
97755701
AL		 937;; This is both the number of Q-Registers needed to hold the corresponding
938;; opaque large integer mode, and the number of elements touched by the
939;; ld..._lane and st..._lane operations.
43e9d192
IB		 940(define_mode_attr nregs [(OI "2") (CI "3") (XI "4")])
941
0462169c
SN		 942;; Mode for atomic operation suffixes
943(define_mode_attr atomic_sfx
944 [(QI "b") (HI "h") (SI "") (DI "")])
945
3f598afe 946(define_mode_attr fcvt_target [(V2DF "v2di") (V4SF "v4si") (V2SF "v2si")
2644d4d9 947 (V2DI "v2df") (V4SI "v4sf") (V2SI "v2sf")
daef0a8c
JW		 948 (SF "si") (DF "di") (SI "sf") (DI "df")
949 (V4HF "v4hi") (V8HF "v8hi") (V4HI "v4hf")
68ad28c3 950 (V8HI "v8hf") (HF "hi") (HI "hf")])
3f598afe 951(define_mode_attr FCVT_TARGET [(V2DF "V2DI") (V4SF "V4SI") (V2SF "V2SI")
2644d4d9 952 (V2DI "V2DF") (V4SI "V4SF") (V2SI "V2SF")
daef0a8c
JW		 953 (SF "SI") (DF "DI") (SI "SF") (DI "DF")
954 (V4HF "V4HI") (V8HF "V8HI") (V4HI "V4HF")
68ad28c3 955 (V8HI "V8HF") (HF "HI") (HI "HF")])
3f598afe 956
0d35c5c2
VP		 957
958;; for the inequal width integer to fp conversions
d7f33f07
JW		 959(define_mode_attr fcvt_iesize [(HF "di") (SF "di") (DF "si")])
960(define_mode_attr FCVT_IESIZE [(HF "DI") (SF "DI") (DF "SI")])
42fc9a7f 961
91bd4114
JG		 962(define_mode_attr VSWAP_WIDTH [(V8QI "V16QI") (V16QI "V8QI")
963 (V4HI "V8HI") (V8HI "V4HI")
964 (V2SI "V4SI") (V4SI "V2SI")
965 (DI "V2DI") (V2DI "DI")
966 (V2SF "V4SF") (V4SF "V2SF")
862abc04 967 (V4HF "V8HF") (V8HF "V4HF")
91bd4114
JG		 968 (DF "V2DF") (V2DF "DF")])
969
970(define_mode_attr vswap_width_name [(V8QI "to_128") (V16QI "to_64")
971 (V4HI "to_128") (V8HI "to_64")
972 (V2SI "to_128") (V4SI "to_64")
973 (DI "to_128") (V2DI "to_64")
862abc04 974 (V4HF "to_128") (V8HF "to_64")
91bd4114
JG		 975 (V2SF "to_128") (V4SF "to_64")
976 (DF "to_128") (V2DF "to_64")])
977
779aea46 978;; For certain vector-by-element multiplication instructions we must
6d06971d 979;; constrain the 16-bit cases to use only V0-V15. This is covered by
779aea46
JG		 980;; the 'x' constraint. All other modes may use the 'w' constraint.
981(define_mode_attr h_con [(V2SI "w") (V4SI "w")
982 (V4HI "x") (V8HI "x")
6d06971d 983 (V4HF "x") (V8HF "x")
779aea46
JG		 984 (V2SF "w") (V4SF "w")
985 (V2DF "w") (DF "w")])
986
987;; Defined to 'f' for types whose element type is a float type.
988(define_mode_attr f [(V8QI "") (V16QI "")
989 (V4HI "") (V8HI "")
990 (V2SI "") (V4SI "")
991 (DI "") (V2DI "")
ab2e8f01 992 (V4HF "f") (V8HF "f")
779aea46
JG		 993 (V2SF "f") (V4SF "f")
994 (V2DF "f") (DF "f")])
995
0f686aa9
JG		 996;; Defined to '_fp' for types whose element type is a float type.
997(define_mode_attr fp [(V8QI "") (V16QI "")
998 (V4HI "") (V8HI "")
999 (V2SI "") (V4SI "")
1000 (DI "") (V2DI "")
ab2e8f01 1001 (V4HF "_fp") (V8HF "_fp")
0f686aa9
JG		 1002 (V2SF "_fp") (V4SF "_fp")
1003 (V2DF "_fp") (DF "_fp")
1004 (SF "_fp")])
1005
a9e66678
JG		 1006;; Defined to '_q' for 128-bit types.
1007(define_mode_attr q [(V8QI "") (V16QI "_q")
0f686aa9
JG		 1008 (V4HI "") (V8HI "_q")
1009 (V2SI "") (V4SI "_q")
1010 (DI "") (V2DI "_q")
71a11456 1011 (V4HF "") (V8HF "_q")
0f686aa9
JG		 1012 (V2SF "") (V4SF "_q")
1013 (V2DF "_q")
d7f33f07 1014 (QI "") (HI "") (SI "") (DI "") (HF "") (SF "") (DF "")])
a9e66678 1015
92835317
TB		 1016(define_mode_attr vp [(V8QI "v") (V16QI "v")
1017 (V4HI "v") (V8HI "v")
1018 (V2SI "p") (V4SI "v")
703bbcdf
JW		 1019 (V2DI "p") (V2DF "p")
1020 (V2SF "p") (V4SF "v")
1021 (V4HF "v") (V8HF "v")])
92835317 1022
5e32e83b
JW		 1023(define_mode_attr vsi2qi [(V2SI "v8qi") (V4SI "v16qi")])
1024(define_mode_attr VSI2QI [(V2SI "V8QI") (V4SI "V16QI")])
1025
7a08d813
TC		 1026
1027;; Register suffix for DOTPROD input types from the return type.
1028(define_mode_attr Vdottype [(V2SI "8b") (V4SI "16b")])
1029
cd78b3dd 1030;; Sum of lengths of instructions needed to move vector registers of a mode.
668046d1
DS		 1031(define_mode_attr insn_count [(OI "8") (CI "12") (XI "16")])
1032
1b1e81f8
JW		 1033;; -fpic small model GOT reloc modifers: gotpage_lo15/lo14 for ILP64/32.
1034;; No need of iterator for -fPIC as it use got_lo12 for both modes.
1035(define_mode_attr got_modifier [(SI "gotpage_lo14") (DI "gotpage_lo15")])
1036
27086ea3
MC		 1037;; Width of 2nd and 3rd arguments to fp16 vector multiply add/sub
1038(define_mode_attr VFMLA_W [(V2SF "V4HF") (V4SF "V8HF")])
1039
1040(define_mode_attr VFMLA_SEL_W [(V2SF "V2HF") (V4SF "V4HF")])
1041
1042(define_mode_attr f16quad [(V2SF "") (V4SF "q")])
1043
1044(define_code_attr f16mac [(plus "a") (minus "s")])
1045
9f4cbab8
RS		 1046;; The number of subvectors in an SVE_STRUCT.
1047(define_mode_attr vector_count [(VNx32QI "2") (VNx16HI "2")
1048 (VNx8SI "2") (VNx4DI "2")
1049 (VNx16HF "2") (VNx8SF "2") (VNx4DF "2")
1050 (VNx48QI "3") (VNx24HI "3")
1051 (VNx12SI "3") (VNx6DI "3")
1052 (VNx24HF "3") (VNx12SF "3") (VNx6DF "3")
1053 (VNx64QI "4") (VNx32HI "4")
1054 (VNx16SI "4") (VNx8DI "4")
1055 (VNx32HF "4") (VNx16SF "4") (VNx8DF "4")])
1056
1057;; The number of instruction bytes needed for an SVE_STRUCT move. This is
1058;; equal to vector_count * 4.
1059(define_mode_attr insn_length [(VNx32QI "8") (VNx16HI "8")
1060 (VNx8SI "8") (VNx4DI "8")
1061 (VNx16HF "8") (VNx8SF "8") (VNx4DF "8")
1062 (VNx48QI "12") (VNx24HI "12")
1063 (VNx12SI "12") (VNx6DI "12")
1064 (VNx24HF "12") (VNx12SF "12") (VNx6DF "12")
1065 (VNx64QI "16") (VNx32HI "16")
1066 (VNx16SI "16") (VNx8DI "16")
1067 (VNx32HF "16") (VNx16SF "16") (VNx8DF "16")])
1068
1069;; The type of a subvector in an SVE_STRUCT.
1070(define_mode_attr VSINGLE [(VNx32QI "VNx16QI")
1071 (VNx16HI "VNx8HI") (VNx16HF "VNx8HF")
1072 (VNx8SI "VNx4SI") (VNx8SF "VNx4SF")
1073 (VNx4DI "VNx2DI") (VNx4DF "VNx2DF")
1074 (VNx48QI "VNx16QI")
1075 (VNx24HI "VNx8HI") (VNx24HF "VNx8HF")
1076 (VNx12SI "VNx4SI") (VNx12SF "VNx4SF")
1077 (VNx6DI "VNx2DI") (VNx6DF "VNx2DF")
1078 (VNx64QI "VNx16QI")
1079 (VNx32HI "VNx8HI") (VNx32HF "VNx8HF")
1080 (VNx16SI "VNx4SI") (VNx16SF "VNx4SF")
1081 (VNx8DI "VNx2DI") (VNx8DF "VNx2DF")])
1082
1083;; ...and again in lower case.
1084(define_mode_attr vsingle [(VNx32QI "vnx16qi")
1085 (VNx16HI "vnx8hi") (VNx16HF "vnx8hf")
1086 (VNx8SI "vnx4si") (VNx8SF "vnx4sf")
1087 (VNx4DI "vnx2di") (VNx4DF "vnx2df")
1088 (VNx48QI "vnx16qi")
1089 (VNx24HI "vnx8hi") (VNx24HF "vnx8hf")
1090 (VNx12SI "vnx4si") (VNx12SF "vnx4sf")
1091 (VNx6DI "vnx2di") (VNx6DF "vnx2df")
1092 (VNx64QI "vnx16qi")
1093 (VNx32HI "vnx8hi") (VNx32HF "vnx8hf")
1094 (VNx16SI "vnx4si") (VNx16SF "vnx4sf")
1095 (VNx8DI "vnx2di") (VNx8DF "vnx2df")])
1096
1097;; The predicate mode associated with an SVE data mode. For structure modes
1098;; this is equivalent to the <VPRED> of the subvector mode.
43cacb12
RS		 1099(define_mode_attr VPRED [(VNx16QI "VNx16BI")
1100 (VNx8HI "VNx8BI") (VNx8HF "VNx8BI")
1101 (VNx4SI "VNx4BI") (VNx4SF "VNx4BI")
9f4cbab8
RS		 1102 (VNx2DI "VNx2BI") (VNx2DF "VNx2BI")
1103 (VNx32QI "VNx16BI")
1104 (VNx16HI "VNx8BI") (VNx16HF "VNx8BI")
1105 (VNx8SI "VNx4BI") (VNx8SF "VNx4BI")
1106 (VNx4DI "VNx2BI") (VNx4DF "VNx2BI")
1107 (VNx48QI "VNx16BI")
1108 (VNx24HI "VNx8BI") (VNx24HF "VNx8BI")
1109 (VNx12SI "VNx4BI") (VNx12SF "VNx4BI")
1110 (VNx6DI "VNx2BI") (VNx6DF "VNx2BI")
1111 (VNx64QI "VNx16BI")
1112 (VNx32HI "VNx8BI") (VNx32HF "VNx8BI")
1113 (VNx16SI "VNx4BI") (VNx16SF "VNx4BI")
1114 (VNx8DI "VNx2BI") (VNx8DF "VNx2BI")])
43cacb12
RS		 1115
1116;; ...and again in lower case.
1117(define_mode_attr vpred [(VNx16QI "vnx16bi")
1118 (VNx8HI "vnx8bi") (VNx8HF "vnx8bi")
1119 (VNx4SI "vnx4bi") (VNx4SF "vnx4bi")
9f4cbab8
RS		 1120 (VNx2DI "vnx2bi") (VNx2DF "vnx2bi")
1121 (VNx32QI "vnx16bi")
1122 (VNx16HI "vnx8bi") (VNx16HF "vnx8bi")
1123 (VNx8SI "vnx4bi") (VNx8SF "vnx4bi")
1124 (VNx4DI "vnx2bi") (VNx4DF "vnx2bi")
1125 (VNx48QI "vnx16bi")
1126 (VNx24HI "vnx8bi") (VNx24HF "vnx8bi")
1127 (VNx12SI "vnx4bi") (VNx12SF "vnx4bi")
1128 (VNx6DI "vnx2bi") (VNx6DF "vnx2bi")
1129 (VNx64QI "vnx16bi")
1130 (VNx32HI "vnx8bi") (VNx32HF "vnx4bi")
1131 (VNx16SI "vnx4bi") (VNx16SF "vnx4bi")
1132 (VNx8DI "vnx2bi") (VNx8DF "vnx2bi")])
43cacb12 1133
43e9d192
IB		 1134;; -------------------------------------------------------------------
1135;; Code Iterators
1136;; -------------------------------------------------------------------
1137
1138;; This code iterator allows the various shifts supported on the core
1139(define_code_iterator SHIFT [ashift ashiftrt lshiftrt rotatert])
1140
1141;; This code iterator allows the shifts supported in arithmetic instructions
1142(define_code_iterator ASHIFT [ashift ashiftrt lshiftrt])
1143
1144;; Code iterator for logical operations
1145(define_code_iterator LOGICAL [and ior xor])
1146
43cacb12
RS		 1147;; LOGICAL without AND.
1148(define_code_iterator LOGICAL_OR [ior xor])
1149
84be6032
AL		 1150;; Code iterator for logical operations whose :nlogical works on SIMD registers.
1151(define_code_iterator NLOGICAL [and ior])
1152
3204ac98
KT		 1153;; Code iterator for unary negate and bitwise complement.
1154(define_code_iterator NEG_NOT [neg not])
1155
43e9d192
IB		 1156;; Code iterator for sign/zero extension
1157(define_code_iterator ANY_EXTEND [sign_extend zero_extend])
1158
1159;; All division operations (signed/unsigned)
1160(define_code_iterator ANY_DIV [div udiv])
1161
1162;; Code iterator for sign/zero extraction
1163(define_code_iterator ANY_EXTRACT [sign_extract zero_extract])
1164
1165;; Code iterator for equality comparisons
1166(define_code_iterator EQL [eq ne])
1167
1168;; Code iterator for less-than and greater/equal-to
1169(define_code_iterator LTGE [lt ge])
1170
1171;; Iterator for __sync_<op> operations that where the operation can be
1172;; represented directly RTL. This is all of the sync operations bar
1173;; nand.
0462169c 1174(define_code_iterator atomic_op [plus minus ior xor and])
43e9d192
IB		 1175
1176;; Iterator for integer conversions
1177(define_code_iterator FIXUORS [fix unsigned_fix])
1178
1709ff9b
JG		 1179;; Iterator for float conversions
1180(define_code_iterator FLOATUORS [float unsigned_float])
1181
43e9d192
IB		 1182;; Code iterator for variants of vector max and min.
1183(define_code_iterator MAXMIN [smax smin umax umin])
1184
998eaf97
JG		 1185(define_code_iterator FMAXMIN [smax smin])
1186
43e9d192
IB		 1187;; Code iterator for variants of vector max and min.
1188(define_code_iterator ADDSUB [plus minus])
1189
1190;; Code iterator for variants of vector saturating binary ops.
1191(define_code_iterator BINQOPS [ss_plus us_plus ss_minus us_minus])
1192
1193;; Code iterator for variants of vector saturating unary ops.
1194(define_code_iterator UNQOPS [ss_neg ss_abs])
1195
1196;; Code iterator for signed variants of vector saturating binary ops.
1197(define_code_iterator SBINQOPS [ss_plus ss_minus])
1198
889b9412
JG		 1199;; Comparison operators for <F>CM.
1200(define_code_iterator COMPARISONS [lt le eq ge gt])
1201
1202;; Unsigned comparison operators.
1203(define_code_iterator UCOMPARISONS [ltu leu geu gtu])
1204
75dd5ace
JG		 1205;; Unsigned comparison operators.
1206(define_code_iterator FAC_COMPARISONS [lt le ge gt])
1207
43cacb12
RS		 1208;; SVE integer unary operations.
1209(define_code_iterator SVE_INT_UNARY [neg not popcount])
1210
1211;; SVE floating-point unary operations.
1212(define_code_iterator SVE_FP_UNARY [neg abs sqrt])
1213
a08acce8 1214;; SVE integer binary operations.
6c4fd4a9 1215(define_code_iterator SVE_INT_BINARY [plus minus mult smax umax smin umin
9d4ac06e
RS		 1216 and ior xor])
1217
a08acce8 1218;; SVE integer binary division operations.
c38f7319
RS		 1219(define_code_iterator SVE_INT_BINARY_SD [div udiv])
1220
f22d7973
RS		 1221;; SVE integer comparisons.
1222(define_code_iterator SVE_INT_CMP [lt le eq ne ge gt ltu leu geu gtu])
1223
1224;; SVE floating-point comparisons.
1225(define_code_iterator SVE_FP_CMP [lt le eq ne ge gt])
1226
43e9d192
IB		 1227;; -------------------------------------------------------------------
1228;; Code Attributes
1229;; -------------------------------------------------------------------
1230;; Map rtl objects to optab names
1231(define_code_attr optab [(ashift "ashl")
1232 (ashiftrt "ashr")
1233 (lshiftrt "lshr")
1234 (rotatert "rotr")
1235 (sign_extend "extend")
1236 (zero_extend "zero_extend")
1237 (sign_extract "extv")
1238 (zero_extract "extzv")
384be29f
JG		 1239 (fix "fix")
1240 (unsigned_fix "fixuns")
1709ff9b
JG		 1241 (float "float")
1242 (unsigned_float "floatuns")
43cacb12 1243 (popcount "popcount")
43e9d192
IB		 1244 (and "and")
1245 (ior "ior")
1246 (xor "xor")
1247 (not "one_cmpl")
1248 (neg "neg")
1249 (plus "add")
1250 (minus "sub")
6c4fd4a9 1251 (mult "mul")
c38f7319
RS		 1252 (div "div")
1253 (udiv "udiv")
43e9d192
IB		 1254 (ss_plus "qadd")
1255 (us_plus "qadd")
1256 (ss_minus "qsub")
1257 (us_minus "qsub")
1258 (ss_neg "qneg")
1259 (ss_abs "qabs")
43cacb12
RS		 1260 (smin "smin")
1261 (smax "smax")
1262 (umin "umin")
1263 (umax "umax")
43e9d192
IB		 1264 (eq "eq")
1265 (ne "ne")
1266 (lt "lt")
889b9412
JG		 1267 (ge "ge")
1268 (le "le")
1269 (gt "gt")
1270 (ltu "ltu")
1271 (leu "leu")
1272 (geu "geu")
43cacb12
RS		 1273 (gtu "gtu")
1274 (abs "abs")
1275 (sqrt "sqrt")])
889b9412
JG		 1276
1277;; For comparison operators we use the FCM* and CM* instructions.
1278;; As there are no CMLE or CMLT instructions which act on 3 vector
1279;; operands, we must use CMGE or CMGT and swap the order of the
1280;; source operands.
1281
1282(define_code_attr n_optab [(lt "gt") (le "ge") (eq "eq") (ge "ge") (gt "gt")
1283 (ltu "hi") (leu "hs") (geu "hs") (gtu "hi")])
1284(define_code_attr cmp_1 [(lt "2") (le "2") (eq "1") (ge "1") (gt "1")
1285 (ltu "2") (leu "2") (geu "1") (gtu "1")])
1286(define_code_attr cmp_2 [(lt "1") (le "1") (eq "2") (ge "2") (gt "2")
1287 (ltu "1") (leu "1") (geu "2") (gtu "2")])
1288
1289(define_code_attr CMP [(lt "LT") (le "LE") (eq "EQ") (ge "GE") (gt "GT")
714e1b3b
KT		 1290 (ltu "LTU") (leu "LEU") (ne "NE") (geu "GEU")
1291 (gtu "GTU")])
43e9d192 1292
f22d7973
RS		 1293;; The AArch64 condition associated with an rtl comparison code.
1294(define_code_attr cmp_op [(lt "lt")
1295 (le "le")
1296 (eq "eq")
1297 (ne "ne")
1298 (ge "ge")
1299 (gt "gt")
1300 (ltu "lo")
1301 (leu "ls")
1302 (geu "hs")
1303 (gtu "hi")])
1304
384be29f
JG		 1305(define_code_attr fix_trunc_optab [(fix "fix_trunc")
1306 (unsigned_fix "fixuns_trunc")])
1307
43e9d192
IB		 1308;; Optab prefix for sign/zero-extending operations
1309(define_code_attr su_optab [(sign_extend "") (zero_extend "u")
1310 (div "") (udiv "u")
1311 (fix "") (unsigned_fix "u")
1709ff9b 1312 (float "s") (unsigned_float "u")
43e9d192
IB		 1313 (ss_plus "s") (us_plus "u")
1314 (ss_minus "s") (us_minus "u")])
1315
1316;; Similar for the instruction mnemonics
1317(define_code_attr shift [(ashift "lsl") (ashiftrt "asr")
1318 (lshiftrt "lsr") (rotatert "ror")])
1319
1320;; Map shift operators onto underlying bit-field instructions
1321(define_code_attr bfshift [(ashift "ubfiz") (ashiftrt "sbfx")
1322 (lshiftrt "ubfx") (rotatert "extr")])
1323
1324;; Logical operator instruction mnemonics
1325(define_code_attr logical [(and "and") (ior "orr") (xor "eor")])
1326
3204ac98
KT		 1327;; Operation names for negate and bitwise complement.
1328(define_code_attr neg_not_op [(neg "neg") (not "not")])
1329
43cacb12 1330;; Similar, but when the second operand is inverted.
43e9d192
IB		 1331(define_code_attr nlogical [(and "bic") (ior "orn") (xor "eon")])
1332
43cacb12
RS		 1333;; Similar, but when both operands are inverted.
1334(define_code_attr logical_nn [(and "nor") (ior "nand")])
1335
43e9d192
IB		 1336;; Sign- or zero-extending data-op
1337(define_code_attr su [(sign_extend "s") (zero_extend "u")
1338 (sign_extract "s") (zero_extract "u")
1339 (fix "s") (unsigned_fix "u")
998eaf97
JG		 1340 (div "s") (udiv "u")
1341 (smax "s") (umax "u")
1342 (smin "s") (umin "u")])
43e9d192 1343
43cacb12
RS		 1344;; Whether a shift is left or right.
1345(define_code_attr lr [(ashift "l") (ashiftrt "r") (lshiftrt "r")])
1346
096e8448
JW		 1347;; Emit conditional branch instructions.
1348(define_code_attr bcond [(eq "beq") (ne "bne") (lt "bne") (ge "beq")])
1349
43e9d192
IB		 1350;; Emit cbz/cbnz depending on comparison type.
1351(define_code_attr cbz [(eq "cbz") (ne "cbnz") (lt "cbnz") (ge "cbz")])
1352
973d2e01
TP		 1353;; Emit inverted cbz/cbnz depending on comparison type.
1354(define_code_attr inv_cb [(eq "cbnz") (ne "cbz") (lt "cbz") (ge "cbnz")])
1355
43e9d192
IB		 1356;; Emit tbz/tbnz depending on comparison type.
1357(define_code_attr tbz [(eq "tbz") (ne "tbnz") (lt "tbnz") (ge "tbz")])
1358
973d2e01
TP		 1359;; Emit inverted tbz/tbnz depending on comparison type.
1360(define_code_attr inv_tb [(eq "tbnz") (ne "tbz") (lt "tbz") (ge "tbnz")])
1361
43e9d192 1362;; Max/min attributes.
998eaf97
JG		 1363(define_code_attr maxmin [(smax "max")
1364 (smin "min")
1365 (umax "max")
1366 (umin "min")])
43e9d192
IB		 1367
1368;; MLA/MLS attributes.
1369(define_code_attr as [(ss_plus "a") (ss_minus "s")])
1370
0462169c
SN		 1371;; Atomic operations
1372(define_code_attr atomic_optab
1373 [(ior "or") (xor "xor") (and "and") (plus "add") (minus "sub")])
1374
1375(define_code_attr atomic_op_operand
1376 [(ior "aarch64_logical_operand")
1377 (xor "aarch64_logical_operand")
1378 (and "aarch64_logical_operand")
1379 (plus "aarch64_plus_operand")
1380 (minus "aarch64_plus_operand")])
43e9d192 1381
356c32e2
MW		 1382;; Constants acceptable for atomic operations.
1383;; This definition must appear in this file before the iterators it refers to.
1384(define_code_attr const_atomic
1385 [(plus "IJ") (minus "IJ")
1386 (xor "<lconst_atomic>") (ior "<lconst_atomic>")
1387 (and "<lconst_atomic>")])
1388
1389;; Attribute to describe constants acceptable in atomic logical operations
1390(define_mode_attr lconst_atomic [(QI "K") (HI "K") (SI "K") (DI "L")])
1391
43cacb12
RS		 1392;; The integer SVE instruction that implements an rtx code.
1393(define_code_attr sve_int_op [(plus "add")
9d4ac06e 1394 (minus "sub")
6c4fd4a9 1395 (mult "mul")
c38f7319
RS		 1396 (div "sdiv")
1397 (udiv "udiv")
43cacb12
RS		 1398 (neg "neg")
1399 (smin "smin")
1400 (smax "smax")
1401 (umin "umin")
1402 (umax "umax")
1403 (and "and")
1404 (ior "orr")
1405 (xor "eor")
1406 (not "not")
1407 (popcount "cnt")])
1408
a08acce8
RH		 1409(define_code_attr sve_int_op_rev [(plus "add")
1410 (minus "subr")
1411 (mult "mul")
1412 (div "sdivr")
1413 (udiv "udivr")
1414 (smin "smin")
1415 (smax "smax")
1416 (umin "umin")
1417 (umax "umax")
1418 (and "and")
1419 (ior "orr")
1420 (xor "eor")])
1421
43cacb12
RS		 1422;; The floating-point SVE instruction that implements an rtx code.
1423(define_code_attr sve_fp_op [(plus "fadd")
1424 (neg "fneg")
1425 (abs "fabs")
1426 (sqrt "fsqrt")])
1427
f22d7973
RS		 1428;; The SVE immediate constraint to use for an rtl code.
1429(define_code_attr sve_imm_con [(eq "vsc")
1430 (ne "vsc")
1431 (lt "vsc")
1432 (ge "vsc")
1433 (le "vsc")
1434 (gt "vsc")
1435 (ltu "vsd")
1436 (leu "vsd")
1437 (geu "vsd")
1438 (gtu "vsd")])
1439
43e9d192
IB		 1440;; -------------------------------------------------------------------
1441;; Int Iterators.
1442;; -------------------------------------------------------------------
75add2d0
KT		 1443
1444;; The unspec codes for the SABAL, UABAL AdvancedSIMD instructions.
1445(define_int_iterator ABAL [UNSPEC_SABAL UNSPEC_UABAL])
1446
1447;; The unspec codes for the SABDL2, UABDL2 AdvancedSIMD instructions.
1448(define_int_iterator ABDL2 [UNSPEC_SABDL2 UNSPEC_UABDL2])
1449
1450;; The unspec codes for the SADALP, UADALP AdvancedSIMD instructions.
1451(define_int_iterator ADALP [UNSPEC_SADALP UNSPEC_UADALP])
1452
43e9d192
IB		 1453(define_int_iterator MAXMINV [UNSPEC_UMAXV UNSPEC_UMINV
1454 UNSPEC_SMAXV UNSPEC_SMINV])
1455
998eaf97
JG		 1456(define_int_iterator FMAXMINV [UNSPEC_FMAXV UNSPEC_FMINV
1457 UNSPEC_FMAXNMV UNSPEC_FMINNMV])
43e9d192 1458
898f07b0
RS		 1459(define_int_iterator BITWISEV [UNSPEC_ANDV UNSPEC_IORV UNSPEC_XORV])
1460
43cacb12
RS		 1461(define_int_iterator LOGICALF [UNSPEC_ANDF UNSPEC_IORF UNSPEC_XORF])
1462
43e9d192
IB		 1463(define_int_iterator HADDSUB [UNSPEC_SHADD UNSPEC_UHADD
1464 UNSPEC_SRHADD UNSPEC_URHADD
1465 UNSPEC_SHSUB UNSPEC_UHSUB
1466 UNSPEC_SRHSUB UNSPEC_URHSUB])
1467
42addb5a
RS		 1468(define_int_iterator HADD [UNSPEC_SHADD UNSPEC_UHADD])
1469
1470(define_int_iterator RHADD [UNSPEC_SRHADD UNSPEC_URHADD])
1471
7a08d813 1472(define_int_iterator DOTPROD [UNSPEC_SDOT UNSPEC_UDOT])
43e9d192
IB		 1473
1474(define_int_iterator ADDSUBHN [UNSPEC_ADDHN UNSPEC_RADDHN
1475 UNSPEC_SUBHN UNSPEC_RSUBHN])
1476
1477(define_int_iterator ADDSUBHN2 [UNSPEC_ADDHN2 UNSPEC_RADDHN2
1478 UNSPEC_SUBHN2 UNSPEC_RSUBHN2])
1479
1efafef3
TC		 1480(define_int_iterator FMAXMIN_UNS [UNSPEC_FMAX UNSPEC_FMIN
1481 UNSPEC_FMAXNM UNSPEC_FMINNM])
202d0c11 1482
db58fd89
JW		 1483(define_int_iterator PAUTH_LR_SP [UNSPEC_PACISP UNSPEC_AUTISP])
1484
1485(define_int_iterator PAUTH_17_16 [UNSPEC_PACI1716 UNSPEC_AUTI1716])
1486
43e9d192
IB		 1487(define_int_iterator VQDMULH [UNSPEC_SQDMULH UNSPEC_SQRDMULH])
1488
1489(define_int_iterator USSUQADD [UNSPEC_SUQADD UNSPEC_USQADD])
1490
1491(define_int_iterator SUQMOVN [UNSPEC_SQXTN UNSPEC_UQXTN])
1492
1493(define_int_iterator VSHL [UNSPEC_SSHL UNSPEC_USHL
1494 UNSPEC_SRSHL UNSPEC_URSHL])
1495
1496(define_int_iterator VSHLL [UNSPEC_SSHLL UNSPEC_USHLL])
1497
1498(define_int_iterator VQSHL [UNSPEC_SQSHL UNSPEC_UQSHL
1499 UNSPEC_SQRSHL UNSPEC_UQRSHL])
1500
1501(define_int_iterator VSRA [UNSPEC_SSRA UNSPEC_USRA
1502 UNSPEC_SRSRA UNSPEC_URSRA])
1503
1504(define_int_iterator VSLRI [UNSPEC_SSLI UNSPEC_USLI
1505 UNSPEC_SSRI UNSPEC_USRI])
1506
1507
1508(define_int_iterator VRSHR_N [UNSPEC_SRSHR UNSPEC_URSHR])
1509
1510(define_int_iterator VQSHL_N [UNSPEC_SQSHLU UNSPEC_SQSHL UNSPEC_UQSHL])
1511
1512(define_int_iterator VQSHRN_N [UNSPEC_SQSHRUN UNSPEC_SQRSHRUN
1513 UNSPEC_SQSHRN UNSPEC_UQSHRN
1514 UNSPEC_SQRSHRN UNSPEC_UQRSHRN])
1515
57b26d65
MW		 1516(define_int_iterator SQRDMLH_AS [UNSPEC_SQRDMLAH UNSPEC_SQRDMLSH])
1517
cc4d934f
JG		 1518(define_int_iterator PERMUTE [UNSPEC_ZIP1 UNSPEC_ZIP2
1519 UNSPEC_TRN1 UNSPEC_TRN2
1520 UNSPEC_UZP1 UNSPEC_UZP2])
43e9d192 1521
43cacb12
RS		 1522(define_int_iterator OPTAB_PERMUTE [UNSPEC_ZIP1 UNSPEC_ZIP2
1523 UNSPEC_UZP1 UNSPEC_UZP2])
1524
923fcec3
AL		 1525(define_int_iterator REVERSE [UNSPEC_REV64 UNSPEC_REV32 UNSPEC_REV16])
1526
42fc9a7f 1527(define_int_iterator FRINT [UNSPEC_FRINTZ UNSPEC_FRINTP UNSPEC_FRINTM
0659ce6f
JG		 1528 UNSPEC_FRINTN UNSPEC_FRINTI UNSPEC_FRINTX
1529 UNSPEC_FRINTA])
42fc9a7f
JG		 1530
1531(define_int_iterator FCVT [UNSPEC_FRINTZ UNSPEC_FRINTP UNSPEC_FRINTM
ce966824 1532 UNSPEC_FRINTA UNSPEC_FRINTN])
42fc9a7f 1533
3f598afe
JW		 1534(define_int_iterator FCVT_F2FIXED [UNSPEC_FCVTZS UNSPEC_FCVTZU])
1535(define_int_iterator FCVT_FIXED2F [UNSPEC_SCVTF UNSPEC_UCVTF])
1536
0050faf8
JG		 1537(define_int_iterator FRECP [UNSPEC_FRECPE UNSPEC_FRECPX])
1538
5d357f26
KT		 1539(define_int_iterator CRC [UNSPEC_CRC32B UNSPEC_CRC32H UNSPEC_CRC32W
1540 UNSPEC_CRC32X UNSPEC_CRC32CB UNSPEC_CRC32CH
1541 UNSPEC_CRC32CW UNSPEC_CRC32CX])
1542
5a7a4e80
TB		 1543(define_int_iterator CRYPTO_AES [UNSPEC_AESE UNSPEC_AESD])
1544(define_int_iterator CRYPTO_AESMC [UNSPEC_AESMC UNSPEC_AESIMC])
1545
30442682
TB		 1546(define_int_iterator CRYPTO_SHA1 [UNSPEC_SHA1C UNSPEC_SHA1M UNSPEC_SHA1P])
1547
b9cb0a44
TB		 1548(define_int_iterator CRYPTO_SHA256 [UNSPEC_SHA256H UNSPEC_SHA256H2])
1549
27086ea3
MC		 1550(define_int_iterator CRYPTO_SHA512 [UNSPEC_SHA512H UNSPEC_SHA512H2])
1551
1552(define_int_iterator CRYPTO_SM3TT [UNSPEC_SM3TT1A UNSPEC_SM3TT1B
1553 UNSPEC_SM3TT2A UNSPEC_SM3TT2B])
1554
1555(define_int_iterator CRYPTO_SM3PART [UNSPEC_SM3PARTW1 UNSPEC_SM3PARTW2])
1556
1557;; Iterators for fp16 operations
1558
1559(define_int_iterator VFMLA16_LOW [UNSPEC_FMLAL UNSPEC_FMLSL])
1560
1561(define_int_iterator VFMLA16_HIGH [UNSPEC_FMLAL2 UNSPEC_FMLSL2])
1562
43cacb12
RS		 1563(define_int_iterator UNPACK [UNSPEC_UNPACKSHI UNSPEC_UNPACKUHI
1564 UNSPEC_UNPACKSLO UNSPEC_UNPACKULO])
1565
1566(define_int_iterator UNPACK_UNSIGNED [UNSPEC_UNPACKULO UNSPEC_UNPACKUHI])
1567
11e9443f
RS		 1568(define_int_iterator MUL_HIGHPART [UNSPEC_SMUL_HIGHPART UNSPEC_UMUL_HIGHPART])
1569
0d2b3bca 1570(define_int_iterator SVE_COND_FP_BINARY [UNSPEC_COND_ADD UNSPEC_COND_SUB
6c4fd4a9 1571 UNSPEC_COND_MUL UNSPEC_COND_DIV
0d2b3bca
RS		 1572 UNSPEC_COND_MAX UNSPEC_COND_MIN])
1573
b41d1f6e
RS		 1574(define_int_iterator SVE_COND_FP_TERNARY [UNSPEC_COND_FMLA
1575 UNSPEC_COND_FMLS
1576 UNSPEC_COND_FNMLA
1577 UNSPEC_COND_FNMLS])
1578
43cacb12
RS		 1579(define_int_iterator SVE_COND_FP_CMP [UNSPEC_COND_LT UNSPEC_COND_LE
1580 UNSPEC_COND_EQ UNSPEC_COND_NE
1581 UNSPEC_COND_GE UNSPEC_COND_GT])
1582
d81cb613
MW		 1583;; Iterators for atomic operations.
1584
1585(define_int_iterator ATOMIC_LDOP
1586 [UNSPECV_ATOMIC_LDOP_OR UNSPECV_ATOMIC_LDOP_BIC
1587 UNSPECV_ATOMIC_LDOP_XOR UNSPECV_ATOMIC_LDOP_PLUS])
1588
1589(define_int_attr atomic_ldop
1590 [(UNSPECV_ATOMIC_LDOP_OR "set") (UNSPECV_ATOMIC_LDOP_BIC "clr")
1591 (UNSPECV_ATOMIC_LDOP_XOR "eor") (UNSPECV_ATOMIC_LDOP_PLUS "add")])
1592
43e9d192
IB		 1593;; -------------------------------------------------------------------
1594;; Int Iterators Attributes.
1595;; -------------------------------------------------------------------
43cacb12
RS		 1596
1597;; The optab associated with an operation. Note that for ANDF, IORF
1598;; and XORF, the optab pattern is not actually defined; we just use this
1599;; name for consistency with the integer patterns.
1600(define_int_attr optab [(UNSPEC_ANDF "and")
1601 (UNSPEC_IORF "ior")
898f07b0
RS		 1602 (UNSPEC_XORF "xor")
1603 (UNSPEC_ANDV "and")
1604 (UNSPEC_IORV "ior")
0972596e
RS		 1605 (UNSPEC_XORV "xor")
1606 (UNSPEC_COND_ADD "add")
0d2b3bca 1607 (UNSPEC_COND_SUB "sub")
6c4fd4a9
RS		 1608 (UNSPEC_COND_MUL "mul")
1609 (UNSPEC_COND_DIV "div")
0d2b3bca 1610 (UNSPEC_COND_MAX "smax")
b41d1f6e
RS		 1611 (UNSPEC_COND_MIN "smin")
1612 (UNSPEC_COND_FMLA "fma")
1613 (UNSPEC_COND_FMLS "fnma")
1614 (UNSPEC_COND_FNMLA "fnms")
1615 (UNSPEC_COND_FNMLS "fms")])
43cacb12 1616
998eaf97
JG		 1617(define_int_attr maxmin_uns [(UNSPEC_UMAXV "umax")
1618 (UNSPEC_UMINV "umin")
1619 (UNSPEC_SMAXV "smax")
1620 (UNSPEC_SMINV "smin")
1621 (UNSPEC_FMAX "smax_nan")
1622 (UNSPEC_FMAXNMV "smax")
1623 (UNSPEC_FMAXV "smax_nan")
1624 (UNSPEC_FMIN "smin_nan")
1625 (UNSPEC_FMINNMV "smin")
1efafef3
TC		 1626 (UNSPEC_FMINV "smin_nan")
1627 (UNSPEC_FMAXNM "fmax")
1628 (UNSPEC_FMINNM "fmin")])
998eaf97
JG		 1629
1630(define_int_attr maxmin_uns_op [(UNSPEC_UMAXV "umax")
1631 (UNSPEC_UMINV "umin")
1632 (UNSPEC_SMAXV "smax")
1633 (UNSPEC_SMINV "smin")
1634 (UNSPEC_FMAX "fmax")
1635 (UNSPEC_FMAXNMV "fmaxnm")
1636 (UNSPEC_FMAXV "fmax")
1637 (UNSPEC_FMIN "fmin")
1638 (UNSPEC_FMINNMV "fminnm")
1efafef3
TC		 1639 (UNSPEC_FMINV "fmin")
1640 (UNSPEC_FMAXNM "fmaxnm")
1641 (UNSPEC_FMINNM "fminnm")])
202d0c11 1642
898f07b0
RS		 1643(define_int_attr bit_reduc_op [(UNSPEC_ANDV "andv")
1644 (UNSPEC_IORV "orv")
1645 (UNSPEC_XORV "eorv")])
1646
43cacb12
RS		 1647;; The SVE logical instruction that implements an unspec.
1648(define_int_attr logicalf_op [(UNSPEC_ANDF "and")
1649 (UNSPEC_IORF "orr")
1650 (UNSPEC_XORF "eor")])
1651
1652;; "s" for signed operations and "u" for unsigned ones.
1653(define_int_attr su [(UNSPEC_UNPACKSHI "s")
1654 (UNSPEC_UNPACKUHI "u")
1655 (UNSPEC_UNPACKSLO "s")
11e9443f
RS		 1656 (UNSPEC_UNPACKULO "u")
1657 (UNSPEC_SMUL_HIGHPART "s")
1658 (UNSPEC_UMUL_HIGHPART "u")])
43cacb12 1659
43e9d192
IB		 1660(define_int_attr sur [(UNSPEC_SHADD "s") (UNSPEC_UHADD "u")
1661 (UNSPEC_SRHADD "sr") (UNSPEC_URHADD "ur")
1662 (UNSPEC_SHSUB "s") (UNSPEC_UHSUB "u")
1663 (UNSPEC_SRHSUB "sr") (UNSPEC_URHSUB "ur")
1664 (UNSPEC_ADDHN "") (UNSPEC_RADDHN "r")
75add2d0
KT		 1665 (UNSPEC_SABAL "s") (UNSPEC_UABAL "u")
1666 (UNSPEC_SABDL2 "s") (UNSPEC_UABDL2 "u")
1667 (UNSPEC_SADALP "s") (UNSPEC_UADALP "u")
43e9d192
IB		 1668 (UNSPEC_SUBHN "") (UNSPEC_RSUBHN "r")
1669 (UNSPEC_ADDHN2 "") (UNSPEC_RADDHN2 "r")
1670 (UNSPEC_SUBHN2 "") (UNSPEC_RSUBHN2 "r")
1671 (UNSPEC_SQXTN "s") (UNSPEC_UQXTN "u")
1672 (UNSPEC_USQADD "us") (UNSPEC_SUQADD "su")
1673 (UNSPEC_SSLI "s") (UNSPEC_USLI "u")
1674 (UNSPEC_SSRI "s") (UNSPEC_USRI "u")
1675 (UNSPEC_USRA "u") (UNSPEC_SSRA "s")
1676 (UNSPEC_URSRA "ur") (UNSPEC_SRSRA "sr")
1677 (UNSPEC_URSHR "ur") (UNSPEC_SRSHR "sr")
1678 (UNSPEC_SQSHLU "s") (UNSPEC_SQSHL "s")
1679 (UNSPEC_UQSHL "u")
1680 (UNSPEC_SQSHRUN "s") (UNSPEC_SQRSHRUN "s")
1681 (UNSPEC_SQSHRN "s") (UNSPEC_UQSHRN "u")
1682 (UNSPEC_SQRSHRN "s") (UNSPEC_UQRSHRN "u")
1683 (UNSPEC_USHL "u") (UNSPEC_SSHL "s")
1684 (UNSPEC_USHLL "u") (UNSPEC_SSHLL "s")
1685 (UNSPEC_URSHL "ur") (UNSPEC_SRSHL "sr")
1686 (UNSPEC_UQRSHL "u") (UNSPEC_SQRSHL "s")
7a08d813 1687 (UNSPEC_SDOT "s") (UNSPEC_UDOT "u")
43e9d192
IB		 1688])
1689
1690(define_int_attr r [(UNSPEC_SQDMULH "") (UNSPEC_SQRDMULH "r")
1691 (UNSPEC_SQSHRUN "") (UNSPEC_SQRSHRUN "r")
1692 (UNSPEC_SQSHRN "") (UNSPEC_UQSHRN "")
1693 (UNSPEC_SQRSHRN "r") (UNSPEC_UQRSHRN "r")
1694 (UNSPEC_SQSHL "") (UNSPEC_UQSHL "")
1695 (UNSPEC_SQRSHL "r")(UNSPEC_UQRSHL "r")
1696])
1697
1698(define_int_attr lr [(UNSPEC_SSLI "l") (UNSPEC_USLI "l")
1699 (UNSPEC_SSRI "r") (UNSPEC_USRI "r")])
1700
1701(define_int_attr u [(UNSPEC_SQSHLU "u") (UNSPEC_SQSHL "") (UNSPEC_UQSHL "")
1702 (UNSPEC_SQSHRUN "u") (UNSPEC_SQRSHRUN "u")
42addb5a
RS		 1703 (UNSPEC_SQSHRN "") (UNSPEC_UQSHRN "")
1704 (UNSPEC_SQRSHRN "") (UNSPEC_UQRSHRN "")
1705 (UNSPEC_SHADD "") (UNSPEC_UHADD "u")
1706 (UNSPEC_SRHADD "") (UNSPEC_URHADD "u")])
43e9d192
IB		 1707
1708(define_int_attr addsub [(UNSPEC_SHADD "add")
1709 (UNSPEC_UHADD "add")
1710 (UNSPEC_SRHADD "add")
1711 (UNSPEC_URHADD "add")
1712 (UNSPEC_SHSUB "sub")
1713 (UNSPEC_UHSUB "sub")
1714 (UNSPEC_SRHSUB "sub")
1715 (UNSPEC_URHSUB "sub")
1716 (UNSPEC_ADDHN "add")
1717 (UNSPEC_SUBHN "sub")
1718 (UNSPEC_RADDHN "add")
1719 (UNSPEC_RSUBHN "sub")
1720 (UNSPEC_ADDHN2 "add")
1721 (UNSPEC_SUBHN2 "sub")
1722 (UNSPEC_RADDHN2 "add")
1723 (UNSPEC_RSUBHN2 "sub")])
1724
cb23a30c
JG		 1725(define_int_attr offsetlr [(UNSPEC_SSLI "") (UNSPEC_USLI "")
1726 (UNSPEC_SSRI "offset_")
1727 (UNSPEC_USRI "offset_")])
43e9d192 1728
42fc9a7f
JG		 1729;; Standard pattern names for floating-point rounding instructions.
1730(define_int_attr frint_pattern [(UNSPEC_FRINTZ "btrunc")
1731 (UNSPEC_FRINTP "ceil")
1732 (UNSPEC_FRINTM "floor")
1733 (UNSPEC_FRINTI "nearbyint")
1734 (UNSPEC_FRINTX "rint")
0659ce6f
JG		 1735 (UNSPEC_FRINTA "round")
1736 (UNSPEC_FRINTN "frintn")])
42fc9a7f
JG		 1737
1738;; frint suffix for floating-point rounding instructions.
1739(define_int_attr frint_suffix [(UNSPEC_FRINTZ "z") (UNSPEC_FRINTP "p")
1740 (UNSPEC_FRINTM "m") (UNSPEC_FRINTI "i")
0659ce6f
JG		 1741 (UNSPEC_FRINTX "x") (UNSPEC_FRINTA "a")
1742 (UNSPEC_FRINTN "n")])
42fc9a7f
JG		 1743
1744(define_int_attr fcvt_pattern [(UNSPEC_FRINTZ "btrunc") (UNSPEC_FRINTA "round")
ce966824
JG		 1745 (UNSPEC_FRINTP "ceil") (UNSPEC_FRINTM "floor")
1746 (UNSPEC_FRINTN "frintn")])
42fc9a7f 1747
3f598afe
JW		 1748(define_int_attr fcvt_fixed_insn [(UNSPEC_SCVTF "scvtf")
1749 (UNSPEC_UCVTF "ucvtf")
1750 (UNSPEC_FCVTZS "fcvtzs")
1751 (UNSPEC_FCVTZU "fcvtzu")])
1752
db58fd89
JW		 1753;; Pointer authentication mnemonic prefix.
1754(define_int_attr pauth_mnem_prefix [(UNSPEC_PACISP "paci")
1755 (UNSPEC_AUTISP "auti")
1756 (UNSPEC_PACI1716 "paci")
1757 (UNSPEC_AUTI1716 "auti")])
1758
1759;; Pointer authentication HINT number for NOP space instructions using A Key.
1760(define_int_attr pauth_hint_num_a [(UNSPEC_PACISP "25")
1761 (UNSPEC_AUTISP "29")
1762 (UNSPEC_PACI1716 "8")
1763 (UNSPEC_AUTI1716 "12")])
1764
cc4d934f
JG		 1765(define_int_attr perm_insn [(UNSPEC_ZIP1 "zip") (UNSPEC_ZIP2 "zip")
1766 (UNSPEC_TRN1 "trn") (UNSPEC_TRN2 "trn")
1767 (UNSPEC_UZP1 "uzp") (UNSPEC_UZP2 "uzp")])
1768
923fcec3
AL		 1769; op code for REV instructions (size within which elements are reversed).
1770(define_int_attr rev_op [(UNSPEC_REV64 "64") (UNSPEC_REV32 "32")
1771 (UNSPEC_REV16 "16")])
1772
cc4d934f
JG		 1773(define_int_attr perm_hilo [(UNSPEC_ZIP1 "1") (UNSPEC_ZIP2 "2")
1774 (UNSPEC_TRN1 "1") (UNSPEC_TRN2 "2")
43cacb12
RS		 1775 (UNSPEC_UZP1 "1") (UNSPEC_UZP2 "2")
1776 (UNSPEC_UNPACKSHI "hi") (UNSPEC_UNPACKUHI "hi")
1777 (UNSPEC_UNPACKSLO "lo") (UNSPEC_UNPACKULO "lo")])
0050faf8 1778
9bfb28ed
RS		 1779;; Return true if the associated optab refers to the high-numbered lanes,
1780;; false if it refers to the low-numbered lanes. The convention is for
1781;; "hi" to refer to the low-numbered lanes (the first ones in memory)
1782;; for big-endian.
1783(define_int_attr hi_lanes_optab [(UNSPEC_UNPACKSHI "!BYTES_BIG_ENDIAN")
1784 (UNSPEC_UNPACKUHI "!BYTES_BIG_ENDIAN")
1785 (UNSPEC_UNPACKSLO "BYTES_BIG_ENDIAN")
1786 (UNSPEC_UNPACKULO "BYTES_BIG_ENDIAN")])
1787
0050faf8 1788(define_int_attr frecp_suffix [(UNSPEC_FRECPE "e") (UNSPEC_FRECPX "x")])
5a7a4e80 1789
5d357f26
KT		 1790(define_int_attr crc_variant [(UNSPEC_CRC32B "crc32b") (UNSPEC_CRC32H "crc32h")
1791 (UNSPEC_CRC32W "crc32w") (UNSPEC_CRC32X "crc32x")
1792 (UNSPEC_CRC32CB "crc32cb") (UNSPEC_CRC32CH "crc32ch")
1793 (UNSPEC_CRC32CW "crc32cw") (UNSPEC_CRC32CX "crc32cx")])
1794
1795(define_int_attr crc_mode [(UNSPEC_CRC32B "QI") (UNSPEC_CRC32H "HI")
1796 (UNSPEC_CRC32W "SI") (UNSPEC_CRC32X "DI")
1797 (UNSPEC_CRC32CB "QI") (UNSPEC_CRC32CH "HI")
1798 (UNSPEC_CRC32CW "SI") (UNSPEC_CRC32CX "DI")])
1799
5a7a4e80
TB		 1800(define_int_attr aes_op [(UNSPEC_AESE "e") (UNSPEC_AESD "d")])
1801(define_int_attr aesmc_op [(UNSPEC_AESMC "mc") (UNSPEC_AESIMC "imc")])
30442682
TB		 1802
1803(define_int_attr sha1_op [(UNSPEC_SHA1C "c") (UNSPEC_SHA1P "p")
1804 (UNSPEC_SHA1M "m")])
b9cb0a44
TB		 1805
1806(define_int_attr sha256_op [(UNSPEC_SHA256H "") (UNSPEC_SHA256H2 "2")])
57b26d65
MW		 1807
1808(define_int_attr rdma_as [(UNSPEC_SQRDMLAH "a") (UNSPEC_SQRDMLSH "s")])
27086ea3
MC		 1809
1810(define_int_attr sha512_op [(UNSPEC_SHA512H "") (UNSPEC_SHA512H2 "2")])
1811
1812(define_int_attr sm3tt_op [(UNSPEC_SM3TT1A "1a") (UNSPEC_SM3TT1B "1b")
1813 (UNSPEC_SM3TT2A "2a") (UNSPEC_SM3TT2B "2b")])
1814
1815(define_int_attr sm3part_op [(UNSPEC_SM3PARTW1 "1") (UNSPEC_SM3PARTW2 "2")])
1816
1817(define_int_attr f16mac1 [(UNSPEC_FMLAL "a") (UNSPEC_FMLSL "s")
1818 (UNSPEC_FMLAL2 "a") (UNSPEC_FMLSL2 "s")])
43cacb12
RS		 1819
1820;; The condition associated with an UNSPEC_COND_<xx>.
1821(define_int_attr cmp_op [(UNSPEC_COND_LT "lt")
1822 (UNSPEC_COND_LE "le")
1823 (UNSPEC_COND_EQ "eq")
1824 (UNSPEC_COND_NE "ne")
1825 (UNSPEC_COND_GE "ge")
f22d7973 1826 (UNSPEC_COND_GT "gt")])
0972596e 1827
0972596e 1828(define_int_attr sve_fp_op [(UNSPEC_COND_ADD "fadd")
0d2b3bca 1829 (UNSPEC_COND_SUB "fsub")
6c4fd4a9
RS		 1830 (UNSPEC_COND_MUL "fmul")
1831 (UNSPEC_COND_DIV "fdiv")
0d2b3bca
RS		 1832 (UNSPEC_COND_MAX "fmaxnm")
1833 (UNSPEC_COND_MIN "fminnm")])
1834
a08acce8
RH		 1835(define_int_attr sve_fp_op_rev [(UNSPEC_COND_ADD "fadd")
1836 (UNSPEC_COND_SUB "fsubr")
1837 (UNSPEC_COND_MUL "fmul")
1838 (UNSPEC_COND_DIV "fdivr")
1839 (UNSPEC_COND_MAX "fmaxnm")
1840 (UNSPEC_COND_MIN "fminnm")])
1841
b41d1f6e
RS		 1842(define_int_attr sve_fmla_op [(UNSPEC_COND_FMLA "fmla")
1843 (UNSPEC_COND_FMLS "fmls")
1844 (UNSPEC_COND_FNMLA "fnmla")
1845 (UNSPEC_COND_FNMLS "fnmls")])
1846
1847(define_int_attr sve_fmad_op [(UNSPEC_COND_FMLA "fmad")
1848 (UNSPEC_COND_FMLS "fmsb")
1849 (UNSPEC_COND_FNMLA "fnmad")
1850 (UNSPEC_COND_FNMLS "fnmsb")])
1851
0d2b3bca
RS		 1852(define_int_attr commutative [(UNSPEC_COND_ADD "true")
1853 (UNSPEC_COND_SUB "false")
6c4fd4a9
RS		 1854 (UNSPEC_COND_MUL "true")
1855 (UNSPEC_COND_DIV "false")
0d2b3bca
RS		 1856 (UNSPEC_COND_MIN "true")
1857 (UNSPEC_COND_MAX "true")])
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