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[AArch64] Tweak sve/vcond_6.c test
[thirdparty/gcc.git] / gcc / config / aarch64 / iterators.md
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43e9d192 1;; Machine description for AArch64 architecture.
85ec4feb 2;; Copyright (C) 2009-2018 Free Software Foundation, Inc.
43e9d192
IB		 3;; Contributed by ARM Ltd.
4;;
5;; This file is part of GCC.
6;;
7;; GCC is free software; you can redistribute it and/or modify it
8;; under the terms of the GNU General Public License as published by
9;; the Free Software Foundation; either version 3, or (at your option)
10;; any later version.
11;;
12;; GCC is distributed in the hope that it will be useful, but
13;; WITHOUT ANY WARRANTY; without even the implied warranty of
14;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15;; General Public License for more details.
16;;
17;; You should have received a copy of the GNU General Public License
18;; along with GCC; see the file COPYING3. If not see
19;; <http://www.gnu.org/licenses/>.
20
21;; -------------------------------------------------------------------
22;; Mode Iterators
23;; -------------------------------------------------------------------
24
25
26;; Iterator for General Purpose Integer registers (32- and 64-bit modes)
27(define_mode_iterator GPI [SI DI])
28
d7f33f07
JW		 29;; Iterator for HI, SI, DI, some instructions can only work on these modes.
30(define_mode_iterator GPI_I16 [(HI "AARCH64_ISA_F16") SI DI])
31
43e9d192
IB		 32;; Iterator for QI and HI modes
33(define_mode_iterator SHORT [QI HI])
34
35;; Iterator for all integer modes (up to 64-bit)
36(define_mode_iterator ALLI [QI HI SI DI])
37
43e9d192
IB		 38;; Iterator for all integer modes that can be extended (up to 64-bit)
39(define_mode_iterator ALLX [QI HI SI])
40
41;; Iterator for General Purpose Floating-point registers (32- and 64-bit modes)
42(define_mode_iterator GPF [SF DF])
43
d7f33f07
JW		 44;; Iterator for all scalar floating point modes (HF, SF, DF)
45(define_mode_iterator GPF_F16 [(HF "AARCH64_ISA_F16") SF DF])
46
90e6443f
TC		 47;; Iterator for all scalar floating point modes (HF, SF, DF)
48(define_mode_iterator GPF_HF [HF SF DF])
49
09fcd8e1
RR		 50;; Iterator for all scalar floating point modes (HF, SF, DF and TF)
51(define_mode_iterator GPF_TF_F16 [HF SF DF TF])
c2ec330c 52
922f9c25
AL		 53;; Double vector modes.
54(define_mode_iterator VDF [V2SF V4HF])
55
b4f50fd4
RR		 56;; Iterator for all scalar floating point modes (SF, DF and TF)
57(define_mode_iterator GPF_TF [SF DF TF])
58
43cacb12 59;; Integer Advanced SIMD modes.
43e9d192
IB		 60(define_mode_iterator VDQ_I [V8QI V16QI V4HI V8HI V2SI V4SI V2DI])
61
43cacb12 62;; Advanced SIMD and scalar, 64 & 128-bit container, all integer modes.
43e9d192
IB		 63(define_mode_iterator VSDQ_I [V8QI V16QI V4HI V8HI V2SI V4SI V2DI QI HI SI DI])
64
43cacb12
RS		 65;; Advanced SIMD and scalar, 64 & 128-bit container: all Advanced SIMD
66;; integer modes; 64-bit scalar integer mode.
43e9d192
IB		 67(define_mode_iterator VSDQ_I_DI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI DI])
68
69;; Double vector modes.
71a11456 70(define_mode_iterator VD [V8QI V4HI V4HF V2SI V2SF])
43e9d192 71
43cacb12 72;; Advanced SIMD, 64-bit container, all integer modes.
43e9d192
IB		 73(define_mode_iterator VD_BHSI [V8QI V4HI V2SI])
74
75;; 128 and 64-bit container; 8, 16, 32-bit vector integer modes
76(define_mode_iterator VDQ_BHSI [V8QI V16QI V4HI V8HI V2SI V4SI])
77
78;; Quad vector modes.
71a11456 79(define_mode_iterator VQ [V16QI V8HI V4SI V2DI V8HF V4SF V2DF])
43e9d192 80
51437269 81;; VQ without 2 element modes.
71a11456 82(define_mode_iterator VQ_NO2E [V16QI V8HI V4SI V8HF V4SF])
51437269
GW		 83
84;; Quad vector with only 2 element modes.
85(define_mode_iterator VQ_2E [V2DI V2DF])
86
28514dda
YZ		 87;; This mode iterator allows :P to be used for patterns that operate on
88;; addresses in different modes. In LP64, only DI will match, while in
89;; ILP32, either can match.
90(define_mode_iterator P [(SI "ptr_mode == SImode || Pmode == SImode")
91 (DI "ptr_mode == DImode || Pmode == DImode")])
92
43e9d192
IB		 93;; This mode iterator allows :PTR to be used for patterns that operate on
94;; pointer-sized quantities. Exactly one of the two alternatives will match.
28514dda 95(define_mode_iterator PTR [(SI "ptr_mode == SImode") (DI "ptr_mode == DImode")])
43e9d192 96
43cacb12 97;; Advanced SIMD Float modes suitable for moving, loading and storing.
862abc04
AL		 98(define_mode_iterator VDQF_F16 [V4HF V8HF V2SF V4SF V2DF])
99
43cacb12 100;; Advanced SIMD Float modes.
43e9d192 101(define_mode_iterator VDQF [V2SF V4SF V2DF])
daef0a8c
JW		 102(define_mode_iterator VHSDF [(V4HF "TARGET_SIMD_F16INST")
103 (V8HF "TARGET_SIMD_F16INST")
104 V2SF V4SF V2DF])
43e9d192 105
43cacb12 106;; Advanced SIMD Float modes, and DF.
daef0a8c
JW		 107(define_mode_iterator VHSDF_DF [(V4HF "TARGET_SIMD_F16INST")
108 (V8HF "TARGET_SIMD_F16INST")
109 V2SF V4SF V2DF DF])
d7f33f07
JW		 110(define_mode_iterator VHSDF_HSDF [(V4HF "TARGET_SIMD_F16INST")
111 (V8HF "TARGET_SIMD_F16INST")
112 V2SF V4SF V2DF
113 (HF "TARGET_SIMD_F16INST")
114 SF DF])
f421c516 115
43cacb12 116;; Advanced SIMD single Float modes.
828e70c1
JG		 117(define_mode_iterator VDQSF [V2SF V4SF])
118
03873eb9
AL		 119;; Quad vector Float modes with half/single elements.
120(define_mode_iterator VQ_HSF [V8HF V4SF])
121
fc21784d
JG		 122;; Modes suitable to use as the return type of a vcond expression.
123(define_mode_iterator VDQF_COND [V2SF V2SI V4SF V4SI V2DF V2DI])
124
43cacb12 125;; All scalar and Advanced SIMD Float modes.
889b9412
JG		 126(define_mode_iterator VALLF [V2SF V4SF V2DF SF DF])
127
43cacb12 128;; Advanced SIMD Float modes with 2 elements.
43e9d192
IB		 129(define_mode_iterator V2F [V2SF V2DF])
130
43cacb12 131;; All Advanced SIMD modes on which we support any arithmetic operations.
43e9d192
IB		 132(define_mode_iterator VALL [V8QI V16QI V4HI V8HI V2SI V4SI V2DI V2SF V4SF V2DF])
133
43cacb12 134;; All Advanced SIMD modes suitable for moving, loading, and storing.
71a11456
AL		 135(define_mode_iterator VALL_F16 [V8QI V16QI V4HI V8HI V2SI V4SI V2DI
136 V4HF V8HF V2SF V4SF V2DF])
137
88119b46
KT		 138;; The VALL_F16 modes except the 128-bit 2-element ones.
139(define_mode_iterator VALL_F16_NO_V2Q [V8QI V16QI V4HI V8HI V2SI V4SI
140 V4HF V8HF V2SF V4SF])
141
43cacb12 142;; All Advanced SIMD modes barring HF modes, plus DI.
a50344cb
TB		 143(define_mode_iterator VALLDI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI V2SF V4SF V2DF DI])
144
43cacb12 145;; All Advanced SIMD modes and DI.
71a11456
AL		 146(define_mode_iterator VALLDI_F16 [V8QI V16QI V4HI V8HI V2SI V4SI V2DI
147 V4HF V8HF V2SF V4SF V2DF DI])
148
43cacb12 149;; All Advanced SIMD modes, plus DI and DF.
46e778c4 150(define_mode_iterator VALLDIF [V8QI V16QI V4HI V8HI V2SI V4SI
7c369485 151 V2DI V4HF V8HF V2SF V4SF V2DF DI DF])
46e778c4 152
43cacb12 153;; Advanced SIMD modes for Integer reduction across lanes.
92835317
TB		 154(define_mode_iterator VDQV [V8QI V16QI V4HI V8HI V4SI V2DI])
155
43cacb12 156;; Advanced SIMD modes (except V2DI) for Integer reduction across lanes.
92835317 157(define_mode_iterator VDQV_S [V8QI V16QI V4HI V8HI V4SI])
43e9d192
IB		 158
159;; All double integer narrow-able modes.
160(define_mode_iterator VDN [V4HI V2SI DI])
161
162;; All quad integer narrow-able modes.
163(define_mode_iterator VQN [V8HI V4SI V2DI])
164
43cacb12
RS		 165;; Advanced SIMD and scalar 128-bit container: narrowable 16, 32, 64-bit
166;; integer modes
43e9d192
IB		 167(define_mode_iterator VSQN_HSDI [V8HI V4SI V2DI HI SI DI])
168
169;; All quad integer widen-able modes.
170(define_mode_iterator VQW [V16QI V8HI V4SI])
171
172;; Double vector modes for combines.
7c369485 173(define_mode_iterator VDC [V8QI V4HI V4HF V2SI V2SF DI DF])
43e9d192 174
43cacb12 175;; Advanced SIMD modes except double int.
43e9d192 176(define_mode_iterator VDQIF [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF V2DF])
703bbcdf
JW		 177(define_mode_iterator VDQIF_F16 [V8QI V16QI V4HI V8HI V2SI V4SI
178 V4HF V8HF V2SF V4SF V2DF])
43e9d192 179
43cacb12 180;; Advanced SIMD modes for S type.
58a3bd25
FY		 181(define_mode_iterator VDQ_SI [V2SI V4SI])
182
43cacb12 183;; Advanced SIMD modes for S and D.
2644d4d9
JW		 184(define_mode_iterator VDQ_SDI [V2SI V4SI V2DI])
185
43cacb12 186;; Advanced SIMD modes for H, S and D.
33d72b63
JW		 187(define_mode_iterator VDQ_HSDI [(V4HI "TARGET_SIMD_F16INST")
188 (V8HI "TARGET_SIMD_F16INST")
189 V2SI V4SI V2DI])
190
43cacb12 191;; Scalar and Advanced SIMD modes for S and D.
2644d4d9
JW		 192(define_mode_iterator VSDQ_SDI [V2SI V4SI V2DI SI DI])
193
43cacb12 194;; Scalar and Advanced SIMD modes for S and D, Advanced SIMD modes for H.
33d72b63
JW		 195(define_mode_iterator VSDQ_HSDI [(V4HI "TARGET_SIMD_F16INST")
196 (V8HI "TARGET_SIMD_F16INST")
68ad28c3
JW		 197 V2SI V4SI V2DI
198 (HI "TARGET_SIMD_F16INST")
199 SI DI])
33d72b63 200
43cacb12 201;; Advanced SIMD modes for Q and H types.
66adb8eb
JG		 202(define_mode_iterator VDQQH [V8QI V16QI V4HI V8HI])
203
43cacb12 204;; Advanced SIMD modes for H and S types.
43e9d192
IB		 205(define_mode_iterator VDQHS [V4HI V8HI V2SI V4SI])
206
43cacb12 207;; Advanced SIMD modes for H, S and D types.
c7f28cd5
KT		 208(define_mode_iterator VDQHSD [V4HI V8HI V2SI V4SI V2DI])
209
43cacb12 210;; Advanced SIMD and scalar integer modes for H and S.
43e9d192
IB		 211(define_mode_iterator VSDQ_HSI [V4HI V8HI V2SI V4SI HI SI])
212
43cacb12 213;; Advanced SIMD and scalar 64-bit container: 16, 32-bit integer modes.
43e9d192
IB		 214(define_mode_iterator VSD_HSI [V4HI V2SI HI SI])
215
43cacb12 216;; Advanced SIMD 64-bit container: 16, 32-bit integer modes.
43e9d192
IB		 217(define_mode_iterator VD_HSI [V4HI V2SI])
218
219;; Scalar 64-bit container: 16, 32-bit integer modes
220(define_mode_iterator SD_HSI [HI SI])
221
43cacb12 222;; Advanced SIMD 64-bit container: 16, 32-bit integer modes.
43e9d192
IB		 223(define_mode_iterator VQ_HSI [V8HI V4SI])
224
225;; All byte modes.
226(define_mode_iterator VB [V8QI V16QI])
227
5e32e83b
JW		 228;; 2 and 4 lane SI modes.
229(define_mode_iterator VS [V2SI V4SI])
230
43e9d192
IB		 231(define_mode_iterator TX [TI TF])
232
43cacb12 233;; Advanced SIMD opaque structure modes.
43e9d192
IB		 234(define_mode_iterator VSTRUCT [OI CI XI])
235
236;; Double scalar modes
237(define_mode_iterator DX [DI DF])
238
43cacb12 239;; Modes available for Advanced SIMD <f>mul lane operations.
ab2e8f01
JW		 240(define_mode_iterator VMUL [V4HI V8HI V2SI V4SI
241 (V4HF "TARGET_SIMD_F16INST")
242 (V8HF "TARGET_SIMD_F16INST")
243 V2SF V4SF V2DF])
779aea46 244
43cacb12
RS		 245;; Modes available for Advanced SIMD <f>mul lane operations changing lane
246;; count.
779aea46
JG		 247(define_mode_iterator VMUL_CHANGE_NLANES [V4HI V8HI V2SI V4SI V2SF V4SF])
248
43cacb12
RS		 249;; All SVE vector modes.
250(define_mode_iterator SVE_ALL [VNx16QI VNx8HI VNx4SI VNx2DI
251 VNx8HF VNx4SF VNx2DF])
252
9f4cbab8
RS		 253;; All SVE vector structure modes.
254(define_mode_iterator SVE_STRUCT [VNx32QI VNx16HI VNx8SI VNx4DI
255 VNx16HF VNx8SF VNx4DF
256 VNx48QI VNx24HI VNx12SI VNx6DI
257 VNx24HF VNx12SF VNx6DF
258 VNx64QI VNx32HI VNx16SI VNx8DI
259 VNx32HF VNx16SF VNx8DF])
260
43cacb12
RS		 261;; All SVE vector modes that have 8-bit or 16-bit elements.
262(define_mode_iterator SVE_BH [VNx16QI VNx8HI VNx8HF])
263
264;; All SVE vector modes that have 8-bit, 16-bit or 32-bit elements.
265(define_mode_iterator SVE_BHS [VNx16QI VNx8HI VNx4SI VNx8HF VNx4SF])
266
267;; All SVE integer vector modes that have 8-bit, 16-bit or 32-bit elements.
268(define_mode_iterator SVE_BHSI [VNx16QI VNx8HI VNx4SI])
269
270;; All SVE integer vector modes that have 16-bit, 32-bit or 64-bit elements.
271(define_mode_iterator SVE_HSDI [VNx16QI VNx8HI VNx4SI])
272
273;; All SVE floating-point vector modes that have 16-bit or 32-bit elements.
274(define_mode_iterator SVE_HSF [VNx8HF VNx4SF])
275
276;; All SVE vector modes that have 32-bit or 64-bit elements.
277(define_mode_iterator SVE_SD [VNx4SI VNx2DI VNx4SF VNx2DF])
278
bfaa08b7
RS		 279;; All SVE vector modes that have 32-bit elements.
280(define_mode_iterator SVE_S [VNx4SI VNx4SF])
281
282;; All SVE vector modes that have 64-bit elements.
283(define_mode_iterator SVE_D [VNx2DI VNx2DF])
284
43cacb12
RS		 285;; All SVE integer vector modes that have 32-bit or 64-bit elements.
286(define_mode_iterator SVE_SDI [VNx4SI VNx2DI])
287
288;; All SVE integer vector modes.
289(define_mode_iterator SVE_I [VNx16QI VNx8HI VNx4SI VNx2DI])
290
291;; All SVE floating-point vector modes.
292(define_mode_iterator SVE_F [VNx8HF VNx4SF VNx2DF])
293
294;; All SVE predicate modes.
295(define_mode_iterator PRED_ALL [VNx16BI VNx8BI VNx4BI VNx2BI])
296
297;; SVE predicate modes that control 8-bit, 16-bit or 32-bit elements.
298(define_mode_iterator PRED_BHS [VNx16BI VNx8BI VNx4BI])
299
43e9d192
IB		 300;; ------------------------------------------------------------------
301;; Unspec enumerations for Advance SIMD. These could well go into
302;; aarch64.md but for their use in int_iterators here.
303;; ------------------------------------------------------------------
304
305(define_c_enum "unspec"
306 [
307 UNSPEC_ASHIFT_SIGNED ; Used in aarch-simd.md.
308 UNSPEC_ASHIFT_UNSIGNED ; Used in aarch64-simd.md.
285398d2 309 UNSPEC_ABS ; Used in aarch64-simd.md.
998eaf97
JG		 310 UNSPEC_FMAX ; Used in aarch64-simd.md.
311 UNSPEC_FMAXNMV ; Used in aarch64-simd.md.
43e9d192 312 UNSPEC_FMAXV ; Used in aarch64-simd.md.
998eaf97
JG		 313 UNSPEC_FMIN ; Used in aarch64-simd.md.
314 UNSPEC_FMINNMV ; Used in aarch64-simd.md.
43e9d192
IB		 315 UNSPEC_FMINV ; Used in aarch64-simd.md.
316 UNSPEC_FADDV ; Used in aarch64-simd.md.
f5156c3e 317 UNSPEC_ADDV ; Used in aarch64-simd.md.
43e9d192
IB		 318 UNSPEC_SMAXV ; Used in aarch64-simd.md.
319 UNSPEC_SMINV ; Used in aarch64-simd.md.
320 UNSPEC_UMAXV ; Used in aarch64-simd.md.
321 UNSPEC_UMINV ; Used in aarch64-simd.md.
322 UNSPEC_SHADD ; Used in aarch64-simd.md.
323 UNSPEC_UHADD ; Used in aarch64-simd.md.
324 UNSPEC_SRHADD ; Used in aarch64-simd.md.
325 UNSPEC_URHADD ; Used in aarch64-simd.md.
326 UNSPEC_SHSUB ; Used in aarch64-simd.md.
327 UNSPEC_UHSUB ; Used in aarch64-simd.md.
328 UNSPEC_SRHSUB ; Used in aarch64-simd.md.
329 UNSPEC_URHSUB ; Used in aarch64-simd.md.
330 UNSPEC_ADDHN ; Used in aarch64-simd.md.
331 UNSPEC_RADDHN ; Used in aarch64-simd.md.
332 UNSPEC_SUBHN ; Used in aarch64-simd.md.
333 UNSPEC_RSUBHN ; Used in aarch64-simd.md.
334 UNSPEC_ADDHN2 ; Used in aarch64-simd.md.
335 UNSPEC_RADDHN2 ; Used in aarch64-simd.md.
336 UNSPEC_SUBHN2 ; Used in aarch64-simd.md.
337 UNSPEC_RSUBHN2 ; Used in aarch64-simd.md.
338 UNSPEC_SQDMULH ; Used in aarch64-simd.md.
339 UNSPEC_SQRDMULH ; Used in aarch64-simd.md.
340 UNSPEC_PMUL ; Used in aarch64-simd.md.
496ea87d 341 UNSPEC_FMULX ; Used in aarch64-simd.md.
43e9d192
IB		 342 UNSPEC_USQADD ; Used in aarch64-simd.md.
343 UNSPEC_SUQADD ; Used in aarch64-simd.md.
344 UNSPEC_SQXTUN ; Used in aarch64-simd.md.
345 UNSPEC_SQXTN ; Used in aarch64-simd.md.
346 UNSPEC_UQXTN ; Used in aarch64-simd.md.
347 UNSPEC_SSRA ; Used in aarch64-simd.md.
348 UNSPEC_USRA ; Used in aarch64-simd.md.
349 UNSPEC_SRSRA ; Used in aarch64-simd.md.
350 UNSPEC_URSRA ; Used in aarch64-simd.md.
351 UNSPEC_SRSHR ; Used in aarch64-simd.md.
352 UNSPEC_URSHR ; Used in aarch64-simd.md.
353 UNSPEC_SQSHLU ; Used in aarch64-simd.md.
354 UNSPEC_SQSHL ; Used in aarch64-simd.md.
355 UNSPEC_UQSHL ; Used in aarch64-simd.md.
356 UNSPEC_SQSHRUN ; Used in aarch64-simd.md.
357 UNSPEC_SQRSHRUN ; Used in aarch64-simd.md.
358 UNSPEC_SQSHRN ; Used in aarch64-simd.md.
359 UNSPEC_UQSHRN ; Used in aarch64-simd.md.
360 UNSPEC_SQRSHRN ; Used in aarch64-simd.md.
361 UNSPEC_UQRSHRN ; Used in aarch64-simd.md.
362 UNSPEC_SSHL ; Used in aarch64-simd.md.
363 UNSPEC_USHL ; Used in aarch64-simd.md.
364 UNSPEC_SRSHL ; Used in aarch64-simd.md.
365 UNSPEC_URSHL ; Used in aarch64-simd.md.
366 UNSPEC_SQRSHL ; Used in aarch64-simd.md.
367 UNSPEC_UQRSHL ; Used in aarch64-simd.md.
43e9d192
IB		 368 UNSPEC_SSLI ; Used in aarch64-simd.md.
369 UNSPEC_USLI ; Used in aarch64-simd.md.
370 UNSPEC_SSRI ; Used in aarch64-simd.md.
371 UNSPEC_USRI ; Used in aarch64-simd.md.
372 UNSPEC_SSHLL ; Used in aarch64-simd.md.
373 UNSPEC_USHLL ; Used in aarch64-simd.md.
374 UNSPEC_ADDP ; Used in aarch64-simd.md.
88b08073 375 UNSPEC_TBL ; Used in vector permute patterns.
9371aecc 376 UNSPEC_TBX ; Used in vector permute patterns.
88b08073 377 UNSPEC_CONCAT ; Used in vector permute patterns.
3f8334a5
RS		 378
379 ;; The following permute unspecs are generated directly by
380 ;; aarch64_expand_vec_perm_const, so any changes to the underlying
381 ;; instructions would need a corresponding change there.
cc4d934f
JG		 382 UNSPEC_ZIP1 ; Used in vector permute patterns.
383 UNSPEC_ZIP2 ; Used in vector permute patterns.
384 UNSPEC_UZP1 ; Used in vector permute patterns.
385 UNSPEC_UZP2 ; Used in vector permute patterns.
386 UNSPEC_TRN1 ; Used in vector permute patterns.
387 UNSPEC_TRN2 ; Used in vector permute patterns.
3f8334a5 388 UNSPEC_EXT ; Used in vector permute patterns.
923fcec3
AL		 389 UNSPEC_REV64 ; Used in vector reverse patterns (permute).
390 UNSPEC_REV32 ; Used in vector reverse patterns (permute).
391 UNSPEC_REV16 ; Used in vector reverse patterns (permute).
3f8334a5 392
5a7a4e80
TB		 393 UNSPEC_AESE ; Used in aarch64-simd.md.
394 UNSPEC_AESD ; Used in aarch64-simd.md.
395 UNSPEC_AESMC ; Used in aarch64-simd.md.
396 UNSPEC_AESIMC ; Used in aarch64-simd.md.
30442682
TB		 397 UNSPEC_SHA1C ; Used in aarch64-simd.md.
398 UNSPEC_SHA1M ; Used in aarch64-simd.md.
399 UNSPEC_SHA1P ; Used in aarch64-simd.md.
400 UNSPEC_SHA1H ; Used in aarch64-simd.md.
401 UNSPEC_SHA1SU0 ; Used in aarch64-simd.md.
402 UNSPEC_SHA1SU1 ; Used in aarch64-simd.md.
b9cb0a44
TB		 403 UNSPEC_SHA256H ; Used in aarch64-simd.md.
404 UNSPEC_SHA256H2 ; Used in aarch64-simd.md.
405 UNSPEC_SHA256SU0 ; Used in aarch64-simd.md.
406 UNSPEC_SHA256SU1 ; Used in aarch64-simd.md.
7baa225d
TB		 407 UNSPEC_PMULL ; Used in aarch64-simd.md.
408 UNSPEC_PMULL2 ; Used in aarch64-simd.md.
668046d1 409 UNSPEC_REV_REGLIST ; Used in aarch64-simd.md.
9c004c58 410 UNSPEC_VEC_SHR ; Used in aarch64-simd.md.
57b26d65
MW		 411 UNSPEC_SQRDMLAH ; Used in aarch64-simd.md.
412 UNSPEC_SQRDMLSH ; Used in aarch64-simd.md.
202d0c11
DS		 413 UNSPEC_FMAXNM ; Used in aarch64-simd.md.
414 UNSPEC_FMINNM ; Used in aarch64-simd.md.
7a08d813
TC		 415 UNSPEC_SDOT ; Used in aarch64-simd.md.
416 UNSPEC_UDOT ; Used in aarch64-simd.md.
27086ea3
MC		 417 UNSPEC_SM3SS1 ; Used in aarch64-simd.md.
418 UNSPEC_SM3TT1A ; Used in aarch64-simd.md.
419 UNSPEC_SM3TT1B ; Used in aarch64-simd.md.
420 UNSPEC_SM3TT2A ; Used in aarch64-simd.md.
421 UNSPEC_SM3TT2B ; Used in aarch64-simd.md.
422 UNSPEC_SM3PARTW1 ; Used in aarch64-simd.md.
423 UNSPEC_SM3PARTW2 ; Used in aarch64-simd.md.
424 UNSPEC_SM4E ; Used in aarch64-simd.md.
425 UNSPEC_SM4EKEY ; Used in aarch64-simd.md.
426 UNSPEC_SHA512H ; Used in aarch64-simd.md.
427 UNSPEC_SHA512H2 ; Used in aarch64-simd.md.
428 UNSPEC_SHA512SU0 ; Used in aarch64-simd.md.
429 UNSPEC_SHA512SU1 ; Used in aarch64-simd.md.
430 UNSPEC_FMLAL ; Used in aarch64-simd.md.
431 UNSPEC_FMLSL ; Used in aarch64-simd.md.
432 UNSPEC_FMLAL2 ; Used in aarch64-simd.md.
433 UNSPEC_FMLSL2 ; Used in aarch64-simd.md.
43cacb12 434 UNSPEC_SEL ; Used in aarch64-sve.md.
898f07b0
RS		 435 UNSPEC_ANDV ; Used in aarch64-sve.md.
436 UNSPEC_IORV ; Used in aarch64-sve.md.
437 UNSPEC_XORV ; Used in aarch64-sve.md.
43cacb12
RS		 438 UNSPEC_ANDF ; Used in aarch64-sve.md.
439 UNSPEC_IORF ; Used in aarch64-sve.md.
440 UNSPEC_XORF ; Used in aarch64-sve.md.
11e9443f
RS		 441 UNSPEC_SMUL_HIGHPART ; Used in aarch64-sve.md.
442 UNSPEC_UMUL_HIGHPART ; Used in aarch64-sve.md.
0972596e
RS		 443 UNSPEC_COND_ADD ; Used in aarch64-sve.md.
444 UNSPEC_COND_SUB ; Used in aarch64-sve.md.
445 UNSPEC_COND_SMAX ; Used in aarch64-sve.md.
446 UNSPEC_COND_UMAX ; Used in aarch64-sve.md.
447 UNSPEC_COND_SMIN ; Used in aarch64-sve.md.
448 UNSPEC_COND_UMIN ; Used in aarch64-sve.md.
449 UNSPEC_COND_AND ; Used in aarch64-sve.md.
450 UNSPEC_COND_ORR ; Used in aarch64-sve.md.
451 UNSPEC_COND_EOR ; Used in aarch64-sve.md.
43cacb12
RS		 452 UNSPEC_COND_LT ; Used in aarch64-sve.md.
453 UNSPEC_COND_LE ; Used in aarch64-sve.md.
454 UNSPEC_COND_EQ ; Used in aarch64-sve.md.
455 UNSPEC_COND_NE ; Used in aarch64-sve.md.
456 UNSPEC_COND_GE ; Used in aarch64-sve.md.
457 UNSPEC_COND_GT ; Used in aarch64-sve.md.
458 UNSPEC_COND_LO ; Used in aarch64-sve.md.
459 UNSPEC_COND_LS ; Used in aarch64-sve.md.
460 UNSPEC_COND_HS ; Used in aarch64-sve.md.
461 UNSPEC_COND_HI ; Used in aarch64-sve.md.
462 UNSPEC_COND_UO ; Used in aarch64-sve.md.
463 UNSPEC_LASTB ; Used in aarch64-sve.md.
43e9d192
IB		 464])
465
d81cb613
MW		 466;; ------------------------------------------------------------------
467;; Unspec enumerations for Atomics. They are here so that they can be
468;; used in the int_iterators for atomic operations.
469;; ------------------------------------------------------------------
470
471(define_c_enum "unspecv"
472 [
473 UNSPECV_LX ; Represent a load-exclusive.
474 UNSPECV_SX ; Represent a store-exclusive.
475 UNSPECV_LDA ; Represent an atomic load or load-acquire.
476 UNSPECV_STL ; Represent an atomic store or store-release.
477 UNSPECV_ATOMIC_CMPSW ; Represent an atomic compare swap.
478 UNSPECV_ATOMIC_EXCHG ; Represent an atomic exchange.
479 UNSPECV_ATOMIC_CAS ; Represent an atomic CAS.
480 UNSPECV_ATOMIC_SWP ; Represent an atomic SWP.
481 UNSPECV_ATOMIC_OP ; Represent an atomic operation.
482 UNSPECV_ATOMIC_LDOP ; Represent an atomic load-operation
483 UNSPECV_ATOMIC_LDOP_OR ; Represent an atomic load-or
484 UNSPECV_ATOMIC_LDOP_BIC ; Represent an atomic load-bic
485 UNSPECV_ATOMIC_LDOP_XOR ; Represent an atomic load-xor
486 UNSPECV_ATOMIC_LDOP_PLUS ; Represent an atomic load-add
487])
488
43e9d192
IB		 489;; -------------------------------------------------------------------
490;; Mode attributes
491;; -------------------------------------------------------------------
492
493;; In GPI templates, a string like "%<w>0" will expand to "%w0" in the
494;; 32-bit version and "%x0" in the 64-bit version.
495(define_mode_attr w [(QI "w") (HI "w") (SI "w") (DI "x") (SF "s") (DF "d")])
496
db46a2e6
JG		 497;; The size of access, in bytes.
498(define_mode_attr ldst_sz [(SI "4") (DI "8")])
499;; Likewise for load/store pair.
500(define_mode_attr ldpstp_sz [(SI "8") (DI "16")])
501
0d35c5c2 502;; For inequal width int to float conversion
d7f33f07
JW		 503(define_mode_attr w1 [(HF "w") (SF "w") (DF "x")])
504(define_mode_attr w2 [(HF "x") (SF "x") (DF "w")])
0d35c5c2 505
22be0d08
MC		 506;; For width of fp registers in fcvt instruction
507(define_mode_attr fpw [(DI "s") (SI "d")])
508
2b8568fe
KT		 509(define_mode_attr short_mask [(HI "65535") (QI "255")])
510
051d0e2f
SN		 511;; For constraints used in scalar immediate vector moves
512(define_mode_attr hq [(HI "h") (QI "q")])
513
ef22810a
RH		 514;; For doubling width of an integer mode
515(define_mode_attr DWI [(QI "HI") (HI "SI") (SI "DI") (DI "TI")])
516
22be0d08
MC		 517(define_mode_attr fcvt_change_mode [(SI "df") (DI "sf")])
518
519(define_mode_attr FCVT_CHANGE_MODE [(SI "DF") (DI "SF")])
520
43e9d192
IB		 521;; For scalar usage of vector/FP registers
522(define_mode_attr v [(QI "b") (HI "h") (SI "s") (DI "d")
d7f33f07 523 (HF "h") (SF "s") (DF "d")
43e9d192
IB		 524 (V8QI "") (V16QI "")
525 (V4HI "") (V8HI "")
526 (V2SI "") (V4SI "")
527 (V2DI "") (V2SF "")
daef0a8c
JW		 528 (V4SF "") (V4HF "")
529 (V8HF "") (V2DF "")])
43e9d192
IB		 530
531;; For scalar usage of vector/FP registers, narrowing
532(define_mode_attr vn2 [(QI "") (HI "b") (SI "h") (DI "s")
533 (V8QI "") (V16QI "")
534 (V4HI "") (V8HI "")
535 (V2SI "") (V4SI "")
536 (V2DI "") (V2SF "")
537 (V4SF "") (V2DF "")])
538
539;; For scalar usage of vector/FP registers, widening
540(define_mode_attr vw2 [(DI "") (QI "h") (HI "s") (SI "d")
541 (V8QI "") (V16QI "")
542 (V4HI "") (V8HI "")
543 (V2SI "") (V4SI "")
544 (V2DI "") (V2SF "")
545 (V4SF "") (V2DF "")])
546
89fdc743
IB		 547;; Register Type Name and Vector Arrangement Specifier for when
548;; we are doing scalar for DI and SIMD for SI (ignoring all but
549;; lane 0).
550(define_mode_attr rtn [(DI "d") (SI "")])
551(define_mode_attr vas [(DI "") (SI ".2s")])
552
7ac29c0f
RS		 553;; Map a vector to the number of units in it, if the size of the mode
554;; is constant.
555(define_mode_attr nunits [(V8QI "8") (V16QI "16")
556 (V4HI "4") (V8HI "8")
557 (V2SI "2") (V4SI "4")
558 (V2DI "2")
559 (V4HF "4") (V8HF "8")
560 (V2SF "2") (V4SF "4")
561 (V1DF "1") (V2DF "2")
562 (DI "1") (DF "1")])
563
b187677b
RS		 564;; Map a mode to the number of bits in it, if the size of the mode
565;; is constant.
566(define_mode_attr bitsize [(V8QI "64") (V16QI "128")
567 (V4HI "64") (V8HI "128")
568 (V2SI "64") (V4SI "128")
569 (V2DI "128")])
570
22be0d08
MC		 571;; Map a floating point or integer mode to the appropriate register name prefix
572(define_mode_attr s [(HF "h") (SF "s") (DF "d") (SI "s") (DI "d")])
43e9d192
IB		 573
574;; Give the length suffix letter for a sign- or zero-extension.
575(define_mode_attr size [(QI "b") (HI "h") (SI "w")])
576
577;; Give the number of bits in the mode
578(define_mode_attr sizen [(QI "8") (HI "16") (SI "32") (DI "64")])
579
580;; Give the ordinal of the MSB in the mode
581(define_mode_attr sizem1 [(QI "#7") (HI "#15") (SI "#31") (DI "#63")])
582
583;; Attribute to describe constants acceptable in logical operations
584(define_mode_attr lconst [(SI "K") (DI "L")])
585
43fd192f
MC		 586;; Attribute to describe constants acceptable in logical and operations
587(define_mode_attr lconst2 [(SI "UsO") (DI "UsP")])
588
43e9d192
IB		 589;; Map a mode to a specific constraint character.
590(define_mode_attr cmode [(QI "q") (HI "h") (SI "s") (DI "d")])
591
0603375c
KT		 592;; Map modes to Usg and Usj constraints for SISD right shifts
593(define_mode_attr cmode_simd [(SI "g") (DI "j")])
594
43e9d192
IB		 595(define_mode_attr Vtype [(V8QI "8b") (V16QI "16b")
596 (V4HI "4h") (V8HI "8h")
597 (V2SI "2s") (V4SI "4s")
598 (DI "1d") (DF "1d")
599 (V2DI "2d") (V2SF "2s")
7c369485
AL		 600 (V4SF "4s") (V2DF "2d")
601 (V4HF "4h") (V8HF "8h")])
43e9d192 602
c7f28cd5
KT		 603(define_mode_attr Vrevsuff [(V4HI "16") (V8HI "16") (V2SI "32")
604 (V4SI "32") (V2DI "64")])
605
43e9d192
IB		 606(define_mode_attr Vmtype [(V8QI ".8b") (V16QI ".16b")
607 (V4HI ".4h") (V8HI ".8h")
608 (V2SI ".2s") (V4SI ".4s")
71a11456
AL		 609 (V2DI ".2d") (V4HF ".4h")
610 (V8HF ".8h") (V2SF ".2s")
43e9d192
IB		 611 (V4SF ".4s") (V2DF ".2d")
612 (DI "") (SI "")
613 (HI "") (QI "")
d7f33f07
JW		 614 (TI "") (HF "")
615 (SF "") (DF "")])
43e9d192
IB		 616
617;; Register suffix narrowed modes for VQN.
618(define_mode_attr Vmntype [(V8HI ".8b") (V4SI ".4h")
619 (V2DI ".2s")
620 (DI "") (SI "")
621 (HI "")])
622
623;; Mode-to-individual element type mapping.
43cacb12
RS		 624(define_mode_attr Vetype [(V8QI "b") (V16QI "b") (VNx16QI "b") (VNx16BI "b")
625 (V4HI "h") (V8HI "h") (VNx8HI "h") (VNx8BI "h")
626 (V2SI "s") (V4SI "s") (VNx4SI "s") (VNx4BI "s")
627 (V2DI "d") (VNx2DI "d") (VNx2BI "d")
628 (V4HF "h") (V8HF "h") (VNx8HF "h")
629 (V2SF "s") (V4SF "s") (VNx4SF "s")
630 (V2DF "d") (VNx2DF "d")
d7f33f07 631 (HF "h")
0f686aa9 632 (SF "s") (DF "d")
43e9d192
IB		 633 (QI "b") (HI "h")
634 (SI "s") (DI "d")])
635
43cacb12
RS		 636;; Equivalent of "size" for a vector element.
637(define_mode_attr Vesize [(VNx16QI "b")
9f4cbab8
RS		 638 (VNx8HI "h") (VNx8HF "h")
639 (VNx4SI "w") (VNx4SF "w")
640 (VNx2DI "d") (VNx2DF "d")
641 (VNx32QI "b") (VNx48QI "b") (VNx64QI "b")
642 (VNx16HI "h") (VNx24HI "h") (VNx32HI "h")
643 (VNx16HF "h") (VNx24HF "h") (VNx32HF "h")
644 (VNx8SI "w") (VNx12SI "w") (VNx16SI "w")
645 (VNx8SF "w") (VNx12SF "w") (VNx16SF "w")
646 (VNx4DI "d") (VNx6DI "d") (VNx8DI "d")
647 (VNx4DF "d") (VNx6DF "d") (VNx8DF "d")])
43cacb12 648
daef0a8c
JW		 649;; Vetype is used everywhere in scheduling type and assembly output,
650;; sometimes they are not the same, for example HF modes on some
651;; instructions. stype is defined to represent scheduling type
652;; more accurately.
653(define_mode_attr stype [(V8QI "b") (V16QI "b") (V4HI "s") (V8HI "s")
654 (V2SI "s") (V4SI "s") (V2DI "d") (V4HF "s")
655 (V8HF "s") (V2SF "s") (V4SF "s") (V2DF "d")
656 (HF "s") (SF "s") (DF "d") (QI "b") (HI "s")
657 (SI "s") (DI "d")])
658
43e9d192
IB		 659;; Mode-to-bitwise operation type mapping.
660(define_mode_attr Vbtype [(V8QI "8b") (V16QI "16b")
661 (V4HI "8b") (V8HI "16b")
662 (V2SI "8b") (V4SI "16b")
7c369485
AL		 663 (V2DI "16b") (V4HF "8b")
664 (V8HF "16b") (V2SF "8b")
46e778c4 665 (V4SF "16b") (V2DF "16b")
fe82d1f2
AL		 666 (DI "8b") (DF "8b")
667 (SI "8b")])
43e9d192
IB		 668
669;; Define element mode for each vector mode.
43cacb12
RS		 670(define_mode_attr VEL [(V8QI "QI") (V16QI "QI") (VNx16QI "QI")
671 (V4HI "HI") (V8HI "HI") (VNx8HI "HI")
672 (V2SI "SI") (V4SI "SI") (VNx4SI "SI")
673 (DI "DI") (V2DI "DI") (VNx2DI "DI")
674 (V4HF "HF") (V8HF "HF") (VNx8HF "HF")
675 (V2SF "SF") (V4SF "SF") (VNx4SF "SF")
676 (DF "DF") (V2DF "DF") (VNx2DF "DF")
677 (SI "SI") (HI "HI")
43e9d192
IB		 678 (QI "QI")])
679
ff03930a 680;; Define element mode for each vector mode (lower case).
43cacb12
RS		 681(define_mode_attr Vel [(V8QI "qi") (V16QI "qi") (VNx16QI "qi")
682 (V4HI "hi") (V8HI "hi") (VNx8HI "hi")
683 (V2SI "si") (V4SI "si") (VNx4SI "si")
684 (DI "di") (V2DI "di") (VNx2DI "di")
685 (V4HF "hf") (V8HF "hf") (VNx8HF "hf")
686 (V2SF "sf") (V4SF "sf") (VNx4SF "sf")
687 (V2DF "df") (DF "df") (VNx2DF "df")
ff03930a
JJ		 688 (SI "si") (HI "hi")
689 (QI "qi")])
690
43cacb12
RS		 691;; Element mode with floating-point values replaced by like-sized integers.
692(define_mode_attr VEL_INT [(VNx16QI "QI")
693 (VNx8HI "HI") (VNx8HF "HI")
694 (VNx4SI "SI") (VNx4SF "SI")
695 (VNx2DI "DI") (VNx2DF "DI")])
696
697;; Gives the mode of the 128-bit lowpart of an SVE vector.
698(define_mode_attr V128 [(VNx16QI "V16QI")
699 (VNx8HI "V8HI") (VNx8HF "V8HF")
700 (VNx4SI "V4SI") (VNx4SF "V4SF")
701 (VNx2DI "V2DI") (VNx2DF "V2DF")])
702
703;; ...and again in lower case.
704(define_mode_attr v128 [(VNx16QI "v16qi")
705 (VNx8HI "v8hi") (VNx8HF "v8hf")
706 (VNx4SI "v4si") (VNx4SF "v4sf")
707 (VNx2DI "v2di") (VNx2DF "v2df")])
708
278821f2
KT		 709;; 64-bit container modes the inner or scalar source mode.
710(define_mode_attr VCOND [(HI "V4HI") (SI "V2SI")
711 (V4HI "V4HI") (V8HI "V4HI")
b7d7d917
TB		 712 (V2SI "V2SI") (V4SI "V2SI")
713 (DI "DI") (V2DI "DI")
714 (V2SF "V2SF") (V4SF "V2SF")
715 (V2DF "DF")])
716
278821f2 717;; 128-bit container modes the inner or scalar source mode.
b7d7d917
TB		 718(define_mode_attr VCONQ [(V8QI "V16QI") (V16QI "V16QI")
719 (V4HI "V8HI") (V8HI "V8HI")
720 (V2SI "V4SI") (V4SI "V4SI")
721 (DI "V2DI") (V2DI "V2DI")
71a11456 722 (V4HF "V8HF") (V8HF "V8HF")
b7d7d917
TB		 723 (V2SF "V2SF") (V4SF "V4SF")
724 (V2DF "V2DF") (SI "V4SI")
725 (HI "V8HI") (QI "V16QI")])
726
43e9d192
IB		 727;; Half modes of all vector modes.
728(define_mode_attr VHALF [(V8QI "V4QI") (V16QI "V8QI")
729 (V4HI "V2HI") (V8HI "V4HI")
730 (V2SI "SI") (V4SI "V2SI")
731 (V2DI "DI") (V2SF "SF")
71a11456
AL		 732 (V4SF "V2SF") (V4HF "V2HF")
733 (V8HF "V4HF") (V2DF "DF")])
43e9d192 734
b1b49824
MC		 735;; Half modes of all vector modes, in lower-case.
736(define_mode_attr Vhalf [(V8QI "v4qi") (V16QI "v8qi")
737 (V4HI "v2hi") (V8HI "v4hi")
738 (V2SI "si") (V4SI "v2si")
739 (V2DI "di") (V2SF "sf")
740 (V4SF "v2sf") (V2DF "df")])
741
43e9d192
IB		 742;; Double modes of vector modes.
743(define_mode_attr VDBL [(V8QI "V16QI") (V4HI "V8HI")
71a11456 744 (V4HF "V8HF")
43e9d192
IB		 745 (V2SI "V4SI") (V2SF "V4SF")
746 (SI "V2SI") (DI "V2DI")
747 (DF "V2DF")])
748
922f9c25
AL		 749;; Register suffix for double-length mode.
750(define_mode_attr Vdtype [(V4HF "8h") (V2SF "4s")])
751
43e9d192
IB		 752;; Double modes of vector modes (lower case).
753(define_mode_attr Vdbl [(V8QI "v16qi") (V4HI "v8hi")
7c369485 754 (V4HF "v8hf")
43e9d192 755 (V2SI "v4si") (V2SF "v4sf")
8b033a8a
SN		 756 (SI "v2si") (DI "v2di")
757 (DF "v2df")])
43e9d192 758
b1b49824
MC		 759;; Modes with double-width elements.
760(define_mode_attr VDBLW [(V8QI "V4HI") (V16QI "V8HI")
761 (V4HI "V2SI") (V8HI "V4SI")
762 (V2SI "DI") (V4SI "V2DI")])
763
43e9d192
IB		 764;; Narrowed modes for VDN.
765(define_mode_attr VNARROWD [(V4HI "V8QI") (V2SI "V4HI")
766 (DI "V2SI")])
767
768;; Narrowed double-modes for VQN (Used for XTN).
769(define_mode_attr VNARROWQ [(V8HI "V8QI") (V4SI "V4HI")
770 (V2DI "V2SI")
771 (DI "SI") (SI "HI")
772 (HI "QI")])
773
774;; Narrowed quad-modes for VQN (Used for XTN2).
775(define_mode_attr VNARROWQ2 [(V8HI "V16QI") (V4SI "V8HI")
776 (V2DI "V4SI")])
777
778;; Register suffix narrowed modes for VQN.
779(define_mode_attr Vntype [(V8HI "8b") (V4SI "4h")
780 (V2DI "2s")])
781
782;; Register suffix narrowed modes for VQN.
783(define_mode_attr V2ntype [(V8HI "16b") (V4SI "8h")
784 (V2DI "4s")])
785
786;; Widened modes of vector modes.
43cacb12
RS		 787(define_mode_attr VWIDE [(V8QI "V8HI") (V4HI "V4SI")
788 (V2SI "V2DI") (V16QI "V8HI")
789 (V8HI "V4SI") (V4SI "V2DI")
790 (HI "SI") (SI "DI")
791 (V8HF "V4SF") (V4SF "V2DF")
792 (V4HF "V4SF") (V2SF "V2DF")
793 (VNx8HF "VNx4SF") (VNx4SF "VNx2DF")
794 (VNx16QI "VNx8HI") (VNx8HI "VNx4SI")
795 (VNx4SI "VNx2DI")
796 (VNx16BI "VNx8BI") (VNx8BI "VNx4BI")
797 (VNx4BI "VNx2BI")])
798
799;; Predicate mode associated with VWIDE.
800(define_mode_attr VWIDE_PRED [(VNx8HF "VNx4BI") (VNx4SF "VNx2BI")])
43e9d192 801
03873eb9 802;; Widened modes of vector modes, lowercase
43cacb12
RS		 803(define_mode_attr Vwide [(V2SF "v2df") (V4HF "v4sf")
804 (VNx16QI "vnx8hi") (VNx8HI "vnx4si")
805 (VNx4SI "vnx2di")
806 (VNx8HF "vnx4sf") (VNx4SF "vnx2df")
807 (VNx16BI "vnx8bi") (VNx8BI "vnx4bi")
808 (VNx4BI "vnx2bi")])
03873eb9
AL		 809
810;; Widened mode register suffixes for VD_BHSI/VQW/VQ_HSF.
43e9d192
IB		 811(define_mode_attr Vwtype [(V8QI "8h") (V4HI "4s")
812 (V2SI "2d") (V16QI "8h")
03873eb9
AL		 813 (V8HI "4s") (V4SI "2d")
814 (V8HF "4s") (V4SF "2d")])
43e9d192 815
43cacb12
RS		 816;; SVE vector after widening
817(define_mode_attr Vewtype [(VNx16QI "h")
818 (VNx8HI "s") (VNx8HF "s")
819 (VNx4SI "d") (VNx4SF "d")])
820
43e9d192
IB		 821;; Widened mode register suffixes for VDW/VQW.
822(define_mode_attr Vmwtype [(V8QI ".8h") (V4HI ".4s")
823 (V2SI ".2d") (V16QI ".8h")
824 (V8HI ".4s") (V4SI ".2d")
922f9c25 825 (V4HF ".4s") (V2SF ".2d")
43e9d192
IB		 826 (SI "") (HI "")])
827
03873eb9 828;; Lower part register suffixes for VQW/VQ_HSF.
43e9d192 829(define_mode_attr Vhalftype [(V16QI "8b") (V8HI "4h")
03873eb9
AL		 830 (V4SI "2s") (V8HF "4h")
831 (V4SF "2s")])
43e9d192
IB		 832
833;; Define corresponding core/FP element mode for each vector mode.
43cacb12
RS		 834(define_mode_attr vw [(V8QI "w") (V16QI "w") (VNx16QI "w")
835 (V4HI "w") (V8HI "w") (VNx8HI "w")
836 (V2SI "w") (V4SI "w") (VNx4SI "w")
837 (DI "x") (V2DI "x") (VNx2DI "x")
838 (VNx8HF "h")
839 (V2SF "s") (V4SF "s") (VNx4SF "s")
840 (V2DF "d") (VNx2DF "d")])
43e9d192 841
66adb8eb
JG		 842;; Corresponding core element mode for each vector mode. This is a
843;; variation on <vw> mapping FP modes to GP regs.
43cacb12
RS		 844(define_mode_attr vwcore [(V8QI "w") (V16QI "w") (VNx16QI "w")
845 (V4HI "w") (V8HI "w") (VNx8HI "w")
846 (V2SI "w") (V4SI "w") (VNx4SI "w")
847 (DI "x") (V2DI "x") (VNx2DI "x")
848 (V4HF "w") (V8HF "w") (VNx8HF "w")
849 (V2SF "w") (V4SF "w") (VNx4SF "w")
850 (V2DF "x") (VNx2DF "x")])
66adb8eb 851
43e9d192
IB		 852;; Double vector types for ALLX.
853(define_mode_attr Vallxd [(QI "8b") (HI "4h") (SI "2s")])
854
5f565314
RS		 855;; Mode with floating-point values replaced by like-sized integers.
856(define_mode_attr V_INT_EQUIV [(V8QI "V8QI") (V16QI "V16QI")
857 (V4HI "V4HI") (V8HI "V8HI")
858 (V2SI "V2SI") (V4SI "V4SI")
859 (DI "DI") (V2DI "V2DI")
860 (V4HF "V4HI") (V8HF "V8HI")
861 (V2SF "V2SI") (V4SF "V4SI")
43cacb12
RS		 862 (DF "DI") (V2DF "V2DI")
863 (SF "SI") (HF "HI")
864 (VNx16QI "VNx16QI")
865 (VNx8HI "VNx8HI") (VNx8HF "VNx8HI")
866 (VNx4SI "VNx4SI") (VNx4SF "VNx4SI")
867 (VNx2DI "VNx2DI") (VNx2DF "VNx2DI")
868])
5f565314
RS		 869
870;; Lower case mode with floating-point values replaced by like-sized integers.
871(define_mode_attr v_int_equiv [(V8QI "v8qi") (V16QI "v16qi")
872 (V4HI "v4hi") (V8HI "v8hi")
873 (V2SI "v2si") (V4SI "v4si")
874 (DI "di") (V2DI "v2di")
875 (V4HF "v4hi") (V8HF "v8hi")
876 (V2SF "v2si") (V4SF "v4si")
43cacb12
RS		 877 (DF "di") (V2DF "v2di")
878 (SF "si")
879 (VNx16QI "vnx16qi")
880 (VNx8HI "vnx8hi") (VNx8HF "vnx8hi")
881 (VNx4SI "vnx4si") (VNx4SF "vnx4si")
882 (VNx2DI "vnx2di") (VNx2DF "vnx2di")
883])
884
885;; Floating-point equivalent of selected modes.
886(define_mode_attr V_FP_EQUIV [(VNx4SI "VNx4SF") (VNx4SF "VNx4SF")
887 (VNx2DI "VNx2DF") (VNx2DF "VNx2DF")])
888(define_mode_attr v_fp_equiv [(VNx4SI "vnx4sf") (VNx4SF "vnx4sf")
889 (VNx2DI "vnx2df") (VNx2DF "vnx2df")])
70c67693 890
6c553b76
BC		 891;; Mode for vector conditional operations where the comparison has
892;; different type from the lhs.
893(define_mode_attr V_cmp_mixed [(V2SI "V2SF") (V4SI "V4SF")
894 (V2DI "V2DF") (V2SF "V2SI")
895 (V4SF "V4SI") (V2DF "V2DI")])
896
897(define_mode_attr v_cmp_mixed [(V2SI "v2sf") (V4SI "v4sf")
898 (V2DI "v2df") (V2SF "v2si")
899 (V4SF "v4si") (V2DF "v2di")])
900
cb23a30c
JG		 901;; Lower case element modes (as used in shift immediate patterns).
902(define_mode_attr ve_mode [(V8QI "qi") (V16QI "qi")
903 (V4HI "hi") (V8HI "hi")
904 (V2SI "si") (V4SI "si")
905 (DI "di") (V2DI "di")
906 (QI "qi") (HI "hi")
907 (SI "si")])
908
43e9d192
IB		 909;; Vm for lane instructions is restricted to FP_LO_REGS.
910(define_mode_attr vwx [(V4HI "x") (V8HI "x") (HI "x")
911 (V2SI "w") (V4SI "w") (SI "w")])
912
913(define_mode_attr Vendreg [(OI "T") (CI "U") (XI "V")])
914
97755701
AL		 915;; This is both the number of Q-Registers needed to hold the corresponding
916;; opaque large integer mode, and the number of elements touched by the
917;; ld..._lane and st..._lane operations.
43e9d192
IB		 918(define_mode_attr nregs [(OI "2") (CI "3") (XI "4")])
919
0462169c
SN		 920;; Mode for atomic operation suffixes
921(define_mode_attr atomic_sfx
922 [(QI "b") (HI "h") (SI "") (DI "")])
923
3f598afe 924(define_mode_attr fcvt_target [(V2DF "v2di") (V4SF "v4si") (V2SF "v2si")
2644d4d9 925 (V2DI "v2df") (V4SI "v4sf") (V2SI "v2sf")
daef0a8c
JW		 926 (SF "si") (DF "di") (SI "sf") (DI "df")
927 (V4HF "v4hi") (V8HF "v8hi") (V4HI "v4hf")
68ad28c3 928 (V8HI "v8hf") (HF "hi") (HI "hf")])
3f598afe 929(define_mode_attr FCVT_TARGET [(V2DF "V2DI") (V4SF "V4SI") (V2SF "V2SI")
2644d4d9 930 (V2DI "V2DF") (V4SI "V4SF") (V2SI "V2SF")
daef0a8c
JW		 931 (SF "SI") (DF "DI") (SI "SF") (DI "DF")
932 (V4HF "V4HI") (V8HF "V8HI") (V4HI "V4HF")
68ad28c3 933 (V8HI "V8HF") (HF "HI") (HI "HF")])
3f598afe 934
0d35c5c2
VP		 935
936;; for the inequal width integer to fp conversions
d7f33f07
JW		 937(define_mode_attr fcvt_iesize [(HF "di") (SF "di") (DF "si")])
938(define_mode_attr FCVT_IESIZE [(HF "DI") (SF "DI") (DF "SI")])
42fc9a7f 939
91bd4114
JG		 940(define_mode_attr VSWAP_WIDTH [(V8QI "V16QI") (V16QI "V8QI")
941 (V4HI "V8HI") (V8HI "V4HI")
942 (V2SI "V4SI") (V4SI "V2SI")
943 (DI "V2DI") (V2DI "DI")
944 (V2SF "V4SF") (V4SF "V2SF")
862abc04 945 (V4HF "V8HF") (V8HF "V4HF")
91bd4114
JG		 946 (DF "V2DF") (V2DF "DF")])
947
948(define_mode_attr vswap_width_name [(V8QI "to_128") (V16QI "to_64")
949 (V4HI "to_128") (V8HI "to_64")
950 (V2SI "to_128") (V4SI "to_64")
951 (DI "to_128") (V2DI "to_64")
862abc04 952 (V4HF "to_128") (V8HF "to_64")
91bd4114
JG		 953 (V2SF "to_128") (V4SF "to_64")
954 (DF "to_128") (V2DF "to_64")])
955
779aea46 956;; For certain vector-by-element multiplication instructions we must
6d06971d 957;; constrain the 16-bit cases to use only V0-V15. This is covered by
779aea46
JG		 958;; the 'x' constraint. All other modes may use the 'w' constraint.
959(define_mode_attr h_con [(V2SI "w") (V4SI "w")
960 (V4HI "x") (V8HI "x")
6d06971d 961 (V4HF "x") (V8HF "x")
779aea46
JG		 962 (V2SF "w") (V4SF "w")
963 (V2DF "w") (DF "w")])
964
965;; Defined to 'f' for types whose element type is a float type.
966(define_mode_attr f [(V8QI "") (V16QI "")
967 (V4HI "") (V8HI "")
968 (V2SI "") (V4SI "")
969 (DI "") (V2DI "")
ab2e8f01 970 (V4HF "f") (V8HF "f")
779aea46
JG		 971 (V2SF "f") (V4SF "f")
972 (V2DF "f") (DF "f")])
973
0f686aa9
JG		 974;; Defined to '_fp' for types whose element type is a float type.
975(define_mode_attr fp [(V8QI "") (V16QI "")
976 (V4HI "") (V8HI "")
977 (V2SI "") (V4SI "")
978 (DI "") (V2DI "")
ab2e8f01 979 (V4HF "_fp") (V8HF "_fp")
0f686aa9
JG		 980 (V2SF "_fp") (V4SF "_fp")
981 (V2DF "_fp") (DF "_fp")
982 (SF "_fp")])
983
a9e66678
JG		 984;; Defined to '_q' for 128-bit types.
985(define_mode_attr q [(V8QI "") (V16QI "_q")
0f686aa9
JG		 986 (V4HI "") (V8HI "_q")
987 (V2SI "") (V4SI "_q")
988 (DI "") (V2DI "_q")
71a11456 989 (V4HF "") (V8HF "_q")
0f686aa9
JG		 990 (V2SF "") (V4SF "_q")
991 (V2DF "_q")
d7f33f07 992 (QI "") (HI "") (SI "") (DI "") (HF "") (SF "") (DF "")])
a9e66678 993
92835317
TB		 994(define_mode_attr vp [(V8QI "v") (V16QI "v")
995 (V4HI "v") (V8HI "v")
996 (V2SI "p") (V4SI "v")
703bbcdf
JW		 997 (V2DI "p") (V2DF "p")
998 (V2SF "p") (V4SF "v")
999 (V4HF "v") (V8HF "v")])
92835317 1000
5e32e83b
JW		 1001(define_mode_attr vsi2qi [(V2SI "v8qi") (V4SI "v16qi")])
1002(define_mode_attr VSI2QI [(V2SI "V8QI") (V4SI "V16QI")])
1003
7a08d813
TC		 1004
1005;; Register suffix for DOTPROD input types from the return type.
1006(define_mode_attr Vdottype [(V2SI "8b") (V4SI "16b")])
1007
cd78b3dd 1008;; Sum of lengths of instructions needed to move vector registers of a mode.
668046d1
DS		 1009(define_mode_attr insn_count [(OI "8") (CI "12") (XI "16")])
1010
1b1e81f8
JW		 1011;; -fpic small model GOT reloc modifers: gotpage_lo15/lo14 for ILP64/32.
1012;; No need of iterator for -fPIC as it use got_lo12 for both modes.
1013(define_mode_attr got_modifier [(SI "gotpage_lo14") (DI "gotpage_lo15")])
1014
27086ea3
MC		 1015;; Width of 2nd and 3rd arguments to fp16 vector multiply add/sub
1016(define_mode_attr VFMLA_W [(V2SF "V4HF") (V4SF "V8HF")])
1017
1018(define_mode_attr VFMLA_SEL_W [(V2SF "V2HF") (V4SF "V4HF")])
1019
1020(define_mode_attr f16quad [(V2SF "") (V4SF "q")])
1021
1022(define_code_attr f16mac [(plus "a") (minus "s")])
1023
9f4cbab8
RS		 1024;; The number of subvectors in an SVE_STRUCT.
1025(define_mode_attr vector_count [(VNx32QI "2") (VNx16HI "2")
1026 (VNx8SI "2") (VNx4DI "2")
1027 (VNx16HF "2") (VNx8SF "2") (VNx4DF "2")
1028 (VNx48QI "3") (VNx24HI "3")
1029 (VNx12SI "3") (VNx6DI "3")
1030 (VNx24HF "3") (VNx12SF "3") (VNx6DF "3")
1031 (VNx64QI "4") (VNx32HI "4")
1032 (VNx16SI "4") (VNx8DI "4")
1033 (VNx32HF "4") (VNx16SF "4") (VNx8DF "4")])
1034
1035;; The number of instruction bytes needed for an SVE_STRUCT move. This is
1036;; equal to vector_count * 4.
1037(define_mode_attr insn_length [(VNx32QI "8") (VNx16HI "8")
1038 (VNx8SI "8") (VNx4DI "8")
1039 (VNx16HF "8") (VNx8SF "8") (VNx4DF "8")
1040 (VNx48QI "12") (VNx24HI "12")
1041 (VNx12SI "12") (VNx6DI "12")
1042 (VNx24HF "12") (VNx12SF "12") (VNx6DF "12")
1043 (VNx64QI "16") (VNx32HI "16")
1044 (VNx16SI "16") (VNx8DI "16")
1045 (VNx32HF "16") (VNx16SF "16") (VNx8DF "16")])
1046
1047;; The type of a subvector in an SVE_STRUCT.
1048(define_mode_attr VSINGLE [(VNx32QI "VNx16QI")
1049 (VNx16HI "VNx8HI") (VNx16HF "VNx8HF")
1050 (VNx8SI "VNx4SI") (VNx8SF "VNx4SF")
1051 (VNx4DI "VNx2DI") (VNx4DF "VNx2DF")
1052 (VNx48QI "VNx16QI")
1053 (VNx24HI "VNx8HI") (VNx24HF "VNx8HF")
1054 (VNx12SI "VNx4SI") (VNx12SF "VNx4SF")
1055 (VNx6DI "VNx2DI") (VNx6DF "VNx2DF")
1056 (VNx64QI "VNx16QI")
1057 (VNx32HI "VNx8HI") (VNx32HF "VNx8HF")
1058 (VNx16SI "VNx4SI") (VNx16SF "VNx4SF")
1059 (VNx8DI "VNx2DI") (VNx8DF "VNx2DF")])
1060
1061;; ...and again in lower case.
1062(define_mode_attr vsingle [(VNx32QI "vnx16qi")
1063 (VNx16HI "vnx8hi") (VNx16HF "vnx8hf")
1064 (VNx8SI "vnx4si") (VNx8SF "vnx4sf")
1065 (VNx4DI "vnx2di") (VNx4DF "vnx2df")
1066 (VNx48QI "vnx16qi")
1067 (VNx24HI "vnx8hi") (VNx24HF "vnx8hf")
1068 (VNx12SI "vnx4si") (VNx12SF "vnx4sf")
1069 (VNx6DI "vnx2di") (VNx6DF "vnx2df")
1070 (VNx64QI "vnx16qi")
1071 (VNx32HI "vnx8hi") (VNx32HF "vnx8hf")
1072 (VNx16SI "vnx4si") (VNx16SF "vnx4sf")
1073 (VNx8DI "vnx2di") (VNx8DF "vnx2df")])
1074
1075;; The predicate mode associated with an SVE data mode. For structure modes
1076;; this is equivalent to the <VPRED> of the subvector mode.
43cacb12
RS		 1077(define_mode_attr VPRED [(VNx16QI "VNx16BI")
1078 (VNx8HI "VNx8BI") (VNx8HF "VNx8BI")
1079 (VNx4SI "VNx4BI") (VNx4SF "VNx4BI")
9f4cbab8
RS		 1080 (VNx2DI "VNx2BI") (VNx2DF "VNx2BI")
1081 (VNx32QI "VNx16BI")
1082 (VNx16HI "VNx8BI") (VNx16HF "VNx8BI")
1083 (VNx8SI "VNx4BI") (VNx8SF "VNx4BI")
1084 (VNx4DI "VNx2BI") (VNx4DF "VNx2BI")
1085 (VNx48QI "VNx16BI")
1086 (VNx24HI "VNx8BI") (VNx24HF "VNx8BI")
1087 (VNx12SI "VNx4BI") (VNx12SF "VNx4BI")
1088 (VNx6DI "VNx2BI") (VNx6DF "VNx2BI")
1089 (VNx64QI "VNx16BI")
1090 (VNx32HI "VNx8BI") (VNx32HF "VNx8BI")
1091 (VNx16SI "VNx4BI") (VNx16SF "VNx4BI")
1092 (VNx8DI "VNx2BI") (VNx8DF "VNx2BI")])
43cacb12
RS		 1093
1094;; ...and again in lower case.
1095(define_mode_attr vpred [(VNx16QI "vnx16bi")
1096 (VNx8HI "vnx8bi") (VNx8HF "vnx8bi")
1097 (VNx4SI "vnx4bi") (VNx4SF "vnx4bi")
9f4cbab8
RS		 1098 (VNx2DI "vnx2bi") (VNx2DF "vnx2bi")
1099 (VNx32QI "vnx16bi")
1100 (VNx16HI "vnx8bi") (VNx16HF "vnx8bi")
1101 (VNx8SI "vnx4bi") (VNx8SF "vnx4bi")
1102 (VNx4DI "vnx2bi") (VNx4DF "vnx2bi")
1103 (VNx48QI "vnx16bi")
1104 (VNx24HI "vnx8bi") (VNx24HF "vnx8bi")
1105 (VNx12SI "vnx4bi") (VNx12SF "vnx4bi")
1106 (VNx6DI "vnx2bi") (VNx6DF "vnx2bi")
1107 (VNx64QI "vnx16bi")
1108 (VNx32HI "vnx8bi") (VNx32HF "vnx4bi")
1109 (VNx16SI "vnx4bi") (VNx16SF "vnx4bi")
1110 (VNx8DI "vnx2bi") (VNx8DF "vnx2bi")])
43cacb12 1111
43e9d192
IB		 1112;; -------------------------------------------------------------------
1113;; Code Iterators
1114;; -------------------------------------------------------------------
1115
1116;; This code iterator allows the various shifts supported on the core
1117(define_code_iterator SHIFT [ashift ashiftrt lshiftrt rotatert])
1118
1119;; This code iterator allows the shifts supported in arithmetic instructions
1120(define_code_iterator ASHIFT [ashift ashiftrt lshiftrt])
1121
1122;; Code iterator for logical operations
1123(define_code_iterator LOGICAL [and ior xor])
1124
43cacb12
RS		 1125;; LOGICAL without AND.
1126(define_code_iterator LOGICAL_OR [ior xor])
1127
84be6032
AL		 1128;; Code iterator for logical operations whose :nlogical works on SIMD registers.
1129(define_code_iterator NLOGICAL [and ior])
1130
3204ac98
KT		 1131;; Code iterator for unary negate and bitwise complement.
1132(define_code_iterator NEG_NOT [neg not])
1133
43e9d192
IB		 1134;; Code iterator for sign/zero extension
1135(define_code_iterator ANY_EXTEND [sign_extend zero_extend])
1136
1137;; All division operations (signed/unsigned)
1138(define_code_iterator ANY_DIV [div udiv])
1139
1140;; Code iterator for sign/zero extraction
1141(define_code_iterator ANY_EXTRACT [sign_extract zero_extract])
1142
1143;; Code iterator for equality comparisons
1144(define_code_iterator EQL [eq ne])
1145
1146;; Code iterator for less-than and greater/equal-to
1147(define_code_iterator LTGE [lt ge])
1148
1149;; Iterator for __sync_<op> operations that where the operation can be
1150;; represented directly RTL. This is all of the sync operations bar
1151;; nand.
0462169c 1152(define_code_iterator atomic_op [plus minus ior xor and])
43e9d192
IB		 1153
1154;; Iterator for integer conversions
1155(define_code_iterator FIXUORS [fix unsigned_fix])
1156
1709ff9b
JG		 1157;; Iterator for float conversions
1158(define_code_iterator FLOATUORS [float unsigned_float])
1159
43e9d192
IB		 1160;; Code iterator for variants of vector max and min.
1161(define_code_iterator MAXMIN [smax smin umax umin])
1162
998eaf97
JG		 1163(define_code_iterator FMAXMIN [smax smin])
1164
43e9d192
IB		 1165;; Code iterator for variants of vector max and min.
1166(define_code_iterator ADDSUB [plus minus])
1167
1168;; Code iterator for variants of vector saturating binary ops.
1169(define_code_iterator BINQOPS [ss_plus us_plus ss_minus us_minus])
1170
1171;; Code iterator for variants of vector saturating unary ops.
1172(define_code_iterator UNQOPS [ss_neg ss_abs])
1173
1174;; Code iterator for signed variants of vector saturating binary ops.
1175(define_code_iterator SBINQOPS [ss_plus ss_minus])
1176
889b9412
JG		 1177;; Comparison operators for <F>CM.
1178(define_code_iterator COMPARISONS [lt le eq ge gt])
1179
1180;; Unsigned comparison operators.
1181(define_code_iterator UCOMPARISONS [ltu leu geu gtu])
1182
75dd5ace
JG		 1183;; Unsigned comparison operators.
1184(define_code_iterator FAC_COMPARISONS [lt le ge gt])
1185
43cacb12
RS		 1186;; SVE integer unary operations.
1187(define_code_iterator SVE_INT_UNARY [neg not popcount])
1188
1189;; SVE floating-point unary operations.
1190(define_code_iterator SVE_FP_UNARY [neg abs sqrt])
1191
43e9d192
IB		 1192;; -------------------------------------------------------------------
1193;; Code Attributes
1194;; -------------------------------------------------------------------
1195;; Map rtl objects to optab names
1196(define_code_attr optab [(ashift "ashl")
1197 (ashiftrt "ashr")
1198 (lshiftrt "lshr")
1199 (rotatert "rotr")
1200 (sign_extend "extend")
1201 (zero_extend "zero_extend")
1202 (sign_extract "extv")
1203 (zero_extract "extzv")
384be29f
JG		 1204 (fix "fix")
1205 (unsigned_fix "fixuns")
1709ff9b
JG		 1206 (float "float")
1207 (unsigned_float "floatuns")
43cacb12 1208 (popcount "popcount")
43e9d192
IB		 1209 (and "and")
1210 (ior "ior")
1211 (xor "xor")
1212 (not "one_cmpl")
1213 (neg "neg")
1214 (plus "add")
1215 (minus "sub")
1216 (ss_plus "qadd")
1217 (us_plus "qadd")
1218 (ss_minus "qsub")
1219 (us_minus "qsub")
1220 (ss_neg "qneg")
1221 (ss_abs "qabs")
43cacb12
RS		 1222 (smin "smin")
1223 (smax "smax")
1224 (umin "umin")
1225 (umax "umax")
43e9d192
IB		 1226 (eq "eq")
1227 (ne "ne")
1228 (lt "lt")
889b9412
JG		 1229 (ge "ge")
1230 (le "le")
1231 (gt "gt")
1232 (ltu "ltu")
1233 (leu "leu")
1234 (geu "geu")
43cacb12
RS		 1235 (gtu "gtu")
1236 (abs "abs")
1237 (sqrt "sqrt")])
889b9412
JG		 1238
1239;; For comparison operators we use the FCM* and CM* instructions.
1240;; As there are no CMLE or CMLT instructions which act on 3 vector
1241;; operands, we must use CMGE or CMGT and swap the order of the
1242;; source operands.
1243
1244(define_code_attr n_optab [(lt "gt") (le "ge") (eq "eq") (ge "ge") (gt "gt")
1245 (ltu "hi") (leu "hs") (geu "hs") (gtu "hi")])
1246(define_code_attr cmp_1 [(lt "2") (le "2") (eq "1") (ge "1") (gt "1")
1247 (ltu "2") (leu "2") (geu "1") (gtu "1")])
1248(define_code_attr cmp_2 [(lt "1") (le "1") (eq "2") (ge "2") (gt "2")
1249 (ltu "1") (leu "1") (geu "2") (gtu "2")])
1250
1251(define_code_attr CMP [(lt "LT") (le "LE") (eq "EQ") (ge "GE") (gt "GT")
714e1b3b
KT		 1252 (ltu "LTU") (leu "LEU") (ne "NE") (geu "GEU")
1253 (gtu "GTU")])
43e9d192 1254
384be29f
JG		 1255(define_code_attr fix_trunc_optab [(fix "fix_trunc")
1256 (unsigned_fix "fixuns_trunc")])
1257
43e9d192
IB		 1258;; Optab prefix for sign/zero-extending operations
1259(define_code_attr su_optab [(sign_extend "") (zero_extend "u")
1260 (div "") (udiv "u")
1261 (fix "") (unsigned_fix "u")
1709ff9b 1262 (float "s") (unsigned_float "u")
43e9d192
IB		 1263 (ss_plus "s") (us_plus "u")
1264 (ss_minus "s") (us_minus "u")])
1265
1266;; Similar for the instruction mnemonics
1267(define_code_attr shift [(ashift "lsl") (ashiftrt "asr")
1268 (lshiftrt "lsr") (rotatert "ror")])
1269
1270;; Map shift operators onto underlying bit-field instructions
1271(define_code_attr bfshift [(ashift "ubfiz") (ashiftrt "sbfx")
1272 (lshiftrt "ubfx") (rotatert "extr")])
1273
1274;; Logical operator instruction mnemonics
1275(define_code_attr logical [(and "and") (ior "orr") (xor "eor")])
1276
3204ac98
KT		 1277;; Operation names for negate and bitwise complement.
1278(define_code_attr neg_not_op [(neg "neg") (not "not")])
1279
43cacb12 1280;; Similar, but when the second operand is inverted.
43e9d192
IB		 1281(define_code_attr nlogical [(and "bic") (ior "orn") (xor "eon")])
1282
43cacb12
RS		 1283;; Similar, but when both operands are inverted.
1284(define_code_attr logical_nn [(and "nor") (ior "nand")])
1285
43e9d192
IB		 1286;; Sign- or zero-extending data-op
1287(define_code_attr su [(sign_extend "s") (zero_extend "u")
1288 (sign_extract "s") (zero_extract "u")
1289 (fix "s") (unsigned_fix "u")
998eaf97
JG		 1290 (div "s") (udiv "u")
1291 (smax "s") (umax "u")
1292 (smin "s") (umin "u")])
43e9d192 1293
43cacb12
RS		 1294;; Whether a shift is left or right.
1295(define_code_attr lr [(ashift "l") (ashiftrt "r") (lshiftrt "r")])
1296
096e8448
JW		 1297;; Emit conditional branch instructions.
1298(define_code_attr bcond [(eq "beq") (ne "bne") (lt "bne") (ge "beq")])
1299
43e9d192
IB		 1300;; Emit cbz/cbnz depending on comparison type.
1301(define_code_attr cbz [(eq "cbz") (ne "cbnz") (lt "cbnz") (ge "cbz")])
1302
973d2e01
TP		 1303;; Emit inverted cbz/cbnz depending on comparison type.
1304(define_code_attr inv_cb [(eq "cbnz") (ne "cbz") (lt "cbz") (ge "cbnz")])
1305
43e9d192
IB		 1306;; Emit tbz/tbnz depending on comparison type.
1307(define_code_attr tbz [(eq "tbz") (ne "tbnz") (lt "tbnz") (ge "tbz")])
1308
973d2e01
TP		 1309;; Emit inverted tbz/tbnz depending on comparison type.
1310(define_code_attr inv_tb [(eq "tbnz") (ne "tbz") (lt "tbz") (ge "tbnz")])
1311
43e9d192 1312;; Max/min attributes.
998eaf97
JG		 1313(define_code_attr maxmin [(smax "max")
1314 (smin "min")
1315 (umax "max")
1316 (umin "min")])
43e9d192
IB		 1317
1318;; MLA/MLS attributes.
1319(define_code_attr as [(ss_plus "a") (ss_minus "s")])
1320
0462169c
SN		 1321;; Atomic operations
1322(define_code_attr atomic_optab
1323 [(ior "or") (xor "xor") (and "and") (plus "add") (minus "sub")])
1324
1325(define_code_attr atomic_op_operand
1326 [(ior "aarch64_logical_operand")
1327 (xor "aarch64_logical_operand")
1328 (and "aarch64_logical_operand")
1329 (plus "aarch64_plus_operand")
1330 (minus "aarch64_plus_operand")])
43e9d192 1331
356c32e2
MW		 1332;; Constants acceptable for atomic operations.
1333;; This definition must appear in this file before the iterators it refers to.
1334(define_code_attr const_atomic
1335 [(plus "IJ") (minus "IJ")
1336 (xor "<lconst_atomic>") (ior "<lconst_atomic>")
1337 (and "<lconst_atomic>")])
1338
1339;; Attribute to describe constants acceptable in atomic logical operations
1340(define_mode_attr lconst_atomic [(QI "K") (HI "K") (SI "K") (DI "L")])
1341
43cacb12
RS		 1342;; The integer SVE instruction that implements an rtx code.
1343(define_code_attr sve_int_op [(plus "add")
1344 (neg "neg")
1345 (smin "smin")
1346 (smax "smax")
1347 (umin "umin")
1348 (umax "umax")
1349 (and "and")
1350 (ior "orr")
1351 (xor "eor")
1352 (not "not")
1353 (popcount "cnt")])
1354
1355;; The floating-point SVE instruction that implements an rtx code.
1356(define_code_attr sve_fp_op [(plus "fadd")
1357 (neg "fneg")
1358 (abs "fabs")
1359 (sqrt "fsqrt")])
1360
43e9d192
IB		 1361;; -------------------------------------------------------------------
1362;; Int Iterators.
1363;; -------------------------------------------------------------------
1364(define_int_iterator MAXMINV [UNSPEC_UMAXV UNSPEC_UMINV
1365 UNSPEC_SMAXV UNSPEC_SMINV])
1366
998eaf97
JG		 1367(define_int_iterator FMAXMINV [UNSPEC_FMAXV UNSPEC_FMINV
1368 UNSPEC_FMAXNMV UNSPEC_FMINNMV])
43e9d192 1369
898f07b0
RS		 1370(define_int_iterator BITWISEV [UNSPEC_ANDV UNSPEC_IORV UNSPEC_XORV])
1371
43cacb12
RS		 1372(define_int_iterator LOGICALF [UNSPEC_ANDF UNSPEC_IORF UNSPEC_XORF])
1373
43e9d192
IB		 1374(define_int_iterator HADDSUB [UNSPEC_SHADD UNSPEC_UHADD
1375 UNSPEC_SRHADD UNSPEC_URHADD
1376 UNSPEC_SHSUB UNSPEC_UHSUB
1377 UNSPEC_SRHSUB UNSPEC_URHSUB])
1378
7a08d813 1379(define_int_iterator DOTPROD [UNSPEC_SDOT UNSPEC_UDOT])
43e9d192
IB		 1380
1381(define_int_iterator ADDSUBHN [UNSPEC_ADDHN UNSPEC_RADDHN
1382 UNSPEC_SUBHN UNSPEC_RSUBHN])
1383
1384(define_int_iterator ADDSUBHN2 [UNSPEC_ADDHN2 UNSPEC_RADDHN2
1385 UNSPEC_SUBHN2 UNSPEC_RSUBHN2])
1386
1efafef3
TC		 1387(define_int_iterator FMAXMIN_UNS [UNSPEC_FMAX UNSPEC_FMIN
1388 UNSPEC_FMAXNM UNSPEC_FMINNM])
202d0c11 1389
db58fd89
JW		 1390(define_int_iterator PAUTH_LR_SP [UNSPEC_PACISP UNSPEC_AUTISP])
1391
1392(define_int_iterator PAUTH_17_16 [UNSPEC_PACI1716 UNSPEC_AUTI1716])
1393
43e9d192
IB		 1394(define_int_iterator VQDMULH [UNSPEC_SQDMULH UNSPEC_SQRDMULH])
1395
1396(define_int_iterator USSUQADD [UNSPEC_SUQADD UNSPEC_USQADD])
1397
1398(define_int_iterator SUQMOVN [UNSPEC_SQXTN UNSPEC_UQXTN])
1399
1400(define_int_iterator VSHL [UNSPEC_SSHL UNSPEC_USHL
1401 UNSPEC_SRSHL UNSPEC_URSHL])
1402
1403(define_int_iterator VSHLL [UNSPEC_SSHLL UNSPEC_USHLL])
1404
1405(define_int_iterator VQSHL [UNSPEC_SQSHL UNSPEC_UQSHL
1406 UNSPEC_SQRSHL UNSPEC_UQRSHL])
1407
1408(define_int_iterator VSRA [UNSPEC_SSRA UNSPEC_USRA
1409 UNSPEC_SRSRA UNSPEC_URSRA])
1410
1411(define_int_iterator VSLRI [UNSPEC_SSLI UNSPEC_USLI
1412 UNSPEC_SSRI UNSPEC_USRI])
1413
1414
1415(define_int_iterator VRSHR_N [UNSPEC_SRSHR UNSPEC_URSHR])
1416
1417(define_int_iterator VQSHL_N [UNSPEC_SQSHLU UNSPEC_SQSHL UNSPEC_UQSHL])
1418
1419(define_int_iterator VQSHRN_N [UNSPEC_SQSHRUN UNSPEC_SQRSHRUN
1420 UNSPEC_SQSHRN UNSPEC_UQSHRN
1421 UNSPEC_SQRSHRN UNSPEC_UQRSHRN])
1422
57b26d65
MW		 1423(define_int_iterator SQRDMLH_AS [UNSPEC_SQRDMLAH UNSPEC_SQRDMLSH])
1424
cc4d934f
JG		 1425(define_int_iterator PERMUTE [UNSPEC_ZIP1 UNSPEC_ZIP2
1426 UNSPEC_TRN1 UNSPEC_TRN2
1427 UNSPEC_UZP1 UNSPEC_UZP2])
43e9d192 1428
43cacb12
RS		 1429(define_int_iterator OPTAB_PERMUTE [UNSPEC_ZIP1 UNSPEC_ZIP2
1430 UNSPEC_UZP1 UNSPEC_UZP2])
1431
923fcec3
AL		 1432(define_int_iterator REVERSE [UNSPEC_REV64 UNSPEC_REV32 UNSPEC_REV16])
1433
42fc9a7f 1434(define_int_iterator FRINT [UNSPEC_FRINTZ UNSPEC_FRINTP UNSPEC_FRINTM
0659ce6f
JG		 1435 UNSPEC_FRINTN UNSPEC_FRINTI UNSPEC_FRINTX
1436 UNSPEC_FRINTA])
42fc9a7f
JG		 1437
1438(define_int_iterator FCVT [UNSPEC_FRINTZ UNSPEC_FRINTP UNSPEC_FRINTM
ce966824 1439 UNSPEC_FRINTA UNSPEC_FRINTN])
42fc9a7f 1440
3f598afe
JW		 1441(define_int_iterator FCVT_F2FIXED [UNSPEC_FCVTZS UNSPEC_FCVTZU])
1442(define_int_iterator FCVT_FIXED2F [UNSPEC_SCVTF UNSPEC_UCVTF])
1443
0050faf8
JG		 1444(define_int_iterator FRECP [UNSPEC_FRECPE UNSPEC_FRECPX])
1445
5d357f26
KT		 1446(define_int_iterator CRC [UNSPEC_CRC32B UNSPEC_CRC32H UNSPEC_CRC32W
1447 UNSPEC_CRC32X UNSPEC_CRC32CB UNSPEC_CRC32CH
1448 UNSPEC_CRC32CW UNSPEC_CRC32CX])
1449
5a7a4e80
TB		 1450(define_int_iterator CRYPTO_AES [UNSPEC_AESE UNSPEC_AESD])
1451(define_int_iterator CRYPTO_AESMC [UNSPEC_AESMC UNSPEC_AESIMC])
1452
30442682
TB		 1453(define_int_iterator CRYPTO_SHA1 [UNSPEC_SHA1C UNSPEC_SHA1M UNSPEC_SHA1P])
1454
b9cb0a44
TB		 1455(define_int_iterator CRYPTO_SHA256 [UNSPEC_SHA256H UNSPEC_SHA256H2])
1456
27086ea3
MC		 1457(define_int_iterator CRYPTO_SHA512 [UNSPEC_SHA512H UNSPEC_SHA512H2])
1458
1459(define_int_iterator CRYPTO_SM3TT [UNSPEC_SM3TT1A UNSPEC_SM3TT1B
1460 UNSPEC_SM3TT2A UNSPEC_SM3TT2B])
1461
1462(define_int_iterator CRYPTO_SM3PART [UNSPEC_SM3PARTW1 UNSPEC_SM3PARTW2])
1463
1464;; Iterators for fp16 operations
1465
1466(define_int_iterator VFMLA16_LOW [UNSPEC_FMLAL UNSPEC_FMLSL])
1467
1468(define_int_iterator VFMLA16_HIGH [UNSPEC_FMLAL2 UNSPEC_FMLSL2])
1469
43cacb12
RS		 1470(define_int_iterator UNPACK [UNSPEC_UNPACKSHI UNSPEC_UNPACKUHI
1471 UNSPEC_UNPACKSLO UNSPEC_UNPACKULO])
1472
1473(define_int_iterator UNPACK_UNSIGNED [UNSPEC_UNPACKULO UNSPEC_UNPACKUHI])
1474
11e9443f
RS		 1475(define_int_iterator MUL_HIGHPART [UNSPEC_SMUL_HIGHPART UNSPEC_UMUL_HIGHPART])
1476
0972596e
RS		 1477(define_int_iterator SVE_COND_INT_OP [UNSPEC_COND_ADD UNSPEC_COND_SUB
1478 UNSPEC_COND_SMAX UNSPEC_COND_UMAX
1479 UNSPEC_COND_SMIN UNSPEC_COND_UMIN
1480 UNSPEC_COND_AND
1481 UNSPEC_COND_ORR
1482 UNSPEC_COND_EOR])
1483
1484(define_int_iterator SVE_COND_FP_OP [UNSPEC_COND_ADD UNSPEC_COND_SUB])
1485
43cacb12
RS		 1486(define_int_iterator SVE_COND_INT_CMP [UNSPEC_COND_LT UNSPEC_COND_LE
1487 UNSPEC_COND_EQ UNSPEC_COND_NE
1488 UNSPEC_COND_GE UNSPEC_COND_GT
1489 UNSPEC_COND_LO UNSPEC_COND_LS
1490 UNSPEC_COND_HS UNSPEC_COND_HI])
1491
1492(define_int_iterator SVE_COND_FP_CMP [UNSPEC_COND_LT UNSPEC_COND_LE
1493 UNSPEC_COND_EQ UNSPEC_COND_NE
1494 UNSPEC_COND_GE UNSPEC_COND_GT])
1495
d81cb613
MW		 1496;; Iterators for atomic operations.
1497
1498(define_int_iterator ATOMIC_LDOP
1499 [UNSPECV_ATOMIC_LDOP_OR UNSPECV_ATOMIC_LDOP_BIC
1500 UNSPECV_ATOMIC_LDOP_XOR UNSPECV_ATOMIC_LDOP_PLUS])
1501
1502(define_int_attr atomic_ldop
1503 [(UNSPECV_ATOMIC_LDOP_OR "set") (UNSPECV_ATOMIC_LDOP_BIC "clr")
1504 (UNSPECV_ATOMIC_LDOP_XOR "eor") (UNSPECV_ATOMIC_LDOP_PLUS "add")])
1505
43e9d192
IB		 1506;; -------------------------------------------------------------------
1507;; Int Iterators Attributes.
1508;; -------------------------------------------------------------------
43cacb12
RS		 1509
1510;; The optab associated with an operation. Note that for ANDF, IORF
1511;; and XORF, the optab pattern is not actually defined; we just use this
1512;; name for consistency with the integer patterns.
1513(define_int_attr optab [(UNSPEC_ANDF "and")
1514 (UNSPEC_IORF "ior")
898f07b0
RS		 1515 (UNSPEC_XORF "xor")
1516 (UNSPEC_ANDV "and")
1517 (UNSPEC_IORV "ior")
0972596e
RS		 1518 (UNSPEC_XORV "xor")
1519 (UNSPEC_COND_ADD "add")
1520 (UNSPEC_COND_SUB "sub")
1521 (UNSPEC_COND_SMAX "smax")
1522 (UNSPEC_COND_UMAX "umax")
1523 (UNSPEC_COND_SMIN "smin")
1524 (UNSPEC_COND_UMIN "umin")
1525 (UNSPEC_COND_AND "and")
1526 (UNSPEC_COND_ORR "ior")
1527 (UNSPEC_COND_EOR "xor")])
43cacb12 1528
998eaf97
JG		 1529(define_int_attr maxmin_uns [(UNSPEC_UMAXV "umax")
1530 (UNSPEC_UMINV "umin")
1531 (UNSPEC_SMAXV "smax")
1532 (UNSPEC_SMINV "smin")
1533 (UNSPEC_FMAX "smax_nan")
1534 (UNSPEC_FMAXNMV "smax")
1535 (UNSPEC_FMAXV "smax_nan")
1536 (UNSPEC_FMIN "smin_nan")
1537 (UNSPEC_FMINNMV "smin")
1efafef3
TC		 1538 (UNSPEC_FMINV "smin_nan")
1539 (UNSPEC_FMAXNM "fmax")
1540 (UNSPEC_FMINNM "fmin")])
998eaf97
JG		 1541
1542(define_int_attr maxmin_uns_op [(UNSPEC_UMAXV "umax")
1543 (UNSPEC_UMINV "umin")
1544 (UNSPEC_SMAXV "smax")
1545 (UNSPEC_SMINV "smin")
1546 (UNSPEC_FMAX "fmax")
1547 (UNSPEC_FMAXNMV "fmaxnm")
1548 (UNSPEC_FMAXV "fmax")
1549 (UNSPEC_FMIN "fmin")
1550 (UNSPEC_FMINNMV "fminnm")
1efafef3
TC		 1551 (UNSPEC_FMINV "fmin")
1552 (UNSPEC_FMAXNM "fmaxnm")
1553 (UNSPEC_FMINNM "fminnm")])
202d0c11 1554
898f07b0
RS		 1555(define_int_attr bit_reduc_op [(UNSPEC_ANDV "andv")
1556 (UNSPEC_IORV "orv")
1557 (UNSPEC_XORV "eorv")])
1558
43cacb12
RS		 1559;; The SVE logical instruction that implements an unspec.
1560(define_int_attr logicalf_op [(UNSPEC_ANDF "and")
1561 (UNSPEC_IORF "orr")
1562 (UNSPEC_XORF "eor")])
1563
1564;; "s" for signed operations and "u" for unsigned ones.
1565(define_int_attr su [(UNSPEC_UNPACKSHI "s")
1566 (UNSPEC_UNPACKUHI "u")
1567 (UNSPEC_UNPACKSLO "s")
11e9443f
RS		 1568 (UNSPEC_UNPACKULO "u")
1569 (UNSPEC_SMUL_HIGHPART "s")
1570 (UNSPEC_UMUL_HIGHPART "u")])
43cacb12 1571
43e9d192
IB		 1572(define_int_attr sur [(UNSPEC_SHADD "s") (UNSPEC_UHADD "u")
1573 (UNSPEC_SRHADD "sr") (UNSPEC_URHADD "ur")
1574 (UNSPEC_SHSUB "s") (UNSPEC_UHSUB "u")
1575 (UNSPEC_SRHSUB "sr") (UNSPEC_URHSUB "ur")
1576 (UNSPEC_ADDHN "") (UNSPEC_RADDHN "r")
1577 (UNSPEC_SUBHN "") (UNSPEC_RSUBHN "r")
1578 (UNSPEC_ADDHN2 "") (UNSPEC_RADDHN2 "r")
1579 (UNSPEC_SUBHN2 "") (UNSPEC_RSUBHN2 "r")
1580 (UNSPEC_SQXTN "s") (UNSPEC_UQXTN "u")
1581 (UNSPEC_USQADD "us") (UNSPEC_SUQADD "su")
1582 (UNSPEC_SSLI "s") (UNSPEC_USLI "u")
1583 (UNSPEC_SSRI "s") (UNSPEC_USRI "u")
1584 (UNSPEC_USRA "u") (UNSPEC_SSRA "s")
1585 (UNSPEC_URSRA "ur") (UNSPEC_SRSRA "sr")
1586 (UNSPEC_URSHR "ur") (UNSPEC_SRSHR "sr")
1587 (UNSPEC_SQSHLU "s") (UNSPEC_SQSHL "s")
1588 (UNSPEC_UQSHL "u")
1589 (UNSPEC_SQSHRUN "s") (UNSPEC_SQRSHRUN "s")
1590 (UNSPEC_SQSHRN "s") (UNSPEC_UQSHRN "u")
1591 (UNSPEC_SQRSHRN "s") (UNSPEC_UQRSHRN "u")
1592 (UNSPEC_USHL "u") (UNSPEC_SSHL "s")
1593 (UNSPEC_USHLL "u") (UNSPEC_SSHLL "s")
1594 (UNSPEC_URSHL "ur") (UNSPEC_SRSHL "sr")
1595 (UNSPEC_UQRSHL "u") (UNSPEC_SQRSHL "s")
7a08d813 1596 (UNSPEC_SDOT "s") (UNSPEC_UDOT "u")
43e9d192
IB		 1597])
1598
1599(define_int_attr r [(UNSPEC_SQDMULH "") (UNSPEC_SQRDMULH "r")
1600 (UNSPEC_SQSHRUN "") (UNSPEC_SQRSHRUN "r")
1601 (UNSPEC_SQSHRN "") (UNSPEC_UQSHRN "")
1602 (UNSPEC_SQRSHRN "r") (UNSPEC_UQRSHRN "r")
1603 (UNSPEC_SQSHL "") (UNSPEC_UQSHL "")
1604 (UNSPEC_SQRSHL "r")(UNSPEC_UQRSHL "r")
1605])
1606
1607(define_int_attr lr [(UNSPEC_SSLI "l") (UNSPEC_USLI "l")
1608 (UNSPEC_SSRI "r") (UNSPEC_USRI "r")])
1609
1610(define_int_attr u [(UNSPEC_SQSHLU "u") (UNSPEC_SQSHL "") (UNSPEC_UQSHL "")
1611 (UNSPEC_SQSHRUN "u") (UNSPEC_SQRSHRUN "u")
1612 (UNSPEC_SQSHRN "") (UNSPEC_UQSHRN "")
1613 (UNSPEC_SQRSHRN "") (UNSPEC_UQRSHRN "")])
1614
1615(define_int_attr addsub [(UNSPEC_SHADD "add")
1616 (UNSPEC_UHADD "add")
1617 (UNSPEC_SRHADD "add")
1618 (UNSPEC_URHADD "add")
1619 (UNSPEC_SHSUB "sub")
1620 (UNSPEC_UHSUB "sub")
1621 (UNSPEC_SRHSUB "sub")
1622 (UNSPEC_URHSUB "sub")
1623 (UNSPEC_ADDHN "add")
1624 (UNSPEC_SUBHN "sub")
1625 (UNSPEC_RADDHN "add")
1626 (UNSPEC_RSUBHN "sub")
1627 (UNSPEC_ADDHN2 "add")
1628 (UNSPEC_SUBHN2 "sub")
1629 (UNSPEC_RADDHN2 "add")
1630 (UNSPEC_RSUBHN2 "sub")])
1631
cb23a30c
JG		 1632(define_int_attr offsetlr [(UNSPEC_SSLI "") (UNSPEC_USLI "")
1633 (UNSPEC_SSRI "offset_")
1634 (UNSPEC_USRI "offset_")])
43e9d192 1635
42fc9a7f
JG		 1636;; Standard pattern names for floating-point rounding instructions.
1637(define_int_attr frint_pattern [(UNSPEC_FRINTZ "btrunc")
1638 (UNSPEC_FRINTP "ceil")
1639 (UNSPEC_FRINTM "floor")
1640 (UNSPEC_FRINTI "nearbyint")
1641 (UNSPEC_FRINTX "rint")
0659ce6f
JG		 1642 (UNSPEC_FRINTA "round")
1643 (UNSPEC_FRINTN "frintn")])
42fc9a7f
JG		 1644
1645;; frint suffix for floating-point rounding instructions.
1646(define_int_attr frint_suffix [(UNSPEC_FRINTZ "z") (UNSPEC_FRINTP "p")
1647 (UNSPEC_FRINTM "m") (UNSPEC_FRINTI "i")
0659ce6f
JG		 1648 (UNSPEC_FRINTX "x") (UNSPEC_FRINTA "a")
1649 (UNSPEC_FRINTN "n")])
42fc9a7f
JG		 1650
1651(define_int_attr fcvt_pattern [(UNSPEC_FRINTZ "btrunc") (UNSPEC_FRINTA "round")
ce966824
JG		 1652 (UNSPEC_FRINTP "ceil") (UNSPEC_FRINTM "floor")
1653 (UNSPEC_FRINTN "frintn")])
42fc9a7f 1654
3f598afe
JW		 1655(define_int_attr fcvt_fixed_insn [(UNSPEC_SCVTF "scvtf")
1656 (UNSPEC_UCVTF "ucvtf")
1657 (UNSPEC_FCVTZS "fcvtzs")
1658 (UNSPEC_FCVTZU "fcvtzu")])
1659
db58fd89
JW		 1660;; Pointer authentication mnemonic prefix.
1661(define_int_attr pauth_mnem_prefix [(UNSPEC_PACISP "paci")
1662 (UNSPEC_AUTISP "auti")
1663 (UNSPEC_PACI1716 "paci")
1664 (UNSPEC_AUTI1716 "auti")])
1665
1666;; Pointer authentication HINT number for NOP space instructions using A Key.
1667(define_int_attr pauth_hint_num_a [(UNSPEC_PACISP "25")
1668 (UNSPEC_AUTISP "29")
1669 (UNSPEC_PACI1716 "8")
1670 (UNSPEC_AUTI1716 "12")])
1671
cc4d934f
JG		 1672(define_int_attr perm_insn [(UNSPEC_ZIP1 "zip") (UNSPEC_ZIP2 "zip")
1673 (UNSPEC_TRN1 "trn") (UNSPEC_TRN2 "trn")
1674 (UNSPEC_UZP1 "uzp") (UNSPEC_UZP2 "uzp")])
1675
923fcec3
AL		 1676; op code for REV instructions (size within which elements are reversed).
1677(define_int_attr rev_op [(UNSPEC_REV64 "64") (UNSPEC_REV32 "32")
1678 (UNSPEC_REV16 "16")])
1679
cc4d934f
JG		 1680(define_int_attr perm_hilo [(UNSPEC_ZIP1 "1") (UNSPEC_ZIP2 "2")
1681 (UNSPEC_TRN1 "1") (UNSPEC_TRN2 "2")
43cacb12
RS		 1682 (UNSPEC_UZP1 "1") (UNSPEC_UZP2 "2")
1683 (UNSPEC_UNPACKSHI "hi") (UNSPEC_UNPACKUHI "hi")
1684 (UNSPEC_UNPACKSLO "lo") (UNSPEC_UNPACKULO "lo")])
0050faf8 1685
9bfb28ed
RS		 1686;; Return true if the associated optab refers to the high-numbered lanes,
1687;; false if it refers to the low-numbered lanes. The convention is for
1688;; "hi" to refer to the low-numbered lanes (the first ones in memory)
1689;; for big-endian.
1690(define_int_attr hi_lanes_optab [(UNSPEC_UNPACKSHI "!BYTES_BIG_ENDIAN")
1691 (UNSPEC_UNPACKUHI "!BYTES_BIG_ENDIAN")
1692 (UNSPEC_UNPACKSLO "BYTES_BIG_ENDIAN")
1693 (UNSPEC_UNPACKULO "BYTES_BIG_ENDIAN")])
1694
0050faf8 1695(define_int_attr frecp_suffix [(UNSPEC_FRECPE "e") (UNSPEC_FRECPX "x")])
5a7a4e80 1696
5d357f26
KT		 1697(define_int_attr crc_variant [(UNSPEC_CRC32B "crc32b") (UNSPEC_CRC32H "crc32h")
1698 (UNSPEC_CRC32W "crc32w") (UNSPEC_CRC32X "crc32x")
1699 (UNSPEC_CRC32CB "crc32cb") (UNSPEC_CRC32CH "crc32ch")
1700 (UNSPEC_CRC32CW "crc32cw") (UNSPEC_CRC32CX "crc32cx")])
1701
1702(define_int_attr crc_mode [(UNSPEC_CRC32B "QI") (UNSPEC_CRC32H "HI")
1703 (UNSPEC_CRC32W "SI") (UNSPEC_CRC32X "DI")
1704 (UNSPEC_CRC32CB "QI") (UNSPEC_CRC32CH "HI")
1705 (UNSPEC_CRC32CW "SI") (UNSPEC_CRC32CX "DI")])
1706
5a7a4e80
TB		 1707(define_int_attr aes_op [(UNSPEC_AESE "e") (UNSPEC_AESD "d")])
1708(define_int_attr aesmc_op [(UNSPEC_AESMC "mc") (UNSPEC_AESIMC "imc")])
30442682
TB		 1709
1710(define_int_attr sha1_op [(UNSPEC_SHA1C "c") (UNSPEC_SHA1P "p")
1711 (UNSPEC_SHA1M "m")])
b9cb0a44
TB		 1712
1713(define_int_attr sha256_op [(UNSPEC_SHA256H "") (UNSPEC_SHA256H2 "2")])
57b26d65
MW		 1714
1715(define_int_attr rdma_as [(UNSPEC_SQRDMLAH "a") (UNSPEC_SQRDMLSH "s")])
27086ea3
MC		 1716
1717(define_int_attr sha512_op [(UNSPEC_SHA512H "") (UNSPEC_SHA512H2 "2")])
1718
1719(define_int_attr sm3tt_op [(UNSPEC_SM3TT1A "1a") (UNSPEC_SM3TT1B "1b")
1720 (UNSPEC_SM3TT2A "2a") (UNSPEC_SM3TT2B "2b")])
1721
1722(define_int_attr sm3part_op [(UNSPEC_SM3PARTW1 "1") (UNSPEC_SM3PARTW2 "2")])
1723
1724(define_int_attr f16mac1 [(UNSPEC_FMLAL "a") (UNSPEC_FMLSL "s")
1725 (UNSPEC_FMLAL2 "a") (UNSPEC_FMLSL2 "s")])
43cacb12
RS		 1726
1727;; The condition associated with an UNSPEC_COND_<xx>.
1728(define_int_attr cmp_op [(UNSPEC_COND_LT "lt")
1729 (UNSPEC_COND_LE "le")
1730 (UNSPEC_COND_EQ "eq")
1731 (UNSPEC_COND_NE "ne")
1732 (UNSPEC_COND_GE "ge")
1733 (UNSPEC_COND_GT "gt")
1734 (UNSPEC_COND_LO "lo")
1735 (UNSPEC_COND_LS "ls")
1736 (UNSPEC_COND_HS "hs")
1737 (UNSPEC_COND_HI "hi")])
1738
1739;; The constraint to use for an UNSPEC_COND_<xx>.
1740(define_int_attr imm_con [(UNSPEC_COND_EQ "vsc")
1741 (UNSPEC_COND_NE "vsc")
1742 (UNSPEC_COND_LT "vsc")
1743 (UNSPEC_COND_GE "vsc")
1744 (UNSPEC_COND_LE "vsc")
1745 (UNSPEC_COND_GT "vsc")
1746 (UNSPEC_COND_LO "vsd")
1747 (UNSPEC_COND_LS "vsd")
1748 (UNSPEC_COND_HS "vsd")
1749 (UNSPEC_COND_HI "vsd")])
0972596e
RS		 1750
1751(define_int_attr sve_int_op [(UNSPEC_COND_ADD "add")
1752 (UNSPEC_COND_SUB "sub")
1753 (UNSPEC_COND_SMAX "smax")
1754 (UNSPEC_COND_UMAX "umax")
1755 (UNSPEC_COND_SMIN "smin")
1756 (UNSPEC_COND_UMIN "umin")
1757 (UNSPEC_COND_AND "and")
1758 (UNSPEC_COND_ORR "orr")
1759 (UNSPEC_COND_EOR "eor")])
1760
1761(define_int_attr sve_fp_op [(UNSPEC_COND_ADD "fadd")
1762 (UNSPEC_COND_SUB "fsub")])
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