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43e9d192 | 1 | ;; Machine description for AArch64 architecture. |
85ec4feb | 2 | ;; Copyright (C) 2009-2018 Free Software Foundation, Inc. |
43e9d192 IB |
3 | ;; Contributed by ARM Ltd. |
4 | ;; | |
5 | ;; This file is part of GCC. | |
6 | ;; | |
7 | ;; GCC is free software; you can redistribute it and/or modify it | |
8 | ;; under the terms of the GNU General Public License as published by | |
9 | ;; the Free Software Foundation; either version 3, or (at your option) | |
10 | ;; any later version. | |
11 | ;; | |
12 | ;; GCC is distributed in the hope that it will be useful, but | |
13 | ;; WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | ;; General Public License for more details. | |
16 | ;; | |
17 | ;; You should have received a copy of the GNU General Public License | |
18 | ;; along with GCC; see the file COPYING3. If not see | |
19 | ;; <http://www.gnu.org/licenses/>. | |
20 | ||
21 | ;; ------------------------------------------------------------------- | |
22 | ;; Mode Iterators | |
23 | ;; ------------------------------------------------------------------- | |
24 | ||
25 | ||
26 | ;; Iterator for General Purpose Integer registers (32- and 64-bit modes) | |
27 | (define_mode_iterator GPI [SI DI]) | |
28 | ||
d7f33f07 JW |
29 | ;; Iterator for HI, SI, DI, some instructions can only work on these modes. |
30 | (define_mode_iterator GPI_I16 [(HI "AARCH64_ISA_F16") SI DI]) | |
31 | ||
43e9d192 IB |
32 | ;; Iterator for QI and HI modes |
33 | (define_mode_iterator SHORT [QI HI]) | |
34 | ||
35 | ;; Iterator for all integer modes (up to 64-bit) | |
36 | (define_mode_iterator ALLI [QI HI SI DI]) | |
37 | ||
43e9d192 IB |
38 | ;; Iterator for all integer modes that can be extended (up to 64-bit) |
39 | (define_mode_iterator ALLX [QI HI SI]) | |
40 | ||
41 | ;; Iterator for General Purpose Floating-point registers (32- and 64-bit modes) | |
42 | (define_mode_iterator GPF [SF DF]) | |
43 | ||
d7f33f07 JW |
44 | ;; Iterator for all scalar floating point modes (HF, SF, DF) |
45 | (define_mode_iterator GPF_F16 [(HF "AARCH64_ISA_F16") SF DF]) | |
46 | ||
90e6443f TC |
47 | ;; Iterator for all scalar floating point modes (HF, SF, DF) |
48 | (define_mode_iterator GPF_HF [HF SF DF]) | |
49 | ||
09fcd8e1 RR |
50 | ;; Iterator for all scalar floating point modes (HF, SF, DF and TF) |
51 | (define_mode_iterator GPF_TF_F16 [HF SF DF TF]) | |
c2ec330c | 52 | |
922f9c25 AL |
53 | ;; Double vector modes. |
54 | (define_mode_iterator VDF [V2SF V4HF]) | |
55 | ||
b4f50fd4 RR |
56 | ;; Iterator for all scalar floating point modes (SF, DF and TF) |
57 | (define_mode_iterator GPF_TF [SF DF TF]) | |
58 | ||
43cacb12 | 59 | ;; Integer Advanced SIMD modes. |
43e9d192 IB |
60 | (define_mode_iterator VDQ_I [V8QI V16QI V4HI V8HI V2SI V4SI V2DI]) |
61 | ||
43cacb12 | 62 | ;; Advanced SIMD and scalar, 64 & 128-bit container, all integer modes. |
43e9d192 IB |
63 | (define_mode_iterator VSDQ_I [V8QI V16QI V4HI V8HI V2SI V4SI V2DI QI HI SI DI]) |
64 | ||
43cacb12 RS |
65 | ;; Advanced SIMD and scalar, 64 & 128-bit container: all Advanced SIMD |
66 | ;; integer modes; 64-bit scalar integer mode. | |
43e9d192 IB |
67 | (define_mode_iterator VSDQ_I_DI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI DI]) |
68 | ||
69 | ;; Double vector modes. | |
71a11456 | 70 | (define_mode_iterator VD [V8QI V4HI V4HF V2SI V2SF]) |
43e9d192 | 71 | |
dfe1da23 JW |
72 | ;; All modes stored in registers d0-d31. |
73 | (define_mode_iterator DREG [V8QI V4HI V4HF V2SI V2SF DF]) | |
74 | ||
75 | ;; Copy of the above. | |
76 | (define_mode_iterator DREG2 [V8QI V4HI V4HF V2SI V2SF DF]) | |
77 | ||
43cacb12 | 78 | ;; Advanced SIMD, 64-bit container, all integer modes. |
43e9d192 IB |
79 | (define_mode_iterator VD_BHSI [V8QI V4HI V2SI]) |
80 | ||
81 | ;; 128 and 64-bit container; 8, 16, 32-bit vector integer modes | |
82 | (define_mode_iterator VDQ_BHSI [V8QI V16QI V4HI V8HI V2SI V4SI]) | |
83 | ||
84 | ;; Quad vector modes. | |
71a11456 | 85 | (define_mode_iterator VQ [V16QI V8HI V4SI V2DI V8HF V4SF V2DF]) |
43e9d192 | 86 | |
9f5361c8 KT |
87 | ;; Copy of the above. |
88 | (define_mode_iterator VQ2 [V16QI V8HI V4SI V2DI V8HF V4SF V2DF]) | |
89 | ||
d21052eb TC |
90 | ;; Quad integer vector modes. |
91 | (define_mode_iterator VQ_I [V16QI V8HI V4SI V2DI]) | |
92 | ||
51437269 | 93 | ;; VQ without 2 element modes. |
71a11456 | 94 | (define_mode_iterator VQ_NO2E [V16QI V8HI V4SI V8HF V4SF]) |
51437269 GW |
95 | |
96 | ;; Quad vector with only 2 element modes. | |
97 | (define_mode_iterator VQ_2E [V2DI V2DF]) | |
98 | ||
28514dda YZ |
99 | ;; This mode iterator allows :P to be used for patterns that operate on |
100 | ;; addresses in different modes. In LP64, only DI will match, while in | |
101 | ;; ILP32, either can match. | |
102 | (define_mode_iterator P [(SI "ptr_mode == SImode || Pmode == SImode") | |
103 | (DI "ptr_mode == DImode || Pmode == DImode")]) | |
104 | ||
43e9d192 IB |
105 | ;; This mode iterator allows :PTR to be used for patterns that operate on |
106 | ;; pointer-sized quantities. Exactly one of the two alternatives will match. | |
28514dda | 107 | (define_mode_iterator PTR [(SI "ptr_mode == SImode") (DI "ptr_mode == DImode")]) |
43e9d192 | 108 | |
43cacb12 | 109 | ;; Advanced SIMD Float modes suitable for moving, loading and storing. |
862abc04 AL |
110 | (define_mode_iterator VDQF_F16 [V4HF V8HF V2SF V4SF V2DF]) |
111 | ||
43cacb12 | 112 | ;; Advanced SIMD Float modes. |
43e9d192 | 113 | (define_mode_iterator VDQF [V2SF V4SF V2DF]) |
daef0a8c JW |
114 | (define_mode_iterator VHSDF [(V4HF "TARGET_SIMD_F16INST") |
115 | (V8HF "TARGET_SIMD_F16INST") | |
116 | V2SF V4SF V2DF]) | |
43e9d192 | 117 | |
43cacb12 | 118 | ;; Advanced SIMD Float modes, and DF. |
daef0a8c JW |
119 | (define_mode_iterator VHSDF_DF [(V4HF "TARGET_SIMD_F16INST") |
120 | (V8HF "TARGET_SIMD_F16INST") | |
121 | V2SF V4SF V2DF DF]) | |
d7f33f07 JW |
122 | (define_mode_iterator VHSDF_HSDF [(V4HF "TARGET_SIMD_F16INST") |
123 | (V8HF "TARGET_SIMD_F16INST") | |
124 | V2SF V4SF V2DF | |
125 | (HF "TARGET_SIMD_F16INST") | |
126 | SF DF]) | |
f421c516 | 127 | |
43cacb12 | 128 | ;; Advanced SIMD single Float modes. |
828e70c1 JG |
129 | (define_mode_iterator VDQSF [V2SF V4SF]) |
130 | ||
03873eb9 AL |
131 | ;; Quad vector Float modes with half/single elements. |
132 | (define_mode_iterator VQ_HSF [V8HF V4SF]) | |
133 | ||
fc21784d JG |
134 | ;; Modes suitable to use as the return type of a vcond expression. |
135 | (define_mode_iterator VDQF_COND [V2SF V2SI V4SF V4SI V2DF V2DI]) | |
136 | ||
43cacb12 | 137 | ;; All scalar and Advanced SIMD Float modes. |
889b9412 JG |
138 | (define_mode_iterator VALLF [V2SF V4SF V2DF SF DF]) |
139 | ||
43cacb12 | 140 | ;; Advanced SIMD Float modes with 2 elements. |
43e9d192 IB |
141 | (define_mode_iterator V2F [V2SF V2DF]) |
142 | ||
43cacb12 | 143 | ;; All Advanced SIMD modes on which we support any arithmetic operations. |
43e9d192 IB |
144 | (define_mode_iterator VALL [V8QI V16QI V4HI V8HI V2SI V4SI V2DI V2SF V4SF V2DF]) |
145 | ||
43cacb12 | 146 | ;; All Advanced SIMD modes suitable for moving, loading, and storing. |
71a11456 AL |
147 | (define_mode_iterator VALL_F16 [V8QI V16QI V4HI V8HI V2SI V4SI V2DI |
148 | V4HF V8HF V2SF V4SF V2DF]) | |
149 | ||
88119b46 KT |
150 | ;; The VALL_F16 modes except the 128-bit 2-element ones. |
151 | (define_mode_iterator VALL_F16_NO_V2Q [V8QI V16QI V4HI V8HI V2SI V4SI | |
152 | V4HF V8HF V2SF V4SF]) | |
153 | ||
43cacb12 | 154 | ;; All Advanced SIMD modes barring HF modes, plus DI. |
a50344cb TB |
155 | (define_mode_iterator VALLDI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI V2SF V4SF V2DF DI]) |
156 | ||
43cacb12 | 157 | ;; All Advanced SIMD modes and DI. |
71a11456 AL |
158 | (define_mode_iterator VALLDI_F16 [V8QI V16QI V4HI V8HI V2SI V4SI V2DI |
159 | V4HF V8HF V2SF V4SF V2DF DI]) | |
160 | ||
43cacb12 | 161 | ;; All Advanced SIMD modes, plus DI and DF. |
46e778c4 | 162 | (define_mode_iterator VALLDIF [V8QI V16QI V4HI V8HI V2SI V4SI |
7c369485 | 163 | V2DI V4HF V8HF V2SF V4SF V2DF DI DF]) |
46e778c4 | 164 | |
43cacb12 | 165 | ;; Advanced SIMD modes for Integer reduction across lanes. |
92835317 TB |
166 | (define_mode_iterator VDQV [V8QI V16QI V4HI V8HI V4SI V2DI]) |
167 | ||
43cacb12 | 168 | ;; Advanced SIMD modes (except V2DI) for Integer reduction across lanes. |
92835317 | 169 | (define_mode_iterator VDQV_S [V8QI V16QI V4HI V8HI V4SI]) |
43e9d192 IB |
170 | |
171 | ;; All double integer narrow-able modes. | |
172 | (define_mode_iterator VDN [V4HI V2SI DI]) | |
173 | ||
174 | ;; All quad integer narrow-able modes. | |
175 | (define_mode_iterator VQN [V8HI V4SI V2DI]) | |
176 | ||
43cacb12 RS |
177 | ;; Advanced SIMD and scalar 128-bit container: narrowable 16, 32, 64-bit |
178 | ;; integer modes | |
43e9d192 IB |
179 | (define_mode_iterator VSQN_HSDI [V8HI V4SI V2DI HI SI DI]) |
180 | ||
181 | ;; All quad integer widen-able modes. | |
182 | (define_mode_iterator VQW [V16QI V8HI V4SI]) | |
183 | ||
184 | ;; Double vector modes for combines. | |
7c369485 | 185 | (define_mode_iterator VDC [V8QI V4HI V4HF V2SI V2SF DI DF]) |
43e9d192 | 186 | |
43cacb12 | 187 | ;; Advanced SIMD modes except double int. |
43e9d192 | 188 | (define_mode_iterator VDQIF [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF V2DF]) |
703bbcdf JW |
189 | (define_mode_iterator VDQIF_F16 [V8QI V16QI V4HI V8HI V2SI V4SI |
190 | V4HF V8HF V2SF V4SF V2DF]) | |
43e9d192 | 191 | |
43cacb12 | 192 | ;; Advanced SIMD modes for S type. |
58a3bd25 FY |
193 | (define_mode_iterator VDQ_SI [V2SI V4SI]) |
194 | ||
43cacb12 | 195 | ;; Advanced SIMD modes for S and D. |
2644d4d9 JW |
196 | (define_mode_iterator VDQ_SDI [V2SI V4SI V2DI]) |
197 | ||
43cacb12 | 198 | ;; Advanced SIMD modes for H, S and D. |
33d72b63 JW |
199 | (define_mode_iterator VDQ_HSDI [(V4HI "TARGET_SIMD_F16INST") |
200 | (V8HI "TARGET_SIMD_F16INST") | |
201 | V2SI V4SI V2DI]) | |
202 | ||
43cacb12 | 203 | ;; Scalar and Advanced SIMD modes for S and D. |
2644d4d9 JW |
204 | (define_mode_iterator VSDQ_SDI [V2SI V4SI V2DI SI DI]) |
205 | ||
43cacb12 | 206 | ;; Scalar and Advanced SIMD modes for S and D, Advanced SIMD modes for H. |
33d72b63 JW |
207 | (define_mode_iterator VSDQ_HSDI [(V4HI "TARGET_SIMD_F16INST") |
208 | (V8HI "TARGET_SIMD_F16INST") | |
68ad28c3 JW |
209 | V2SI V4SI V2DI |
210 | (HI "TARGET_SIMD_F16INST") | |
211 | SI DI]) | |
33d72b63 | 212 | |
43cacb12 | 213 | ;; Advanced SIMD modes for Q and H types. |
66adb8eb JG |
214 | (define_mode_iterator VDQQH [V8QI V16QI V4HI V8HI]) |
215 | ||
43cacb12 | 216 | ;; Advanced SIMD modes for H and S types. |
43e9d192 IB |
217 | (define_mode_iterator VDQHS [V4HI V8HI V2SI V4SI]) |
218 | ||
43cacb12 | 219 | ;; Advanced SIMD modes for H, S and D types. |
c7f28cd5 KT |
220 | (define_mode_iterator VDQHSD [V4HI V8HI V2SI V4SI V2DI]) |
221 | ||
43cacb12 | 222 | ;; Advanced SIMD and scalar integer modes for H and S. |
43e9d192 IB |
223 | (define_mode_iterator VSDQ_HSI [V4HI V8HI V2SI V4SI HI SI]) |
224 | ||
43cacb12 | 225 | ;; Advanced SIMD and scalar 64-bit container: 16, 32-bit integer modes. |
43e9d192 IB |
226 | (define_mode_iterator VSD_HSI [V4HI V2SI HI SI]) |
227 | ||
43cacb12 | 228 | ;; Advanced SIMD 64-bit container: 16, 32-bit integer modes. |
43e9d192 IB |
229 | (define_mode_iterator VD_HSI [V4HI V2SI]) |
230 | ||
231 | ;; Scalar 64-bit container: 16, 32-bit integer modes | |
232 | (define_mode_iterator SD_HSI [HI SI]) | |
233 | ||
43cacb12 | 234 | ;; Advanced SIMD 64-bit container: 16, 32-bit integer modes. |
43e9d192 IB |
235 | (define_mode_iterator VQ_HSI [V8HI V4SI]) |
236 | ||
237 | ;; All byte modes. | |
238 | (define_mode_iterator VB [V8QI V16QI]) | |
239 | ||
5e32e83b JW |
240 | ;; 2 and 4 lane SI modes. |
241 | (define_mode_iterator VS [V2SI V4SI]) | |
242 | ||
43e9d192 IB |
243 | (define_mode_iterator TX [TI TF]) |
244 | ||
43cacb12 | 245 | ;; Advanced SIMD opaque structure modes. |
43e9d192 IB |
246 | (define_mode_iterator VSTRUCT [OI CI XI]) |
247 | ||
248 | ;; Double scalar modes | |
249 | (define_mode_iterator DX [DI DF]) | |
250 | ||
dfe1da23 JW |
251 | ;; Duplicate of the above |
252 | (define_mode_iterator DX2 [DI DF]) | |
253 | ||
254 | ;; Single scalar modes | |
255 | (define_mode_iterator SX [SI SF]) | |
256 | ||
257 | ;; Duplicate of the above | |
258 | (define_mode_iterator SX2 [SI SF]) | |
259 | ||
260 | ;; Single and double integer and float modes | |
261 | (define_mode_iterator DSX [DF DI SF SI]) | |
262 | ||
263 | ||
43cacb12 | 264 | ;; Modes available for Advanced SIMD <f>mul lane operations. |
ab2e8f01 JW |
265 | (define_mode_iterator VMUL [V4HI V8HI V2SI V4SI |
266 | (V4HF "TARGET_SIMD_F16INST") | |
267 | (V8HF "TARGET_SIMD_F16INST") | |
268 | V2SF V4SF V2DF]) | |
779aea46 | 269 | |
43cacb12 RS |
270 | ;; Modes available for Advanced SIMD <f>mul lane operations changing lane |
271 | ;; count. | |
779aea46 JG |
272 | (define_mode_iterator VMUL_CHANGE_NLANES [V4HI V8HI V2SI V4SI V2SF V4SF]) |
273 | ||
43cacb12 RS |
274 | ;; All SVE vector modes. |
275 | (define_mode_iterator SVE_ALL [VNx16QI VNx8HI VNx4SI VNx2DI | |
276 | VNx8HF VNx4SF VNx2DF]) | |
277 | ||
9f4cbab8 RS |
278 | ;; All SVE vector structure modes. |
279 | (define_mode_iterator SVE_STRUCT [VNx32QI VNx16HI VNx8SI VNx4DI | |
280 | VNx16HF VNx8SF VNx4DF | |
281 | VNx48QI VNx24HI VNx12SI VNx6DI | |
282 | VNx24HF VNx12SF VNx6DF | |
283 | VNx64QI VNx32HI VNx16SI VNx8DI | |
284 | VNx32HF VNx16SF VNx8DF]) | |
285 | ||
43cacb12 RS |
286 | ;; All SVE vector modes that have 8-bit or 16-bit elements. |
287 | (define_mode_iterator SVE_BH [VNx16QI VNx8HI VNx8HF]) | |
288 | ||
289 | ;; All SVE vector modes that have 8-bit, 16-bit or 32-bit elements. | |
290 | (define_mode_iterator SVE_BHS [VNx16QI VNx8HI VNx4SI VNx8HF VNx4SF]) | |
291 | ||
292 | ;; All SVE integer vector modes that have 8-bit, 16-bit or 32-bit elements. | |
293 | (define_mode_iterator SVE_BHSI [VNx16QI VNx8HI VNx4SI]) | |
294 | ||
295 | ;; All SVE integer vector modes that have 16-bit, 32-bit or 64-bit elements. | |
296 | (define_mode_iterator SVE_HSDI [VNx16QI VNx8HI VNx4SI]) | |
297 | ||
298 | ;; All SVE floating-point vector modes that have 16-bit or 32-bit elements. | |
299 | (define_mode_iterator SVE_HSF [VNx8HF VNx4SF]) | |
300 | ||
301 | ;; All SVE vector modes that have 32-bit or 64-bit elements. | |
302 | (define_mode_iterator SVE_SD [VNx4SI VNx2DI VNx4SF VNx2DF]) | |
303 | ||
bfaa08b7 RS |
304 | ;; All SVE vector modes that have 32-bit elements. |
305 | (define_mode_iterator SVE_S [VNx4SI VNx4SF]) | |
306 | ||
307 | ;; All SVE vector modes that have 64-bit elements. | |
308 | (define_mode_iterator SVE_D [VNx2DI VNx2DF]) | |
309 | ||
43cacb12 RS |
310 | ;; All SVE integer vector modes that have 32-bit or 64-bit elements. |
311 | (define_mode_iterator SVE_SDI [VNx4SI VNx2DI]) | |
312 | ||
313 | ;; All SVE integer vector modes. | |
314 | (define_mode_iterator SVE_I [VNx16QI VNx8HI VNx4SI VNx2DI]) | |
315 | ||
316 | ;; All SVE floating-point vector modes. | |
317 | (define_mode_iterator SVE_F [VNx8HF VNx4SF VNx2DF]) | |
318 | ||
319 | ;; All SVE predicate modes. | |
320 | (define_mode_iterator PRED_ALL [VNx16BI VNx8BI VNx4BI VNx2BI]) | |
321 | ||
322 | ;; SVE predicate modes that control 8-bit, 16-bit or 32-bit elements. | |
323 | (define_mode_iterator PRED_BHS [VNx16BI VNx8BI VNx4BI]) | |
324 | ||
43e9d192 IB |
325 | ;; ------------------------------------------------------------------ |
326 | ;; Unspec enumerations for Advance SIMD. These could well go into | |
327 | ;; aarch64.md but for their use in int_iterators here. | |
328 | ;; ------------------------------------------------------------------ | |
329 | ||
330 | (define_c_enum "unspec" | |
331 | [ | |
332 | UNSPEC_ASHIFT_SIGNED ; Used in aarch-simd.md. | |
333 | UNSPEC_ASHIFT_UNSIGNED ; Used in aarch64-simd.md. | |
285398d2 | 334 | UNSPEC_ABS ; Used in aarch64-simd.md. |
998eaf97 JG |
335 | UNSPEC_FMAX ; Used in aarch64-simd.md. |
336 | UNSPEC_FMAXNMV ; Used in aarch64-simd.md. | |
43e9d192 | 337 | UNSPEC_FMAXV ; Used in aarch64-simd.md. |
998eaf97 JG |
338 | UNSPEC_FMIN ; Used in aarch64-simd.md. |
339 | UNSPEC_FMINNMV ; Used in aarch64-simd.md. | |
43e9d192 IB |
340 | UNSPEC_FMINV ; Used in aarch64-simd.md. |
341 | UNSPEC_FADDV ; Used in aarch64-simd.md. | |
f5156c3e | 342 | UNSPEC_ADDV ; Used in aarch64-simd.md. |
43e9d192 IB |
343 | UNSPEC_SMAXV ; Used in aarch64-simd.md. |
344 | UNSPEC_SMINV ; Used in aarch64-simd.md. | |
345 | UNSPEC_UMAXV ; Used in aarch64-simd.md. | |
346 | UNSPEC_UMINV ; Used in aarch64-simd.md. | |
347 | UNSPEC_SHADD ; Used in aarch64-simd.md. | |
348 | UNSPEC_UHADD ; Used in aarch64-simd.md. | |
349 | UNSPEC_SRHADD ; Used in aarch64-simd.md. | |
350 | UNSPEC_URHADD ; Used in aarch64-simd.md. | |
351 | UNSPEC_SHSUB ; Used in aarch64-simd.md. | |
352 | UNSPEC_UHSUB ; Used in aarch64-simd.md. | |
353 | UNSPEC_SRHSUB ; Used in aarch64-simd.md. | |
354 | UNSPEC_URHSUB ; Used in aarch64-simd.md. | |
355 | UNSPEC_ADDHN ; Used in aarch64-simd.md. | |
356 | UNSPEC_RADDHN ; Used in aarch64-simd.md. | |
357 | UNSPEC_SUBHN ; Used in aarch64-simd.md. | |
358 | UNSPEC_RSUBHN ; Used in aarch64-simd.md. | |
359 | UNSPEC_ADDHN2 ; Used in aarch64-simd.md. | |
360 | UNSPEC_RADDHN2 ; Used in aarch64-simd.md. | |
361 | UNSPEC_SUBHN2 ; Used in aarch64-simd.md. | |
362 | UNSPEC_RSUBHN2 ; Used in aarch64-simd.md. | |
363 | UNSPEC_SQDMULH ; Used in aarch64-simd.md. | |
364 | UNSPEC_SQRDMULH ; Used in aarch64-simd.md. | |
365 | UNSPEC_PMUL ; Used in aarch64-simd.md. | |
496ea87d | 366 | UNSPEC_FMULX ; Used in aarch64-simd.md. |
43e9d192 IB |
367 | UNSPEC_USQADD ; Used in aarch64-simd.md. |
368 | UNSPEC_SUQADD ; Used in aarch64-simd.md. | |
369 | UNSPEC_SQXTUN ; Used in aarch64-simd.md. | |
370 | UNSPEC_SQXTN ; Used in aarch64-simd.md. | |
371 | UNSPEC_UQXTN ; Used in aarch64-simd.md. | |
372 | UNSPEC_SSRA ; Used in aarch64-simd.md. | |
373 | UNSPEC_USRA ; Used in aarch64-simd.md. | |
374 | UNSPEC_SRSRA ; Used in aarch64-simd.md. | |
375 | UNSPEC_URSRA ; Used in aarch64-simd.md. | |
376 | UNSPEC_SRSHR ; Used in aarch64-simd.md. | |
377 | UNSPEC_URSHR ; Used in aarch64-simd.md. | |
378 | UNSPEC_SQSHLU ; Used in aarch64-simd.md. | |
379 | UNSPEC_SQSHL ; Used in aarch64-simd.md. | |
380 | UNSPEC_UQSHL ; Used in aarch64-simd.md. | |
381 | UNSPEC_SQSHRUN ; Used in aarch64-simd.md. | |
382 | UNSPEC_SQRSHRUN ; Used in aarch64-simd.md. | |
383 | UNSPEC_SQSHRN ; Used in aarch64-simd.md. | |
384 | UNSPEC_UQSHRN ; Used in aarch64-simd.md. | |
385 | UNSPEC_SQRSHRN ; Used in aarch64-simd.md. | |
386 | UNSPEC_UQRSHRN ; Used in aarch64-simd.md. | |
387 | UNSPEC_SSHL ; Used in aarch64-simd.md. | |
388 | UNSPEC_USHL ; Used in aarch64-simd.md. | |
389 | UNSPEC_SRSHL ; Used in aarch64-simd.md. | |
390 | UNSPEC_URSHL ; Used in aarch64-simd.md. | |
391 | UNSPEC_SQRSHL ; Used in aarch64-simd.md. | |
392 | UNSPEC_UQRSHL ; Used in aarch64-simd.md. | |
43e9d192 IB |
393 | UNSPEC_SSLI ; Used in aarch64-simd.md. |
394 | UNSPEC_USLI ; Used in aarch64-simd.md. | |
395 | UNSPEC_SSRI ; Used in aarch64-simd.md. | |
396 | UNSPEC_USRI ; Used in aarch64-simd.md. | |
397 | UNSPEC_SSHLL ; Used in aarch64-simd.md. | |
398 | UNSPEC_USHLL ; Used in aarch64-simd.md. | |
399 | UNSPEC_ADDP ; Used in aarch64-simd.md. | |
88b08073 | 400 | UNSPEC_TBL ; Used in vector permute patterns. |
9371aecc | 401 | UNSPEC_TBX ; Used in vector permute patterns. |
88b08073 | 402 | UNSPEC_CONCAT ; Used in vector permute patterns. |
3f8334a5 RS |
403 | |
404 | ;; The following permute unspecs are generated directly by | |
405 | ;; aarch64_expand_vec_perm_const, so any changes to the underlying | |
406 | ;; instructions would need a corresponding change there. | |
cc4d934f JG |
407 | UNSPEC_ZIP1 ; Used in vector permute patterns. |
408 | UNSPEC_ZIP2 ; Used in vector permute patterns. | |
409 | UNSPEC_UZP1 ; Used in vector permute patterns. | |
410 | UNSPEC_UZP2 ; Used in vector permute patterns. | |
411 | UNSPEC_TRN1 ; Used in vector permute patterns. | |
412 | UNSPEC_TRN2 ; Used in vector permute patterns. | |
3f8334a5 | 413 | UNSPEC_EXT ; Used in vector permute patterns. |
923fcec3 AL |
414 | UNSPEC_REV64 ; Used in vector reverse patterns (permute). |
415 | UNSPEC_REV32 ; Used in vector reverse patterns (permute). | |
416 | UNSPEC_REV16 ; Used in vector reverse patterns (permute). | |
3f8334a5 | 417 | |
5a7a4e80 TB |
418 | UNSPEC_AESE ; Used in aarch64-simd.md. |
419 | UNSPEC_AESD ; Used in aarch64-simd.md. | |
420 | UNSPEC_AESMC ; Used in aarch64-simd.md. | |
421 | UNSPEC_AESIMC ; Used in aarch64-simd.md. | |
30442682 TB |
422 | UNSPEC_SHA1C ; Used in aarch64-simd.md. |
423 | UNSPEC_SHA1M ; Used in aarch64-simd.md. | |
424 | UNSPEC_SHA1P ; Used in aarch64-simd.md. | |
425 | UNSPEC_SHA1H ; Used in aarch64-simd.md. | |
426 | UNSPEC_SHA1SU0 ; Used in aarch64-simd.md. | |
427 | UNSPEC_SHA1SU1 ; Used in aarch64-simd.md. | |
b9cb0a44 TB |
428 | UNSPEC_SHA256H ; Used in aarch64-simd.md. |
429 | UNSPEC_SHA256H2 ; Used in aarch64-simd.md. | |
430 | UNSPEC_SHA256SU0 ; Used in aarch64-simd.md. | |
431 | UNSPEC_SHA256SU1 ; Used in aarch64-simd.md. | |
7baa225d TB |
432 | UNSPEC_PMULL ; Used in aarch64-simd.md. |
433 | UNSPEC_PMULL2 ; Used in aarch64-simd.md. | |
668046d1 | 434 | UNSPEC_REV_REGLIST ; Used in aarch64-simd.md. |
9c004c58 | 435 | UNSPEC_VEC_SHR ; Used in aarch64-simd.md. |
57b26d65 MW |
436 | UNSPEC_SQRDMLAH ; Used in aarch64-simd.md. |
437 | UNSPEC_SQRDMLSH ; Used in aarch64-simd.md. | |
202d0c11 DS |
438 | UNSPEC_FMAXNM ; Used in aarch64-simd.md. |
439 | UNSPEC_FMINNM ; Used in aarch64-simd.md. | |
7a08d813 TC |
440 | UNSPEC_SDOT ; Used in aarch64-simd.md. |
441 | UNSPEC_UDOT ; Used in aarch64-simd.md. | |
27086ea3 MC |
442 | UNSPEC_SM3SS1 ; Used in aarch64-simd.md. |
443 | UNSPEC_SM3TT1A ; Used in aarch64-simd.md. | |
444 | UNSPEC_SM3TT1B ; Used in aarch64-simd.md. | |
445 | UNSPEC_SM3TT2A ; Used in aarch64-simd.md. | |
446 | UNSPEC_SM3TT2B ; Used in aarch64-simd.md. | |
447 | UNSPEC_SM3PARTW1 ; Used in aarch64-simd.md. | |
448 | UNSPEC_SM3PARTW2 ; Used in aarch64-simd.md. | |
449 | UNSPEC_SM4E ; Used in aarch64-simd.md. | |
450 | UNSPEC_SM4EKEY ; Used in aarch64-simd.md. | |
451 | UNSPEC_SHA512H ; Used in aarch64-simd.md. | |
452 | UNSPEC_SHA512H2 ; Used in aarch64-simd.md. | |
453 | UNSPEC_SHA512SU0 ; Used in aarch64-simd.md. | |
454 | UNSPEC_SHA512SU1 ; Used in aarch64-simd.md. | |
455 | UNSPEC_FMLAL ; Used in aarch64-simd.md. | |
456 | UNSPEC_FMLSL ; Used in aarch64-simd.md. | |
457 | UNSPEC_FMLAL2 ; Used in aarch64-simd.md. | |
458 | UNSPEC_FMLSL2 ; Used in aarch64-simd.md. | |
43cacb12 | 459 | UNSPEC_SEL ; Used in aarch64-sve.md. |
898f07b0 RS |
460 | UNSPEC_ANDV ; Used in aarch64-sve.md. |
461 | UNSPEC_IORV ; Used in aarch64-sve.md. | |
462 | UNSPEC_XORV ; Used in aarch64-sve.md. | |
43cacb12 RS |
463 | UNSPEC_ANDF ; Used in aarch64-sve.md. |
464 | UNSPEC_IORF ; Used in aarch64-sve.md. | |
465 | UNSPEC_XORF ; Used in aarch64-sve.md. | |
11e9443f RS |
466 | UNSPEC_SMUL_HIGHPART ; Used in aarch64-sve.md. |
467 | UNSPEC_UMUL_HIGHPART ; Used in aarch64-sve.md. | |
0972596e RS |
468 | UNSPEC_COND_ADD ; Used in aarch64-sve.md. |
469 | UNSPEC_COND_SUB ; Used in aarch64-sve.md. | |
6c4fd4a9 RS |
470 | UNSPEC_COND_MUL ; Used in aarch64-sve.md. |
471 | UNSPEC_COND_DIV ; Used in aarch64-sve.md. | |
0d2b3bca RS |
472 | UNSPEC_COND_MAX ; Used in aarch64-sve.md. |
473 | UNSPEC_COND_MIN ; Used in aarch64-sve.md. | |
43cacb12 RS |
474 | UNSPEC_COND_LT ; Used in aarch64-sve.md. |
475 | UNSPEC_COND_LE ; Used in aarch64-sve.md. | |
476 | UNSPEC_COND_EQ ; Used in aarch64-sve.md. | |
477 | UNSPEC_COND_NE ; Used in aarch64-sve.md. | |
478 | UNSPEC_COND_GE ; Used in aarch64-sve.md. | |
479 | UNSPEC_COND_GT ; Used in aarch64-sve.md. | |
43cacb12 | 480 | UNSPEC_LASTB ; Used in aarch64-sve.md. |
43e9d192 IB |
481 | ]) |
482 | ||
d81cb613 MW |
483 | ;; ------------------------------------------------------------------ |
484 | ;; Unspec enumerations for Atomics. They are here so that they can be | |
485 | ;; used in the int_iterators for atomic operations. | |
486 | ;; ------------------------------------------------------------------ | |
487 | ||
488 | (define_c_enum "unspecv" | |
489 | [ | |
490 | UNSPECV_LX ; Represent a load-exclusive. | |
491 | UNSPECV_SX ; Represent a store-exclusive. | |
492 | UNSPECV_LDA ; Represent an atomic load or load-acquire. | |
493 | UNSPECV_STL ; Represent an atomic store or store-release. | |
494 | UNSPECV_ATOMIC_CMPSW ; Represent an atomic compare swap. | |
495 | UNSPECV_ATOMIC_EXCHG ; Represent an atomic exchange. | |
496 | UNSPECV_ATOMIC_CAS ; Represent an atomic CAS. | |
497 | UNSPECV_ATOMIC_SWP ; Represent an atomic SWP. | |
498 | UNSPECV_ATOMIC_OP ; Represent an atomic operation. | |
499 | UNSPECV_ATOMIC_LDOP ; Represent an atomic load-operation | |
500 | UNSPECV_ATOMIC_LDOP_OR ; Represent an atomic load-or | |
501 | UNSPECV_ATOMIC_LDOP_BIC ; Represent an atomic load-bic | |
502 | UNSPECV_ATOMIC_LDOP_XOR ; Represent an atomic load-xor | |
503 | UNSPECV_ATOMIC_LDOP_PLUS ; Represent an atomic load-add | |
504 | ]) | |
505 | ||
43e9d192 IB |
506 | ;; ------------------------------------------------------------------- |
507 | ;; Mode attributes | |
508 | ;; ------------------------------------------------------------------- | |
509 | ||
510 | ;; In GPI templates, a string like "%<w>0" will expand to "%w0" in the | |
511 | ;; 32-bit version and "%x0" in the 64-bit version. | |
512 | (define_mode_attr w [(QI "w") (HI "w") (SI "w") (DI "x") (SF "s") (DF "d")]) | |
513 | ||
db46a2e6 JG |
514 | ;; The size of access, in bytes. |
515 | (define_mode_attr ldst_sz [(SI "4") (DI "8")]) | |
516 | ;; Likewise for load/store pair. | |
517 | (define_mode_attr ldpstp_sz [(SI "8") (DI "16")]) | |
518 | ||
0d35c5c2 | 519 | ;; For inequal width int to float conversion |
d7f33f07 JW |
520 | (define_mode_attr w1 [(HF "w") (SF "w") (DF "x")]) |
521 | (define_mode_attr w2 [(HF "x") (SF "x") (DF "w")]) | |
0d35c5c2 | 522 | |
22be0d08 MC |
523 | ;; For width of fp registers in fcvt instruction |
524 | (define_mode_attr fpw [(DI "s") (SI "d")]) | |
525 | ||
2b8568fe KT |
526 | (define_mode_attr short_mask [(HI "65535") (QI "255")]) |
527 | ||
051d0e2f SN |
528 | ;; For constraints used in scalar immediate vector moves |
529 | (define_mode_attr hq [(HI "h") (QI "q")]) | |
530 | ||
ef22810a RH |
531 | ;; For doubling width of an integer mode |
532 | (define_mode_attr DWI [(QI "HI") (HI "SI") (SI "DI") (DI "TI")]) | |
533 | ||
22be0d08 MC |
534 | (define_mode_attr fcvt_change_mode [(SI "df") (DI "sf")]) |
535 | ||
536 | (define_mode_attr FCVT_CHANGE_MODE [(SI "DF") (DI "SF")]) | |
537 | ||
43e9d192 IB |
538 | ;; For scalar usage of vector/FP registers |
539 | (define_mode_attr v [(QI "b") (HI "h") (SI "s") (DI "d") | |
d7f33f07 | 540 | (HF "h") (SF "s") (DF "d") |
43e9d192 IB |
541 | (V8QI "") (V16QI "") |
542 | (V4HI "") (V8HI "") | |
543 | (V2SI "") (V4SI "") | |
544 | (V2DI "") (V2SF "") | |
daef0a8c JW |
545 | (V4SF "") (V4HF "") |
546 | (V8HF "") (V2DF "")]) | |
43e9d192 IB |
547 | |
548 | ;; For scalar usage of vector/FP registers, narrowing | |
549 | (define_mode_attr vn2 [(QI "") (HI "b") (SI "h") (DI "s") | |
550 | (V8QI "") (V16QI "") | |
551 | (V4HI "") (V8HI "") | |
552 | (V2SI "") (V4SI "") | |
553 | (V2DI "") (V2SF "") | |
554 | (V4SF "") (V2DF "")]) | |
555 | ||
556 | ;; For scalar usage of vector/FP registers, widening | |
557 | (define_mode_attr vw2 [(DI "") (QI "h") (HI "s") (SI "d") | |
558 | (V8QI "") (V16QI "") | |
559 | (V4HI "") (V8HI "") | |
560 | (V2SI "") (V4SI "") | |
561 | (V2DI "") (V2SF "") | |
562 | (V4SF "") (V2DF "")]) | |
563 | ||
89fdc743 IB |
564 | ;; Register Type Name and Vector Arrangement Specifier for when |
565 | ;; we are doing scalar for DI and SIMD for SI (ignoring all but | |
566 | ;; lane 0). | |
567 | (define_mode_attr rtn [(DI "d") (SI "")]) | |
568 | (define_mode_attr vas [(DI "") (SI ".2s")]) | |
569 | ||
7ac29c0f RS |
570 | ;; Map a vector to the number of units in it, if the size of the mode |
571 | ;; is constant. | |
572 | (define_mode_attr nunits [(V8QI "8") (V16QI "16") | |
573 | (V4HI "4") (V8HI "8") | |
574 | (V2SI "2") (V4SI "4") | |
575 | (V2DI "2") | |
576 | (V4HF "4") (V8HF "8") | |
577 | (V2SF "2") (V4SF "4") | |
578 | (V1DF "1") (V2DF "2") | |
579 | (DI "1") (DF "1")]) | |
580 | ||
b187677b RS |
581 | ;; Map a mode to the number of bits in it, if the size of the mode |
582 | ;; is constant. | |
583 | (define_mode_attr bitsize [(V8QI "64") (V16QI "128") | |
584 | (V4HI "64") (V8HI "128") | |
585 | (V2SI "64") (V4SI "128") | |
586 | (V2DI "128")]) | |
587 | ||
22be0d08 MC |
588 | ;; Map a floating point or integer mode to the appropriate register name prefix |
589 | (define_mode_attr s [(HF "h") (SF "s") (DF "d") (SI "s") (DI "d")]) | |
43e9d192 IB |
590 | |
591 | ;; Give the length suffix letter for a sign- or zero-extension. | |
592 | (define_mode_attr size [(QI "b") (HI "h") (SI "w")]) | |
593 | ||
594 | ;; Give the number of bits in the mode | |
595 | (define_mode_attr sizen [(QI "8") (HI "16") (SI "32") (DI "64")]) | |
596 | ||
597 | ;; Give the ordinal of the MSB in the mode | |
598 | (define_mode_attr sizem1 [(QI "#7") (HI "#15") (SI "#31") (DI "#63")]) | |
599 | ||
600 | ;; Attribute to describe constants acceptable in logical operations | |
601 | (define_mode_attr lconst [(SI "K") (DI "L")]) | |
602 | ||
43fd192f MC |
603 | ;; Attribute to describe constants acceptable in logical and operations |
604 | (define_mode_attr lconst2 [(SI "UsO") (DI "UsP")]) | |
605 | ||
43e9d192 IB |
606 | ;; Map a mode to a specific constraint character. |
607 | (define_mode_attr cmode [(QI "q") (HI "h") (SI "s") (DI "d")]) | |
608 | ||
0603375c KT |
609 | ;; Map modes to Usg and Usj constraints for SISD right shifts |
610 | (define_mode_attr cmode_simd [(SI "g") (DI "j")]) | |
611 | ||
43e9d192 IB |
612 | (define_mode_attr Vtype [(V8QI "8b") (V16QI "16b") |
613 | (V4HI "4h") (V8HI "8h") | |
614 | (V2SI "2s") (V4SI "4s") | |
615 | (DI "1d") (DF "1d") | |
616 | (V2DI "2d") (V2SF "2s") | |
7c369485 AL |
617 | (V4SF "4s") (V2DF "2d") |
618 | (V4HF "4h") (V8HF "8h")]) | |
43e9d192 | 619 | |
c7f28cd5 KT |
620 | (define_mode_attr Vrevsuff [(V4HI "16") (V8HI "16") (V2SI "32") |
621 | (V4SI "32") (V2DI "64")]) | |
622 | ||
43e9d192 IB |
623 | (define_mode_attr Vmtype [(V8QI ".8b") (V16QI ".16b") |
624 | (V4HI ".4h") (V8HI ".8h") | |
625 | (V2SI ".2s") (V4SI ".4s") | |
71a11456 AL |
626 | (V2DI ".2d") (V4HF ".4h") |
627 | (V8HF ".8h") (V2SF ".2s") | |
43e9d192 IB |
628 | (V4SF ".4s") (V2DF ".2d") |
629 | (DI "") (SI "") | |
630 | (HI "") (QI "") | |
d7f33f07 JW |
631 | (TI "") (HF "") |
632 | (SF "") (DF "")]) | |
43e9d192 IB |
633 | |
634 | ;; Register suffix narrowed modes for VQN. | |
635 | (define_mode_attr Vmntype [(V8HI ".8b") (V4SI ".4h") | |
636 | (V2DI ".2s") | |
637 | (DI "") (SI "") | |
638 | (HI "")]) | |
639 | ||
640 | ;; Mode-to-individual element type mapping. | |
43cacb12 RS |
641 | (define_mode_attr Vetype [(V8QI "b") (V16QI "b") (VNx16QI "b") (VNx16BI "b") |
642 | (V4HI "h") (V8HI "h") (VNx8HI "h") (VNx8BI "h") | |
643 | (V2SI "s") (V4SI "s") (VNx4SI "s") (VNx4BI "s") | |
644 | (V2DI "d") (VNx2DI "d") (VNx2BI "d") | |
645 | (V4HF "h") (V8HF "h") (VNx8HF "h") | |
646 | (V2SF "s") (V4SF "s") (VNx4SF "s") | |
647 | (V2DF "d") (VNx2DF "d") | |
d7f33f07 | 648 | (HF "h") |
0f686aa9 | 649 | (SF "s") (DF "d") |
43e9d192 IB |
650 | (QI "b") (HI "h") |
651 | (SI "s") (DI "d")]) | |
652 | ||
43cacb12 RS |
653 | ;; Equivalent of "size" for a vector element. |
654 | (define_mode_attr Vesize [(VNx16QI "b") | |
9f4cbab8 RS |
655 | (VNx8HI "h") (VNx8HF "h") |
656 | (VNx4SI "w") (VNx4SF "w") | |
657 | (VNx2DI "d") (VNx2DF "d") | |
658 | (VNx32QI "b") (VNx48QI "b") (VNx64QI "b") | |
659 | (VNx16HI "h") (VNx24HI "h") (VNx32HI "h") | |
660 | (VNx16HF "h") (VNx24HF "h") (VNx32HF "h") | |
661 | (VNx8SI "w") (VNx12SI "w") (VNx16SI "w") | |
662 | (VNx8SF "w") (VNx12SF "w") (VNx16SF "w") | |
663 | (VNx4DI "d") (VNx6DI "d") (VNx8DI "d") | |
664 | (VNx4DF "d") (VNx6DF "d") (VNx8DF "d")]) | |
43cacb12 | 665 | |
daef0a8c JW |
666 | ;; Vetype is used everywhere in scheduling type and assembly output, |
667 | ;; sometimes they are not the same, for example HF modes on some | |
668 | ;; instructions. stype is defined to represent scheduling type | |
669 | ;; more accurately. | |
670 | (define_mode_attr stype [(V8QI "b") (V16QI "b") (V4HI "s") (V8HI "s") | |
671 | (V2SI "s") (V4SI "s") (V2DI "d") (V4HF "s") | |
672 | (V8HF "s") (V2SF "s") (V4SF "s") (V2DF "d") | |
673 | (HF "s") (SF "s") (DF "d") (QI "b") (HI "s") | |
674 | (SI "s") (DI "d")]) | |
675 | ||
43e9d192 IB |
676 | ;; Mode-to-bitwise operation type mapping. |
677 | (define_mode_attr Vbtype [(V8QI "8b") (V16QI "16b") | |
678 | (V4HI "8b") (V8HI "16b") | |
679 | (V2SI "8b") (V4SI "16b") | |
7c369485 AL |
680 | (V2DI "16b") (V4HF "8b") |
681 | (V8HF "16b") (V2SF "8b") | |
46e778c4 | 682 | (V4SF "16b") (V2DF "16b") |
fe82d1f2 AL |
683 | (DI "8b") (DF "8b") |
684 | (SI "8b")]) | |
43e9d192 IB |
685 | |
686 | ;; Define element mode for each vector mode. | |
43cacb12 RS |
687 | (define_mode_attr VEL [(V8QI "QI") (V16QI "QI") (VNx16QI "QI") |
688 | (V4HI "HI") (V8HI "HI") (VNx8HI "HI") | |
689 | (V2SI "SI") (V4SI "SI") (VNx4SI "SI") | |
690 | (DI "DI") (V2DI "DI") (VNx2DI "DI") | |
691 | (V4HF "HF") (V8HF "HF") (VNx8HF "HF") | |
692 | (V2SF "SF") (V4SF "SF") (VNx4SF "SF") | |
693 | (DF "DF") (V2DF "DF") (VNx2DF "DF") | |
694 | (SI "SI") (HI "HI") | |
43e9d192 IB |
695 | (QI "QI")]) |
696 | ||
ff03930a | 697 | ;; Define element mode for each vector mode (lower case). |
43cacb12 RS |
698 | (define_mode_attr Vel [(V8QI "qi") (V16QI "qi") (VNx16QI "qi") |
699 | (V4HI "hi") (V8HI "hi") (VNx8HI "hi") | |
700 | (V2SI "si") (V4SI "si") (VNx4SI "si") | |
701 | (DI "di") (V2DI "di") (VNx2DI "di") | |
702 | (V4HF "hf") (V8HF "hf") (VNx8HF "hf") | |
703 | (V2SF "sf") (V4SF "sf") (VNx4SF "sf") | |
704 | (V2DF "df") (DF "df") (VNx2DF "df") | |
ff03930a JJ |
705 | (SI "si") (HI "hi") |
706 | (QI "qi")]) | |
707 | ||
43cacb12 RS |
708 | ;; Element mode with floating-point values replaced by like-sized integers. |
709 | (define_mode_attr VEL_INT [(VNx16QI "QI") | |
710 | (VNx8HI "HI") (VNx8HF "HI") | |
711 | (VNx4SI "SI") (VNx4SF "SI") | |
712 | (VNx2DI "DI") (VNx2DF "DI")]) | |
713 | ||
714 | ;; Gives the mode of the 128-bit lowpart of an SVE vector. | |
715 | (define_mode_attr V128 [(VNx16QI "V16QI") | |
716 | (VNx8HI "V8HI") (VNx8HF "V8HF") | |
717 | (VNx4SI "V4SI") (VNx4SF "V4SF") | |
718 | (VNx2DI "V2DI") (VNx2DF "V2DF")]) | |
719 | ||
720 | ;; ...and again in lower case. | |
721 | (define_mode_attr v128 [(VNx16QI "v16qi") | |
722 | (VNx8HI "v8hi") (VNx8HF "v8hf") | |
723 | (VNx4SI "v4si") (VNx4SF "v4sf") | |
724 | (VNx2DI "v2di") (VNx2DF "v2df")]) | |
725 | ||
278821f2 KT |
726 | ;; 64-bit container modes the inner or scalar source mode. |
727 | (define_mode_attr VCOND [(HI "V4HI") (SI "V2SI") | |
728 | (V4HI "V4HI") (V8HI "V4HI") | |
b7d7d917 TB |
729 | (V2SI "V2SI") (V4SI "V2SI") |
730 | (DI "DI") (V2DI "DI") | |
731 | (V2SF "V2SF") (V4SF "V2SF") | |
732 | (V2DF "DF")]) | |
733 | ||
278821f2 | 734 | ;; 128-bit container modes the inner or scalar source mode. |
b7d7d917 TB |
735 | (define_mode_attr VCONQ [(V8QI "V16QI") (V16QI "V16QI") |
736 | (V4HI "V8HI") (V8HI "V8HI") | |
737 | (V2SI "V4SI") (V4SI "V4SI") | |
738 | (DI "V2DI") (V2DI "V2DI") | |
71a11456 | 739 | (V4HF "V8HF") (V8HF "V8HF") |
b7d7d917 TB |
740 | (V2SF "V2SF") (V4SF "V4SF") |
741 | (V2DF "V2DF") (SI "V4SI") | |
742 | (HI "V8HI") (QI "V16QI")]) | |
743 | ||
43e9d192 IB |
744 | ;; Half modes of all vector modes. |
745 | (define_mode_attr VHALF [(V8QI "V4QI") (V16QI "V8QI") | |
746 | (V4HI "V2HI") (V8HI "V4HI") | |
747 | (V2SI "SI") (V4SI "V2SI") | |
748 | (V2DI "DI") (V2SF "SF") | |
71a11456 AL |
749 | (V4SF "V2SF") (V4HF "V2HF") |
750 | (V8HF "V4HF") (V2DF "DF")]) | |
43e9d192 | 751 | |
b1b49824 MC |
752 | ;; Half modes of all vector modes, in lower-case. |
753 | (define_mode_attr Vhalf [(V8QI "v4qi") (V16QI "v8qi") | |
754 | (V4HI "v2hi") (V8HI "v4hi") | |
755 | (V2SI "si") (V4SI "v2si") | |
756 | (V2DI "di") (V2SF "sf") | |
757 | (V4SF "v2sf") (V2DF "df")]) | |
758 | ||
43e9d192 IB |
759 | ;; Double modes of vector modes. |
760 | (define_mode_attr VDBL [(V8QI "V16QI") (V4HI "V8HI") | |
71a11456 | 761 | (V4HF "V8HF") |
43e9d192 IB |
762 | (V2SI "V4SI") (V2SF "V4SF") |
763 | (SI "V2SI") (DI "V2DI") | |
764 | (DF "V2DF")]) | |
765 | ||
922f9c25 AL |
766 | ;; Register suffix for double-length mode. |
767 | (define_mode_attr Vdtype [(V4HF "8h") (V2SF "4s")]) | |
768 | ||
43e9d192 IB |
769 | ;; Double modes of vector modes (lower case). |
770 | (define_mode_attr Vdbl [(V8QI "v16qi") (V4HI "v8hi") | |
7c369485 | 771 | (V4HF "v8hf") |
43e9d192 | 772 | (V2SI "v4si") (V2SF "v4sf") |
8b033a8a SN |
773 | (SI "v2si") (DI "v2di") |
774 | (DF "v2df")]) | |
43e9d192 | 775 | |
b1b49824 MC |
776 | ;; Modes with double-width elements. |
777 | (define_mode_attr VDBLW [(V8QI "V4HI") (V16QI "V8HI") | |
778 | (V4HI "V2SI") (V8HI "V4SI") | |
779 | (V2SI "DI") (V4SI "V2DI")]) | |
780 | ||
43e9d192 IB |
781 | ;; Narrowed modes for VDN. |
782 | (define_mode_attr VNARROWD [(V4HI "V8QI") (V2SI "V4HI") | |
783 | (DI "V2SI")]) | |
784 | ||
785 | ;; Narrowed double-modes for VQN (Used for XTN). | |
786 | (define_mode_attr VNARROWQ [(V8HI "V8QI") (V4SI "V4HI") | |
787 | (V2DI "V2SI") | |
788 | (DI "SI") (SI "HI") | |
789 | (HI "QI")]) | |
790 | ||
791 | ;; Narrowed quad-modes for VQN (Used for XTN2). | |
792 | (define_mode_attr VNARROWQ2 [(V8HI "V16QI") (V4SI "V8HI") | |
793 | (V2DI "V4SI")]) | |
794 | ||
795 | ;; Register suffix narrowed modes for VQN. | |
796 | (define_mode_attr Vntype [(V8HI "8b") (V4SI "4h") | |
797 | (V2DI "2s")]) | |
798 | ||
799 | ;; Register suffix narrowed modes for VQN. | |
800 | (define_mode_attr V2ntype [(V8HI "16b") (V4SI "8h") | |
801 | (V2DI "4s")]) | |
802 | ||
803 | ;; Widened modes of vector modes. | |
43cacb12 RS |
804 | (define_mode_attr VWIDE [(V8QI "V8HI") (V4HI "V4SI") |
805 | (V2SI "V2DI") (V16QI "V8HI") | |
806 | (V8HI "V4SI") (V4SI "V2DI") | |
807 | (HI "SI") (SI "DI") | |
808 | (V8HF "V4SF") (V4SF "V2DF") | |
809 | (V4HF "V4SF") (V2SF "V2DF") | |
810 | (VNx8HF "VNx4SF") (VNx4SF "VNx2DF") | |
811 | (VNx16QI "VNx8HI") (VNx8HI "VNx4SI") | |
812 | (VNx4SI "VNx2DI") | |
813 | (VNx16BI "VNx8BI") (VNx8BI "VNx4BI") | |
814 | (VNx4BI "VNx2BI")]) | |
815 | ||
816 | ;; Predicate mode associated with VWIDE. | |
817 | (define_mode_attr VWIDE_PRED [(VNx8HF "VNx4BI") (VNx4SF "VNx2BI")]) | |
43e9d192 | 818 | |
03873eb9 | 819 | ;; Widened modes of vector modes, lowercase |
43cacb12 RS |
820 | (define_mode_attr Vwide [(V2SF "v2df") (V4HF "v4sf") |
821 | (VNx16QI "vnx8hi") (VNx8HI "vnx4si") | |
822 | (VNx4SI "vnx2di") | |
823 | (VNx8HF "vnx4sf") (VNx4SF "vnx2df") | |
824 | (VNx16BI "vnx8bi") (VNx8BI "vnx4bi") | |
825 | (VNx4BI "vnx2bi")]) | |
03873eb9 AL |
826 | |
827 | ;; Widened mode register suffixes for VD_BHSI/VQW/VQ_HSF. | |
43e9d192 IB |
828 | (define_mode_attr Vwtype [(V8QI "8h") (V4HI "4s") |
829 | (V2SI "2d") (V16QI "8h") | |
03873eb9 AL |
830 | (V8HI "4s") (V4SI "2d") |
831 | (V8HF "4s") (V4SF "2d")]) | |
43e9d192 | 832 | |
43cacb12 RS |
833 | ;; SVE vector after widening |
834 | (define_mode_attr Vewtype [(VNx16QI "h") | |
835 | (VNx8HI "s") (VNx8HF "s") | |
836 | (VNx4SI "d") (VNx4SF "d")]) | |
837 | ||
43e9d192 IB |
838 | ;; Widened mode register suffixes for VDW/VQW. |
839 | (define_mode_attr Vmwtype [(V8QI ".8h") (V4HI ".4s") | |
840 | (V2SI ".2d") (V16QI ".8h") | |
841 | (V8HI ".4s") (V4SI ".2d") | |
922f9c25 | 842 | (V4HF ".4s") (V2SF ".2d") |
43e9d192 IB |
843 | (SI "") (HI "")]) |
844 | ||
03873eb9 | 845 | ;; Lower part register suffixes for VQW/VQ_HSF. |
43e9d192 | 846 | (define_mode_attr Vhalftype [(V16QI "8b") (V8HI "4h") |
03873eb9 AL |
847 | (V4SI "2s") (V8HF "4h") |
848 | (V4SF "2s")]) | |
43e9d192 IB |
849 | |
850 | ;; Define corresponding core/FP element mode for each vector mode. | |
43cacb12 RS |
851 | (define_mode_attr vw [(V8QI "w") (V16QI "w") (VNx16QI "w") |
852 | (V4HI "w") (V8HI "w") (VNx8HI "w") | |
853 | (V2SI "w") (V4SI "w") (VNx4SI "w") | |
854 | (DI "x") (V2DI "x") (VNx2DI "x") | |
855 | (VNx8HF "h") | |
856 | (V2SF "s") (V4SF "s") (VNx4SF "s") | |
857 | (V2DF "d") (VNx2DF "d")]) | |
43e9d192 | 858 | |
66adb8eb JG |
859 | ;; Corresponding core element mode for each vector mode. This is a |
860 | ;; variation on <vw> mapping FP modes to GP regs. | |
43cacb12 RS |
861 | (define_mode_attr vwcore [(V8QI "w") (V16QI "w") (VNx16QI "w") |
862 | (V4HI "w") (V8HI "w") (VNx8HI "w") | |
863 | (V2SI "w") (V4SI "w") (VNx4SI "w") | |
864 | (DI "x") (V2DI "x") (VNx2DI "x") | |
865 | (V4HF "w") (V8HF "w") (VNx8HF "w") | |
866 | (V2SF "w") (V4SF "w") (VNx4SF "w") | |
867 | (V2DF "x") (VNx2DF "x")]) | |
66adb8eb | 868 | |
43e9d192 IB |
869 | ;; Double vector types for ALLX. |
870 | (define_mode_attr Vallxd [(QI "8b") (HI "4h") (SI "2s")]) | |
871 | ||
5f565314 RS |
872 | ;; Mode with floating-point values replaced by like-sized integers. |
873 | (define_mode_attr V_INT_EQUIV [(V8QI "V8QI") (V16QI "V16QI") | |
874 | (V4HI "V4HI") (V8HI "V8HI") | |
875 | (V2SI "V2SI") (V4SI "V4SI") | |
876 | (DI "DI") (V2DI "V2DI") | |
877 | (V4HF "V4HI") (V8HF "V8HI") | |
878 | (V2SF "V2SI") (V4SF "V4SI") | |
43cacb12 | 879 | (DF "DI") (V2DF "V2DI") |
dfe1da23 JW |
880 | (SF "SI") (SI "SI") |
881 | (HF "HI") | |
43cacb12 RS |
882 | (VNx16QI "VNx16QI") |
883 | (VNx8HI "VNx8HI") (VNx8HF "VNx8HI") | |
884 | (VNx4SI "VNx4SI") (VNx4SF "VNx4SI") | |
885 | (VNx2DI "VNx2DI") (VNx2DF "VNx2DI") | |
886 | ]) | |
5f565314 RS |
887 | |
888 | ;; Lower case mode with floating-point values replaced by like-sized integers. | |
889 | (define_mode_attr v_int_equiv [(V8QI "v8qi") (V16QI "v16qi") | |
890 | (V4HI "v4hi") (V8HI "v8hi") | |
891 | (V2SI "v2si") (V4SI "v4si") | |
892 | (DI "di") (V2DI "v2di") | |
893 | (V4HF "v4hi") (V8HF "v8hi") | |
894 | (V2SF "v2si") (V4SF "v4si") | |
43cacb12 RS |
895 | (DF "di") (V2DF "v2di") |
896 | (SF "si") | |
897 | (VNx16QI "vnx16qi") | |
898 | (VNx8HI "vnx8hi") (VNx8HF "vnx8hi") | |
899 | (VNx4SI "vnx4si") (VNx4SF "vnx4si") | |
900 | (VNx2DI "vnx2di") (VNx2DF "vnx2di") | |
901 | ]) | |
902 | ||
903 | ;; Floating-point equivalent of selected modes. | |
904 | (define_mode_attr V_FP_EQUIV [(VNx4SI "VNx4SF") (VNx4SF "VNx4SF") | |
905 | (VNx2DI "VNx2DF") (VNx2DF "VNx2DF")]) | |
906 | (define_mode_attr v_fp_equiv [(VNx4SI "vnx4sf") (VNx4SF "vnx4sf") | |
907 | (VNx2DI "vnx2df") (VNx2DF "vnx2df")]) | |
70c67693 | 908 | |
6c553b76 BC |
909 | ;; Mode for vector conditional operations where the comparison has |
910 | ;; different type from the lhs. | |
911 | (define_mode_attr V_cmp_mixed [(V2SI "V2SF") (V4SI "V4SF") | |
912 | (V2DI "V2DF") (V2SF "V2SI") | |
913 | (V4SF "V4SI") (V2DF "V2DI")]) | |
914 | ||
915 | (define_mode_attr v_cmp_mixed [(V2SI "v2sf") (V4SI "v4sf") | |
916 | (V2DI "v2df") (V2SF "v2si") | |
917 | (V4SF "v4si") (V2DF "v2di")]) | |
918 | ||
cb23a30c JG |
919 | ;; Lower case element modes (as used in shift immediate patterns). |
920 | (define_mode_attr ve_mode [(V8QI "qi") (V16QI "qi") | |
921 | (V4HI "hi") (V8HI "hi") | |
922 | (V2SI "si") (V4SI "si") | |
923 | (DI "di") (V2DI "di") | |
924 | (QI "qi") (HI "hi") | |
925 | (SI "si")]) | |
926 | ||
43e9d192 IB |
927 | ;; Vm for lane instructions is restricted to FP_LO_REGS. |
928 | (define_mode_attr vwx [(V4HI "x") (V8HI "x") (HI "x") | |
929 | (V2SI "w") (V4SI "w") (SI "w")]) | |
930 | ||
931 | (define_mode_attr Vendreg [(OI "T") (CI "U") (XI "V")]) | |
932 | ||
97755701 AL |
933 | ;; This is both the number of Q-Registers needed to hold the corresponding |
934 | ;; opaque large integer mode, and the number of elements touched by the | |
935 | ;; ld..._lane and st..._lane operations. | |
43e9d192 IB |
936 | (define_mode_attr nregs [(OI "2") (CI "3") (XI "4")]) |
937 | ||
0462169c SN |
938 | ;; Mode for atomic operation suffixes |
939 | (define_mode_attr atomic_sfx | |
940 | [(QI "b") (HI "h") (SI "") (DI "")]) | |
941 | ||
3f598afe | 942 | (define_mode_attr fcvt_target [(V2DF "v2di") (V4SF "v4si") (V2SF "v2si") |
2644d4d9 | 943 | (V2DI "v2df") (V4SI "v4sf") (V2SI "v2sf") |
daef0a8c JW |
944 | (SF "si") (DF "di") (SI "sf") (DI "df") |
945 | (V4HF "v4hi") (V8HF "v8hi") (V4HI "v4hf") | |
68ad28c3 | 946 | (V8HI "v8hf") (HF "hi") (HI "hf")]) |
3f598afe | 947 | (define_mode_attr FCVT_TARGET [(V2DF "V2DI") (V4SF "V4SI") (V2SF "V2SI") |
2644d4d9 | 948 | (V2DI "V2DF") (V4SI "V4SF") (V2SI "V2SF") |
daef0a8c JW |
949 | (SF "SI") (DF "DI") (SI "SF") (DI "DF") |
950 | (V4HF "V4HI") (V8HF "V8HI") (V4HI "V4HF") | |
68ad28c3 | 951 | (V8HI "V8HF") (HF "HI") (HI "HF")]) |
3f598afe | 952 | |
0d35c5c2 VP |
953 | |
954 | ;; for the inequal width integer to fp conversions | |
d7f33f07 JW |
955 | (define_mode_attr fcvt_iesize [(HF "di") (SF "di") (DF "si")]) |
956 | (define_mode_attr FCVT_IESIZE [(HF "DI") (SF "DI") (DF "SI")]) | |
42fc9a7f | 957 | |
91bd4114 JG |
958 | (define_mode_attr VSWAP_WIDTH [(V8QI "V16QI") (V16QI "V8QI") |
959 | (V4HI "V8HI") (V8HI "V4HI") | |
960 | (V2SI "V4SI") (V4SI "V2SI") | |
961 | (DI "V2DI") (V2DI "DI") | |
962 | (V2SF "V4SF") (V4SF "V2SF") | |
862abc04 | 963 | (V4HF "V8HF") (V8HF "V4HF") |
91bd4114 JG |
964 | (DF "V2DF") (V2DF "DF")]) |
965 | ||
966 | (define_mode_attr vswap_width_name [(V8QI "to_128") (V16QI "to_64") | |
967 | (V4HI "to_128") (V8HI "to_64") | |
968 | (V2SI "to_128") (V4SI "to_64") | |
969 | (DI "to_128") (V2DI "to_64") | |
862abc04 | 970 | (V4HF "to_128") (V8HF "to_64") |
91bd4114 JG |
971 | (V2SF "to_128") (V4SF "to_64") |
972 | (DF "to_128") (V2DF "to_64")]) | |
973 | ||
779aea46 | 974 | ;; For certain vector-by-element multiplication instructions we must |
6d06971d | 975 | ;; constrain the 16-bit cases to use only V0-V15. This is covered by |
779aea46 JG |
976 | ;; the 'x' constraint. All other modes may use the 'w' constraint. |
977 | (define_mode_attr h_con [(V2SI "w") (V4SI "w") | |
978 | (V4HI "x") (V8HI "x") | |
6d06971d | 979 | (V4HF "x") (V8HF "x") |
779aea46 JG |
980 | (V2SF "w") (V4SF "w") |
981 | (V2DF "w") (DF "w")]) | |
982 | ||
983 | ;; Defined to 'f' for types whose element type is a float type. | |
984 | (define_mode_attr f [(V8QI "") (V16QI "") | |
985 | (V4HI "") (V8HI "") | |
986 | (V2SI "") (V4SI "") | |
987 | (DI "") (V2DI "") | |
ab2e8f01 | 988 | (V4HF "f") (V8HF "f") |
779aea46 JG |
989 | (V2SF "f") (V4SF "f") |
990 | (V2DF "f") (DF "f")]) | |
991 | ||
0f686aa9 JG |
992 | ;; Defined to '_fp' for types whose element type is a float type. |
993 | (define_mode_attr fp [(V8QI "") (V16QI "") | |
994 | (V4HI "") (V8HI "") | |
995 | (V2SI "") (V4SI "") | |
996 | (DI "") (V2DI "") | |
ab2e8f01 | 997 | (V4HF "_fp") (V8HF "_fp") |
0f686aa9 JG |
998 | (V2SF "_fp") (V4SF "_fp") |
999 | (V2DF "_fp") (DF "_fp") | |
1000 | (SF "_fp")]) | |
1001 | ||
a9e66678 JG |
1002 | ;; Defined to '_q' for 128-bit types. |
1003 | (define_mode_attr q [(V8QI "") (V16QI "_q") | |
0f686aa9 JG |
1004 | (V4HI "") (V8HI "_q") |
1005 | (V2SI "") (V4SI "_q") | |
1006 | (DI "") (V2DI "_q") | |
71a11456 | 1007 | (V4HF "") (V8HF "_q") |
0f686aa9 JG |
1008 | (V2SF "") (V4SF "_q") |
1009 | (V2DF "_q") | |
d7f33f07 | 1010 | (QI "") (HI "") (SI "") (DI "") (HF "") (SF "") (DF "")]) |
a9e66678 | 1011 | |
92835317 TB |
1012 | (define_mode_attr vp [(V8QI "v") (V16QI "v") |
1013 | (V4HI "v") (V8HI "v") | |
1014 | (V2SI "p") (V4SI "v") | |
703bbcdf JW |
1015 | (V2DI "p") (V2DF "p") |
1016 | (V2SF "p") (V4SF "v") | |
1017 | (V4HF "v") (V8HF "v")]) | |
92835317 | 1018 | |
5e32e83b JW |
1019 | (define_mode_attr vsi2qi [(V2SI "v8qi") (V4SI "v16qi")]) |
1020 | (define_mode_attr VSI2QI [(V2SI "V8QI") (V4SI "V16QI")]) | |
1021 | ||
7a08d813 TC |
1022 | |
1023 | ;; Register suffix for DOTPROD input types from the return type. | |
1024 | (define_mode_attr Vdottype [(V2SI "8b") (V4SI "16b")]) | |
1025 | ||
cd78b3dd | 1026 | ;; Sum of lengths of instructions needed to move vector registers of a mode. |
668046d1 DS |
1027 | (define_mode_attr insn_count [(OI "8") (CI "12") (XI "16")]) |
1028 | ||
1b1e81f8 JW |
1029 | ;; -fpic small model GOT reloc modifers: gotpage_lo15/lo14 for ILP64/32. |
1030 | ;; No need of iterator for -fPIC as it use got_lo12 for both modes. | |
1031 | (define_mode_attr got_modifier [(SI "gotpage_lo14") (DI "gotpage_lo15")]) | |
1032 | ||
27086ea3 MC |
1033 | ;; Width of 2nd and 3rd arguments to fp16 vector multiply add/sub |
1034 | (define_mode_attr VFMLA_W [(V2SF "V4HF") (V4SF "V8HF")]) | |
1035 | ||
1036 | (define_mode_attr VFMLA_SEL_W [(V2SF "V2HF") (V4SF "V4HF")]) | |
1037 | ||
1038 | (define_mode_attr f16quad [(V2SF "") (V4SF "q")]) | |
1039 | ||
1040 | (define_code_attr f16mac [(plus "a") (minus "s")]) | |
1041 | ||
9f4cbab8 RS |
1042 | ;; The number of subvectors in an SVE_STRUCT. |
1043 | (define_mode_attr vector_count [(VNx32QI "2") (VNx16HI "2") | |
1044 | (VNx8SI "2") (VNx4DI "2") | |
1045 | (VNx16HF "2") (VNx8SF "2") (VNx4DF "2") | |
1046 | (VNx48QI "3") (VNx24HI "3") | |
1047 | (VNx12SI "3") (VNx6DI "3") | |
1048 | (VNx24HF "3") (VNx12SF "3") (VNx6DF "3") | |
1049 | (VNx64QI "4") (VNx32HI "4") | |
1050 | (VNx16SI "4") (VNx8DI "4") | |
1051 | (VNx32HF "4") (VNx16SF "4") (VNx8DF "4")]) | |
1052 | ||
1053 | ;; The number of instruction bytes needed for an SVE_STRUCT move. This is | |
1054 | ;; equal to vector_count * 4. | |
1055 | (define_mode_attr insn_length [(VNx32QI "8") (VNx16HI "8") | |
1056 | (VNx8SI "8") (VNx4DI "8") | |
1057 | (VNx16HF "8") (VNx8SF "8") (VNx4DF "8") | |
1058 | (VNx48QI "12") (VNx24HI "12") | |
1059 | (VNx12SI "12") (VNx6DI "12") | |
1060 | (VNx24HF "12") (VNx12SF "12") (VNx6DF "12") | |
1061 | (VNx64QI "16") (VNx32HI "16") | |
1062 | (VNx16SI "16") (VNx8DI "16") | |
1063 | (VNx32HF "16") (VNx16SF "16") (VNx8DF "16")]) | |
1064 | ||
1065 | ;; The type of a subvector in an SVE_STRUCT. | |
1066 | (define_mode_attr VSINGLE [(VNx32QI "VNx16QI") | |
1067 | (VNx16HI "VNx8HI") (VNx16HF "VNx8HF") | |
1068 | (VNx8SI "VNx4SI") (VNx8SF "VNx4SF") | |
1069 | (VNx4DI "VNx2DI") (VNx4DF "VNx2DF") | |
1070 | (VNx48QI "VNx16QI") | |
1071 | (VNx24HI "VNx8HI") (VNx24HF "VNx8HF") | |
1072 | (VNx12SI "VNx4SI") (VNx12SF "VNx4SF") | |
1073 | (VNx6DI "VNx2DI") (VNx6DF "VNx2DF") | |
1074 | (VNx64QI "VNx16QI") | |
1075 | (VNx32HI "VNx8HI") (VNx32HF "VNx8HF") | |
1076 | (VNx16SI "VNx4SI") (VNx16SF "VNx4SF") | |
1077 | (VNx8DI "VNx2DI") (VNx8DF "VNx2DF")]) | |
1078 | ||
1079 | ;; ...and again in lower case. | |
1080 | (define_mode_attr vsingle [(VNx32QI "vnx16qi") | |
1081 | (VNx16HI "vnx8hi") (VNx16HF "vnx8hf") | |
1082 | (VNx8SI "vnx4si") (VNx8SF "vnx4sf") | |
1083 | (VNx4DI "vnx2di") (VNx4DF "vnx2df") | |
1084 | (VNx48QI "vnx16qi") | |
1085 | (VNx24HI "vnx8hi") (VNx24HF "vnx8hf") | |
1086 | (VNx12SI "vnx4si") (VNx12SF "vnx4sf") | |
1087 | (VNx6DI "vnx2di") (VNx6DF "vnx2df") | |
1088 | (VNx64QI "vnx16qi") | |
1089 | (VNx32HI "vnx8hi") (VNx32HF "vnx8hf") | |
1090 | (VNx16SI "vnx4si") (VNx16SF "vnx4sf") | |
1091 | (VNx8DI "vnx2di") (VNx8DF "vnx2df")]) | |
1092 | ||
1093 | ;; The predicate mode associated with an SVE data mode. For structure modes | |
1094 | ;; this is equivalent to the <VPRED> of the subvector mode. | |
43cacb12 RS |
1095 | (define_mode_attr VPRED [(VNx16QI "VNx16BI") |
1096 | (VNx8HI "VNx8BI") (VNx8HF "VNx8BI") | |
1097 | (VNx4SI "VNx4BI") (VNx4SF "VNx4BI") | |
9f4cbab8 RS |
1098 | (VNx2DI "VNx2BI") (VNx2DF "VNx2BI") |
1099 | (VNx32QI "VNx16BI") | |
1100 | (VNx16HI "VNx8BI") (VNx16HF "VNx8BI") | |
1101 | (VNx8SI "VNx4BI") (VNx8SF "VNx4BI") | |
1102 | (VNx4DI "VNx2BI") (VNx4DF "VNx2BI") | |
1103 | (VNx48QI "VNx16BI") | |
1104 | (VNx24HI "VNx8BI") (VNx24HF "VNx8BI") | |
1105 | (VNx12SI "VNx4BI") (VNx12SF "VNx4BI") | |
1106 | (VNx6DI "VNx2BI") (VNx6DF "VNx2BI") | |
1107 | (VNx64QI "VNx16BI") | |
1108 | (VNx32HI "VNx8BI") (VNx32HF "VNx8BI") | |
1109 | (VNx16SI "VNx4BI") (VNx16SF "VNx4BI") | |
1110 | (VNx8DI "VNx2BI") (VNx8DF "VNx2BI")]) | |
43cacb12 RS |
1111 | |
1112 | ;; ...and again in lower case. | |
1113 | (define_mode_attr vpred [(VNx16QI "vnx16bi") | |
1114 | (VNx8HI "vnx8bi") (VNx8HF "vnx8bi") | |
1115 | (VNx4SI "vnx4bi") (VNx4SF "vnx4bi") | |
9f4cbab8 RS |
1116 | (VNx2DI "vnx2bi") (VNx2DF "vnx2bi") |
1117 | (VNx32QI "vnx16bi") | |
1118 | (VNx16HI "vnx8bi") (VNx16HF "vnx8bi") | |
1119 | (VNx8SI "vnx4bi") (VNx8SF "vnx4bi") | |
1120 | (VNx4DI "vnx2bi") (VNx4DF "vnx2bi") | |
1121 | (VNx48QI "vnx16bi") | |
1122 | (VNx24HI "vnx8bi") (VNx24HF "vnx8bi") | |
1123 | (VNx12SI "vnx4bi") (VNx12SF "vnx4bi") | |
1124 | (VNx6DI "vnx2bi") (VNx6DF "vnx2bi") | |
1125 | (VNx64QI "vnx16bi") | |
1126 | (VNx32HI "vnx8bi") (VNx32HF "vnx4bi") | |
1127 | (VNx16SI "vnx4bi") (VNx16SF "vnx4bi") | |
1128 | (VNx8DI "vnx2bi") (VNx8DF "vnx2bi")]) | |
43cacb12 | 1129 | |
43e9d192 IB |
1130 | ;; ------------------------------------------------------------------- |
1131 | ;; Code Iterators | |
1132 | ;; ------------------------------------------------------------------- | |
1133 | ||
1134 | ;; This code iterator allows the various shifts supported on the core | |
1135 | (define_code_iterator SHIFT [ashift ashiftrt lshiftrt rotatert]) | |
1136 | ||
1137 | ;; This code iterator allows the shifts supported in arithmetic instructions | |
1138 | (define_code_iterator ASHIFT [ashift ashiftrt lshiftrt]) | |
1139 | ||
1140 | ;; Code iterator for logical operations | |
1141 | (define_code_iterator LOGICAL [and ior xor]) | |
1142 | ||
43cacb12 RS |
1143 | ;; LOGICAL without AND. |
1144 | (define_code_iterator LOGICAL_OR [ior xor]) | |
1145 | ||
84be6032 AL |
1146 | ;; Code iterator for logical operations whose :nlogical works on SIMD registers. |
1147 | (define_code_iterator NLOGICAL [and ior]) | |
1148 | ||
3204ac98 KT |
1149 | ;; Code iterator for unary negate and bitwise complement. |
1150 | (define_code_iterator NEG_NOT [neg not]) | |
1151 | ||
43e9d192 IB |
1152 | ;; Code iterator for sign/zero extension |
1153 | (define_code_iterator ANY_EXTEND [sign_extend zero_extend]) | |
1154 | ||
1155 | ;; All division operations (signed/unsigned) | |
1156 | (define_code_iterator ANY_DIV [div udiv]) | |
1157 | ||
1158 | ;; Code iterator for sign/zero extraction | |
1159 | (define_code_iterator ANY_EXTRACT [sign_extract zero_extract]) | |
1160 | ||
1161 | ;; Code iterator for equality comparisons | |
1162 | (define_code_iterator EQL [eq ne]) | |
1163 | ||
1164 | ;; Code iterator for less-than and greater/equal-to | |
1165 | (define_code_iterator LTGE [lt ge]) | |
1166 | ||
1167 | ;; Iterator for __sync_<op> operations that where the operation can be | |
1168 | ;; represented directly RTL. This is all of the sync operations bar | |
1169 | ;; nand. | |
0462169c | 1170 | (define_code_iterator atomic_op [plus minus ior xor and]) |
43e9d192 IB |
1171 | |
1172 | ;; Iterator for integer conversions | |
1173 | (define_code_iterator FIXUORS [fix unsigned_fix]) | |
1174 | ||
1709ff9b JG |
1175 | ;; Iterator for float conversions |
1176 | (define_code_iterator FLOATUORS [float unsigned_float]) | |
1177 | ||
43e9d192 IB |
1178 | ;; Code iterator for variants of vector max and min. |
1179 | (define_code_iterator MAXMIN [smax smin umax umin]) | |
1180 | ||
998eaf97 JG |
1181 | (define_code_iterator FMAXMIN [smax smin]) |
1182 | ||
43e9d192 IB |
1183 | ;; Code iterator for variants of vector max and min. |
1184 | (define_code_iterator ADDSUB [plus minus]) | |
1185 | ||
1186 | ;; Code iterator for variants of vector saturating binary ops. | |
1187 | (define_code_iterator BINQOPS [ss_plus us_plus ss_minus us_minus]) | |
1188 | ||
1189 | ;; Code iterator for variants of vector saturating unary ops. | |
1190 | (define_code_iterator UNQOPS [ss_neg ss_abs]) | |
1191 | ||
1192 | ;; Code iterator for signed variants of vector saturating binary ops. | |
1193 | (define_code_iterator SBINQOPS [ss_plus ss_minus]) | |
1194 | ||
889b9412 JG |
1195 | ;; Comparison operators for <F>CM. |
1196 | (define_code_iterator COMPARISONS [lt le eq ge gt]) | |
1197 | ||
1198 | ;; Unsigned comparison operators. | |
1199 | (define_code_iterator UCOMPARISONS [ltu leu geu gtu]) | |
1200 | ||
75dd5ace JG |
1201 | ;; Unsigned comparison operators. |
1202 | (define_code_iterator FAC_COMPARISONS [lt le ge gt]) | |
1203 | ||
43cacb12 RS |
1204 | ;; SVE integer unary operations. |
1205 | (define_code_iterator SVE_INT_UNARY [neg not popcount]) | |
1206 | ||
1207 | ;; SVE floating-point unary operations. | |
1208 | (define_code_iterator SVE_FP_UNARY [neg abs sqrt]) | |
1209 | ||
a08acce8 | 1210 | ;; SVE integer binary operations. |
6c4fd4a9 | 1211 | (define_code_iterator SVE_INT_BINARY [plus minus mult smax umax smin umin |
9d4ac06e RS |
1212 | and ior xor]) |
1213 | ||
a08acce8 | 1214 | ;; SVE integer binary division operations. |
c38f7319 RS |
1215 | (define_code_iterator SVE_INT_BINARY_SD [div udiv]) |
1216 | ||
f22d7973 RS |
1217 | ;; SVE integer comparisons. |
1218 | (define_code_iterator SVE_INT_CMP [lt le eq ne ge gt ltu leu geu gtu]) | |
1219 | ||
1220 | ;; SVE floating-point comparisons. | |
1221 | (define_code_iterator SVE_FP_CMP [lt le eq ne ge gt]) | |
1222 | ||
43e9d192 IB |
1223 | ;; ------------------------------------------------------------------- |
1224 | ;; Code Attributes | |
1225 | ;; ------------------------------------------------------------------- | |
1226 | ;; Map rtl objects to optab names | |
1227 | (define_code_attr optab [(ashift "ashl") | |
1228 | (ashiftrt "ashr") | |
1229 | (lshiftrt "lshr") | |
1230 | (rotatert "rotr") | |
1231 | (sign_extend "extend") | |
1232 | (zero_extend "zero_extend") | |
1233 | (sign_extract "extv") | |
1234 | (zero_extract "extzv") | |
384be29f JG |
1235 | (fix "fix") |
1236 | (unsigned_fix "fixuns") | |
1709ff9b JG |
1237 | (float "float") |
1238 | (unsigned_float "floatuns") | |
43cacb12 | 1239 | (popcount "popcount") |
43e9d192 IB |
1240 | (and "and") |
1241 | (ior "ior") | |
1242 | (xor "xor") | |
1243 | (not "one_cmpl") | |
1244 | (neg "neg") | |
1245 | (plus "add") | |
1246 | (minus "sub") | |
6c4fd4a9 | 1247 | (mult "mul") |
c38f7319 RS |
1248 | (div "div") |
1249 | (udiv "udiv") | |
43e9d192 IB |
1250 | (ss_plus "qadd") |
1251 | (us_plus "qadd") | |
1252 | (ss_minus "qsub") | |
1253 | (us_minus "qsub") | |
1254 | (ss_neg "qneg") | |
1255 | (ss_abs "qabs") | |
43cacb12 RS |
1256 | (smin "smin") |
1257 | (smax "smax") | |
1258 | (umin "umin") | |
1259 | (umax "umax") | |
43e9d192 IB |
1260 | (eq "eq") |
1261 | (ne "ne") | |
1262 | (lt "lt") | |
889b9412 JG |
1263 | (ge "ge") |
1264 | (le "le") | |
1265 | (gt "gt") | |
1266 | (ltu "ltu") | |
1267 | (leu "leu") | |
1268 | (geu "geu") | |
43cacb12 RS |
1269 | (gtu "gtu") |
1270 | (abs "abs") | |
1271 | (sqrt "sqrt")]) | |
889b9412 JG |
1272 | |
1273 | ;; For comparison operators we use the FCM* and CM* instructions. | |
1274 | ;; As there are no CMLE or CMLT instructions which act on 3 vector | |
1275 | ;; operands, we must use CMGE or CMGT and swap the order of the | |
1276 | ;; source operands. | |
1277 | ||
1278 | (define_code_attr n_optab [(lt "gt") (le "ge") (eq "eq") (ge "ge") (gt "gt") | |
1279 | (ltu "hi") (leu "hs") (geu "hs") (gtu "hi")]) | |
1280 | (define_code_attr cmp_1 [(lt "2") (le "2") (eq "1") (ge "1") (gt "1") | |
1281 | (ltu "2") (leu "2") (geu "1") (gtu "1")]) | |
1282 | (define_code_attr cmp_2 [(lt "1") (le "1") (eq "2") (ge "2") (gt "2") | |
1283 | (ltu "1") (leu "1") (geu "2") (gtu "2")]) | |
1284 | ||
1285 | (define_code_attr CMP [(lt "LT") (le "LE") (eq "EQ") (ge "GE") (gt "GT") | |
714e1b3b KT |
1286 | (ltu "LTU") (leu "LEU") (ne "NE") (geu "GEU") |
1287 | (gtu "GTU")]) | |
43e9d192 | 1288 | |
f22d7973 RS |
1289 | ;; The AArch64 condition associated with an rtl comparison code. |
1290 | (define_code_attr cmp_op [(lt "lt") | |
1291 | (le "le") | |
1292 | (eq "eq") | |
1293 | (ne "ne") | |
1294 | (ge "ge") | |
1295 | (gt "gt") | |
1296 | (ltu "lo") | |
1297 | (leu "ls") | |
1298 | (geu "hs") | |
1299 | (gtu "hi")]) | |
1300 | ||
384be29f JG |
1301 | (define_code_attr fix_trunc_optab [(fix "fix_trunc") |
1302 | (unsigned_fix "fixuns_trunc")]) | |
1303 | ||
43e9d192 IB |
1304 | ;; Optab prefix for sign/zero-extending operations |
1305 | (define_code_attr su_optab [(sign_extend "") (zero_extend "u") | |
1306 | (div "") (udiv "u") | |
1307 | (fix "") (unsigned_fix "u") | |
1709ff9b | 1308 | (float "s") (unsigned_float "u") |
43e9d192 IB |
1309 | (ss_plus "s") (us_plus "u") |
1310 | (ss_minus "s") (us_minus "u")]) | |
1311 | ||
1312 | ;; Similar for the instruction mnemonics | |
1313 | (define_code_attr shift [(ashift "lsl") (ashiftrt "asr") | |
1314 | (lshiftrt "lsr") (rotatert "ror")]) | |
1315 | ||
1316 | ;; Map shift operators onto underlying bit-field instructions | |
1317 | (define_code_attr bfshift [(ashift "ubfiz") (ashiftrt "sbfx") | |
1318 | (lshiftrt "ubfx") (rotatert "extr")]) | |
1319 | ||
1320 | ;; Logical operator instruction mnemonics | |
1321 | (define_code_attr logical [(and "and") (ior "orr") (xor "eor")]) | |
1322 | ||
3204ac98 KT |
1323 | ;; Operation names for negate and bitwise complement. |
1324 | (define_code_attr neg_not_op [(neg "neg") (not "not")]) | |
1325 | ||
43cacb12 | 1326 | ;; Similar, but when the second operand is inverted. |
43e9d192 IB |
1327 | (define_code_attr nlogical [(and "bic") (ior "orn") (xor "eon")]) |
1328 | ||
43cacb12 RS |
1329 | ;; Similar, but when both operands are inverted. |
1330 | (define_code_attr logical_nn [(and "nor") (ior "nand")]) | |
1331 | ||
43e9d192 IB |
1332 | ;; Sign- or zero-extending data-op |
1333 | (define_code_attr su [(sign_extend "s") (zero_extend "u") | |
1334 | (sign_extract "s") (zero_extract "u") | |
1335 | (fix "s") (unsigned_fix "u") | |
998eaf97 JG |
1336 | (div "s") (udiv "u") |
1337 | (smax "s") (umax "u") | |
1338 | (smin "s") (umin "u")]) | |
43e9d192 | 1339 | |
43cacb12 RS |
1340 | ;; Whether a shift is left or right. |
1341 | (define_code_attr lr [(ashift "l") (ashiftrt "r") (lshiftrt "r")]) | |
1342 | ||
096e8448 JW |
1343 | ;; Emit conditional branch instructions. |
1344 | (define_code_attr bcond [(eq "beq") (ne "bne") (lt "bne") (ge "beq")]) | |
1345 | ||
43e9d192 IB |
1346 | ;; Emit cbz/cbnz depending on comparison type. |
1347 | (define_code_attr cbz [(eq "cbz") (ne "cbnz") (lt "cbnz") (ge "cbz")]) | |
1348 | ||
973d2e01 TP |
1349 | ;; Emit inverted cbz/cbnz depending on comparison type. |
1350 | (define_code_attr inv_cb [(eq "cbnz") (ne "cbz") (lt "cbz") (ge "cbnz")]) | |
1351 | ||
43e9d192 IB |
1352 | ;; Emit tbz/tbnz depending on comparison type. |
1353 | (define_code_attr tbz [(eq "tbz") (ne "tbnz") (lt "tbnz") (ge "tbz")]) | |
1354 | ||
973d2e01 TP |
1355 | ;; Emit inverted tbz/tbnz depending on comparison type. |
1356 | (define_code_attr inv_tb [(eq "tbnz") (ne "tbz") (lt "tbz") (ge "tbnz")]) | |
1357 | ||
43e9d192 | 1358 | ;; Max/min attributes. |
998eaf97 JG |
1359 | (define_code_attr maxmin [(smax "max") |
1360 | (smin "min") | |
1361 | (umax "max") | |
1362 | (umin "min")]) | |
43e9d192 IB |
1363 | |
1364 | ;; MLA/MLS attributes. | |
1365 | (define_code_attr as [(ss_plus "a") (ss_minus "s")]) | |
1366 | ||
0462169c SN |
1367 | ;; Atomic operations |
1368 | (define_code_attr atomic_optab | |
1369 | [(ior "or") (xor "xor") (and "and") (plus "add") (minus "sub")]) | |
1370 | ||
1371 | (define_code_attr atomic_op_operand | |
1372 | [(ior "aarch64_logical_operand") | |
1373 | (xor "aarch64_logical_operand") | |
1374 | (and "aarch64_logical_operand") | |
1375 | (plus "aarch64_plus_operand") | |
1376 | (minus "aarch64_plus_operand")]) | |
43e9d192 | 1377 | |
356c32e2 MW |
1378 | ;; Constants acceptable for atomic operations. |
1379 | ;; This definition must appear in this file before the iterators it refers to. | |
1380 | (define_code_attr const_atomic | |
1381 | [(plus "IJ") (minus "IJ") | |
1382 | (xor "<lconst_atomic>") (ior "<lconst_atomic>") | |
1383 | (and "<lconst_atomic>")]) | |
1384 | ||
1385 | ;; Attribute to describe constants acceptable in atomic logical operations | |
1386 | (define_mode_attr lconst_atomic [(QI "K") (HI "K") (SI "K") (DI "L")]) | |
1387 | ||
43cacb12 RS |
1388 | ;; The integer SVE instruction that implements an rtx code. |
1389 | (define_code_attr sve_int_op [(plus "add") | |
9d4ac06e | 1390 | (minus "sub") |
6c4fd4a9 | 1391 | (mult "mul") |
c38f7319 RS |
1392 | (div "sdiv") |
1393 | (udiv "udiv") | |
43cacb12 RS |
1394 | (neg "neg") |
1395 | (smin "smin") | |
1396 | (smax "smax") | |
1397 | (umin "umin") | |
1398 | (umax "umax") | |
1399 | (and "and") | |
1400 | (ior "orr") | |
1401 | (xor "eor") | |
1402 | (not "not") | |
1403 | (popcount "cnt")]) | |
1404 | ||
a08acce8 RH |
1405 | (define_code_attr sve_int_op_rev [(plus "add") |
1406 | (minus "subr") | |
1407 | (mult "mul") | |
1408 | (div "sdivr") | |
1409 | (udiv "udivr") | |
1410 | (smin "smin") | |
1411 | (smax "smax") | |
1412 | (umin "umin") | |
1413 | (umax "umax") | |
1414 | (and "and") | |
1415 | (ior "orr") | |
1416 | (xor "eor")]) | |
1417 | ||
43cacb12 RS |
1418 | ;; The floating-point SVE instruction that implements an rtx code. |
1419 | (define_code_attr sve_fp_op [(plus "fadd") | |
1420 | (neg "fneg") | |
1421 | (abs "fabs") | |
1422 | (sqrt "fsqrt")]) | |
1423 | ||
f22d7973 RS |
1424 | ;; The SVE immediate constraint to use for an rtl code. |
1425 | (define_code_attr sve_imm_con [(eq "vsc") | |
1426 | (ne "vsc") | |
1427 | (lt "vsc") | |
1428 | (ge "vsc") | |
1429 | (le "vsc") | |
1430 | (gt "vsc") | |
1431 | (ltu "vsd") | |
1432 | (leu "vsd") | |
1433 | (geu "vsd") | |
1434 | (gtu "vsd")]) | |
1435 | ||
43e9d192 IB |
1436 | ;; ------------------------------------------------------------------- |
1437 | ;; Int Iterators. | |
1438 | ;; ------------------------------------------------------------------- | |
75add2d0 KT |
1439 | |
1440 | ;; The unspec codes for the SABAL, UABAL AdvancedSIMD instructions. | |
1441 | (define_int_iterator ABAL [UNSPEC_SABAL UNSPEC_UABAL]) | |
1442 | ||
1443 | ;; The unspec codes for the SABDL2, UABDL2 AdvancedSIMD instructions. | |
1444 | (define_int_iterator ABDL2 [UNSPEC_SABDL2 UNSPEC_UABDL2]) | |
1445 | ||
1446 | ;; The unspec codes for the SADALP, UADALP AdvancedSIMD instructions. | |
1447 | (define_int_iterator ADALP [UNSPEC_SADALP UNSPEC_UADALP]) | |
1448 | ||
43e9d192 IB |
1449 | (define_int_iterator MAXMINV [UNSPEC_UMAXV UNSPEC_UMINV |
1450 | UNSPEC_SMAXV UNSPEC_SMINV]) | |
1451 | ||
998eaf97 JG |
1452 | (define_int_iterator FMAXMINV [UNSPEC_FMAXV UNSPEC_FMINV |
1453 | UNSPEC_FMAXNMV UNSPEC_FMINNMV]) | |
43e9d192 | 1454 | |
898f07b0 RS |
1455 | (define_int_iterator BITWISEV [UNSPEC_ANDV UNSPEC_IORV UNSPEC_XORV]) |
1456 | ||
43cacb12 RS |
1457 | (define_int_iterator LOGICALF [UNSPEC_ANDF UNSPEC_IORF UNSPEC_XORF]) |
1458 | ||
43e9d192 IB |
1459 | (define_int_iterator HADDSUB [UNSPEC_SHADD UNSPEC_UHADD |
1460 | UNSPEC_SRHADD UNSPEC_URHADD | |
1461 | UNSPEC_SHSUB UNSPEC_UHSUB | |
1462 | UNSPEC_SRHSUB UNSPEC_URHSUB]) | |
1463 | ||
42addb5a RS |
1464 | (define_int_iterator HADD [UNSPEC_SHADD UNSPEC_UHADD]) |
1465 | ||
1466 | (define_int_iterator RHADD [UNSPEC_SRHADD UNSPEC_URHADD]) | |
1467 | ||
7a08d813 | 1468 | (define_int_iterator DOTPROD [UNSPEC_SDOT UNSPEC_UDOT]) |
43e9d192 IB |
1469 | |
1470 | (define_int_iterator ADDSUBHN [UNSPEC_ADDHN UNSPEC_RADDHN | |
1471 | UNSPEC_SUBHN UNSPEC_RSUBHN]) | |
1472 | ||
1473 | (define_int_iterator ADDSUBHN2 [UNSPEC_ADDHN2 UNSPEC_RADDHN2 | |
1474 | UNSPEC_SUBHN2 UNSPEC_RSUBHN2]) | |
1475 | ||
1efafef3 TC |
1476 | (define_int_iterator FMAXMIN_UNS [UNSPEC_FMAX UNSPEC_FMIN |
1477 | UNSPEC_FMAXNM UNSPEC_FMINNM]) | |
202d0c11 | 1478 | |
db58fd89 JW |
1479 | (define_int_iterator PAUTH_LR_SP [UNSPEC_PACISP UNSPEC_AUTISP]) |
1480 | ||
1481 | (define_int_iterator PAUTH_17_16 [UNSPEC_PACI1716 UNSPEC_AUTI1716]) | |
1482 | ||
43e9d192 IB |
1483 | (define_int_iterator VQDMULH [UNSPEC_SQDMULH UNSPEC_SQRDMULH]) |
1484 | ||
1485 | (define_int_iterator USSUQADD [UNSPEC_SUQADD UNSPEC_USQADD]) | |
1486 | ||
1487 | (define_int_iterator SUQMOVN [UNSPEC_SQXTN UNSPEC_UQXTN]) | |
1488 | ||
1489 | (define_int_iterator VSHL [UNSPEC_SSHL UNSPEC_USHL | |
1490 | UNSPEC_SRSHL UNSPEC_URSHL]) | |
1491 | ||
1492 | (define_int_iterator VSHLL [UNSPEC_SSHLL UNSPEC_USHLL]) | |
1493 | ||
1494 | (define_int_iterator VQSHL [UNSPEC_SQSHL UNSPEC_UQSHL | |
1495 | UNSPEC_SQRSHL UNSPEC_UQRSHL]) | |
1496 | ||
1497 | (define_int_iterator VSRA [UNSPEC_SSRA UNSPEC_USRA | |
1498 | UNSPEC_SRSRA UNSPEC_URSRA]) | |
1499 | ||
1500 | (define_int_iterator VSLRI [UNSPEC_SSLI UNSPEC_USLI | |
1501 | UNSPEC_SSRI UNSPEC_USRI]) | |
1502 | ||
1503 | ||
1504 | (define_int_iterator VRSHR_N [UNSPEC_SRSHR UNSPEC_URSHR]) | |
1505 | ||
1506 | (define_int_iterator VQSHL_N [UNSPEC_SQSHLU UNSPEC_SQSHL UNSPEC_UQSHL]) | |
1507 | ||
1508 | (define_int_iterator VQSHRN_N [UNSPEC_SQSHRUN UNSPEC_SQRSHRUN | |
1509 | UNSPEC_SQSHRN UNSPEC_UQSHRN | |
1510 | UNSPEC_SQRSHRN UNSPEC_UQRSHRN]) | |
1511 | ||
57b26d65 MW |
1512 | (define_int_iterator SQRDMLH_AS [UNSPEC_SQRDMLAH UNSPEC_SQRDMLSH]) |
1513 | ||
cc4d934f JG |
1514 | (define_int_iterator PERMUTE [UNSPEC_ZIP1 UNSPEC_ZIP2 |
1515 | UNSPEC_TRN1 UNSPEC_TRN2 | |
1516 | UNSPEC_UZP1 UNSPEC_UZP2]) | |
43e9d192 | 1517 | |
43cacb12 RS |
1518 | (define_int_iterator OPTAB_PERMUTE [UNSPEC_ZIP1 UNSPEC_ZIP2 |
1519 | UNSPEC_UZP1 UNSPEC_UZP2]) | |
1520 | ||
923fcec3 AL |
1521 | (define_int_iterator REVERSE [UNSPEC_REV64 UNSPEC_REV32 UNSPEC_REV16]) |
1522 | ||
42fc9a7f | 1523 | (define_int_iterator FRINT [UNSPEC_FRINTZ UNSPEC_FRINTP UNSPEC_FRINTM |
0659ce6f JG |
1524 | UNSPEC_FRINTN UNSPEC_FRINTI UNSPEC_FRINTX |
1525 | UNSPEC_FRINTA]) | |
42fc9a7f JG |
1526 | |
1527 | (define_int_iterator FCVT [UNSPEC_FRINTZ UNSPEC_FRINTP UNSPEC_FRINTM | |
ce966824 | 1528 | UNSPEC_FRINTA UNSPEC_FRINTN]) |
42fc9a7f | 1529 | |
3f598afe JW |
1530 | (define_int_iterator FCVT_F2FIXED [UNSPEC_FCVTZS UNSPEC_FCVTZU]) |
1531 | (define_int_iterator FCVT_FIXED2F [UNSPEC_SCVTF UNSPEC_UCVTF]) | |
1532 | ||
0050faf8 JG |
1533 | (define_int_iterator FRECP [UNSPEC_FRECPE UNSPEC_FRECPX]) |
1534 | ||
5d357f26 KT |
1535 | (define_int_iterator CRC [UNSPEC_CRC32B UNSPEC_CRC32H UNSPEC_CRC32W |
1536 | UNSPEC_CRC32X UNSPEC_CRC32CB UNSPEC_CRC32CH | |
1537 | UNSPEC_CRC32CW UNSPEC_CRC32CX]) | |
1538 | ||
5a7a4e80 TB |
1539 | (define_int_iterator CRYPTO_AES [UNSPEC_AESE UNSPEC_AESD]) |
1540 | (define_int_iterator CRYPTO_AESMC [UNSPEC_AESMC UNSPEC_AESIMC]) | |
1541 | ||
30442682 TB |
1542 | (define_int_iterator CRYPTO_SHA1 [UNSPEC_SHA1C UNSPEC_SHA1M UNSPEC_SHA1P]) |
1543 | ||
b9cb0a44 TB |
1544 | (define_int_iterator CRYPTO_SHA256 [UNSPEC_SHA256H UNSPEC_SHA256H2]) |
1545 | ||
27086ea3 MC |
1546 | (define_int_iterator CRYPTO_SHA512 [UNSPEC_SHA512H UNSPEC_SHA512H2]) |
1547 | ||
1548 | (define_int_iterator CRYPTO_SM3TT [UNSPEC_SM3TT1A UNSPEC_SM3TT1B | |
1549 | UNSPEC_SM3TT2A UNSPEC_SM3TT2B]) | |
1550 | ||
1551 | (define_int_iterator CRYPTO_SM3PART [UNSPEC_SM3PARTW1 UNSPEC_SM3PARTW2]) | |
1552 | ||
1553 | ;; Iterators for fp16 operations | |
1554 | ||
1555 | (define_int_iterator VFMLA16_LOW [UNSPEC_FMLAL UNSPEC_FMLSL]) | |
1556 | ||
1557 | (define_int_iterator VFMLA16_HIGH [UNSPEC_FMLAL2 UNSPEC_FMLSL2]) | |
1558 | ||
43cacb12 RS |
1559 | (define_int_iterator UNPACK [UNSPEC_UNPACKSHI UNSPEC_UNPACKUHI |
1560 | UNSPEC_UNPACKSLO UNSPEC_UNPACKULO]) | |
1561 | ||
1562 | (define_int_iterator UNPACK_UNSIGNED [UNSPEC_UNPACKULO UNSPEC_UNPACKUHI]) | |
1563 | ||
11e9443f RS |
1564 | (define_int_iterator MUL_HIGHPART [UNSPEC_SMUL_HIGHPART UNSPEC_UMUL_HIGHPART]) |
1565 | ||
0d2b3bca | 1566 | (define_int_iterator SVE_COND_FP_BINARY [UNSPEC_COND_ADD UNSPEC_COND_SUB |
6c4fd4a9 | 1567 | UNSPEC_COND_MUL UNSPEC_COND_DIV |
0d2b3bca RS |
1568 | UNSPEC_COND_MAX UNSPEC_COND_MIN]) |
1569 | ||
43cacb12 RS |
1570 | (define_int_iterator SVE_COND_FP_CMP [UNSPEC_COND_LT UNSPEC_COND_LE |
1571 | UNSPEC_COND_EQ UNSPEC_COND_NE | |
1572 | UNSPEC_COND_GE UNSPEC_COND_GT]) | |
1573 | ||
d81cb613 MW |
1574 | ;; Iterators for atomic operations. |
1575 | ||
1576 | (define_int_iterator ATOMIC_LDOP | |
1577 | [UNSPECV_ATOMIC_LDOP_OR UNSPECV_ATOMIC_LDOP_BIC | |
1578 | UNSPECV_ATOMIC_LDOP_XOR UNSPECV_ATOMIC_LDOP_PLUS]) | |
1579 | ||
1580 | (define_int_attr atomic_ldop | |
1581 | [(UNSPECV_ATOMIC_LDOP_OR "set") (UNSPECV_ATOMIC_LDOP_BIC "clr") | |
1582 | (UNSPECV_ATOMIC_LDOP_XOR "eor") (UNSPECV_ATOMIC_LDOP_PLUS "add")]) | |
1583 | ||
43e9d192 IB |
1584 | ;; ------------------------------------------------------------------- |
1585 | ;; Int Iterators Attributes. | |
1586 | ;; ------------------------------------------------------------------- | |
43cacb12 RS |
1587 | |
1588 | ;; The optab associated with an operation. Note that for ANDF, IORF | |
1589 | ;; and XORF, the optab pattern is not actually defined; we just use this | |
1590 | ;; name for consistency with the integer patterns. | |
1591 | (define_int_attr optab [(UNSPEC_ANDF "and") | |
1592 | (UNSPEC_IORF "ior") | |
898f07b0 RS |
1593 | (UNSPEC_XORF "xor") |
1594 | (UNSPEC_ANDV "and") | |
1595 | (UNSPEC_IORV "ior") | |
0972596e RS |
1596 | (UNSPEC_XORV "xor") |
1597 | (UNSPEC_COND_ADD "add") | |
0d2b3bca | 1598 | (UNSPEC_COND_SUB "sub") |
6c4fd4a9 RS |
1599 | (UNSPEC_COND_MUL "mul") |
1600 | (UNSPEC_COND_DIV "div") | |
0d2b3bca RS |
1601 | (UNSPEC_COND_MAX "smax") |
1602 | (UNSPEC_COND_MIN "smin")]) | |
43cacb12 | 1603 | |
998eaf97 JG |
1604 | (define_int_attr maxmin_uns [(UNSPEC_UMAXV "umax") |
1605 | (UNSPEC_UMINV "umin") | |
1606 | (UNSPEC_SMAXV "smax") | |
1607 | (UNSPEC_SMINV "smin") | |
1608 | (UNSPEC_FMAX "smax_nan") | |
1609 | (UNSPEC_FMAXNMV "smax") | |
1610 | (UNSPEC_FMAXV "smax_nan") | |
1611 | (UNSPEC_FMIN "smin_nan") | |
1612 | (UNSPEC_FMINNMV "smin") | |
1efafef3 TC |
1613 | (UNSPEC_FMINV "smin_nan") |
1614 | (UNSPEC_FMAXNM "fmax") | |
1615 | (UNSPEC_FMINNM "fmin")]) | |
998eaf97 JG |
1616 | |
1617 | (define_int_attr maxmin_uns_op [(UNSPEC_UMAXV "umax") | |
1618 | (UNSPEC_UMINV "umin") | |
1619 | (UNSPEC_SMAXV "smax") | |
1620 | (UNSPEC_SMINV "smin") | |
1621 | (UNSPEC_FMAX "fmax") | |
1622 | (UNSPEC_FMAXNMV "fmaxnm") | |
1623 | (UNSPEC_FMAXV "fmax") | |
1624 | (UNSPEC_FMIN "fmin") | |
1625 | (UNSPEC_FMINNMV "fminnm") | |
1efafef3 TC |
1626 | (UNSPEC_FMINV "fmin") |
1627 | (UNSPEC_FMAXNM "fmaxnm") | |
1628 | (UNSPEC_FMINNM "fminnm")]) | |
202d0c11 | 1629 | |
898f07b0 RS |
1630 | (define_int_attr bit_reduc_op [(UNSPEC_ANDV "andv") |
1631 | (UNSPEC_IORV "orv") | |
1632 | (UNSPEC_XORV "eorv")]) | |
1633 | ||
43cacb12 RS |
1634 | ;; The SVE logical instruction that implements an unspec. |
1635 | (define_int_attr logicalf_op [(UNSPEC_ANDF "and") | |
1636 | (UNSPEC_IORF "orr") | |
1637 | (UNSPEC_XORF "eor")]) | |
1638 | ||
1639 | ;; "s" for signed operations and "u" for unsigned ones. | |
1640 | (define_int_attr su [(UNSPEC_UNPACKSHI "s") | |
1641 | (UNSPEC_UNPACKUHI "u") | |
1642 | (UNSPEC_UNPACKSLO "s") | |
11e9443f RS |
1643 | (UNSPEC_UNPACKULO "u") |
1644 | (UNSPEC_SMUL_HIGHPART "s") | |
1645 | (UNSPEC_UMUL_HIGHPART "u")]) | |
43cacb12 | 1646 | |
43e9d192 IB |
1647 | (define_int_attr sur [(UNSPEC_SHADD "s") (UNSPEC_UHADD "u") |
1648 | (UNSPEC_SRHADD "sr") (UNSPEC_URHADD "ur") | |
1649 | (UNSPEC_SHSUB "s") (UNSPEC_UHSUB "u") | |
1650 | (UNSPEC_SRHSUB "sr") (UNSPEC_URHSUB "ur") | |
1651 | (UNSPEC_ADDHN "") (UNSPEC_RADDHN "r") | |
75add2d0 KT |
1652 | (UNSPEC_SABAL "s") (UNSPEC_UABAL "u") |
1653 | (UNSPEC_SABDL2 "s") (UNSPEC_UABDL2 "u") | |
1654 | (UNSPEC_SADALP "s") (UNSPEC_UADALP "u") | |
43e9d192 IB |
1655 | (UNSPEC_SUBHN "") (UNSPEC_RSUBHN "r") |
1656 | (UNSPEC_ADDHN2 "") (UNSPEC_RADDHN2 "r") | |
1657 | (UNSPEC_SUBHN2 "") (UNSPEC_RSUBHN2 "r") | |
1658 | (UNSPEC_SQXTN "s") (UNSPEC_UQXTN "u") | |
1659 | (UNSPEC_USQADD "us") (UNSPEC_SUQADD "su") | |
1660 | (UNSPEC_SSLI "s") (UNSPEC_USLI "u") | |
1661 | (UNSPEC_SSRI "s") (UNSPEC_USRI "u") | |
1662 | (UNSPEC_USRA "u") (UNSPEC_SSRA "s") | |
1663 | (UNSPEC_URSRA "ur") (UNSPEC_SRSRA "sr") | |
1664 | (UNSPEC_URSHR "ur") (UNSPEC_SRSHR "sr") | |
1665 | (UNSPEC_SQSHLU "s") (UNSPEC_SQSHL "s") | |
1666 | (UNSPEC_UQSHL "u") | |
1667 | (UNSPEC_SQSHRUN "s") (UNSPEC_SQRSHRUN "s") | |
1668 | (UNSPEC_SQSHRN "s") (UNSPEC_UQSHRN "u") | |
1669 | (UNSPEC_SQRSHRN "s") (UNSPEC_UQRSHRN "u") | |
1670 | (UNSPEC_USHL "u") (UNSPEC_SSHL "s") | |
1671 | (UNSPEC_USHLL "u") (UNSPEC_SSHLL "s") | |
1672 | (UNSPEC_URSHL "ur") (UNSPEC_SRSHL "sr") | |
1673 | (UNSPEC_UQRSHL "u") (UNSPEC_SQRSHL "s") | |
7a08d813 | 1674 | (UNSPEC_SDOT "s") (UNSPEC_UDOT "u") |
43e9d192 IB |
1675 | ]) |
1676 | ||
1677 | (define_int_attr r [(UNSPEC_SQDMULH "") (UNSPEC_SQRDMULH "r") | |
1678 | (UNSPEC_SQSHRUN "") (UNSPEC_SQRSHRUN "r") | |
1679 | (UNSPEC_SQSHRN "") (UNSPEC_UQSHRN "") | |
1680 | (UNSPEC_SQRSHRN "r") (UNSPEC_UQRSHRN "r") | |
1681 | (UNSPEC_SQSHL "") (UNSPEC_UQSHL "") | |
1682 | (UNSPEC_SQRSHL "r")(UNSPEC_UQRSHL "r") | |
1683 | ]) | |
1684 | ||
1685 | (define_int_attr lr [(UNSPEC_SSLI "l") (UNSPEC_USLI "l") | |
1686 | (UNSPEC_SSRI "r") (UNSPEC_USRI "r")]) | |
1687 | ||
1688 | (define_int_attr u [(UNSPEC_SQSHLU "u") (UNSPEC_SQSHL "") (UNSPEC_UQSHL "") | |
1689 | (UNSPEC_SQSHRUN "u") (UNSPEC_SQRSHRUN "u") | |
42addb5a RS |
1690 | (UNSPEC_SQSHRN "") (UNSPEC_UQSHRN "") |
1691 | (UNSPEC_SQRSHRN "") (UNSPEC_UQRSHRN "") | |
1692 | (UNSPEC_SHADD "") (UNSPEC_UHADD "u") | |
1693 | (UNSPEC_SRHADD "") (UNSPEC_URHADD "u")]) | |
43e9d192 IB |
1694 | |
1695 | (define_int_attr addsub [(UNSPEC_SHADD "add") | |
1696 | (UNSPEC_UHADD "add") | |
1697 | (UNSPEC_SRHADD "add") | |
1698 | (UNSPEC_URHADD "add") | |
1699 | (UNSPEC_SHSUB "sub") | |
1700 | (UNSPEC_UHSUB "sub") | |
1701 | (UNSPEC_SRHSUB "sub") | |
1702 | (UNSPEC_URHSUB "sub") | |
1703 | (UNSPEC_ADDHN "add") | |
1704 | (UNSPEC_SUBHN "sub") | |
1705 | (UNSPEC_RADDHN "add") | |
1706 | (UNSPEC_RSUBHN "sub") | |
1707 | (UNSPEC_ADDHN2 "add") | |
1708 | (UNSPEC_SUBHN2 "sub") | |
1709 | (UNSPEC_RADDHN2 "add") | |
1710 | (UNSPEC_RSUBHN2 "sub")]) | |
1711 | ||
cb23a30c JG |
1712 | (define_int_attr offsetlr [(UNSPEC_SSLI "") (UNSPEC_USLI "") |
1713 | (UNSPEC_SSRI "offset_") | |
1714 | (UNSPEC_USRI "offset_")]) | |
43e9d192 | 1715 | |
42fc9a7f JG |
1716 | ;; Standard pattern names for floating-point rounding instructions. |
1717 | (define_int_attr frint_pattern [(UNSPEC_FRINTZ "btrunc") | |
1718 | (UNSPEC_FRINTP "ceil") | |
1719 | (UNSPEC_FRINTM "floor") | |
1720 | (UNSPEC_FRINTI "nearbyint") | |
1721 | (UNSPEC_FRINTX "rint") | |
0659ce6f JG |
1722 | (UNSPEC_FRINTA "round") |
1723 | (UNSPEC_FRINTN "frintn")]) | |
42fc9a7f JG |
1724 | |
1725 | ;; frint suffix for floating-point rounding instructions. | |
1726 | (define_int_attr frint_suffix [(UNSPEC_FRINTZ "z") (UNSPEC_FRINTP "p") | |
1727 | (UNSPEC_FRINTM "m") (UNSPEC_FRINTI "i") | |
0659ce6f JG |
1728 | (UNSPEC_FRINTX "x") (UNSPEC_FRINTA "a") |
1729 | (UNSPEC_FRINTN "n")]) | |
42fc9a7f JG |
1730 | |
1731 | (define_int_attr fcvt_pattern [(UNSPEC_FRINTZ "btrunc") (UNSPEC_FRINTA "round") | |
ce966824 JG |
1732 | (UNSPEC_FRINTP "ceil") (UNSPEC_FRINTM "floor") |
1733 | (UNSPEC_FRINTN "frintn")]) | |
42fc9a7f | 1734 | |
3f598afe JW |
1735 | (define_int_attr fcvt_fixed_insn [(UNSPEC_SCVTF "scvtf") |
1736 | (UNSPEC_UCVTF "ucvtf") | |
1737 | (UNSPEC_FCVTZS "fcvtzs") | |
1738 | (UNSPEC_FCVTZU "fcvtzu")]) | |
1739 | ||
db58fd89 JW |
1740 | ;; Pointer authentication mnemonic prefix. |
1741 | (define_int_attr pauth_mnem_prefix [(UNSPEC_PACISP "paci") | |
1742 | (UNSPEC_AUTISP "auti") | |
1743 | (UNSPEC_PACI1716 "paci") | |
1744 | (UNSPEC_AUTI1716 "auti")]) | |
1745 | ||
1746 | ;; Pointer authentication HINT number for NOP space instructions using A Key. | |
1747 | (define_int_attr pauth_hint_num_a [(UNSPEC_PACISP "25") | |
1748 | (UNSPEC_AUTISP "29") | |
1749 | (UNSPEC_PACI1716 "8") | |
1750 | (UNSPEC_AUTI1716 "12")]) | |
1751 | ||
cc4d934f JG |
1752 | (define_int_attr perm_insn [(UNSPEC_ZIP1 "zip") (UNSPEC_ZIP2 "zip") |
1753 | (UNSPEC_TRN1 "trn") (UNSPEC_TRN2 "trn") | |
1754 | (UNSPEC_UZP1 "uzp") (UNSPEC_UZP2 "uzp")]) | |
1755 | ||
923fcec3 AL |
1756 | ; op code for REV instructions (size within which elements are reversed). |
1757 | (define_int_attr rev_op [(UNSPEC_REV64 "64") (UNSPEC_REV32 "32") | |
1758 | (UNSPEC_REV16 "16")]) | |
1759 | ||
cc4d934f JG |
1760 | (define_int_attr perm_hilo [(UNSPEC_ZIP1 "1") (UNSPEC_ZIP2 "2") |
1761 | (UNSPEC_TRN1 "1") (UNSPEC_TRN2 "2") | |
43cacb12 RS |
1762 | (UNSPEC_UZP1 "1") (UNSPEC_UZP2 "2") |
1763 | (UNSPEC_UNPACKSHI "hi") (UNSPEC_UNPACKUHI "hi") | |
1764 | (UNSPEC_UNPACKSLO "lo") (UNSPEC_UNPACKULO "lo")]) | |
0050faf8 | 1765 | |
9bfb28ed RS |
1766 | ;; Return true if the associated optab refers to the high-numbered lanes, |
1767 | ;; false if it refers to the low-numbered lanes. The convention is for | |
1768 | ;; "hi" to refer to the low-numbered lanes (the first ones in memory) | |
1769 | ;; for big-endian. | |
1770 | (define_int_attr hi_lanes_optab [(UNSPEC_UNPACKSHI "!BYTES_BIG_ENDIAN") | |
1771 | (UNSPEC_UNPACKUHI "!BYTES_BIG_ENDIAN") | |
1772 | (UNSPEC_UNPACKSLO "BYTES_BIG_ENDIAN") | |
1773 | (UNSPEC_UNPACKULO "BYTES_BIG_ENDIAN")]) | |
1774 | ||
0050faf8 | 1775 | (define_int_attr frecp_suffix [(UNSPEC_FRECPE "e") (UNSPEC_FRECPX "x")]) |
5a7a4e80 | 1776 | |
5d357f26 KT |
1777 | (define_int_attr crc_variant [(UNSPEC_CRC32B "crc32b") (UNSPEC_CRC32H "crc32h") |
1778 | (UNSPEC_CRC32W "crc32w") (UNSPEC_CRC32X "crc32x") | |
1779 | (UNSPEC_CRC32CB "crc32cb") (UNSPEC_CRC32CH "crc32ch") | |
1780 | (UNSPEC_CRC32CW "crc32cw") (UNSPEC_CRC32CX "crc32cx")]) | |
1781 | ||
1782 | (define_int_attr crc_mode [(UNSPEC_CRC32B "QI") (UNSPEC_CRC32H "HI") | |
1783 | (UNSPEC_CRC32W "SI") (UNSPEC_CRC32X "DI") | |
1784 | (UNSPEC_CRC32CB "QI") (UNSPEC_CRC32CH "HI") | |
1785 | (UNSPEC_CRC32CW "SI") (UNSPEC_CRC32CX "DI")]) | |
1786 | ||
5a7a4e80 TB |
1787 | (define_int_attr aes_op [(UNSPEC_AESE "e") (UNSPEC_AESD "d")]) |
1788 | (define_int_attr aesmc_op [(UNSPEC_AESMC "mc") (UNSPEC_AESIMC "imc")]) | |
30442682 TB |
1789 | |
1790 | (define_int_attr sha1_op [(UNSPEC_SHA1C "c") (UNSPEC_SHA1P "p") | |
1791 | (UNSPEC_SHA1M "m")]) | |
b9cb0a44 TB |
1792 | |
1793 | (define_int_attr sha256_op [(UNSPEC_SHA256H "") (UNSPEC_SHA256H2 "2")]) | |
57b26d65 MW |
1794 | |
1795 | (define_int_attr rdma_as [(UNSPEC_SQRDMLAH "a") (UNSPEC_SQRDMLSH "s")]) | |
27086ea3 MC |
1796 | |
1797 | (define_int_attr sha512_op [(UNSPEC_SHA512H "") (UNSPEC_SHA512H2 "2")]) | |
1798 | ||
1799 | (define_int_attr sm3tt_op [(UNSPEC_SM3TT1A "1a") (UNSPEC_SM3TT1B "1b") | |
1800 | (UNSPEC_SM3TT2A "2a") (UNSPEC_SM3TT2B "2b")]) | |
1801 | ||
1802 | (define_int_attr sm3part_op [(UNSPEC_SM3PARTW1 "1") (UNSPEC_SM3PARTW2 "2")]) | |
1803 | ||
1804 | (define_int_attr f16mac1 [(UNSPEC_FMLAL "a") (UNSPEC_FMLSL "s") | |
1805 | (UNSPEC_FMLAL2 "a") (UNSPEC_FMLSL2 "s")]) | |
43cacb12 RS |
1806 | |
1807 | ;; The condition associated with an UNSPEC_COND_<xx>. | |
1808 | (define_int_attr cmp_op [(UNSPEC_COND_LT "lt") | |
1809 | (UNSPEC_COND_LE "le") | |
1810 | (UNSPEC_COND_EQ "eq") | |
1811 | (UNSPEC_COND_NE "ne") | |
1812 | (UNSPEC_COND_GE "ge") | |
f22d7973 | 1813 | (UNSPEC_COND_GT "gt")]) |
0972596e | 1814 | |
0972596e | 1815 | (define_int_attr sve_fp_op [(UNSPEC_COND_ADD "fadd") |
0d2b3bca | 1816 | (UNSPEC_COND_SUB "fsub") |
6c4fd4a9 RS |
1817 | (UNSPEC_COND_MUL "fmul") |
1818 | (UNSPEC_COND_DIV "fdiv") | |
0d2b3bca RS |
1819 | (UNSPEC_COND_MAX "fmaxnm") |
1820 | (UNSPEC_COND_MIN "fminnm")]) | |
1821 | ||
a08acce8 RH |
1822 | (define_int_attr sve_fp_op_rev [(UNSPEC_COND_ADD "fadd") |
1823 | (UNSPEC_COND_SUB "fsubr") | |
1824 | (UNSPEC_COND_MUL "fmul") | |
1825 | (UNSPEC_COND_DIV "fdivr") | |
1826 | (UNSPEC_COND_MAX "fmaxnm") | |
1827 | (UNSPEC_COND_MIN "fminnm")]) | |
1828 | ||
0d2b3bca RS |
1829 | (define_int_attr commutative [(UNSPEC_COND_ADD "true") |
1830 | (UNSPEC_COND_SUB "false") | |
6c4fd4a9 RS |
1831 | (UNSPEC_COND_MUL "true") |
1832 | (UNSPEC_COND_DIV "false") | |
0d2b3bca RS |
1833 | (UNSPEC_COND_MIN "true") |
1834 | (UNSPEC_COND_MAX "true")]) |