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43e9d192 1;; Machine description for AArch64 architecture.
85ec4feb 2;; Copyright (C) 2009-2018 Free Software Foundation, Inc.
43e9d192
IB		 3;; Contributed by ARM Ltd.
4;;
5;; This file is part of GCC.
6;;
7;; GCC is free software; you can redistribute it and/or modify it
8;; under the terms of the GNU General Public License as published by
9;; the Free Software Foundation; either version 3, or (at your option)
10;; any later version.
11;;
12;; GCC is distributed in the hope that it will be useful, but
13;; WITHOUT ANY WARRANTY; without even the implied warranty of
14;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15;; General Public License for more details.
16;;
17;; You should have received a copy of the GNU General Public License
18;; along with GCC; see the file COPYING3. If not see
19;; <http://www.gnu.org/licenses/>.
20
21;; -------------------------------------------------------------------
22;; Mode Iterators
23;; -------------------------------------------------------------------
24
25
26;; Iterator for General Purpose Integer registers (32- and 64-bit modes)
27(define_mode_iterator GPI [SI DI])
28
d7f33f07
JW		 29;; Iterator for HI, SI, DI, some instructions can only work on these modes.
30(define_mode_iterator GPI_I16 [(HI "AARCH64_ISA_F16") SI DI])
31
43e9d192
IB		 32;; Iterator for QI and HI modes
33(define_mode_iterator SHORT [QI HI])
34
35;; Iterator for all integer modes (up to 64-bit)
36(define_mode_iterator ALLI [QI HI SI DI])
37
43e9d192
IB		 38;; Iterator for all integer modes that can be extended (up to 64-bit)
39(define_mode_iterator ALLX [QI HI SI])
40
41;; Iterator for General Purpose Floating-point registers (32- and 64-bit modes)
42(define_mode_iterator GPF [SF DF])
43
d7f33f07
JW		 44;; Iterator for all scalar floating point modes (HF, SF, DF)
45(define_mode_iterator GPF_F16 [(HF "AARCH64_ISA_F16") SF DF])
46
90e6443f
TC		 47;; Iterator for all scalar floating point modes (HF, SF, DF)
48(define_mode_iterator GPF_HF [HF SF DF])
49
09fcd8e1
RR		 50;; Iterator for all scalar floating point modes (HF, SF, DF and TF)
51(define_mode_iterator GPF_TF_F16 [HF SF DF TF])
c2ec330c 52
922f9c25
AL		 53;; Double vector modes.
54(define_mode_iterator VDF [V2SF V4HF])
55
b4f50fd4
RR		 56;; Iterator for all scalar floating point modes (SF, DF and TF)
57(define_mode_iterator GPF_TF [SF DF TF])
58
43cacb12 59;; Integer Advanced SIMD modes.
43e9d192
IB		 60(define_mode_iterator VDQ_I [V8QI V16QI V4HI V8HI V2SI V4SI V2DI])
61
43cacb12 62;; Advanced SIMD and scalar, 64 & 128-bit container, all integer modes.
43e9d192
IB		 63(define_mode_iterator VSDQ_I [V8QI V16QI V4HI V8HI V2SI V4SI V2DI QI HI SI DI])
64
43cacb12
RS		 65;; Advanced SIMD and scalar, 64 & 128-bit container: all Advanced SIMD
66;; integer modes; 64-bit scalar integer mode.
43e9d192
IB		 67(define_mode_iterator VSDQ_I_DI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI DI])
68
69;; Double vector modes.
71a11456 70(define_mode_iterator VD [V8QI V4HI V4HF V2SI V2SF])
43e9d192 71
43cacb12 72;; Advanced SIMD, 64-bit container, all integer modes.
43e9d192
IB		 73(define_mode_iterator VD_BHSI [V8QI V4HI V2SI])
74
75;; 128 and 64-bit container; 8, 16, 32-bit vector integer modes
76(define_mode_iterator VDQ_BHSI [V8QI V16QI V4HI V8HI V2SI V4SI])
77
78;; Quad vector modes.
71a11456 79(define_mode_iterator VQ [V16QI V8HI V4SI V2DI V8HF V4SF V2DF])
43e9d192 80
d21052eb
TC		 81;; Quad integer vector modes.
82(define_mode_iterator VQ_I [V16QI V8HI V4SI V2DI])
83
51437269 84;; VQ without 2 element modes.
71a11456 85(define_mode_iterator VQ_NO2E [V16QI V8HI V4SI V8HF V4SF])
51437269
GW		 86
87;; Quad vector with only 2 element modes.
88(define_mode_iterator VQ_2E [V2DI V2DF])
89
28514dda
YZ		 90;; This mode iterator allows :P to be used for patterns that operate on
91;; addresses in different modes. In LP64, only DI will match, while in
92;; ILP32, either can match.
93(define_mode_iterator P [(SI "ptr_mode == SImode || Pmode == SImode")
94 (DI "ptr_mode == DImode || Pmode == DImode")])
95
43e9d192
IB		 96;; This mode iterator allows :PTR to be used for patterns that operate on
97;; pointer-sized quantities. Exactly one of the two alternatives will match.
28514dda 98(define_mode_iterator PTR [(SI "ptr_mode == SImode") (DI "ptr_mode == DImode")])
43e9d192 99
43cacb12 100;; Advanced SIMD Float modes suitable for moving, loading and storing.
862abc04
AL		 101(define_mode_iterator VDQF_F16 [V4HF V8HF V2SF V4SF V2DF])
102
43cacb12 103;; Advanced SIMD Float modes.
43e9d192 104(define_mode_iterator VDQF [V2SF V4SF V2DF])
daef0a8c
JW		 105(define_mode_iterator VHSDF [(V4HF "TARGET_SIMD_F16INST")
106 (V8HF "TARGET_SIMD_F16INST")
107 V2SF V4SF V2DF])
43e9d192 108
43cacb12 109;; Advanced SIMD Float modes, and DF.
daef0a8c
JW		 110(define_mode_iterator VHSDF_DF [(V4HF "TARGET_SIMD_F16INST")
111 (V8HF "TARGET_SIMD_F16INST")
112 V2SF V4SF V2DF DF])
d7f33f07
JW		 113(define_mode_iterator VHSDF_HSDF [(V4HF "TARGET_SIMD_F16INST")
114 (V8HF "TARGET_SIMD_F16INST")
115 V2SF V4SF V2DF
116 (HF "TARGET_SIMD_F16INST")
117 SF DF])
f421c516 118
43cacb12 119;; Advanced SIMD single Float modes.
828e70c1
JG		 120(define_mode_iterator VDQSF [V2SF V4SF])
121
03873eb9
AL		 122;; Quad vector Float modes with half/single elements.
123(define_mode_iterator VQ_HSF [V8HF V4SF])
124
fc21784d
JG		 125;; Modes suitable to use as the return type of a vcond expression.
126(define_mode_iterator VDQF_COND [V2SF V2SI V4SF V4SI V2DF V2DI])
127
43cacb12 128;; All scalar and Advanced SIMD Float modes.
889b9412
JG		 129(define_mode_iterator VALLF [V2SF V4SF V2DF SF DF])
130
43cacb12 131;; Advanced SIMD Float modes with 2 elements.
43e9d192
IB		 132(define_mode_iterator V2F [V2SF V2DF])
133
43cacb12 134;; All Advanced SIMD modes on which we support any arithmetic operations.
43e9d192
IB		 135(define_mode_iterator VALL [V8QI V16QI V4HI V8HI V2SI V4SI V2DI V2SF V4SF V2DF])
136
43cacb12 137;; All Advanced SIMD modes suitable for moving, loading, and storing.
71a11456
AL		 138(define_mode_iterator VALL_F16 [V8QI V16QI V4HI V8HI V2SI V4SI V2DI
139 V4HF V8HF V2SF V4SF V2DF])
140
88119b46
KT		 141;; The VALL_F16 modes except the 128-bit 2-element ones.
142(define_mode_iterator VALL_F16_NO_V2Q [V8QI V16QI V4HI V8HI V2SI V4SI
143 V4HF V8HF V2SF V4SF])
144
43cacb12 145;; All Advanced SIMD modes barring HF modes, plus DI.
a50344cb
TB		 146(define_mode_iterator VALLDI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI V2SF V4SF V2DF DI])
147
43cacb12 148;; All Advanced SIMD modes and DI.
71a11456
AL		 149(define_mode_iterator VALLDI_F16 [V8QI V16QI V4HI V8HI V2SI V4SI V2DI
150 V4HF V8HF V2SF V4SF V2DF DI])
151
43cacb12 152;; All Advanced SIMD modes, plus DI and DF.
46e778c4 153(define_mode_iterator VALLDIF [V8QI V16QI V4HI V8HI V2SI V4SI
7c369485 154 V2DI V4HF V8HF V2SF V4SF V2DF DI DF])
46e778c4 155
43cacb12 156;; Advanced SIMD modes for Integer reduction across lanes.
92835317
TB		 157(define_mode_iterator VDQV [V8QI V16QI V4HI V8HI V4SI V2DI])
158
43cacb12 159;; Advanced SIMD modes (except V2DI) for Integer reduction across lanes.
92835317 160(define_mode_iterator VDQV_S [V8QI V16QI V4HI V8HI V4SI])
43e9d192
IB		 161
162;; All double integer narrow-able modes.
163(define_mode_iterator VDN [V4HI V2SI DI])
164
165;; All quad integer narrow-able modes.
166(define_mode_iterator VQN [V8HI V4SI V2DI])
167
43cacb12
RS		 168;; Advanced SIMD and scalar 128-bit container: narrowable 16, 32, 64-bit
169;; integer modes
43e9d192
IB		 170(define_mode_iterator VSQN_HSDI [V8HI V4SI V2DI HI SI DI])
171
172;; All quad integer widen-able modes.
173(define_mode_iterator VQW [V16QI V8HI V4SI])
174
175;; Double vector modes for combines.
7c369485 176(define_mode_iterator VDC [V8QI V4HI V4HF V2SI V2SF DI DF])
43e9d192 177
43cacb12 178;; Advanced SIMD modes except double int.
43e9d192 179(define_mode_iterator VDQIF [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF V2DF])
703bbcdf
JW		 180(define_mode_iterator VDQIF_F16 [V8QI V16QI V4HI V8HI V2SI V4SI
181 V4HF V8HF V2SF V4SF V2DF])
43e9d192 182
43cacb12 183;; Advanced SIMD modes for S type.
58a3bd25
FY		 184(define_mode_iterator VDQ_SI [V2SI V4SI])
185
43cacb12 186;; Advanced SIMD modes for S and D.
2644d4d9
JW		 187(define_mode_iterator VDQ_SDI [V2SI V4SI V2DI])
188
43cacb12 189;; Advanced SIMD modes for H, S and D.
33d72b63
JW		 190(define_mode_iterator VDQ_HSDI [(V4HI "TARGET_SIMD_F16INST")
191 (V8HI "TARGET_SIMD_F16INST")
192 V2SI V4SI V2DI])
193
43cacb12 194;; Scalar and Advanced SIMD modes for S and D.
2644d4d9
JW		 195(define_mode_iterator VSDQ_SDI [V2SI V4SI V2DI SI DI])
196
43cacb12 197;; Scalar and Advanced SIMD modes for S and D, Advanced SIMD modes for H.
33d72b63
JW		 198(define_mode_iterator VSDQ_HSDI [(V4HI "TARGET_SIMD_F16INST")
199 (V8HI "TARGET_SIMD_F16INST")
68ad28c3
JW		 200 V2SI V4SI V2DI
201 (HI "TARGET_SIMD_F16INST")
202 SI DI])
33d72b63 203
43cacb12 204;; Advanced SIMD modes for Q and H types.
66adb8eb
JG		 205(define_mode_iterator VDQQH [V8QI V16QI V4HI V8HI])
206
43cacb12 207;; Advanced SIMD modes for H and S types.
43e9d192
IB		 208(define_mode_iterator VDQHS [V4HI V8HI V2SI V4SI])
209
43cacb12 210;; Advanced SIMD modes for H, S and D types.
c7f28cd5
KT		 211(define_mode_iterator VDQHSD [V4HI V8HI V2SI V4SI V2DI])
212
43cacb12 213;; Advanced SIMD and scalar integer modes for H and S.
43e9d192
IB		 214(define_mode_iterator VSDQ_HSI [V4HI V8HI V2SI V4SI HI SI])
215
43cacb12 216;; Advanced SIMD and scalar 64-bit container: 16, 32-bit integer modes.
43e9d192
IB		 217(define_mode_iterator VSD_HSI [V4HI V2SI HI SI])
218
43cacb12 219;; Advanced SIMD 64-bit container: 16, 32-bit integer modes.
43e9d192
IB		 220(define_mode_iterator VD_HSI [V4HI V2SI])
221
222;; Scalar 64-bit container: 16, 32-bit integer modes
223(define_mode_iterator SD_HSI [HI SI])
224
43cacb12 225;; Advanced SIMD 64-bit container: 16, 32-bit integer modes.
43e9d192
IB		 226(define_mode_iterator VQ_HSI [V8HI V4SI])
227
228;; All byte modes.
229(define_mode_iterator VB [V8QI V16QI])
230
5e32e83b
JW		 231;; 2 and 4 lane SI modes.
232(define_mode_iterator VS [V2SI V4SI])
233
43e9d192
IB		 234(define_mode_iterator TX [TI TF])
235
43cacb12 236;; Advanced SIMD opaque structure modes.
43e9d192
IB		 237(define_mode_iterator VSTRUCT [OI CI XI])
238
239;; Double scalar modes
240(define_mode_iterator DX [DI DF])
241
43cacb12 242;; Modes available for Advanced SIMD <f>mul lane operations.
ab2e8f01
JW		 243(define_mode_iterator VMUL [V4HI V8HI V2SI V4SI
244 (V4HF "TARGET_SIMD_F16INST")
245 (V8HF "TARGET_SIMD_F16INST")
246 V2SF V4SF V2DF])
779aea46 247
43cacb12
RS		 248;; Modes available for Advanced SIMD <f>mul lane operations changing lane
249;; count.
779aea46
JG		 250(define_mode_iterator VMUL_CHANGE_NLANES [V4HI V8HI V2SI V4SI V2SF V4SF])
251
43cacb12
RS		 252;; All SVE vector modes.
253(define_mode_iterator SVE_ALL [VNx16QI VNx8HI VNx4SI VNx2DI
254 VNx8HF VNx4SF VNx2DF])
255
9f4cbab8
RS		 256;; All SVE vector structure modes.
257(define_mode_iterator SVE_STRUCT [VNx32QI VNx16HI VNx8SI VNx4DI
258 VNx16HF VNx8SF VNx4DF
259 VNx48QI VNx24HI VNx12SI VNx6DI
260 VNx24HF VNx12SF VNx6DF
261 VNx64QI VNx32HI VNx16SI VNx8DI
262 VNx32HF VNx16SF VNx8DF])
263
43cacb12
RS		 264;; All SVE vector modes that have 8-bit or 16-bit elements.
265(define_mode_iterator SVE_BH [VNx16QI VNx8HI VNx8HF])
266
267;; All SVE vector modes that have 8-bit, 16-bit or 32-bit elements.
268(define_mode_iterator SVE_BHS [VNx16QI VNx8HI VNx4SI VNx8HF VNx4SF])
269
270;; All SVE integer vector modes that have 8-bit, 16-bit or 32-bit elements.
271(define_mode_iterator SVE_BHSI [VNx16QI VNx8HI VNx4SI])
272
273;; All SVE integer vector modes that have 16-bit, 32-bit or 64-bit elements.
274(define_mode_iterator SVE_HSDI [VNx16QI VNx8HI VNx4SI])
275
276;; All SVE floating-point vector modes that have 16-bit or 32-bit elements.
277(define_mode_iterator SVE_HSF [VNx8HF VNx4SF])
278
279;; All SVE vector modes that have 32-bit or 64-bit elements.
280(define_mode_iterator SVE_SD [VNx4SI VNx2DI VNx4SF VNx2DF])
281
bfaa08b7
RS		 282;; All SVE vector modes that have 32-bit elements.
283(define_mode_iterator SVE_S [VNx4SI VNx4SF])
284
285;; All SVE vector modes that have 64-bit elements.
286(define_mode_iterator SVE_D [VNx2DI VNx2DF])
287
43cacb12
RS		 288;; All SVE integer vector modes that have 32-bit or 64-bit elements.
289(define_mode_iterator SVE_SDI [VNx4SI VNx2DI])
290
291;; All SVE integer vector modes.
292(define_mode_iterator SVE_I [VNx16QI VNx8HI VNx4SI VNx2DI])
293
294;; All SVE floating-point vector modes.
295(define_mode_iterator SVE_F [VNx8HF VNx4SF VNx2DF])
296
297;; All SVE predicate modes.
298(define_mode_iterator PRED_ALL [VNx16BI VNx8BI VNx4BI VNx2BI])
299
300;; SVE predicate modes that control 8-bit, 16-bit or 32-bit elements.
301(define_mode_iterator PRED_BHS [VNx16BI VNx8BI VNx4BI])
302
43e9d192
IB		 303;; ------------------------------------------------------------------
304;; Unspec enumerations for Advance SIMD. These could well go into
305;; aarch64.md but for their use in int_iterators here.
306;; ------------------------------------------------------------------
307
308(define_c_enum "unspec"
309 [
310 UNSPEC_ASHIFT_SIGNED ; Used in aarch-simd.md.
311 UNSPEC_ASHIFT_UNSIGNED ; Used in aarch64-simd.md.
285398d2 312 UNSPEC_ABS ; Used in aarch64-simd.md.
998eaf97
JG		 313 UNSPEC_FMAX ; Used in aarch64-simd.md.
314 UNSPEC_FMAXNMV ; Used in aarch64-simd.md.
43e9d192 315 UNSPEC_FMAXV ; Used in aarch64-simd.md.
998eaf97
JG		 316 UNSPEC_FMIN ; Used in aarch64-simd.md.
317 UNSPEC_FMINNMV ; Used in aarch64-simd.md.
43e9d192
IB		 318 UNSPEC_FMINV ; Used in aarch64-simd.md.
319 UNSPEC_FADDV ; Used in aarch64-simd.md.
f5156c3e 320 UNSPEC_ADDV ; Used in aarch64-simd.md.
43e9d192
IB		 321 UNSPEC_SMAXV ; Used in aarch64-simd.md.
322 UNSPEC_SMINV ; Used in aarch64-simd.md.
323 UNSPEC_UMAXV ; Used in aarch64-simd.md.
324 UNSPEC_UMINV ; Used in aarch64-simd.md.
325 UNSPEC_SHADD ; Used in aarch64-simd.md.
326 UNSPEC_UHADD ; Used in aarch64-simd.md.
327 UNSPEC_SRHADD ; Used in aarch64-simd.md.
328 UNSPEC_URHADD ; Used in aarch64-simd.md.
329 UNSPEC_SHSUB ; Used in aarch64-simd.md.
330 UNSPEC_UHSUB ; Used in aarch64-simd.md.
331 UNSPEC_SRHSUB ; Used in aarch64-simd.md.
332 UNSPEC_URHSUB ; Used in aarch64-simd.md.
333 UNSPEC_ADDHN ; Used in aarch64-simd.md.
334 UNSPEC_RADDHN ; Used in aarch64-simd.md.
335 UNSPEC_SUBHN ; Used in aarch64-simd.md.
336 UNSPEC_RSUBHN ; Used in aarch64-simd.md.
337 UNSPEC_ADDHN2 ; Used in aarch64-simd.md.
338 UNSPEC_RADDHN2 ; Used in aarch64-simd.md.
339 UNSPEC_SUBHN2 ; Used in aarch64-simd.md.
340 UNSPEC_RSUBHN2 ; Used in aarch64-simd.md.
341 UNSPEC_SQDMULH ; Used in aarch64-simd.md.
342 UNSPEC_SQRDMULH ; Used in aarch64-simd.md.
343 UNSPEC_PMUL ; Used in aarch64-simd.md.
496ea87d 344 UNSPEC_FMULX ; Used in aarch64-simd.md.
43e9d192
IB		 345 UNSPEC_USQADD ; Used in aarch64-simd.md.
346 UNSPEC_SUQADD ; Used in aarch64-simd.md.
347 UNSPEC_SQXTUN ; Used in aarch64-simd.md.
348 UNSPEC_SQXTN ; Used in aarch64-simd.md.
349 UNSPEC_UQXTN ; Used in aarch64-simd.md.
350 UNSPEC_SSRA ; Used in aarch64-simd.md.
351 UNSPEC_USRA ; Used in aarch64-simd.md.
352 UNSPEC_SRSRA ; Used in aarch64-simd.md.
353 UNSPEC_URSRA ; Used in aarch64-simd.md.
354 UNSPEC_SRSHR ; Used in aarch64-simd.md.
355 UNSPEC_URSHR ; Used in aarch64-simd.md.
356 UNSPEC_SQSHLU ; Used in aarch64-simd.md.
357 UNSPEC_SQSHL ; Used in aarch64-simd.md.
358 UNSPEC_UQSHL ; Used in aarch64-simd.md.
359 UNSPEC_SQSHRUN ; Used in aarch64-simd.md.
360 UNSPEC_SQRSHRUN ; Used in aarch64-simd.md.
361 UNSPEC_SQSHRN ; Used in aarch64-simd.md.
362 UNSPEC_UQSHRN ; Used in aarch64-simd.md.
363 UNSPEC_SQRSHRN ; Used in aarch64-simd.md.
364 UNSPEC_UQRSHRN ; Used in aarch64-simd.md.
365 UNSPEC_SSHL ; Used in aarch64-simd.md.
366 UNSPEC_USHL ; Used in aarch64-simd.md.
367 UNSPEC_SRSHL ; Used in aarch64-simd.md.
368 UNSPEC_URSHL ; Used in aarch64-simd.md.
369 UNSPEC_SQRSHL ; Used in aarch64-simd.md.
370 UNSPEC_UQRSHL ; Used in aarch64-simd.md.
43e9d192
IB		 371 UNSPEC_SSLI ; Used in aarch64-simd.md.
372 UNSPEC_USLI ; Used in aarch64-simd.md.
373 UNSPEC_SSRI ; Used in aarch64-simd.md.
374 UNSPEC_USRI ; Used in aarch64-simd.md.
375 UNSPEC_SSHLL ; Used in aarch64-simd.md.
376 UNSPEC_USHLL ; Used in aarch64-simd.md.
377 UNSPEC_ADDP ; Used in aarch64-simd.md.
88b08073 378 UNSPEC_TBL ; Used in vector permute patterns.
9371aecc 379 UNSPEC_TBX ; Used in vector permute patterns.
88b08073 380 UNSPEC_CONCAT ; Used in vector permute patterns.
3f8334a5
RS		 381
382 ;; The following permute unspecs are generated directly by
383 ;; aarch64_expand_vec_perm_const, so any changes to the underlying
384 ;; instructions would need a corresponding change there.
cc4d934f
JG		 385 UNSPEC_ZIP1 ; Used in vector permute patterns.
386 UNSPEC_ZIP2 ; Used in vector permute patterns.
387 UNSPEC_UZP1 ; Used in vector permute patterns.
388 UNSPEC_UZP2 ; Used in vector permute patterns.
389 UNSPEC_TRN1 ; Used in vector permute patterns.
390 UNSPEC_TRN2 ; Used in vector permute patterns.
3f8334a5 391 UNSPEC_EXT ; Used in vector permute patterns.
923fcec3
AL		 392 UNSPEC_REV64 ; Used in vector reverse patterns (permute).
393 UNSPEC_REV32 ; Used in vector reverse patterns (permute).
394 UNSPEC_REV16 ; Used in vector reverse patterns (permute).
3f8334a5 395
5a7a4e80
TB		 396 UNSPEC_AESE ; Used in aarch64-simd.md.
397 UNSPEC_AESD ; Used in aarch64-simd.md.
398 UNSPEC_AESMC ; Used in aarch64-simd.md.
399 UNSPEC_AESIMC ; Used in aarch64-simd.md.
30442682
TB		 400 UNSPEC_SHA1C ; Used in aarch64-simd.md.
401 UNSPEC_SHA1M ; Used in aarch64-simd.md.
402 UNSPEC_SHA1P ; Used in aarch64-simd.md.
403 UNSPEC_SHA1H ; Used in aarch64-simd.md.
404 UNSPEC_SHA1SU0 ; Used in aarch64-simd.md.
405 UNSPEC_SHA1SU1 ; Used in aarch64-simd.md.
b9cb0a44
TB		 406 UNSPEC_SHA256H ; Used in aarch64-simd.md.
407 UNSPEC_SHA256H2 ; Used in aarch64-simd.md.
408 UNSPEC_SHA256SU0 ; Used in aarch64-simd.md.
409 UNSPEC_SHA256SU1 ; Used in aarch64-simd.md.
7baa225d
TB		 410 UNSPEC_PMULL ; Used in aarch64-simd.md.
411 UNSPEC_PMULL2 ; Used in aarch64-simd.md.
668046d1 412 UNSPEC_REV_REGLIST ; Used in aarch64-simd.md.
9c004c58 413 UNSPEC_VEC_SHR ; Used in aarch64-simd.md.
57b26d65
MW		 414 UNSPEC_SQRDMLAH ; Used in aarch64-simd.md.
415 UNSPEC_SQRDMLSH ; Used in aarch64-simd.md.
202d0c11
DS		 416 UNSPEC_FMAXNM ; Used in aarch64-simd.md.
417 UNSPEC_FMINNM ; Used in aarch64-simd.md.
7a08d813
TC		 418 UNSPEC_SDOT ; Used in aarch64-simd.md.
419 UNSPEC_UDOT ; Used in aarch64-simd.md.
27086ea3
MC		 420 UNSPEC_SM3SS1 ; Used in aarch64-simd.md.
421 UNSPEC_SM3TT1A ; Used in aarch64-simd.md.
422 UNSPEC_SM3TT1B ; Used in aarch64-simd.md.
423 UNSPEC_SM3TT2A ; Used in aarch64-simd.md.
424 UNSPEC_SM3TT2B ; Used in aarch64-simd.md.
425 UNSPEC_SM3PARTW1 ; Used in aarch64-simd.md.
426 UNSPEC_SM3PARTW2 ; Used in aarch64-simd.md.
427 UNSPEC_SM4E ; Used in aarch64-simd.md.
428 UNSPEC_SM4EKEY ; Used in aarch64-simd.md.
429 UNSPEC_SHA512H ; Used in aarch64-simd.md.
430 UNSPEC_SHA512H2 ; Used in aarch64-simd.md.
431 UNSPEC_SHA512SU0 ; Used in aarch64-simd.md.
432 UNSPEC_SHA512SU1 ; Used in aarch64-simd.md.
433 UNSPEC_FMLAL ; Used in aarch64-simd.md.
434 UNSPEC_FMLSL ; Used in aarch64-simd.md.
435 UNSPEC_FMLAL2 ; Used in aarch64-simd.md.
436 UNSPEC_FMLSL2 ; Used in aarch64-simd.md.
43cacb12 437 UNSPEC_SEL ; Used in aarch64-sve.md.
898f07b0
RS		 438 UNSPEC_ANDV ; Used in aarch64-sve.md.
439 UNSPEC_IORV ; Used in aarch64-sve.md.
440 UNSPEC_XORV ; Used in aarch64-sve.md.
43cacb12
RS		 441 UNSPEC_ANDF ; Used in aarch64-sve.md.
442 UNSPEC_IORF ; Used in aarch64-sve.md.
443 UNSPEC_XORF ; Used in aarch64-sve.md.
11e9443f
RS		 444 UNSPEC_SMUL_HIGHPART ; Used in aarch64-sve.md.
445 UNSPEC_UMUL_HIGHPART ; Used in aarch64-sve.md.
0972596e
RS		 446 UNSPEC_COND_ADD ; Used in aarch64-sve.md.
447 UNSPEC_COND_SUB ; Used in aarch64-sve.md.
448 UNSPEC_COND_SMAX ; Used in aarch64-sve.md.
449 UNSPEC_COND_UMAX ; Used in aarch64-sve.md.
450 UNSPEC_COND_SMIN ; Used in aarch64-sve.md.
451 UNSPEC_COND_UMIN ; Used in aarch64-sve.md.
452 UNSPEC_COND_AND ; Used in aarch64-sve.md.
453 UNSPEC_COND_ORR ; Used in aarch64-sve.md.
454 UNSPEC_COND_EOR ; Used in aarch64-sve.md.
43cacb12
RS		 455 UNSPEC_COND_LT ; Used in aarch64-sve.md.
456 UNSPEC_COND_LE ; Used in aarch64-sve.md.
457 UNSPEC_COND_EQ ; Used in aarch64-sve.md.
458 UNSPEC_COND_NE ; Used in aarch64-sve.md.
459 UNSPEC_COND_GE ; Used in aarch64-sve.md.
460 UNSPEC_COND_GT ; Used in aarch64-sve.md.
43cacb12 461 UNSPEC_LASTB ; Used in aarch64-sve.md.
43e9d192
IB		 462])
463
d81cb613
MW		 464;; ------------------------------------------------------------------
465;; Unspec enumerations for Atomics. They are here so that they can be
466;; used in the int_iterators for atomic operations.
467;; ------------------------------------------------------------------
468
469(define_c_enum "unspecv"
470 [
471 UNSPECV_LX ; Represent a load-exclusive.
472 UNSPECV_SX ; Represent a store-exclusive.
473 UNSPECV_LDA ; Represent an atomic load or load-acquire.
474 UNSPECV_STL ; Represent an atomic store or store-release.
475 UNSPECV_ATOMIC_CMPSW ; Represent an atomic compare swap.
476 UNSPECV_ATOMIC_EXCHG ; Represent an atomic exchange.
477 UNSPECV_ATOMIC_CAS ; Represent an atomic CAS.
478 UNSPECV_ATOMIC_SWP ; Represent an atomic SWP.
479 UNSPECV_ATOMIC_OP ; Represent an atomic operation.
480 UNSPECV_ATOMIC_LDOP ; Represent an atomic load-operation
481 UNSPECV_ATOMIC_LDOP_OR ; Represent an atomic load-or
482 UNSPECV_ATOMIC_LDOP_BIC ; Represent an atomic load-bic
483 UNSPECV_ATOMIC_LDOP_XOR ; Represent an atomic load-xor
484 UNSPECV_ATOMIC_LDOP_PLUS ; Represent an atomic load-add
485])
486
43e9d192
IB		 487;; -------------------------------------------------------------------
488;; Mode attributes
489;; -------------------------------------------------------------------
490
491;; In GPI templates, a string like "%<w>0" will expand to "%w0" in the
492;; 32-bit version and "%x0" in the 64-bit version.
493(define_mode_attr w [(QI "w") (HI "w") (SI "w") (DI "x") (SF "s") (DF "d")])
494
db46a2e6
JG		 495;; The size of access, in bytes.
496(define_mode_attr ldst_sz [(SI "4") (DI "8")])
497;; Likewise for load/store pair.
498(define_mode_attr ldpstp_sz [(SI "8") (DI "16")])
499
0d35c5c2 500;; For inequal width int to float conversion
d7f33f07
JW		 501(define_mode_attr w1 [(HF "w") (SF "w") (DF "x")])
502(define_mode_attr w2 [(HF "x") (SF "x") (DF "w")])
0d35c5c2 503
22be0d08
MC		 504;; For width of fp registers in fcvt instruction
505(define_mode_attr fpw [(DI "s") (SI "d")])
506
2b8568fe
KT		 507(define_mode_attr short_mask [(HI "65535") (QI "255")])
508
051d0e2f
SN		 509;; For constraints used in scalar immediate vector moves
510(define_mode_attr hq [(HI "h") (QI "q")])
511
ef22810a
RH		 512;; For doubling width of an integer mode
513(define_mode_attr DWI [(QI "HI") (HI "SI") (SI "DI") (DI "TI")])
514
22be0d08
MC		 515(define_mode_attr fcvt_change_mode [(SI "df") (DI "sf")])
516
517(define_mode_attr FCVT_CHANGE_MODE [(SI "DF") (DI "SF")])
518
43e9d192
IB		 519;; For scalar usage of vector/FP registers
520(define_mode_attr v [(QI "b") (HI "h") (SI "s") (DI "d")
d7f33f07 521 (HF "h") (SF "s") (DF "d")
43e9d192
IB		 522 (V8QI "") (V16QI "")
523 (V4HI "") (V8HI "")
524 (V2SI "") (V4SI "")
525 (V2DI "") (V2SF "")
daef0a8c
JW		 526 (V4SF "") (V4HF "")
527 (V8HF "") (V2DF "")])
43e9d192
IB		 528
529;; For scalar usage of vector/FP registers, narrowing
530(define_mode_attr vn2 [(QI "") (HI "b") (SI "h") (DI "s")
531 (V8QI "") (V16QI "")
532 (V4HI "") (V8HI "")
533 (V2SI "") (V4SI "")
534 (V2DI "") (V2SF "")
535 (V4SF "") (V2DF "")])
536
537;; For scalar usage of vector/FP registers, widening
538(define_mode_attr vw2 [(DI "") (QI "h") (HI "s") (SI "d")
539 (V8QI "") (V16QI "")
540 (V4HI "") (V8HI "")
541 (V2SI "") (V4SI "")
542 (V2DI "") (V2SF "")
543 (V4SF "") (V2DF "")])
544
89fdc743
IB		 545;; Register Type Name and Vector Arrangement Specifier for when
546;; we are doing scalar for DI and SIMD for SI (ignoring all but
547;; lane 0).
548(define_mode_attr rtn [(DI "d") (SI "")])
549(define_mode_attr vas [(DI "") (SI ".2s")])
550
7ac29c0f
RS		 551;; Map a vector to the number of units in it, if the size of the mode
552;; is constant.
553(define_mode_attr nunits [(V8QI "8") (V16QI "16")
554 (V4HI "4") (V8HI "8")
555 (V2SI "2") (V4SI "4")
556 (V2DI "2")
557 (V4HF "4") (V8HF "8")
558 (V2SF "2") (V4SF "4")
559 (V1DF "1") (V2DF "2")
560 (DI "1") (DF "1")])
561
b187677b
RS		 562;; Map a mode to the number of bits in it, if the size of the mode
563;; is constant.
564(define_mode_attr bitsize [(V8QI "64") (V16QI "128")
565 (V4HI "64") (V8HI "128")
566 (V2SI "64") (V4SI "128")
567 (V2DI "128")])
568
22be0d08
MC		 569;; Map a floating point or integer mode to the appropriate register name prefix
570(define_mode_attr s [(HF "h") (SF "s") (DF "d") (SI "s") (DI "d")])
43e9d192
IB		 571
572;; Give the length suffix letter for a sign- or zero-extension.
573(define_mode_attr size [(QI "b") (HI "h") (SI "w")])
574
575;; Give the number of bits in the mode
576(define_mode_attr sizen [(QI "8") (HI "16") (SI "32") (DI "64")])
577
578;; Give the ordinal of the MSB in the mode
579(define_mode_attr sizem1 [(QI "#7") (HI "#15") (SI "#31") (DI "#63")])
580
581;; Attribute to describe constants acceptable in logical operations
582(define_mode_attr lconst [(SI "K") (DI "L")])
583
43fd192f
MC		 584;; Attribute to describe constants acceptable in logical and operations
585(define_mode_attr lconst2 [(SI "UsO") (DI "UsP")])
586
43e9d192
IB		 587;; Map a mode to a specific constraint character.
588(define_mode_attr cmode [(QI "q") (HI "h") (SI "s") (DI "d")])
589
0603375c
KT		 590;; Map modes to Usg and Usj constraints for SISD right shifts
591(define_mode_attr cmode_simd [(SI "g") (DI "j")])
592
43e9d192
IB		 593(define_mode_attr Vtype [(V8QI "8b") (V16QI "16b")
594 (V4HI "4h") (V8HI "8h")
595 (V2SI "2s") (V4SI "4s")
596 (DI "1d") (DF "1d")
597 (V2DI "2d") (V2SF "2s")
7c369485
AL		 598 (V4SF "4s") (V2DF "2d")
599 (V4HF "4h") (V8HF "8h")])
43e9d192 600
c7f28cd5
KT		 601(define_mode_attr Vrevsuff [(V4HI "16") (V8HI "16") (V2SI "32")
602 (V4SI "32") (V2DI "64")])
603
43e9d192
IB		 604(define_mode_attr Vmtype [(V8QI ".8b") (V16QI ".16b")
605 (V4HI ".4h") (V8HI ".8h")
606 (V2SI ".2s") (V4SI ".4s")
71a11456
AL		 607 (V2DI ".2d") (V4HF ".4h")
608 (V8HF ".8h") (V2SF ".2s")
43e9d192
IB		 609 (V4SF ".4s") (V2DF ".2d")
610 (DI "") (SI "")
611 (HI "") (QI "")
d7f33f07
JW		 612 (TI "") (HF "")
613 (SF "") (DF "")])
43e9d192
IB		 614
615;; Register suffix narrowed modes for VQN.
616(define_mode_attr Vmntype [(V8HI ".8b") (V4SI ".4h")
617 (V2DI ".2s")
618 (DI "") (SI "")
619 (HI "")])
620
621;; Mode-to-individual element type mapping.
43cacb12
RS		 622(define_mode_attr Vetype [(V8QI "b") (V16QI "b") (VNx16QI "b") (VNx16BI "b")
623 (V4HI "h") (V8HI "h") (VNx8HI "h") (VNx8BI "h")
624 (V2SI "s") (V4SI "s") (VNx4SI "s") (VNx4BI "s")
625 (V2DI "d") (VNx2DI "d") (VNx2BI "d")
626 (V4HF "h") (V8HF "h") (VNx8HF "h")
627 (V2SF "s") (V4SF "s") (VNx4SF "s")
628 (V2DF "d") (VNx2DF "d")
d7f33f07 629 (HF "h")
0f686aa9 630 (SF "s") (DF "d")
43e9d192
IB		 631 (QI "b") (HI "h")
632 (SI "s") (DI "d")])
633
43cacb12
RS		 634;; Equivalent of "size" for a vector element.
635(define_mode_attr Vesize [(VNx16QI "b")
9f4cbab8
RS		 636 (VNx8HI "h") (VNx8HF "h")
637 (VNx4SI "w") (VNx4SF "w")
638 (VNx2DI "d") (VNx2DF "d")
639 (VNx32QI "b") (VNx48QI "b") (VNx64QI "b")
640 (VNx16HI "h") (VNx24HI "h") (VNx32HI "h")
641 (VNx16HF "h") (VNx24HF "h") (VNx32HF "h")
642 (VNx8SI "w") (VNx12SI "w") (VNx16SI "w")
643 (VNx8SF "w") (VNx12SF "w") (VNx16SF "w")
644 (VNx4DI "d") (VNx6DI "d") (VNx8DI "d")
645 (VNx4DF "d") (VNx6DF "d") (VNx8DF "d")])
43cacb12 646
daef0a8c
JW		 647;; Vetype is used everywhere in scheduling type and assembly output,
648;; sometimes they are not the same, for example HF modes on some
649;; instructions. stype is defined to represent scheduling type
650;; more accurately.
651(define_mode_attr stype [(V8QI "b") (V16QI "b") (V4HI "s") (V8HI "s")
652 (V2SI "s") (V4SI "s") (V2DI "d") (V4HF "s")
653 (V8HF "s") (V2SF "s") (V4SF "s") (V2DF "d")
654 (HF "s") (SF "s") (DF "d") (QI "b") (HI "s")
655 (SI "s") (DI "d")])
656
43e9d192
IB		 657;; Mode-to-bitwise operation type mapping.
658(define_mode_attr Vbtype [(V8QI "8b") (V16QI "16b")
659 (V4HI "8b") (V8HI "16b")
660 (V2SI "8b") (V4SI "16b")
7c369485
AL		 661 (V2DI "16b") (V4HF "8b")
662 (V8HF "16b") (V2SF "8b")
46e778c4 663 (V4SF "16b") (V2DF "16b")
fe82d1f2
AL		 664 (DI "8b") (DF "8b")
665 (SI "8b")])
43e9d192
IB		 666
667;; Define element mode for each vector mode.
43cacb12
RS		 668(define_mode_attr VEL [(V8QI "QI") (V16QI "QI") (VNx16QI "QI")
669 (V4HI "HI") (V8HI "HI") (VNx8HI "HI")
670 (V2SI "SI") (V4SI "SI") (VNx4SI "SI")
671 (DI "DI") (V2DI "DI") (VNx2DI "DI")
672 (V4HF "HF") (V8HF "HF") (VNx8HF "HF")
673 (V2SF "SF") (V4SF "SF") (VNx4SF "SF")
674 (DF "DF") (V2DF "DF") (VNx2DF "DF")
675 (SI "SI") (HI "HI")
43e9d192
IB		 676 (QI "QI")])
677
ff03930a 678;; Define element mode for each vector mode (lower case).
43cacb12
RS		 679(define_mode_attr Vel [(V8QI "qi") (V16QI "qi") (VNx16QI "qi")
680 (V4HI "hi") (V8HI "hi") (VNx8HI "hi")
681 (V2SI "si") (V4SI "si") (VNx4SI "si")
682 (DI "di") (V2DI "di") (VNx2DI "di")
683 (V4HF "hf") (V8HF "hf") (VNx8HF "hf")
684 (V2SF "sf") (V4SF "sf") (VNx4SF "sf")
685 (V2DF "df") (DF "df") (VNx2DF "df")
ff03930a
JJ		 686 (SI "si") (HI "hi")
687 (QI "qi")])
688
43cacb12
RS		 689;; Element mode with floating-point values replaced by like-sized integers.
690(define_mode_attr VEL_INT [(VNx16QI "QI")
691 (VNx8HI "HI") (VNx8HF "HI")
692 (VNx4SI "SI") (VNx4SF "SI")
693 (VNx2DI "DI") (VNx2DF "DI")])
694
695;; Gives the mode of the 128-bit lowpart of an SVE vector.
696(define_mode_attr V128 [(VNx16QI "V16QI")
697 (VNx8HI "V8HI") (VNx8HF "V8HF")
698 (VNx4SI "V4SI") (VNx4SF "V4SF")
699 (VNx2DI "V2DI") (VNx2DF "V2DF")])
700
701;; ...and again in lower case.
702(define_mode_attr v128 [(VNx16QI "v16qi")
703 (VNx8HI "v8hi") (VNx8HF "v8hf")
704 (VNx4SI "v4si") (VNx4SF "v4sf")
705 (VNx2DI "v2di") (VNx2DF "v2df")])
706
278821f2
KT		 707;; 64-bit container modes the inner or scalar source mode.
708(define_mode_attr VCOND [(HI "V4HI") (SI "V2SI")
709 (V4HI "V4HI") (V8HI "V4HI")
b7d7d917
TB		 710 (V2SI "V2SI") (V4SI "V2SI")
711 (DI "DI") (V2DI "DI")
712 (V2SF "V2SF") (V4SF "V2SF")
713 (V2DF "DF")])
714
278821f2 715;; 128-bit container modes the inner or scalar source mode.
b7d7d917
TB		 716(define_mode_attr VCONQ [(V8QI "V16QI") (V16QI "V16QI")
717 (V4HI "V8HI") (V8HI "V8HI")
718 (V2SI "V4SI") (V4SI "V4SI")
719 (DI "V2DI") (V2DI "V2DI")
71a11456 720 (V4HF "V8HF") (V8HF "V8HF")
b7d7d917
TB		 721 (V2SF "V2SF") (V4SF "V4SF")
722 (V2DF "V2DF") (SI "V4SI")
723 (HI "V8HI") (QI "V16QI")])
724
43e9d192
IB		 725;; Half modes of all vector modes.
726(define_mode_attr VHALF [(V8QI "V4QI") (V16QI "V8QI")
727 (V4HI "V2HI") (V8HI "V4HI")
728 (V2SI "SI") (V4SI "V2SI")
729 (V2DI "DI") (V2SF "SF")
71a11456
AL		 730 (V4SF "V2SF") (V4HF "V2HF")
731 (V8HF "V4HF") (V2DF "DF")])
43e9d192 732
b1b49824
MC		 733;; Half modes of all vector modes, in lower-case.
734(define_mode_attr Vhalf [(V8QI "v4qi") (V16QI "v8qi")
735 (V4HI "v2hi") (V8HI "v4hi")
736 (V2SI "si") (V4SI "v2si")
737 (V2DI "di") (V2SF "sf")
738 (V4SF "v2sf") (V2DF "df")])
739
43e9d192
IB		 740;; Double modes of vector modes.
741(define_mode_attr VDBL [(V8QI "V16QI") (V4HI "V8HI")
71a11456 742 (V4HF "V8HF")
43e9d192
IB		 743 (V2SI "V4SI") (V2SF "V4SF")
744 (SI "V2SI") (DI "V2DI")
745 (DF "V2DF")])
746
922f9c25
AL		 747;; Register suffix for double-length mode.
748(define_mode_attr Vdtype [(V4HF "8h") (V2SF "4s")])
749
43e9d192
IB		 750;; Double modes of vector modes (lower case).
751(define_mode_attr Vdbl [(V8QI "v16qi") (V4HI "v8hi")
7c369485 752 (V4HF "v8hf")
43e9d192 753 (V2SI "v4si") (V2SF "v4sf")
8b033a8a
SN		 754 (SI "v2si") (DI "v2di")
755 (DF "v2df")])
43e9d192 756
b1b49824
MC		 757;; Modes with double-width elements.
758(define_mode_attr VDBLW [(V8QI "V4HI") (V16QI "V8HI")
759 (V4HI "V2SI") (V8HI "V4SI")
760 (V2SI "DI") (V4SI "V2DI")])
761
43e9d192
IB		 762;; Narrowed modes for VDN.
763(define_mode_attr VNARROWD [(V4HI "V8QI") (V2SI "V4HI")
764 (DI "V2SI")])
765
766;; Narrowed double-modes for VQN (Used for XTN).
767(define_mode_attr VNARROWQ [(V8HI "V8QI") (V4SI "V4HI")
768 (V2DI "V2SI")
769 (DI "SI") (SI "HI")
770 (HI "QI")])
771
772;; Narrowed quad-modes for VQN (Used for XTN2).
773(define_mode_attr VNARROWQ2 [(V8HI "V16QI") (V4SI "V8HI")
774 (V2DI "V4SI")])
775
776;; Register suffix narrowed modes for VQN.
777(define_mode_attr Vntype [(V8HI "8b") (V4SI "4h")
778 (V2DI "2s")])
779
780;; Register suffix narrowed modes for VQN.
781(define_mode_attr V2ntype [(V8HI "16b") (V4SI "8h")
782 (V2DI "4s")])
783
784;; Widened modes of vector modes.
43cacb12
RS		 785(define_mode_attr VWIDE [(V8QI "V8HI") (V4HI "V4SI")
786 (V2SI "V2DI") (V16QI "V8HI")
787 (V8HI "V4SI") (V4SI "V2DI")
788 (HI "SI") (SI "DI")
789 (V8HF "V4SF") (V4SF "V2DF")
790 (V4HF "V4SF") (V2SF "V2DF")
791 (VNx8HF "VNx4SF") (VNx4SF "VNx2DF")
792 (VNx16QI "VNx8HI") (VNx8HI "VNx4SI")
793 (VNx4SI "VNx2DI")
794 (VNx16BI "VNx8BI") (VNx8BI "VNx4BI")
795 (VNx4BI "VNx2BI")])
796
797;; Predicate mode associated with VWIDE.
798(define_mode_attr VWIDE_PRED [(VNx8HF "VNx4BI") (VNx4SF "VNx2BI")])
43e9d192 799
03873eb9 800;; Widened modes of vector modes, lowercase
43cacb12
RS		 801(define_mode_attr Vwide [(V2SF "v2df") (V4HF "v4sf")
802 (VNx16QI "vnx8hi") (VNx8HI "vnx4si")
803 (VNx4SI "vnx2di")
804 (VNx8HF "vnx4sf") (VNx4SF "vnx2df")
805 (VNx16BI "vnx8bi") (VNx8BI "vnx4bi")
806 (VNx4BI "vnx2bi")])
03873eb9
AL		 807
808;; Widened mode register suffixes for VD_BHSI/VQW/VQ_HSF.
43e9d192
IB		 809(define_mode_attr Vwtype [(V8QI "8h") (V4HI "4s")
810 (V2SI "2d") (V16QI "8h")
03873eb9
AL		 811 (V8HI "4s") (V4SI "2d")
812 (V8HF "4s") (V4SF "2d")])
43e9d192 813
43cacb12
RS		 814;; SVE vector after widening
815(define_mode_attr Vewtype [(VNx16QI "h")
816 (VNx8HI "s") (VNx8HF "s")
817 (VNx4SI "d") (VNx4SF "d")])
818
43e9d192
IB		 819;; Widened mode register suffixes for VDW/VQW.
820(define_mode_attr Vmwtype [(V8QI ".8h") (V4HI ".4s")
821 (V2SI ".2d") (V16QI ".8h")
822 (V8HI ".4s") (V4SI ".2d")
922f9c25 823 (V4HF ".4s") (V2SF ".2d")
43e9d192
IB		 824 (SI "") (HI "")])
825
03873eb9 826;; Lower part register suffixes for VQW/VQ_HSF.
43e9d192 827(define_mode_attr Vhalftype [(V16QI "8b") (V8HI "4h")
03873eb9
AL		 828 (V4SI "2s") (V8HF "4h")
829 (V4SF "2s")])
43e9d192
IB		 830
831;; Define corresponding core/FP element mode for each vector mode.
43cacb12
RS		 832(define_mode_attr vw [(V8QI "w") (V16QI "w") (VNx16QI "w")
833 (V4HI "w") (V8HI "w") (VNx8HI "w")
834 (V2SI "w") (V4SI "w") (VNx4SI "w")
835 (DI "x") (V2DI "x") (VNx2DI "x")
836 (VNx8HF "h")
837 (V2SF "s") (V4SF "s") (VNx4SF "s")
838 (V2DF "d") (VNx2DF "d")])
43e9d192 839
66adb8eb
JG		 840;; Corresponding core element mode for each vector mode. This is a
841;; variation on <vw> mapping FP modes to GP regs.
43cacb12
RS		 842(define_mode_attr vwcore [(V8QI "w") (V16QI "w") (VNx16QI "w")
843 (V4HI "w") (V8HI "w") (VNx8HI "w")
844 (V2SI "w") (V4SI "w") (VNx4SI "w")
845 (DI "x") (V2DI "x") (VNx2DI "x")
846 (V4HF "w") (V8HF "w") (VNx8HF "w")
847 (V2SF "w") (V4SF "w") (VNx4SF "w")
848 (V2DF "x") (VNx2DF "x")])
66adb8eb 849
43e9d192
IB		 850;; Double vector types for ALLX.
851(define_mode_attr Vallxd [(QI "8b") (HI "4h") (SI "2s")])
852
5f565314
RS		 853;; Mode with floating-point values replaced by like-sized integers.
854(define_mode_attr V_INT_EQUIV [(V8QI "V8QI") (V16QI "V16QI")
855 (V4HI "V4HI") (V8HI "V8HI")
856 (V2SI "V2SI") (V4SI "V4SI")
857 (DI "DI") (V2DI "V2DI")
858 (V4HF "V4HI") (V8HF "V8HI")
859 (V2SF "V2SI") (V4SF "V4SI")
43cacb12
RS		 860 (DF "DI") (V2DF "V2DI")
861 (SF "SI") (HF "HI")
862 (VNx16QI "VNx16QI")
863 (VNx8HI "VNx8HI") (VNx8HF "VNx8HI")
864 (VNx4SI "VNx4SI") (VNx4SF "VNx4SI")
865 (VNx2DI "VNx2DI") (VNx2DF "VNx2DI")
866])
5f565314
RS		 867
868;; Lower case mode with floating-point values replaced by like-sized integers.
869(define_mode_attr v_int_equiv [(V8QI "v8qi") (V16QI "v16qi")
870 (V4HI "v4hi") (V8HI "v8hi")
871 (V2SI "v2si") (V4SI "v4si")
872 (DI "di") (V2DI "v2di")
873 (V4HF "v4hi") (V8HF "v8hi")
874 (V2SF "v2si") (V4SF "v4si")
43cacb12
RS		 875 (DF "di") (V2DF "v2di")
876 (SF "si")
877 (VNx16QI "vnx16qi")
878 (VNx8HI "vnx8hi") (VNx8HF "vnx8hi")
879 (VNx4SI "vnx4si") (VNx4SF "vnx4si")
880 (VNx2DI "vnx2di") (VNx2DF "vnx2di")
881])
882
883;; Floating-point equivalent of selected modes.
884(define_mode_attr V_FP_EQUIV [(VNx4SI "VNx4SF") (VNx4SF "VNx4SF")
885 (VNx2DI "VNx2DF") (VNx2DF "VNx2DF")])
886(define_mode_attr v_fp_equiv [(VNx4SI "vnx4sf") (VNx4SF "vnx4sf")
887 (VNx2DI "vnx2df") (VNx2DF "vnx2df")])
70c67693 888
6c553b76
BC		 889;; Mode for vector conditional operations where the comparison has
890;; different type from the lhs.
891(define_mode_attr V_cmp_mixed [(V2SI "V2SF") (V4SI "V4SF")
892 (V2DI "V2DF") (V2SF "V2SI")
893 (V4SF "V4SI") (V2DF "V2DI")])
894
895(define_mode_attr v_cmp_mixed [(V2SI "v2sf") (V4SI "v4sf")
896 (V2DI "v2df") (V2SF "v2si")
897 (V4SF "v4si") (V2DF "v2di")])
898
cb23a30c
JG		 899;; Lower case element modes (as used in shift immediate patterns).
900(define_mode_attr ve_mode [(V8QI "qi") (V16QI "qi")
901 (V4HI "hi") (V8HI "hi")
902 (V2SI "si") (V4SI "si")
903 (DI "di") (V2DI "di")
904 (QI "qi") (HI "hi")
905 (SI "si")])
906
43e9d192
IB		 907;; Vm for lane instructions is restricted to FP_LO_REGS.
908(define_mode_attr vwx [(V4HI "x") (V8HI "x") (HI "x")
909 (V2SI "w") (V4SI "w") (SI "w")])
910
911(define_mode_attr Vendreg [(OI "T") (CI "U") (XI "V")])
912
97755701
AL		 913;; This is both the number of Q-Registers needed to hold the corresponding
914;; opaque large integer mode, and the number of elements touched by the
915;; ld..._lane and st..._lane operations.
43e9d192
IB		 916(define_mode_attr nregs [(OI "2") (CI "3") (XI "4")])
917
0462169c
SN		 918;; Mode for atomic operation suffixes
919(define_mode_attr atomic_sfx
920 [(QI "b") (HI "h") (SI "") (DI "")])
921
3f598afe 922(define_mode_attr fcvt_target [(V2DF "v2di") (V4SF "v4si") (V2SF "v2si")
2644d4d9 923 (V2DI "v2df") (V4SI "v4sf") (V2SI "v2sf")
daef0a8c
JW		 924 (SF "si") (DF "di") (SI "sf") (DI "df")
925 (V4HF "v4hi") (V8HF "v8hi") (V4HI "v4hf")
68ad28c3 926 (V8HI "v8hf") (HF "hi") (HI "hf")])
3f598afe 927(define_mode_attr FCVT_TARGET [(V2DF "V2DI") (V4SF "V4SI") (V2SF "V2SI")
2644d4d9 928 (V2DI "V2DF") (V4SI "V4SF") (V2SI "V2SF")
daef0a8c
JW		 929 (SF "SI") (DF "DI") (SI "SF") (DI "DF")
930 (V4HF "V4HI") (V8HF "V8HI") (V4HI "V4HF")
68ad28c3 931 (V8HI "V8HF") (HF "HI") (HI "HF")])
3f598afe 932
0d35c5c2
VP		 933
934;; for the inequal width integer to fp conversions
d7f33f07
JW		 935(define_mode_attr fcvt_iesize [(HF "di") (SF "di") (DF "si")])
936(define_mode_attr FCVT_IESIZE [(HF "DI") (SF "DI") (DF "SI")])
42fc9a7f 937
91bd4114
JG		 938(define_mode_attr VSWAP_WIDTH [(V8QI "V16QI") (V16QI "V8QI")
939 (V4HI "V8HI") (V8HI "V4HI")
940 (V2SI "V4SI") (V4SI "V2SI")
941 (DI "V2DI") (V2DI "DI")
942 (V2SF "V4SF") (V4SF "V2SF")
862abc04 943 (V4HF "V8HF") (V8HF "V4HF")
91bd4114
JG		 944 (DF "V2DF") (V2DF "DF")])
945
946(define_mode_attr vswap_width_name [(V8QI "to_128") (V16QI "to_64")
947 (V4HI "to_128") (V8HI "to_64")
948 (V2SI "to_128") (V4SI "to_64")
949 (DI "to_128") (V2DI "to_64")
862abc04 950 (V4HF "to_128") (V8HF "to_64")
91bd4114
JG		 951 (V2SF "to_128") (V4SF "to_64")
952 (DF "to_128") (V2DF "to_64")])
953
779aea46 954;; For certain vector-by-element multiplication instructions we must
6d06971d 955;; constrain the 16-bit cases to use only V0-V15. This is covered by
779aea46
JG		 956;; the 'x' constraint. All other modes may use the 'w' constraint.
957(define_mode_attr h_con [(V2SI "w") (V4SI "w")
958 (V4HI "x") (V8HI "x")
6d06971d 959 (V4HF "x") (V8HF "x")
779aea46
JG		 960 (V2SF "w") (V4SF "w")
961 (V2DF "w") (DF "w")])
962
963;; Defined to 'f' for types whose element type is a float type.
964(define_mode_attr f [(V8QI "") (V16QI "")
965 (V4HI "") (V8HI "")
966 (V2SI "") (V4SI "")
967 (DI "") (V2DI "")
ab2e8f01 968 (V4HF "f") (V8HF "f")
779aea46
JG		 969 (V2SF "f") (V4SF "f")
970 (V2DF "f") (DF "f")])
971
0f686aa9
JG		 972;; Defined to '_fp' for types whose element type is a float type.
973(define_mode_attr fp [(V8QI "") (V16QI "")
974 (V4HI "") (V8HI "")
975 (V2SI "") (V4SI "")
976 (DI "") (V2DI "")
ab2e8f01 977 (V4HF "_fp") (V8HF "_fp")
0f686aa9
JG		 978 (V2SF "_fp") (V4SF "_fp")
979 (V2DF "_fp") (DF "_fp")
980 (SF "_fp")])
981
a9e66678
JG		 982;; Defined to '_q' for 128-bit types.
983(define_mode_attr q [(V8QI "") (V16QI "_q")
0f686aa9
JG		 984 (V4HI "") (V8HI "_q")
985 (V2SI "") (V4SI "_q")
986 (DI "") (V2DI "_q")
71a11456 987 (V4HF "") (V8HF "_q")
0f686aa9
JG		 988 (V2SF "") (V4SF "_q")
989 (V2DF "_q")
d7f33f07 990 (QI "") (HI "") (SI "") (DI "") (HF "") (SF "") (DF "")])
a9e66678 991
92835317
TB		 992(define_mode_attr vp [(V8QI "v") (V16QI "v")
993 (V4HI "v") (V8HI "v")
994 (V2SI "p") (V4SI "v")
703bbcdf
JW		 995 (V2DI "p") (V2DF "p")
996 (V2SF "p") (V4SF "v")
997 (V4HF "v") (V8HF "v")])
92835317 998
5e32e83b
JW		 999(define_mode_attr vsi2qi [(V2SI "v8qi") (V4SI "v16qi")])
1000(define_mode_attr VSI2QI [(V2SI "V8QI") (V4SI "V16QI")])
1001
7a08d813
TC		 1002
1003;; Register suffix for DOTPROD input types from the return type.
1004(define_mode_attr Vdottype [(V2SI "8b") (V4SI "16b")])
1005
cd78b3dd 1006;; Sum of lengths of instructions needed to move vector registers of a mode.
668046d1
DS		 1007(define_mode_attr insn_count [(OI "8") (CI "12") (XI "16")])
1008
1b1e81f8
JW		 1009;; -fpic small model GOT reloc modifers: gotpage_lo15/lo14 for ILP64/32.
1010;; No need of iterator for -fPIC as it use got_lo12 for both modes.
1011(define_mode_attr got_modifier [(SI "gotpage_lo14") (DI "gotpage_lo15")])
1012
27086ea3
MC		 1013;; Width of 2nd and 3rd arguments to fp16 vector multiply add/sub
1014(define_mode_attr VFMLA_W [(V2SF "V4HF") (V4SF "V8HF")])
1015
1016(define_mode_attr VFMLA_SEL_W [(V2SF "V2HF") (V4SF "V4HF")])
1017
1018(define_mode_attr f16quad [(V2SF "") (V4SF "q")])
1019
1020(define_code_attr f16mac [(plus "a") (minus "s")])
1021
9f4cbab8
RS		 1022;; The number of subvectors in an SVE_STRUCT.
1023(define_mode_attr vector_count [(VNx32QI "2") (VNx16HI "2")
1024 (VNx8SI "2") (VNx4DI "2")
1025 (VNx16HF "2") (VNx8SF "2") (VNx4DF "2")
1026 (VNx48QI "3") (VNx24HI "3")
1027 (VNx12SI "3") (VNx6DI "3")
1028 (VNx24HF "3") (VNx12SF "3") (VNx6DF "3")
1029 (VNx64QI "4") (VNx32HI "4")
1030 (VNx16SI "4") (VNx8DI "4")
1031 (VNx32HF "4") (VNx16SF "4") (VNx8DF "4")])
1032
1033;; The number of instruction bytes needed for an SVE_STRUCT move. This is
1034;; equal to vector_count * 4.
1035(define_mode_attr insn_length [(VNx32QI "8") (VNx16HI "8")
1036 (VNx8SI "8") (VNx4DI "8")
1037 (VNx16HF "8") (VNx8SF "8") (VNx4DF "8")
1038 (VNx48QI "12") (VNx24HI "12")
1039 (VNx12SI "12") (VNx6DI "12")
1040 (VNx24HF "12") (VNx12SF "12") (VNx6DF "12")
1041 (VNx64QI "16") (VNx32HI "16")
1042 (VNx16SI "16") (VNx8DI "16")
1043 (VNx32HF "16") (VNx16SF "16") (VNx8DF "16")])
1044
1045;; The type of a subvector in an SVE_STRUCT.
1046(define_mode_attr VSINGLE [(VNx32QI "VNx16QI")
1047 (VNx16HI "VNx8HI") (VNx16HF "VNx8HF")
1048 (VNx8SI "VNx4SI") (VNx8SF "VNx4SF")
1049 (VNx4DI "VNx2DI") (VNx4DF "VNx2DF")
1050 (VNx48QI "VNx16QI")
1051 (VNx24HI "VNx8HI") (VNx24HF "VNx8HF")
1052 (VNx12SI "VNx4SI") (VNx12SF "VNx4SF")
1053 (VNx6DI "VNx2DI") (VNx6DF "VNx2DF")
1054 (VNx64QI "VNx16QI")
1055 (VNx32HI "VNx8HI") (VNx32HF "VNx8HF")
1056 (VNx16SI "VNx4SI") (VNx16SF "VNx4SF")
1057 (VNx8DI "VNx2DI") (VNx8DF "VNx2DF")])
1058
1059;; ...and again in lower case.
1060(define_mode_attr vsingle [(VNx32QI "vnx16qi")
1061 (VNx16HI "vnx8hi") (VNx16HF "vnx8hf")
1062 (VNx8SI "vnx4si") (VNx8SF "vnx4sf")
1063 (VNx4DI "vnx2di") (VNx4DF "vnx2df")
1064 (VNx48QI "vnx16qi")
1065 (VNx24HI "vnx8hi") (VNx24HF "vnx8hf")
1066 (VNx12SI "vnx4si") (VNx12SF "vnx4sf")
1067 (VNx6DI "vnx2di") (VNx6DF "vnx2df")
1068 (VNx64QI "vnx16qi")
1069 (VNx32HI "vnx8hi") (VNx32HF "vnx8hf")
1070 (VNx16SI "vnx4si") (VNx16SF "vnx4sf")
1071 (VNx8DI "vnx2di") (VNx8DF "vnx2df")])
1072
1073;; The predicate mode associated with an SVE data mode. For structure modes
1074;; this is equivalent to the <VPRED> of the subvector mode.
43cacb12
RS		 1075(define_mode_attr VPRED [(VNx16QI "VNx16BI")
1076 (VNx8HI "VNx8BI") (VNx8HF "VNx8BI")
1077 (VNx4SI "VNx4BI") (VNx4SF "VNx4BI")
9f4cbab8
RS		 1078 (VNx2DI "VNx2BI") (VNx2DF "VNx2BI")
1079 (VNx32QI "VNx16BI")
1080 (VNx16HI "VNx8BI") (VNx16HF "VNx8BI")
1081 (VNx8SI "VNx4BI") (VNx8SF "VNx4BI")
1082 (VNx4DI "VNx2BI") (VNx4DF "VNx2BI")
1083 (VNx48QI "VNx16BI")
1084 (VNx24HI "VNx8BI") (VNx24HF "VNx8BI")
1085 (VNx12SI "VNx4BI") (VNx12SF "VNx4BI")
1086 (VNx6DI "VNx2BI") (VNx6DF "VNx2BI")
1087 (VNx64QI "VNx16BI")
1088 (VNx32HI "VNx8BI") (VNx32HF "VNx8BI")
1089 (VNx16SI "VNx4BI") (VNx16SF "VNx4BI")
1090 (VNx8DI "VNx2BI") (VNx8DF "VNx2BI")])
43cacb12
RS		 1091
1092;; ...and again in lower case.
1093(define_mode_attr vpred [(VNx16QI "vnx16bi")
1094 (VNx8HI "vnx8bi") (VNx8HF "vnx8bi")
1095 (VNx4SI "vnx4bi") (VNx4SF "vnx4bi")
9f4cbab8
RS		 1096 (VNx2DI "vnx2bi") (VNx2DF "vnx2bi")
1097 (VNx32QI "vnx16bi")
1098 (VNx16HI "vnx8bi") (VNx16HF "vnx8bi")
1099 (VNx8SI "vnx4bi") (VNx8SF "vnx4bi")
1100 (VNx4DI "vnx2bi") (VNx4DF "vnx2bi")
1101 (VNx48QI "vnx16bi")
1102 (VNx24HI "vnx8bi") (VNx24HF "vnx8bi")
1103 (VNx12SI "vnx4bi") (VNx12SF "vnx4bi")
1104 (VNx6DI "vnx2bi") (VNx6DF "vnx2bi")
1105 (VNx64QI "vnx16bi")
1106 (VNx32HI "vnx8bi") (VNx32HF "vnx4bi")
1107 (VNx16SI "vnx4bi") (VNx16SF "vnx4bi")
1108 (VNx8DI "vnx2bi") (VNx8DF "vnx2bi")])
43cacb12 1109
43e9d192
IB		 1110;; -------------------------------------------------------------------
1111;; Code Iterators
1112;; -------------------------------------------------------------------
1113
1114;; This code iterator allows the various shifts supported on the core
1115(define_code_iterator SHIFT [ashift ashiftrt lshiftrt rotatert])
1116
1117;; This code iterator allows the shifts supported in arithmetic instructions
1118(define_code_iterator ASHIFT [ashift ashiftrt lshiftrt])
1119
1120;; Code iterator for logical operations
1121(define_code_iterator LOGICAL [and ior xor])
1122
43cacb12
RS		 1123;; LOGICAL without AND.
1124(define_code_iterator LOGICAL_OR [ior xor])
1125
84be6032
AL		 1126;; Code iterator for logical operations whose :nlogical works on SIMD registers.
1127(define_code_iterator NLOGICAL [and ior])
1128
3204ac98
KT		 1129;; Code iterator for unary negate and bitwise complement.
1130(define_code_iterator NEG_NOT [neg not])
1131
43e9d192
IB		 1132;; Code iterator for sign/zero extension
1133(define_code_iterator ANY_EXTEND [sign_extend zero_extend])
1134
1135;; All division operations (signed/unsigned)
1136(define_code_iterator ANY_DIV [div udiv])
1137
1138;; Code iterator for sign/zero extraction
1139(define_code_iterator ANY_EXTRACT [sign_extract zero_extract])
1140
1141;; Code iterator for equality comparisons
1142(define_code_iterator EQL [eq ne])
1143
1144;; Code iterator for less-than and greater/equal-to
1145(define_code_iterator LTGE [lt ge])
1146
1147;; Iterator for __sync_<op> operations that where the operation can be
1148;; represented directly RTL. This is all of the sync operations bar
1149;; nand.
0462169c 1150(define_code_iterator atomic_op [plus minus ior xor and])
43e9d192
IB		 1151
1152;; Iterator for integer conversions
1153(define_code_iterator FIXUORS [fix unsigned_fix])
1154
1709ff9b
JG		 1155;; Iterator for float conversions
1156(define_code_iterator FLOATUORS [float unsigned_float])
1157
43e9d192
IB		 1158;; Code iterator for variants of vector max and min.
1159(define_code_iterator MAXMIN [smax smin umax umin])
1160
998eaf97
JG		 1161(define_code_iterator FMAXMIN [smax smin])
1162
43e9d192
IB		 1163;; Code iterator for variants of vector max and min.
1164(define_code_iterator ADDSUB [plus minus])
1165
1166;; Code iterator for variants of vector saturating binary ops.
1167(define_code_iterator BINQOPS [ss_plus us_plus ss_minus us_minus])
1168
1169;; Code iterator for variants of vector saturating unary ops.
1170(define_code_iterator UNQOPS [ss_neg ss_abs])
1171
1172;; Code iterator for signed variants of vector saturating binary ops.
1173(define_code_iterator SBINQOPS [ss_plus ss_minus])
1174
889b9412
JG		 1175;; Comparison operators for <F>CM.
1176(define_code_iterator COMPARISONS [lt le eq ge gt])
1177
1178;; Unsigned comparison operators.
1179(define_code_iterator UCOMPARISONS [ltu leu geu gtu])
1180
75dd5ace
JG		 1181;; Unsigned comparison operators.
1182(define_code_iterator FAC_COMPARISONS [lt le ge gt])
1183
43cacb12
RS		 1184;; SVE integer unary operations.
1185(define_code_iterator SVE_INT_UNARY [neg not popcount])
1186
1187;; SVE floating-point unary operations.
1188(define_code_iterator SVE_FP_UNARY [neg abs sqrt])
1189
f22d7973
RS		 1190;; SVE integer comparisons.
1191(define_code_iterator SVE_INT_CMP [lt le eq ne ge gt ltu leu geu gtu])
1192
1193;; SVE floating-point comparisons.
1194(define_code_iterator SVE_FP_CMP [lt le eq ne ge gt])
1195
43e9d192
IB		 1196;; -------------------------------------------------------------------
1197;; Code Attributes
1198;; -------------------------------------------------------------------
1199;; Map rtl objects to optab names
1200(define_code_attr optab [(ashift "ashl")
1201 (ashiftrt "ashr")
1202 (lshiftrt "lshr")
1203 (rotatert "rotr")
1204 (sign_extend "extend")
1205 (zero_extend "zero_extend")
1206 (sign_extract "extv")
1207 (zero_extract "extzv")
384be29f
JG		 1208 (fix "fix")
1209 (unsigned_fix "fixuns")
1709ff9b
JG		 1210 (float "float")
1211 (unsigned_float "floatuns")
43cacb12 1212 (popcount "popcount")
43e9d192
IB		 1213 (and "and")
1214 (ior "ior")
1215 (xor "xor")
1216 (not "one_cmpl")
1217 (neg "neg")
1218 (plus "add")
1219 (minus "sub")
1220 (ss_plus "qadd")
1221 (us_plus "qadd")
1222 (ss_minus "qsub")
1223 (us_minus "qsub")
1224 (ss_neg "qneg")
1225 (ss_abs "qabs")
43cacb12
RS		 1226 (smin "smin")
1227 (smax "smax")
1228 (umin "umin")
1229 (umax "umax")
43e9d192
IB		 1230 (eq "eq")
1231 (ne "ne")
1232 (lt "lt")
889b9412
JG		 1233 (ge "ge")
1234 (le "le")
1235 (gt "gt")
1236 (ltu "ltu")
1237 (leu "leu")
1238 (geu "geu")
43cacb12
RS		 1239 (gtu "gtu")
1240 (abs "abs")
1241 (sqrt "sqrt")])
889b9412
JG		 1242
1243;; For comparison operators we use the FCM* and CM* instructions.
1244;; As there are no CMLE or CMLT instructions which act on 3 vector
1245;; operands, we must use CMGE or CMGT and swap the order of the
1246;; source operands.
1247
1248(define_code_attr n_optab [(lt "gt") (le "ge") (eq "eq") (ge "ge") (gt "gt")
1249 (ltu "hi") (leu "hs") (geu "hs") (gtu "hi")])
1250(define_code_attr cmp_1 [(lt "2") (le "2") (eq "1") (ge "1") (gt "1")
1251 (ltu "2") (leu "2") (geu "1") (gtu "1")])
1252(define_code_attr cmp_2 [(lt "1") (le "1") (eq "2") (ge "2") (gt "2")
1253 (ltu "1") (leu "1") (geu "2") (gtu "2")])
1254
1255(define_code_attr CMP [(lt "LT") (le "LE") (eq "EQ") (ge "GE") (gt "GT")
714e1b3b
KT		 1256 (ltu "LTU") (leu "LEU") (ne "NE") (geu "GEU")
1257 (gtu "GTU")])
43e9d192 1258
f22d7973
RS		 1259;; The AArch64 condition associated with an rtl comparison code.
1260(define_code_attr cmp_op [(lt "lt")
1261 (le "le")
1262 (eq "eq")
1263 (ne "ne")
1264 (ge "ge")
1265 (gt "gt")
1266 (ltu "lo")
1267 (leu "ls")
1268 (geu "hs")
1269 (gtu "hi")])
1270
384be29f
JG		 1271(define_code_attr fix_trunc_optab [(fix "fix_trunc")
1272 (unsigned_fix "fixuns_trunc")])
1273
43e9d192
IB		 1274;; Optab prefix for sign/zero-extending operations
1275(define_code_attr su_optab [(sign_extend "") (zero_extend "u")
1276 (div "") (udiv "u")
1277 (fix "") (unsigned_fix "u")
1709ff9b 1278 (float "s") (unsigned_float "u")
43e9d192
IB		 1279 (ss_plus "s") (us_plus "u")
1280 (ss_minus "s") (us_minus "u")])
1281
1282;; Similar for the instruction mnemonics
1283(define_code_attr shift [(ashift "lsl") (ashiftrt "asr")
1284 (lshiftrt "lsr") (rotatert "ror")])
1285
1286;; Map shift operators onto underlying bit-field instructions
1287(define_code_attr bfshift [(ashift "ubfiz") (ashiftrt "sbfx")
1288 (lshiftrt "ubfx") (rotatert "extr")])
1289
1290;; Logical operator instruction mnemonics
1291(define_code_attr logical [(and "and") (ior "orr") (xor "eor")])
1292
3204ac98
KT		 1293;; Operation names for negate and bitwise complement.
1294(define_code_attr neg_not_op [(neg "neg") (not "not")])
1295
43cacb12 1296;; Similar, but when the second operand is inverted.
43e9d192
IB		 1297(define_code_attr nlogical [(and "bic") (ior "orn") (xor "eon")])
1298
43cacb12
RS		 1299;; Similar, but when both operands are inverted.
1300(define_code_attr logical_nn [(and "nor") (ior "nand")])
1301
43e9d192
IB		 1302;; Sign- or zero-extending data-op
1303(define_code_attr su [(sign_extend "s") (zero_extend "u")
1304 (sign_extract "s") (zero_extract "u")
1305 (fix "s") (unsigned_fix "u")
998eaf97
JG		 1306 (div "s") (udiv "u")
1307 (smax "s") (umax "u")
1308 (smin "s") (umin "u")])
43e9d192 1309
43cacb12
RS		 1310;; Whether a shift is left or right.
1311(define_code_attr lr [(ashift "l") (ashiftrt "r") (lshiftrt "r")])
1312
096e8448
JW		 1313;; Emit conditional branch instructions.
1314(define_code_attr bcond [(eq "beq") (ne "bne") (lt "bne") (ge "beq")])
1315
43e9d192
IB		 1316;; Emit cbz/cbnz depending on comparison type.
1317(define_code_attr cbz [(eq "cbz") (ne "cbnz") (lt "cbnz") (ge "cbz")])
1318
973d2e01
TP		 1319;; Emit inverted cbz/cbnz depending on comparison type.
1320(define_code_attr inv_cb [(eq "cbnz") (ne "cbz") (lt "cbz") (ge "cbnz")])
1321
43e9d192
IB		 1322;; Emit tbz/tbnz depending on comparison type.
1323(define_code_attr tbz [(eq "tbz") (ne "tbnz") (lt "tbnz") (ge "tbz")])
1324
973d2e01
TP		 1325;; Emit inverted tbz/tbnz depending on comparison type.
1326(define_code_attr inv_tb [(eq "tbnz") (ne "tbz") (lt "tbz") (ge "tbnz")])
1327
43e9d192 1328;; Max/min attributes.
998eaf97
JG		 1329(define_code_attr maxmin [(smax "max")
1330 (smin "min")
1331 (umax "max")
1332 (umin "min")])
43e9d192
IB		 1333
1334;; MLA/MLS attributes.
1335(define_code_attr as [(ss_plus "a") (ss_minus "s")])
1336
0462169c
SN		 1337;; Atomic operations
1338(define_code_attr atomic_optab
1339 [(ior "or") (xor "xor") (and "and") (plus "add") (minus "sub")])
1340
1341(define_code_attr atomic_op_operand
1342 [(ior "aarch64_logical_operand")
1343 (xor "aarch64_logical_operand")
1344 (and "aarch64_logical_operand")
1345 (plus "aarch64_plus_operand")
1346 (minus "aarch64_plus_operand")])
43e9d192 1347
356c32e2
MW		 1348;; Constants acceptable for atomic operations.
1349;; This definition must appear in this file before the iterators it refers to.
1350(define_code_attr const_atomic
1351 [(plus "IJ") (minus "IJ")
1352 (xor "<lconst_atomic>") (ior "<lconst_atomic>")
1353 (and "<lconst_atomic>")])
1354
1355;; Attribute to describe constants acceptable in atomic logical operations
1356(define_mode_attr lconst_atomic [(QI "K") (HI "K") (SI "K") (DI "L")])
1357
43cacb12
RS		 1358;; The integer SVE instruction that implements an rtx code.
1359(define_code_attr sve_int_op [(plus "add")
1360 (neg "neg")
1361 (smin "smin")
1362 (smax "smax")
1363 (umin "umin")
1364 (umax "umax")
1365 (and "and")
1366 (ior "orr")
1367 (xor "eor")
1368 (not "not")
1369 (popcount "cnt")])
1370
1371;; The floating-point SVE instruction that implements an rtx code.
1372(define_code_attr sve_fp_op [(plus "fadd")
1373 (neg "fneg")
1374 (abs "fabs")
1375 (sqrt "fsqrt")])
1376
f22d7973
RS		 1377;; The SVE immediate constraint to use for an rtl code.
1378(define_code_attr sve_imm_con [(eq "vsc")
1379 (ne "vsc")
1380 (lt "vsc")
1381 (ge "vsc")
1382 (le "vsc")
1383 (gt "vsc")
1384 (ltu "vsd")
1385 (leu "vsd")
1386 (geu "vsd")
1387 (gtu "vsd")])
1388
43e9d192
IB		 1389;; -------------------------------------------------------------------
1390;; Int Iterators.
1391;; -------------------------------------------------------------------
75add2d0
KT		 1392
1393;; The unspec codes for the SABAL, UABAL AdvancedSIMD instructions.
1394(define_int_iterator ABAL [UNSPEC_SABAL UNSPEC_UABAL])
1395
1396;; The unspec codes for the SABDL2, UABDL2 AdvancedSIMD instructions.
1397(define_int_iterator ABDL2 [UNSPEC_SABDL2 UNSPEC_UABDL2])
1398
1399;; The unspec codes for the SADALP, UADALP AdvancedSIMD instructions.
1400(define_int_iterator ADALP [UNSPEC_SADALP UNSPEC_UADALP])
1401
43e9d192
IB		 1402(define_int_iterator MAXMINV [UNSPEC_UMAXV UNSPEC_UMINV
1403 UNSPEC_SMAXV UNSPEC_SMINV])
1404
998eaf97
JG		 1405(define_int_iterator FMAXMINV [UNSPEC_FMAXV UNSPEC_FMINV
1406 UNSPEC_FMAXNMV UNSPEC_FMINNMV])
43e9d192 1407
898f07b0
RS		 1408(define_int_iterator BITWISEV [UNSPEC_ANDV UNSPEC_IORV UNSPEC_XORV])
1409
43cacb12
RS		 1410(define_int_iterator LOGICALF [UNSPEC_ANDF UNSPEC_IORF UNSPEC_XORF])
1411
43e9d192
IB		 1412(define_int_iterator HADDSUB [UNSPEC_SHADD UNSPEC_UHADD
1413 UNSPEC_SRHADD UNSPEC_URHADD
1414 UNSPEC_SHSUB UNSPEC_UHSUB
1415 UNSPEC_SRHSUB UNSPEC_URHSUB])
1416
7a08d813 1417(define_int_iterator DOTPROD [UNSPEC_SDOT UNSPEC_UDOT])
43e9d192
IB		 1418
1419(define_int_iterator ADDSUBHN [UNSPEC_ADDHN UNSPEC_RADDHN
1420 UNSPEC_SUBHN UNSPEC_RSUBHN])
1421
1422(define_int_iterator ADDSUBHN2 [UNSPEC_ADDHN2 UNSPEC_RADDHN2
1423 UNSPEC_SUBHN2 UNSPEC_RSUBHN2])
1424
1efafef3
TC		 1425(define_int_iterator FMAXMIN_UNS [UNSPEC_FMAX UNSPEC_FMIN
1426 UNSPEC_FMAXNM UNSPEC_FMINNM])
202d0c11 1427
db58fd89
JW		 1428(define_int_iterator PAUTH_LR_SP [UNSPEC_PACISP UNSPEC_AUTISP])
1429
1430(define_int_iterator PAUTH_17_16 [UNSPEC_PACI1716 UNSPEC_AUTI1716])
1431
43e9d192
IB		 1432(define_int_iterator VQDMULH [UNSPEC_SQDMULH UNSPEC_SQRDMULH])
1433
1434(define_int_iterator USSUQADD [UNSPEC_SUQADD UNSPEC_USQADD])
1435
1436(define_int_iterator SUQMOVN [UNSPEC_SQXTN UNSPEC_UQXTN])
1437
1438(define_int_iterator VSHL [UNSPEC_SSHL UNSPEC_USHL
1439 UNSPEC_SRSHL UNSPEC_URSHL])
1440
1441(define_int_iterator VSHLL [UNSPEC_SSHLL UNSPEC_USHLL])
1442
1443(define_int_iterator VQSHL [UNSPEC_SQSHL UNSPEC_UQSHL
1444 UNSPEC_SQRSHL UNSPEC_UQRSHL])
1445
1446(define_int_iterator VSRA [UNSPEC_SSRA UNSPEC_USRA
1447 UNSPEC_SRSRA UNSPEC_URSRA])
1448
1449(define_int_iterator VSLRI [UNSPEC_SSLI UNSPEC_USLI
1450 UNSPEC_SSRI UNSPEC_USRI])
1451
1452
1453(define_int_iterator VRSHR_N [UNSPEC_SRSHR UNSPEC_URSHR])
1454
1455(define_int_iterator VQSHL_N [UNSPEC_SQSHLU UNSPEC_SQSHL UNSPEC_UQSHL])
1456
1457(define_int_iterator VQSHRN_N [UNSPEC_SQSHRUN UNSPEC_SQRSHRUN
1458 UNSPEC_SQSHRN UNSPEC_UQSHRN
1459 UNSPEC_SQRSHRN UNSPEC_UQRSHRN])
1460
57b26d65
MW		 1461(define_int_iterator SQRDMLH_AS [UNSPEC_SQRDMLAH UNSPEC_SQRDMLSH])
1462
cc4d934f
JG		 1463(define_int_iterator PERMUTE [UNSPEC_ZIP1 UNSPEC_ZIP2
1464 UNSPEC_TRN1 UNSPEC_TRN2
1465 UNSPEC_UZP1 UNSPEC_UZP2])
43e9d192 1466
43cacb12
RS		 1467(define_int_iterator OPTAB_PERMUTE [UNSPEC_ZIP1 UNSPEC_ZIP2
1468 UNSPEC_UZP1 UNSPEC_UZP2])
1469
923fcec3
AL		 1470(define_int_iterator REVERSE [UNSPEC_REV64 UNSPEC_REV32 UNSPEC_REV16])
1471
42fc9a7f 1472(define_int_iterator FRINT [UNSPEC_FRINTZ UNSPEC_FRINTP UNSPEC_FRINTM
0659ce6f
JG		 1473 UNSPEC_FRINTN UNSPEC_FRINTI UNSPEC_FRINTX
1474 UNSPEC_FRINTA])
42fc9a7f
JG		 1475
1476(define_int_iterator FCVT [UNSPEC_FRINTZ UNSPEC_FRINTP UNSPEC_FRINTM
ce966824 1477 UNSPEC_FRINTA UNSPEC_FRINTN])
42fc9a7f 1478
3f598afe
JW		 1479(define_int_iterator FCVT_F2FIXED [UNSPEC_FCVTZS UNSPEC_FCVTZU])
1480(define_int_iterator FCVT_FIXED2F [UNSPEC_SCVTF UNSPEC_UCVTF])
1481
0050faf8
JG		 1482(define_int_iterator FRECP [UNSPEC_FRECPE UNSPEC_FRECPX])
1483
5d357f26
KT		 1484(define_int_iterator CRC [UNSPEC_CRC32B UNSPEC_CRC32H UNSPEC_CRC32W
1485 UNSPEC_CRC32X UNSPEC_CRC32CB UNSPEC_CRC32CH
1486 UNSPEC_CRC32CW UNSPEC_CRC32CX])
1487
5a7a4e80
TB		 1488(define_int_iterator CRYPTO_AES [UNSPEC_AESE UNSPEC_AESD])
1489(define_int_iterator CRYPTO_AESMC [UNSPEC_AESMC UNSPEC_AESIMC])
1490
30442682
TB		 1491(define_int_iterator CRYPTO_SHA1 [UNSPEC_SHA1C UNSPEC_SHA1M UNSPEC_SHA1P])
1492
b9cb0a44
TB		 1493(define_int_iterator CRYPTO_SHA256 [UNSPEC_SHA256H UNSPEC_SHA256H2])
1494
27086ea3
MC		 1495(define_int_iterator CRYPTO_SHA512 [UNSPEC_SHA512H UNSPEC_SHA512H2])
1496
1497(define_int_iterator CRYPTO_SM3TT [UNSPEC_SM3TT1A UNSPEC_SM3TT1B
1498 UNSPEC_SM3TT2A UNSPEC_SM3TT2B])
1499
1500(define_int_iterator CRYPTO_SM3PART [UNSPEC_SM3PARTW1 UNSPEC_SM3PARTW2])
1501
1502;; Iterators for fp16 operations
1503
1504(define_int_iterator VFMLA16_LOW [UNSPEC_FMLAL UNSPEC_FMLSL])
1505
1506(define_int_iterator VFMLA16_HIGH [UNSPEC_FMLAL2 UNSPEC_FMLSL2])
1507
43cacb12
RS		 1508(define_int_iterator UNPACK [UNSPEC_UNPACKSHI UNSPEC_UNPACKUHI
1509 UNSPEC_UNPACKSLO UNSPEC_UNPACKULO])
1510
1511(define_int_iterator UNPACK_UNSIGNED [UNSPEC_UNPACKULO UNSPEC_UNPACKUHI])
1512
11e9443f
RS		 1513(define_int_iterator MUL_HIGHPART [UNSPEC_SMUL_HIGHPART UNSPEC_UMUL_HIGHPART])
1514
0972596e
RS		 1515(define_int_iterator SVE_COND_INT_OP [UNSPEC_COND_ADD UNSPEC_COND_SUB
1516 UNSPEC_COND_SMAX UNSPEC_COND_UMAX
1517 UNSPEC_COND_SMIN UNSPEC_COND_UMIN
1518 UNSPEC_COND_AND
1519 UNSPEC_COND_ORR
1520 UNSPEC_COND_EOR])
1521
1522(define_int_iterator SVE_COND_FP_OP [UNSPEC_COND_ADD UNSPEC_COND_SUB])
1523
43cacb12
RS		 1524(define_int_iterator SVE_COND_FP_CMP [UNSPEC_COND_LT UNSPEC_COND_LE
1525 UNSPEC_COND_EQ UNSPEC_COND_NE
1526 UNSPEC_COND_GE UNSPEC_COND_GT])
1527
d81cb613
MW		 1528;; Iterators for atomic operations.
1529
1530(define_int_iterator ATOMIC_LDOP
1531 [UNSPECV_ATOMIC_LDOP_OR UNSPECV_ATOMIC_LDOP_BIC
1532 UNSPECV_ATOMIC_LDOP_XOR UNSPECV_ATOMIC_LDOP_PLUS])
1533
1534(define_int_attr atomic_ldop
1535 [(UNSPECV_ATOMIC_LDOP_OR "set") (UNSPECV_ATOMIC_LDOP_BIC "clr")
1536 (UNSPECV_ATOMIC_LDOP_XOR "eor") (UNSPECV_ATOMIC_LDOP_PLUS "add")])
1537
43e9d192
IB		 1538;; -------------------------------------------------------------------
1539;; Int Iterators Attributes.
1540;; -------------------------------------------------------------------
43cacb12
RS		 1541
1542;; The optab associated with an operation. Note that for ANDF, IORF
1543;; and XORF, the optab pattern is not actually defined; we just use this
1544;; name for consistency with the integer patterns.
1545(define_int_attr optab [(UNSPEC_ANDF "and")
1546 (UNSPEC_IORF "ior")
898f07b0
RS		 1547 (UNSPEC_XORF "xor")
1548 (UNSPEC_ANDV "and")
1549 (UNSPEC_IORV "ior")
0972596e
RS		 1550 (UNSPEC_XORV "xor")
1551 (UNSPEC_COND_ADD "add")
1552 (UNSPEC_COND_SUB "sub")
1553 (UNSPEC_COND_SMAX "smax")
1554 (UNSPEC_COND_UMAX "umax")
1555 (UNSPEC_COND_SMIN "smin")
1556 (UNSPEC_COND_UMIN "umin")
1557 (UNSPEC_COND_AND "and")
1558 (UNSPEC_COND_ORR "ior")
1559 (UNSPEC_COND_EOR "xor")])
43cacb12 1560
998eaf97
JG		 1561(define_int_attr maxmin_uns [(UNSPEC_UMAXV "umax")
1562 (UNSPEC_UMINV "umin")
1563 (UNSPEC_SMAXV "smax")
1564 (UNSPEC_SMINV "smin")
1565 (UNSPEC_FMAX "smax_nan")
1566 (UNSPEC_FMAXNMV "smax")
1567 (UNSPEC_FMAXV "smax_nan")
1568 (UNSPEC_FMIN "smin_nan")
1569 (UNSPEC_FMINNMV "smin")
1efafef3
TC		 1570 (UNSPEC_FMINV "smin_nan")
1571 (UNSPEC_FMAXNM "fmax")
1572 (UNSPEC_FMINNM "fmin")])
998eaf97
JG		 1573
1574(define_int_attr maxmin_uns_op [(UNSPEC_UMAXV "umax")
1575 (UNSPEC_UMINV "umin")
1576 (UNSPEC_SMAXV "smax")
1577 (UNSPEC_SMINV "smin")
1578 (UNSPEC_FMAX "fmax")
1579 (UNSPEC_FMAXNMV "fmaxnm")
1580 (UNSPEC_FMAXV "fmax")
1581 (UNSPEC_FMIN "fmin")
1582 (UNSPEC_FMINNMV "fminnm")
1efafef3
TC		 1583 (UNSPEC_FMINV "fmin")
1584 (UNSPEC_FMAXNM "fmaxnm")
1585 (UNSPEC_FMINNM "fminnm")])
202d0c11 1586
898f07b0
RS		 1587(define_int_attr bit_reduc_op [(UNSPEC_ANDV "andv")
1588 (UNSPEC_IORV "orv")
1589 (UNSPEC_XORV "eorv")])
1590
43cacb12
RS		 1591;; The SVE logical instruction that implements an unspec.
1592(define_int_attr logicalf_op [(UNSPEC_ANDF "and")
1593 (UNSPEC_IORF "orr")
1594 (UNSPEC_XORF "eor")])
1595
1596;; "s" for signed operations and "u" for unsigned ones.
1597(define_int_attr su [(UNSPEC_UNPACKSHI "s")
1598 (UNSPEC_UNPACKUHI "u")
1599 (UNSPEC_UNPACKSLO "s")
11e9443f
RS		 1600 (UNSPEC_UNPACKULO "u")
1601 (UNSPEC_SMUL_HIGHPART "s")
1602 (UNSPEC_UMUL_HIGHPART "u")])
43cacb12 1603
43e9d192
IB		 1604(define_int_attr sur [(UNSPEC_SHADD "s") (UNSPEC_UHADD "u")
1605 (UNSPEC_SRHADD "sr") (UNSPEC_URHADD "ur")
1606 (UNSPEC_SHSUB "s") (UNSPEC_UHSUB "u")
1607 (UNSPEC_SRHSUB "sr") (UNSPEC_URHSUB "ur")
1608 (UNSPEC_ADDHN "") (UNSPEC_RADDHN "r")
75add2d0
KT		 1609 (UNSPEC_SABAL "s") (UNSPEC_UABAL "u")
1610 (UNSPEC_SABDL2 "s") (UNSPEC_UABDL2 "u")
1611 (UNSPEC_SADALP "s") (UNSPEC_UADALP "u")
43e9d192
IB		 1612 (UNSPEC_SUBHN "") (UNSPEC_RSUBHN "r")
1613 (UNSPEC_ADDHN2 "") (UNSPEC_RADDHN2 "r")
1614 (UNSPEC_SUBHN2 "") (UNSPEC_RSUBHN2 "r")
1615 (UNSPEC_SQXTN "s") (UNSPEC_UQXTN "u")
1616 (UNSPEC_USQADD "us") (UNSPEC_SUQADD "su")
1617 (UNSPEC_SSLI "s") (UNSPEC_USLI "u")
1618 (UNSPEC_SSRI "s") (UNSPEC_USRI "u")
1619 (UNSPEC_USRA "u") (UNSPEC_SSRA "s")
1620 (UNSPEC_URSRA "ur") (UNSPEC_SRSRA "sr")
1621 (UNSPEC_URSHR "ur") (UNSPEC_SRSHR "sr")
1622 (UNSPEC_SQSHLU "s") (UNSPEC_SQSHL "s")
1623 (UNSPEC_UQSHL "u")
1624 (UNSPEC_SQSHRUN "s") (UNSPEC_SQRSHRUN "s")
1625 (UNSPEC_SQSHRN "s") (UNSPEC_UQSHRN "u")
1626 (UNSPEC_SQRSHRN "s") (UNSPEC_UQRSHRN "u")
1627 (UNSPEC_USHL "u") (UNSPEC_SSHL "s")
1628 (UNSPEC_USHLL "u") (UNSPEC_SSHLL "s")
1629 (UNSPEC_URSHL "ur") (UNSPEC_SRSHL "sr")
1630 (UNSPEC_UQRSHL "u") (UNSPEC_SQRSHL "s")
7a08d813 1631 (UNSPEC_SDOT "s") (UNSPEC_UDOT "u")
43e9d192
IB		 1632])
1633
1634(define_int_attr r [(UNSPEC_SQDMULH "") (UNSPEC_SQRDMULH "r")
1635 (UNSPEC_SQSHRUN "") (UNSPEC_SQRSHRUN "r")
1636 (UNSPEC_SQSHRN "") (UNSPEC_UQSHRN "")
1637 (UNSPEC_SQRSHRN "r") (UNSPEC_UQRSHRN "r")
1638 (UNSPEC_SQSHL "") (UNSPEC_UQSHL "")
1639 (UNSPEC_SQRSHL "r")(UNSPEC_UQRSHL "r")
1640])
1641
1642(define_int_attr lr [(UNSPEC_SSLI "l") (UNSPEC_USLI "l")
1643 (UNSPEC_SSRI "r") (UNSPEC_USRI "r")])
1644
1645(define_int_attr u [(UNSPEC_SQSHLU "u") (UNSPEC_SQSHL "") (UNSPEC_UQSHL "")
1646 (UNSPEC_SQSHRUN "u") (UNSPEC_SQRSHRUN "u")
1647 (UNSPEC_SQSHRN "") (UNSPEC_UQSHRN "")
1648 (UNSPEC_SQRSHRN "") (UNSPEC_UQRSHRN "")])
1649
1650(define_int_attr addsub [(UNSPEC_SHADD "add")
1651 (UNSPEC_UHADD "add")
1652 (UNSPEC_SRHADD "add")
1653 (UNSPEC_URHADD "add")
1654 (UNSPEC_SHSUB "sub")
1655 (UNSPEC_UHSUB "sub")
1656 (UNSPEC_SRHSUB "sub")
1657 (UNSPEC_URHSUB "sub")
1658 (UNSPEC_ADDHN "add")
1659 (UNSPEC_SUBHN "sub")
1660 (UNSPEC_RADDHN "add")
1661 (UNSPEC_RSUBHN "sub")
1662 (UNSPEC_ADDHN2 "add")
1663 (UNSPEC_SUBHN2 "sub")
1664 (UNSPEC_RADDHN2 "add")
1665 (UNSPEC_RSUBHN2 "sub")])
1666
cb23a30c
JG		 1667(define_int_attr offsetlr [(UNSPEC_SSLI "") (UNSPEC_USLI "")
1668 (UNSPEC_SSRI "offset_")
1669 (UNSPEC_USRI "offset_")])
43e9d192 1670
42fc9a7f
JG		 1671;; Standard pattern names for floating-point rounding instructions.
1672(define_int_attr frint_pattern [(UNSPEC_FRINTZ "btrunc")
1673 (UNSPEC_FRINTP "ceil")
1674 (UNSPEC_FRINTM "floor")
1675 (UNSPEC_FRINTI "nearbyint")
1676 (UNSPEC_FRINTX "rint")
0659ce6f
JG		 1677 (UNSPEC_FRINTA "round")
1678 (UNSPEC_FRINTN "frintn")])
42fc9a7f
JG		 1679
1680;; frint suffix for floating-point rounding instructions.
1681(define_int_attr frint_suffix [(UNSPEC_FRINTZ "z") (UNSPEC_FRINTP "p")
1682 (UNSPEC_FRINTM "m") (UNSPEC_FRINTI "i")
0659ce6f
JG		 1683 (UNSPEC_FRINTX "x") (UNSPEC_FRINTA "a")
1684 (UNSPEC_FRINTN "n")])
42fc9a7f
JG		 1685
1686(define_int_attr fcvt_pattern [(UNSPEC_FRINTZ "btrunc") (UNSPEC_FRINTA "round")
ce966824
JG		 1687 (UNSPEC_FRINTP "ceil") (UNSPEC_FRINTM "floor")
1688 (UNSPEC_FRINTN "frintn")])
42fc9a7f 1689
3f598afe
JW		 1690(define_int_attr fcvt_fixed_insn [(UNSPEC_SCVTF "scvtf")
1691 (UNSPEC_UCVTF "ucvtf")
1692 (UNSPEC_FCVTZS "fcvtzs")
1693 (UNSPEC_FCVTZU "fcvtzu")])
1694
db58fd89
JW		 1695;; Pointer authentication mnemonic prefix.
1696(define_int_attr pauth_mnem_prefix [(UNSPEC_PACISP "paci")
1697 (UNSPEC_AUTISP "auti")
1698 (UNSPEC_PACI1716 "paci")
1699 (UNSPEC_AUTI1716 "auti")])
1700
1701;; Pointer authentication HINT number for NOP space instructions using A Key.
1702(define_int_attr pauth_hint_num_a [(UNSPEC_PACISP "25")
1703 (UNSPEC_AUTISP "29")
1704 (UNSPEC_PACI1716 "8")
1705 (UNSPEC_AUTI1716 "12")])
1706
cc4d934f
JG		 1707(define_int_attr perm_insn [(UNSPEC_ZIP1 "zip") (UNSPEC_ZIP2 "zip")
1708 (UNSPEC_TRN1 "trn") (UNSPEC_TRN2 "trn")
1709 (UNSPEC_UZP1 "uzp") (UNSPEC_UZP2 "uzp")])
1710
923fcec3
AL		 1711; op code for REV instructions (size within which elements are reversed).
1712(define_int_attr rev_op [(UNSPEC_REV64 "64") (UNSPEC_REV32 "32")
1713 (UNSPEC_REV16 "16")])
1714
cc4d934f
JG		 1715(define_int_attr perm_hilo [(UNSPEC_ZIP1 "1") (UNSPEC_ZIP2 "2")
1716 (UNSPEC_TRN1 "1") (UNSPEC_TRN2 "2")
43cacb12
RS		 1717 (UNSPEC_UZP1 "1") (UNSPEC_UZP2 "2")
1718 (UNSPEC_UNPACKSHI "hi") (UNSPEC_UNPACKUHI "hi")
1719 (UNSPEC_UNPACKSLO "lo") (UNSPEC_UNPACKULO "lo")])
0050faf8 1720
9bfb28ed
RS		 1721;; Return true if the associated optab refers to the high-numbered lanes,
1722;; false if it refers to the low-numbered lanes. The convention is for
1723;; "hi" to refer to the low-numbered lanes (the first ones in memory)
1724;; for big-endian.
1725(define_int_attr hi_lanes_optab [(UNSPEC_UNPACKSHI "!BYTES_BIG_ENDIAN")
1726 (UNSPEC_UNPACKUHI "!BYTES_BIG_ENDIAN")
1727 (UNSPEC_UNPACKSLO "BYTES_BIG_ENDIAN")
1728 (UNSPEC_UNPACKULO "BYTES_BIG_ENDIAN")])
1729
0050faf8 1730(define_int_attr frecp_suffix [(UNSPEC_FRECPE "e") (UNSPEC_FRECPX "x")])
5a7a4e80 1731
5d357f26
KT		 1732(define_int_attr crc_variant [(UNSPEC_CRC32B "crc32b") (UNSPEC_CRC32H "crc32h")
1733 (UNSPEC_CRC32W "crc32w") (UNSPEC_CRC32X "crc32x")
1734 (UNSPEC_CRC32CB "crc32cb") (UNSPEC_CRC32CH "crc32ch")
1735 (UNSPEC_CRC32CW "crc32cw") (UNSPEC_CRC32CX "crc32cx")])
1736
1737(define_int_attr crc_mode [(UNSPEC_CRC32B "QI") (UNSPEC_CRC32H "HI")
1738 (UNSPEC_CRC32W "SI") (UNSPEC_CRC32X "DI")
1739 (UNSPEC_CRC32CB "QI") (UNSPEC_CRC32CH "HI")
1740 (UNSPEC_CRC32CW "SI") (UNSPEC_CRC32CX "DI")])
1741
5a7a4e80
TB		 1742(define_int_attr aes_op [(UNSPEC_AESE "e") (UNSPEC_AESD "d")])
1743(define_int_attr aesmc_op [(UNSPEC_AESMC "mc") (UNSPEC_AESIMC "imc")])
30442682
TB		 1744
1745(define_int_attr sha1_op [(UNSPEC_SHA1C "c") (UNSPEC_SHA1P "p")
1746 (UNSPEC_SHA1M "m")])
b9cb0a44
TB		 1747
1748(define_int_attr sha256_op [(UNSPEC_SHA256H "") (UNSPEC_SHA256H2 "2")])
57b26d65
MW		 1749
1750(define_int_attr rdma_as [(UNSPEC_SQRDMLAH "a") (UNSPEC_SQRDMLSH "s")])
27086ea3
MC		 1751
1752(define_int_attr sha512_op [(UNSPEC_SHA512H "") (UNSPEC_SHA512H2 "2")])
1753
1754(define_int_attr sm3tt_op [(UNSPEC_SM3TT1A "1a") (UNSPEC_SM3TT1B "1b")
1755 (UNSPEC_SM3TT2A "2a") (UNSPEC_SM3TT2B "2b")])
1756
1757(define_int_attr sm3part_op [(UNSPEC_SM3PARTW1 "1") (UNSPEC_SM3PARTW2 "2")])
1758
1759(define_int_attr f16mac1 [(UNSPEC_FMLAL "a") (UNSPEC_FMLSL "s")
1760 (UNSPEC_FMLAL2 "a") (UNSPEC_FMLSL2 "s")])
43cacb12
RS		 1761
1762;; The condition associated with an UNSPEC_COND_<xx>.
1763(define_int_attr cmp_op [(UNSPEC_COND_LT "lt")
1764 (UNSPEC_COND_LE "le")
1765 (UNSPEC_COND_EQ "eq")
1766 (UNSPEC_COND_NE "ne")
1767 (UNSPEC_COND_GE "ge")
f22d7973 1768 (UNSPEC_COND_GT "gt")])
0972596e
RS		 1769
1770(define_int_attr sve_int_op [(UNSPEC_COND_ADD "add")
1771 (UNSPEC_COND_SUB "sub")
1772 (UNSPEC_COND_SMAX "smax")
1773 (UNSPEC_COND_UMAX "umax")
1774 (UNSPEC_COND_SMIN "smin")
1775 (UNSPEC_COND_UMIN "umin")
1776 (UNSPEC_COND_AND "and")
1777 (UNSPEC_COND_ORR "orr")
1778 (UNSPEC_COND_EOR "eor")])
1779
1780(define_int_attr sve_fp_op [(UNSPEC_COND_ADD "fadd")
1781 (UNSPEC_COND_SUB "fsub")])
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