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[AArch64] Use SVE ADR to optimise shift-add sequences
[thirdparty/gcc.git] / gcc / config / aarch64 / iterators.md
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43e9d192 1;; Machine description for AArch64 architecture.
a5544970 2;; Copyright (C) 2009-2019 Free Software Foundation, Inc.
43e9d192
IB		 3;; Contributed by ARM Ltd.
4;;
5;; This file is part of GCC.
6;;
7;; GCC is free software; you can redistribute it and/or modify it
8;; under the terms of the GNU General Public License as published by
9;; the Free Software Foundation; either version 3, or (at your option)
10;; any later version.
11;;
12;; GCC is distributed in the hope that it will be useful, but
13;; WITHOUT ANY WARRANTY; without even the implied warranty of
14;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15;; General Public License for more details.
16;;
17;; You should have received a copy of the GNU General Public License
18;; along with GCC; see the file COPYING3. If not see
19;; <http://www.gnu.org/licenses/>.
20
21;; -------------------------------------------------------------------
22;; Mode Iterators
23;; -------------------------------------------------------------------
24
25
26;; Iterator for General Purpose Integer registers (32- and 64-bit modes)
27(define_mode_iterator GPI [SI DI])
28
d7f33f07
JW		 29;; Iterator for HI, SI, DI, some instructions can only work on these modes.
30(define_mode_iterator GPI_I16 [(HI "AARCH64_ISA_F16") SI DI])
31
43e9d192
IB		 32;; Iterator for QI and HI modes
33(define_mode_iterator SHORT [QI HI])
34
35;; Iterator for all integer modes (up to 64-bit)
36(define_mode_iterator ALLI [QI HI SI DI])
37
c0111dc4
RE		 38;; Iterator for all integer modes (up to 128-bit)
39(define_mode_iterator ALLI_TI [QI HI SI DI TI])
40
43e9d192
IB		 41;; Iterator for all integer modes that can be extended (up to 64-bit)
42(define_mode_iterator ALLX [QI HI SI])
43
44;; Iterator for General Purpose Floating-point registers (32- and 64-bit modes)
45(define_mode_iterator GPF [SF DF])
46
d7f33f07
JW		 47;; Iterator for all scalar floating point modes (HF, SF, DF)
48(define_mode_iterator GPF_F16 [(HF "AARCH64_ISA_F16") SF DF])
49
90e6443f
TC		 50;; Iterator for all scalar floating point modes (HF, SF, DF)
51(define_mode_iterator GPF_HF [HF SF DF])
52
09fcd8e1
RR		 53;; Iterator for all scalar floating point modes (HF, SF, DF and TF)
54(define_mode_iterator GPF_TF_F16 [HF SF DF TF])
c2ec330c 55
922f9c25
AL		 56;; Double vector modes.
57(define_mode_iterator VDF [V2SF V4HF])
58
b4f50fd4
RR		 59;; Iterator for all scalar floating point modes (SF, DF and TF)
60(define_mode_iterator GPF_TF [SF DF TF])
61
43cacb12 62;; Integer Advanced SIMD modes.
43e9d192
IB		 63(define_mode_iterator VDQ_I [V8QI V16QI V4HI V8HI V2SI V4SI V2DI])
64
43cacb12 65;; Advanced SIMD and scalar, 64 & 128-bit container, all integer modes.
43e9d192
IB		 66(define_mode_iterator VSDQ_I [V8QI V16QI V4HI V8HI V2SI V4SI V2DI QI HI SI DI])
67
43cacb12
RS		 68;; Advanced SIMD and scalar, 64 & 128-bit container: all Advanced SIMD
69;; integer modes; 64-bit scalar integer mode.
43e9d192
IB		 70(define_mode_iterator VSDQ_I_DI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI DI])
71
72;; Double vector modes.
71a11456 73(define_mode_iterator VD [V8QI V4HI V4HF V2SI V2SF])
43e9d192 74
dfe1da23
JW		 75;; All modes stored in registers d0-d31.
76(define_mode_iterator DREG [V8QI V4HI V4HF V2SI V2SF DF])
77
78;; Copy of the above.
79(define_mode_iterator DREG2 [V8QI V4HI V4HF V2SI V2SF DF])
80
43cacb12 81;; Advanced SIMD, 64-bit container, all integer modes.
43e9d192
IB		 82(define_mode_iterator VD_BHSI [V8QI V4HI V2SI])
83
84;; 128 and 64-bit container; 8, 16, 32-bit vector integer modes
85(define_mode_iterator VDQ_BHSI [V8QI V16QI V4HI V8HI V2SI V4SI])
86
87;; Quad vector modes.
71a11456 88(define_mode_iterator VQ [V16QI V8HI V4SI V2DI V8HF V4SF V2DF])
43e9d192 89
9f5361c8
KT		 90;; Copy of the above.
91(define_mode_iterator VQ2 [V16QI V8HI V4SI V2DI V8HF V4SF V2DF])
92
d21052eb
TC		 93;; Quad integer vector modes.
94(define_mode_iterator VQ_I [V16QI V8HI V4SI V2DI])
95
51437269 96;; VQ without 2 element modes.
71a11456 97(define_mode_iterator VQ_NO2E [V16QI V8HI V4SI V8HF V4SF])
51437269
GW		 98
99;; Quad vector with only 2 element modes.
100(define_mode_iterator VQ_2E [V2DI V2DF])
101
28514dda
YZ		 102;; This mode iterator allows :P to be used for patterns that operate on
103;; addresses in different modes. In LP64, only DI will match, while in
104;; ILP32, either can match.
105(define_mode_iterator P [(SI "ptr_mode == SImode || Pmode == SImode")
106 (DI "ptr_mode == DImode || Pmode == DImode")])
107
43e9d192
IB		 108;; This mode iterator allows :PTR to be used for patterns that operate on
109;; pointer-sized quantities. Exactly one of the two alternatives will match.
28514dda 110(define_mode_iterator PTR [(SI "ptr_mode == SImode") (DI "ptr_mode == DImode")])
43e9d192 111
43cacb12 112;; Advanced SIMD Float modes suitable for moving, loading and storing.
862abc04
AL		 113(define_mode_iterator VDQF_F16 [V4HF V8HF V2SF V4SF V2DF])
114
43cacb12 115;; Advanced SIMD Float modes.
43e9d192 116(define_mode_iterator VDQF [V2SF V4SF V2DF])
daef0a8c
JW		 117(define_mode_iterator VHSDF [(V4HF "TARGET_SIMD_F16INST")
118 (V8HF "TARGET_SIMD_F16INST")
119 V2SF V4SF V2DF])
43e9d192 120
43cacb12 121;; Advanced SIMD Float modes, and DF.
daef0a8c
JW		 122(define_mode_iterator VHSDF_DF [(V4HF "TARGET_SIMD_F16INST")
123 (V8HF "TARGET_SIMD_F16INST")
124 V2SF V4SF V2DF DF])
d7f33f07
JW		 125(define_mode_iterator VHSDF_HSDF [(V4HF "TARGET_SIMD_F16INST")
126 (V8HF "TARGET_SIMD_F16INST")
127 V2SF V4SF V2DF
128 (HF "TARGET_SIMD_F16INST")
129 SF DF])
f421c516 130
43cacb12 131;; Advanced SIMD single Float modes.
828e70c1
JG		 132(define_mode_iterator VDQSF [V2SF V4SF])
133
03873eb9
AL		 134;; Quad vector Float modes with half/single elements.
135(define_mode_iterator VQ_HSF [V8HF V4SF])
136
fc21784d
JG		 137;; Modes suitable to use as the return type of a vcond expression.
138(define_mode_iterator VDQF_COND [V2SF V2SI V4SF V4SI V2DF V2DI])
139
43cacb12 140;; All scalar and Advanced SIMD Float modes.
889b9412
JG		 141(define_mode_iterator VALLF [V2SF V4SF V2DF SF DF])
142
43cacb12 143;; Advanced SIMD Float modes with 2 elements.
43e9d192
IB		 144(define_mode_iterator V2F [V2SF V2DF])
145
43cacb12 146;; All Advanced SIMD modes on which we support any arithmetic operations.
43e9d192
IB		 147(define_mode_iterator VALL [V8QI V16QI V4HI V8HI V2SI V4SI V2DI V2SF V4SF V2DF])
148
43cacb12 149;; All Advanced SIMD modes suitable for moving, loading, and storing.
71a11456
AL		 150(define_mode_iterator VALL_F16 [V8QI V16QI V4HI V8HI V2SI V4SI V2DI
151 V4HF V8HF V2SF V4SF V2DF])
152
88119b46
KT		 153;; The VALL_F16 modes except the 128-bit 2-element ones.
154(define_mode_iterator VALL_F16_NO_V2Q [V8QI V16QI V4HI V8HI V2SI V4SI
155 V4HF V8HF V2SF V4SF])
156
43cacb12 157;; All Advanced SIMD modes barring HF modes, plus DI.
a50344cb
TB		 158(define_mode_iterator VALLDI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI V2SF V4SF V2DF DI])
159
43cacb12 160;; All Advanced SIMD modes and DI.
71a11456
AL		 161(define_mode_iterator VALLDI_F16 [V8QI V16QI V4HI V8HI V2SI V4SI V2DI
162 V4HF V8HF V2SF V4SF V2DF DI])
163
43cacb12 164;; All Advanced SIMD modes, plus DI and DF.
46e778c4 165(define_mode_iterator VALLDIF [V8QI V16QI V4HI V8HI V2SI V4SI
7c369485 166 V2DI V4HF V8HF V2SF V4SF V2DF DI DF])
46e778c4 167
43cacb12 168;; Advanced SIMD modes for Integer reduction across lanes.
92835317
TB		 169(define_mode_iterator VDQV [V8QI V16QI V4HI V8HI V4SI V2DI])
170
43cacb12 171;; Advanced SIMD modes (except V2DI) for Integer reduction across lanes.
92835317 172(define_mode_iterator VDQV_S [V8QI V16QI V4HI V8HI V4SI])
43e9d192
IB		 173
174;; All double integer narrow-able modes.
175(define_mode_iterator VDN [V4HI V2SI DI])
176
177;; All quad integer narrow-able modes.
178(define_mode_iterator VQN [V8HI V4SI V2DI])
179
43cacb12
RS		 180;; Advanced SIMD and scalar 128-bit container: narrowable 16, 32, 64-bit
181;; integer modes
43e9d192
IB		 182(define_mode_iterator VSQN_HSDI [V8HI V4SI V2DI HI SI DI])
183
184;; All quad integer widen-able modes.
185(define_mode_iterator VQW [V16QI V8HI V4SI])
186
187;; Double vector modes for combines.
7c369485 188(define_mode_iterator VDC [V8QI V4HI V4HF V2SI V2SF DI DF])
43e9d192 189
43cacb12 190;; Advanced SIMD modes except double int.
43e9d192 191(define_mode_iterator VDQIF [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF V2DF])
703bbcdf
JW		 192(define_mode_iterator VDQIF_F16 [V8QI V16QI V4HI V8HI V2SI V4SI
193 V4HF V8HF V2SF V4SF V2DF])
43e9d192 194
43cacb12 195;; Advanced SIMD modes for S type.
58a3bd25
FY		 196(define_mode_iterator VDQ_SI [V2SI V4SI])
197
43cacb12 198;; Advanced SIMD modes for S and D.
2644d4d9
JW		 199(define_mode_iterator VDQ_SDI [V2SI V4SI V2DI])
200
43cacb12 201;; Advanced SIMD modes for H, S and D.
33d72b63
JW		 202(define_mode_iterator VDQ_HSDI [(V4HI "TARGET_SIMD_F16INST")
203 (V8HI "TARGET_SIMD_F16INST")
204 V2SI V4SI V2DI])
205
43cacb12 206;; Scalar and Advanced SIMD modes for S and D.
2644d4d9
JW		 207(define_mode_iterator VSDQ_SDI [V2SI V4SI V2DI SI DI])
208
43cacb12 209;; Scalar and Advanced SIMD modes for S and D, Advanced SIMD modes for H.
33d72b63
JW		 210(define_mode_iterator VSDQ_HSDI [(V4HI "TARGET_SIMD_F16INST")
211 (V8HI "TARGET_SIMD_F16INST")
68ad28c3
JW		 212 V2SI V4SI V2DI
213 (HI "TARGET_SIMD_F16INST")
214 SI DI])
33d72b63 215
43cacb12 216;; Advanced SIMD modes for Q and H types.
66adb8eb
JG		 217(define_mode_iterator VDQQH [V8QI V16QI V4HI V8HI])
218
43cacb12 219;; Advanced SIMD modes for H and S types.
43e9d192
IB		 220(define_mode_iterator VDQHS [V4HI V8HI V2SI V4SI])
221
43cacb12 222;; Advanced SIMD modes for H, S and D types.
c7f28cd5
KT		 223(define_mode_iterator VDQHSD [V4HI V8HI V2SI V4SI V2DI])
224
43cacb12 225;; Advanced SIMD and scalar integer modes for H and S.
43e9d192
IB		 226(define_mode_iterator VSDQ_HSI [V4HI V8HI V2SI V4SI HI SI])
227
43cacb12 228;; Advanced SIMD and scalar 64-bit container: 16, 32-bit integer modes.
43e9d192
IB		 229(define_mode_iterator VSD_HSI [V4HI V2SI HI SI])
230
43cacb12 231;; Advanced SIMD 64-bit container: 16, 32-bit integer modes.
43e9d192
IB		 232(define_mode_iterator VD_HSI [V4HI V2SI])
233
234;; Scalar 64-bit container: 16, 32-bit integer modes
235(define_mode_iterator SD_HSI [HI SI])
236
43cacb12 237;; Advanced SIMD 64-bit container: 16, 32-bit integer modes.
43e9d192
IB		 238(define_mode_iterator VQ_HSI [V8HI V4SI])
239
240;; All byte modes.
241(define_mode_iterator VB [V8QI V16QI])
242
5e32e83b
JW		 243;; 2 and 4 lane SI modes.
244(define_mode_iterator VS [V2SI V4SI])
245
43e9d192
IB		 246(define_mode_iterator TX [TI TF])
247
43cacb12 248;; Advanced SIMD opaque structure modes.
43e9d192
IB		 249(define_mode_iterator VSTRUCT [OI CI XI])
250
251;; Double scalar modes
252(define_mode_iterator DX [DI DF])
253
dfe1da23
JW		 254;; Duplicate of the above
255(define_mode_iterator DX2 [DI DF])
256
257;; Single scalar modes
258(define_mode_iterator SX [SI SF])
259
260;; Duplicate of the above
261(define_mode_iterator SX2 [SI SF])
262
263;; Single and double integer and float modes
264(define_mode_iterator DSX [DF DI SF SI])
265
266
43cacb12 267;; Modes available for Advanced SIMD <f>mul lane operations.
ab2e8f01
JW		 268(define_mode_iterator VMUL [V4HI V8HI V2SI V4SI
269 (V4HF "TARGET_SIMD_F16INST")
270 (V8HF "TARGET_SIMD_F16INST")
271 V2SF V4SF V2DF])
779aea46 272
43cacb12
RS		 273;; Modes available for Advanced SIMD <f>mul lane operations changing lane
274;; count.
779aea46
JG		 275(define_mode_iterator VMUL_CHANGE_NLANES [V4HI V8HI V2SI V4SI V2SF V4SF])
276
43cacb12
RS		 277;; All SVE vector modes.
278(define_mode_iterator SVE_ALL [VNx16QI VNx8HI VNx4SI VNx2DI
279 VNx8HF VNx4SF VNx2DF])
280
95eb5537
RS		 281;; Iterators for single modes, for "@" patterns.
282(define_mode_iterator VNx4SI_ONLY [VNx4SI])
283(define_mode_iterator VNx2DF_ONLY [VNx2DF])
284
9f4cbab8
RS		 285;; All SVE vector structure modes.
286(define_mode_iterator SVE_STRUCT [VNx32QI VNx16HI VNx8SI VNx4DI
287 VNx16HF VNx8SF VNx4DF
288 VNx48QI VNx24HI VNx12SI VNx6DI
289 VNx24HF VNx12SF VNx6DF
290 VNx64QI VNx32HI VNx16SI VNx8DI
291 VNx32HF VNx16SF VNx8DF])
292
43cacb12
RS		 293;; All SVE vector modes that have 8-bit or 16-bit elements.
294(define_mode_iterator SVE_BH [VNx16QI VNx8HI VNx8HF])
295
296;; All SVE vector modes that have 8-bit, 16-bit or 32-bit elements.
297(define_mode_iterator SVE_BHS [VNx16QI VNx8HI VNx4SI VNx8HF VNx4SF])
298
95eb5537 299;; SVE integer vector modes that have 8-bit, 16-bit or 32-bit elements.
43cacb12
RS		 300(define_mode_iterator SVE_BHSI [VNx16QI VNx8HI VNx4SI])
301
95eb5537
RS		 302;; SVE integer vector modes that have 16-bit, 32-bit or 64-bit elements.
303(define_mode_iterator SVE_HSDI [VNx8HI VNx4SI VNx2DI])
43cacb12 304
95eb5537 305;; SVE floating-point vector modes that have 16-bit or 32-bit elements.
43cacb12
RS		 306(define_mode_iterator SVE_HSF [VNx8HF VNx4SF])
307
95eb5537
RS		 308;; SVE integer vector modes that have 32-bit or 64-bit elements.
309(define_mode_iterator SVE_SDI [VNx4SI VNx2DI])
310
311;; SVE floating-point vector modes that have 32-bit or 64-bit elements.
312(define_mode_iterator SVE_SDF [VNx4SF VNx2DF])
313
a70965b1
RS		 314;; All SVE vector modes that have 16-bit, 32-bit or 64-bit elements.
315(define_mode_iterator SVE_HSD [VNx8HI VNx4SI VNx2DI VNx8HF VNx4SF VNx2DF])
316
43cacb12
RS		 317;; All SVE vector modes that have 32-bit or 64-bit elements.
318(define_mode_iterator SVE_SD [VNx4SI VNx2DI VNx4SF VNx2DF])
319
bfaa08b7
RS		 320;; All SVE vector modes that have 32-bit elements.
321(define_mode_iterator SVE_S [VNx4SI VNx4SF])
322
323;; All SVE vector modes that have 64-bit elements.
324(define_mode_iterator SVE_D [VNx2DI VNx2DF])
325
43cacb12
RS		 326;; All SVE integer vector modes.
327(define_mode_iterator SVE_I [VNx16QI VNx8HI VNx4SI VNx2DI])
328
329;; All SVE floating-point vector modes.
330(define_mode_iterator SVE_F [VNx8HF VNx4SF VNx2DF])
331
332;; All SVE predicate modes.
333(define_mode_iterator PRED_ALL [VNx16BI VNx8BI VNx4BI VNx2BI])
334
335;; SVE predicate modes that control 8-bit, 16-bit or 32-bit elements.
336(define_mode_iterator PRED_BHS [VNx16BI VNx8BI VNx4BI])
337
43e9d192
IB		 338;; ------------------------------------------------------------------
339;; Unspec enumerations for Advance SIMD. These could well go into
340;; aarch64.md but for their use in int_iterators here.
341;; ------------------------------------------------------------------
342
343(define_c_enum "unspec"
344 [
345 UNSPEC_ASHIFT_SIGNED ; Used in aarch-simd.md.
346 UNSPEC_ASHIFT_UNSIGNED ; Used in aarch64-simd.md.
285398d2 347 UNSPEC_ABS ; Used in aarch64-simd.md.
998eaf97
JG		 348 UNSPEC_FMAX ; Used in aarch64-simd.md.
349 UNSPEC_FMAXNMV ; Used in aarch64-simd.md.
43e9d192 350 UNSPEC_FMAXV ; Used in aarch64-simd.md.
998eaf97
JG		 351 UNSPEC_FMIN ; Used in aarch64-simd.md.
352 UNSPEC_FMINNMV ; Used in aarch64-simd.md.
43e9d192
IB		 353 UNSPEC_FMINV ; Used in aarch64-simd.md.
354 UNSPEC_FADDV ; Used in aarch64-simd.md.
f5156c3e 355 UNSPEC_ADDV ; Used in aarch64-simd.md.
43e9d192
IB		 356 UNSPEC_SMAXV ; Used in aarch64-simd.md.
357 UNSPEC_SMINV ; Used in aarch64-simd.md.
358 UNSPEC_UMAXV ; Used in aarch64-simd.md.
359 UNSPEC_UMINV ; Used in aarch64-simd.md.
360 UNSPEC_SHADD ; Used in aarch64-simd.md.
361 UNSPEC_UHADD ; Used in aarch64-simd.md.
362 UNSPEC_SRHADD ; Used in aarch64-simd.md.
363 UNSPEC_URHADD ; Used in aarch64-simd.md.
364 UNSPEC_SHSUB ; Used in aarch64-simd.md.
365 UNSPEC_UHSUB ; Used in aarch64-simd.md.
366 UNSPEC_SRHSUB ; Used in aarch64-simd.md.
367 UNSPEC_URHSUB ; Used in aarch64-simd.md.
368 UNSPEC_ADDHN ; Used in aarch64-simd.md.
369 UNSPEC_RADDHN ; Used in aarch64-simd.md.
370 UNSPEC_SUBHN ; Used in aarch64-simd.md.
371 UNSPEC_RSUBHN ; Used in aarch64-simd.md.
372 UNSPEC_ADDHN2 ; Used in aarch64-simd.md.
373 UNSPEC_RADDHN2 ; Used in aarch64-simd.md.
374 UNSPEC_SUBHN2 ; Used in aarch64-simd.md.
375 UNSPEC_RSUBHN2 ; Used in aarch64-simd.md.
376 UNSPEC_SQDMULH ; Used in aarch64-simd.md.
377 UNSPEC_SQRDMULH ; Used in aarch64-simd.md.
378 UNSPEC_PMUL ; Used in aarch64-simd.md.
496ea87d 379 UNSPEC_FMULX ; Used in aarch64-simd.md.
43e9d192
IB		 380 UNSPEC_USQADD ; Used in aarch64-simd.md.
381 UNSPEC_SUQADD ; Used in aarch64-simd.md.
382 UNSPEC_SQXTUN ; Used in aarch64-simd.md.
383 UNSPEC_SQXTN ; Used in aarch64-simd.md.
384 UNSPEC_UQXTN ; Used in aarch64-simd.md.
385 UNSPEC_SSRA ; Used in aarch64-simd.md.
386 UNSPEC_USRA ; Used in aarch64-simd.md.
387 UNSPEC_SRSRA ; Used in aarch64-simd.md.
388 UNSPEC_URSRA ; Used in aarch64-simd.md.
389 UNSPEC_SRSHR ; Used in aarch64-simd.md.
390 UNSPEC_URSHR ; Used in aarch64-simd.md.
391 UNSPEC_SQSHLU ; Used in aarch64-simd.md.
392 UNSPEC_SQSHL ; Used in aarch64-simd.md.
393 UNSPEC_UQSHL ; Used in aarch64-simd.md.
394 UNSPEC_SQSHRUN ; Used in aarch64-simd.md.
395 UNSPEC_SQRSHRUN ; Used in aarch64-simd.md.
396 UNSPEC_SQSHRN ; Used in aarch64-simd.md.
397 UNSPEC_UQSHRN ; Used in aarch64-simd.md.
398 UNSPEC_SQRSHRN ; Used in aarch64-simd.md.
399 UNSPEC_UQRSHRN ; Used in aarch64-simd.md.
400 UNSPEC_SSHL ; Used in aarch64-simd.md.
401 UNSPEC_USHL ; Used in aarch64-simd.md.
402 UNSPEC_SRSHL ; Used in aarch64-simd.md.
403 UNSPEC_URSHL ; Used in aarch64-simd.md.
404 UNSPEC_SQRSHL ; Used in aarch64-simd.md.
405 UNSPEC_UQRSHL ; Used in aarch64-simd.md.
43e9d192
IB		 406 UNSPEC_SSLI ; Used in aarch64-simd.md.
407 UNSPEC_USLI ; Used in aarch64-simd.md.
408 UNSPEC_SSRI ; Used in aarch64-simd.md.
409 UNSPEC_USRI ; Used in aarch64-simd.md.
410 UNSPEC_SSHLL ; Used in aarch64-simd.md.
411 UNSPEC_USHLL ; Used in aarch64-simd.md.
412 UNSPEC_ADDP ; Used in aarch64-simd.md.
88b08073 413 UNSPEC_TBL ; Used in vector permute patterns.
9371aecc 414 UNSPEC_TBX ; Used in vector permute patterns.
88b08073 415 UNSPEC_CONCAT ; Used in vector permute patterns.
3f8334a5
RS		 416
417 ;; The following permute unspecs are generated directly by
418 ;; aarch64_expand_vec_perm_const, so any changes to the underlying
419 ;; instructions would need a corresponding change there.
cc4d934f
JG		 420 UNSPEC_ZIP1 ; Used in vector permute patterns.
421 UNSPEC_ZIP2 ; Used in vector permute patterns.
422 UNSPEC_UZP1 ; Used in vector permute patterns.
423 UNSPEC_UZP2 ; Used in vector permute patterns.
424 UNSPEC_TRN1 ; Used in vector permute patterns.
425 UNSPEC_TRN2 ; Used in vector permute patterns.
3f8334a5 426 UNSPEC_EXT ; Used in vector permute patterns.
923fcec3
AL		 427 UNSPEC_REV64 ; Used in vector reverse patterns (permute).
428 UNSPEC_REV32 ; Used in vector reverse patterns (permute).
429 UNSPEC_REV16 ; Used in vector reverse patterns (permute).
3f8334a5 430
5a7a4e80
TB		 431 UNSPEC_AESE ; Used in aarch64-simd.md.
432 UNSPEC_AESD ; Used in aarch64-simd.md.
433 UNSPEC_AESMC ; Used in aarch64-simd.md.
434 UNSPEC_AESIMC ; Used in aarch64-simd.md.
30442682
TB		 435 UNSPEC_SHA1C ; Used in aarch64-simd.md.
436 UNSPEC_SHA1M ; Used in aarch64-simd.md.
437 UNSPEC_SHA1P ; Used in aarch64-simd.md.
438 UNSPEC_SHA1H ; Used in aarch64-simd.md.
439 UNSPEC_SHA1SU0 ; Used in aarch64-simd.md.
440 UNSPEC_SHA1SU1 ; Used in aarch64-simd.md.
b9cb0a44
TB		 441 UNSPEC_SHA256H ; Used in aarch64-simd.md.
442 UNSPEC_SHA256H2 ; Used in aarch64-simd.md.
443 UNSPEC_SHA256SU0 ; Used in aarch64-simd.md.
444 UNSPEC_SHA256SU1 ; Used in aarch64-simd.md.
7baa225d
TB		 445 UNSPEC_PMULL ; Used in aarch64-simd.md.
446 UNSPEC_PMULL2 ; Used in aarch64-simd.md.
668046d1 447 UNSPEC_REV_REGLIST ; Used in aarch64-simd.md.
9c004c58 448 UNSPEC_VEC_SHR ; Used in aarch64-simd.md.
57b26d65
MW		 449 UNSPEC_SQRDMLAH ; Used in aarch64-simd.md.
450 UNSPEC_SQRDMLSH ; Used in aarch64-simd.md.
202d0c11
DS		 451 UNSPEC_FMAXNM ; Used in aarch64-simd.md.
452 UNSPEC_FMINNM ; Used in aarch64-simd.md.
7a08d813
TC		 453 UNSPEC_SDOT ; Used in aarch64-simd.md.
454 UNSPEC_UDOT ; Used in aarch64-simd.md.
27086ea3
MC		 455 UNSPEC_SM3SS1 ; Used in aarch64-simd.md.
456 UNSPEC_SM3TT1A ; Used in aarch64-simd.md.
457 UNSPEC_SM3TT1B ; Used in aarch64-simd.md.
458 UNSPEC_SM3TT2A ; Used in aarch64-simd.md.
459 UNSPEC_SM3TT2B ; Used in aarch64-simd.md.
460 UNSPEC_SM3PARTW1 ; Used in aarch64-simd.md.
461 UNSPEC_SM3PARTW2 ; Used in aarch64-simd.md.
462 UNSPEC_SM4E ; Used in aarch64-simd.md.
463 UNSPEC_SM4EKEY ; Used in aarch64-simd.md.
464 UNSPEC_SHA512H ; Used in aarch64-simd.md.
465 UNSPEC_SHA512H2 ; Used in aarch64-simd.md.
466 UNSPEC_SHA512SU0 ; Used in aarch64-simd.md.
467 UNSPEC_SHA512SU1 ; Used in aarch64-simd.md.
468 UNSPEC_FMLAL ; Used in aarch64-simd.md.
469 UNSPEC_FMLSL ; Used in aarch64-simd.md.
470 UNSPEC_FMLAL2 ; Used in aarch64-simd.md.
471 UNSPEC_FMLSL2 ; Used in aarch64-simd.md.
43cacb12 472 UNSPEC_SEL ; Used in aarch64-sve.md.
898f07b0
RS		 473 UNSPEC_ANDV ; Used in aarch64-sve.md.
474 UNSPEC_IORV ; Used in aarch64-sve.md.
475 UNSPEC_XORV ; Used in aarch64-sve.md.
43cacb12
RS		 476 UNSPEC_ANDF ; Used in aarch64-sve.md.
477 UNSPEC_IORF ; Used in aarch64-sve.md.
478 UNSPEC_XORF ; Used in aarch64-sve.md.
11e9443f
RS		 479 UNSPEC_SMUL_HIGHPART ; Used in aarch64-sve.md.
480 UNSPEC_UMUL_HIGHPART ; Used in aarch64-sve.md.
d45b20a5 481 UNSPEC_COND_FABS ; Used in aarch64-sve.md.
cb18e86d
RS		 482 UNSPEC_COND_FADD ; Used in aarch64-sve.md.
483 UNSPEC_COND_FCMEQ ; Used in aarch64-sve.md.
484 UNSPEC_COND_FCMGE ; Used in aarch64-sve.md.
485 UNSPEC_COND_FCMGT ; Used in aarch64-sve.md.
486 UNSPEC_COND_FCMLE ; Used in aarch64-sve.md.
487 UNSPEC_COND_FCMLT ; Used in aarch64-sve.md.
488 UNSPEC_COND_FCMNE ; Used in aarch64-sve.md.
4a942af6 489 UNSPEC_COND_FCMUO ; Used in aarch64-sve.md.
99361551
RS		 490 UNSPEC_COND_FCVT ; Used in aarch64-sve.md.
491 UNSPEC_COND_FCVTZS ; Used in aarch64-sve.md.
492 UNSPEC_COND_FCVTZU ; Used in aarch64-sve.md.
cb18e86d
RS		 493 UNSPEC_COND_FDIV ; Used in aarch64-sve.md.
494 UNSPEC_COND_FMAXNM ; Used in aarch64-sve.md.
495 UNSPEC_COND_FMINNM ; Used in aarch64-sve.md.
b41d1f6e
RS		 496 UNSPEC_COND_FMLA ; Used in aarch64-sve.md.
497 UNSPEC_COND_FMLS ; Used in aarch64-sve.md.
cb18e86d 498 UNSPEC_COND_FMUL ; Used in aarch64-sve.md.
d45b20a5 499 UNSPEC_COND_FNEG ; Used in aarch64-sve.md.
b41d1f6e
RS		 500 UNSPEC_COND_FNMLA ; Used in aarch64-sve.md.
501 UNSPEC_COND_FNMLS ; Used in aarch64-sve.md.
d45b20a5
RS		 502 UNSPEC_COND_FRINTA ; Used in aarch64-sve.md.
503 UNSPEC_COND_FRINTI ; Used in aarch64-sve.md.
504 UNSPEC_COND_FRINTM ; Used in aarch64-sve.md.
505 UNSPEC_COND_FRINTN ; Used in aarch64-sve.md.
506 UNSPEC_COND_FRINTP ; Used in aarch64-sve.md.
507 UNSPEC_COND_FRINTX ; Used in aarch64-sve.md.
508 UNSPEC_COND_FRINTZ ; Used in aarch64-sve.md.
509 UNSPEC_COND_FSQRT ; Used in aarch64-sve.md.
cb18e86d 510 UNSPEC_COND_FSUB ; Used in aarch64-sve.md.
99361551
RS		 511 UNSPEC_COND_SCVTF ; Used in aarch64-sve.md.
512 UNSPEC_COND_UCVTF ; Used in aarch64-sve.md.
43cacb12 513 UNSPEC_LASTB ; Used in aarch64-sve.md.
9d63f43b
TC		 514 UNSPEC_FCADD90 ; Used in aarch64-simd.md.
515 UNSPEC_FCADD270 ; Used in aarch64-simd.md.
516 UNSPEC_FCMLA ; Used in aarch64-simd.md.
517 UNSPEC_FCMLA90 ; Used in aarch64-simd.md.
518 UNSPEC_FCMLA180 ; Used in aarch64-simd.md.
519 UNSPEC_FCMLA270 ; Used in aarch64-simd.md.
43e9d192
IB		 520])
521
d81cb613
MW		 522;; ------------------------------------------------------------------
523;; Unspec enumerations for Atomics. They are here so that they can be
524;; used in the int_iterators for atomic operations.
525;; ------------------------------------------------------------------
526
527(define_c_enum "unspecv"
528 [
529 UNSPECV_LX ; Represent a load-exclusive.
530 UNSPECV_SX ; Represent a store-exclusive.
531 UNSPECV_LDA ; Represent an atomic load or load-acquire.
532 UNSPECV_STL ; Represent an atomic store or store-release.
533 UNSPECV_ATOMIC_CMPSW ; Represent an atomic compare swap.
534 UNSPECV_ATOMIC_EXCHG ; Represent an atomic exchange.
535 UNSPECV_ATOMIC_CAS ; Represent an atomic CAS.
536 UNSPECV_ATOMIC_SWP ; Represent an atomic SWP.
537 UNSPECV_ATOMIC_OP ; Represent an atomic operation.
d81cb613
MW		 538 UNSPECV_ATOMIC_LDOP_OR ; Represent an atomic load-or
539 UNSPECV_ATOMIC_LDOP_BIC ; Represent an atomic load-bic
540 UNSPECV_ATOMIC_LDOP_XOR ; Represent an atomic load-xor
541 UNSPECV_ATOMIC_LDOP_PLUS ; Represent an atomic load-add
542])
543
43e9d192
IB		 544;; -------------------------------------------------------------------
545;; Mode attributes
546;; -------------------------------------------------------------------
547
548;; In GPI templates, a string like "%<w>0" will expand to "%w0" in the
549;; 32-bit version and "%x0" in the 64-bit version.
550(define_mode_attr w [(QI "w") (HI "w") (SI "w") (DI "x") (SF "s") (DF "d")])
551
db46a2e6
JG		 552;; The size of access, in bytes.
553(define_mode_attr ldst_sz [(SI "4") (DI "8")])
554;; Likewise for load/store pair.
555(define_mode_attr ldpstp_sz [(SI "8") (DI "16")])
556
0d35c5c2 557;; For inequal width int to float conversion
d7f33f07
JW		 558(define_mode_attr w1 [(HF "w") (SF "w") (DF "x")])
559(define_mode_attr w2 [(HF "x") (SF "x") (DF "w")])
0d35c5c2 560
22be0d08
MC		 561;; For width of fp registers in fcvt instruction
562(define_mode_attr fpw [(DI "s") (SI "d")])
563
2b8568fe
KT		 564(define_mode_attr short_mask [(HI "65535") (QI "255")])
565
051d0e2f
SN		 566;; For constraints used in scalar immediate vector moves
567(define_mode_attr hq [(HI "h") (QI "q")])
568
ef22810a
RH		 569;; For doubling width of an integer mode
570(define_mode_attr DWI [(QI "HI") (HI "SI") (SI "DI") (DI "TI")])
571
22be0d08
MC		 572(define_mode_attr fcvt_change_mode [(SI "df") (DI "sf")])
573
574(define_mode_attr FCVT_CHANGE_MODE [(SI "DF") (DI "SF")])
575
43e9d192
IB		 576;; For scalar usage of vector/FP registers
577(define_mode_attr v [(QI "b") (HI "h") (SI "s") (DI "d")
d7f33f07 578 (HF "h") (SF "s") (DF "d")
43e9d192
IB		 579 (V8QI "") (V16QI "")
580 (V4HI "") (V8HI "")
581 (V2SI "") (V4SI "")
582 (V2DI "") (V2SF "")
daef0a8c
JW		 583 (V4SF "") (V4HF "")
584 (V8HF "") (V2DF "")])
43e9d192
IB		 585
586;; For scalar usage of vector/FP registers, narrowing
587(define_mode_attr vn2 [(QI "") (HI "b") (SI "h") (DI "s")
588 (V8QI "") (V16QI "")
589 (V4HI "") (V8HI "")
590 (V2SI "") (V4SI "")
591 (V2DI "") (V2SF "")
592 (V4SF "") (V2DF "")])
593
594;; For scalar usage of vector/FP registers, widening
595(define_mode_attr vw2 [(DI "") (QI "h") (HI "s") (SI "d")
596 (V8QI "") (V16QI "")
597 (V4HI "") (V8HI "")
598 (V2SI "") (V4SI "")
599 (V2DI "") (V2SF "")
600 (V4SF "") (V2DF "")])
601
89fdc743
IB		 602;; Register Type Name and Vector Arrangement Specifier for when
603;; we are doing scalar for DI and SIMD for SI (ignoring all but
604;; lane 0).
605(define_mode_attr rtn [(DI "d") (SI "")])
606(define_mode_attr vas [(DI "") (SI ".2s")])
607
7ac29c0f
RS		 608;; Map a vector to the number of units in it, if the size of the mode
609;; is constant.
610(define_mode_attr nunits [(V8QI "8") (V16QI "16")
611 (V4HI "4") (V8HI "8")
612 (V2SI "2") (V4SI "4")
613 (V2DI "2")
614 (V4HF "4") (V8HF "8")
615 (V2SF "2") (V4SF "4")
616 (V1DF "1") (V2DF "2")
617 (DI "1") (DF "1")])
618
b187677b
RS		 619;; Map a mode to the number of bits in it, if the size of the mode
620;; is constant.
621(define_mode_attr bitsize [(V8QI "64") (V16QI "128")
622 (V4HI "64") (V8HI "128")
623 (V2SI "64") (V4SI "128")
624 (V2DI "128")])
625
22be0d08
MC		 626;; Map a floating point or integer mode to the appropriate register name prefix
627(define_mode_attr s [(HF "h") (SF "s") (DF "d") (SI "s") (DI "d")])
43e9d192
IB		 628
629;; Give the length suffix letter for a sign- or zero-extension.
630(define_mode_attr size [(QI "b") (HI "h") (SI "w")])
631
632;; Give the number of bits in the mode
633(define_mode_attr sizen [(QI "8") (HI "16") (SI "32") (DI "64")])
634
635;; Give the ordinal of the MSB in the mode
315fdae8
RE		 636(define_mode_attr sizem1 [(QI "#7") (HI "#15") (SI "#31") (DI "#63")
637 (HF "#15") (SF "#31") (DF "#63")])
43e9d192 638
95eb5537
RS		 639;; The number of bits in a vector element, or controlled by a predicate
640;; element.
641(define_mode_attr elem_bits [(VNx8HI "16") (VNx4SI "32") (VNx2DI "64")
642 (VNx8HF "16") (VNx4SF "32") (VNx2DF "64")])
643
43e9d192
IB		 644;; Attribute to describe constants acceptable in logical operations
645(define_mode_attr lconst [(SI "K") (DI "L")])
646
43fd192f
MC		 647;; Attribute to describe constants acceptable in logical and operations
648(define_mode_attr lconst2 [(SI "UsO") (DI "UsP")])
649
43e9d192
IB		 650;; Map a mode to a specific constraint character.
651(define_mode_attr cmode [(QI "q") (HI "h") (SI "s") (DI "d")])
652
0603375c
KT		 653;; Map modes to Usg and Usj constraints for SISD right shifts
654(define_mode_attr cmode_simd [(SI "g") (DI "j")])
655
43e9d192
IB		 656(define_mode_attr Vtype [(V8QI "8b") (V16QI "16b")
657 (V4HI "4h") (V8HI "8h")
658 (V2SI "2s") (V4SI "4s")
659 (DI "1d") (DF "1d")
660 (V2DI "2d") (V2SF "2s")
7c369485
AL		 661 (V4SF "4s") (V2DF "2d")
662 (V4HF "4h") (V8HF "8h")])
43e9d192 663
c7f28cd5
KT		 664(define_mode_attr Vrevsuff [(V4HI "16") (V8HI "16") (V2SI "32")
665 (V4SI "32") (V2DI "64")])
666
43e9d192
IB		 667(define_mode_attr Vmtype [(V8QI ".8b") (V16QI ".16b")
668 (V4HI ".4h") (V8HI ".8h")
669 (V2SI ".2s") (V4SI ".4s")
71a11456
AL		 670 (V2DI ".2d") (V4HF ".4h")
671 (V8HF ".8h") (V2SF ".2s")
43e9d192
IB		 672 (V4SF ".4s") (V2DF ".2d")
673 (DI "") (SI "")
674 (HI "") (QI "")
d7f33f07
JW		 675 (TI "") (HF "")
676 (SF "") (DF "")])
43e9d192
IB		 677
678;; Register suffix narrowed modes for VQN.
679(define_mode_attr Vmntype [(V8HI ".8b") (V4SI ".4h")
680 (V2DI ".2s")
681 (DI "") (SI "")
682 (HI "")])
683
684;; Mode-to-individual element type mapping.
43cacb12
RS		 685(define_mode_attr Vetype [(V8QI "b") (V16QI "b") (VNx16QI "b") (VNx16BI "b")
686 (V4HI "h") (V8HI "h") (VNx8HI "h") (VNx8BI "h")
687 (V2SI "s") (V4SI "s") (VNx4SI "s") (VNx4BI "s")
688 (V2DI "d") (VNx2DI "d") (VNx2BI "d")
689 (V4HF "h") (V8HF "h") (VNx8HF "h")
690 (V2SF "s") (V4SF "s") (VNx4SF "s")
691 (V2DF "d") (VNx2DF "d")
d7f33f07 692 (HF "h")
0f686aa9 693 (SF "s") (DF "d")
43e9d192
IB		 694 (QI "b") (HI "h")
695 (SI "s") (DI "d")])
696
9feeafd7
AM		 697;; Like Vetype, but map to types that are a quarter of the element size.
698(define_mode_attr Vetype_fourth [(VNx4SI "b") (VNx2DI "h")])
699
43cacb12
RS		 700;; Equivalent of "size" for a vector element.
701(define_mode_attr Vesize [(VNx16QI "b")
9f4cbab8
RS		 702 (VNx8HI "h") (VNx8HF "h")
703 (VNx4SI "w") (VNx4SF "w")
704 (VNx2DI "d") (VNx2DF "d")
705 (VNx32QI "b") (VNx48QI "b") (VNx64QI "b")
706 (VNx16HI "h") (VNx24HI "h") (VNx32HI "h")
707 (VNx16HF "h") (VNx24HF "h") (VNx32HF "h")
708 (VNx8SI "w") (VNx12SI "w") (VNx16SI "w")
709 (VNx8SF "w") (VNx12SF "w") (VNx16SF "w")
710 (VNx4DI "d") (VNx6DI "d") (VNx8DI "d")
711 (VNx4DF "d") (VNx6DF "d") (VNx8DF "d")])
43cacb12 712
daef0a8c
JW		 713;; Vetype is used everywhere in scheduling type and assembly output,
714;; sometimes they are not the same, for example HF modes on some
715;; instructions. stype is defined to represent scheduling type
716;; more accurately.
717(define_mode_attr stype [(V8QI "b") (V16QI "b") (V4HI "s") (V8HI "s")
718 (V2SI "s") (V4SI "s") (V2DI "d") (V4HF "s")
719 (V8HF "s") (V2SF "s") (V4SF "s") (V2DF "d")
720 (HF "s") (SF "s") (DF "d") (QI "b") (HI "s")
721 (SI "s") (DI "d")])
722
43e9d192
IB		 723;; Mode-to-bitwise operation type mapping.
724(define_mode_attr Vbtype [(V8QI "8b") (V16QI "16b")
725 (V4HI "8b") (V8HI "16b")
726 (V2SI "8b") (V4SI "16b")
7c369485
AL		 727 (V2DI "16b") (V4HF "8b")
728 (V8HF "16b") (V2SF "8b")
46e778c4 729 (V4SF "16b") (V2DF "16b")
fe82d1f2 730 (DI "8b") (DF "8b")
315fdae8 731 (SI "8b") (SF "8b")])
43e9d192
IB		 732
733;; Define element mode for each vector mode.
43cacb12
RS		 734(define_mode_attr VEL [(V8QI "QI") (V16QI "QI") (VNx16QI "QI")
735 (V4HI "HI") (V8HI "HI") (VNx8HI "HI")
736 (V2SI "SI") (V4SI "SI") (VNx4SI "SI")
737 (DI "DI") (V2DI "DI") (VNx2DI "DI")
738 (V4HF "HF") (V8HF "HF") (VNx8HF "HF")
739 (V2SF "SF") (V4SF "SF") (VNx4SF "SF")
740 (DF "DF") (V2DF "DF") (VNx2DF "DF")
741 (SI "SI") (HI "HI")
43e9d192
IB		 742 (QI "QI")])
743
ff03930a 744;; Define element mode for each vector mode (lower case).
43cacb12
RS		 745(define_mode_attr Vel [(V8QI "qi") (V16QI "qi") (VNx16QI "qi")
746 (V4HI "hi") (V8HI "hi") (VNx8HI "hi")
747 (V2SI "si") (V4SI "si") (VNx4SI "si")
748 (DI "di") (V2DI "di") (VNx2DI "di")
749 (V4HF "hf") (V8HF "hf") (VNx8HF "hf")
750 (V2SF "sf") (V4SF "sf") (VNx4SF "sf")
751 (V2DF "df") (DF "df") (VNx2DF "df")
ff03930a
JJ		 752 (SI "si") (HI "hi")
753 (QI "qi")])
754
43cacb12
RS		 755;; Element mode with floating-point values replaced by like-sized integers.
756(define_mode_attr VEL_INT [(VNx16QI "QI")
757 (VNx8HI "HI") (VNx8HF "HI")
758 (VNx4SI "SI") (VNx4SF "SI")
759 (VNx2DI "DI") (VNx2DF "DI")])
760
761;; Gives the mode of the 128-bit lowpart of an SVE vector.
762(define_mode_attr V128 [(VNx16QI "V16QI")
763 (VNx8HI "V8HI") (VNx8HF "V8HF")
764 (VNx4SI "V4SI") (VNx4SF "V4SF")
765 (VNx2DI "V2DI") (VNx2DF "V2DF")])
766
767;; ...and again in lower case.
768(define_mode_attr v128 [(VNx16QI "v16qi")
769 (VNx8HI "v8hi") (VNx8HF "v8hf")
770 (VNx4SI "v4si") (VNx4SF "v4sf")
771 (VNx2DI "v2di") (VNx2DF "v2df")])
772
278821f2
KT		 773;; 64-bit container modes the inner or scalar source mode.
774(define_mode_attr VCOND [(HI "V4HI") (SI "V2SI")
775 (V4HI "V4HI") (V8HI "V4HI")
b7d7d917
TB		 776 (V2SI "V2SI") (V4SI "V2SI")
777 (DI "DI") (V2DI "DI")
778 (V2SF "V2SF") (V4SF "V2SF")
779 (V2DF "DF")])
780
278821f2 781;; 128-bit container modes the inner or scalar source mode.
b7d7d917
TB		 782(define_mode_attr VCONQ [(V8QI "V16QI") (V16QI "V16QI")
783 (V4HI "V8HI") (V8HI "V8HI")
784 (V2SI "V4SI") (V4SI "V4SI")
785 (DI "V2DI") (V2DI "V2DI")
71a11456 786 (V4HF "V8HF") (V8HF "V8HF")
b7d7d917
TB		 787 (V2SF "V2SF") (V4SF "V4SF")
788 (V2DF "V2DF") (SI "V4SI")
789 (HI "V8HI") (QI "V16QI")])
790
43e9d192
IB		 791;; Half modes of all vector modes.
792(define_mode_attr VHALF [(V8QI "V4QI") (V16QI "V8QI")
793 (V4HI "V2HI") (V8HI "V4HI")
794 (V2SI "SI") (V4SI "V2SI")
795 (V2DI "DI") (V2SF "SF")
71a11456
AL		 796 (V4SF "V2SF") (V4HF "V2HF")
797 (V8HF "V4HF") (V2DF "DF")])
43e9d192 798
b1b49824
MC		 799;; Half modes of all vector modes, in lower-case.
800(define_mode_attr Vhalf [(V8QI "v4qi") (V16QI "v8qi")
801 (V4HI "v2hi") (V8HI "v4hi")
41dab855 802 (V8HF "v4hf")
b1b49824
MC		 803 (V2SI "si") (V4SI "v2si")
804 (V2DI "di") (V2SF "sf")
805 (V4SF "v2sf") (V2DF "df")])
806
43e9d192
IB		 807;; Double modes of vector modes.
808(define_mode_attr VDBL [(V8QI "V16QI") (V4HI "V8HI")
71a11456 809 (V4HF "V8HF")
43e9d192
IB		 810 (V2SI "V4SI") (V2SF "V4SF")
811 (SI "V2SI") (DI "V2DI")
812 (DF "V2DF")])
813
922f9c25
AL		 814;; Register suffix for double-length mode.
815(define_mode_attr Vdtype [(V4HF "8h") (V2SF "4s")])
816
43e9d192
IB		 817;; Double modes of vector modes (lower case).
818(define_mode_attr Vdbl [(V8QI "v16qi") (V4HI "v8hi")
7c369485 819 (V4HF "v8hf")
43e9d192 820 (V2SI "v4si") (V2SF "v4sf")
8b033a8a
SN		 821 (SI "v2si") (DI "v2di")
822 (DF "v2df")])
43e9d192 823
b1b49824
MC		 824;; Modes with double-width elements.
825(define_mode_attr VDBLW [(V8QI "V4HI") (V16QI "V8HI")
826 (V4HI "V2SI") (V8HI "V4SI")
827 (V2SI "DI") (V4SI "V2DI")])
828
43e9d192
IB		 829;; Narrowed modes for VDN.
830(define_mode_attr VNARROWD [(V4HI "V8QI") (V2SI "V4HI")
831 (DI "V2SI")])
832
833;; Narrowed double-modes for VQN (Used for XTN).
834(define_mode_attr VNARROWQ [(V8HI "V8QI") (V4SI "V4HI")
835 (V2DI "V2SI")
836 (DI "SI") (SI "HI")
837 (HI "QI")])
838
839;; Narrowed quad-modes for VQN (Used for XTN2).
840(define_mode_attr VNARROWQ2 [(V8HI "V16QI") (V4SI "V8HI")
841 (V2DI "V4SI")])
842
843;; Register suffix narrowed modes for VQN.
844(define_mode_attr Vntype [(V8HI "8b") (V4SI "4h")
845 (V2DI "2s")])
846
847;; Register suffix narrowed modes for VQN.
848(define_mode_attr V2ntype [(V8HI "16b") (V4SI "8h")
849 (V2DI "4s")])
850
851;; Widened modes of vector modes.
43cacb12
RS		 852(define_mode_attr VWIDE [(V8QI "V8HI") (V4HI "V4SI")
853 (V2SI "V2DI") (V16QI "V8HI")
854 (V8HI "V4SI") (V4SI "V2DI")
855 (HI "SI") (SI "DI")
856 (V8HF "V4SF") (V4SF "V2DF")
857 (V4HF "V4SF") (V2SF "V2DF")
858 (VNx8HF "VNx4SF") (VNx4SF "VNx2DF")
859 (VNx16QI "VNx8HI") (VNx8HI "VNx4SI")
860 (VNx4SI "VNx2DI")
861 (VNx16BI "VNx8BI") (VNx8BI "VNx4BI")
862 (VNx4BI "VNx2BI")])
863
864;; Predicate mode associated with VWIDE.
865(define_mode_attr VWIDE_PRED [(VNx8HF "VNx4BI") (VNx4SF "VNx2BI")])
43e9d192 866
03873eb9 867;; Widened modes of vector modes, lowercase
43cacb12
RS		 868(define_mode_attr Vwide [(V2SF "v2df") (V4HF "v4sf")
869 (VNx16QI "vnx8hi") (VNx8HI "vnx4si")
870 (VNx4SI "vnx2di")
871 (VNx8HF "vnx4sf") (VNx4SF "vnx2df")
872 (VNx16BI "vnx8bi") (VNx8BI "vnx4bi")
873 (VNx4BI "vnx2bi")])
03873eb9
AL		 874
875;; Widened mode register suffixes for VD_BHSI/VQW/VQ_HSF.
43e9d192
IB		 876(define_mode_attr Vwtype [(V8QI "8h") (V4HI "4s")
877 (V2SI "2d") (V16QI "8h")
03873eb9
AL		 878 (V8HI "4s") (V4SI "2d")
879 (V8HF "4s") (V4SF "2d")])
43e9d192 880
43cacb12
RS		 881;; SVE vector after widening
882(define_mode_attr Vewtype [(VNx16QI "h")
883 (VNx8HI "s") (VNx8HF "s")
884 (VNx4SI "d") (VNx4SF "d")])
885
43e9d192
IB		 886;; Widened mode register suffixes for VDW/VQW.
887(define_mode_attr Vmwtype [(V8QI ".8h") (V4HI ".4s")
888 (V2SI ".2d") (V16QI ".8h")
889 (V8HI ".4s") (V4SI ".2d")
922f9c25 890 (V4HF ".4s") (V2SF ".2d")
43e9d192
IB		 891 (SI "") (HI "")])
892
03873eb9 893;; Lower part register suffixes for VQW/VQ_HSF.
43e9d192 894(define_mode_attr Vhalftype [(V16QI "8b") (V8HI "4h")
03873eb9
AL		 895 (V4SI "2s") (V8HF "4h")
896 (V4SF "2s")])
43e9d192
IB		 897
898;; Define corresponding core/FP element mode for each vector mode.
43cacb12
RS		 899(define_mode_attr vw [(V8QI "w") (V16QI "w") (VNx16QI "w")
900 (V4HI "w") (V8HI "w") (VNx8HI "w")
901 (V2SI "w") (V4SI "w") (VNx4SI "w")
902 (DI "x") (V2DI "x") (VNx2DI "x")
903 (VNx8HF "h")
904 (V2SF "s") (V4SF "s") (VNx4SF "s")
905 (V2DF "d") (VNx2DF "d")])
43e9d192 906
66adb8eb
JG		 907;; Corresponding core element mode for each vector mode. This is a
908;; variation on <vw> mapping FP modes to GP regs.
43cacb12
RS		 909(define_mode_attr vwcore [(V8QI "w") (V16QI "w") (VNx16QI "w")
910 (V4HI "w") (V8HI "w") (VNx8HI "w")
911 (V2SI "w") (V4SI "w") (VNx4SI "w")
912 (DI "x") (V2DI "x") (VNx2DI "x")
913 (V4HF "w") (V8HF "w") (VNx8HF "w")
914 (V2SF "w") (V4SF "w") (VNx4SF "w")
915 (V2DF "x") (VNx2DF "x")])
66adb8eb 916
43e9d192
IB		 917;; Double vector types for ALLX.
918(define_mode_attr Vallxd [(QI "8b") (HI "4h") (SI "2s")])
919
5f565314
RS		 920;; Mode with floating-point values replaced by like-sized integers.
921(define_mode_attr V_INT_EQUIV [(V8QI "V8QI") (V16QI "V16QI")
922 (V4HI "V4HI") (V8HI "V8HI")
923 (V2SI "V2SI") (V4SI "V4SI")
924 (DI "DI") (V2DI "V2DI")
925 (V4HF "V4HI") (V8HF "V8HI")
926 (V2SF "V2SI") (V4SF "V4SI")
43cacb12 927 (DF "DI") (V2DF "V2DI")
dfe1da23
JW		 928 (SF "SI") (SI "SI")
929 (HF "HI")
43cacb12
RS		 930 (VNx16QI "VNx16QI")
931 (VNx8HI "VNx8HI") (VNx8HF "VNx8HI")
932 (VNx4SI "VNx4SI") (VNx4SF "VNx4SI")
933 (VNx2DI "VNx2DI") (VNx2DF "VNx2DI")
934])
5f565314
RS		 935
936;; Lower case mode with floating-point values replaced by like-sized integers.
937(define_mode_attr v_int_equiv [(V8QI "v8qi") (V16QI "v16qi")
938 (V4HI "v4hi") (V8HI "v8hi")
939 (V2SI "v2si") (V4SI "v4si")
940 (DI "di") (V2DI "v2di")
941 (V4HF "v4hi") (V8HF "v8hi")
942 (V2SF "v2si") (V4SF "v4si")
43cacb12
RS		 943 (DF "di") (V2DF "v2di")
944 (SF "si")
945 (VNx16QI "vnx16qi")
946 (VNx8HI "vnx8hi") (VNx8HF "vnx8hi")
947 (VNx4SI "vnx4si") (VNx4SF "vnx4si")
948 (VNx2DI "vnx2di") (VNx2DF "vnx2di")
949])
950
951;; Floating-point equivalent of selected modes.
a70965b1
RS		 952(define_mode_attr V_FP_EQUIV [(VNx8HI "VNx8HF") (VNx8HF "VNx8HF")
953 (VNx4SI "VNx4SF") (VNx4SF "VNx4SF")
43cacb12 954 (VNx2DI "VNx2DF") (VNx2DF "VNx2DF")])
a70965b1
RS		 955(define_mode_attr v_fp_equiv [(VNx8HI "vnx8hf") (VNx8HF "vnx8hf")
956 (VNx4SI "vnx4sf") (VNx4SF "vnx4sf")
43cacb12 957 (VNx2DI "vnx2df") (VNx2DF "vnx2df")])
70c67693 958
6c553b76
BC		 959;; Mode for vector conditional operations where the comparison has
960;; different type from the lhs.
961(define_mode_attr V_cmp_mixed [(V2SI "V2SF") (V4SI "V4SF")
962 (V2DI "V2DF") (V2SF "V2SI")
963 (V4SF "V4SI") (V2DF "V2DI")])
964
965(define_mode_attr v_cmp_mixed [(V2SI "v2sf") (V4SI "v4sf")
966 (V2DI "v2df") (V2SF "v2si")
967 (V4SF "v4si") (V2DF "v2di")])
968
cb23a30c
JG		 969;; Lower case element modes (as used in shift immediate patterns).
970(define_mode_attr ve_mode [(V8QI "qi") (V16QI "qi")
971 (V4HI "hi") (V8HI "hi")
972 (V2SI "si") (V4SI "si")
973 (DI "di") (V2DI "di")
974 (QI "qi") (HI "hi")
975 (SI "si")])
976
43e9d192
IB		 977;; Vm for lane instructions is restricted to FP_LO_REGS.
978(define_mode_attr vwx [(V4HI "x") (V8HI "x") (HI "x")
979 (V2SI "w") (V4SI "w") (SI "w")])
980
981(define_mode_attr Vendreg [(OI "T") (CI "U") (XI "V")])
982
97755701
AL		 983;; This is both the number of Q-Registers needed to hold the corresponding
984;; opaque large integer mode, and the number of elements touched by the
985;; ld..._lane and st..._lane operations.
43e9d192
IB		 986(define_mode_attr nregs [(OI "2") (CI "3") (XI "4")])
987
0462169c
SN		 988;; Mode for atomic operation suffixes
989(define_mode_attr atomic_sfx
990 [(QI "b") (HI "h") (SI "") (DI "")])
991
3f598afe 992(define_mode_attr fcvt_target [(V2DF "v2di") (V4SF "v4si") (V2SF "v2si")
2644d4d9 993 (V2DI "v2df") (V4SI "v4sf") (V2SI "v2sf")
daef0a8c
JW		 994 (SF "si") (DF "di") (SI "sf") (DI "df")
995 (V4HF "v4hi") (V8HF "v8hi") (V4HI "v4hf")
68ad28c3 996 (V8HI "v8hf") (HF "hi") (HI "hf")])
3f598afe 997(define_mode_attr FCVT_TARGET [(V2DF "V2DI") (V4SF "V4SI") (V2SF "V2SI")
2644d4d9 998 (V2DI "V2DF") (V4SI "V4SF") (V2SI "V2SF")
daef0a8c
JW		 999 (SF "SI") (DF "DI") (SI "SF") (DI "DF")
1000 (V4HF "V4HI") (V8HF "V8HI") (V4HI "V4HF")
68ad28c3 1001 (V8HI "V8HF") (HF "HI") (HI "HF")])
3f598afe 1002
0d35c5c2
VP		 1003
1004;; for the inequal width integer to fp conversions
d7f33f07
JW		 1005(define_mode_attr fcvt_iesize [(HF "di") (SF "di") (DF "si")])
1006(define_mode_attr FCVT_IESIZE [(HF "DI") (SF "DI") (DF "SI")])
42fc9a7f 1007
91bd4114
JG		 1008(define_mode_attr VSWAP_WIDTH [(V8QI "V16QI") (V16QI "V8QI")
1009 (V4HI "V8HI") (V8HI "V4HI")
1010 (V2SI "V4SI") (V4SI "V2SI")
1011 (DI "V2DI") (V2DI "DI")
1012 (V2SF "V4SF") (V4SF "V2SF")
862abc04 1013 (V4HF "V8HF") (V8HF "V4HF")
91bd4114
JG		 1014 (DF "V2DF") (V2DF "DF")])
1015
1016(define_mode_attr vswap_width_name [(V8QI "to_128") (V16QI "to_64")
1017 (V4HI "to_128") (V8HI "to_64")
1018 (V2SI "to_128") (V4SI "to_64")
1019 (DI "to_128") (V2DI "to_64")
862abc04 1020 (V4HF "to_128") (V8HF "to_64")
91bd4114
JG		 1021 (V2SF "to_128") (V4SF "to_64")
1022 (DF "to_128") (V2DF "to_64")])
1023
779aea46 1024;; For certain vector-by-element multiplication instructions we must
6d06971d 1025;; constrain the 16-bit cases to use only V0-V15. This is covered by
779aea46
JG		 1026;; the 'x' constraint. All other modes may use the 'w' constraint.
1027(define_mode_attr h_con [(V2SI "w") (V4SI "w")
1028 (V4HI "x") (V8HI "x")
6d06971d 1029 (V4HF "x") (V8HF "x")
779aea46
JG		 1030 (V2SF "w") (V4SF "w")
1031 (V2DF "w") (DF "w")])
1032
1033;; Defined to 'f' for types whose element type is a float type.
1034(define_mode_attr f [(V8QI "") (V16QI "")
1035 (V4HI "") (V8HI "")
1036 (V2SI "") (V4SI "")
1037 (DI "") (V2DI "")
ab2e8f01 1038 (V4HF "f") (V8HF "f")
779aea46
JG		 1039 (V2SF "f") (V4SF "f")
1040 (V2DF "f") (DF "f")])
1041
0f686aa9
JG		 1042;; Defined to '_fp' for types whose element type is a float type.
1043(define_mode_attr fp [(V8QI "") (V16QI "")
1044 (V4HI "") (V8HI "")
1045 (V2SI "") (V4SI "")
1046 (DI "") (V2DI "")
ab2e8f01 1047 (V4HF "_fp") (V8HF "_fp")
0f686aa9
JG		 1048 (V2SF "_fp") (V4SF "_fp")
1049 (V2DF "_fp") (DF "_fp")
1050 (SF "_fp")])
1051
a9e66678
JG		 1052;; Defined to '_q' for 128-bit types.
1053(define_mode_attr q [(V8QI "") (V16QI "_q")
0f686aa9
JG		 1054 (V4HI "") (V8HI "_q")
1055 (V2SI "") (V4SI "_q")
1056 (DI "") (V2DI "_q")
71a11456 1057 (V4HF "") (V8HF "_q")
0f686aa9
JG		 1058 (V2SF "") (V4SF "_q")
1059 (V2DF "_q")
d7f33f07 1060 (QI "") (HI "") (SI "") (DI "") (HF "") (SF "") (DF "")])
a9e66678 1061
92835317
TB		 1062(define_mode_attr vp [(V8QI "v") (V16QI "v")
1063 (V4HI "v") (V8HI "v")
1064 (V2SI "p") (V4SI "v")
703bbcdf
JW		 1065 (V2DI "p") (V2DF "p")
1066 (V2SF "p") (V4SF "v")
1067 (V4HF "v") (V8HF "v")])
92835317 1068
9feeafd7
AM		 1069(define_mode_attr vsi2qi [(V2SI "v8qi") (V4SI "v16qi")
1070 (VNx4SI "vnx16qi") (VNx2DI "vnx8hi")])
1071(define_mode_attr VSI2QI [(V2SI "V8QI") (V4SI "V16QI")
1072 (VNx4SI "VNx16QI") (VNx2DI "VNx8HI")])
5e32e83b 1073
7a08d813
TC		 1074
1075;; Register suffix for DOTPROD input types from the return type.
1076(define_mode_attr Vdottype [(V2SI "8b") (V4SI "16b")])
1077
cd78b3dd 1078;; Sum of lengths of instructions needed to move vector registers of a mode.
668046d1
DS		 1079(define_mode_attr insn_count [(OI "8") (CI "12") (XI "16")])
1080
1b1e81f8
JW		 1081;; -fpic small model GOT reloc modifers: gotpage_lo15/lo14 for ILP64/32.
1082;; No need of iterator for -fPIC as it use got_lo12 for both modes.
1083(define_mode_attr got_modifier [(SI "gotpage_lo14") (DI "gotpage_lo15")])
1084
27086ea3
MC		 1085;; Width of 2nd and 3rd arguments to fp16 vector multiply add/sub
1086(define_mode_attr VFMLA_W [(V2SF "V4HF") (V4SF "V8HF")])
1087
1088(define_mode_attr VFMLA_SEL_W [(V2SF "V2HF") (V4SF "V4HF")])
1089
1090(define_mode_attr f16quad [(V2SF "") (V4SF "q")])
1091
1092(define_code_attr f16mac [(plus "a") (minus "s")])
1093
8544ed6e
KT		 1094;; Map smax to smin and umax to umin.
1095(define_code_attr max_opp [(smax "smin") (umax "umin")])
1096
a9fad8fe
AM		 1097;; Same as above, but louder.
1098(define_code_attr MAX_OPP [(smax "SMIN") (umax "UMIN")])
1099
9f4cbab8
RS		 1100;; The number of subvectors in an SVE_STRUCT.
1101(define_mode_attr vector_count [(VNx32QI "2") (VNx16HI "2")
1102 (VNx8SI "2") (VNx4DI "2")
1103 (VNx16HF "2") (VNx8SF "2") (VNx4DF "2")
1104 (VNx48QI "3") (VNx24HI "3")
1105 (VNx12SI "3") (VNx6DI "3")
1106 (VNx24HF "3") (VNx12SF "3") (VNx6DF "3")
1107 (VNx64QI "4") (VNx32HI "4")
1108 (VNx16SI "4") (VNx8DI "4")
1109 (VNx32HF "4") (VNx16SF "4") (VNx8DF "4")])
1110
1111;; The number of instruction bytes needed for an SVE_STRUCT move. This is
1112;; equal to vector_count * 4.
1113(define_mode_attr insn_length [(VNx32QI "8") (VNx16HI "8")
1114 (VNx8SI "8") (VNx4DI "8")
1115 (VNx16HF "8") (VNx8SF "8") (VNx4DF "8")
1116 (VNx48QI "12") (VNx24HI "12")
1117 (VNx12SI "12") (VNx6DI "12")
1118 (VNx24HF "12") (VNx12SF "12") (VNx6DF "12")
1119 (VNx64QI "16") (VNx32HI "16")
1120 (VNx16SI "16") (VNx8DI "16")
1121 (VNx32HF "16") (VNx16SF "16") (VNx8DF "16")])
1122
1123;; The type of a subvector in an SVE_STRUCT.
1124(define_mode_attr VSINGLE [(VNx32QI "VNx16QI")
1125 (VNx16HI "VNx8HI") (VNx16HF "VNx8HF")
1126 (VNx8SI "VNx4SI") (VNx8SF "VNx4SF")
1127 (VNx4DI "VNx2DI") (VNx4DF "VNx2DF")
1128 (VNx48QI "VNx16QI")
1129 (VNx24HI "VNx8HI") (VNx24HF "VNx8HF")
1130 (VNx12SI "VNx4SI") (VNx12SF "VNx4SF")
1131 (VNx6DI "VNx2DI") (VNx6DF "VNx2DF")
1132 (VNx64QI "VNx16QI")
1133 (VNx32HI "VNx8HI") (VNx32HF "VNx8HF")
1134 (VNx16SI "VNx4SI") (VNx16SF "VNx4SF")
1135 (VNx8DI "VNx2DI") (VNx8DF "VNx2DF")])
1136
1137;; ...and again in lower case.
1138(define_mode_attr vsingle [(VNx32QI "vnx16qi")
1139 (VNx16HI "vnx8hi") (VNx16HF "vnx8hf")
1140 (VNx8SI "vnx4si") (VNx8SF "vnx4sf")
1141 (VNx4DI "vnx2di") (VNx4DF "vnx2df")
1142 (VNx48QI "vnx16qi")
1143 (VNx24HI "vnx8hi") (VNx24HF "vnx8hf")
1144 (VNx12SI "vnx4si") (VNx12SF "vnx4sf")
1145 (VNx6DI "vnx2di") (VNx6DF "vnx2df")
1146 (VNx64QI "vnx16qi")
1147 (VNx32HI "vnx8hi") (VNx32HF "vnx8hf")
1148 (VNx16SI "vnx4si") (VNx16SF "vnx4sf")
1149 (VNx8DI "vnx2di") (VNx8DF "vnx2df")])
1150
1151;; The predicate mode associated with an SVE data mode. For structure modes
1152;; this is equivalent to the <VPRED> of the subvector mode.
43cacb12
RS		 1153(define_mode_attr VPRED [(VNx16QI "VNx16BI")
1154 (VNx8HI "VNx8BI") (VNx8HF "VNx8BI")
1155 (VNx4SI "VNx4BI") (VNx4SF "VNx4BI")
9f4cbab8
RS		 1156 (VNx2DI "VNx2BI") (VNx2DF "VNx2BI")
1157 (VNx32QI "VNx16BI")
1158 (VNx16HI "VNx8BI") (VNx16HF "VNx8BI")
1159 (VNx8SI "VNx4BI") (VNx8SF "VNx4BI")
1160 (VNx4DI "VNx2BI") (VNx4DF "VNx2BI")
1161 (VNx48QI "VNx16BI")
1162 (VNx24HI "VNx8BI") (VNx24HF "VNx8BI")
1163 (VNx12SI "VNx4BI") (VNx12SF "VNx4BI")
1164 (VNx6DI "VNx2BI") (VNx6DF "VNx2BI")
1165 (VNx64QI "VNx16BI")
1166 (VNx32HI "VNx8BI") (VNx32HF "VNx8BI")
1167 (VNx16SI "VNx4BI") (VNx16SF "VNx4BI")
1168 (VNx8DI "VNx2BI") (VNx8DF "VNx2BI")])
43cacb12
RS		 1169
1170;; ...and again in lower case.
1171(define_mode_attr vpred [(VNx16QI "vnx16bi")
1172 (VNx8HI "vnx8bi") (VNx8HF "vnx8bi")
1173 (VNx4SI "vnx4bi") (VNx4SF "vnx4bi")
9f4cbab8
RS		 1174 (VNx2DI "vnx2bi") (VNx2DF "vnx2bi")
1175 (VNx32QI "vnx16bi")
1176 (VNx16HI "vnx8bi") (VNx16HF "vnx8bi")
1177 (VNx8SI "vnx4bi") (VNx8SF "vnx4bi")
1178 (VNx4DI "vnx2bi") (VNx4DF "vnx2bi")
1179 (VNx48QI "vnx16bi")
1180 (VNx24HI "vnx8bi") (VNx24HF "vnx8bi")
1181 (VNx12SI "vnx4bi") (VNx12SF "vnx4bi")
1182 (VNx6DI "vnx2bi") (VNx6DF "vnx2bi")
1183 (VNx64QI "vnx16bi")
1184 (VNx32HI "vnx8bi") (VNx32HF "vnx4bi")
1185 (VNx16SI "vnx4bi") (VNx16SF "vnx4bi")
1186 (VNx8DI "vnx2bi") (VNx8DF "vnx2bi")])
43cacb12 1187
9d63f43b
TC		 1188;; On AArch64 the By element instruction doesn't have a 2S variant.
1189;; However because the instruction always selects a pair of values
1190;; The normal 3SAME instruction can be used here instead.
1191(define_mode_attr FCMLA_maybe_lane [(V2SF "<Vtype>") (V4SF "<Vetype>[%4]")
1192 (V4HF "<Vetype>[%4]") (V8HF "<Vetype>[%4]")
1193 ])
1194
34467289
RS		 1195;; The number of bytes controlled by a predicate
1196(define_mode_attr data_bytes [(VNx16BI "1") (VNx8BI "2")
1197 (VNx4BI "4") (VNx2BI "8")])
1198
43e9d192
IB		 1199;; -------------------------------------------------------------------
1200;; Code Iterators
1201;; -------------------------------------------------------------------
1202
1203;; This code iterator allows the various shifts supported on the core
1204(define_code_iterator SHIFT [ashift ashiftrt lshiftrt rotatert])
1205
1206;; This code iterator allows the shifts supported in arithmetic instructions
1207(define_code_iterator ASHIFT [ashift ashiftrt lshiftrt])
1208
462e6f9a
ST		 1209(define_code_iterator SHIFTRT [ashiftrt lshiftrt])
1210
43e9d192
IB		 1211;; Code iterator for logical operations
1212(define_code_iterator LOGICAL [and ior xor])
1213
43cacb12
RS		 1214;; LOGICAL without AND.
1215(define_code_iterator LOGICAL_OR [ior xor])
1216
84be6032
AL		 1217;; Code iterator for logical operations whose :nlogical works on SIMD registers.
1218(define_code_iterator NLOGICAL [and ior])
1219
3204ac98
KT		 1220;; Code iterator for unary negate and bitwise complement.
1221(define_code_iterator NEG_NOT [neg not])
1222
43e9d192
IB		 1223;; Code iterator for sign/zero extension
1224(define_code_iterator ANY_EXTEND [sign_extend zero_extend])
1225
1226;; All division operations (signed/unsigned)
1227(define_code_iterator ANY_DIV [div udiv])
1228
1229;; Code iterator for sign/zero extraction
1230(define_code_iterator ANY_EXTRACT [sign_extract zero_extract])
1231
1232;; Code iterator for equality comparisons
1233(define_code_iterator EQL [eq ne])
1234
1235;; Code iterator for less-than and greater/equal-to
1236(define_code_iterator LTGE [lt ge])
1237
1238;; Iterator for __sync_<op> operations that where the operation can be
1239;; represented directly RTL. This is all of the sync operations bar
1240;; nand.
0462169c 1241(define_code_iterator atomic_op [plus minus ior xor and])
43e9d192
IB		 1242
1243;; Iterator for integer conversions
1244(define_code_iterator FIXUORS [fix unsigned_fix])
1245
1709ff9b
JG		 1246;; Iterator for float conversions
1247(define_code_iterator FLOATUORS [float unsigned_float])
1248
43e9d192
IB		 1249;; Code iterator for variants of vector max and min.
1250(define_code_iterator MAXMIN [smax smin umax umin])
1251
998eaf97
JG		 1252(define_code_iterator FMAXMIN [smax smin])
1253
8544ed6e
KT		 1254;; Signed and unsigned max operations.
1255(define_code_iterator USMAX [smax umax])
1256
dd550c99 1257;; Code iterator for plus and minus.
43e9d192
IB		 1258(define_code_iterator ADDSUB [plus minus])
1259
1260;; Code iterator for variants of vector saturating binary ops.
1261(define_code_iterator BINQOPS [ss_plus us_plus ss_minus us_minus])
1262
1263;; Code iterator for variants of vector saturating unary ops.
1264(define_code_iterator UNQOPS [ss_neg ss_abs])
1265
1266;; Code iterator for signed variants of vector saturating binary ops.
1267(define_code_iterator SBINQOPS [ss_plus ss_minus])
1268
889b9412
JG		 1269;; Comparison operators for <F>CM.
1270(define_code_iterator COMPARISONS [lt le eq ge gt])
1271
1272;; Unsigned comparison operators.
1273(define_code_iterator UCOMPARISONS [ltu leu geu gtu])
1274
75dd5ace
JG		 1275;; Unsigned comparison operators.
1276(define_code_iterator FAC_COMPARISONS [lt le ge gt])
1277
43cacb12 1278;; SVE integer unary operations.
69c5fdcf 1279(define_code_iterator SVE_INT_UNARY [abs neg not popcount])
43cacb12 1280
a08acce8 1281;; SVE integer binary operations.
6c4fd4a9 1282(define_code_iterator SVE_INT_BINARY [plus minus mult smax umax smin umin
9d4ac06e
RS		 1283 and ior xor])
1284
a08acce8 1285;; SVE integer binary division operations.
c38f7319
RS		 1286(define_code_iterator SVE_INT_BINARY_SD [div udiv])
1287
740c1ed7
RS		 1288;; SVE floating-point operations with an unpredicated all-register form.
1289(define_code_iterator SVE_UNPRED_FP_BINARY [plus minus mult])
1290
f22d7973
RS		 1291;; SVE integer comparisons.
1292(define_code_iterator SVE_INT_CMP [lt le eq ne ge gt ltu leu geu gtu])
1293
43e9d192
IB		 1294;; -------------------------------------------------------------------
1295;; Code Attributes
1296;; -------------------------------------------------------------------
1297;; Map rtl objects to optab names
1298(define_code_attr optab [(ashift "ashl")
1299 (ashiftrt "ashr")
1300 (lshiftrt "lshr")
1301 (rotatert "rotr")
1302 (sign_extend "extend")
1303 (zero_extend "zero_extend")
1304 (sign_extract "extv")
1305 (zero_extract "extzv")
384be29f
JG		 1306 (fix "fix")
1307 (unsigned_fix "fixuns")
1709ff9b
JG		 1308 (float "float")
1309 (unsigned_float "floatuns")
43cacb12 1310 (popcount "popcount")
43e9d192
IB		 1311 (and "and")
1312 (ior "ior")
1313 (xor "xor")
1314 (not "one_cmpl")
1315 (neg "neg")
1316 (plus "add")
1317 (minus "sub")
6c4fd4a9 1318 (mult "mul")
c38f7319
RS		 1319 (div "div")
1320 (udiv "udiv")
43e9d192
IB		 1321 (ss_plus "qadd")
1322 (us_plus "qadd")
1323 (ss_minus "qsub")
1324 (us_minus "qsub")
1325 (ss_neg "qneg")
1326 (ss_abs "qabs")
43cacb12
RS		 1327 (smin "smin")
1328 (smax "smax")
1329 (umin "umin")
1330 (umax "umax")
43e9d192
IB		 1331 (eq "eq")
1332 (ne "ne")
1333 (lt "lt")
889b9412
JG		 1334 (ge "ge")
1335 (le "le")
1336 (gt "gt")
1337 (ltu "ltu")
1338 (leu "leu")
1339 (geu "geu")
43cacb12 1340 (gtu "gtu")
d45b20a5 1341 (abs "abs")])
889b9412
JG		 1342
1343;; For comparison operators we use the FCM* and CM* instructions.
1344;; As there are no CMLE or CMLT instructions which act on 3 vector
1345;; operands, we must use CMGE or CMGT and swap the order of the
1346;; source operands.
1347
1348(define_code_attr n_optab [(lt "gt") (le "ge") (eq "eq") (ge "ge") (gt "gt")
1349 (ltu "hi") (leu "hs") (geu "hs") (gtu "hi")])
1350(define_code_attr cmp_1 [(lt "2") (le "2") (eq "1") (ge "1") (gt "1")
1351 (ltu "2") (leu "2") (geu "1") (gtu "1")])
1352(define_code_attr cmp_2 [(lt "1") (le "1") (eq "2") (ge "2") (gt "2")
1353 (ltu "1") (leu "1") (geu "2") (gtu "2")])
1354
1355(define_code_attr CMP [(lt "LT") (le "LE") (eq "EQ") (ge "GE") (gt "GT")
714e1b3b
KT		 1356 (ltu "LTU") (leu "LEU") (ne "NE") (geu "GEU")
1357 (gtu "GTU")])
43e9d192 1358
f22d7973
RS		 1359;; The AArch64 condition associated with an rtl comparison code.
1360(define_code_attr cmp_op [(lt "lt")
1361 (le "le")
1362 (eq "eq")
1363 (ne "ne")
1364 (ge "ge")
1365 (gt "gt")
1366 (ltu "lo")
1367 (leu "ls")
1368 (geu "hs")
1369 (gtu "hi")])
1370
384be29f
JG		 1371(define_code_attr fix_trunc_optab [(fix "fix_trunc")
1372 (unsigned_fix "fixuns_trunc")])
1373
43e9d192
IB		 1374;; Optab prefix for sign/zero-extending operations
1375(define_code_attr su_optab [(sign_extend "") (zero_extend "u")
1376 (div "") (udiv "u")
1377 (fix "") (unsigned_fix "u")
1709ff9b 1378 (float "s") (unsigned_float "u")
43e9d192
IB		 1379 (ss_plus "s") (us_plus "u")
1380 (ss_minus "s") (us_minus "u")])
1381
1382;; Similar for the instruction mnemonics
1383(define_code_attr shift [(ashift "lsl") (ashiftrt "asr")
1384 (lshiftrt "lsr") (rotatert "ror")])
1385
462e6f9a
ST		 1386;; Op prefix for shift right and accumulate.
1387(define_code_attr sra_op [(ashiftrt "s") (lshiftrt "u")])
1388
43e9d192
IB		 1389;; Map shift operators onto underlying bit-field instructions
1390(define_code_attr bfshift [(ashift "ubfiz") (ashiftrt "sbfx")
1391 (lshiftrt "ubfx") (rotatert "extr")])
1392
1393;; Logical operator instruction mnemonics
1394(define_code_attr logical [(and "and") (ior "orr") (xor "eor")])
1395
3204ac98
KT		 1396;; Operation names for negate and bitwise complement.
1397(define_code_attr neg_not_op [(neg "neg") (not "not")])
1398
43cacb12 1399;; Similar, but when the second operand is inverted.
43e9d192
IB		 1400(define_code_attr nlogical [(and "bic") (ior "orn") (xor "eon")])
1401
43cacb12
RS		 1402;; Similar, but when both operands are inverted.
1403(define_code_attr logical_nn [(and "nor") (ior "nand")])
1404
43e9d192
IB		 1405;; Sign- or zero-extending data-op
1406(define_code_attr su [(sign_extend "s") (zero_extend "u")
1407 (sign_extract "s") (zero_extract "u")
1408 (fix "s") (unsigned_fix "u")
998eaf97
JG		 1409 (div "s") (udiv "u")
1410 (smax "s") (umax "u")
1411 (smin "s") (umin "u")])
43e9d192 1412
43cacb12
RS		 1413;; Whether a shift is left or right.
1414(define_code_attr lr [(ashift "l") (ashiftrt "r") (lshiftrt "r")])
1415
096e8448
JW		 1416;; Emit conditional branch instructions.
1417(define_code_attr bcond [(eq "beq") (ne "bne") (lt "bne") (ge "beq")])
1418
43e9d192
IB		 1419;; Emit cbz/cbnz depending on comparison type.
1420(define_code_attr cbz [(eq "cbz") (ne "cbnz") (lt "cbnz") (ge "cbz")])
1421
973d2e01
TP		 1422;; Emit inverted cbz/cbnz depending on comparison type.
1423(define_code_attr inv_cb [(eq "cbnz") (ne "cbz") (lt "cbz") (ge "cbnz")])
1424
43e9d192
IB		 1425;; Emit tbz/tbnz depending on comparison type.
1426(define_code_attr tbz [(eq "tbz") (ne "tbnz") (lt "tbnz") (ge "tbz")])
1427
973d2e01
TP		 1428;; Emit inverted tbz/tbnz depending on comparison type.
1429(define_code_attr inv_tb [(eq "tbnz") (ne "tbz") (lt "tbz") (ge "tbnz")])
1430
43e9d192 1431;; Max/min attributes.
998eaf97
JG		 1432(define_code_attr maxmin [(smax "max")
1433 (smin "min")
1434 (umax "max")
1435 (umin "min")])
43e9d192
IB		 1436
1437;; MLA/MLS attributes.
1438(define_code_attr as [(ss_plus "a") (ss_minus "s")])
1439
0462169c
SN		 1440;; Atomic operations
1441(define_code_attr atomic_optab
1442 [(ior "or") (xor "xor") (and "and") (plus "add") (minus "sub")])
1443
1444(define_code_attr atomic_op_operand
1445 [(ior "aarch64_logical_operand")
1446 (xor "aarch64_logical_operand")
1447 (and "aarch64_logical_operand")
1448 (plus "aarch64_plus_operand")
1449 (minus "aarch64_plus_operand")])
43e9d192 1450
356c32e2
MW		 1451;; Constants acceptable for atomic operations.
1452;; This definition must appear in this file before the iterators it refers to.
1453(define_code_attr const_atomic
1454 [(plus "IJ") (minus "IJ")
1455 (xor "<lconst_atomic>") (ior "<lconst_atomic>")
1456 (and "<lconst_atomic>")])
1457
1458;; Attribute to describe constants acceptable in atomic logical operations
1459(define_mode_attr lconst_atomic [(QI "K") (HI "K") (SI "K") (DI "L")])
1460
43cacb12
RS		 1461;; The integer SVE instruction that implements an rtx code.
1462(define_code_attr sve_int_op [(plus "add")
9d4ac06e 1463 (minus "sub")
6c4fd4a9 1464 (mult "mul")
c38f7319
RS		 1465 (div "sdiv")
1466 (udiv "udiv")
69c5fdcf 1467 (abs "abs")
43cacb12
RS		 1468 (neg "neg")
1469 (smin "smin")
1470 (smax "smax")
1471 (umin "umin")
1472 (umax "umax")
1473 (and "and")
1474 (ior "orr")
1475 (xor "eor")
1476 (not "not")
1477 (popcount "cnt")])
1478
a08acce8
RH		 1479(define_code_attr sve_int_op_rev [(plus "add")
1480 (minus "subr")
1481 (mult "mul")
1482 (div "sdivr")
1483 (udiv "udivr")
1484 (smin "smin")
1485 (smax "smax")
1486 (umin "umin")
1487 (umax "umax")
1488 (and "and")
1489 (ior "orr")
1490 (xor "eor")])
1491
43cacb12
RS		 1492;; The floating-point SVE instruction that implements an rtx code.
1493(define_code_attr sve_fp_op [(plus "fadd")
740c1ed7 1494 (minus "fsub")
d45b20a5 1495 (mult "fmul")])
43cacb12 1496
f22d7973
RS		 1497;; The SVE immediate constraint to use for an rtl code.
1498(define_code_attr sve_imm_con [(eq "vsc")
1499 (ne "vsc")
1500 (lt "vsc")
1501 (ge "vsc")
1502 (le "vsc")
1503 (gt "vsc")
1504 (ltu "vsd")
1505 (leu "vsd")
1506 (geu "vsd")
1507 (gtu "vsd")])
1508
43e9d192
IB		 1509;; -------------------------------------------------------------------
1510;; Int Iterators.
1511;; -------------------------------------------------------------------
75add2d0
KT		 1512
1513;; The unspec codes for the SABAL, UABAL AdvancedSIMD instructions.
1514(define_int_iterator ABAL [UNSPEC_SABAL UNSPEC_UABAL])
1515
1516;; The unspec codes for the SABDL2, UABDL2 AdvancedSIMD instructions.
1517(define_int_iterator ABDL2 [UNSPEC_SABDL2 UNSPEC_UABDL2])
1518
1519;; The unspec codes for the SADALP, UADALP AdvancedSIMD instructions.
1520(define_int_iterator ADALP [UNSPEC_SADALP UNSPEC_UADALP])
1521
43e9d192
IB		 1522(define_int_iterator MAXMINV [UNSPEC_UMAXV UNSPEC_UMINV
1523 UNSPEC_SMAXV UNSPEC_SMINV])
1524
998eaf97
JG		 1525(define_int_iterator FMAXMINV [UNSPEC_FMAXV UNSPEC_FMINV
1526 UNSPEC_FMAXNMV UNSPEC_FMINNMV])
43e9d192 1527
43cacb12
RS		 1528(define_int_iterator LOGICALF [UNSPEC_ANDF UNSPEC_IORF UNSPEC_XORF])
1529
43e9d192
IB		 1530(define_int_iterator HADDSUB [UNSPEC_SHADD UNSPEC_UHADD
1531 UNSPEC_SRHADD UNSPEC_URHADD
1532 UNSPEC_SHSUB UNSPEC_UHSUB
1533 UNSPEC_SRHSUB UNSPEC_URHSUB])
1534
42addb5a
RS		 1535(define_int_iterator HADD [UNSPEC_SHADD UNSPEC_UHADD])
1536
1537(define_int_iterator RHADD [UNSPEC_SRHADD UNSPEC_URHADD])
1538
7a08d813 1539(define_int_iterator DOTPROD [UNSPEC_SDOT UNSPEC_UDOT])
43e9d192
IB		 1540
1541(define_int_iterator ADDSUBHN [UNSPEC_ADDHN UNSPEC_RADDHN
1542 UNSPEC_SUBHN UNSPEC_RSUBHN])
1543
1544(define_int_iterator ADDSUBHN2 [UNSPEC_ADDHN2 UNSPEC_RADDHN2
1545 UNSPEC_SUBHN2 UNSPEC_RSUBHN2])
1546
1efafef3
TC		 1547(define_int_iterator FMAXMIN_UNS [UNSPEC_FMAX UNSPEC_FMIN
1548 UNSPEC_FMAXNM UNSPEC_FMINNM])
202d0c11 1549
8fc16d72
ST		 1550(define_int_iterator PAUTH_LR_SP [UNSPEC_PACIASP UNSPEC_AUTIASP
1551 UNSPEC_PACIBSP UNSPEC_AUTIBSP])
db58fd89 1552
8fc16d72
ST		 1553(define_int_iterator PAUTH_17_16 [UNSPEC_PACIA1716 UNSPEC_AUTIA1716
1554 UNSPEC_PACIB1716 UNSPEC_AUTIB1716])
db58fd89 1555
43e9d192
IB		 1556(define_int_iterator VQDMULH [UNSPEC_SQDMULH UNSPEC_SQRDMULH])
1557
1558(define_int_iterator USSUQADD [UNSPEC_SUQADD UNSPEC_USQADD])
1559
1560(define_int_iterator SUQMOVN [UNSPEC_SQXTN UNSPEC_UQXTN])
1561
1562(define_int_iterator VSHL [UNSPEC_SSHL UNSPEC_USHL
1563 UNSPEC_SRSHL UNSPEC_URSHL])
1564
1565(define_int_iterator VSHLL [UNSPEC_SSHLL UNSPEC_USHLL])
1566
1567(define_int_iterator VQSHL [UNSPEC_SQSHL UNSPEC_UQSHL
1568 UNSPEC_SQRSHL UNSPEC_UQRSHL])
1569
1570(define_int_iterator VSRA [UNSPEC_SSRA UNSPEC_USRA
1571 UNSPEC_SRSRA UNSPEC_URSRA])
1572
1573(define_int_iterator VSLRI [UNSPEC_SSLI UNSPEC_USLI
1574 UNSPEC_SSRI UNSPEC_USRI])
1575
1576
1577(define_int_iterator VRSHR_N [UNSPEC_SRSHR UNSPEC_URSHR])
1578
1579(define_int_iterator VQSHL_N [UNSPEC_SQSHLU UNSPEC_SQSHL UNSPEC_UQSHL])
1580
1581(define_int_iterator VQSHRN_N [UNSPEC_SQSHRUN UNSPEC_SQRSHRUN
1582 UNSPEC_SQSHRN UNSPEC_UQSHRN
1583 UNSPEC_SQRSHRN UNSPEC_UQRSHRN])
1584
57b26d65
MW		 1585(define_int_iterator SQRDMLH_AS [UNSPEC_SQRDMLAH UNSPEC_SQRDMLSH])
1586
cc4d934f
JG		 1587(define_int_iterator PERMUTE [UNSPEC_ZIP1 UNSPEC_ZIP2
1588 UNSPEC_TRN1 UNSPEC_TRN2
1589 UNSPEC_UZP1 UNSPEC_UZP2])
43e9d192 1590
43cacb12
RS		 1591(define_int_iterator OPTAB_PERMUTE [UNSPEC_ZIP1 UNSPEC_ZIP2
1592 UNSPEC_UZP1 UNSPEC_UZP2])
1593
923fcec3
AL		 1594(define_int_iterator REVERSE [UNSPEC_REV64 UNSPEC_REV32 UNSPEC_REV16])
1595
42fc9a7f 1596(define_int_iterator FRINT [UNSPEC_FRINTZ UNSPEC_FRINTP UNSPEC_FRINTM
0659ce6f
JG		 1597 UNSPEC_FRINTN UNSPEC_FRINTI UNSPEC_FRINTX
1598 UNSPEC_FRINTA])
42fc9a7f
JG		 1599
1600(define_int_iterator FCVT [UNSPEC_FRINTZ UNSPEC_FRINTP UNSPEC_FRINTM
ce966824 1601 UNSPEC_FRINTA UNSPEC_FRINTN])
42fc9a7f 1602
3f598afe
JW		 1603(define_int_iterator FCVT_F2FIXED [UNSPEC_FCVTZS UNSPEC_FCVTZU])
1604(define_int_iterator FCVT_FIXED2F [UNSPEC_SCVTF UNSPEC_UCVTF])
1605
5d357f26
KT		 1606(define_int_iterator CRC [UNSPEC_CRC32B UNSPEC_CRC32H UNSPEC_CRC32W
1607 UNSPEC_CRC32X UNSPEC_CRC32CB UNSPEC_CRC32CH
1608 UNSPEC_CRC32CW UNSPEC_CRC32CX])
1609
5a7a4e80
TB		 1610(define_int_iterator CRYPTO_AES [UNSPEC_AESE UNSPEC_AESD])
1611(define_int_iterator CRYPTO_AESMC [UNSPEC_AESMC UNSPEC_AESIMC])
1612
30442682
TB		 1613(define_int_iterator CRYPTO_SHA1 [UNSPEC_SHA1C UNSPEC_SHA1M UNSPEC_SHA1P])
1614
b9cb0a44
TB		 1615(define_int_iterator CRYPTO_SHA256 [UNSPEC_SHA256H UNSPEC_SHA256H2])
1616
27086ea3
MC		 1617(define_int_iterator CRYPTO_SHA512 [UNSPEC_SHA512H UNSPEC_SHA512H2])
1618
1619(define_int_iterator CRYPTO_SM3TT [UNSPEC_SM3TT1A UNSPEC_SM3TT1B
1620 UNSPEC_SM3TT2A UNSPEC_SM3TT2B])
1621
1622(define_int_iterator CRYPTO_SM3PART [UNSPEC_SM3PARTW1 UNSPEC_SM3PARTW2])
1623
1624;; Iterators for fp16 operations
1625
1626(define_int_iterator VFMLA16_LOW [UNSPEC_FMLAL UNSPEC_FMLSL])
1627
1628(define_int_iterator VFMLA16_HIGH [UNSPEC_FMLAL2 UNSPEC_FMLSL2])
1629
43cacb12
RS		 1630(define_int_iterator UNPACK [UNSPEC_UNPACKSHI UNSPEC_UNPACKUHI
1631 UNSPEC_UNPACKSLO UNSPEC_UNPACKULO])
1632
1633(define_int_iterator UNPACK_UNSIGNED [UNSPEC_UNPACKULO UNSPEC_UNPACKUHI])
1634
11e9443f
RS		 1635(define_int_iterator MUL_HIGHPART [UNSPEC_SMUL_HIGHPART UNSPEC_UMUL_HIGHPART])
1636
b0760a40
RS		 1637(define_int_iterator SVE_INT_REDUCTION [UNSPEC_ANDV
1638 UNSPEC_IORV
1639 UNSPEC_SMAXV
1640 UNSPEC_SMINV
1641 UNSPEC_UMAXV
1642 UNSPEC_UMINV
1643 UNSPEC_XORV])
1644
1645(define_int_iterator SVE_FP_REDUCTION [UNSPEC_FADDV
1646 UNSPEC_FMAXV
1647 UNSPEC_FMAXNMV
1648 UNSPEC_FMINV
1649 UNSPEC_FMINNMV])
1650
d45b20a5
RS		 1651(define_int_iterator SVE_COND_FP_UNARY [UNSPEC_COND_FABS
1652 UNSPEC_COND_FNEG
1653 UNSPEC_COND_FRINTA
1654 UNSPEC_COND_FRINTI
1655 UNSPEC_COND_FRINTM
1656 UNSPEC_COND_FRINTN
1657 UNSPEC_COND_FRINTP
1658 UNSPEC_COND_FRINTX
1659 UNSPEC_COND_FRINTZ
1660 UNSPEC_COND_FSQRT])
1661
95eb5537 1662(define_int_iterator SVE_COND_FCVT [UNSPEC_COND_FCVT])
99361551
RS		 1663(define_int_iterator SVE_COND_FCVTI [UNSPEC_COND_FCVTZS UNSPEC_COND_FCVTZU])
1664(define_int_iterator SVE_COND_ICVTF [UNSPEC_COND_SCVTF UNSPEC_COND_UCVTF])
1665
cb18e86d
RS		 1666(define_int_iterator SVE_COND_FP_BINARY [UNSPEC_COND_FADD
1667 UNSPEC_COND_FDIV
1668 UNSPEC_COND_FMAXNM
1669 UNSPEC_COND_FMINNM
1670 UNSPEC_COND_FMUL
1671 UNSPEC_COND_FSUB])
0d2b3bca 1672
0254ed79
RS		 1673(define_int_iterator SVE_COND_FP_BINARY_REG [UNSPEC_COND_FDIV])
1674
214c42fa
RS		 1675;; Floating-point max/min operations that correspond to optabs,
1676;; as opposed to those that are internal to the port.
1677(define_int_iterator SVE_COND_FP_MAXMIN_PUBLIC [UNSPEC_COND_FMAXNM
1678 UNSPEC_COND_FMINNM])
1679
b41d1f6e
RS		 1680(define_int_iterator SVE_COND_FP_TERNARY [UNSPEC_COND_FMLA
1681 UNSPEC_COND_FMLS
1682 UNSPEC_COND_FNMLA
1683 UNSPEC_COND_FNMLS])
1684
4a942af6
RS		 1685;; SVE FP comparisons that accept #0.0.
1686(define_int_iterator SVE_COND_FP_CMP_I0 [UNSPEC_COND_FCMEQ
1687 UNSPEC_COND_FCMGE
1688 UNSPEC_COND_FCMGT
1689 UNSPEC_COND_FCMLE
1690 UNSPEC_COND_FCMLT
1691 UNSPEC_COND_FCMNE])
43cacb12 1692
9d63f43b
TC		 1693(define_int_iterator FCADD [UNSPEC_FCADD90
1694 UNSPEC_FCADD270])
1695
1696(define_int_iterator FCMLA [UNSPEC_FCMLA
1697 UNSPEC_FCMLA90
1698 UNSPEC_FCMLA180
1699 UNSPEC_FCMLA270])
1700
d81cb613
MW		 1701;; Iterators for atomic operations.
1702
1703(define_int_iterator ATOMIC_LDOP
1704 [UNSPECV_ATOMIC_LDOP_OR UNSPECV_ATOMIC_LDOP_BIC
1705 UNSPECV_ATOMIC_LDOP_XOR UNSPECV_ATOMIC_LDOP_PLUS])
1706
1707(define_int_attr atomic_ldop
1708 [(UNSPECV_ATOMIC_LDOP_OR "set") (UNSPECV_ATOMIC_LDOP_BIC "clr")
1709 (UNSPECV_ATOMIC_LDOP_XOR "eor") (UNSPECV_ATOMIC_LDOP_PLUS "add")])
1710
7803ec5e
RH		 1711(define_int_attr atomic_ldoptab
1712 [(UNSPECV_ATOMIC_LDOP_OR "ior") (UNSPECV_ATOMIC_LDOP_BIC "bic")
1713 (UNSPECV_ATOMIC_LDOP_XOR "xor") (UNSPECV_ATOMIC_LDOP_PLUS "add")])
1714
43e9d192
IB		 1715;; -------------------------------------------------------------------
1716;; Int Iterators Attributes.
1717;; -------------------------------------------------------------------
43cacb12
RS		 1718
1719;; The optab associated with an operation. Note that for ANDF, IORF
1720;; and XORF, the optab pattern is not actually defined; we just use this
1721;; name for consistency with the integer patterns.
1722(define_int_attr optab [(UNSPEC_ANDF "and")
1723 (UNSPEC_IORF "ior")
898f07b0
RS		 1724 (UNSPEC_XORF "xor")
1725 (UNSPEC_ANDV "and")
1726 (UNSPEC_IORV "ior")
0972596e 1727 (UNSPEC_XORV "xor")
b0760a40
RS		 1728 (UNSPEC_UMAXV "umax")
1729 (UNSPEC_UMINV "umin")
1730 (UNSPEC_SMAXV "smax")
1731 (UNSPEC_SMINV "smin")
1732 (UNSPEC_FADDV "plus")
1733 (UNSPEC_FMAXNMV "smax")
1734 (UNSPEC_FMAXV "smax_nan")
1735 (UNSPEC_FMINNMV "smin")
1736 (UNSPEC_FMINV "smin_nan")
d45b20a5 1737 (UNSPEC_COND_FABS "abs")
cb18e86d 1738 (UNSPEC_COND_FADD "add")
99361551
RS		 1739 (UNSPEC_COND_FCVT "fcvt")
1740 (UNSPEC_COND_FCVTZS "fix_trunc")
1741 (UNSPEC_COND_FCVTZU "fixuns_trunc")
cb18e86d
RS		 1742 (UNSPEC_COND_FDIV "div")
1743 (UNSPEC_COND_FMAXNM "smax")
1744 (UNSPEC_COND_FMINNM "smin")
b41d1f6e
RS		 1745 (UNSPEC_COND_FMLA "fma")
1746 (UNSPEC_COND_FMLS "fnma")
cb18e86d 1747 (UNSPEC_COND_FMUL "mul")
d45b20a5 1748 (UNSPEC_COND_FNEG "neg")
b41d1f6e 1749 (UNSPEC_COND_FNMLA "fnms")
cb18e86d 1750 (UNSPEC_COND_FNMLS "fms")
d45b20a5
RS		 1751 (UNSPEC_COND_FRINTA "round")
1752 (UNSPEC_COND_FRINTI "nearbyint")
1753 (UNSPEC_COND_FRINTM "floor")
1754 (UNSPEC_COND_FRINTN "frintn")
1755 (UNSPEC_COND_FRINTP "ceil")
1756 (UNSPEC_COND_FRINTX "rint")
1757 (UNSPEC_COND_FRINTZ "btrunc")
1758 (UNSPEC_COND_FSQRT "sqrt")
99361551
RS		 1759 (UNSPEC_COND_FSUB "sub")
1760 (UNSPEC_COND_SCVTF "float")
1761 (UNSPEC_COND_UCVTF "floatuns")])
43cacb12 1762
998eaf97
JG		 1763(define_int_attr maxmin_uns [(UNSPEC_UMAXV "umax")
1764 (UNSPEC_UMINV "umin")
1765 (UNSPEC_SMAXV "smax")
1766 (UNSPEC_SMINV "smin")
1767 (UNSPEC_FMAX "smax_nan")
1768 (UNSPEC_FMAXNMV "smax")
1769 (UNSPEC_FMAXV "smax_nan")
1770 (UNSPEC_FMIN "smin_nan")
1771 (UNSPEC_FMINNMV "smin")
1efafef3
TC		 1772 (UNSPEC_FMINV "smin_nan")
1773 (UNSPEC_FMAXNM "fmax")
214c42fa
RS		 1774 (UNSPEC_FMINNM "fmin")
1775 (UNSPEC_COND_FMAXNM "fmax")
1776 (UNSPEC_COND_FMINNM "fmin")])
998eaf97
JG		 1777
1778(define_int_attr maxmin_uns_op [(UNSPEC_UMAXV "umax")
1779 (UNSPEC_UMINV "umin")
1780 (UNSPEC_SMAXV "smax")
1781 (UNSPEC_SMINV "smin")
1782 (UNSPEC_FMAX "fmax")
1783 (UNSPEC_FMAXNMV "fmaxnm")
1784 (UNSPEC_FMAXV "fmax")
1785 (UNSPEC_FMIN "fmin")
1786 (UNSPEC_FMINNMV "fminnm")
1efafef3
TC		 1787 (UNSPEC_FMINV "fmin")
1788 (UNSPEC_FMAXNM "fmaxnm")
1789 (UNSPEC_FMINNM "fminnm")])
202d0c11 1790
43cacb12
RS		 1791;; The SVE logical instruction that implements an unspec.
1792(define_int_attr logicalf_op [(UNSPEC_ANDF "and")
1793 (UNSPEC_IORF "orr")
1794 (UNSPEC_XORF "eor")])
1795
1796;; "s" for signed operations and "u" for unsigned ones.
1797(define_int_attr su [(UNSPEC_UNPACKSHI "s")
1798 (UNSPEC_UNPACKUHI "u")
1799 (UNSPEC_UNPACKSLO "s")
11e9443f
RS		 1800 (UNSPEC_UNPACKULO "u")
1801 (UNSPEC_SMUL_HIGHPART "s")
99361551
RS		 1802 (UNSPEC_UMUL_HIGHPART "u")
1803 (UNSPEC_COND_FCVTZS "s")
1804 (UNSPEC_COND_FCVTZU "u")
1805 (UNSPEC_COND_SCVTF "s")
1806 (UNSPEC_COND_UCVTF "u")])
43cacb12 1807
43e9d192
IB		 1808(define_int_attr sur [(UNSPEC_SHADD "s") (UNSPEC_UHADD "u")
1809 (UNSPEC_SRHADD "sr") (UNSPEC_URHADD "ur")
1810 (UNSPEC_SHSUB "s") (UNSPEC_UHSUB "u")
1811 (UNSPEC_SRHSUB "sr") (UNSPEC_URHSUB "ur")
1812 (UNSPEC_ADDHN "") (UNSPEC_RADDHN "r")
75add2d0
KT		 1813 (UNSPEC_SABAL "s") (UNSPEC_UABAL "u")
1814 (UNSPEC_SABDL2 "s") (UNSPEC_UABDL2 "u")
1815 (UNSPEC_SADALP "s") (UNSPEC_UADALP "u")
43e9d192
IB		 1816 (UNSPEC_SUBHN "") (UNSPEC_RSUBHN "r")
1817 (UNSPEC_ADDHN2 "") (UNSPEC_RADDHN2 "r")
1818 (UNSPEC_SUBHN2 "") (UNSPEC_RSUBHN2 "r")
1819 (UNSPEC_SQXTN "s") (UNSPEC_UQXTN "u")
1820 (UNSPEC_USQADD "us") (UNSPEC_SUQADD "su")
1821 (UNSPEC_SSLI "s") (UNSPEC_USLI "u")
1822 (UNSPEC_SSRI "s") (UNSPEC_USRI "u")
1823 (UNSPEC_USRA "u") (UNSPEC_SSRA "s")
1824 (UNSPEC_URSRA "ur") (UNSPEC_SRSRA "sr")
1825 (UNSPEC_URSHR "ur") (UNSPEC_SRSHR "sr")
1826 (UNSPEC_SQSHLU "s") (UNSPEC_SQSHL "s")
1827 (UNSPEC_UQSHL "u")
1828 (UNSPEC_SQSHRUN "s") (UNSPEC_SQRSHRUN "s")
1829 (UNSPEC_SQSHRN "s") (UNSPEC_UQSHRN "u")
1830 (UNSPEC_SQRSHRN "s") (UNSPEC_UQRSHRN "u")
1831 (UNSPEC_USHL "u") (UNSPEC_SSHL "s")
1832 (UNSPEC_USHLL "u") (UNSPEC_SSHLL "s")
1833 (UNSPEC_URSHL "ur") (UNSPEC_SRSHL "sr")
1834 (UNSPEC_UQRSHL "u") (UNSPEC_SQRSHL "s")
7a08d813 1835 (UNSPEC_SDOT "s") (UNSPEC_UDOT "u")
43e9d192
IB		 1836])
1837
1838(define_int_attr r [(UNSPEC_SQDMULH "") (UNSPEC_SQRDMULH "r")
1839 (UNSPEC_SQSHRUN "") (UNSPEC_SQRSHRUN "r")
1840 (UNSPEC_SQSHRN "") (UNSPEC_UQSHRN "")
1841 (UNSPEC_SQRSHRN "r") (UNSPEC_UQRSHRN "r")
1842 (UNSPEC_SQSHL "") (UNSPEC_UQSHL "")
1843 (UNSPEC_SQRSHL "r")(UNSPEC_UQRSHL "r")
1844])
1845
1846(define_int_attr lr [(UNSPEC_SSLI "l") (UNSPEC_USLI "l")
1847 (UNSPEC_SSRI "r") (UNSPEC_USRI "r")])
1848
1849(define_int_attr u [(UNSPEC_SQSHLU "u") (UNSPEC_SQSHL "") (UNSPEC_UQSHL "")
1850 (UNSPEC_SQSHRUN "u") (UNSPEC_SQRSHRUN "u")
42addb5a
RS		 1851 (UNSPEC_SQSHRN "") (UNSPEC_UQSHRN "")
1852 (UNSPEC_SQRSHRN "") (UNSPEC_UQRSHRN "")
1853 (UNSPEC_SHADD "") (UNSPEC_UHADD "u")
1854 (UNSPEC_SRHADD "") (UNSPEC_URHADD "u")])
43e9d192
IB		 1855
1856(define_int_attr addsub [(UNSPEC_SHADD "add")
1857 (UNSPEC_UHADD "add")
1858 (UNSPEC_SRHADD "add")
1859 (UNSPEC_URHADD "add")
1860 (UNSPEC_SHSUB "sub")
1861 (UNSPEC_UHSUB "sub")
1862 (UNSPEC_SRHSUB "sub")
1863 (UNSPEC_URHSUB "sub")
1864 (UNSPEC_ADDHN "add")
1865 (UNSPEC_SUBHN "sub")
1866 (UNSPEC_RADDHN "add")
1867 (UNSPEC_RSUBHN "sub")
1868 (UNSPEC_ADDHN2 "add")
1869 (UNSPEC_SUBHN2 "sub")
1870 (UNSPEC_RADDHN2 "add")
1871 (UNSPEC_RSUBHN2 "sub")])
1872
cb23a30c
JG		 1873(define_int_attr offsetlr [(UNSPEC_SSLI "") (UNSPEC_USLI "")
1874 (UNSPEC_SSRI "offset_")
1875 (UNSPEC_USRI "offset_")])
43e9d192 1876
42fc9a7f
JG		 1877;; Standard pattern names for floating-point rounding instructions.
1878(define_int_attr frint_pattern [(UNSPEC_FRINTZ "btrunc")
1879 (UNSPEC_FRINTP "ceil")
1880 (UNSPEC_FRINTM "floor")
1881 (UNSPEC_FRINTI "nearbyint")
1882 (UNSPEC_FRINTX "rint")
0659ce6f
JG		 1883 (UNSPEC_FRINTA "round")
1884 (UNSPEC_FRINTN "frintn")])
42fc9a7f
JG		 1885
1886;; frint suffix for floating-point rounding instructions.
1887(define_int_attr frint_suffix [(UNSPEC_FRINTZ "z") (UNSPEC_FRINTP "p")
1888 (UNSPEC_FRINTM "m") (UNSPEC_FRINTI "i")
0659ce6f
JG		 1889 (UNSPEC_FRINTX "x") (UNSPEC_FRINTA "a")
1890 (UNSPEC_FRINTN "n")])
42fc9a7f
JG		 1891
1892(define_int_attr fcvt_pattern [(UNSPEC_FRINTZ "btrunc") (UNSPEC_FRINTA "round")
ce966824
JG		 1893 (UNSPEC_FRINTP "ceil") (UNSPEC_FRINTM "floor")
1894 (UNSPEC_FRINTN "frintn")])
42fc9a7f 1895
3f598afe
JW		 1896(define_int_attr fcvt_fixed_insn [(UNSPEC_SCVTF "scvtf")
1897 (UNSPEC_UCVTF "ucvtf")
1898 (UNSPEC_FCVTZS "fcvtzs")
1899 (UNSPEC_FCVTZU "fcvtzu")])
1900
db58fd89 1901;; Pointer authentication mnemonic prefix.
8fc16d72
ST		 1902(define_int_attr pauth_mnem_prefix [(UNSPEC_PACIASP "pacia")
1903 (UNSPEC_PACIBSP "pacib")
1904 (UNSPEC_PACIA1716 "pacia")
1905 (UNSPEC_PACIB1716 "pacib")
1906 (UNSPEC_AUTIASP "autia")
1907 (UNSPEC_AUTIBSP "autib")
1908 (UNSPEC_AUTIA1716 "autia")
1909 (UNSPEC_AUTIB1716 "autib")])
1910
1911(define_int_attr pauth_key [(UNSPEC_PACIASP "AARCH64_KEY_A")
1912 (UNSPEC_PACIBSP "AARCH64_KEY_B")
1913 (UNSPEC_PACIA1716 "AARCH64_KEY_A")
1914 (UNSPEC_PACIB1716 "AARCH64_KEY_B")
1915 (UNSPEC_AUTIASP "AARCH64_KEY_A")
1916 (UNSPEC_AUTIBSP "AARCH64_KEY_B")
1917 (UNSPEC_AUTIA1716 "AARCH64_KEY_A")
1918 (UNSPEC_AUTIB1716 "AARCH64_KEY_B")])
1919
1920;; Pointer authentication HINT number for NOP space instructions using A and
1921;; B key.
1922(define_int_attr pauth_hint_num [(UNSPEC_PACIASP "25")
1923 (UNSPEC_PACIBSP "27")
1924 (UNSPEC_AUTIASP "29")
1925 (UNSPEC_AUTIBSP "31")
1926 (UNSPEC_PACIA1716 "8")
1927 (UNSPEC_PACIB1716 "10")
1928 (UNSPEC_AUTIA1716 "12")
1929 (UNSPEC_AUTIB1716 "14")])
db58fd89 1930
3e2751ce
RS		 1931(define_int_attr perm_insn [(UNSPEC_ZIP1 "zip1") (UNSPEC_ZIP2 "zip2")
1932 (UNSPEC_TRN1 "trn1") (UNSPEC_TRN2 "trn2")
1933 (UNSPEC_UZP1 "uzp1") (UNSPEC_UZP2 "uzp2")])
cc4d934f 1934
923fcec3
AL		 1935; op code for REV instructions (size within which elements are reversed).
1936(define_int_attr rev_op [(UNSPEC_REV64 "64") (UNSPEC_REV32 "32")
1937 (UNSPEC_REV16 "16")])
1938
3e2751ce 1939(define_int_attr perm_hilo [(UNSPEC_UNPACKSHI "hi") (UNSPEC_UNPACKUHI "hi")
43cacb12 1940 (UNSPEC_UNPACKSLO "lo") (UNSPEC_UNPACKULO "lo")])
0050faf8 1941
9bfb28ed
RS		 1942;; Return true if the associated optab refers to the high-numbered lanes,
1943;; false if it refers to the low-numbered lanes. The convention is for
1944;; "hi" to refer to the low-numbered lanes (the first ones in memory)
1945;; for big-endian.
1946(define_int_attr hi_lanes_optab [(UNSPEC_UNPACKSHI "!BYTES_BIG_ENDIAN")
1947 (UNSPEC_UNPACKUHI "!BYTES_BIG_ENDIAN")
1948 (UNSPEC_UNPACKSLO "BYTES_BIG_ENDIAN")
1949 (UNSPEC_UNPACKULO "BYTES_BIG_ENDIAN")])
1950
5d357f26
KT		 1951(define_int_attr crc_variant [(UNSPEC_CRC32B "crc32b") (UNSPEC_CRC32H "crc32h")
1952 (UNSPEC_CRC32W "crc32w") (UNSPEC_CRC32X "crc32x")
1953 (UNSPEC_CRC32CB "crc32cb") (UNSPEC_CRC32CH "crc32ch")
1954 (UNSPEC_CRC32CW "crc32cw") (UNSPEC_CRC32CX "crc32cx")])
1955
1956(define_int_attr crc_mode [(UNSPEC_CRC32B "QI") (UNSPEC_CRC32H "HI")
1957 (UNSPEC_CRC32W "SI") (UNSPEC_CRC32X "DI")
1958 (UNSPEC_CRC32CB "QI") (UNSPEC_CRC32CH "HI")
1959 (UNSPEC_CRC32CW "SI") (UNSPEC_CRC32CX "DI")])
1960
5a7a4e80
TB		 1961(define_int_attr aes_op [(UNSPEC_AESE "e") (UNSPEC_AESD "d")])
1962(define_int_attr aesmc_op [(UNSPEC_AESMC "mc") (UNSPEC_AESIMC "imc")])
30442682
TB		 1963
1964(define_int_attr sha1_op [(UNSPEC_SHA1C "c") (UNSPEC_SHA1P "p")
1965 (UNSPEC_SHA1M "m")])
b9cb0a44
TB		 1966
1967(define_int_attr sha256_op [(UNSPEC_SHA256H "") (UNSPEC_SHA256H2 "2")])
57b26d65
MW		 1968
1969(define_int_attr rdma_as [(UNSPEC_SQRDMLAH "a") (UNSPEC_SQRDMLSH "s")])
27086ea3
MC		 1970
1971(define_int_attr sha512_op [(UNSPEC_SHA512H "") (UNSPEC_SHA512H2 "2")])
1972
1973(define_int_attr sm3tt_op [(UNSPEC_SM3TT1A "1a") (UNSPEC_SM3TT1B "1b")
1974 (UNSPEC_SM3TT2A "2a") (UNSPEC_SM3TT2B "2b")])
1975
1976(define_int_attr sm3part_op [(UNSPEC_SM3PARTW1 "1") (UNSPEC_SM3PARTW2 "2")])
1977
1978(define_int_attr f16mac1 [(UNSPEC_FMLAL "a") (UNSPEC_FMLSL "s")
1979 (UNSPEC_FMLAL2 "a") (UNSPEC_FMLSL2 "s")])
43cacb12
RS		 1980
1981;; The condition associated with an UNSPEC_COND_<xx>.
cb18e86d
RS		 1982(define_int_attr cmp_op [(UNSPEC_COND_FCMEQ "eq")
1983 (UNSPEC_COND_FCMGE "ge")
1984 (UNSPEC_COND_FCMGT "gt")
1985 (UNSPEC_COND_FCMLE "le")
1986 (UNSPEC_COND_FCMLT "lt")
4a942af6
RS		 1987 (UNSPEC_COND_FCMNE "ne")
1988 (UNSPEC_COND_FCMUO "uo")])
cb18e86d 1989
b0760a40
RS		 1990(define_int_attr sve_int_op [(UNSPEC_ANDV "andv")
1991 (UNSPEC_IORV "orv")
1992 (UNSPEC_XORV "eorv")
1993 (UNSPEC_UMAXV "umaxv")
1994 (UNSPEC_UMINV "uminv")
1995 (UNSPEC_SMAXV "smaxv")
1996 (UNSPEC_SMINV "sminv")])
1997
1998(define_int_attr sve_fp_op [(UNSPEC_FADDV "faddv")
1999 (UNSPEC_FMAXNMV "fmaxnmv")
2000 (UNSPEC_FMAXV "fmaxv")
2001 (UNSPEC_FMINNMV "fminnmv")
2002 (UNSPEC_FMINV "fminv")
2003 (UNSPEC_COND_FABS "fabs")
d45b20a5 2004 (UNSPEC_COND_FADD "fadd")
cb18e86d
RS		 2005 (UNSPEC_COND_FDIV "fdiv")
2006 (UNSPEC_COND_FMAXNM "fmaxnm")
2007 (UNSPEC_COND_FMINNM "fminnm")
2008 (UNSPEC_COND_FMUL "fmul")
d45b20a5
RS		 2009 (UNSPEC_COND_FNEG "fneg")
2010 (UNSPEC_COND_FRINTA "frinta")
2011 (UNSPEC_COND_FRINTI "frinti")
2012 (UNSPEC_COND_FRINTM "frintm")
2013 (UNSPEC_COND_FRINTN "frintn")
2014 (UNSPEC_COND_FRINTP "frintp")
2015 (UNSPEC_COND_FRINTX "frintx")
2016 (UNSPEC_COND_FRINTZ "frintz")
2017 (UNSPEC_COND_FSQRT "fsqrt")
cb18e86d
RS		 2018 (UNSPEC_COND_FSUB "fsub")])
2019
2020(define_int_attr sve_fp_op_rev [(UNSPEC_COND_FADD "fadd")
2021 (UNSPEC_COND_FDIV "fdivr")
2022 (UNSPEC_COND_FMAXNM "fmaxnm")
2023 (UNSPEC_COND_FMINNM "fminnm")
2024 (UNSPEC_COND_FMUL "fmul")
2025 (UNSPEC_COND_FSUB "fsubr")])
a08acce8 2026
9d63f43b
TC		 2027(define_int_attr rot [(UNSPEC_FCADD90 "90")
2028 (UNSPEC_FCADD270 "270")
2029 (UNSPEC_FCMLA "0")
2030 (UNSPEC_FCMLA90 "90")
2031 (UNSPEC_FCMLA180 "180")
2032 (UNSPEC_FCMLA270 "270")])
2033
b41d1f6e
RS		 2034(define_int_attr sve_fmla_op [(UNSPEC_COND_FMLA "fmla")
2035 (UNSPEC_COND_FMLS "fmls")
2036 (UNSPEC_COND_FNMLA "fnmla")
2037 (UNSPEC_COND_FNMLS "fnmls")])
2038
2039(define_int_attr sve_fmad_op [(UNSPEC_COND_FMLA "fmad")
2040 (UNSPEC_COND_FMLS "fmsb")
2041 (UNSPEC_COND_FNMLA "fnmad")
2042 (UNSPEC_COND_FNMLS "fnmsb")])
0254ed79
RS		 2043
2044;; The predicate to use for the first input operand in a floating-point
2045;; <optab><mode>3 pattern.
2046(define_int_attr sve_pred_fp_rhs1_operand
2047 [(UNSPEC_COND_FADD "register_operand")
2048 (UNSPEC_COND_FDIV "register_operand")
2049 (UNSPEC_COND_FMAXNM "register_operand")
2050 (UNSPEC_COND_FMINNM "register_operand")
2051 (UNSPEC_COND_FMUL "register_operand")
2052 (UNSPEC_COND_FSUB "aarch64_sve_float_arith_operand")])
2053
2054;; The predicate to use for the second input operand in a floating-point
2055;; <optab><mode>3 pattern.
2056(define_int_attr sve_pred_fp_rhs2_operand
2057 [(UNSPEC_COND_FADD "aarch64_sve_float_arith_with_sub_operand")
2058 (UNSPEC_COND_FDIV "register_operand")
2059 (UNSPEC_COND_FMAXNM "register_operand")
2060 (UNSPEC_COND_FMINNM "register_operand")
2061 (UNSPEC_COND_FMUL "aarch64_sve_float_mul_operand")
2062 (UNSPEC_COND_FSUB "register_operand")])
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