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43e9d192 | 1 | ;; Machine description for AArch64 architecture. |
d1e082c2 | 2 | ;; Copyright (C) 2009-2013 Free Software Foundation, Inc. |
43e9d192 IB |
3 | ;; Contributed by ARM Ltd. |
4 | ;; | |
5 | ;; This file is part of GCC. | |
6 | ;; | |
7 | ;; GCC is free software; you can redistribute it and/or modify it | |
8 | ;; under the terms of the GNU General Public License as published by | |
9 | ;; the Free Software Foundation; either version 3, or (at your option) | |
10 | ;; any later version. | |
11 | ;; | |
12 | ;; GCC is distributed in the hope that it will be useful, but | |
13 | ;; WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | ;; General Public License for more details. | |
16 | ;; | |
17 | ;; You should have received a copy of the GNU General Public License | |
18 | ;; along with GCC; see the file COPYING3. If not see | |
19 | ;; <http://www.gnu.org/licenses/>. | |
20 | ||
21 | ;; ------------------------------------------------------------------- | |
22 | ;; Mode Iterators | |
23 | ;; ------------------------------------------------------------------- | |
24 | ||
25 | ||
26 | ;; Iterator for General Purpose Integer registers (32- and 64-bit modes) | |
27 | (define_mode_iterator GPI [SI DI]) | |
28 | ||
29 | ;; Iterator for QI and HI modes | |
30 | (define_mode_iterator SHORT [QI HI]) | |
31 | ||
32 | ;; Iterator for all integer modes (up to 64-bit) | |
33 | (define_mode_iterator ALLI [QI HI SI DI]) | |
34 | ||
35 | ;; Iterator scalar modes (up to 64-bit) | |
36 | (define_mode_iterator SDQ_I [QI HI SI DI]) | |
37 | ||
38 | ;; Iterator for all integer modes that can be extended (up to 64-bit) | |
39 | (define_mode_iterator ALLX [QI HI SI]) | |
40 | ||
41 | ;; Iterator for General Purpose Floating-point registers (32- and 64-bit modes) | |
42 | (define_mode_iterator GPF [SF DF]) | |
43 | ||
44 | ;; Integer vector modes. | |
45 | (define_mode_iterator VDQ [V8QI V16QI V4HI V8HI V2SI V4SI V2DI]) | |
46 | ||
47 | ;; Integer vector modes. | |
48 | (define_mode_iterator VDQ_I [V8QI V16QI V4HI V8HI V2SI V4SI V2DI]) | |
49 | ||
50 | ;; vector and scalar, 64 & 128-bit container, all integer modes | |
51 | (define_mode_iterator VSDQ_I [V8QI V16QI V4HI V8HI V2SI V4SI V2DI QI HI SI DI]) | |
52 | ||
53 | ;; vector and scalar, 64 & 128-bit container: all vector integer modes; | |
54 | ;; 64-bit scalar integer mode | |
55 | (define_mode_iterator VSDQ_I_DI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI DI]) | |
56 | ||
57 | ;; Double vector modes. | |
58 | (define_mode_iterator VD [V8QI V4HI V2SI V2SF]) | |
59 | ||
60 | ;; vector, 64-bit container, all integer modes | |
61 | (define_mode_iterator VD_BHSI [V8QI V4HI V2SI]) | |
62 | ||
63 | ;; 128 and 64-bit container; 8, 16, 32-bit vector integer modes | |
64 | (define_mode_iterator VDQ_BHSI [V8QI V16QI V4HI V8HI V2SI V4SI]) | |
65 | ||
66 | ;; Quad vector modes. | |
67 | (define_mode_iterator VQ [V16QI V8HI V4SI V2DI V4SF V2DF]) | |
68 | ||
69 | ;; All vector modes, except double. | |
70 | (define_mode_iterator VQ_S [V8QI V16QI V4HI V8HI V2SI V4SI]) | |
71 | ||
72 | ;; Vector and scalar, 64 & 128-bit container: all vector integer mode; | |
73 | ;; 8, 16, 32-bit scalar integer modes | |
74 | (define_mode_iterator VSDQ_I_BHSI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI QI HI SI]) | |
75 | ||
76 | ;; Vector modes for moves. | |
77 | (define_mode_iterator VDQM [V8QI V16QI V4HI V8HI V2SI V4SI]) | |
78 | ||
28514dda YZ |
79 | ;; This mode iterator allows :P to be used for patterns that operate on |
80 | ;; addresses in different modes. In LP64, only DI will match, while in | |
81 | ;; ILP32, either can match. | |
82 | (define_mode_iterator P [(SI "ptr_mode == SImode || Pmode == SImode") | |
83 | (DI "ptr_mode == DImode || Pmode == DImode")]) | |
84 | ||
43e9d192 IB |
85 | ;; This mode iterator allows :PTR to be used for patterns that operate on |
86 | ;; pointer-sized quantities. Exactly one of the two alternatives will match. | |
28514dda | 87 | (define_mode_iterator PTR [(SI "ptr_mode == SImode") (DI "ptr_mode == DImode")]) |
43e9d192 IB |
88 | |
89 | ;; Vector Float modes. | |
90 | (define_mode_iterator VDQF [V2SF V4SF V2DF]) | |
91 | ||
fc21784d JG |
92 | ;; Modes suitable to use as the return type of a vcond expression. |
93 | (define_mode_iterator VDQF_COND [V2SF V2SI V4SF V4SI V2DF V2DI]) | |
94 | ||
889b9412 JG |
95 | ;; All Float modes. |
96 | (define_mode_iterator VALLF [V2SF V4SF V2DF SF DF]) | |
97 | ||
43e9d192 IB |
98 | ;; Vector Float modes with 2 elements. |
99 | (define_mode_iterator V2F [V2SF V2DF]) | |
100 | ||
101 | ;; All modes. | |
102 | (define_mode_iterator VALL [V8QI V16QI V4HI V8HI V2SI V4SI V2DI V2SF V4SF V2DF]) | |
103 | ||
a50344cb TB |
104 | ;; All vector modes and DI. |
105 | (define_mode_iterator VALLDI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI V2SF V4SF V2DF DI]) | |
106 | ||
43e9d192 IB |
107 | ;; Vector modes for Integer reduction across lanes. |
108 | (define_mode_iterator VDQV [V8QI V16QI V4HI V8HI V4SI]) | |
109 | ||
110 | ;; All double integer narrow-able modes. | |
111 | (define_mode_iterator VDN [V4HI V2SI DI]) | |
112 | ||
113 | ;; All quad integer narrow-able modes. | |
114 | (define_mode_iterator VQN [V8HI V4SI V2DI]) | |
115 | ||
116 | ;; All double integer widen-able modes. | |
117 | (define_mode_iterator VDW [V8QI V4HI V2SI]) | |
118 | ||
119 | ;; Vector and scalar 128-bit container: narrowable 16, 32, 64-bit integer modes | |
120 | (define_mode_iterator VSQN_HSDI [V8HI V4SI V2DI HI SI DI]) | |
121 | ||
122 | ;; All quad integer widen-able modes. | |
123 | (define_mode_iterator VQW [V16QI V8HI V4SI]) | |
124 | ||
125 | ;; Double vector modes for combines. | |
126 | (define_mode_iterator VDC [V8QI V4HI V2SI V2SF DI DF]) | |
127 | ||
128 | ;; Double vector modes for combines. | |
129 | (define_mode_iterator VDIC [V8QI V4HI V2SI]) | |
130 | ||
131 | ;; Double vector modes. | |
132 | (define_mode_iterator VD_RE [V8QI V4HI V2SI DI DF V2SF]) | |
133 | ||
134 | ;; Vector modes except double int. | |
135 | (define_mode_iterator VDQIF [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF V2DF]) | |
136 | ||
66adb8eb JG |
137 | ;; Vector modes for Q and H types. |
138 | (define_mode_iterator VDQQH [V8QI V16QI V4HI V8HI]) | |
139 | ||
43e9d192 IB |
140 | ;; Vector modes for H and S types. |
141 | (define_mode_iterator VDQHS [V4HI V8HI V2SI V4SI]) | |
142 | ||
66adb8eb JG |
143 | ;; Vector modes for Q, H and S types. |
144 | (define_mode_iterator VDQQHS [V8QI V16QI V4HI V8HI V2SI V4SI]) | |
145 | ||
43e9d192 IB |
146 | ;; Vector and scalar integer modes for H and S |
147 | (define_mode_iterator VSDQ_HSI [V4HI V8HI V2SI V4SI HI SI]) | |
148 | ||
149 | ;; Vector and scalar 64-bit container: 16, 32-bit integer modes | |
150 | (define_mode_iterator VSD_HSI [V4HI V2SI HI SI]) | |
151 | ||
152 | ;; Vector 64-bit container: 16, 32-bit integer modes | |
153 | (define_mode_iterator VD_HSI [V4HI V2SI]) | |
154 | ||
155 | ;; Scalar 64-bit container: 16, 32-bit integer modes | |
156 | (define_mode_iterator SD_HSI [HI SI]) | |
157 | ||
158 | ;; Vector 64-bit container: 16, 32-bit integer modes | |
159 | (define_mode_iterator VQ_HSI [V8HI V4SI]) | |
160 | ||
161 | ;; All byte modes. | |
162 | (define_mode_iterator VB [V8QI V16QI]) | |
163 | ||
164 | (define_mode_iterator TX [TI TF]) | |
165 | ||
166 | ;; Opaque structure modes. | |
167 | (define_mode_iterator VSTRUCT [OI CI XI]) | |
168 | ||
169 | ;; Double scalar modes | |
170 | (define_mode_iterator DX [DI DF]) | |
171 | ||
172 | ;; ------------------------------------------------------------------ | |
173 | ;; Unspec enumerations for Advance SIMD. These could well go into | |
174 | ;; aarch64.md but for their use in int_iterators here. | |
175 | ;; ------------------------------------------------------------------ | |
176 | ||
177 | (define_c_enum "unspec" | |
178 | [ | |
179 | UNSPEC_ASHIFT_SIGNED ; Used in aarch-simd.md. | |
180 | UNSPEC_ASHIFT_UNSIGNED ; Used in aarch64-simd.md. | |
998eaf97 JG |
181 | UNSPEC_FMAX ; Used in aarch64-simd.md. |
182 | UNSPEC_FMAXNMV ; Used in aarch64-simd.md. | |
43e9d192 | 183 | UNSPEC_FMAXV ; Used in aarch64-simd.md. |
998eaf97 JG |
184 | UNSPEC_FMIN ; Used in aarch64-simd.md. |
185 | UNSPEC_FMINNMV ; Used in aarch64-simd.md. | |
43e9d192 IB |
186 | UNSPEC_FMINV ; Used in aarch64-simd.md. |
187 | UNSPEC_FADDV ; Used in aarch64-simd.md. | |
36054fab JG |
188 | UNSPEC_SADDV ; Used in aarch64-simd.md. |
189 | UNSPEC_UADDV ; Used in aarch64-simd.md. | |
43e9d192 IB |
190 | UNSPEC_SMAXV ; Used in aarch64-simd.md. |
191 | UNSPEC_SMINV ; Used in aarch64-simd.md. | |
192 | UNSPEC_UMAXV ; Used in aarch64-simd.md. | |
193 | UNSPEC_UMINV ; Used in aarch64-simd.md. | |
194 | UNSPEC_SHADD ; Used in aarch64-simd.md. | |
195 | UNSPEC_UHADD ; Used in aarch64-simd.md. | |
196 | UNSPEC_SRHADD ; Used in aarch64-simd.md. | |
197 | UNSPEC_URHADD ; Used in aarch64-simd.md. | |
198 | UNSPEC_SHSUB ; Used in aarch64-simd.md. | |
199 | UNSPEC_UHSUB ; Used in aarch64-simd.md. | |
200 | UNSPEC_SRHSUB ; Used in aarch64-simd.md. | |
201 | UNSPEC_URHSUB ; Used in aarch64-simd.md. | |
202 | UNSPEC_ADDHN ; Used in aarch64-simd.md. | |
203 | UNSPEC_RADDHN ; Used in aarch64-simd.md. | |
204 | UNSPEC_SUBHN ; Used in aarch64-simd.md. | |
205 | UNSPEC_RSUBHN ; Used in aarch64-simd.md. | |
206 | UNSPEC_ADDHN2 ; Used in aarch64-simd.md. | |
207 | UNSPEC_RADDHN2 ; Used in aarch64-simd.md. | |
208 | UNSPEC_SUBHN2 ; Used in aarch64-simd.md. | |
209 | UNSPEC_RSUBHN2 ; Used in aarch64-simd.md. | |
210 | UNSPEC_SQDMULH ; Used in aarch64-simd.md. | |
211 | UNSPEC_SQRDMULH ; Used in aarch64-simd.md. | |
212 | UNSPEC_PMUL ; Used in aarch64-simd.md. | |
213 | UNSPEC_USQADD ; Used in aarch64-simd.md. | |
214 | UNSPEC_SUQADD ; Used in aarch64-simd.md. | |
215 | UNSPEC_SQXTUN ; Used in aarch64-simd.md. | |
216 | UNSPEC_SQXTN ; Used in aarch64-simd.md. | |
217 | UNSPEC_UQXTN ; Used in aarch64-simd.md. | |
218 | UNSPEC_SSRA ; Used in aarch64-simd.md. | |
219 | UNSPEC_USRA ; Used in aarch64-simd.md. | |
220 | UNSPEC_SRSRA ; Used in aarch64-simd.md. | |
221 | UNSPEC_URSRA ; Used in aarch64-simd.md. | |
222 | UNSPEC_SRSHR ; Used in aarch64-simd.md. | |
223 | UNSPEC_URSHR ; Used in aarch64-simd.md. | |
224 | UNSPEC_SQSHLU ; Used in aarch64-simd.md. | |
225 | UNSPEC_SQSHL ; Used in aarch64-simd.md. | |
226 | UNSPEC_UQSHL ; Used in aarch64-simd.md. | |
227 | UNSPEC_SQSHRUN ; Used in aarch64-simd.md. | |
228 | UNSPEC_SQRSHRUN ; Used in aarch64-simd.md. | |
229 | UNSPEC_SQSHRN ; Used in aarch64-simd.md. | |
230 | UNSPEC_UQSHRN ; Used in aarch64-simd.md. | |
231 | UNSPEC_SQRSHRN ; Used in aarch64-simd.md. | |
232 | UNSPEC_UQRSHRN ; Used in aarch64-simd.md. | |
233 | UNSPEC_SSHL ; Used in aarch64-simd.md. | |
234 | UNSPEC_USHL ; Used in aarch64-simd.md. | |
235 | UNSPEC_SRSHL ; Used in aarch64-simd.md. | |
236 | UNSPEC_URSHL ; Used in aarch64-simd.md. | |
237 | UNSPEC_SQRSHL ; Used in aarch64-simd.md. | |
238 | UNSPEC_UQRSHL ; Used in aarch64-simd.md. | |
43e9d192 IB |
239 | UNSPEC_SSLI ; Used in aarch64-simd.md. |
240 | UNSPEC_USLI ; Used in aarch64-simd.md. | |
241 | UNSPEC_SSRI ; Used in aarch64-simd.md. | |
242 | UNSPEC_USRI ; Used in aarch64-simd.md. | |
243 | UNSPEC_SSHLL ; Used in aarch64-simd.md. | |
244 | UNSPEC_USHLL ; Used in aarch64-simd.md. | |
245 | UNSPEC_ADDP ; Used in aarch64-simd.md. | |
88b08073 JG |
246 | UNSPEC_TBL ; Used in vector permute patterns. |
247 | UNSPEC_CONCAT ; Used in vector permute patterns. | |
cc4d934f JG |
248 | UNSPEC_ZIP1 ; Used in vector permute patterns. |
249 | UNSPEC_ZIP2 ; Used in vector permute patterns. | |
250 | UNSPEC_UZP1 ; Used in vector permute patterns. | |
251 | UNSPEC_UZP2 ; Used in vector permute patterns. | |
252 | UNSPEC_TRN1 ; Used in vector permute patterns. | |
253 | UNSPEC_TRN2 ; Used in vector permute patterns. | |
43e9d192 IB |
254 | ]) |
255 | ||
256 | ;; ------------------------------------------------------------------- | |
257 | ;; Mode attributes | |
258 | ;; ------------------------------------------------------------------- | |
259 | ||
260 | ;; In GPI templates, a string like "%<w>0" will expand to "%w0" in the | |
261 | ;; 32-bit version and "%x0" in the 64-bit version. | |
262 | (define_mode_attr w [(QI "w") (HI "w") (SI "w") (DI "x") (SF "s") (DF "d")]) | |
263 | ||
051d0e2f SN |
264 | ;; For constraints used in scalar immediate vector moves |
265 | (define_mode_attr hq [(HI "h") (QI "q")]) | |
266 | ||
43e9d192 IB |
267 | ;; For scalar usage of vector/FP registers |
268 | (define_mode_attr v [(QI "b") (HI "h") (SI "s") (DI "d") | |
889b9412 | 269 | (SF "s") (DF "d") |
43e9d192 IB |
270 | (V8QI "") (V16QI "") |
271 | (V4HI "") (V8HI "") | |
272 | (V2SI "") (V4SI "") | |
273 | (V2DI "") (V2SF "") | |
274 | (V4SF "") (V2DF "")]) | |
275 | ||
276 | ;; For scalar usage of vector/FP registers, narrowing | |
277 | (define_mode_attr vn2 [(QI "") (HI "b") (SI "h") (DI "s") | |
278 | (V8QI "") (V16QI "") | |
279 | (V4HI "") (V8HI "") | |
280 | (V2SI "") (V4SI "") | |
281 | (V2DI "") (V2SF "") | |
282 | (V4SF "") (V2DF "")]) | |
283 | ||
284 | ;; For scalar usage of vector/FP registers, widening | |
285 | (define_mode_attr vw2 [(DI "") (QI "h") (HI "s") (SI "d") | |
286 | (V8QI "") (V16QI "") | |
287 | (V4HI "") (V8HI "") | |
288 | (V2SI "") (V4SI "") | |
289 | (V2DI "") (V2SF "") | |
290 | (V4SF "") (V2DF "")]) | |
291 | ||
89fdc743 IB |
292 | ;; Register Type Name and Vector Arrangement Specifier for when |
293 | ;; we are doing scalar for DI and SIMD for SI (ignoring all but | |
294 | ;; lane 0). | |
295 | (define_mode_attr rtn [(DI "d") (SI "")]) | |
296 | (define_mode_attr vas [(DI "") (SI ".2s")]) | |
297 | ||
43e9d192 IB |
298 | ;; Map a floating point mode to the appropriate register name prefix |
299 | (define_mode_attr s [(SF "s") (DF "d")]) | |
300 | ||
301 | ;; Give the length suffix letter for a sign- or zero-extension. | |
302 | (define_mode_attr size [(QI "b") (HI "h") (SI "w")]) | |
303 | ||
304 | ;; Give the number of bits in the mode | |
305 | (define_mode_attr sizen [(QI "8") (HI "16") (SI "32") (DI "64")]) | |
306 | ||
307 | ;; Give the ordinal of the MSB in the mode | |
308 | (define_mode_attr sizem1 [(QI "#7") (HI "#15") (SI "#31") (DI "#63")]) | |
309 | ||
310 | ;; Attribute to describe constants acceptable in logical operations | |
311 | (define_mode_attr lconst [(SI "K") (DI "L")]) | |
312 | ||
313 | ;; Map a mode to a specific constraint character. | |
314 | (define_mode_attr cmode [(QI "q") (HI "h") (SI "s") (DI "d")]) | |
315 | ||
316 | (define_mode_attr Vtype [(V8QI "8b") (V16QI "16b") | |
317 | (V4HI "4h") (V8HI "8h") | |
318 | (V2SI "2s") (V4SI "4s") | |
319 | (DI "1d") (DF "1d") | |
320 | (V2DI "2d") (V2SF "2s") | |
321 | (V4SF "4s") (V2DF "2d")]) | |
322 | ||
323 | (define_mode_attr Vmtype [(V8QI ".8b") (V16QI ".16b") | |
324 | (V4HI ".4h") (V8HI ".8h") | |
325 | (V2SI ".2s") (V4SI ".4s") | |
326 | (V2DI ".2d") (V2SF ".2s") | |
327 | (V4SF ".4s") (V2DF ".2d") | |
328 | (DI "") (SI "") | |
329 | (HI "") (QI "") | |
889b9412 JG |
330 | (TI "") (SF "") |
331 | (DF "")]) | |
43e9d192 IB |
332 | |
333 | ;; Register suffix narrowed modes for VQN. | |
334 | (define_mode_attr Vmntype [(V8HI ".8b") (V4SI ".4h") | |
335 | (V2DI ".2s") | |
336 | (DI "") (SI "") | |
337 | (HI "")]) | |
338 | ||
339 | ;; Mode-to-individual element type mapping. | |
340 | (define_mode_attr Vetype [(V8QI "b") (V16QI "b") | |
341 | (V4HI "h") (V8HI "h") | |
342 | (V2SI "s") (V4SI "s") | |
343 | (V2DI "d") (V2SF "s") | |
344 | (V4SF "s") (V2DF "d") | |
345 | (QI "b") (HI "h") | |
346 | (SI "s") (DI "d")]) | |
347 | ||
348 | ;; Mode-to-bitwise operation type mapping. | |
349 | (define_mode_attr Vbtype [(V8QI "8b") (V16QI "16b") | |
350 | (V4HI "8b") (V8HI "16b") | |
351 | (V2SI "8b") (V4SI "16b") | |
352 | (V2DI "16b") (V2SF "8b") | |
353 | (V4SF "16b") (V2DF "16b")]) | |
354 | ||
355 | ;; Define element mode for each vector mode. | |
356 | (define_mode_attr VEL [(V8QI "QI") (V16QI "QI") | |
357 | (V4HI "HI") (V8HI "HI") | |
358 | (V2SI "SI") (V4SI "SI") | |
359 | (DI "DI") (V2DI "DI") | |
360 | (V2SF "SF") (V4SF "SF") | |
361 | (V2DF "DF") | |
362 | (SI "SI") (HI "HI") | |
363 | (QI "QI")]) | |
364 | ||
b7d7d917 TB |
365 | ;; Define container mode for lane selection. |
366 | (define_mode_attr VCOND [(V4HI "V4HI") (V8HI "V4HI") | |
367 | (V2SI "V2SI") (V4SI "V2SI") | |
368 | (DI "DI") (V2DI "DI") | |
369 | (V2SF "V2SF") (V4SF "V2SF") | |
370 | (V2DF "DF")]) | |
371 | ||
372 | ;; Define container mode for lane selection. | |
373 | (define_mode_attr VCONQ [(V8QI "V16QI") (V16QI "V16QI") | |
374 | (V4HI "V8HI") (V8HI "V8HI") | |
375 | (V2SI "V4SI") (V4SI "V4SI") | |
376 | (DI "V2DI") (V2DI "V2DI") | |
377 | (V2SF "V2SF") (V4SF "V4SF") | |
378 | (V2DF "V2DF") (SI "V4SI") | |
379 | (HI "V8HI") (QI "V16QI")]) | |
380 | ||
43e9d192 IB |
381 | ;; Define container mode for lane selection. |
382 | (define_mode_attr VCON [(V8QI "V16QI") (V16QI "V16QI") | |
383 | (V4HI "V8HI") (V8HI "V8HI") | |
384 | (V2SI "V4SI") (V4SI "V4SI") | |
385 | (DI "V2DI") (V2DI "V2DI") | |
91bd4114 | 386 | (V2SF "V4SF") (V4SF "V4SF") |
43e9d192 IB |
387 | (V2DF "V2DF") (SI "V4SI") |
388 | (HI "V8HI") (QI "V16QI")]) | |
389 | ||
390 | ;; Half modes of all vector modes. | |
391 | (define_mode_attr VHALF [(V8QI "V4QI") (V16QI "V8QI") | |
392 | (V4HI "V2HI") (V8HI "V4HI") | |
393 | (V2SI "SI") (V4SI "V2SI") | |
394 | (V2DI "DI") (V2SF "SF") | |
395 | (V4SF "V2SF") (V2DF "DF")]) | |
396 | ||
397 | ;; Double modes of vector modes. | |
398 | (define_mode_attr VDBL [(V8QI "V16QI") (V4HI "V8HI") | |
399 | (V2SI "V4SI") (V2SF "V4SF") | |
400 | (SI "V2SI") (DI "V2DI") | |
401 | (DF "V2DF")]) | |
402 | ||
403 | ;; Double modes of vector modes (lower case). | |
404 | (define_mode_attr Vdbl [(V8QI "v16qi") (V4HI "v8hi") | |
405 | (V2SI "v4si") (V2SF "v4sf") | |
8b033a8a SN |
406 | (SI "v2si") (DI "v2di") |
407 | (DF "v2df")]) | |
43e9d192 IB |
408 | |
409 | ;; Narrowed modes for VDN. | |
410 | (define_mode_attr VNARROWD [(V4HI "V8QI") (V2SI "V4HI") | |
411 | (DI "V2SI")]) | |
412 | ||
413 | ;; Narrowed double-modes for VQN (Used for XTN). | |
414 | (define_mode_attr VNARROWQ [(V8HI "V8QI") (V4SI "V4HI") | |
415 | (V2DI "V2SI") | |
416 | (DI "SI") (SI "HI") | |
417 | (HI "QI")]) | |
418 | ||
419 | ;; Narrowed quad-modes for VQN (Used for XTN2). | |
420 | (define_mode_attr VNARROWQ2 [(V8HI "V16QI") (V4SI "V8HI") | |
421 | (V2DI "V4SI")]) | |
422 | ||
423 | ;; Register suffix narrowed modes for VQN. | |
424 | (define_mode_attr Vntype [(V8HI "8b") (V4SI "4h") | |
425 | (V2DI "2s")]) | |
426 | ||
427 | ;; Register suffix narrowed modes for VQN. | |
428 | (define_mode_attr V2ntype [(V8HI "16b") (V4SI "8h") | |
429 | (V2DI "4s")]) | |
430 | ||
431 | ;; Widened modes of vector modes. | |
432 | (define_mode_attr VWIDE [(V8QI "V8HI") (V4HI "V4SI") | |
433 | (V2SI "V2DI") (V16QI "V8HI") | |
434 | (V8HI "V4SI") (V4SI "V2DI") | |
435 | (HI "SI") (SI "DI")] | |
436 | ||
437 | ) | |
438 | ||
439 | ;; Widened mode register suffixes for VDW/VQW. | |
440 | (define_mode_attr Vwtype [(V8QI "8h") (V4HI "4s") | |
441 | (V2SI "2d") (V16QI "8h") | |
442 | (V8HI "4s") (V4SI "2d")]) | |
443 | ||
444 | ;; Widened mode register suffixes for VDW/VQW. | |
445 | (define_mode_attr Vmwtype [(V8QI ".8h") (V4HI ".4s") | |
446 | (V2SI ".2d") (V16QI ".8h") | |
447 | (V8HI ".4s") (V4SI ".2d") | |
448 | (SI "") (HI "")]) | |
449 | ||
450 | ;; Lower part register suffixes for VQW. | |
451 | (define_mode_attr Vhalftype [(V16QI "8b") (V8HI "4h") | |
452 | (V4SI "2s")]) | |
453 | ||
454 | ;; Define corresponding core/FP element mode for each vector mode. | |
455 | (define_mode_attr vw [(V8QI "w") (V16QI "w") | |
456 | (V4HI "w") (V8HI "w") | |
457 | (V2SI "w") (V4SI "w") | |
458 | (DI "x") (V2DI "x") | |
459 | (V2SF "s") (V4SF "s") | |
460 | (V2DF "d")]) | |
461 | ||
66adb8eb JG |
462 | ;; Corresponding core element mode for each vector mode. This is a |
463 | ;; variation on <vw> mapping FP modes to GP regs. | |
464 | (define_mode_attr vwcore [(V8QI "w") (V16QI "w") | |
465 | (V4HI "w") (V8HI "w") | |
466 | (V2SI "w") (V4SI "w") | |
467 | (DI "x") (V2DI "x") | |
468 | (V2SF "w") (V4SF "w") | |
469 | (V2DF "x")]) | |
470 | ||
43e9d192 IB |
471 | ;; Double vector types for ALLX. |
472 | (define_mode_attr Vallxd [(QI "8b") (HI "4h") (SI "2s")]) | |
473 | ||
474 | ;; Mode of result of comparison operations. | |
475 | (define_mode_attr V_cmp_result [(V8QI "V8QI") (V16QI "V16QI") | |
476 | (V4HI "V4HI") (V8HI "V8HI") | |
477 | (V2SI "V2SI") (V4SI "V4SI") | |
88b08073 | 478 | (DI "DI") (V2DI "V2DI") |
43e9d192 | 479 | (V2SF "V2SI") (V4SF "V4SI") |
889b9412 JG |
480 | (V2DF "V2DI") (DF "DI") |
481 | (SF "SI")]) | |
43e9d192 | 482 | |
70c67693 JG |
483 | ;; Lower case mode of results of comparison operations. |
484 | (define_mode_attr v_cmp_result [(V8QI "v8qi") (V16QI "v16qi") | |
485 | (V4HI "v4hi") (V8HI "v8hi") | |
486 | (V2SI "v2si") (V4SI "v4si") | |
487 | (DI "di") (V2DI "v2di") | |
488 | (V2SF "v2si") (V4SF "v4si") | |
889b9412 JG |
489 | (V2DF "v2di") (DF "di") |
490 | (SF "si")]) | |
70c67693 | 491 | |
43e9d192 IB |
492 | ;; Vm for lane instructions is restricted to FP_LO_REGS. |
493 | (define_mode_attr vwx [(V4HI "x") (V8HI "x") (HI "x") | |
494 | (V2SI "w") (V4SI "w") (SI "w")]) | |
495 | ||
496 | (define_mode_attr Vendreg [(OI "T") (CI "U") (XI "V")]) | |
497 | ||
498 | (define_mode_attr nregs [(OI "2") (CI "3") (XI "4")]) | |
499 | ||
500 | (define_mode_attr VRL2 [(V8QI "V32QI") (V4HI "V16HI") | |
501 | (V2SI "V8SI") (V2SF "V8SF") | |
502 | (DI "V4DI") (DF "V4DF") | |
503 | (V16QI "V32QI") (V8HI "V16HI") | |
504 | (V4SI "V8SI") (V4SF "V8SF") | |
505 | (V2DI "V4DI") (V2DF "V4DF")]) | |
506 | ||
507 | (define_mode_attr VRL3 [(V8QI "V48QI") (V4HI "V24HI") | |
508 | (V2SI "V12SI") (V2SF "V12SF") | |
509 | (DI "V6DI") (DF "V6DF") | |
510 | (V16QI "V48QI") (V8HI "V24HI") | |
511 | (V4SI "V12SI") (V4SF "V12SF") | |
512 | (V2DI "V6DI") (V2DF "V6DF")]) | |
513 | ||
514 | (define_mode_attr VRL4 [(V8QI "V64QI") (V4HI "V32HI") | |
515 | (V2SI "V16SI") (V2SF "V16SF") | |
516 | (DI "V8DI") (DF "V8DF") | |
517 | (V16QI "V64QI") (V8HI "V32HI") | |
518 | (V4SI "V16SI") (V4SF "V16SF") | |
519 | (V2DI "V8DI") (V2DF "V8DF")]) | |
520 | ||
521 | (define_mode_attr VSTRUCT_DREG [(OI "TI") (CI "EI") (XI "OI")]) | |
522 | ||
0462169c SN |
523 | ;; Mode for atomic operation suffixes |
524 | (define_mode_attr atomic_sfx | |
525 | [(QI "b") (HI "h") (SI "") (DI "")]) | |
526 | ||
42fc9a7f JG |
527 | (define_mode_attr fcvt_target [(V2DF "v2di") (V4SF "v4si") (V2SF "v2si")]) |
528 | (define_mode_attr FCVT_TARGET [(V2DF "V2DI") (V4SF "V4SI") (V2SF "V2SI")]) | |
529 | ||
91bd4114 JG |
530 | (define_mode_attr VSWAP_WIDTH [(V8QI "V16QI") (V16QI "V8QI") |
531 | (V4HI "V8HI") (V8HI "V4HI") | |
532 | (V2SI "V4SI") (V4SI "V2SI") | |
533 | (DI "V2DI") (V2DI "DI") | |
534 | (V2SF "V4SF") (V4SF "V2SF") | |
535 | (DF "V2DF") (V2DF "DF")]) | |
536 | ||
537 | (define_mode_attr vswap_width_name [(V8QI "to_128") (V16QI "to_64") | |
538 | (V4HI "to_128") (V8HI "to_64") | |
539 | (V2SI "to_128") (V4SI "to_64") | |
540 | (DI "to_128") (V2DI "to_64") | |
541 | (V2SF "to_128") (V4SF "to_64") | |
542 | (DF "to_128") (V2DF "to_64")]) | |
543 | ||
43e9d192 IB |
544 | ;; ------------------------------------------------------------------- |
545 | ;; Code Iterators | |
546 | ;; ------------------------------------------------------------------- | |
547 | ||
548 | ;; This code iterator allows the various shifts supported on the core | |
549 | (define_code_iterator SHIFT [ashift ashiftrt lshiftrt rotatert]) | |
550 | ||
551 | ;; This code iterator allows the shifts supported in arithmetic instructions | |
552 | (define_code_iterator ASHIFT [ashift ashiftrt lshiftrt]) | |
553 | ||
554 | ;; Code iterator for logical operations | |
555 | (define_code_iterator LOGICAL [and ior xor]) | |
556 | ||
557 | ;; Code iterator for sign/zero extension | |
558 | (define_code_iterator ANY_EXTEND [sign_extend zero_extend]) | |
559 | ||
560 | ;; All division operations (signed/unsigned) | |
561 | (define_code_iterator ANY_DIV [div udiv]) | |
562 | ||
563 | ;; Code iterator for sign/zero extraction | |
564 | (define_code_iterator ANY_EXTRACT [sign_extract zero_extract]) | |
565 | ||
566 | ;; Code iterator for equality comparisons | |
567 | (define_code_iterator EQL [eq ne]) | |
568 | ||
569 | ;; Code iterator for less-than and greater/equal-to | |
570 | (define_code_iterator LTGE [lt ge]) | |
571 | ||
572 | ;; Iterator for __sync_<op> operations that where the operation can be | |
573 | ;; represented directly RTL. This is all of the sync operations bar | |
574 | ;; nand. | |
0462169c | 575 | (define_code_iterator atomic_op [plus minus ior xor and]) |
43e9d192 IB |
576 | |
577 | ;; Iterator for integer conversions | |
578 | (define_code_iterator FIXUORS [fix unsigned_fix]) | |
579 | ||
1709ff9b JG |
580 | ;; Iterator for float conversions |
581 | (define_code_iterator FLOATUORS [float unsigned_float]) | |
582 | ||
43e9d192 IB |
583 | ;; Code iterator for variants of vector max and min. |
584 | (define_code_iterator MAXMIN [smax smin umax umin]) | |
585 | ||
998eaf97 JG |
586 | (define_code_iterator FMAXMIN [smax smin]) |
587 | ||
43e9d192 IB |
588 | ;; Code iterator for variants of vector max and min. |
589 | (define_code_iterator ADDSUB [plus minus]) | |
590 | ||
591 | ;; Code iterator for variants of vector saturating binary ops. | |
592 | (define_code_iterator BINQOPS [ss_plus us_plus ss_minus us_minus]) | |
593 | ||
594 | ;; Code iterator for variants of vector saturating unary ops. | |
595 | (define_code_iterator UNQOPS [ss_neg ss_abs]) | |
596 | ||
597 | ;; Code iterator for signed variants of vector saturating binary ops. | |
598 | (define_code_iterator SBINQOPS [ss_plus ss_minus]) | |
599 | ||
889b9412 JG |
600 | ;; Comparison operators for <F>CM. |
601 | (define_code_iterator COMPARISONS [lt le eq ge gt]) | |
602 | ||
603 | ;; Unsigned comparison operators. | |
604 | (define_code_iterator UCOMPARISONS [ltu leu geu gtu]) | |
605 | ||
75dd5ace JG |
606 | ;; Unsigned comparison operators. |
607 | (define_code_iterator FAC_COMPARISONS [lt le ge gt]) | |
608 | ||
43e9d192 IB |
609 | ;; ------------------------------------------------------------------- |
610 | ;; Code Attributes | |
611 | ;; ------------------------------------------------------------------- | |
612 | ;; Map rtl objects to optab names | |
613 | (define_code_attr optab [(ashift "ashl") | |
614 | (ashiftrt "ashr") | |
615 | (lshiftrt "lshr") | |
616 | (rotatert "rotr") | |
617 | (sign_extend "extend") | |
618 | (zero_extend "zero_extend") | |
619 | (sign_extract "extv") | |
620 | (zero_extract "extzv") | |
384be29f JG |
621 | (fix "fix") |
622 | (unsigned_fix "fixuns") | |
1709ff9b JG |
623 | (float "float") |
624 | (unsigned_float "floatuns") | |
43e9d192 IB |
625 | (and "and") |
626 | (ior "ior") | |
627 | (xor "xor") | |
628 | (not "one_cmpl") | |
629 | (neg "neg") | |
630 | (plus "add") | |
631 | (minus "sub") | |
632 | (ss_plus "qadd") | |
633 | (us_plus "qadd") | |
634 | (ss_minus "qsub") | |
635 | (us_minus "qsub") | |
636 | (ss_neg "qneg") | |
637 | (ss_abs "qabs") | |
638 | (eq "eq") | |
639 | (ne "ne") | |
640 | (lt "lt") | |
889b9412 JG |
641 | (ge "ge") |
642 | (le "le") | |
643 | (gt "gt") | |
644 | (ltu "ltu") | |
645 | (leu "leu") | |
646 | (geu "geu") | |
647 | (gtu "gtu")]) | |
648 | ||
649 | ;; For comparison operators we use the FCM* and CM* instructions. | |
650 | ;; As there are no CMLE or CMLT instructions which act on 3 vector | |
651 | ;; operands, we must use CMGE or CMGT and swap the order of the | |
652 | ;; source operands. | |
653 | ||
654 | (define_code_attr n_optab [(lt "gt") (le "ge") (eq "eq") (ge "ge") (gt "gt") | |
655 | (ltu "hi") (leu "hs") (geu "hs") (gtu "hi")]) | |
656 | (define_code_attr cmp_1 [(lt "2") (le "2") (eq "1") (ge "1") (gt "1") | |
657 | (ltu "2") (leu "2") (geu "1") (gtu "1")]) | |
658 | (define_code_attr cmp_2 [(lt "1") (le "1") (eq "2") (ge "2") (gt "2") | |
659 | (ltu "1") (leu "1") (geu "2") (gtu "2")]) | |
660 | ||
661 | (define_code_attr CMP [(lt "LT") (le "LE") (eq "EQ") (ge "GE") (gt "GT") | |
662 | (ltu "LTU") (leu "LEU") (geu "GEU") (gtu "GTU")]) | |
43e9d192 | 663 | |
384be29f JG |
664 | (define_code_attr fix_trunc_optab [(fix "fix_trunc") |
665 | (unsigned_fix "fixuns_trunc")]) | |
666 | ||
43e9d192 IB |
667 | ;; Optab prefix for sign/zero-extending operations |
668 | (define_code_attr su_optab [(sign_extend "") (zero_extend "u") | |
669 | (div "") (udiv "u") | |
670 | (fix "") (unsigned_fix "u") | |
1709ff9b | 671 | (float "s") (unsigned_float "u") |
43e9d192 IB |
672 | (ss_plus "s") (us_plus "u") |
673 | (ss_minus "s") (us_minus "u")]) | |
674 | ||
675 | ;; Similar for the instruction mnemonics | |
676 | (define_code_attr shift [(ashift "lsl") (ashiftrt "asr") | |
677 | (lshiftrt "lsr") (rotatert "ror")]) | |
678 | ||
679 | ;; Map shift operators onto underlying bit-field instructions | |
680 | (define_code_attr bfshift [(ashift "ubfiz") (ashiftrt "sbfx") | |
681 | (lshiftrt "ubfx") (rotatert "extr")]) | |
682 | ||
683 | ;; Logical operator instruction mnemonics | |
684 | (define_code_attr logical [(and "and") (ior "orr") (xor "eor")]) | |
685 | ||
686 | ;; Similar, but when not(op) | |
687 | (define_code_attr nlogical [(and "bic") (ior "orn") (xor "eon")]) | |
688 | ||
689 | ;; Sign- or zero-extending load | |
690 | (define_code_attr ldrxt [(sign_extend "ldrs") (zero_extend "ldr")]) | |
691 | ||
692 | ;; Sign- or zero-extending data-op | |
693 | (define_code_attr su [(sign_extend "s") (zero_extend "u") | |
694 | (sign_extract "s") (zero_extract "u") | |
695 | (fix "s") (unsigned_fix "u") | |
998eaf97 JG |
696 | (div "s") (udiv "u") |
697 | (smax "s") (umax "u") | |
698 | (smin "s") (umin "u")]) | |
43e9d192 IB |
699 | |
700 | ;; Emit cbz/cbnz depending on comparison type. | |
701 | (define_code_attr cbz [(eq "cbz") (ne "cbnz") (lt "cbnz") (ge "cbz")]) | |
702 | ||
703 | ;; Emit tbz/tbnz depending on comparison type. | |
704 | (define_code_attr tbz [(eq "tbz") (ne "tbnz") (lt "tbnz") (ge "tbz")]) | |
705 | ||
706 | ;; Max/min attributes. | |
998eaf97 JG |
707 | (define_code_attr maxmin [(smax "max") |
708 | (smin "min") | |
709 | (umax "max") | |
710 | (umin "min")]) | |
43e9d192 IB |
711 | |
712 | ;; MLA/MLS attributes. | |
713 | (define_code_attr as [(ss_plus "a") (ss_minus "s")]) | |
714 | ||
0462169c SN |
715 | ;; Atomic operations |
716 | (define_code_attr atomic_optab | |
717 | [(ior "or") (xor "xor") (and "and") (plus "add") (minus "sub")]) | |
718 | ||
719 | (define_code_attr atomic_op_operand | |
720 | [(ior "aarch64_logical_operand") | |
721 | (xor "aarch64_logical_operand") | |
722 | (and "aarch64_logical_operand") | |
723 | (plus "aarch64_plus_operand") | |
724 | (minus "aarch64_plus_operand")]) | |
43e9d192 IB |
725 | |
726 | ;; ------------------------------------------------------------------- | |
727 | ;; Int Iterators. | |
728 | ;; ------------------------------------------------------------------- | |
729 | (define_int_iterator MAXMINV [UNSPEC_UMAXV UNSPEC_UMINV | |
730 | UNSPEC_SMAXV UNSPEC_SMINV]) | |
731 | ||
998eaf97 JG |
732 | (define_int_iterator FMAXMINV [UNSPEC_FMAXV UNSPEC_FMINV |
733 | UNSPEC_FMAXNMV UNSPEC_FMINNMV]) | |
43e9d192 | 734 | |
36054fab JG |
735 | (define_int_iterator SUADDV [UNSPEC_SADDV UNSPEC_UADDV]) |
736 | ||
43e9d192 IB |
737 | (define_int_iterator HADDSUB [UNSPEC_SHADD UNSPEC_UHADD |
738 | UNSPEC_SRHADD UNSPEC_URHADD | |
739 | UNSPEC_SHSUB UNSPEC_UHSUB | |
740 | UNSPEC_SRHSUB UNSPEC_URHSUB]) | |
741 | ||
742 | ||
743 | (define_int_iterator ADDSUBHN [UNSPEC_ADDHN UNSPEC_RADDHN | |
744 | UNSPEC_SUBHN UNSPEC_RSUBHN]) | |
745 | ||
746 | (define_int_iterator ADDSUBHN2 [UNSPEC_ADDHN2 UNSPEC_RADDHN2 | |
747 | UNSPEC_SUBHN2 UNSPEC_RSUBHN2]) | |
748 | ||
998eaf97 | 749 | (define_int_iterator FMAXMIN_UNS [UNSPEC_FMAX UNSPEC_FMIN]) |
43e9d192 IB |
750 | |
751 | (define_int_iterator VQDMULH [UNSPEC_SQDMULH UNSPEC_SQRDMULH]) | |
752 | ||
753 | (define_int_iterator USSUQADD [UNSPEC_SUQADD UNSPEC_USQADD]) | |
754 | ||
755 | (define_int_iterator SUQMOVN [UNSPEC_SQXTN UNSPEC_UQXTN]) | |
756 | ||
757 | (define_int_iterator VSHL [UNSPEC_SSHL UNSPEC_USHL | |
758 | UNSPEC_SRSHL UNSPEC_URSHL]) | |
759 | ||
760 | (define_int_iterator VSHLL [UNSPEC_SSHLL UNSPEC_USHLL]) | |
761 | ||
762 | (define_int_iterator VQSHL [UNSPEC_SQSHL UNSPEC_UQSHL | |
763 | UNSPEC_SQRSHL UNSPEC_UQRSHL]) | |
764 | ||
765 | (define_int_iterator VSRA [UNSPEC_SSRA UNSPEC_USRA | |
766 | UNSPEC_SRSRA UNSPEC_URSRA]) | |
767 | ||
768 | (define_int_iterator VSLRI [UNSPEC_SSLI UNSPEC_USLI | |
769 | UNSPEC_SSRI UNSPEC_USRI]) | |
770 | ||
771 | ||
772 | (define_int_iterator VRSHR_N [UNSPEC_SRSHR UNSPEC_URSHR]) | |
773 | ||
774 | (define_int_iterator VQSHL_N [UNSPEC_SQSHLU UNSPEC_SQSHL UNSPEC_UQSHL]) | |
775 | ||
776 | (define_int_iterator VQSHRN_N [UNSPEC_SQSHRUN UNSPEC_SQRSHRUN | |
777 | UNSPEC_SQSHRN UNSPEC_UQSHRN | |
778 | UNSPEC_SQRSHRN UNSPEC_UQRSHRN]) | |
779 | ||
cc4d934f JG |
780 | (define_int_iterator PERMUTE [UNSPEC_ZIP1 UNSPEC_ZIP2 |
781 | UNSPEC_TRN1 UNSPEC_TRN2 | |
782 | UNSPEC_UZP1 UNSPEC_UZP2]) | |
43e9d192 | 783 | |
42fc9a7f | 784 | (define_int_iterator FRINT [UNSPEC_FRINTZ UNSPEC_FRINTP UNSPEC_FRINTM |
0659ce6f JG |
785 | UNSPEC_FRINTN UNSPEC_FRINTI UNSPEC_FRINTX |
786 | UNSPEC_FRINTA]) | |
42fc9a7f JG |
787 | |
788 | (define_int_iterator FCVT [UNSPEC_FRINTZ UNSPEC_FRINTP UNSPEC_FRINTM | |
ce966824 | 789 | UNSPEC_FRINTA UNSPEC_FRINTN]) |
42fc9a7f | 790 | |
0050faf8 JG |
791 | (define_int_iterator FRECP [UNSPEC_FRECPE UNSPEC_FRECPX]) |
792 | ||
43e9d192 IB |
793 | ;; ------------------------------------------------------------------- |
794 | ;; Int Iterators Attributes. | |
795 | ;; ------------------------------------------------------------------- | |
998eaf97 JG |
796 | (define_int_attr maxmin_uns [(UNSPEC_UMAXV "umax") |
797 | (UNSPEC_UMINV "umin") | |
798 | (UNSPEC_SMAXV "smax") | |
799 | (UNSPEC_SMINV "smin") | |
800 | (UNSPEC_FMAX "smax_nan") | |
801 | (UNSPEC_FMAXNMV "smax") | |
802 | (UNSPEC_FMAXV "smax_nan") | |
803 | (UNSPEC_FMIN "smin_nan") | |
804 | (UNSPEC_FMINNMV "smin") | |
805 | (UNSPEC_FMINV "smin_nan")]) | |
806 | ||
807 | (define_int_attr maxmin_uns_op [(UNSPEC_UMAXV "umax") | |
808 | (UNSPEC_UMINV "umin") | |
809 | (UNSPEC_SMAXV "smax") | |
810 | (UNSPEC_SMINV "smin") | |
811 | (UNSPEC_FMAX "fmax") | |
812 | (UNSPEC_FMAXNMV "fmaxnm") | |
813 | (UNSPEC_FMAXV "fmax") | |
814 | (UNSPEC_FMIN "fmin") | |
815 | (UNSPEC_FMINNMV "fminnm") | |
816 | (UNSPEC_FMINV "fmin")]) | |
43e9d192 IB |
817 | |
818 | (define_int_attr sur [(UNSPEC_SHADD "s") (UNSPEC_UHADD "u") | |
819 | (UNSPEC_SRHADD "sr") (UNSPEC_URHADD "ur") | |
820 | (UNSPEC_SHSUB "s") (UNSPEC_UHSUB "u") | |
821 | (UNSPEC_SRHSUB "sr") (UNSPEC_URHSUB "ur") | |
822 | (UNSPEC_ADDHN "") (UNSPEC_RADDHN "r") | |
823 | (UNSPEC_SUBHN "") (UNSPEC_RSUBHN "r") | |
824 | (UNSPEC_ADDHN2 "") (UNSPEC_RADDHN2 "r") | |
825 | (UNSPEC_SUBHN2 "") (UNSPEC_RSUBHN2 "r") | |
826 | (UNSPEC_SQXTN "s") (UNSPEC_UQXTN "u") | |
827 | (UNSPEC_USQADD "us") (UNSPEC_SUQADD "su") | |
36054fab | 828 | (UNSPEC_SADDV "s") (UNSPEC_UADDV "u") |
43e9d192 IB |
829 | (UNSPEC_SSLI "s") (UNSPEC_USLI "u") |
830 | (UNSPEC_SSRI "s") (UNSPEC_USRI "u") | |
831 | (UNSPEC_USRA "u") (UNSPEC_SSRA "s") | |
832 | (UNSPEC_URSRA "ur") (UNSPEC_SRSRA "sr") | |
833 | (UNSPEC_URSHR "ur") (UNSPEC_SRSHR "sr") | |
834 | (UNSPEC_SQSHLU "s") (UNSPEC_SQSHL "s") | |
835 | (UNSPEC_UQSHL "u") | |
836 | (UNSPEC_SQSHRUN "s") (UNSPEC_SQRSHRUN "s") | |
837 | (UNSPEC_SQSHRN "s") (UNSPEC_UQSHRN "u") | |
838 | (UNSPEC_SQRSHRN "s") (UNSPEC_UQRSHRN "u") | |
839 | (UNSPEC_USHL "u") (UNSPEC_SSHL "s") | |
840 | (UNSPEC_USHLL "u") (UNSPEC_SSHLL "s") | |
841 | (UNSPEC_URSHL "ur") (UNSPEC_SRSHL "sr") | |
842 | (UNSPEC_UQRSHL "u") (UNSPEC_SQRSHL "s") | |
843 | ]) | |
844 | ||
845 | (define_int_attr r [(UNSPEC_SQDMULH "") (UNSPEC_SQRDMULH "r") | |
846 | (UNSPEC_SQSHRUN "") (UNSPEC_SQRSHRUN "r") | |
847 | (UNSPEC_SQSHRN "") (UNSPEC_UQSHRN "") | |
848 | (UNSPEC_SQRSHRN "r") (UNSPEC_UQRSHRN "r") | |
849 | (UNSPEC_SQSHL "") (UNSPEC_UQSHL "") | |
850 | (UNSPEC_SQRSHL "r")(UNSPEC_UQRSHL "r") | |
851 | ]) | |
852 | ||
853 | (define_int_attr lr [(UNSPEC_SSLI "l") (UNSPEC_USLI "l") | |
854 | (UNSPEC_SSRI "r") (UNSPEC_USRI "r")]) | |
855 | ||
856 | (define_int_attr u [(UNSPEC_SQSHLU "u") (UNSPEC_SQSHL "") (UNSPEC_UQSHL "") | |
857 | (UNSPEC_SQSHRUN "u") (UNSPEC_SQRSHRUN "u") | |
858 | (UNSPEC_SQSHRN "") (UNSPEC_UQSHRN "") | |
859 | (UNSPEC_SQRSHRN "") (UNSPEC_UQRSHRN "")]) | |
860 | ||
861 | (define_int_attr addsub [(UNSPEC_SHADD "add") | |
862 | (UNSPEC_UHADD "add") | |
863 | (UNSPEC_SRHADD "add") | |
864 | (UNSPEC_URHADD "add") | |
865 | (UNSPEC_SHSUB "sub") | |
866 | (UNSPEC_UHSUB "sub") | |
867 | (UNSPEC_SRHSUB "sub") | |
868 | (UNSPEC_URHSUB "sub") | |
869 | (UNSPEC_ADDHN "add") | |
870 | (UNSPEC_SUBHN "sub") | |
871 | (UNSPEC_RADDHN "add") | |
872 | (UNSPEC_RSUBHN "sub") | |
873 | (UNSPEC_ADDHN2 "add") | |
874 | (UNSPEC_SUBHN2 "sub") | |
875 | (UNSPEC_RADDHN2 "add") | |
876 | (UNSPEC_RSUBHN2 "sub")]) | |
877 | ||
43e9d192 IB |
878 | (define_int_attr offsetlr [(UNSPEC_SSLI "1") (UNSPEC_USLI "1") |
879 | (UNSPEC_SSRI "0") (UNSPEC_USRI "0")]) | |
880 | ||
42fc9a7f JG |
881 | ;; Standard pattern names for floating-point rounding instructions. |
882 | (define_int_attr frint_pattern [(UNSPEC_FRINTZ "btrunc") | |
883 | (UNSPEC_FRINTP "ceil") | |
884 | (UNSPEC_FRINTM "floor") | |
885 | (UNSPEC_FRINTI "nearbyint") | |
886 | (UNSPEC_FRINTX "rint") | |
0659ce6f JG |
887 | (UNSPEC_FRINTA "round") |
888 | (UNSPEC_FRINTN "frintn")]) | |
42fc9a7f JG |
889 | |
890 | ;; frint suffix for floating-point rounding instructions. | |
891 | (define_int_attr frint_suffix [(UNSPEC_FRINTZ "z") (UNSPEC_FRINTP "p") | |
892 | (UNSPEC_FRINTM "m") (UNSPEC_FRINTI "i") | |
0659ce6f JG |
893 | (UNSPEC_FRINTX "x") (UNSPEC_FRINTA "a") |
894 | (UNSPEC_FRINTN "n")]) | |
42fc9a7f JG |
895 | |
896 | (define_int_attr fcvt_pattern [(UNSPEC_FRINTZ "btrunc") (UNSPEC_FRINTA "round") | |
ce966824 JG |
897 | (UNSPEC_FRINTP "ceil") (UNSPEC_FRINTM "floor") |
898 | (UNSPEC_FRINTN "frintn")]) | |
42fc9a7f | 899 | |
cc4d934f JG |
900 | (define_int_attr perm_insn [(UNSPEC_ZIP1 "zip") (UNSPEC_ZIP2 "zip") |
901 | (UNSPEC_TRN1 "trn") (UNSPEC_TRN2 "trn") | |
902 | (UNSPEC_UZP1 "uzp") (UNSPEC_UZP2 "uzp")]) | |
903 | ||
904 | (define_int_attr perm_hilo [(UNSPEC_ZIP1 "1") (UNSPEC_ZIP2 "2") | |
905 | (UNSPEC_TRN1 "1") (UNSPEC_TRN2 "2") | |
906 | (UNSPEC_UZP1 "1") (UNSPEC_UZP2 "2")]) | |
0050faf8 JG |
907 | |
908 | (define_int_attr frecp_suffix [(UNSPEC_FRECPE "e") (UNSPEC_FRECPX "x")]) |