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43e9d192 1;; Machine description for AArch64 architecture.
a5544970 2;; Copyright (C) 2009-2019 Free Software Foundation, Inc.
43e9d192
IB		 3;; Contributed by ARM Ltd.
4;;
5;; This file is part of GCC.
6;;
7;; GCC is free software; you can redistribute it and/or modify it
8;; under the terms of the GNU General Public License as published by
9;; the Free Software Foundation; either version 3, or (at your option)
10;; any later version.
11;;
12;; GCC is distributed in the hope that it will be useful, but
13;; WITHOUT ANY WARRANTY; without even the implied warranty of
14;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15;; General Public License for more details.
16;;
17;; You should have received a copy of the GNU General Public License
18;; along with GCC; see the file COPYING3. If not see
19;; <http://www.gnu.org/licenses/>.
20
21;; -------------------------------------------------------------------
22;; Mode Iterators
23;; -------------------------------------------------------------------
24
25
26;; Iterator for General Purpose Integer registers (32- and 64-bit modes)
27(define_mode_iterator GPI [SI DI])
28
d7f33f07
JW		 29;; Iterator for HI, SI, DI, some instructions can only work on these modes.
30(define_mode_iterator GPI_I16 [(HI "AARCH64_ISA_F16") SI DI])
31
43e9d192
IB		 32;; Iterator for QI and HI modes
33(define_mode_iterator SHORT [QI HI])
34
35;; Iterator for all integer modes (up to 64-bit)
36(define_mode_iterator ALLI [QI HI SI DI])
37
c0111dc4
RE		 38;; Iterator for all integer modes (up to 128-bit)
39(define_mode_iterator ALLI_TI [QI HI SI DI TI])
40
43e9d192
IB		 41;; Iterator for all integer modes that can be extended (up to 64-bit)
42(define_mode_iterator ALLX [QI HI SI])
43
44;; Iterator for General Purpose Floating-point registers (32- and 64-bit modes)
45(define_mode_iterator GPF [SF DF])
46
d7f33f07
JW		 47;; Iterator for all scalar floating point modes (HF, SF, DF)
48(define_mode_iterator GPF_F16 [(HF "AARCH64_ISA_F16") SF DF])
49
90e6443f
TC		 50;; Iterator for all scalar floating point modes (HF, SF, DF)
51(define_mode_iterator GPF_HF [HF SF DF])
52
09fcd8e1
RR		 53;; Iterator for all scalar floating point modes (HF, SF, DF and TF)
54(define_mode_iterator GPF_TF_F16 [HF SF DF TF])
c2ec330c 55
922f9c25
AL		 56;; Double vector modes.
57(define_mode_iterator VDF [V2SF V4HF])
58
b4f50fd4
RR		 59;; Iterator for all scalar floating point modes (SF, DF and TF)
60(define_mode_iterator GPF_TF [SF DF TF])
61
43cacb12 62;; Integer Advanced SIMD modes.
43e9d192
IB		 63(define_mode_iterator VDQ_I [V8QI V16QI V4HI V8HI V2SI V4SI V2DI])
64
43cacb12 65;; Advanced SIMD and scalar, 64 & 128-bit container, all integer modes.
43e9d192
IB		 66(define_mode_iterator VSDQ_I [V8QI V16QI V4HI V8HI V2SI V4SI V2DI QI HI SI DI])
67
43cacb12
RS		 68;; Advanced SIMD and scalar, 64 & 128-bit container: all Advanced SIMD
69;; integer modes; 64-bit scalar integer mode.
43e9d192
IB		 70(define_mode_iterator VSDQ_I_DI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI DI])
71
72;; Double vector modes.
71a11456 73(define_mode_iterator VD [V8QI V4HI V4HF V2SI V2SF])
43e9d192 74
dfe1da23
JW		 75;; All modes stored in registers d0-d31.
76(define_mode_iterator DREG [V8QI V4HI V4HF V2SI V2SF DF])
77
78;; Copy of the above.
79(define_mode_iterator DREG2 [V8QI V4HI V4HF V2SI V2SF DF])
80
43cacb12 81;; Advanced SIMD, 64-bit container, all integer modes.
43e9d192
IB		 82(define_mode_iterator VD_BHSI [V8QI V4HI V2SI])
83
84;; 128 and 64-bit container; 8, 16, 32-bit vector integer modes
85(define_mode_iterator VDQ_BHSI [V8QI V16QI V4HI V8HI V2SI V4SI])
86
87;; Quad vector modes.
71a11456 88(define_mode_iterator VQ [V16QI V8HI V4SI V2DI V8HF V4SF V2DF])
43e9d192 89
9f5361c8
KT		 90;; Copy of the above.
91(define_mode_iterator VQ2 [V16QI V8HI V4SI V2DI V8HF V4SF V2DF])
92
d21052eb
TC		 93;; Quad integer vector modes.
94(define_mode_iterator VQ_I [V16QI V8HI V4SI V2DI])
95
51437269 96;; VQ without 2 element modes.
71a11456 97(define_mode_iterator VQ_NO2E [V16QI V8HI V4SI V8HF V4SF])
51437269
GW		 98
99;; Quad vector with only 2 element modes.
100(define_mode_iterator VQ_2E [V2DI V2DF])
101
28514dda
YZ		 102;; This mode iterator allows :P to be used for patterns that operate on
103;; addresses in different modes. In LP64, only DI will match, while in
104;; ILP32, either can match.
105(define_mode_iterator P [(SI "ptr_mode == SImode || Pmode == SImode")
106 (DI "ptr_mode == DImode || Pmode == DImode")])
107
43e9d192
IB		 108;; This mode iterator allows :PTR to be used for patterns that operate on
109;; pointer-sized quantities. Exactly one of the two alternatives will match.
28514dda 110(define_mode_iterator PTR [(SI "ptr_mode == SImode") (DI "ptr_mode == DImode")])
43e9d192 111
43cacb12 112;; Advanced SIMD Float modes suitable for moving, loading and storing.
862abc04
AL		 113(define_mode_iterator VDQF_F16 [V4HF V8HF V2SF V4SF V2DF])
114
43cacb12 115;; Advanced SIMD Float modes.
43e9d192 116(define_mode_iterator VDQF [V2SF V4SF V2DF])
daef0a8c
JW		 117(define_mode_iterator VHSDF [(V4HF "TARGET_SIMD_F16INST")
118 (V8HF "TARGET_SIMD_F16INST")
119 V2SF V4SF V2DF])
43e9d192 120
43cacb12 121;; Advanced SIMD Float modes, and DF.
daef0a8c
JW		 122(define_mode_iterator VHSDF_DF [(V4HF "TARGET_SIMD_F16INST")
123 (V8HF "TARGET_SIMD_F16INST")
124 V2SF V4SF V2DF DF])
d7f33f07
JW		 125(define_mode_iterator VHSDF_HSDF [(V4HF "TARGET_SIMD_F16INST")
126 (V8HF "TARGET_SIMD_F16INST")
127 V2SF V4SF V2DF
128 (HF "TARGET_SIMD_F16INST")
129 SF DF])
f421c516 130
43cacb12 131;; Advanced SIMD single Float modes.
828e70c1
JG		 132(define_mode_iterator VDQSF [V2SF V4SF])
133
03873eb9
AL		 134;; Quad vector Float modes with half/single elements.
135(define_mode_iterator VQ_HSF [V8HF V4SF])
136
fc21784d
JG		 137;; Modes suitable to use as the return type of a vcond expression.
138(define_mode_iterator VDQF_COND [V2SF V2SI V4SF V4SI V2DF V2DI])
139
43cacb12 140;; All scalar and Advanced SIMD Float modes.
889b9412
JG		 141(define_mode_iterator VALLF [V2SF V4SF V2DF SF DF])
142
43cacb12 143;; Advanced SIMD Float modes with 2 elements.
43e9d192
IB		 144(define_mode_iterator V2F [V2SF V2DF])
145
43cacb12 146;; All Advanced SIMD modes on which we support any arithmetic operations.
43e9d192
IB		 147(define_mode_iterator VALL [V8QI V16QI V4HI V8HI V2SI V4SI V2DI V2SF V4SF V2DF])
148
43cacb12 149;; All Advanced SIMD modes suitable for moving, loading, and storing.
71a11456
AL		 150(define_mode_iterator VALL_F16 [V8QI V16QI V4HI V8HI V2SI V4SI V2DI
151 V4HF V8HF V2SF V4SF V2DF])
152
88119b46
KT		 153;; The VALL_F16 modes except the 128-bit 2-element ones.
154(define_mode_iterator VALL_F16_NO_V2Q [V8QI V16QI V4HI V8HI V2SI V4SI
155 V4HF V8HF V2SF V4SF])
156
43cacb12 157;; All Advanced SIMD modes barring HF modes, plus DI.
a50344cb
TB		 158(define_mode_iterator VALLDI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI V2SF V4SF V2DF DI])
159
43cacb12 160;; All Advanced SIMD modes and DI.
71a11456
AL		 161(define_mode_iterator VALLDI_F16 [V8QI V16QI V4HI V8HI V2SI V4SI V2DI
162 V4HF V8HF V2SF V4SF V2DF DI])
163
43cacb12 164;; All Advanced SIMD modes, plus DI and DF.
46e778c4 165(define_mode_iterator VALLDIF [V8QI V16QI V4HI V8HI V2SI V4SI
7c369485 166 V2DI V4HF V8HF V2SF V4SF V2DF DI DF])
46e778c4 167
43cacb12 168;; Advanced SIMD modes for Integer reduction across lanes.
92835317
TB		 169(define_mode_iterator VDQV [V8QI V16QI V4HI V8HI V4SI V2DI])
170
43cacb12 171;; Advanced SIMD modes (except V2DI) for Integer reduction across lanes.
92835317 172(define_mode_iterator VDQV_S [V8QI V16QI V4HI V8HI V4SI])
43e9d192
IB		 173
174;; All double integer narrow-able modes.
175(define_mode_iterator VDN [V4HI V2SI DI])
176
177;; All quad integer narrow-able modes.
178(define_mode_iterator VQN [V8HI V4SI V2DI])
179
43cacb12
RS		 180;; Advanced SIMD and scalar 128-bit container: narrowable 16, 32, 64-bit
181;; integer modes
43e9d192
IB		 182(define_mode_iterator VSQN_HSDI [V8HI V4SI V2DI HI SI DI])
183
184;; All quad integer widen-able modes.
185(define_mode_iterator VQW [V16QI V8HI V4SI])
186
187;; Double vector modes for combines.
7c369485 188(define_mode_iterator VDC [V8QI V4HI V4HF V2SI V2SF DI DF])
43e9d192 189
43cacb12 190;; Advanced SIMD modes except double int.
43e9d192 191(define_mode_iterator VDQIF [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF V2DF])
703bbcdf
JW		 192(define_mode_iterator VDQIF_F16 [V8QI V16QI V4HI V8HI V2SI V4SI
193 V4HF V8HF V2SF V4SF V2DF])
43e9d192 194
43cacb12 195;; Advanced SIMD modes for S type.
58a3bd25
FY		 196(define_mode_iterator VDQ_SI [V2SI V4SI])
197
43cacb12 198;; Advanced SIMD modes for S and D.
2644d4d9
JW		 199(define_mode_iterator VDQ_SDI [V2SI V4SI V2DI])
200
43cacb12 201;; Advanced SIMD modes for H, S and D.
33d72b63
JW		 202(define_mode_iterator VDQ_HSDI [(V4HI "TARGET_SIMD_F16INST")
203 (V8HI "TARGET_SIMD_F16INST")
204 V2SI V4SI V2DI])
205
43cacb12 206;; Scalar and Advanced SIMD modes for S and D.
2644d4d9
JW		 207(define_mode_iterator VSDQ_SDI [V2SI V4SI V2DI SI DI])
208
43cacb12 209;; Scalar and Advanced SIMD modes for S and D, Advanced SIMD modes for H.
33d72b63
JW		 210(define_mode_iterator VSDQ_HSDI [(V4HI "TARGET_SIMD_F16INST")
211 (V8HI "TARGET_SIMD_F16INST")
68ad28c3
JW		 212 V2SI V4SI V2DI
213 (HI "TARGET_SIMD_F16INST")
214 SI DI])
33d72b63 215
43cacb12 216;; Advanced SIMD modes for Q and H types.
66adb8eb
JG		 217(define_mode_iterator VDQQH [V8QI V16QI V4HI V8HI])
218
43cacb12 219;; Advanced SIMD modes for H and S types.
43e9d192
IB		 220(define_mode_iterator VDQHS [V4HI V8HI V2SI V4SI])
221
43cacb12 222;; Advanced SIMD modes for H, S and D types.
c7f28cd5
KT		 223(define_mode_iterator VDQHSD [V4HI V8HI V2SI V4SI V2DI])
224
43cacb12 225;; Advanced SIMD and scalar integer modes for H and S.
43e9d192
IB		 226(define_mode_iterator VSDQ_HSI [V4HI V8HI V2SI V4SI HI SI])
227
43cacb12 228;; Advanced SIMD and scalar 64-bit container: 16, 32-bit integer modes.
43e9d192
IB		 229(define_mode_iterator VSD_HSI [V4HI V2SI HI SI])
230
43cacb12 231;; Advanced SIMD 64-bit container: 16, 32-bit integer modes.
43e9d192
IB		 232(define_mode_iterator VD_HSI [V4HI V2SI])
233
234;; Scalar 64-bit container: 16, 32-bit integer modes
235(define_mode_iterator SD_HSI [HI SI])
236
43cacb12 237;; Advanced SIMD 64-bit container: 16, 32-bit integer modes.
43e9d192
IB		 238(define_mode_iterator VQ_HSI [V8HI V4SI])
239
240;; All byte modes.
241(define_mode_iterator VB [V8QI V16QI])
242
5e32e83b
JW		 243;; 2 and 4 lane SI modes.
244(define_mode_iterator VS [V2SI V4SI])
245
43e9d192
IB		 246(define_mode_iterator TX [TI TF])
247
43cacb12 248;; Advanced SIMD opaque structure modes.
43e9d192
IB		 249(define_mode_iterator VSTRUCT [OI CI XI])
250
251;; Double scalar modes
252(define_mode_iterator DX [DI DF])
253
dfe1da23
JW		 254;; Duplicate of the above
255(define_mode_iterator DX2 [DI DF])
256
257;; Single scalar modes
258(define_mode_iterator SX [SI SF])
259
260;; Duplicate of the above
261(define_mode_iterator SX2 [SI SF])
262
263;; Single and double integer and float modes
264(define_mode_iterator DSX [DF DI SF SI])
265
266
43cacb12 267;; Modes available for Advanced SIMD <f>mul lane operations.
ab2e8f01
JW		 268(define_mode_iterator VMUL [V4HI V8HI V2SI V4SI
269 (V4HF "TARGET_SIMD_F16INST")
270 (V8HF "TARGET_SIMD_F16INST")
271 V2SF V4SF V2DF])
779aea46 272
43cacb12
RS		 273;; Modes available for Advanced SIMD <f>mul lane operations changing lane
274;; count.
779aea46
JG		 275(define_mode_iterator VMUL_CHANGE_NLANES [V4HI V8HI V2SI V4SI V2SF V4SF])
276
43cacb12
RS		 277;; All SVE vector modes.
278(define_mode_iterator SVE_ALL [VNx16QI VNx8HI VNx4SI VNx2DI
279 VNx8HF VNx4SF VNx2DF])
280
9f4cbab8
RS		 281;; All SVE vector structure modes.
282(define_mode_iterator SVE_STRUCT [VNx32QI VNx16HI VNx8SI VNx4DI
283 VNx16HF VNx8SF VNx4DF
284 VNx48QI VNx24HI VNx12SI VNx6DI
285 VNx24HF VNx12SF VNx6DF
286 VNx64QI VNx32HI VNx16SI VNx8DI
287 VNx32HF VNx16SF VNx8DF])
288
43cacb12
RS		 289;; All SVE vector modes that have 8-bit or 16-bit elements.
290(define_mode_iterator SVE_BH [VNx16QI VNx8HI VNx8HF])
291
292;; All SVE vector modes that have 8-bit, 16-bit or 32-bit elements.
293(define_mode_iterator SVE_BHS [VNx16QI VNx8HI VNx4SI VNx8HF VNx4SF])
294
295;; All SVE integer vector modes that have 8-bit, 16-bit or 32-bit elements.
296(define_mode_iterator SVE_BHSI [VNx16QI VNx8HI VNx4SI])
297
298;; All SVE integer vector modes that have 16-bit, 32-bit or 64-bit elements.
299(define_mode_iterator SVE_HSDI [VNx16QI VNx8HI VNx4SI])
300
301;; All SVE floating-point vector modes that have 16-bit or 32-bit elements.
302(define_mode_iterator SVE_HSF [VNx8HF VNx4SF])
303
304;; All SVE vector modes that have 32-bit or 64-bit elements.
305(define_mode_iterator SVE_SD [VNx4SI VNx2DI VNx4SF VNx2DF])
306
bfaa08b7
RS		 307;; All SVE vector modes that have 32-bit elements.
308(define_mode_iterator SVE_S [VNx4SI VNx4SF])
309
310;; All SVE vector modes that have 64-bit elements.
311(define_mode_iterator SVE_D [VNx2DI VNx2DF])
312
43cacb12
RS		 313;; All SVE integer vector modes that have 32-bit or 64-bit elements.
314(define_mode_iterator SVE_SDI [VNx4SI VNx2DI])
315
316;; All SVE integer vector modes.
317(define_mode_iterator SVE_I [VNx16QI VNx8HI VNx4SI VNx2DI])
318
319;; All SVE floating-point vector modes.
320(define_mode_iterator SVE_F [VNx8HF VNx4SF VNx2DF])
321
322;; All SVE predicate modes.
323(define_mode_iterator PRED_ALL [VNx16BI VNx8BI VNx4BI VNx2BI])
324
325;; SVE predicate modes that control 8-bit, 16-bit or 32-bit elements.
326(define_mode_iterator PRED_BHS [VNx16BI VNx8BI VNx4BI])
327
43e9d192
IB		 328;; ------------------------------------------------------------------
329;; Unspec enumerations for Advance SIMD. These could well go into
330;; aarch64.md but for their use in int_iterators here.
331;; ------------------------------------------------------------------
332
333(define_c_enum "unspec"
334 [
335 UNSPEC_ASHIFT_SIGNED ; Used in aarch-simd.md.
336 UNSPEC_ASHIFT_UNSIGNED ; Used in aarch64-simd.md.
285398d2 337 UNSPEC_ABS ; Used in aarch64-simd.md.
998eaf97
JG		 338 UNSPEC_FMAX ; Used in aarch64-simd.md.
339 UNSPEC_FMAXNMV ; Used in aarch64-simd.md.
43e9d192 340 UNSPEC_FMAXV ; Used in aarch64-simd.md.
998eaf97
JG		 341 UNSPEC_FMIN ; Used in aarch64-simd.md.
342 UNSPEC_FMINNMV ; Used in aarch64-simd.md.
43e9d192
IB		 343 UNSPEC_FMINV ; Used in aarch64-simd.md.
344 UNSPEC_FADDV ; Used in aarch64-simd.md.
f5156c3e 345 UNSPEC_ADDV ; Used in aarch64-simd.md.
43e9d192
IB		 346 UNSPEC_SMAXV ; Used in aarch64-simd.md.
347 UNSPEC_SMINV ; Used in aarch64-simd.md.
348 UNSPEC_UMAXV ; Used in aarch64-simd.md.
349 UNSPEC_UMINV ; Used in aarch64-simd.md.
350 UNSPEC_SHADD ; Used in aarch64-simd.md.
351 UNSPEC_UHADD ; Used in aarch64-simd.md.
352 UNSPEC_SRHADD ; Used in aarch64-simd.md.
353 UNSPEC_URHADD ; Used in aarch64-simd.md.
354 UNSPEC_SHSUB ; Used in aarch64-simd.md.
355 UNSPEC_UHSUB ; Used in aarch64-simd.md.
356 UNSPEC_SRHSUB ; Used in aarch64-simd.md.
357 UNSPEC_URHSUB ; Used in aarch64-simd.md.
358 UNSPEC_ADDHN ; Used in aarch64-simd.md.
359 UNSPEC_RADDHN ; Used in aarch64-simd.md.
360 UNSPEC_SUBHN ; Used in aarch64-simd.md.
361 UNSPEC_RSUBHN ; Used in aarch64-simd.md.
362 UNSPEC_ADDHN2 ; Used in aarch64-simd.md.
363 UNSPEC_RADDHN2 ; Used in aarch64-simd.md.
364 UNSPEC_SUBHN2 ; Used in aarch64-simd.md.
365 UNSPEC_RSUBHN2 ; Used in aarch64-simd.md.
366 UNSPEC_SQDMULH ; Used in aarch64-simd.md.
367 UNSPEC_SQRDMULH ; Used in aarch64-simd.md.
368 UNSPEC_PMUL ; Used in aarch64-simd.md.
496ea87d 369 UNSPEC_FMULX ; Used in aarch64-simd.md.
43e9d192
IB		 370 UNSPEC_USQADD ; Used in aarch64-simd.md.
371 UNSPEC_SUQADD ; Used in aarch64-simd.md.
372 UNSPEC_SQXTUN ; Used in aarch64-simd.md.
373 UNSPEC_SQXTN ; Used in aarch64-simd.md.
374 UNSPEC_UQXTN ; Used in aarch64-simd.md.
375 UNSPEC_SSRA ; Used in aarch64-simd.md.
376 UNSPEC_USRA ; Used in aarch64-simd.md.
377 UNSPEC_SRSRA ; Used in aarch64-simd.md.
378 UNSPEC_URSRA ; Used in aarch64-simd.md.
379 UNSPEC_SRSHR ; Used in aarch64-simd.md.
380 UNSPEC_URSHR ; Used in aarch64-simd.md.
381 UNSPEC_SQSHLU ; Used in aarch64-simd.md.
382 UNSPEC_SQSHL ; Used in aarch64-simd.md.
383 UNSPEC_UQSHL ; Used in aarch64-simd.md.
384 UNSPEC_SQSHRUN ; Used in aarch64-simd.md.
385 UNSPEC_SQRSHRUN ; Used in aarch64-simd.md.
386 UNSPEC_SQSHRN ; Used in aarch64-simd.md.
387 UNSPEC_UQSHRN ; Used in aarch64-simd.md.
388 UNSPEC_SQRSHRN ; Used in aarch64-simd.md.
389 UNSPEC_UQRSHRN ; Used in aarch64-simd.md.
390 UNSPEC_SSHL ; Used in aarch64-simd.md.
391 UNSPEC_USHL ; Used in aarch64-simd.md.
392 UNSPEC_SRSHL ; Used in aarch64-simd.md.
393 UNSPEC_URSHL ; Used in aarch64-simd.md.
394 UNSPEC_SQRSHL ; Used in aarch64-simd.md.
395 UNSPEC_UQRSHL ; Used in aarch64-simd.md.
43e9d192
IB		 396 UNSPEC_SSLI ; Used in aarch64-simd.md.
397 UNSPEC_USLI ; Used in aarch64-simd.md.
398 UNSPEC_SSRI ; Used in aarch64-simd.md.
399 UNSPEC_USRI ; Used in aarch64-simd.md.
400 UNSPEC_SSHLL ; Used in aarch64-simd.md.
401 UNSPEC_USHLL ; Used in aarch64-simd.md.
402 UNSPEC_ADDP ; Used in aarch64-simd.md.
88b08073 403 UNSPEC_TBL ; Used in vector permute patterns.
9371aecc 404 UNSPEC_TBX ; Used in vector permute patterns.
88b08073 405 UNSPEC_CONCAT ; Used in vector permute patterns.
3f8334a5
RS		 406
407 ;; The following permute unspecs are generated directly by
408 ;; aarch64_expand_vec_perm_const, so any changes to the underlying
409 ;; instructions would need a corresponding change there.
cc4d934f
JG		 410 UNSPEC_ZIP1 ; Used in vector permute patterns.
411 UNSPEC_ZIP2 ; Used in vector permute patterns.
412 UNSPEC_UZP1 ; Used in vector permute patterns.
413 UNSPEC_UZP2 ; Used in vector permute patterns.
414 UNSPEC_TRN1 ; Used in vector permute patterns.
415 UNSPEC_TRN2 ; Used in vector permute patterns.
3f8334a5 416 UNSPEC_EXT ; Used in vector permute patterns.
923fcec3
AL		 417 UNSPEC_REV64 ; Used in vector reverse patterns (permute).
418 UNSPEC_REV32 ; Used in vector reverse patterns (permute).
419 UNSPEC_REV16 ; Used in vector reverse patterns (permute).
3f8334a5 420
5a7a4e80
TB		 421 UNSPEC_AESE ; Used in aarch64-simd.md.
422 UNSPEC_AESD ; Used in aarch64-simd.md.
423 UNSPEC_AESMC ; Used in aarch64-simd.md.
424 UNSPEC_AESIMC ; Used in aarch64-simd.md.
30442682
TB		 425 UNSPEC_SHA1C ; Used in aarch64-simd.md.
426 UNSPEC_SHA1M ; Used in aarch64-simd.md.
427 UNSPEC_SHA1P ; Used in aarch64-simd.md.
428 UNSPEC_SHA1H ; Used in aarch64-simd.md.
429 UNSPEC_SHA1SU0 ; Used in aarch64-simd.md.
430 UNSPEC_SHA1SU1 ; Used in aarch64-simd.md.
b9cb0a44
TB		 431 UNSPEC_SHA256H ; Used in aarch64-simd.md.
432 UNSPEC_SHA256H2 ; Used in aarch64-simd.md.
433 UNSPEC_SHA256SU0 ; Used in aarch64-simd.md.
434 UNSPEC_SHA256SU1 ; Used in aarch64-simd.md.
7baa225d
TB		 435 UNSPEC_PMULL ; Used in aarch64-simd.md.
436 UNSPEC_PMULL2 ; Used in aarch64-simd.md.
668046d1 437 UNSPEC_REV_REGLIST ; Used in aarch64-simd.md.
9c004c58 438 UNSPEC_VEC_SHR ; Used in aarch64-simd.md.
57b26d65
MW		 439 UNSPEC_SQRDMLAH ; Used in aarch64-simd.md.
440 UNSPEC_SQRDMLSH ; Used in aarch64-simd.md.
202d0c11
DS		 441 UNSPEC_FMAXNM ; Used in aarch64-simd.md.
442 UNSPEC_FMINNM ; Used in aarch64-simd.md.
7a08d813
TC		 443 UNSPEC_SDOT ; Used in aarch64-simd.md.
444 UNSPEC_UDOT ; Used in aarch64-simd.md.
27086ea3
MC		 445 UNSPEC_SM3SS1 ; Used in aarch64-simd.md.
446 UNSPEC_SM3TT1A ; Used in aarch64-simd.md.
447 UNSPEC_SM3TT1B ; Used in aarch64-simd.md.
448 UNSPEC_SM3TT2A ; Used in aarch64-simd.md.
449 UNSPEC_SM3TT2B ; Used in aarch64-simd.md.
450 UNSPEC_SM3PARTW1 ; Used in aarch64-simd.md.
451 UNSPEC_SM3PARTW2 ; Used in aarch64-simd.md.
452 UNSPEC_SM4E ; Used in aarch64-simd.md.
453 UNSPEC_SM4EKEY ; Used in aarch64-simd.md.
454 UNSPEC_SHA512H ; Used in aarch64-simd.md.
455 UNSPEC_SHA512H2 ; Used in aarch64-simd.md.
456 UNSPEC_SHA512SU0 ; Used in aarch64-simd.md.
457 UNSPEC_SHA512SU1 ; Used in aarch64-simd.md.
458 UNSPEC_FMLAL ; Used in aarch64-simd.md.
459 UNSPEC_FMLSL ; Used in aarch64-simd.md.
460 UNSPEC_FMLAL2 ; Used in aarch64-simd.md.
461 UNSPEC_FMLSL2 ; Used in aarch64-simd.md.
43cacb12 462 UNSPEC_SEL ; Used in aarch64-sve.md.
898f07b0
RS		 463 UNSPEC_ANDV ; Used in aarch64-sve.md.
464 UNSPEC_IORV ; Used in aarch64-sve.md.
465 UNSPEC_XORV ; Used in aarch64-sve.md.
43cacb12
RS		 466 UNSPEC_ANDF ; Used in aarch64-sve.md.
467 UNSPEC_IORF ; Used in aarch64-sve.md.
468 UNSPEC_XORF ; Used in aarch64-sve.md.
11e9443f
RS		 469 UNSPEC_SMUL_HIGHPART ; Used in aarch64-sve.md.
470 UNSPEC_UMUL_HIGHPART ; Used in aarch64-sve.md.
d45b20a5 471 UNSPEC_COND_FABS ; Used in aarch64-sve.md.
cb18e86d
RS		 472 UNSPEC_COND_FADD ; Used in aarch64-sve.md.
473 UNSPEC_COND_FCMEQ ; Used in aarch64-sve.md.
474 UNSPEC_COND_FCMGE ; Used in aarch64-sve.md.
475 UNSPEC_COND_FCMGT ; Used in aarch64-sve.md.
476 UNSPEC_COND_FCMLE ; Used in aarch64-sve.md.
477 UNSPEC_COND_FCMLT ; Used in aarch64-sve.md.
478 UNSPEC_COND_FCMNE ; Used in aarch64-sve.md.
479 UNSPEC_COND_FDIV ; Used in aarch64-sve.md.
480 UNSPEC_COND_FMAXNM ; Used in aarch64-sve.md.
481 UNSPEC_COND_FMINNM ; Used in aarch64-sve.md.
b41d1f6e
RS		 482 UNSPEC_COND_FMLA ; Used in aarch64-sve.md.
483 UNSPEC_COND_FMLS ; Used in aarch64-sve.md.
cb18e86d 484 UNSPEC_COND_FMUL ; Used in aarch64-sve.md.
d45b20a5 485 UNSPEC_COND_FNEG ; Used in aarch64-sve.md.
b41d1f6e
RS		 486 UNSPEC_COND_FNMLA ; Used in aarch64-sve.md.
487 UNSPEC_COND_FNMLS ; Used in aarch64-sve.md.
d45b20a5
RS		 488 UNSPEC_COND_FRINTA ; Used in aarch64-sve.md.
489 UNSPEC_COND_FRINTI ; Used in aarch64-sve.md.
490 UNSPEC_COND_FRINTM ; Used in aarch64-sve.md.
491 UNSPEC_COND_FRINTN ; Used in aarch64-sve.md.
492 UNSPEC_COND_FRINTP ; Used in aarch64-sve.md.
493 UNSPEC_COND_FRINTX ; Used in aarch64-sve.md.
494 UNSPEC_COND_FRINTZ ; Used in aarch64-sve.md.
495 UNSPEC_COND_FSQRT ; Used in aarch64-sve.md.
cb18e86d 496 UNSPEC_COND_FSUB ; Used in aarch64-sve.md.
43cacb12 497 UNSPEC_LASTB ; Used in aarch64-sve.md.
9d63f43b
TC		 498 UNSPEC_FCADD90 ; Used in aarch64-simd.md.
499 UNSPEC_FCADD270 ; Used in aarch64-simd.md.
500 UNSPEC_FCMLA ; Used in aarch64-simd.md.
501 UNSPEC_FCMLA90 ; Used in aarch64-simd.md.
502 UNSPEC_FCMLA180 ; Used in aarch64-simd.md.
503 UNSPEC_FCMLA270 ; Used in aarch64-simd.md.
43e9d192
IB		 504])
505
d81cb613
MW		 506;; ------------------------------------------------------------------
507;; Unspec enumerations for Atomics. They are here so that they can be
508;; used in the int_iterators for atomic operations.
509;; ------------------------------------------------------------------
510
511(define_c_enum "unspecv"
512 [
513 UNSPECV_LX ; Represent a load-exclusive.
514 UNSPECV_SX ; Represent a store-exclusive.
515 UNSPECV_LDA ; Represent an atomic load or load-acquire.
516 UNSPECV_STL ; Represent an atomic store or store-release.
517 UNSPECV_ATOMIC_CMPSW ; Represent an atomic compare swap.
518 UNSPECV_ATOMIC_EXCHG ; Represent an atomic exchange.
519 UNSPECV_ATOMIC_CAS ; Represent an atomic CAS.
520 UNSPECV_ATOMIC_SWP ; Represent an atomic SWP.
521 UNSPECV_ATOMIC_OP ; Represent an atomic operation.
d81cb613
MW		 522 UNSPECV_ATOMIC_LDOP_OR ; Represent an atomic load-or
523 UNSPECV_ATOMIC_LDOP_BIC ; Represent an atomic load-bic
524 UNSPECV_ATOMIC_LDOP_XOR ; Represent an atomic load-xor
525 UNSPECV_ATOMIC_LDOP_PLUS ; Represent an atomic load-add
526])
527
43e9d192
IB		 528;; -------------------------------------------------------------------
529;; Mode attributes
530;; -------------------------------------------------------------------
531
532;; In GPI templates, a string like "%<w>0" will expand to "%w0" in the
533;; 32-bit version and "%x0" in the 64-bit version.
534(define_mode_attr w [(QI "w") (HI "w") (SI "w") (DI "x") (SF "s") (DF "d")])
535
db46a2e6
JG		 536;; The size of access, in bytes.
537(define_mode_attr ldst_sz [(SI "4") (DI "8")])
538;; Likewise for load/store pair.
539(define_mode_attr ldpstp_sz [(SI "8") (DI "16")])
540
0d35c5c2 541;; For inequal width int to float conversion
d7f33f07
JW		 542(define_mode_attr w1 [(HF "w") (SF "w") (DF "x")])
543(define_mode_attr w2 [(HF "x") (SF "x") (DF "w")])
0d35c5c2 544
22be0d08
MC		 545;; For width of fp registers in fcvt instruction
546(define_mode_attr fpw [(DI "s") (SI "d")])
547
2b8568fe
KT		 548(define_mode_attr short_mask [(HI "65535") (QI "255")])
549
051d0e2f
SN		 550;; For constraints used in scalar immediate vector moves
551(define_mode_attr hq [(HI "h") (QI "q")])
552
ef22810a
RH		 553;; For doubling width of an integer mode
554(define_mode_attr DWI [(QI "HI") (HI "SI") (SI "DI") (DI "TI")])
555
22be0d08
MC		 556(define_mode_attr fcvt_change_mode [(SI "df") (DI "sf")])
557
558(define_mode_attr FCVT_CHANGE_MODE [(SI "DF") (DI "SF")])
559
43e9d192
IB		 560;; For scalar usage of vector/FP registers
561(define_mode_attr v [(QI "b") (HI "h") (SI "s") (DI "d")
d7f33f07 562 (HF "h") (SF "s") (DF "d")
43e9d192
IB		 563 (V8QI "") (V16QI "")
564 (V4HI "") (V8HI "")
565 (V2SI "") (V4SI "")
566 (V2DI "") (V2SF "")
daef0a8c
JW		 567 (V4SF "") (V4HF "")
568 (V8HF "") (V2DF "")])
43e9d192
IB		 569
570;; For scalar usage of vector/FP registers, narrowing
571(define_mode_attr vn2 [(QI "") (HI "b") (SI "h") (DI "s")
572 (V8QI "") (V16QI "")
573 (V4HI "") (V8HI "")
574 (V2SI "") (V4SI "")
575 (V2DI "") (V2SF "")
576 (V4SF "") (V2DF "")])
577
578;; For scalar usage of vector/FP registers, widening
579(define_mode_attr vw2 [(DI "") (QI "h") (HI "s") (SI "d")
580 (V8QI "") (V16QI "")
581 (V4HI "") (V8HI "")
582 (V2SI "") (V4SI "")
583 (V2DI "") (V2SF "")
584 (V4SF "") (V2DF "")])
585
89fdc743
IB		 586;; Register Type Name and Vector Arrangement Specifier for when
587;; we are doing scalar for DI and SIMD for SI (ignoring all but
588;; lane 0).
589(define_mode_attr rtn [(DI "d") (SI "")])
590(define_mode_attr vas [(DI "") (SI ".2s")])
591
7ac29c0f
RS		 592;; Map a vector to the number of units in it, if the size of the mode
593;; is constant.
594(define_mode_attr nunits [(V8QI "8") (V16QI "16")
595 (V4HI "4") (V8HI "8")
596 (V2SI "2") (V4SI "4")
597 (V2DI "2")
598 (V4HF "4") (V8HF "8")
599 (V2SF "2") (V4SF "4")
600 (V1DF "1") (V2DF "2")
601 (DI "1") (DF "1")])
602
b187677b
RS		 603;; Map a mode to the number of bits in it, if the size of the mode
604;; is constant.
605(define_mode_attr bitsize [(V8QI "64") (V16QI "128")
606 (V4HI "64") (V8HI "128")
607 (V2SI "64") (V4SI "128")
608 (V2DI "128")])
609
22be0d08
MC		 610;; Map a floating point or integer mode to the appropriate register name prefix
611(define_mode_attr s [(HF "h") (SF "s") (DF "d") (SI "s") (DI "d")])
43e9d192
IB		 612
613;; Give the length suffix letter for a sign- or zero-extension.
614(define_mode_attr size [(QI "b") (HI "h") (SI "w")])
615
616;; Give the number of bits in the mode
617(define_mode_attr sizen [(QI "8") (HI "16") (SI "32") (DI "64")])
618
619;; Give the ordinal of the MSB in the mode
315fdae8
RE		 620(define_mode_attr sizem1 [(QI "#7") (HI "#15") (SI "#31") (DI "#63")
621 (HF "#15") (SF "#31") (DF "#63")])
43e9d192
IB		 622
623;; Attribute to describe constants acceptable in logical operations
624(define_mode_attr lconst [(SI "K") (DI "L")])
625
43fd192f
MC		 626;; Attribute to describe constants acceptable in logical and operations
627(define_mode_attr lconst2 [(SI "UsO") (DI "UsP")])
628
43e9d192
IB		 629;; Map a mode to a specific constraint character.
630(define_mode_attr cmode [(QI "q") (HI "h") (SI "s") (DI "d")])
631
0603375c
KT		 632;; Map modes to Usg and Usj constraints for SISD right shifts
633(define_mode_attr cmode_simd [(SI "g") (DI "j")])
634
43e9d192
IB		 635(define_mode_attr Vtype [(V8QI "8b") (V16QI "16b")
636 (V4HI "4h") (V8HI "8h")
637 (V2SI "2s") (V4SI "4s")
638 (DI "1d") (DF "1d")
639 (V2DI "2d") (V2SF "2s")
7c369485
AL		 640 (V4SF "4s") (V2DF "2d")
641 (V4HF "4h") (V8HF "8h")])
43e9d192 642
c7f28cd5
KT		 643(define_mode_attr Vrevsuff [(V4HI "16") (V8HI "16") (V2SI "32")
644 (V4SI "32") (V2DI "64")])
645
43e9d192
IB		 646(define_mode_attr Vmtype [(V8QI ".8b") (V16QI ".16b")
647 (V4HI ".4h") (V8HI ".8h")
648 (V2SI ".2s") (V4SI ".4s")
71a11456
AL		 649 (V2DI ".2d") (V4HF ".4h")
650 (V8HF ".8h") (V2SF ".2s")
43e9d192
IB		 651 (V4SF ".4s") (V2DF ".2d")
652 (DI "") (SI "")
653 (HI "") (QI "")
d7f33f07
JW		 654 (TI "") (HF "")
655 (SF "") (DF "")])
43e9d192
IB		 656
657;; Register suffix narrowed modes for VQN.
658(define_mode_attr Vmntype [(V8HI ".8b") (V4SI ".4h")
659 (V2DI ".2s")
660 (DI "") (SI "")
661 (HI "")])
662
663;; Mode-to-individual element type mapping.
43cacb12
RS		 664(define_mode_attr Vetype [(V8QI "b") (V16QI "b") (VNx16QI "b") (VNx16BI "b")
665 (V4HI "h") (V8HI "h") (VNx8HI "h") (VNx8BI "h")
666 (V2SI "s") (V4SI "s") (VNx4SI "s") (VNx4BI "s")
667 (V2DI "d") (VNx2DI "d") (VNx2BI "d")
668 (V4HF "h") (V8HF "h") (VNx8HF "h")
669 (V2SF "s") (V4SF "s") (VNx4SF "s")
670 (V2DF "d") (VNx2DF "d")
d7f33f07 671 (HF "h")
0f686aa9 672 (SF "s") (DF "d")
43e9d192
IB		 673 (QI "b") (HI "h")
674 (SI "s") (DI "d")])
675
9feeafd7
AM		 676;; Like Vetype, but map to types that are a quarter of the element size.
677(define_mode_attr Vetype_fourth [(VNx4SI "b") (VNx2DI "h")])
678
43cacb12
RS		 679;; Equivalent of "size" for a vector element.
680(define_mode_attr Vesize [(VNx16QI "b")
9f4cbab8
RS		 681 (VNx8HI "h") (VNx8HF "h")
682 (VNx4SI "w") (VNx4SF "w")
683 (VNx2DI "d") (VNx2DF "d")
684 (VNx32QI "b") (VNx48QI "b") (VNx64QI "b")
685 (VNx16HI "h") (VNx24HI "h") (VNx32HI "h")
686 (VNx16HF "h") (VNx24HF "h") (VNx32HF "h")
687 (VNx8SI "w") (VNx12SI "w") (VNx16SI "w")
688 (VNx8SF "w") (VNx12SF "w") (VNx16SF "w")
689 (VNx4DI "d") (VNx6DI "d") (VNx8DI "d")
690 (VNx4DF "d") (VNx6DF "d") (VNx8DF "d")])
43cacb12 691
daef0a8c
JW		 692;; Vetype is used everywhere in scheduling type and assembly output,
693;; sometimes they are not the same, for example HF modes on some
694;; instructions. stype is defined to represent scheduling type
695;; more accurately.
696(define_mode_attr stype [(V8QI "b") (V16QI "b") (V4HI "s") (V8HI "s")
697 (V2SI "s") (V4SI "s") (V2DI "d") (V4HF "s")
698 (V8HF "s") (V2SF "s") (V4SF "s") (V2DF "d")
699 (HF "s") (SF "s") (DF "d") (QI "b") (HI "s")
700 (SI "s") (DI "d")])
701
43e9d192
IB		 702;; Mode-to-bitwise operation type mapping.
703(define_mode_attr Vbtype [(V8QI "8b") (V16QI "16b")
704 (V4HI "8b") (V8HI "16b")
705 (V2SI "8b") (V4SI "16b")
7c369485
AL		 706 (V2DI "16b") (V4HF "8b")
707 (V8HF "16b") (V2SF "8b")
46e778c4 708 (V4SF "16b") (V2DF "16b")
fe82d1f2 709 (DI "8b") (DF "8b")
315fdae8 710 (SI "8b") (SF "8b")])
43e9d192
IB		 711
712;; Define element mode for each vector mode.
43cacb12
RS		 713(define_mode_attr VEL [(V8QI "QI") (V16QI "QI") (VNx16QI "QI")
714 (V4HI "HI") (V8HI "HI") (VNx8HI "HI")
715 (V2SI "SI") (V4SI "SI") (VNx4SI "SI")
716 (DI "DI") (V2DI "DI") (VNx2DI "DI")
717 (V4HF "HF") (V8HF "HF") (VNx8HF "HF")
718 (V2SF "SF") (V4SF "SF") (VNx4SF "SF")
719 (DF "DF") (V2DF "DF") (VNx2DF "DF")
720 (SI "SI") (HI "HI")
43e9d192
IB		 721 (QI "QI")])
722
ff03930a 723;; Define element mode for each vector mode (lower case).
43cacb12
RS		 724(define_mode_attr Vel [(V8QI "qi") (V16QI "qi") (VNx16QI "qi")
725 (V4HI "hi") (V8HI "hi") (VNx8HI "hi")
726 (V2SI "si") (V4SI "si") (VNx4SI "si")
727 (DI "di") (V2DI "di") (VNx2DI "di")
728 (V4HF "hf") (V8HF "hf") (VNx8HF "hf")
729 (V2SF "sf") (V4SF "sf") (VNx4SF "sf")
730 (V2DF "df") (DF "df") (VNx2DF "df")
ff03930a
JJ		 731 (SI "si") (HI "hi")
732 (QI "qi")])
733
43cacb12
RS		 734;; Element mode with floating-point values replaced by like-sized integers.
735(define_mode_attr VEL_INT [(VNx16QI "QI")
736 (VNx8HI "HI") (VNx8HF "HI")
737 (VNx4SI "SI") (VNx4SF "SI")
738 (VNx2DI "DI") (VNx2DF "DI")])
739
740;; Gives the mode of the 128-bit lowpart of an SVE vector.
741(define_mode_attr V128 [(VNx16QI "V16QI")
742 (VNx8HI "V8HI") (VNx8HF "V8HF")
743 (VNx4SI "V4SI") (VNx4SF "V4SF")
744 (VNx2DI "V2DI") (VNx2DF "V2DF")])
745
746;; ...and again in lower case.
747(define_mode_attr v128 [(VNx16QI "v16qi")
748 (VNx8HI "v8hi") (VNx8HF "v8hf")
749 (VNx4SI "v4si") (VNx4SF "v4sf")
750 (VNx2DI "v2di") (VNx2DF "v2df")])
751
278821f2
KT		 752;; 64-bit container modes the inner or scalar source mode.
753(define_mode_attr VCOND [(HI "V4HI") (SI "V2SI")
754 (V4HI "V4HI") (V8HI "V4HI")
b7d7d917
TB		 755 (V2SI "V2SI") (V4SI "V2SI")
756 (DI "DI") (V2DI "DI")
757 (V2SF "V2SF") (V4SF "V2SF")
758 (V2DF "DF")])
759
278821f2 760;; 128-bit container modes the inner or scalar source mode.
b7d7d917
TB		 761(define_mode_attr VCONQ [(V8QI "V16QI") (V16QI "V16QI")
762 (V4HI "V8HI") (V8HI "V8HI")
763 (V2SI "V4SI") (V4SI "V4SI")
764 (DI "V2DI") (V2DI "V2DI")
71a11456 765 (V4HF "V8HF") (V8HF "V8HF")
b7d7d917
TB		 766 (V2SF "V2SF") (V4SF "V4SF")
767 (V2DF "V2DF") (SI "V4SI")
768 (HI "V8HI") (QI "V16QI")])
769
43e9d192
IB		 770;; Half modes of all vector modes.
771(define_mode_attr VHALF [(V8QI "V4QI") (V16QI "V8QI")
772 (V4HI "V2HI") (V8HI "V4HI")
773 (V2SI "SI") (V4SI "V2SI")
774 (V2DI "DI") (V2SF "SF")
71a11456
AL		 775 (V4SF "V2SF") (V4HF "V2HF")
776 (V8HF "V4HF") (V2DF "DF")])
43e9d192 777
b1b49824
MC		 778;; Half modes of all vector modes, in lower-case.
779(define_mode_attr Vhalf [(V8QI "v4qi") (V16QI "v8qi")
780 (V4HI "v2hi") (V8HI "v4hi")
41dab855 781 (V8HF "v4hf")
b1b49824
MC		 782 (V2SI "si") (V4SI "v2si")
783 (V2DI "di") (V2SF "sf")
784 (V4SF "v2sf") (V2DF "df")])
785
43e9d192
IB		 786;; Double modes of vector modes.
787(define_mode_attr VDBL [(V8QI "V16QI") (V4HI "V8HI")
71a11456 788 (V4HF "V8HF")
43e9d192
IB		 789 (V2SI "V4SI") (V2SF "V4SF")
790 (SI "V2SI") (DI "V2DI")
791 (DF "V2DF")])
792
922f9c25
AL		 793;; Register suffix for double-length mode.
794(define_mode_attr Vdtype [(V4HF "8h") (V2SF "4s")])
795
43e9d192
IB		 796;; Double modes of vector modes (lower case).
797(define_mode_attr Vdbl [(V8QI "v16qi") (V4HI "v8hi")
7c369485 798 (V4HF "v8hf")
43e9d192 799 (V2SI "v4si") (V2SF "v4sf")
8b033a8a
SN		 800 (SI "v2si") (DI "v2di")
801 (DF "v2df")])
43e9d192 802
b1b49824
MC		 803;; Modes with double-width elements.
804(define_mode_attr VDBLW [(V8QI "V4HI") (V16QI "V8HI")
805 (V4HI "V2SI") (V8HI "V4SI")
806 (V2SI "DI") (V4SI "V2DI")])
807
43e9d192
IB		 808;; Narrowed modes for VDN.
809(define_mode_attr VNARROWD [(V4HI "V8QI") (V2SI "V4HI")
810 (DI "V2SI")])
811
812;; Narrowed double-modes for VQN (Used for XTN).
813(define_mode_attr VNARROWQ [(V8HI "V8QI") (V4SI "V4HI")
814 (V2DI "V2SI")
815 (DI "SI") (SI "HI")
816 (HI "QI")])
817
818;; Narrowed quad-modes for VQN (Used for XTN2).
819(define_mode_attr VNARROWQ2 [(V8HI "V16QI") (V4SI "V8HI")
820 (V2DI "V4SI")])
821
822;; Register suffix narrowed modes for VQN.
823(define_mode_attr Vntype [(V8HI "8b") (V4SI "4h")
824 (V2DI "2s")])
825
826;; Register suffix narrowed modes for VQN.
827(define_mode_attr V2ntype [(V8HI "16b") (V4SI "8h")
828 (V2DI "4s")])
829
830;; Widened modes of vector modes.
43cacb12
RS		 831(define_mode_attr VWIDE [(V8QI "V8HI") (V4HI "V4SI")
832 (V2SI "V2DI") (V16QI "V8HI")
833 (V8HI "V4SI") (V4SI "V2DI")
834 (HI "SI") (SI "DI")
835 (V8HF "V4SF") (V4SF "V2DF")
836 (V4HF "V4SF") (V2SF "V2DF")
837 (VNx8HF "VNx4SF") (VNx4SF "VNx2DF")
838 (VNx16QI "VNx8HI") (VNx8HI "VNx4SI")
839 (VNx4SI "VNx2DI")
840 (VNx16BI "VNx8BI") (VNx8BI "VNx4BI")
841 (VNx4BI "VNx2BI")])
842
843;; Predicate mode associated with VWIDE.
844(define_mode_attr VWIDE_PRED [(VNx8HF "VNx4BI") (VNx4SF "VNx2BI")])
43e9d192 845
03873eb9 846;; Widened modes of vector modes, lowercase
43cacb12
RS		 847(define_mode_attr Vwide [(V2SF "v2df") (V4HF "v4sf")
848 (VNx16QI "vnx8hi") (VNx8HI "vnx4si")
849 (VNx4SI "vnx2di")
850 (VNx8HF "vnx4sf") (VNx4SF "vnx2df")
851 (VNx16BI "vnx8bi") (VNx8BI "vnx4bi")
852 (VNx4BI "vnx2bi")])
03873eb9
AL		 853
854;; Widened mode register suffixes for VD_BHSI/VQW/VQ_HSF.
43e9d192
IB		 855(define_mode_attr Vwtype [(V8QI "8h") (V4HI "4s")
856 (V2SI "2d") (V16QI "8h")
03873eb9
AL		 857 (V8HI "4s") (V4SI "2d")
858 (V8HF "4s") (V4SF "2d")])
43e9d192 859
43cacb12
RS		 860;; SVE vector after widening
861(define_mode_attr Vewtype [(VNx16QI "h")
862 (VNx8HI "s") (VNx8HF "s")
863 (VNx4SI "d") (VNx4SF "d")])
864
43e9d192
IB		 865;; Widened mode register suffixes for VDW/VQW.
866(define_mode_attr Vmwtype [(V8QI ".8h") (V4HI ".4s")
867 (V2SI ".2d") (V16QI ".8h")
868 (V8HI ".4s") (V4SI ".2d")
922f9c25 869 (V4HF ".4s") (V2SF ".2d")
43e9d192
IB		 870 (SI "") (HI "")])
871
03873eb9 872;; Lower part register suffixes for VQW/VQ_HSF.
43e9d192 873(define_mode_attr Vhalftype [(V16QI "8b") (V8HI "4h")
03873eb9
AL		 874 (V4SI "2s") (V8HF "4h")
875 (V4SF "2s")])
43e9d192
IB		 876
877;; Define corresponding core/FP element mode for each vector mode.
43cacb12
RS		 878(define_mode_attr vw [(V8QI "w") (V16QI "w") (VNx16QI "w")
879 (V4HI "w") (V8HI "w") (VNx8HI "w")
880 (V2SI "w") (V4SI "w") (VNx4SI "w")
881 (DI "x") (V2DI "x") (VNx2DI "x")
882 (VNx8HF "h")
883 (V2SF "s") (V4SF "s") (VNx4SF "s")
884 (V2DF "d") (VNx2DF "d")])
43e9d192 885
66adb8eb
JG		 886;; Corresponding core element mode for each vector mode. This is a
887;; variation on <vw> mapping FP modes to GP regs.
43cacb12
RS		 888(define_mode_attr vwcore [(V8QI "w") (V16QI "w") (VNx16QI "w")
889 (V4HI "w") (V8HI "w") (VNx8HI "w")
890 (V2SI "w") (V4SI "w") (VNx4SI "w")
891 (DI "x") (V2DI "x") (VNx2DI "x")
892 (V4HF "w") (V8HF "w") (VNx8HF "w")
893 (V2SF "w") (V4SF "w") (VNx4SF "w")
894 (V2DF "x") (VNx2DF "x")])
66adb8eb 895
43e9d192
IB		 896;; Double vector types for ALLX.
897(define_mode_attr Vallxd [(QI "8b") (HI "4h") (SI "2s")])
898
5f565314
RS		 899;; Mode with floating-point values replaced by like-sized integers.
900(define_mode_attr V_INT_EQUIV [(V8QI "V8QI") (V16QI "V16QI")
901 (V4HI "V4HI") (V8HI "V8HI")
902 (V2SI "V2SI") (V4SI "V4SI")
903 (DI "DI") (V2DI "V2DI")
904 (V4HF "V4HI") (V8HF "V8HI")
905 (V2SF "V2SI") (V4SF "V4SI")
43cacb12 906 (DF "DI") (V2DF "V2DI")
dfe1da23
JW		 907 (SF "SI") (SI "SI")
908 (HF "HI")
43cacb12
RS		 909 (VNx16QI "VNx16QI")
910 (VNx8HI "VNx8HI") (VNx8HF "VNx8HI")
911 (VNx4SI "VNx4SI") (VNx4SF "VNx4SI")
912 (VNx2DI "VNx2DI") (VNx2DF "VNx2DI")
913])
5f565314
RS		 914
915;; Lower case mode with floating-point values replaced by like-sized integers.
916(define_mode_attr v_int_equiv [(V8QI "v8qi") (V16QI "v16qi")
917 (V4HI "v4hi") (V8HI "v8hi")
918 (V2SI "v2si") (V4SI "v4si")
919 (DI "di") (V2DI "v2di")
920 (V4HF "v4hi") (V8HF "v8hi")
921 (V2SF "v2si") (V4SF "v4si")
43cacb12
RS		 922 (DF "di") (V2DF "v2di")
923 (SF "si")
924 (VNx16QI "vnx16qi")
925 (VNx8HI "vnx8hi") (VNx8HF "vnx8hi")
926 (VNx4SI "vnx4si") (VNx4SF "vnx4si")
927 (VNx2DI "vnx2di") (VNx2DF "vnx2di")
928])
929
930;; Floating-point equivalent of selected modes.
931(define_mode_attr V_FP_EQUIV [(VNx4SI "VNx4SF") (VNx4SF "VNx4SF")
932 (VNx2DI "VNx2DF") (VNx2DF "VNx2DF")])
933(define_mode_attr v_fp_equiv [(VNx4SI "vnx4sf") (VNx4SF "vnx4sf")
934 (VNx2DI "vnx2df") (VNx2DF "vnx2df")])
70c67693 935
6c553b76
BC		 936;; Mode for vector conditional operations where the comparison has
937;; different type from the lhs.
938(define_mode_attr V_cmp_mixed [(V2SI "V2SF") (V4SI "V4SF")
939 (V2DI "V2DF") (V2SF "V2SI")
940 (V4SF "V4SI") (V2DF "V2DI")])
941
942(define_mode_attr v_cmp_mixed [(V2SI "v2sf") (V4SI "v4sf")
943 (V2DI "v2df") (V2SF "v2si")
944 (V4SF "v4si") (V2DF "v2di")])
945
cb23a30c
JG		 946;; Lower case element modes (as used in shift immediate patterns).
947(define_mode_attr ve_mode [(V8QI "qi") (V16QI "qi")
948 (V4HI "hi") (V8HI "hi")
949 (V2SI "si") (V4SI "si")
950 (DI "di") (V2DI "di")
951 (QI "qi") (HI "hi")
952 (SI "si")])
953
43e9d192
IB		 954;; Vm for lane instructions is restricted to FP_LO_REGS.
955(define_mode_attr vwx [(V4HI "x") (V8HI "x") (HI "x")
956 (V2SI "w") (V4SI "w") (SI "w")])
957
958(define_mode_attr Vendreg [(OI "T") (CI "U") (XI "V")])
959
97755701
AL		 960;; This is both the number of Q-Registers needed to hold the corresponding
961;; opaque large integer mode, and the number of elements touched by the
962;; ld..._lane and st..._lane operations.
43e9d192
IB		 963(define_mode_attr nregs [(OI "2") (CI "3") (XI "4")])
964
0462169c
SN		 965;; Mode for atomic operation suffixes
966(define_mode_attr atomic_sfx
967 [(QI "b") (HI "h") (SI "") (DI "")])
968
3f598afe 969(define_mode_attr fcvt_target [(V2DF "v2di") (V4SF "v4si") (V2SF "v2si")
2644d4d9 970 (V2DI "v2df") (V4SI "v4sf") (V2SI "v2sf")
daef0a8c
JW		 971 (SF "si") (DF "di") (SI "sf") (DI "df")
972 (V4HF "v4hi") (V8HF "v8hi") (V4HI "v4hf")
68ad28c3 973 (V8HI "v8hf") (HF "hi") (HI "hf")])
3f598afe 974(define_mode_attr FCVT_TARGET [(V2DF "V2DI") (V4SF "V4SI") (V2SF "V2SI")
2644d4d9 975 (V2DI "V2DF") (V4SI "V4SF") (V2SI "V2SF")
daef0a8c
JW		 976 (SF "SI") (DF "DI") (SI "SF") (DI "DF")
977 (V4HF "V4HI") (V8HF "V8HI") (V4HI "V4HF")
68ad28c3 978 (V8HI "V8HF") (HF "HI") (HI "HF")])
3f598afe 979
0d35c5c2
VP		 980
981;; for the inequal width integer to fp conversions
d7f33f07
JW		 982(define_mode_attr fcvt_iesize [(HF "di") (SF "di") (DF "si")])
983(define_mode_attr FCVT_IESIZE [(HF "DI") (SF "DI") (DF "SI")])
42fc9a7f 984
91bd4114
JG		 985(define_mode_attr VSWAP_WIDTH [(V8QI "V16QI") (V16QI "V8QI")
986 (V4HI "V8HI") (V8HI "V4HI")
987 (V2SI "V4SI") (V4SI "V2SI")
988 (DI "V2DI") (V2DI "DI")
989 (V2SF "V4SF") (V4SF "V2SF")
862abc04 990 (V4HF "V8HF") (V8HF "V4HF")
91bd4114
JG		 991 (DF "V2DF") (V2DF "DF")])
992
993(define_mode_attr vswap_width_name [(V8QI "to_128") (V16QI "to_64")
994 (V4HI "to_128") (V8HI "to_64")
995 (V2SI "to_128") (V4SI "to_64")
996 (DI "to_128") (V2DI "to_64")
862abc04 997 (V4HF "to_128") (V8HF "to_64")
91bd4114
JG		 998 (V2SF "to_128") (V4SF "to_64")
999 (DF "to_128") (V2DF "to_64")])
1000
779aea46 1001;; For certain vector-by-element multiplication instructions we must
6d06971d 1002;; constrain the 16-bit cases to use only V0-V15. This is covered by
779aea46
JG		 1003;; the 'x' constraint. All other modes may use the 'w' constraint.
1004(define_mode_attr h_con [(V2SI "w") (V4SI "w")
1005 (V4HI "x") (V8HI "x")
6d06971d 1006 (V4HF "x") (V8HF "x")
779aea46
JG		 1007 (V2SF "w") (V4SF "w")
1008 (V2DF "w") (DF "w")])
1009
1010;; Defined to 'f' for types whose element type is a float type.
1011(define_mode_attr f [(V8QI "") (V16QI "")
1012 (V4HI "") (V8HI "")
1013 (V2SI "") (V4SI "")
1014 (DI "") (V2DI "")
ab2e8f01 1015 (V4HF "f") (V8HF "f")
779aea46
JG		 1016 (V2SF "f") (V4SF "f")
1017 (V2DF "f") (DF "f")])
1018
0f686aa9
JG		 1019;; Defined to '_fp' for types whose element type is a float type.
1020(define_mode_attr fp [(V8QI "") (V16QI "")
1021 (V4HI "") (V8HI "")
1022 (V2SI "") (V4SI "")
1023 (DI "") (V2DI "")
ab2e8f01 1024 (V4HF "_fp") (V8HF "_fp")
0f686aa9
JG		 1025 (V2SF "_fp") (V4SF "_fp")
1026 (V2DF "_fp") (DF "_fp")
1027 (SF "_fp")])
1028
a9e66678
JG		 1029;; Defined to '_q' for 128-bit types.
1030(define_mode_attr q [(V8QI "") (V16QI "_q")
0f686aa9
JG		 1031 (V4HI "") (V8HI "_q")
1032 (V2SI "") (V4SI "_q")
1033 (DI "") (V2DI "_q")
71a11456 1034 (V4HF "") (V8HF "_q")
0f686aa9
JG		 1035 (V2SF "") (V4SF "_q")
1036 (V2DF "_q")
d7f33f07 1037 (QI "") (HI "") (SI "") (DI "") (HF "") (SF "") (DF "")])
a9e66678 1038
92835317
TB		 1039(define_mode_attr vp [(V8QI "v") (V16QI "v")
1040 (V4HI "v") (V8HI "v")
1041 (V2SI "p") (V4SI "v")
703bbcdf
JW		 1042 (V2DI "p") (V2DF "p")
1043 (V2SF "p") (V4SF "v")
1044 (V4HF "v") (V8HF "v")])
92835317 1045
9feeafd7
AM		 1046(define_mode_attr vsi2qi [(V2SI "v8qi") (V4SI "v16qi")
1047 (VNx4SI "vnx16qi") (VNx2DI "vnx8hi")])
1048(define_mode_attr VSI2QI [(V2SI "V8QI") (V4SI "V16QI")
1049 (VNx4SI "VNx16QI") (VNx2DI "VNx8HI")])
5e32e83b 1050
7a08d813
TC		 1051
1052;; Register suffix for DOTPROD input types from the return type.
1053(define_mode_attr Vdottype [(V2SI "8b") (V4SI "16b")])
1054
cd78b3dd 1055;; Sum of lengths of instructions needed to move vector registers of a mode.
668046d1
DS		 1056(define_mode_attr insn_count [(OI "8") (CI "12") (XI "16")])
1057
1b1e81f8
JW		 1058;; -fpic small model GOT reloc modifers: gotpage_lo15/lo14 for ILP64/32.
1059;; No need of iterator for -fPIC as it use got_lo12 for both modes.
1060(define_mode_attr got_modifier [(SI "gotpage_lo14") (DI "gotpage_lo15")])
1061
27086ea3
MC		 1062;; Width of 2nd and 3rd arguments to fp16 vector multiply add/sub
1063(define_mode_attr VFMLA_W [(V2SF "V4HF") (V4SF "V8HF")])
1064
1065(define_mode_attr VFMLA_SEL_W [(V2SF "V2HF") (V4SF "V4HF")])
1066
1067(define_mode_attr f16quad [(V2SF "") (V4SF "q")])
1068
1069(define_code_attr f16mac [(plus "a") (minus "s")])
1070
8544ed6e
KT		 1071;; Map smax to smin and umax to umin.
1072(define_code_attr max_opp [(smax "smin") (umax "umin")])
1073
a9fad8fe
AM		 1074;; Same as above, but louder.
1075(define_code_attr MAX_OPP [(smax "SMIN") (umax "UMIN")])
1076
9f4cbab8
RS		 1077;; The number of subvectors in an SVE_STRUCT.
1078(define_mode_attr vector_count [(VNx32QI "2") (VNx16HI "2")
1079 (VNx8SI "2") (VNx4DI "2")
1080 (VNx16HF "2") (VNx8SF "2") (VNx4DF "2")
1081 (VNx48QI "3") (VNx24HI "3")
1082 (VNx12SI "3") (VNx6DI "3")
1083 (VNx24HF "3") (VNx12SF "3") (VNx6DF "3")
1084 (VNx64QI "4") (VNx32HI "4")
1085 (VNx16SI "4") (VNx8DI "4")
1086 (VNx32HF "4") (VNx16SF "4") (VNx8DF "4")])
1087
1088;; The number of instruction bytes needed for an SVE_STRUCT move. This is
1089;; equal to vector_count * 4.
1090(define_mode_attr insn_length [(VNx32QI "8") (VNx16HI "8")
1091 (VNx8SI "8") (VNx4DI "8")
1092 (VNx16HF "8") (VNx8SF "8") (VNx4DF "8")
1093 (VNx48QI "12") (VNx24HI "12")
1094 (VNx12SI "12") (VNx6DI "12")
1095 (VNx24HF "12") (VNx12SF "12") (VNx6DF "12")
1096 (VNx64QI "16") (VNx32HI "16")
1097 (VNx16SI "16") (VNx8DI "16")
1098 (VNx32HF "16") (VNx16SF "16") (VNx8DF "16")])
1099
1100;; The type of a subvector in an SVE_STRUCT.
1101(define_mode_attr VSINGLE [(VNx32QI "VNx16QI")
1102 (VNx16HI "VNx8HI") (VNx16HF "VNx8HF")
1103 (VNx8SI "VNx4SI") (VNx8SF "VNx4SF")
1104 (VNx4DI "VNx2DI") (VNx4DF "VNx2DF")
1105 (VNx48QI "VNx16QI")
1106 (VNx24HI "VNx8HI") (VNx24HF "VNx8HF")
1107 (VNx12SI "VNx4SI") (VNx12SF "VNx4SF")
1108 (VNx6DI "VNx2DI") (VNx6DF "VNx2DF")
1109 (VNx64QI "VNx16QI")
1110 (VNx32HI "VNx8HI") (VNx32HF "VNx8HF")
1111 (VNx16SI "VNx4SI") (VNx16SF "VNx4SF")
1112 (VNx8DI "VNx2DI") (VNx8DF "VNx2DF")])
1113
1114;; ...and again in lower case.
1115(define_mode_attr vsingle [(VNx32QI "vnx16qi")
1116 (VNx16HI "vnx8hi") (VNx16HF "vnx8hf")
1117 (VNx8SI "vnx4si") (VNx8SF "vnx4sf")
1118 (VNx4DI "vnx2di") (VNx4DF "vnx2df")
1119 (VNx48QI "vnx16qi")
1120 (VNx24HI "vnx8hi") (VNx24HF "vnx8hf")
1121 (VNx12SI "vnx4si") (VNx12SF "vnx4sf")
1122 (VNx6DI "vnx2di") (VNx6DF "vnx2df")
1123 (VNx64QI "vnx16qi")
1124 (VNx32HI "vnx8hi") (VNx32HF "vnx8hf")
1125 (VNx16SI "vnx4si") (VNx16SF "vnx4sf")
1126 (VNx8DI "vnx2di") (VNx8DF "vnx2df")])
1127
1128;; The predicate mode associated with an SVE data mode. For structure modes
1129;; this is equivalent to the <VPRED> of the subvector mode.
43cacb12
RS		 1130(define_mode_attr VPRED [(VNx16QI "VNx16BI")
1131 (VNx8HI "VNx8BI") (VNx8HF "VNx8BI")
1132 (VNx4SI "VNx4BI") (VNx4SF "VNx4BI")
9f4cbab8
RS		 1133 (VNx2DI "VNx2BI") (VNx2DF "VNx2BI")
1134 (VNx32QI "VNx16BI")
1135 (VNx16HI "VNx8BI") (VNx16HF "VNx8BI")
1136 (VNx8SI "VNx4BI") (VNx8SF "VNx4BI")
1137 (VNx4DI "VNx2BI") (VNx4DF "VNx2BI")
1138 (VNx48QI "VNx16BI")
1139 (VNx24HI "VNx8BI") (VNx24HF "VNx8BI")
1140 (VNx12SI "VNx4BI") (VNx12SF "VNx4BI")
1141 (VNx6DI "VNx2BI") (VNx6DF "VNx2BI")
1142 (VNx64QI "VNx16BI")
1143 (VNx32HI "VNx8BI") (VNx32HF "VNx8BI")
1144 (VNx16SI "VNx4BI") (VNx16SF "VNx4BI")
1145 (VNx8DI "VNx2BI") (VNx8DF "VNx2BI")])
43cacb12
RS		 1146
1147;; ...and again in lower case.
1148(define_mode_attr vpred [(VNx16QI "vnx16bi")
1149 (VNx8HI "vnx8bi") (VNx8HF "vnx8bi")
1150 (VNx4SI "vnx4bi") (VNx4SF "vnx4bi")
9f4cbab8
RS		 1151 (VNx2DI "vnx2bi") (VNx2DF "vnx2bi")
1152 (VNx32QI "vnx16bi")
1153 (VNx16HI "vnx8bi") (VNx16HF "vnx8bi")
1154 (VNx8SI "vnx4bi") (VNx8SF "vnx4bi")
1155 (VNx4DI "vnx2bi") (VNx4DF "vnx2bi")
1156 (VNx48QI "vnx16bi")
1157 (VNx24HI "vnx8bi") (VNx24HF "vnx8bi")
1158 (VNx12SI "vnx4bi") (VNx12SF "vnx4bi")
1159 (VNx6DI "vnx2bi") (VNx6DF "vnx2bi")
1160 (VNx64QI "vnx16bi")
1161 (VNx32HI "vnx8bi") (VNx32HF "vnx4bi")
1162 (VNx16SI "vnx4bi") (VNx16SF "vnx4bi")
1163 (VNx8DI "vnx2bi") (VNx8DF "vnx2bi")])
43cacb12 1164
9d63f43b
TC		 1165;; On AArch64 the By element instruction doesn't have a 2S variant.
1166;; However because the instruction always selects a pair of values
1167;; The normal 3SAME instruction can be used here instead.
1168(define_mode_attr FCMLA_maybe_lane [(V2SF "<Vtype>") (V4SF "<Vetype>[%4]")
1169 (V4HF "<Vetype>[%4]") (V8HF "<Vetype>[%4]")
1170 ])
1171
43e9d192
IB		 1172;; -------------------------------------------------------------------
1173;; Code Iterators
1174;; -------------------------------------------------------------------
1175
1176;; This code iterator allows the various shifts supported on the core
1177(define_code_iterator SHIFT [ashift ashiftrt lshiftrt rotatert])
1178
1179;; This code iterator allows the shifts supported in arithmetic instructions
1180(define_code_iterator ASHIFT [ashift ashiftrt lshiftrt])
1181
462e6f9a
ST		 1182(define_code_iterator SHIFTRT [ashiftrt lshiftrt])
1183
43e9d192
IB		 1184;; Code iterator for logical operations
1185(define_code_iterator LOGICAL [and ior xor])
1186
43cacb12
RS		 1187;; LOGICAL without AND.
1188(define_code_iterator LOGICAL_OR [ior xor])
1189
84be6032
AL		 1190;; Code iterator for logical operations whose :nlogical works on SIMD registers.
1191(define_code_iterator NLOGICAL [and ior])
1192
3204ac98
KT		 1193;; Code iterator for unary negate and bitwise complement.
1194(define_code_iterator NEG_NOT [neg not])
1195
43e9d192
IB		 1196;; Code iterator for sign/zero extension
1197(define_code_iterator ANY_EXTEND [sign_extend zero_extend])
1198
1199;; All division operations (signed/unsigned)
1200(define_code_iterator ANY_DIV [div udiv])
1201
1202;; Code iterator for sign/zero extraction
1203(define_code_iterator ANY_EXTRACT [sign_extract zero_extract])
1204
1205;; Code iterator for equality comparisons
1206(define_code_iterator EQL [eq ne])
1207
1208;; Code iterator for less-than and greater/equal-to
1209(define_code_iterator LTGE [lt ge])
1210
1211;; Iterator for __sync_<op> operations that where the operation can be
1212;; represented directly RTL. This is all of the sync operations bar
1213;; nand.
0462169c 1214(define_code_iterator atomic_op [plus minus ior xor and])
43e9d192
IB		 1215
1216;; Iterator for integer conversions
1217(define_code_iterator FIXUORS [fix unsigned_fix])
1218
1709ff9b
JG		 1219;; Iterator for float conversions
1220(define_code_iterator FLOATUORS [float unsigned_float])
1221
43e9d192
IB		 1222;; Code iterator for variants of vector max and min.
1223(define_code_iterator MAXMIN [smax smin umax umin])
1224
998eaf97
JG		 1225(define_code_iterator FMAXMIN [smax smin])
1226
8544ed6e
KT		 1227;; Signed and unsigned max operations.
1228(define_code_iterator USMAX [smax umax])
1229
dd550c99 1230;; Code iterator for plus and minus.
43e9d192
IB		 1231(define_code_iterator ADDSUB [plus minus])
1232
1233;; Code iterator for variants of vector saturating binary ops.
1234(define_code_iterator BINQOPS [ss_plus us_plus ss_minus us_minus])
1235
1236;; Code iterator for variants of vector saturating unary ops.
1237(define_code_iterator UNQOPS [ss_neg ss_abs])
1238
1239;; Code iterator for signed variants of vector saturating binary ops.
1240(define_code_iterator SBINQOPS [ss_plus ss_minus])
1241
889b9412
JG		 1242;; Comparison operators for <F>CM.
1243(define_code_iterator COMPARISONS [lt le eq ge gt])
1244
1245;; Unsigned comparison operators.
1246(define_code_iterator UCOMPARISONS [ltu leu geu gtu])
1247
75dd5ace
JG		 1248;; Unsigned comparison operators.
1249(define_code_iterator FAC_COMPARISONS [lt le ge gt])
1250
43cacb12 1251;; SVE integer unary operations.
69c5fdcf 1252(define_code_iterator SVE_INT_UNARY [abs neg not popcount])
43cacb12 1253
a08acce8 1254;; SVE integer binary operations.
6c4fd4a9 1255(define_code_iterator SVE_INT_BINARY [plus minus mult smax umax smin umin
9d4ac06e
RS		 1256 and ior xor])
1257
a08acce8 1258;; SVE integer binary division operations.
c38f7319
RS		 1259(define_code_iterator SVE_INT_BINARY_SD [div udiv])
1260
740c1ed7
RS		 1261;; SVE floating-point operations with an unpredicated all-register form.
1262(define_code_iterator SVE_UNPRED_FP_BINARY [plus minus mult])
1263
f22d7973
RS		 1264;; SVE integer comparisons.
1265(define_code_iterator SVE_INT_CMP [lt le eq ne ge gt ltu leu geu gtu])
1266
1267;; SVE floating-point comparisons.
1268(define_code_iterator SVE_FP_CMP [lt le eq ne ge gt])
1269
43e9d192
IB		 1270;; -------------------------------------------------------------------
1271;; Code Attributes
1272;; -------------------------------------------------------------------
1273;; Map rtl objects to optab names
1274(define_code_attr optab [(ashift "ashl")
1275 (ashiftrt "ashr")
1276 (lshiftrt "lshr")
1277 (rotatert "rotr")
1278 (sign_extend "extend")
1279 (zero_extend "zero_extend")
1280 (sign_extract "extv")
1281 (zero_extract "extzv")
384be29f
JG		 1282 (fix "fix")
1283 (unsigned_fix "fixuns")
1709ff9b
JG		 1284 (float "float")
1285 (unsigned_float "floatuns")
43cacb12 1286 (popcount "popcount")
43e9d192
IB		 1287 (and "and")
1288 (ior "ior")
1289 (xor "xor")
1290 (not "one_cmpl")
1291 (neg "neg")
1292 (plus "add")
1293 (minus "sub")
6c4fd4a9 1294 (mult "mul")
c38f7319
RS		 1295 (div "div")
1296 (udiv "udiv")
43e9d192
IB		 1297 (ss_plus "qadd")
1298 (us_plus "qadd")
1299 (ss_minus "qsub")
1300 (us_minus "qsub")
1301 (ss_neg "qneg")
1302 (ss_abs "qabs")
43cacb12
RS		 1303 (smin "smin")
1304 (smax "smax")
1305 (umin "umin")
1306 (umax "umax")
43e9d192
IB		 1307 (eq "eq")
1308 (ne "ne")
1309 (lt "lt")
889b9412
JG		 1310 (ge "ge")
1311 (le "le")
1312 (gt "gt")
1313 (ltu "ltu")
1314 (leu "leu")
1315 (geu "geu")
43cacb12 1316 (gtu "gtu")
d45b20a5 1317 (abs "abs")])
889b9412
JG		 1318
1319;; For comparison operators we use the FCM* and CM* instructions.
1320;; As there are no CMLE or CMLT instructions which act on 3 vector
1321;; operands, we must use CMGE or CMGT and swap the order of the
1322;; source operands.
1323
1324(define_code_attr n_optab [(lt "gt") (le "ge") (eq "eq") (ge "ge") (gt "gt")
1325 (ltu "hi") (leu "hs") (geu "hs") (gtu "hi")])
1326(define_code_attr cmp_1 [(lt "2") (le "2") (eq "1") (ge "1") (gt "1")
1327 (ltu "2") (leu "2") (geu "1") (gtu "1")])
1328(define_code_attr cmp_2 [(lt "1") (le "1") (eq "2") (ge "2") (gt "2")
1329 (ltu "1") (leu "1") (geu "2") (gtu "2")])
1330
1331(define_code_attr CMP [(lt "LT") (le "LE") (eq "EQ") (ge "GE") (gt "GT")
714e1b3b
KT		 1332 (ltu "LTU") (leu "LEU") (ne "NE") (geu "GEU")
1333 (gtu "GTU")])
43e9d192 1334
f22d7973
RS		 1335;; The AArch64 condition associated with an rtl comparison code.
1336(define_code_attr cmp_op [(lt "lt")
1337 (le "le")
1338 (eq "eq")
1339 (ne "ne")
1340 (ge "ge")
1341 (gt "gt")
1342 (ltu "lo")
1343 (leu "ls")
1344 (geu "hs")
1345 (gtu "hi")])
1346
384be29f
JG		 1347(define_code_attr fix_trunc_optab [(fix "fix_trunc")
1348 (unsigned_fix "fixuns_trunc")])
1349
43e9d192
IB		 1350;; Optab prefix for sign/zero-extending operations
1351(define_code_attr su_optab [(sign_extend "") (zero_extend "u")
1352 (div "") (udiv "u")
1353 (fix "") (unsigned_fix "u")
1709ff9b 1354 (float "s") (unsigned_float "u")
43e9d192
IB		 1355 (ss_plus "s") (us_plus "u")
1356 (ss_minus "s") (us_minus "u")])
1357
1358;; Similar for the instruction mnemonics
1359(define_code_attr shift [(ashift "lsl") (ashiftrt "asr")
1360 (lshiftrt "lsr") (rotatert "ror")])
1361
462e6f9a
ST		 1362;; Op prefix for shift right and accumulate.
1363(define_code_attr sra_op [(ashiftrt "s") (lshiftrt "u")])
1364
43e9d192
IB		 1365;; Map shift operators onto underlying bit-field instructions
1366(define_code_attr bfshift [(ashift "ubfiz") (ashiftrt "sbfx")
1367 (lshiftrt "ubfx") (rotatert "extr")])
1368
1369;; Logical operator instruction mnemonics
1370(define_code_attr logical [(and "and") (ior "orr") (xor "eor")])
1371
3204ac98
KT		 1372;; Operation names for negate and bitwise complement.
1373(define_code_attr neg_not_op [(neg "neg") (not "not")])
1374
43cacb12 1375;; Similar, but when the second operand is inverted.
43e9d192
IB		 1376(define_code_attr nlogical [(and "bic") (ior "orn") (xor "eon")])
1377
43cacb12
RS		 1378;; Similar, but when both operands are inverted.
1379(define_code_attr logical_nn [(and "nor") (ior "nand")])
1380
43e9d192
IB		 1381;; Sign- or zero-extending data-op
1382(define_code_attr su [(sign_extend "s") (zero_extend "u")
1383 (sign_extract "s") (zero_extract "u")
1384 (fix "s") (unsigned_fix "u")
998eaf97
JG		 1385 (div "s") (udiv "u")
1386 (smax "s") (umax "u")
1387 (smin "s") (umin "u")])
43e9d192 1388
43cacb12
RS		 1389;; Whether a shift is left or right.
1390(define_code_attr lr [(ashift "l") (ashiftrt "r") (lshiftrt "r")])
1391
096e8448
JW		 1392;; Emit conditional branch instructions.
1393(define_code_attr bcond [(eq "beq") (ne "bne") (lt "bne") (ge "beq")])
1394
43e9d192
IB		 1395;; Emit cbz/cbnz depending on comparison type.
1396(define_code_attr cbz [(eq "cbz") (ne "cbnz") (lt "cbnz") (ge "cbz")])
1397
973d2e01
TP		 1398;; Emit inverted cbz/cbnz depending on comparison type.
1399(define_code_attr inv_cb [(eq "cbnz") (ne "cbz") (lt "cbz") (ge "cbnz")])
1400
43e9d192
IB		 1401;; Emit tbz/tbnz depending on comparison type.
1402(define_code_attr tbz [(eq "tbz") (ne "tbnz") (lt "tbnz") (ge "tbz")])
1403
973d2e01
TP		 1404;; Emit inverted tbz/tbnz depending on comparison type.
1405(define_code_attr inv_tb [(eq "tbnz") (ne "tbz") (lt "tbz") (ge "tbnz")])
1406
43e9d192 1407;; Max/min attributes.
998eaf97
JG		 1408(define_code_attr maxmin [(smax "max")
1409 (smin "min")
1410 (umax "max")
1411 (umin "min")])
43e9d192
IB		 1412
1413;; MLA/MLS attributes.
1414(define_code_attr as [(ss_plus "a") (ss_minus "s")])
1415
0462169c
SN		 1416;; Atomic operations
1417(define_code_attr atomic_optab
1418 [(ior "or") (xor "xor") (and "and") (plus "add") (minus "sub")])
1419
1420(define_code_attr atomic_op_operand
1421 [(ior "aarch64_logical_operand")
1422 (xor "aarch64_logical_operand")
1423 (and "aarch64_logical_operand")
1424 (plus "aarch64_plus_operand")
1425 (minus "aarch64_plus_operand")])
43e9d192 1426
356c32e2
MW		 1427;; Constants acceptable for atomic operations.
1428;; This definition must appear in this file before the iterators it refers to.
1429(define_code_attr const_atomic
1430 [(plus "IJ") (minus "IJ")
1431 (xor "<lconst_atomic>") (ior "<lconst_atomic>")
1432 (and "<lconst_atomic>")])
1433
1434;; Attribute to describe constants acceptable in atomic logical operations
1435(define_mode_attr lconst_atomic [(QI "K") (HI "K") (SI "K") (DI "L")])
1436
43cacb12
RS		 1437;; The integer SVE instruction that implements an rtx code.
1438(define_code_attr sve_int_op [(plus "add")
9d4ac06e 1439 (minus "sub")
6c4fd4a9 1440 (mult "mul")
c38f7319
RS		 1441 (div "sdiv")
1442 (udiv "udiv")
69c5fdcf 1443 (abs "abs")
43cacb12
RS		 1444 (neg "neg")
1445 (smin "smin")
1446 (smax "smax")
1447 (umin "umin")
1448 (umax "umax")
1449 (and "and")
1450 (ior "orr")
1451 (xor "eor")
1452 (not "not")
1453 (popcount "cnt")])
1454
a08acce8
RH		 1455(define_code_attr sve_int_op_rev [(plus "add")
1456 (minus "subr")
1457 (mult "mul")
1458 (div "sdivr")
1459 (udiv "udivr")
1460 (smin "smin")
1461 (smax "smax")
1462 (umin "umin")
1463 (umax "umax")
1464 (and "and")
1465 (ior "orr")
1466 (xor "eor")])
1467
43cacb12
RS		 1468;; The floating-point SVE instruction that implements an rtx code.
1469(define_code_attr sve_fp_op [(plus "fadd")
740c1ed7 1470 (minus "fsub")
d45b20a5 1471 (mult "fmul")])
43cacb12 1472
f22d7973
RS		 1473;; The SVE immediate constraint to use for an rtl code.
1474(define_code_attr sve_imm_con [(eq "vsc")
1475 (ne "vsc")
1476 (lt "vsc")
1477 (ge "vsc")
1478 (le "vsc")
1479 (gt "vsc")
1480 (ltu "vsd")
1481 (leu "vsd")
1482 (geu "vsd")
1483 (gtu "vsd")])
1484
43e9d192
IB		 1485;; -------------------------------------------------------------------
1486;; Int Iterators.
1487;; -------------------------------------------------------------------
75add2d0
KT		 1488
1489;; The unspec codes for the SABAL, UABAL AdvancedSIMD instructions.
1490(define_int_iterator ABAL [UNSPEC_SABAL UNSPEC_UABAL])
1491
1492;; The unspec codes for the SABDL2, UABDL2 AdvancedSIMD instructions.
1493(define_int_iterator ABDL2 [UNSPEC_SABDL2 UNSPEC_UABDL2])
1494
1495;; The unspec codes for the SADALP, UADALP AdvancedSIMD instructions.
1496(define_int_iterator ADALP [UNSPEC_SADALP UNSPEC_UADALP])
1497
43e9d192
IB		 1498(define_int_iterator MAXMINV [UNSPEC_UMAXV UNSPEC_UMINV
1499 UNSPEC_SMAXV UNSPEC_SMINV])
1500
998eaf97
JG		 1501(define_int_iterator FMAXMINV [UNSPEC_FMAXV UNSPEC_FMINV
1502 UNSPEC_FMAXNMV UNSPEC_FMINNMV])
43e9d192 1503
43cacb12
RS		 1504(define_int_iterator LOGICALF [UNSPEC_ANDF UNSPEC_IORF UNSPEC_XORF])
1505
43e9d192
IB		 1506(define_int_iterator HADDSUB [UNSPEC_SHADD UNSPEC_UHADD
1507 UNSPEC_SRHADD UNSPEC_URHADD
1508 UNSPEC_SHSUB UNSPEC_UHSUB
1509 UNSPEC_SRHSUB UNSPEC_URHSUB])
1510
42addb5a
RS		 1511(define_int_iterator HADD [UNSPEC_SHADD UNSPEC_UHADD])
1512
1513(define_int_iterator RHADD [UNSPEC_SRHADD UNSPEC_URHADD])
1514
7a08d813 1515(define_int_iterator DOTPROD [UNSPEC_SDOT UNSPEC_UDOT])
43e9d192
IB		 1516
1517(define_int_iterator ADDSUBHN [UNSPEC_ADDHN UNSPEC_RADDHN
1518 UNSPEC_SUBHN UNSPEC_RSUBHN])
1519
1520(define_int_iterator ADDSUBHN2 [UNSPEC_ADDHN2 UNSPEC_RADDHN2
1521 UNSPEC_SUBHN2 UNSPEC_RSUBHN2])
1522
1efafef3
TC		 1523(define_int_iterator FMAXMIN_UNS [UNSPEC_FMAX UNSPEC_FMIN
1524 UNSPEC_FMAXNM UNSPEC_FMINNM])
202d0c11 1525
8fc16d72
ST		 1526(define_int_iterator PAUTH_LR_SP [UNSPEC_PACIASP UNSPEC_AUTIASP
1527 UNSPEC_PACIBSP UNSPEC_AUTIBSP])
db58fd89 1528
8fc16d72
ST		 1529(define_int_iterator PAUTH_17_16 [UNSPEC_PACIA1716 UNSPEC_AUTIA1716
1530 UNSPEC_PACIB1716 UNSPEC_AUTIB1716])
db58fd89 1531
43e9d192
IB		 1532(define_int_iterator VQDMULH [UNSPEC_SQDMULH UNSPEC_SQRDMULH])
1533
1534(define_int_iterator USSUQADD [UNSPEC_SUQADD UNSPEC_USQADD])
1535
1536(define_int_iterator SUQMOVN [UNSPEC_SQXTN UNSPEC_UQXTN])
1537
1538(define_int_iterator VSHL [UNSPEC_SSHL UNSPEC_USHL
1539 UNSPEC_SRSHL UNSPEC_URSHL])
1540
1541(define_int_iterator VSHLL [UNSPEC_SSHLL UNSPEC_USHLL])
1542
1543(define_int_iterator VQSHL [UNSPEC_SQSHL UNSPEC_UQSHL
1544 UNSPEC_SQRSHL UNSPEC_UQRSHL])
1545
1546(define_int_iterator VSRA [UNSPEC_SSRA UNSPEC_USRA
1547 UNSPEC_SRSRA UNSPEC_URSRA])
1548
1549(define_int_iterator VSLRI [UNSPEC_SSLI UNSPEC_USLI
1550 UNSPEC_SSRI UNSPEC_USRI])
1551
1552
1553(define_int_iterator VRSHR_N [UNSPEC_SRSHR UNSPEC_URSHR])
1554
1555(define_int_iterator VQSHL_N [UNSPEC_SQSHLU UNSPEC_SQSHL UNSPEC_UQSHL])
1556
1557(define_int_iterator VQSHRN_N [UNSPEC_SQSHRUN UNSPEC_SQRSHRUN
1558 UNSPEC_SQSHRN UNSPEC_UQSHRN
1559 UNSPEC_SQRSHRN UNSPEC_UQRSHRN])
1560
57b26d65
MW		 1561(define_int_iterator SQRDMLH_AS [UNSPEC_SQRDMLAH UNSPEC_SQRDMLSH])
1562
cc4d934f
JG		 1563(define_int_iterator PERMUTE [UNSPEC_ZIP1 UNSPEC_ZIP2
1564 UNSPEC_TRN1 UNSPEC_TRN2
1565 UNSPEC_UZP1 UNSPEC_UZP2])
43e9d192 1566
43cacb12
RS		 1567(define_int_iterator OPTAB_PERMUTE [UNSPEC_ZIP1 UNSPEC_ZIP2
1568 UNSPEC_UZP1 UNSPEC_UZP2])
1569
923fcec3
AL		 1570(define_int_iterator REVERSE [UNSPEC_REV64 UNSPEC_REV32 UNSPEC_REV16])
1571
42fc9a7f 1572(define_int_iterator FRINT [UNSPEC_FRINTZ UNSPEC_FRINTP UNSPEC_FRINTM
0659ce6f
JG		 1573 UNSPEC_FRINTN UNSPEC_FRINTI UNSPEC_FRINTX
1574 UNSPEC_FRINTA])
42fc9a7f
JG		 1575
1576(define_int_iterator FCVT [UNSPEC_FRINTZ UNSPEC_FRINTP UNSPEC_FRINTM
ce966824 1577 UNSPEC_FRINTA UNSPEC_FRINTN])
42fc9a7f 1578
3f598afe
JW		 1579(define_int_iterator FCVT_F2FIXED [UNSPEC_FCVTZS UNSPEC_FCVTZU])
1580(define_int_iterator FCVT_FIXED2F [UNSPEC_SCVTF UNSPEC_UCVTF])
1581
5d357f26
KT		 1582(define_int_iterator CRC [UNSPEC_CRC32B UNSPEC_CRC32H UNSPEC_CRC32W
1583 UNSPEC_CRC32X UNSPEC_CRC32CB UNSPEC_CRC32CH
1584 UNSPEC_CRC32CW UNSPEC_CRC32CX])
1585
5a7a4e80
TB		 1586(define_int_iterator CRYPTO_AES [UNSPEC_AESE UNSPEC_AESD])
1587(define_int_iterator CRYPTO_AESMC [UNSPEC_AESMC UNSPEC_AESIMC])
1588
30442682
TB		 1589(define_int_iterator CRYPTO_SHA1 [UNSPEC_SHA1C UNSPEC_SHA1M UNSPEC_SHA1P])
1590
b9cb0a44
TB		 1591(define_int_iterator CRYPTO_SHA256 [UNSPEC_SHA256H UNSPEC_SHA256H2])
1592
27086ea3
MC		 1593(define_int_iterator CRYPTO_SHA512 [UNSPEC_SHA512H UNSPEC_SHA512H2])
1594
1595(define_int_iterator CRYPTO_SM3TT [UNSPEC_SM3TT1A UNSPEC_SM3TT1B
1596 UNSPEC_SM3TT2A UNSPEC_SM3TT2B])
1597
1598(define_int_iterator CRYPTO_SM3PART [UNSPEC_SM3PARTW1 UNSPEC_SM3PARTW2])
1599
1600;; Iterators for fp16 operations
1601
1602(define_int_iterator VFMLA16_LOW [UNSPEC_FMLAL UNSPEC_FMLSL])
1603
1604(define_int_iterator VFMLA16_HIGH [UNSPEC_FMLAL2 UNSPEC_FMLSL2])
1605
43cacb12
RS		 1606(define_int_iterator UNPACK [UNSPEC_UNPACKSHI UNSPEC_UNPACKUHI
1607 UNSPEC_UNPACKSLO UNSPEC_UNPACKULO])
1608
1609(define_int_iterator UNPACK_UNSIGNED [UNSPEC_UNPACKULO UNSPEC_UNPACKUHI])
1610
11e9443f
RS		 1611(define_int_iterator MUL_HIGHPART [UNSPEC_SMUL_HIGHPART UNSPEC_UMUL_HIGHPART])
1612
b0760a40
RS		 1613(define_int_iterator SVE_INT_REDUCTION [UNSPEC_ANDV
1614 UNSPEC_IORV
1615 UNSPEC_SMAXV
1616 UNSPEC_SMINV
1617 UNSPEC_UMAXV
1618 UNSPEC_UMINV
1619 UNSPEC_XORV])
1620
1621(define_int_iterator SVE_FP_REDUCTION [UNSPEC_FADDV
1622 UNSPEC_FMAXV
1623 UNSPEC_FMAXNMV
1624 UNSPEC_FMINV
1625 UNSPEC_FMINNMV])
1626
d45b20a5
RS		 1627(define_int_iterator SVE_COND_FP_UNARY [UNSPEC_COND_FABS
1628 UNSPEC_COND_FNEG
1629 UNSPEC_COND_FRINTA
1630 UNSPEC_COND_FRINTI
1631 UNSPEC_COND_FRINTM
1632 UNSPEC_COND_FRINTN
1633 UNSPEC_COND_FRINTP
1634 UNSPEC_COND_FRINTX
1635 UNSPEC_COND_FRINTZ
1636 UNSPEC_COND_FSQRT])
1637
cb18e86d
RS		 1638(define_int_iterator SVE_COND_FP_BINARY [UNSPEC_COND_FADD
1639 UNSPEC_COND_FDIV
1640 UNSPEC_COND_FMAXNM
1641 UNSPEC_COND_FMINNM
1642 UNSPEC_COND_FMUL
1643 UNSPEC_COND_FSUB])
0d2b3bca 1644
214c42fa
RS		 1645;; Floating-point max/min operations that correspond to optabs,
1646;; as opposed to those that are internal to the port.
1647(define_int_iterator SVE_COND_FP_MAXMIN_PUBLIC [UNSPEC_COND_FMAXNM
1648 UNSPEC_COND_FMINNM])
1649
b41d1f6e
RS		 1650(define_int_iterator SVE_COND_FP_TERNARY [UNSPEC_COND_FMLA
1651 UNSPEC_COND_FMLS
1652 UNSPEC_COND_FNMLA
1653 UNSPEC_COND_FNMLS])
1654
cb18e86d
RS		 1655(define_int_iterator SVE_COND_FP_CMP [UNSPEC_COND_FCMEQ
1656 UNSPEC_COND_FCMGE
1657 UNSPEC_COND_FCMGT
1658 UNSPEC_COND_FCMLE
1659 UNSPEC_COND_FCMLT
1660 UNSPEC_COND_FCMNE])
43cacb12 1661
9d63f43b
TC		 1662(define_int_iterator FCADD [UNSPEC_FCADD90
1663 UNSPEC_FCADD270])
1664
1665(define_int_iterator FCMLA [UNSPEC_FCMLA
1666 UNSPEC_FCMLA90
1667 UNSPEC_FCMLA180
1668 UNSPEC_FCMLA270])
1669
d81cb613
MW		 1670;; Iterators for atomic operations.
1671
1672(define_int_iterator ATOMIC_LDOP
1673 [UNSPECV_ATOMIC_LDOP_OR UNSPECV_ATOMIC_LDOP_BIC
1674 UNSPECV_ATOMIC_LDOP_XOR UNSPECV_ATOMIC_LDOP_PLUS])
1675
1676(define_int_attr atomic_ldop
1677 [(UNSPECV_ATOMIC_LDOP_OR "set") (UNSPECV_ATOMIC_LDOP_BIC "clr")
1678 (UNSPECV_ATOMIC_LDOP_XOR "eor") (UNSPECV_ATOMIC_LDOP_PLUS "add")])
1679
7803ec5e
RH		 1680(define_int_attr atomic_ldoptab
1681 [(UNSPECV_ATOMIC_LDOP_OR "ior") (UNSPECV_ATOMIC_LDOP_BIC "bic")
1682 (UNSPECV_ATOMIC_LDOP_XOR "xor") (UNSPECV_ATOMIC_LDOP_PLUS "add")])
1683
43e9d192
IB		 1684;; -------------------------------------------------------------------
1685;; Int Iterators Attributes.
1686;; -------------------------------------------------------------------
43cacb12
RS		 1687
1688;; The optab associated with an operation. Note that for ANDF, IORF
1689;; and XORF, the optab pattern is not actually defined; we just use this
1690;; name for consistency with the integer patterns.
1691(define_int_attr optab [(UNSPEC_ANDF "and")
1692 (UNSPEC_IORF "ior")
898f07b0
RS		 1693 (UNSPEC_XORF "xor")
1694 (UNSPEC_ANDV "and")
1695 (UNSPEC_IORV "ior")
0972596e 1696 (UNSPEC_XORV "xor")
b0760a40
RS		 1697 (UNSPEC_UMAXV "umax")
1698 (UNSPEC_UMINV "umin")
1699 (UNSPEC_SMAXV "smax")
1700 (UNSPEC_SMINV "smin")
1701 (UNSPEC_FADDV "plus")
1702 (UNSPEC_FMAXNMV "smax")
1703 (UNSPEC_FMAXV "smax_nan")
1704 (UNSPEC_FMINNMV "smin")
1705 (UNSPEC_FMINV "smin_nan")
d45b20a5 1706 (UNSPEC_COND_FABS "abs")
cb18e86d
RS		 1707 (UNSPEC_COND_FADD "add")
1708 (UNSPEC_COND_FDIV "div")
1709 (UNSPEC_COND_FMAXNM "smax")
1710 (UNSPEC_COND_FMINNM "smin")
b41d1f6e
RS		 1711 (UNSPEC_COND_FMLA "fma")
1712 (UNSPEC_COND_FMLS "fnma")
cb18e86d 1713 (UNSPEC_COND_FMUL "mul")
d45b20a5 1714 (UNSPEC_COND_FNEG "neg")
b41d1f6e 1715 (UNSPEC_COND_FNMLA "fnms")
cb18e86d 1716 (UNSPEC_COND_FNMLS "fms")
d45b20a5
RS		 1717 (UNSPEC_COND_FRINTA "round")
1718 (UNSPEC_COND_FRINTI "nearbyint")
1719 (UNSPEC_COND_FRINTM "floor")
1720 (UNSPEC_COND_FRINTN "frintn")
1721 (UNSPEC_COND_FRINTP "ceil")
1722 (UNSPEC_COND_FRINTX "rint")
1723 (UNSPEC_COND_FRINTZ "btrunc")
1724 (UNSPEC_COND_FSQRT "sqrt")
cb18e86d 1725 (UNSPEC_COND_FSUB "sub")])
43cacb12 1726
998eaf97
JG		 1727(define_int_attr maxmin_uns [(UNSPEC_UMAXV "umax")
1728 (UNSPEC_UMINV "umin")
1729 (UNSPEC_SMAXV "smax")
1730 (UNSPEC_SMINV "smin")
1731 (UNSPEC_FMAX "smax_nan")
1732 (UNSPEC_FMAXNMV "smax")
1733 (UNSPEC_FMAXV "smax_nan")
1734 (UNSPEC_FMIN "smin_nan")
1735 (UNSPEC_FMINNMV "smin")
1efafef3
TC		 1736 (UNSPEC_FMINV "smin_nan")
1737 (UNSPEC_FMAXNM "fmax")
214c42fa
RS		 1738 (UNSPEC_FMINNM "fmin")
1739 (UNSPEC_COND_FMAXNM "fmax")
1740 (UNSPEC_COND_FMINNM "fmin")])
998eaf97
JG		 1741
1742(define_int_attr maxmin_uns_op [(UNSPEC_UMAXV "umax")
1743 (UNSPEC_UMINV "umin")
1744 (UNSPEC_SMAXV "smax")
1745 (UNSPEC_SMINV "smin")
1746 (UNSPEC_FMAX "fmax")
1747 (UNSPEC_FMAXNMV "fmaxnm")
1748 (UNSPEC_FMAXV "fmax")
1749 (UNSPEC_FMIN "fmin")
1750 (UNSPEC_FMINNMV "fminnm")
1efafef3
TC		 1751 (UNSPEC_FMINV "fmin")
1752 (UNSPEC_FMAXNM "fmaxnm")
1753 (UNSPEC_FMINNM "fminnm")])
202d0c11 1754
43cacb12
RS		 1755;; The SVE logical instruction that implements an unspec.
1756(define_int_attr logicalf_op [(UNSPEC_ANDF "and")
1757 (UNSPEC_IORF "orr")
1758 (UNSPEC_XORF "eor")])
1759
1760;; "s" for signed operations and "u" for unsigned ones.
1761(define_int_attr su [(UNSPEC_UNPACKSHI "s")
1762 (UNSPEC_UNPACKUHI "u")
1763 (UNSPEC_UNPACKSLO "s")
11e9443f
RS		 1764 (UNSPEC_UNPACKULO "u")
1765 (UNSPEC_SMUL_HIGHPART "s")
1766 (UNSPEC_UMUL_HIGHPART "u")])
43cacb12 1767
43e9d192
IB		 1768(define_int_attr sur [(UNSPEC_SHADD "s") (UNSPEC_UHADD "u")
1769 (UNSPEC_SRHADD "sr") (UNSPEC_URHADD "ur")
1770 (UNSPEC_SHSUB "s") (UNSPEC_UHSUB "u")
1771 (UNSPEC_SRHSUB "sr") (UNSPEC_URHSUB "ur")
1772 (UNSPEC_ADDHN "") (UNSPEC_RADDHN "r")
75add2d0
KT		 1773 (UNSPEC_SABAL "s") (UNSPEC_UABAL "u")
1774 (UNSPEC_SABDL2 "s") (UNSPEC_UABDL2 "u")
1775 (UNSPEC_SADALP "s") (UNSPEC_UADALP "u")
43e9d192
IB		 1776 (UNSPEC_SUBHN "") (UNSPEC_RSUBHN "r")
1777 (UNSPEC_ADDHN2 "") (UNSPEC_RADDHN2 "r")
1778 (UNSPEC_SUBHN2 "") (UNSPEC_RSUBHN2 "r")
1779 (UNSPEC_SQXTN "s") (UNSPEC_UQXTN "u")
1780 (UNSPEC_USQADD "us") (UNSPEC_SUQADD "su")
1781 (UNSPEC_SSLI "s") (UNSPEC_USLI "u")
1782 (UNSPEC_SSRI "s") (UNSPEC_USRI "u")
1783 (UNSPEC_USRA "u") (UNSPEC_SSRA "s")
1784 (UNSPEC_URSRA "ur") (UNSPEC_SRSRA "sr")
1785 (UNSPEC_URSHR "ur") (UNSPEC_SRSHR "sr")
1786 (UNSPEC_SQSHLU "s") (UNSPEC_SQSHL "s")
1787 (UNSPEC_UQSHL "u")
1788 (UNSPEC_SQSHRUN "s") (UNSPEC_SQRSHRUN "s")
1789 (UNSPEC_SQSHRN "s") (UNSPEC_UQSHRN "u")
1790 (UNSPEC_SQRSHRN "s") (UNSPEC_UQRSHRN "u")
1791 (UNSPEC_USHL "u") (UNSPEC_SSHL "s")
1792 (UNSPEC_USHLL "u") (UNSPEC_SSHLL "s")
1793 (UNSPEC_URSHL "ur") (UNSPEC_SRSHL "sr")
1794 (UNSPEC_UQRSHL "u") (UNSPEC_SQRSHL "s")
7a08d813 1795 (UNSPEC_SDOT "s") (UNSPEC_UDOT "u")
43e9d192
IB		 1796])
1797
1798(define_int_attr r [(UNSPEC_SQDMULH "") (UNSPEC_SQRDMULH "r")
1799 (UNSPEC_SQSHRUN "") (UNSPEC_SQRSHRUN "r")
1800 (UNSPEC_SQSHRN "") (UNSPEC_UQSHRN "")
1801 (UNSPEC_SQRSHRN "r") (UNSPEC_UQRSHRN "r")
1802 (UNSPEC_SQSHL "") (UNSPEC_UQSHL "")
1803 (UNSPEC_SQRSHL "r")(UNSPEC_UQRSHL "r")
1804])
1805
1806(define_int_attr lr [(UNSPEC_SSLI "l") (UNSPEC_USLI "l")
1807 (UNSPEC_SSRI "r") (UNSPEC_USRI "r")])
1808
1809(define_int_attr u [(UNSPEC_SQSHLU "u") (UNSPEC_SQSHL "") (UNSPEC_UQSHL "")
1810 (UNSPEC_SQSHRUN "u") (UNSPEC_SQRSHRUN "u")
42addb5a
RS		 1811 (UNSPEC_SQSHRN "") (UNSPEC_UQSHRN "")
1812 (UNSPEC_SQRSHRN "") (UNSPEC_UQRSHRN "")
1813 (UNSPEC_SHADD "") (UNSPEC_UHADD "u")
1814 (UNSPEC_SRHADD "") (UNSPEC_URHADD "u")])
43e9d192
IB		 1815
1816(define_int_attr addsub [(UNSPEC_SHADD "add")
1817 (UNSPEC_UHADD "add")
1818 (UNSPEC_SRHADD "add")
1819 (UNSPEC_URHADD "add")
1820 (UNSPEC_SHSUB "sub")
1821 (UNSPEC_UHSUB "sub")
1822 (UNSPEC_SRHSUB "sub")
1823 (UNSPEC_URHSUB "sub")
1824 (UNSPEC_ADDHN "add")
1825 (UNSPEC_SUBHN "sub")
1826 (UNSPEC_RADDHN "add")
1827 (UNSPEC_RSUBHN "sub")
1828 (UNSPEC_ADDHN2 "add")
1829 (UNSPEC_SUBHN2 "sub")
1830 (UNSPEC_RADDHN2 "add")
1831 (UNSPEC_RSUBHN2 "sub")])
1832
cb23a30c
JG		 1833(define_int_attr offsetlr [(UNSPEC_SSLI "") (UNSPEC_USLI "")
1834 (UNSPEC_SSRI "offset_")
1835 (UNSPEC_USRI "offset_")])
43e9d192 1836
42fc9a7f
JG		 1837;; Standard pattern names for floating-point rounding instructions.
1838(define_int_attr frint_pattern [(UNSPEC_FRINTZ "btrunc")
1839 (UNSPEC_FRINTP "ceil")
1840 (UNSPEC_FRINTM "floor")
1841 (UNSPEC_FRINTI "nearbyint")
1842 (UNSPEC_FRINTX "rint")
0659ce6f
JG		 1843 (UNSPEC_FRINTA "round")
1844 (UNSPEC_FRINTN "frintn")])
42fc9a7f
JG		 1845
1846;; frint suffix for floating-point rounding instructions.
1847(define_int_attr frint_suffix [(UNSPEC_FRINTZ "z") (UNSPEC_FRINTP "p")
1848 (UNSPEC_FRINTM "m") (UNSPEC_FRINTI "i")
0659ce6f
JG		 1849 (UNSPEC_FRINTX "x") (UNSPEC_FRINTA "a")
1850 (UNSPEC_FRINTN "n")])
42fc9a7f
JG		 1851
1852(define_int_attr fcvt_pattern [(UNSPEC_FRINTZ "btrunc") (UNSPEC_FRINTA "round")
ce966824
JG		 1853 (UNSPEC_FRINTP "ceil") (UNSPEC_FRINTM "floor")
1854 (UNSPEC_FRINTN "frintn")])
42fc9a7f 1855
3f598afe
JW		 1856(define_int_attr fcvt_fixed_insn [(UNSPEC_SCVTF "scvtf")
1857 (UNSPEC_UCVTF "ucvtf")
1858 (UNSPEC_FCVTZS "fcvtzs")
1859 (UNSPEC_FCVTZU "fcvtzu")])
1860
db58fd89 1861;; Pointer authentication mnemonic prefix.
8fc16d72
ST		 1862(define_int_attr pauth_mnem_prefix [(UNSPEC_PACIASP "pacia")
1863 (UNSPEC_PACIBSP "pacib")
1864 (UNSPEC_PACIA1716 "pacia")
1865 (UNSPEC_PACIB1716 "pacib")
1866 (UNSPEC_AUTIASP "autia")
1867 (UNSPEC_AUTIBSP "autib")
1868 (UNSPEC_AUTIA1716 "autia")
1869 (UNSPEC_AUTIB1716 "autib")])
1870
1871(define_int_attr pauth_key [(UNSPEC_PACIASP "AARCH64_KEY_A")
1872 (UNSPEC_PACIBSP "AARCH64_KEY_B")
1873 (UNSPEC_PACIA1716 "AARCH64_KEY_A")
1874 (UNSPEC_PACIB1716 "AARCH64_KEY_B")
1875 (UNSPEC_AUTIASP "AARCH64_KEY_A")
1876 (UNSPEC_AUTIBSP "AARCH64_KEY_B")
1877 (UNSPEC_AUTIA1716 "AARCH64_KEY_A")
1878 (UNSPEC_AUTIB1716 "AARCH64_KEY_B")])
1879
1880;; Pointer authentication HINT number for NOP space instructions using A and
1881;; B key.
1882(define_int_attr pauth_hint_num [(UNSPEC_PACIASP "25")
1883 (UNSPEC_PACIBSP "27")
1884 (UNSPEC_AUTIASP "29")
1885 (UNSPEC_AUTIBSP "31")
1886 (UNSPEC_PACIA1716 "8")
1887 (UNSPEC_PACIB1716 "10")
1888 (UNSPEC_AUTIA1716 "12")
1889 (UNSPEC_AUTIB1716 "14")])
db58fd89 1890
3e2751ce
RS		 1891(define_int_attr perm_insn [(UNSPEC_ZIP1 "zip1") (UNSPEC_ZIP2 "zip2")
1892 (UNSPEC_TRN1 "trn1") (UNSPEC_TRN2 "trn2")
1893 (UNSPEC_UZP1 "uzp1") (UNSPEC_UZP2 "uzp2")])
cc4d934f 1894
923fcec3
AL		 1895; op code for REV instructions (size within which elements are reversed).
1896(define_int_attr rev_op [(UNSPEC_REV64 "64") (UNSPEC_REV32 "32")
1897 (UNSPEC_REV16 "16")])
1898
3e2751ce 1899(define_int_attr perm_hilo [(UNSPEC_UNPACKSHI "hi") (UNSPEC_UNPACKUHI "hi")
43cacb12 1900 (UNSPEC_UNPACKSLO "lo") (UNSPEC_UNPACKULO "lo")])
0050faf8 1901
9bfb28ed
RS		 1902;; Return true if the associated optab refers to the high-numbered lanes,
1903;; false if it refers to the low-numbered lanes. The convention is for
1904;; "hi" to refer to the low-numbered lanes (the first ones in memory)
1905;; for big-endian.
1906(define_int_attr hi_lanes_optab [(UNSPEC_UNPACKSHI "!BYTES_BIG_ENDIAN")
1907 (UNSPEC_UNPACKUHI "!BYTES_BIG_ENDIAN")
1908 (UNSPEC_UNPACKSLO "BYTES_BIG_ENDIAN")
1909 (UNSPEC_UNPACKULO "BYTES_BIG_ENDIAN")])
1910
5d357f26
KT		 1911(define_int_attr crc_variant [(UNSPEC_CRC32B "crc32b") (UNSPEC_CRC32H "crc32h")
1912 (UNSPEC_CRC32W "crc32w") (UNSPEC_CRC32X "crc32x")
1913 (UNSPEC_CRC32CB "crc32cb") (UNSPEC_CRC32CH "crc32ch")
1914 (UNSPEC_CRC32CW "crc32cw") (UNSPEC_CRC32CX "crc32cx")])
1915
1916(define_int_attr crc_mode [(UNSPEC_CRC32B "QI") (UNSPEC_CRC32H "HI")
1917 (UNSPEC_CRC32W "SI") (UNSPEC_CRC32X "DI")
1918 (UNSPEC_CRC32CB "QI") (UNSPEC_CRC32CH "HI")
1919 (UNSPEC_CRC32CW "SI") (UNSPEC_CRC32CX "DI")])
1920
5a7a4e80
TB		 1921(define_int_attr aes_op [(UNSPEC_AESE "e") (UNSPEC_AESD "d")])
1922(define_int_attr aesmc_op [(UNSPEC_AESMC "mc") (UNSPEC_AESIMC "imc")])
30442682
TB		 1923
1924(define_int_attr sha1_op [(UNSPEC_SHA1C "c") (UNSPEC_SHA1P "p")
1925 (UNSPEC_SHA1M "m")])
b9cb0a44
TB		 1926
1927(define_int_attr sha256_op [(UNSPEC_SHA256H "") (UNSPEC_SHA256H2 "2")])
57b26d65
MW		 1928
1929(define_int_attr rdma_as [(UNSPEC_SQRDMLAH "a") (UNSPEC_SQRDMLSH "s")])
27086ea3
MC		 1930
1931(define_int_attr sha512_op [(UNSPEC_SHA512H "") (UNSPEC_SHA512H2 "2")])
1932
1933(define_int_attr sm3tt_op [(UNSPEC_SM3TT1A "1a") (UNSPEC_SM3TT1B "1b")
1934 (UNSPEC_SM3TT2A "2a") (UNSPEC_SM3TT2B "2b")])
1935
1936(define_int_attr sm3part_op [(UNSPEC_SM3PARTW1 "1") (UNSPEC_SM3PARTW2 "2")])
1937
1938(define_int_attr f16mac1 [(UNSPEC_FMLAL "a") (UNSPEC_FMLSL "s")
1939 (UNSPEC_FMLAL2 "a") (UNSPEC_FMLSL2 "s")])
43cacb12
RS		 1940
1941;; The condition associated with an UNSPEC_COND_<xx>.
cb18e86d
RS		 1942(define_int_attr cmp_op [(UNSPEC_COND_FCMEQ "eq")
1943 (UNSPEC_COND_FCMGE "ge")
1944 (UNSPEC_COND_FCMGT "gt")
1945 (UNSPEC_COND_FCMLE "le")
1946 (UNSPEC_COND_FCMLT "lt")
1947 (UNSPEC_COND_FCMNE "ne")])
1948
b0760a40
RS		 1949(define_int_attr sve_int_op [(UNSPEC_ANDV "andv")
1950 (UNSPEC_IORV "orv")
1951 (UNSPEC_XORV "eorv")
1952 (UNSPEC_UMAXV "umaxv")
1953 (UNSPEC_UMINV "uminv")
1954 (UNSPEC_SMAXV "smaxv")
1955 (UNSPEC_SMINV "sminv")])
1956
1957(define_int_attr sve_fp_op [(UNSPEC_FADDV "faddv")
1958 (UNSPEC_FMAXNMV "fmaxnmv")
1959 (UNSPEC_FMAXV "fmaxv")
1960 (UNSPEC_FMINNMV "fminnmv")
1961 (UNSPEC_FMINV "fminv")
1962 (UNSPEC_COND_FABS "fabs")
d45b20a5 1963 (UNSPEC_COND_FADD "fadd")
cb18e86d
RS		 1964 (UNSPEC_COND_FDIV "fdiv")
1965 (UNSPEC_COND_FMAXNM "fmaxnm")
1966 (UNSPEC_COND_FMINNM "fminnm")
1967 (UNSPEC_COND_FMUL "fmul")
d45b20a5
RS		 1968 (UNSPEC_COND_FNEG "fneg")
1969 (UNSPEC_COND_FRINTA "frinta")
1970 (UNSPEC_COND_FRINTI "frinti")
1971 (UNSPEC_COND_FRINTM "frintm")
1972 (UNSPEC_COND_FRINTN "frintn")
1973 (UNSPEC_COND_FRINTP "frintp")
1974 (UNSPEC_COND_FRINTX "frintx")
1975 (UNSPEC_COND_FRINTZ "frintz")
1976 (UNSPEC_COND_FSQRT "fsqrt")
cb18e86d
RS		 1977 (UNSPEC_COND_FSUB "fsub")])
1978
1979(define_int_attr sve_fp_op_rev [(UNSPEC_COND_FADD "fadd")
1980 (UNSPEC_COND_FDIV "fdivr")
1981 (UNSPEC_COND_FMAXNM "fmaxnm")
1982 (UNSPEC_COND_FMINNM "fminnm")
1983 (UNSPEC_COND_FMUL "fmul")
1984 (UNSPEC_COND_FSUB "fsubr")])
a08acce8 1985
9d63f43b
TC		 1986(define_int_attr rot [(UNSPEC_FCADD90 "90")
1987 (UNSPEC_FCADD270 "270")
1988 (UNSPEC_FCMLA "0")
1989 (UNSPEC_FCMLA90 "90")
1990 (UNSPEC_FCMLA180 "180")
1991 (UNSPEC_FCMLA270 "270")])
1992
b41d1f6e
RS		 1993(define_int_attr sve_fmla_op [(UNSPEC_COND_FMLA "fmla")
1994 (UNSPEC_COND_FMLS "fmls")
1995 (UNSPEC_COND_FNMLA "fnmla")
1996 (UNSPEC_COND_FNMLS "fnmls")])
1997
1998(define_int_attr sve_fmad_op [(UNSPEC_COND_FMLA "fmad")
1999 (UNSPEC_COND_FMLS "fmsb")
2000 (UNSPEC_COND_FNMLA "fnmad")
2001 (UNSPEC_COND_FNMLS "fnmsb")])
Mirror of https://gcc.gnu.org/git/gcc.git