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43e9d192 | 1 | ;; Machine description for AArch64 architecture. |
818ab71a | 2 | ;; Copyright (C) 2009-2016 Free Software Foundation, Inc. |
43e9d192 IB |
3 | ;; Contributed by ARM Ltd. |
4 | ;; | |
5 | ;; This file is part of GCC. | |
6 | ;; | |
7 | ;; GCC is free software; you can redistribute it and/or modify it | |
8 | ;; under the terms of the GNU General Public License as published by | |
9 | ;; the Free Software Foundation; either version 3, or (at your option) | |
10 | ;; any later version. | |
11 | ;; | |
12 | ;; GCC is distributed in the hope that it will be useful, but | |
13 | ;; WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | ;; General Public License for more details. | |
16 | ;; | |
17 | ;; You should have received a copy of the GNU General Public License | |
18 | ;; along with GCC; see the file COPYING3. If not see | |
19 | ;; <http://www.gnu.org/licenses/>. | |
20 | ||
21 | ;; ------------------------------------------------------------------- | |
22 | ;; Mode Iterators | |
23 | ;; ------------------------------------------------------------------- | |
24 | ||
25 | ||
26 | ;; Iterator for General Purpose Integer registers (32- and 64-bit modes) | |
27 | (define_mode_iterator GPI [SI DI]) | |
28 | ||
d7f33f07 JW |
29 | ;; Iterator for HI, SI, DI, some instructions can only work on these modes. |
30 | (define_mode_iterator GPI_I16 [(HI "AARCH64_ISA_F16") SI DI]) | |
31 | ||
43e9d192 IB |
32 | ;; Iterator for QI and HI modes |
33 | (define_mode_iterator SHORT [QI HI]) | |
34 | ||
35 | ;; Iterator for all integer modes (up to 64-bit) | |
36 | (define_mode_iterator ALLI [QI HI SI DI]) | |
37 | ||
43e9d192 IB |
38 | ;; Iterator for all integer modes that can be extended (up to 64-bit) |
39 | (define_mode_iterator ALLX [QI HI SI]) | |
40 | ||
41 | ;; Iterator for General Purpose Floating-point registers (32- and 64-bit modes) | |
42 | (define_mode_iterator GPF [SF DF]) | |
43 | ||
d7f33f07 JW |
44 | ;; Iterator for all scalar floating point modes (HF, SF, DF) |
45 | (define_mode_iterator GPF_F16 [(HF "AARCH64_ISA_F16") SF DF]) | |
46 | ||
09fcd8e1 RR |
47 | ;; Iterator for all scalar floating point modes (HF, SF, DF and TF) |
48 | (define_mode_iterator GPF_TF_F16 [HF SF DF TF]) | |
c2ec330c | 49 | |
922f9c25 AL |
50 | ;; Double vector modes. |
51 | (define_mode_iterator VDF [V2SF V4HF]) | |
52 | ||
b4f50fd4 RR |
53 | ;; Iterator for all scalar floating point modes (SF, DF and TF) |
54 | (define_mode_iterator GPF_TF [SF DF TF]) | |
55 | ||
43e9d192 IB |
56 | ;; Integer vector modes. |
57 | (define_mode_iterator VDQ_I [V8QI V16QI V4HI V8HI V2SI V4SI V2DI]) | |
58 | ||
59 | ;; vector and scalar, 64 & 128-bit container, all integer modes | |
60 | (define_mode_iterator VSDQ_I [V8QI V16QI V4HI V8HI V2SI V4SI V2DI QI HI SI DI]) | |
61 | ||
62 | ;; vector and scalar, 64 & 128-bit container: all vector integer modes; | |
63 | ;; 64-bit scalar integer mode | |
64 | (define_mode_iterator VSDQ_I_DI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI DI]) | |
65 | ||
66 | ;; Double vector modes. | |
71a11456 | 67 | (define_mode_iterator VD [V8QI V4HI V4HF V2SI V2SF]) |
43e9d192 IB |
68 | |
69 | ;; vector, 64-bit container, all integer modes | |
70 | (define_mode_iterator VD_BHSI [V8QI V4HI V2SI]) | |
71 | ||
72 | ;; 128 and 64-bit container; 8, 16, 32-bit vector integer modes | |
73 | (define_mode_iterator VDQ_BHSI [V8QI V16QI V4HI V8HI V2SI V4SI]) | |
74 | ||
75 | ;; Quad vector modes. | |
71a11456 | 76 | (define_mode_iterator VQ [V16QI V8HI V4SI V2DI V8HF V4SF V2DF]) |
43e9d192 | 77 | |
51437269 | 78 | ;; VQ without 2 element modes. |
71a11456 | 79 | (define_mode_iterator VQ_NO2E [V16QI V8HI V4SI V8HF V4SF]) |
51437269 GW |
80 | |
81 | ;; Quad vector with only 2 element modes. | |
82 | (define_mode_iterator VQ_2E [V2DI V2DF]) | |
83 | ||
28514dda YZ |
84 | ;; This mode iterator allows :P to be used for patterns that operate on |
85 | ;; addresses in different modes. In LP64, only DI will match, while in | |
86 | ;; ILP32, either can match. | |
87 | (define_mode_iterator P [(SI "ptr_mode == SImode || Pmode == SImode") | |
88 | (DI "ptr_mode == DImode || Pmode == DImode")]) | |
89 | ||
43e9d192 IB |
90 | ;; This mode iterator allows :PTR to be used for patterns that operate on |
91 | ;; pointer-sized quantities. Exactly one of the two alternatives will match. | |
28514dda | 92 | (define_mode_iterator PTR [(SI "ptr_mode == SImode") (DI "ptr_mode == DImode")]) |
43e9d192 | 93 | |
862abc04 AL |
94 | ;; Vector Float modes suitable for moving, loading and storing. |
95 | (define_mode_iterator VDQF_F16 [V4HF V8HF V2SF V4SF V2DF]) | |
96 | ||
daef0a8c | 97 | ;; Vector Float modes. |
43e9d192 | 98 | (define_mode_iterator VDQF [V2SF V4SF V2DF]) |
daef0a8c JW |
99 | (define_mode_iterator VHSDF [(V4HF "TARGET_SIMD_F16INST") |
100 | (V8HF "TARGET_SIMD_F16INST") | |
101 | V2SF V4SF V2DF]) | |
43e9d192 | 102 | |
f421c516 JG |
103 | ;; Vector Float modes, and DF. |
104 | (define_mode_iterator VDQF_DF [V2SF V4SF V2DF DF]) | |
daef0a8c JW |
105 | (define_mode_iterator VHSDF_DF [(V4HF "TARGET_SIMD_F16INST") |
106 | (V8HF "TARGET_SIMD_F16INST") | |
107 | V2SF V4SF V2DF DF]) | |
108 | (define_mode_iterator VHSDF_SDF [(V4HF "TARGET_SIMD_F16INST") | |
109 | (V8HF "TARGET_SIMD_F16INST") | |
110 | V2SF V4SF V2DF SF DF]) | |
d7f33f07 JW |
111 | (define_mode_iterator VHSDF_HSDF [(V4HF "TARGET_SIMD_F16INST") |
112 | (V8HF "TARGET_SIMD_F16INST") | |
113 | V2SF V4SF V2DF | |
114 | (HF "TARGET_SIMD_F16INST") | |
115 | SF DF]) | |
f421c516 | 116 | |
828e70c1 JG |
117 | ;; Vector single Float modes. |
118 | (define_mode_iterator VDQSF [V2SF V4SF]) | |
119 | ||
03873eb9 AL |
120 | ;; Quad vector Float modes with half/single elements. |
121 | (define_mode_iterator VQ_HSF [V8HF V4SF]) | |
122 | ||
fc21784d JG |
123 | ;; Modes suitable to use as the return type of a vcond expression. |
124 | (define_mode_iterator VDQF_COND [V2SF V2SI V4SF V4SI V2DF V2DI]) | |
125 | ||
889b9412 JG |
126 | ;; All Float modes. |
127 | (define_mode_iterator VALLF [V2SF V4SF V2DF SF DF]) | |
128 | ||
43e9d192 IB |
129 | ;; Vector Float modes with 2 elements. |
130 | (define_mode_iterator V2F [V2SF V2DF]) | |
131 | ||
71a11456 | 132 | ;; All vector modes on which we support any arithmetic operations. |
43e9d192 IB |
133 | (define_mode_iterator VALL [V8QI V16QI V4HI V8HI V2SI V4SI V2DI V2SF V4SF V2DF]) |
134 | ||
71a11456 AL |
135 | ;; All vector modes suitable for moving, loading, and storing. |
136 | (define_mode_iterator VALL_F16 [V8QI V16QI V4HI V8HI V2SI V4SI V2DI | |
137 | V4HF V8HF V2SF V4SF V2DF]) | |
138 | ||
139 | ;; All vector modes barring HF modes, plus DI. | |
a50344cb TB |
140 | (define_mode_iterator VALLDI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI V2SF V4SF V2DF DI]) |
141 | ||
71a11456 AL |
142 | ;; All vector modes and DI. |
143 | (define_mode_iterator VALLDI_F16 [V8QI V16QI V4HI V8HI V2SI V4SI V2DI | |
144 | V4HF V8HF V2SF V4SF V2DF DI]) | |
145 | ||
7c369485 | 146 | ;; All vector modes, plus DI and DF. |
46e778c4 | 147 | (define_mode_iterator VALLDIF [V8QI V16QI V4HI V8HI V2SI V4SI |
7c369485 | 148 | V2DI V4HF V8HF V2SF V4SF V2DF DI DF]) |
46e778c4 | 149 | |
43e9d192 | 150 | ;; Vector modes for Integer reduction across lanes. |
92835317 TB |
151 | (define_mode_iterator VDQV [V8QI V16QI V4HI V8HI V4SI V2DI]) |
152 | ||
153 | ;; Vector modes(except V2DI) for Integer reduction across lanes. | |
154 | (define_mode_iterator VDQV_S [V8QI V16QI V4HI V8HI V4SI]) | |
43e9d192 IB |
155 | |
156 | ;; All double integer narrow-able modes. | |
157 | (define_mode_iterator VDN [V4HI V2SI DI]) | |
158 | ||
159 | ;; All quad integer narrow-able modes. | |
160 | (define_mode_iterator VQN [V8HI V4SI V2DI]) | |
161 | ||
43e9d192 IB |
162 | ;; Vector and scalar 128-bit container: narrowable 16, 32, 64-bit integer modes |
163 | (define_mode_iterator VSQN_HSDI [V8HI V4SI V2DI HI SI DI]) | |
164 | ||
165 | ;; All quad integer widen-able modes. | |
166 | (define_mode_iterator VQW [V16QI V8HI V4SI]) | |
167 | ||
168 | ;; Double vector modes for combines. | |
7c369485 | 169 | (define_mode_iterator VDC [V8QI V4HI V4HF V2SI V2SF DI DF]) |
43e9d192 | 170 | |
43e9d192 IB |
171 | ;; Vector modes except double int. |
172 | (define_mode_iterator VDQIF [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF V2DF]) | |
703bbcdf JW |
173 | (define_mode_iterator VDQIF_F16 [V8QI V16QI V4HI V8HI V2SI V4SI |
174 | V4HF V8HF V2SF V4SF V2DF]) | |
43e9d192 | 175 | |
58a3bd25 FY |
176 | ;; Vector modes for S type. |
177 | (define_mode_iterator VDQ_SI [V2SI V4SI]) | |
178 | ||
2644d4d9 JW |
179 | ;; Vector modes for S and D |
180 | (define_mode_iterator VDQ_SDI [V2SI V4SI V2DI]) | |
181 | ||
33d72b63 JW |
182 | ;; Vector modes for H, S and D |
183 | (define_mode_iterator VDQ_HSDI [(V4HI "TARGET_SIMD_F16INST") | |
184 | (V8HI "TARGET_SIMD_F16INST") | |
185 | V2SI V4SI V2DI]) | |
186 | ||
2644d4d9 JW |
187 | ;; Scalar and Vector modes for S and D |
188 | (define_mode_iterator VSDQ_SDI [V2SI V4SI V2DI SI DI]) | |
189 | ||
33d72b63 JW |
190 | ;; Scalar and Vector modes for S and D, Vector modes for H. |
191 | (define_mode_iterator VSDQ_HSDI [(V4HI "TARGET_SIMD_F16INST") | |
192 | (V8HI "TARGET_SIMD_F16INST") | |
193 | V2SI V4SI V2DI SI DI]) | |
194 | ||
66adb8eb JG |
195 | ;; Vector modes for Q and H types. |
196 | (define_mode_iterator VDQQH [V8QI V16QI V4HI V8HI]) | |
197 | ||
43e9d192 IB |
198 | ;; Vector modes for H and S types. |
199 | (define_mode_iterator VDQHS [V4HI V8HI V2SI V4SI]) | |
200 | ||
c7f28cd5 KT |
201 | ;; Vector modes for H, S and D types. |
202 | (define_mode_iterator VDQHSD [V4HI V8HI V2SI V4SI V2DI]) | |
203 | ||
43e9d192 IB |
204 | ;; Vector and scalar integer modes for H and S |
205 | (define_mode_iterator VSDQ_HSI [V4HI V8HI V2SI V4SI HI SI]) | |
206 | ||
207 | ;; Vector and scalar 64-bit container: 16, 32-bit integer modes | |
208 | (define_mode_iterator VSD_HSI [V4HI V2SI HI SI]) | |
209 | ||
210 | ;; Vector 64-bit container: 16, 32-bit integer modes | |
211 | (define_mode_iterator VD_HSI [V4HI V2SI]) | |
212 | ||
213 | ;; Scalar 64-bit container: 16, 32-bit integer modes | |
214 | (define_mode_iterator SD_HSI [HI SI]) | |
215 | ||
216 | ;; Vector 64-bit container: 16, 32-bit integer modes | |
217 | (define_mode_iterator VQ_HSI [V8HI V4SI]) | |
218 | ||
219 | ;; All byte modes. | |
220 | (define_mode_iterator VB [V8QI V16QI]) | |
221 | ||
5e32e83b JW |
222 | ;; 2 and 4 lane SI modes. |
223 | (define_mode_iterator VS [V2SI V4SI]) | |
224 | ||
43e9d192 IB |
225 | (define_mode_iterator TX [TI TF]) |
226 | ||
227 | ;; Opaque structure modes. | |
228 | (define_mode_iterator VSTRUCT [OI CI XI]) | |
229 | ||
230 | ;; Double scalar modes | |
231 | (define_mode_iterator DX [DI DF]) | |
232 | ||
779aea46 | 233 | ;; Modes available for <f>mul lane operations. |
ab2e8f01 JW |
234 | (define_mode_iterator VMUL [V4HI V8HI V2SI V4SI |
235 | (V4HF "TARGET_SIMD_F16INST") | |
236 | (V8HF "TARGET_SIMD_F16INST") | |
237 | V2SF V4SF V2DF]) | |
779aea46 JG |
238 | |
239 | ;; Modes available for <f>mul lane operations changing lane count. | |
240 | (define_mode_iterator VMUL_CHANGE_NLANES [V4HI V8HI V2SI V4SI V2SF V4SF]) | |
241 | ||
43e9d192 IB |
242 | ;; ------------------------------------------------------------------ |
243 | ;; Unspec enumerations for Advance SIMD. These could well go into | |
244 | ;; aarch64.md but for their use in int_iterators here. | |
245 | ;; ------------------------------------------------------------------ | |
246 | ||
247 | (define_c_enum "unspec" | |
248 | [ | |
249 | UNSPEC_ASHIFT_SIGNED ; Used in aarch-simd.md. | |
250 | UNSPEC_ASHIFT_UNSIGNED ; Used in aarch64-simd.md. | |
285398d2 | 251 | UNSPEC_ABS ; Used in aarch64-simd.md. |
998eaf97 JG |
252 | UNSPEC_FMAX ; Used in aarch64-simd.md. |
253 | UNSPEC_FMAXNMV ; Used in aarch64-simd.md. | |
43e9d192 | 254 | UNSPEC_FMAXV ; Used in aarch64-simd.md. |
998eaf97 JG |
255 | UNSPEC_FMIN ; Used in aarch64-simd.md. |
256 | UNSPEC_FMINNMV ; Used in aarch64-simd.md. | |
43e9d192 IB |
257 | UNSPEC_FMINV ; Used in aarch64-simd.md. |
258 | UNSPEC_FADDV ; Used in aarch64-simd.md. | |
f5156c3e | 259 | UNSPEC_ADDV ; Used in aarch64-simd.md. |
43e9d192 IB |
260 | UNSPEC_SMAXV ; Used in aarch64-simd.md. |
261 | UNSPEC_SMINV ; Used in aarch64-simd.md. | |
262 | UNSPEC_UMAXV ; Used in aarch64-simd.md. | |
263 | UNSPEC_UMINV ; Used in aarch64-simd.md. | |
264 | UNSPEC_SHADD ; Used in aarch64-simd.md. | |
265 | UNSPEC_UHADD ; Used in aarch64-simd.md. | |
266 | UNSPEC_SRHADD ; Used in aarch64-simd.md. | |
267 | UNSPEC_URHADD ; Used in aarch64-simd.md. | |
268 | UNSPEC_SHSUB ; Used in aarch64-simd.md. | |
269 | UNSPEC_UHSUB ; Used in aarch64-simd.md. | |
270 | UNSPEC_SRHSUB ; Used in aarch64-simd.md. | |
271 | UNSPEC_URHSUB ; Used in aarch64-simd.md. | |
272 | UNSPEC_ADDHN ; Used in aarch64-simd.md. | |
273 | UNSPEC_RADDHN ; Used in aarch64-simd.md. | |
274 | UNSPEC_SUBHN ; Used in aarch64-simd.md. | |
275 | UNSPEC_RSUBHN ; Used in aarch64-simd.md. | |
276 | UNSPEC_ADDHN2 ; Used in aarch64-simd.md. | |
277 | UNSPEC_RADDHN2 ; Used in aarch64-simd.md. | |
278 | UNSPEC_SUBHN2 ; Used in aarch64-simd.md. | |
279 | UNSPEC_RSUBHN2 ; Used in aarch64-simd.md. | |
280 | UNSPEC_SQDMULH ; Used in aarch64-simd.md. | |
281 | UNSPEC_SQRDMULH ; Used in aarch64-simd.md. | |
282 | UNSPEC_PMUL ; Used in aarch64-simd.md. | |
496ea87d | 283 | UNSPEC_FMULX ; Used in aarch64-simd.md. |
43e9d192 IB |
284 | UNSPEC_USQADD ; Used in aarch64-simd.md. |
285 | UNSPEC_SUQADD ; Used in aarch64-simd.md. | |
286 | UNSPEC_SQXTUN ; Used in aarch64-simd.md. | |
287 | UNSPEC_SQXTN ; Used in aarch64-simd.md. | |
288 | UNSPEC_UQXTN ; Used in aarch64-simd.md. | |
289 | UNSPEC_SSRA ; Used in aarch64-simd.md. | |
290 | UNSPEC_USRA ; Used in aarch64-simd.md. | |
291 | UNSPEC_SRSRA ; Used in aarch64-simd.md. | |
292 | UNSPEC_URSRA ; Used in aarch64-simd.md. | |
293 | UNSPEC_SRSHR ; Used in aarch64-simd.md. | |
294 | UNSPEC_URSHR ; Used in aarch64-simd.md. | |
295 | UNSPEC_SQSHLU ; Used in aarch64-simd.md. | |
296 | UNSPEC_SQSHL ; Used in aarch64-simd.md. | |
297 | UNSPEC_UQSHL ; Used in aarch64-simd.md. | |
298 | UNSPEC_SQSHRUN ; Used in aarch64-simd.md. | |
299 | UNSPEC_SQRSHRUN ; Used in aarch64-simd.md. | |
300 | UNSPEC_SQSHRN ; Used in aarch64-simd.md. | |
301 | UNSPEC_UQSHRN ; Used in aarch64-simd.md. | |
302 | UNSPEC_SQRSHRN ; Used in aarch64-simd.md. | |
303 | UNSPEC_UQRSHRN ; Used in aarch64-simd.md. | |
304 | UNSPEC_SSHL ; Used in aarch64-simd.md. | |
305 | UNSPEC_USHL ; Used in aarch64-simd.md. | |
306 | UNSPEC_SRSHL ; Used in aarch64-simd.md. | |
307 | UNSPEC_URSHL ; Used in aarch64-simd.md. | |
308 | UNSPEC_SQRSHL ; Used in aarch64-simd.md. | |
309 | UNSPEC_UQRSHL ; Used in aarch64-simd.md. | |
43e9d192 IB |
310 | UNSPEC_SSLI ; Used in aarch64-simd.md. |
311 | UNSPEC_USLI ; Used in aarch64-simd.md. | |
312 | UNSPEC_SSRI ; Used in aarch64-simd.md. | |
313 | UNSPEC_USRI ; Used in aarch64-simd.md. | |
314 | UNSPEC_SSHLL ; Used in aarch64-simd.md. | |
315 | UNSPEC_USHLL ; Used in aarch64-simd.md. | |
316 | UNSPEC_ADDP ; Used in aarch64-simd.md. | |
88b08073 | 317 | UNSPEC_TBL ; Used in vector permute patterns. |
9371aecc | 318 | UNSPEC_TBX ; Used in vector permute patterns. |
88b08073 | 319 | UNSPEC_CONCAT ; Used in vector permute patterns. |
cc4d934f JG |
320 | UNSPEC_ZIP1 ; Used in vector permute patterns. |
321 | UNSPEC_ZIP2 ; Used in vector permute patterns. | |
322 | UNSPEC_UZP1 ; Used in vector permute patterns. | |
323 | UNSPEC_UZP2 ; Used in vector permute patterns. | |
324 | UNSPEC_TRN1 ; Used in vector permute patterns. | |
325 | UNSPEC_TRN2 ; Used in vector permute patterns. | |
ae0533da | 326 | UNSPEC_EXT ; Used in aarch64-simd.md. |
923fcec3 AL |
327 | UNSPEC_REV64 ; Used in vector reverse patterns (permute). |
328 | UNSPEC_REV32 ; Used in vector reverse patterns (permute). | |
329 | UNSPEC_REV16 ; Used in vector reverse patterns (permute). | |
5a7a4e80 TB |
330 | UNSPEC_AESE ; Used in aarch64-simd.md. |
331 | UNSPEC_AESD ; Used in aarch64-simd.md. | |
332 | UNSPEC_AESMC ; Used in aarch64-simd.md. | |
333 | UNSPEC_AESIMC ; Used in aarch64-simd.md. | |
30442682 TB |
334 | UNSPEC_SHA1C ; Used in aarch64-simd.md. |
335 | UNSPEC_SHA1M ; Used in aarch64-simd.md. | |
336 | UNSPEC_SHA1P ; Used in aarch64-simd.md. | |
337 | UNSPEC_SHA1H ; Used in aarch64-simd.md. | |
338 | UNSPEC_SHA1SU0 ; Used in aarch64-simd.md. | |
339 | UNSPEC_SHA1SU1 ; Used in aarch64-simd.md. | |
b9cb0a44 TB |
340 | UNSPEC_SHA256H ; Used in aarch64-simd.md. |
341 | UNSPEC_SHA256H2 ; Used in aarch64-simd.md. | |
342 | UNSPEC_SHA256SU0 ; Used in aarch64-simd.md. | |
343 | UNSPEC_SHA256SU1 ; Used in aarch64-simd.md. | |
7baa225d TB |
344 | UNSPEC_PMULL ; Used in aarch64-simd.md. |
345 | UNSPEC_PMULL2 ; Used in aarch64-simd.md. | |
668046d1 | 346 | UNSPEC_REV_REGLIST ; Used in aarch64-simd.md. |
9c004c58 | 347 | UNSPEC_VEC_SHR ; Used in aarch64-simd.md. |
57b26d65 MW |
348 | UNSPEC_SQRDMLAH ; Used in aarch64-simd.md. |
349 | UNSPEC_SQRDMLSH ; Used in aarch64-simd.md. | |
202d0c11 DS |
350 | UNSPEC_FMAXNM ; Used in aarch64-simd.md. |
351 | UNSPEC_FMINNM ; Used in aarch64-simd.md. | |
43e9d192 IB |
352 | ]) |
353 | ||
d81cb613 MW |
354 | ;; ------------------------------------------------------------------ |
355 | ;; Unspec enumerations for Atomics. They are here so that they can be | |
356 | ;; used in the int_iterators for atomic operations. | |
357 | ;; ------------------------------------------------------------------ | |
358 | ||
359 | (define_c_enum "unspecv" | |
360 | [ | |
361 | UNSPECV_LX ; Represent a load-exclusive. | |
362 | UNSPECV_SX ; Represent a store-exclusive. | |
363 | UNSPECV_LDA ; Represent an atomic load or load-acquire. | |
364 | UNSPECV_STL ; Represent an atomic store or store-release. | |
365 | UNSPECV_ATOMIC_CMPSW ; Represent an atomic compare swap. | |
366 | UNSPECV_ATOMIC_EXCHG ; Represent an atomic exchange. | |
367 | UNSPECV_ATOMIC_CAS ; Represent an atomic CAS. | |
368 | UNSPECV_ATOMIC_SWP ; Represent an atomic SWP. | |
369 | UNSPECV_ATOMIC_OP ; Represent an atomic operation. | |
370 | UNSPECV_ATOMIC_LDOP ; Represent an atomic load-operation | |
371 | UNSPECV_ATOMIC_LDOP_OR ; Represent an atomic load-or | |
372 | UNSPECV_ATOMIC_LDOP_BIC ; Represent an atomic load-bic | |
373 | UNSPECV_ATOMIC_LDOP_XOR ; Represent an atomic load-xor | |
374 | UNSPECV_ATOMIC_LDOP_PLUS ; Represent an atomic load-add | |
375 | ]) | |
376 | ||
43e9d192 IB |
377 | ;; ------------------------------------------------------------------- |
378 | ;; Mode attributes | |
379 | ;; ------------------------------------------------------------------- | |
380 | ||
381 | ;; In GPI templates, a string like "%<w>0" will expand to "%w0" in the | |
382 | ;; 32-bit version and "%x0" in the 64-bit version. | |
383 | (define_mode_attr w [(QI "w") (HI "w") (SI "w") (DI "x") (SF "s") (DF "d")]) | |
384 | ||
0d35c5c2 | 385 | ;; For inequal width int to float conversion |
d7f33f07 JW |
386 | (define_mode_attr w1 [(HF "w") (SF "w") (DF "x")]) |
387 | (define_mode_attr w2 [(HF "x") (SF "x") (DF "w")]) | |
0d35c5c2 | 388 | |
2b8568fe KT |
389 | (define_mode_attr short_mask [(HI "65535") (QI "255")]) |
390 | ||
051d0e2f SN |
391 | ;; For constraints used in scalar immediate vector moves |
392 | (define_mode_attr hq [(HI "h") (QI "q")]) | |
393 | ||
ef22810a RH |
394 | ;; For doubling width of an integer mode |
395 | (define_mode_attr DWI [(QI "HI") (HI "SI") (SI "DI") (DI "TI")]) | |
396 | ||
43e9d192 IB |
397 | ;; For scalar usage of vector/FP registers |
398 | (define_mode_attr v [(QI "b") (HI "h") (SI "s") (DI "d") | |
d7f33f07 | 399 | (HF "h") (SF "s") (DF "d") |
43e9d192 IB |
400 | (V8QI "") (V16QI "") |
401 | (V4HI "") (V8HI "") | |
402 | (V2SI "") (V4SI "") | |
403 | (V2DI "") (V2SF "") | |
daef0a8c JW |
404 | (V4SF "") (V4HF "") |
405 | (V8HF "") (V2DF "")]) | |
43e9d192 IB |
406 | |
407 | ;; For scalar usage of vector/FP registers, narrowing | |
408 | (define_mode_attr vn2 [(QI "") (HI "b") (SI "h") (DI "s") | |
409 | (V8QI "") (V16QI "") | |
410 | (V4HI "") (V8HI "") | |
411 | (V2SI "") (V4SI "") | |
412 | (V2DI "") (V2SF "") | |
413 | (V4SF "") (V2DF "")]) | |
414 | ||
415 | ;; For scalar usage of vector/FP registers, widening | |
416 | (define_mode_attr vw2 [(DI "") (QI "h") (HI "s") (SI "d") | |
417 | (V8QI "") (V16QI "") | |
418 | (V4HI "") (V8HI "") | |
419 | (V2SI "") (V4SI "") | |
420 | (V2DI "") (V2SF "") | |
421 | (V4SF "") (V2DF "")]) | |
422 | ||
89fdc743 IB |
423 | ;; Register Type Name and Vector Arrangement Specifier for when |
424 | ;; we are doing scalar for DI and SIMD for SI (ignoring all but | |
425 | ;; lane 0). | |
426 | (define_mode_attr rtn [(DI "d") (SI "")]) | |
427 | (define_mode_attr vas [(DI "") (SI ".2s")]) | |
428 | ||
43e9d192 | 429 | ;; Map a floating point mode to the appropriate register name prefix |
d7f33f07 | 430 | (define_mode_attr s [(HF "h") (SF "s") (DF "d")]) |
43e9d192 IB |
431 | |
432 | ;; Give the length suffix letter for a sign- or zero-extension. | |
433 | (define_mode_attr size [(QI "b") (HI "h") (SI "w")]) | |
434 | ||
435 | ;; Give the number of bits in the mode | |
436 | (define_mode_attr sizen [(QI "8") (HI "16") (SI "32") (DI "64")]) | |
437 | ||
438 | ;; Give the ordinal of the MSB in the mode | |
439 | (define_mode_attr sizem1 [(QI "#7") (HI "#15") (SI "#31") (DI "#63")]) | |
440 | ||
441 | ;; Attribute to describe constants acceptable in logical operations | |
442 | (define_mode_attr lconst [(SI "K") (DI "L")]) | |
443 | ||
444 | ;; Map a mode to a specific constraint character. | |
445 | (define_mode_attr cmode [(QI "q") (HI "h") (SI "s") (DI "d")]) | |
446 | ||
447 | (define_mode_attr Vtype [(V8QI "8b") (V16QI "16b") | |
448 | (V4HI "4h") (V8HI "8h") | |
449 | (V2SI "2s") (V4SI "4s") | |
450 | (DI "1d") (DF "1d") | |
451 | (V2DI "2d") (V2SF "2s") | |
7c369485 AL |
452 | (V4SF "4s") (V2DF "2d") |
453 | (V4HF "4h") (V8HF "8h")]) | |
43e9d192 | 454 | |
c7f28cd5 KT |
455 | (define_mode_attr Vrevsuff [(V4HI "16") (V8HI "16") (V2SI "32") |
456 | (V4SI "32") (V2DI "64")]) | |
457 | ||
43e9d192 IB |
458 | (define_mode_attr Vmtype [(V8QI ".8b") (V16QI ".16b") |
459 | (V4HI ".4h") (V8HI ".8h") | |
460 | (V2SI ".2s") (V4SI ".4s") | |
71a11456 AL |
461 | (V2DI ".2d") (V4HF ".4h") |
462 | (V8HF ".8h") (V2SF ".2s") | |
43e9d192 IB |
463 | (V4SF ".4s") (V2DF ".2d") |
464 | (DI "") (SI "") | |
465 | (HI "") (QI "") | |
d7f33f07 JW |
466 | (TI "") (HF "") |
467 | (SF "") (DF "")]) | |
43e9d192 IB |
468 | |
469 | ;; Register suffix narrowed modes for VQN. | |
470 | (define_mode_attr Vmntype [(V8HI ".8b") (V4SI ".4h") | |
471 | (V2DI ".2s") | |
472 | (DI "") (SI "") | |
473 | (HI "")]) | |
474 | ||
475 | ;; Mode-to-individual element type mapping. | |
476 | (define_mode_attr Vetype [(V8QI "b") (V16QI "b") | |
477 | (V4HI "h") (V8HI "h") | |
478 | (V2SI "s") (V4SI "s") | |
7c369485 AL |
479 | (V2DI "d") (V4HF "h") |
480 | (V8HF "h") (V2SF "s") | |
43e9d192 | 481 | (V4SF "s") (V2DF "d") |
d7f33f07 | 482 | (HF "h") |
0f686aa9 | 483 | (SF "s") (DF "d") |
43e9d192 IB |
484 | (QI "b") (HI "h") |
485 | (SI "s") (DI "d")]) | |
486 | ||
daef0a8c JW |
487 | ;; Vetype is used everywhere in scheduling type and assembly output, |
488 | ;; sometimes they are not the same, for example HF modes on some | |
489 | ;; instructions. stype is defined to represent scheduling type | |
490 | ;; more accurately. | |
491 | (define_mode_attr stype [(V8QI "b") (V16QI "b") (V4HI "s") (V8HI "s") | |
492 | (V2SI "s") (V4SI "s") (V2DI "d") (V4HF "s") | |
493 | (V8HF "s") (V2SF "s") (V4SF "s") (V2DF "d") | |
494 | (HF "s") (SF "s") (DF "d") (QI "b") (HI "s") | |
495 | (SI "s") (DI "d")]) | |
496 | ||
43e9d192 IB |
497 | ;; Mode-to-bitwise operation type mapping. |
498 | (define_mode_attr Vbtype [(V8QI "8b") (V16QI "16b") | |
499 | (V4HI "8b") (V8HI "16b") | |
500 | (V2SI "8b") (V4SI "16b") | |
7c369485 AL |
501 | (V2DI "16b") (V4HF "8b") |
502 | (V8HF "16b") (V2SF "8b") | |
46e778c4 | 503 | (V4SF "16b") (V2DF "16b") |
fe82d1f2 AL |
504 | (DI "8b") (DF "8b") |
505 | (SI "8b")]) | |
43e9d192 IB |
506 | |
507 | ;; Define element mode for each vector mode. | |
508 | (define_mode_attr VEL [(V8QI "QI") (V16QI "QI") | |
509 | (V4HI "HI") (V8HI "HI") | |
510 | (V2SI "SI") (V4SI "SI") | |
511 | (DI "DI") (V2DI "DI") | |
71a11456 | 512 | (V4HF "HF") (V8HF "HF") |
43e9d192 | 513 | (V2SF "SF") (V4SF "SF") |
779aea46 | 514 | (V2DF "DF") (DF "DF") |
43e9d192 IB |
515 | (SI "SI") (HI "HI") |
516 | (QI "QI")]) | |
517 | ||
278821f2 KT |
518 | ;; 64-bit container modes the inner or scalar source mode. |
519 | (define_mode_attr VCOND [(HI "V4HI") (SI "V2SI") | |
520 | (V4HI "V4HI") (V8HI "V4HI") | |
b7d7d917 TB |
521 | (V2SI "V2SI") (V4SI "V2SI") |
522 | (DI "DI") (V2DI "DI") | |
523 | (V2SF "V2SF") (V4SF "V2SF") | |
524 | (V2DF "DF")]) | |
525 | ||
278821f2 | 526 | ;; 128-bit container modes the inner or scalar source mode. |
b7d7d917 TB |
527 | (define_mode_attr VCONQ [(V8QI "V16QI") (V16QI "V16QI") |
528 | (V4HI "V8HI") (V8HI "V8HI") | |
529 | (V2SI "V4SI") (V4SI "V4SI") | |
530 | (DI "V2DI") (V2DI "V2DI") | |
71a11456 | 531 | (V4HF "V8HF") (V8HF "V8HF") |
b7d7d917 TB |
532 | (V2SF "V2SF") (V4SF "V4SF") |
533 | (V2DF "V2DF") (SI "V4SI") | |
534 | (HI "V8HI") (QI "V16QI")]) | |
535 | ||
43e9d192 IB |
536 | ;; Half modes of all vector modes. |
537 | (define_mode_attr VHALF [(V8QI "V4QI") (V16QI "V8QI") | |
538 | (V4HI "V2HI") (V8HI "V4HI") | |
539 | (V2SI "SI") (V4SI "V2SI") | |
540 | (V2DI "DI") (V2SF "SF") | |
71a11456 AL |
541 | (V4SF "V2SF") (V4HF "V2HF") |
542 | (V8HF "V4HF") (V2DF "DF")]) | |
43e9d192 | 543 | |
b1b49824 MC |
544 | ;; Half modes of all vector modes, in lower-case. |
545 | (define_mode_attr Vhalf [(V8QI "v4qi") (V16QI "v8qi") | |
546 | (V4HI "v2hi") (V8HI "v4hi") | |
547 | (V2SI "si") (V4SI "v2si") | |
548 | (V2DI "di") (V2SF "sf") | |
549 | (V4SF "v2sf") (V2DF "df")]) | |
550 | ||
43e9d192 IB |
551 | ;; Double modes of vector modes. |
552 | (define_mode_attr VDBL [(V8QI "V16QI") (V4HI "V8HI") | |
71a11456 | 553 | (V4HF "V8HF") |
43e9d192 IB |
554 | (V2SI "V4SI") (V2SF "V4SF") |
555 | (SI "V2SI") (DI "V2DI") | |
556 | (DF "V2DF")]) | |
557 | ||
922f9c25 AL |
558 | ;; Register suffix for double-length mode. |
559 | (define_mode_attr Vdtype [(V4HF "8h") (V2SF "4s")]) | |
560 | ||
43e9d192 IB |
561 | ;; Double modes of vector modes (lower case). |
562 | (define_mode_attr Vdbl [(V8QI "v16qi") (V4HI "v8hi") | |
7c369485 | 563 | (V4HF "v8hf") |
43e9d192 | 564 | (V2SI "v4si") (V2SF "v4sf") |
8b033a8a SN |
565 | (SI "v2si") (DI "v2di") |
566 | (DF "v2df")]) | |
43e9d192 | 567 | |
b1b49824 MC |
568 | ;; Modes with double-width elements. |
569 | (define_mode_attr VDBLW [(V8QI "V4HI") (V16QI "V8HI") | |
570 | (V4HI "V2SI") (V8HI "V4SI") | |
571 | (V2SI "DI") (V4SI "V2DI")]) | |
572 | ||
43e9d192 IB |
573 | ;; Narrowed modes for VDN. |
574 | (define_mode_attr VNARROWD [(V4HI "V8QI") (V2SI "V4HI") | |
575 | (DI "V2SI")]) | |
576 | ||
577 | ;; Narrowed double-modes for VQN (Used for XTN). | |
578 | (define_mode_attr VNARROWQ [(V8HI "V8QI") (V4SI "V4HI") | |
579 | (V2DI "V2SI") | |
580 | (DI "SI") (SI "HI") | |
581 | (HI "QI")]) | |
582 | ||
583 | ;; Narrowed quad-modes for VQN (Used for XTN2). | |
584 | (define_mode_attr VNARROWQ2 [(V8HI "V16QI") (V4SI "V8HI") | |
585 | (V2DI "V4SI")]) | |
586 | ||
587 | ;; Register suffix narrowed modes for VQN. | |
588 | (define_mode_attr Vntype [(V8HI "8b") (V4SI "4h") | |
589 | (V2DI "2s")]) | |
590 | ||
591 | ;; Register suffix narrowed modes for VQN. | |
592 | (define_mode_attr V2ntype [(V8HI "16b") (V4SI "8h") | |
593 | (V2DI "4s")]) | |
594 | ||
595 | ;; Widened modes of vector modes. | |
596 | (define_mode_attr VWIDE [(V8QI "V8HI") (V4HI "V4SI") | |
597 | (V2SI "V2DI") (V16QI "V8HI") | |
598 | (V8HI "V4SI") (V4SI "V2DI") | |
922f9c25 | 599 | (HI "SI") (SI "DI") |
03873eb9 | 600 | (V8HF "V4SF") (V4SF "V2DF") |
922f9c25 | 601 | (V4HF "V4SF") (V2SF "V2DF")] |
43e9d192 IB |
602 | ) |
603 | ||
03873eb9 AL |
604 | ;; Widened modes of vector modes, lowercase |
605 | (define_mode_attr Vwide [(V2SF "v2df") (V4HF "v4sf")]) | |
606 | ||
607 | ;; Widened mode register suffixes for VD_BHSI/VQW/VQ_HSF. | |
43e9d192 IB |
608 | (define_mode_attr Vwtype [(V8QI "8h") (V4HI "4s") |
609 | (V2SI "2d") (V16QI "8h") | |
03873eb9 AL |
610 | (V8HI "4s") (V4SI "2d") |
611 | (V8HF "4s") (V4SF "2d")]) | |
43e9d192 IB |
612 | |
613 | ;; Widened mode register suffixes for VDW/VQW. | |
614 | (define_mode_attr Vmwtype [(V8QI ".8h") (V4HI ".4s") | |
615 | (V2SI ".2d") (V16QI ".8h") | |
616 | (V8HI ".4s") (V4SI ".2d") | |
922f9c25 | 617 | (V4HF ".4s") (V2SF ".2d") |
43e9d192 IB |
618 | (SI "") (HI "")]) |
619 | ||
03873eb9 | 620 | ;; Lower part register suffixes for VQW/VQ_HSF. |
43e9d192 | 621 | (define_mode_attr Vhalftype [(V16QI "8b") (V8HI "4h") |
03873eb9 AL |
622 | (V4SI "2s") (V8HF "4h") |
623 | (V4SF "2s")]) | |
43e9d192 IB |
624 | |
625 | ;; Define corresponding core/FP element mode for each vector mode. | |
626 | (define_mode_attr vw [(V8QI "w") (V16QI "w") | |
627 | (V4HI "w") (V8HI "w") | |
628 | (V2SI "w") (V4SI "w") | |
629 | (DI "x") (V2DI "x") | |
630 | (V2SF "s") (V4SF "s") | |
631 | (V2DF "d")]) | |
632 | ||
66adb8eb JG |
633 | ;; Corresponding core element mode for each vector mode. This is a |
634 | ;; variation on <vw> mapping FP modes to GP regs. | |
635 | (define_mode_attr vwcore [(V8QI "w") (V16QI "w") | |
636 | (V4HI "w") (V8HI "w") | |
637 | (V2SI "w") (V4SI "w") | |
638 | (DI "x") (V2DI "x") | |
64e9a944 | 639 | (V4HF "w") (V8HF "w") |
66adb8eb JG |
640 | (V2SF "w") (V4SF "w") |
641 | (V2DF "x")]) | |
642 | ||
43e9d192 IB |
643 | ;; Double vector types for ALLX. |
644 | (define_mode_attr Vallxd [(QI "8b") (HI "4h") (SI "2s")]) | |
645 | ||
646 | ;; Mode of result of comparison operations. | |
647 | (define_mode_attr V_cmp_result [(V8QI "V8QI") (V16QI "V16QI") | |
648 | (V4HI "V4HI") (V8HI "V8HI") | |
649 | (V2SI "V2SI") (V4SI "V4SI") | |
88b08073 | 650 | (DI "DI") (V2DI "V2DI") |
7c369485 | 651 | (V4HF "V4HI") (V8HF "V8HI") |
43e9d192 | 652 | (V2SF "V2SI") (V4SF "V4SI") |
889b9412 | 653 | (V2DF "V2DI") (DF "DI") |
d7f33f07 | 654 | (SF "SI") (HF "HI")]) |
43e9d192 | 655 | |
70c67693 JG |
656 | ;; Lower case mode of results of comparison operations. |
657 | (define_mode_attr v_cmp_result [(V8QI "v8qi") (V16QI "v16qi") | |
658 | (V4HI "v4hi") (V8HI "v8hi") | |
659 | (V2SI "v2si") (V4SI "v4si") | |
660 | (DI "di") (V2DI "v2di") | |
7c369485 | 661 | (V4HF "v4hi") (V8HF "v8hi") |
70c67693 | 662 | (V2SF "v2si") (V4SF "v4si") |
889b9412 JG |
663 | (V2DF "v2di") (DF "di") |
664 | (SF "si")]) | |
70c67693 | 665 | |
cb23a30c JG |
666 | ;; Lower case element modes (as used in shift immediate patterns). |
667 | (define_mode_attr ve_mode [(V8QI "qi") (V16QI "qi") | |
668 | (V4HI "hi") (V8HI "hi") | |
669 | (V2SI "si") (V4SI "si") | |
670 | (DI "di") (V2DI "di") | |
671 | (QI "qi") (HI "hi") | |
672 | (SI "si")]) | |
673 | ||
43e9d192 IB |
674 | ;; Vm for lane instructions is restricted to FP_LO_REGS. |
675 | (define_mode_attr vwx [(V4HI "x") (V8HI "x") (HI "x") | |
676 | (V2SI "w") (V4SI "w") (SI "w")]) | |
677 | ||
678 | (define_mode_attr Vendreg [(OI "T") (CI "U") (XI "V")]) | |
679 | ||
97755701 AL |
680 | ;; This is both the number of Q-Registers needed to hold the corresponding |
681 | ;; opaque large integer mode, and the number of elements touched by the | |
682 | ;; ld..._lane and st..._lane operations. | |
43e9d192 IB |
683 | (define_mode_attr nregs [(OI "2") (CI "3") (XI "4")]) |
684 | ||
685 | (define_mode_attr VRL2 [(V8QI "V32QI") (V4HI "V16HI") | |
71a11456 | 686 | (V4HF "V16HF") |
43e9d192 | 687 | (V2SI "V8SI") (V2SF "V8SF") |
110d61da | 688 | (DI "V4DI") (DF "V4DF")]) |
43e9d192 IB |
689 | |
690 | (define_mode_attr VRL3 [(V8QI "V48QI") (V4HI "V24HI") | |
71a11456 | 691 | (V4HF "V24HF") |
43e9d192 | 692 | (V2SI "V12SI") (V2SF "V12SF") |
110d61da | 693 | (DI "V6DI") (DF "V6DF")]) |
43e9d192 IB |
694 | |
695 | (define_mode_attr VRL4 [(V8QI "V64QI") (V4HI "V32HI") | |
71a11456 | 696 | (V4HF "V32HF") |
43e9d192 | 697 | (V2SI "V16SI") (V2SF "V16SF") |
110d61da | 698 | (DI "V8DI") (DF "V8DF")]) |
43e9d192 | 699 | |
0462169c SN |
700 | ;; Mode for atomic operation suffixes |
701 | (define_mode_attr atomic_sfx | |
702 | [(QI "b") (HI "h") (SI "") (DI "")]) | |
703 | ||
3f598afe | 704 | (define_mode_attr fcvt_target [(V2DF "v2di") (V4SF "v4si") (V2SF "v2si") |
2644d4d9 | 705 | (V2DI "v2df") (V4SI "v4sf") (V2SI "v2sf") |
daef0a8c JW |
706 | (SF "si") (DF "di") (SI "sf") (DI "df") |
707 | (V4HF "v4hi") (V8HF "v8hi") (V4HI "v4hf") | |
708 | (V8HI "v8hf")]) | |
3f598afe | 709 | (define_mode_attr FCVT_TARGET [(V2DF "V2DI") (V4SF "V4SI") (V2SF "V2SI") |
2644d4d9 | 710 | (V2DI "V2DF") (V4SI "V4SF") (V2SI "V2SF") |
daef0a8c JW |
711 | (SF "SI") (DF "DI") (SI "SF") (DI "DF") |
712 | (V4HF "V4HI") (V8HF "V8HI") (V4HI "V4HF") | |
713 | (V8HI "V8HF")]) | |
3f598afe | 714 | |
0d35c5c2 VP |
715 | |
716 | ;; for the inequal width integer to fp conversions | |
d7f33f07 JW |
717 | (define_mode_attr fcvt_iesize [(HF "di") (SF "di") (DF "si")]) |
718 | (define_mode_attr FCVT_IESIZE [(HF "DI") (SF "DI") (DF "SI")]) | |
42fc9a7f | 719 | |
91bd4114 JG |
720 | (define_mode_attr VSWAP_WIDTH [(V8QI "V16QI") (V16QI "V8QI") |
721 | (V4HI "V8HI") (V8HI "V4HI") | |
722 | (V2SI "V4SI") (V4SI "V2SI") | |
723 | (DI "V2DI") (V2DI "DI") | |
724 | (V2SF "V4SF") (V4SF "V2SF") | |
862abc04 | 725 | (V4HF "V8HF") (V8HF "V4HF") |
91bd4114 JG |
726 | (DF "V2DF") (V2DF "DF")]) |
727 | ||
728 | (define_mode_attr vswap_width_name [(V8QI "to_128") (V16QI "to_64") | |
729 | (V4HI "to_128") (V8HI "to_64") | |
730 | (V2SI "to_128") (V4SI "to_64") | |
731 | (DI "to_128") (V2DI "to_64") | |
862abc04 | 732 | (V4HF "to_128") (V8HF "to_64") |
91bd4114 JG |
733 | (V2SF "to_128") (V4SF "to_64") |
734 | (DF "to_128") (V2DF "to_64")]) | |
735 | ||
779aea46 JG |
736 | ;; For certain vector-by-element multiplication instructions we must |
737 | ;; constrain the HI cases to use only V0-V15. This is covered by | |
738 | ;; the 'x' constraint. All other modes may use the 'w' constraint. | |
739 | (define_mode_attr h_con [(V2SI "w") (V4SI "w") | |
740 | (V4HI "x") (V8HI "x") | |
daef0a8c | 741 | (V4HF "w") (V8HF "w") |
779aea46 JG |
742 | (V2SF "w") (V4SF "w") |
743 | (V2DF "w") (DF "w")]) | |
744 | ||
745 | ;; Defined to 'f' for types whose element type is a float type. | |
746 | (define_mode_attr f [(V8QI "") (V16QI "") | |
747 | (V4HI "") (V8HI "") | |
748 | (V2SI "") (V4SI "") | |
749 | (DI "") (V2DI "") | |
ab2e8f01 | 750 | (V4HF "f") (V8HF "f") |
779aea46 JG |
751 | (V2SF "f") (V4SF "f") |
752 | (V2DF "f") (DF "f")]) | |
753 | ||
0f686aa9 JG |
754 | ;; Defined to '_fp' for types whose element type is a float type. |
755 | (define_mode_attr fp [(V8QI "") (V16QI "") | |
756 | (V4HI "") (V8HI "") | |
757 | (V2SI "") (V4SI "") | |
758 | (DI "") (V2DI "") | |
ab2e8f01 | 759 | (V4HF "_fp") (V8HF "_fp") |
0f686aa9 JG |
760 | (V2SF "_fp") (V4SF "_fp") |
761 | (V2DF "_fp") (DF "_fp") | |
762 | (SF "_fp")]) | |
763 | ||
a9e66678 JG |
764 | ;; Defined to '_q' for 128-bit types. |
765 | (define_mode_attr q [(V8QI "") (V16QI "_q") | |
0f686aa9 JG |
766 | (V4HI "") (V8HI "_q") |
767 | (V2SI "") (V4SI "_q") | |
768 | (DI "") (V2DI "_q") | |
71a11456 | 769 | (V4HF "") (V8HF "_q") |
0f686aa9 JG |
770 | (V2SF "") (V4SF "_q") |
771 | (V2DF "_q") | |
d7f33f07 | 772 | (QI "") (HI "") (SI "") (DI "") (HF "") (SF "") (DF "")]) |
a9e66678 | 773 | |
92835317 TB |
774 | (define_mode_attr vp [(V8QI "v") (V16QI "v") |
775 | (V4HI "v") (V8HI "v") | |
776 | (V2SI "p") (V4SI "v") | |
703bbcdf JW |
777 | (V2DI "p") (V2DF "p") |
778 | (V2SF "p") (V4SF "v") | |
779 | (V4HF "v") (V8HF "v")]) | |
92835317 | 780 | |
5e32e83b JW |
781 | (define_mode_attr vsi2qi [(V2SI "v8qi") (V4SI "v16qi")]) |
782 | (define_mode_attr VSI2QI [(V2SI "V8QI") (V4SI "V16QI")]) | |
783 | ||
cd78b3dd | 784 | ;; Sum of lengths of instructions needed to move vector registers of a mode. |
668046d1 DS |
785 | (define_mode_attr insn_count [(OI "8") (CI "12") (XI "16")]) |
786 | ||
1b1e81f8 JW |
787 | ;; -fpic small model GOT reloc modifers: gotpage_lo15/lo14 for ILP64/32. |
788 | ;; No need of iterator for -fPIC as it use got_lo12 for both modes. | |
789 | (define_mode_attr got_modifier [(SI "gotpage_lo14") (DI "gotpage_lo15")]) | |
790 | ||
43e9d192 IB |
791 | ;; ------------------------------------------------------------------- |
792 | ;; Code Iterators | |
793 | ;; ------------------------------------------------------------------- | |
794 | ||
795 | ;; This code iterator allows the various shifts supported on the core | |
796 | (define_code_iterator SHIFT [ashift ashiftrt lshiftrt rotatert]) | |
797 | ||
798 | ;; This code iterator allows the shifts supported in arithmetic instructions | |
799 | (define_code_iterator ASHIFT [ashift ashiftrt lshiftrt]) | |
800 | ||
801 | ;; Code iterator for logical operations | |
802 | (define_code_iterator LOGICAL [and ior xor]) | |
803 | ||
84be6032 AL |
804 | ;; Code iterator for logical operations whose :nlogical works on SIMD registers. |
805 | (define_code_iterator NLOGICAL [and ior]) | |
806 | ||
3204ac98 KT |
807 | ;; Code iterator for unary negate and bitwise complement. |
808 | (define_code_iterator NEG_NOT [neg not]) | |
809 | ||
43e9d192 IB |
810 | ;; Code iterator for sign/zero extension |
811 | (define_code_iterator ANY_EXTEND [sign_extend zero_extend]) | |
812 | ||
813 | ;; All division operations (signed/unsigned) | |
814 | (define_code_iterator ANY_DIV [div udiv]) | |
815 | ||
816 | ;; Code iterator for sign/zero extraction | |
817 | (define_code_iterator ANY_EXTRACT [sign_extract zero_extract]) | |
818 | ||
819 | ;; Code iterator for equality comparisons | |
820 | (define_code_iterator EQL [eq ne]) | |
821 | ||
822 | ;; Code iterator for less-than and greater/equal-to | |
823 | (define_code_iterator LTGE [lt ge]) | |
824 | ||
825 | ;; Iterator for __sync_<op> operations that where the operation can be | |
826 | ;; represented directly RTL. This is all of the sync operations bar | |
827 | ;; nand. | |
0462169c | 828 | (define_code_iterator atomic_op [plus minus ior xor and]) |
43e9d192 IB |
829 | |
830 | ;; Iterator for integer conversions | |
831 | (define_code_iterator FIXUORS [fix unsigned_fix]) | |
832 | ||
1709ff9b JG |
833 | ;; Iterator for float conversions |
834 | (define_code_iterator FLOATUORS [float unsigned_float]) | |
835 | ||
43e9d192 IB |
836 | ;; Code iterator for variants of vector max and min. |
837 | (define_code_iterator MAXMIN [smax smin umax umin]) | |
838 | ||
998eaf97 JG |
839 | (define_code_iterator FMAXMIN [smax smin]) |
840 | ||
43e9d192 IB |
841 | ;; Code iterator for variants of vector max and min. |
842 | (define_code_iterator ADDSUB [plus minus]) | |
843 | ||
844 | ;; Code iterator for variants of vector saturating binary ops. | |
845 | (define_code_iterator BINQOPS [ss_plus us_plus ss_minus us_minus]) | |
846 | ||
847 | ;; Code iterator for variants of vector saturating unary ops. | |
848 | (define_code_iterator UNQOPS [ss_neg ss_abs]) | |
849 | ||
850 | ;; Code iterator for signed variants of vector saturating binary ops. | |
851 | (define_code_iterator SBINQOPS [ss_plus ss_minus]) | |
852 | ||
889b9412 JG |
853 | ;; Comparison operators for <F>CM. |
854 | (define_code_iterator COMPARISONS [lt le eq ge gt]) | |
855 | ||
856 | ;; Unsigned comparison operators. | |
857 | (define_code_iterator UCOMPARISONS [ltu leu geu gtu]) | |
858 | ||
75dd5ace JG |
859 | ;; Unsigned comparison operators. |
860 | (define_code_iterator FAC_COMPARISONS [lt le ge gt]) | |
861 | ||
43e9d192 IB |
862 | ;; ------------------------------------------------------------------- |
863 | ;; Code Attributes | |
864 | ;; ------------------------------------------------------------------- | |
865 | ;; Map rtl objects to optab names | |
866 | (define_code_attr optab [(ashift "ashl") | |
867 | (ashiftrt "ashr") | |
868 | (lshiftrt "lshr") | |
869 | (rotatert "rotr") | |
870 | (sign_extend "extend") | |
871 | (zero_extend "zero_extend") | |
872 | (sign_extract "extv") | |
873 | (zero_extract "extzv") | |
384be29f JG |
874 | (fix "fix") |
875 | (unsigned_fix "fixuns") | |
1709ff9b JG |
876 | (float "float") |
877 | (unsigned_float "floatuns") | |
43e9d192 IB |
878 | (and "and") |
879 | (ior "ior") | |
880 | (xor "xor") | |
881 | (not "one_cmpl") | |
882 | (neg "neg") | |
883 | (plus "add") | |
884 | (minus "sub") | |
885 | (ss_plus "qadd") | |
886 | (us_plus "qadd") | |
887 | (ss_minus "qsub") | |
888 | (us_minus "qsub") | |
889 | (ss_neg "qneg") | |
890 | (ss_abs "qabs") | |
891 | (eq "eq") | |
892 | (ne "ne") | |
893 | (lt "lt") | |
889b9412 JG |
894 | (ge "ge") |
895 | (le "le") | |
896 | (gt "gt") | |
897 | (ltu "ltu") | |
898 | (leu "leu") | |
899 | (geu "geu") | |
900 | (gtu "gtu")]) | |
901 | ||
902 | ;; For comparison operators we use the FCM* and CM* instructions. | |
903 | ;; As there are no CMLE or CMLT instructions which act on 3 vector | |
904 | ;; operands, we must use CMGE or CMGT and swap the order of the | |
905 | ;; source operands. | |
906 | ||
907 | (define_code_attr n_optab [(lt "gt") (le "ge") (eq "eq") (ge "ge") (gt "gt") | |
908 | (ltu "hi") (leu "hs") (geu "hs") (gtu "hi")]) | |
909 | (define_code_attr cmp_1 [(lt "2") (le "2") (eq "1") (ge "1") (gt "1") | |
910 | (ltu "2") (leu "2") (geu "1") (gtu "1")]) | |
911 | (define_code_attr cmp_2 [(lt "1") (le "1") (eq "2") (ge "2") (gt "2") | |
912 | (ltu "1") (leu "1") (geu "2") (gtu "2")]) | |
913 | ||
914 | (define_code_attr CMP [(lt "LT") (le "LE") (eq "EQ") (ge "GE") (gt "GT") | |
714e1b3b KT |
915 | (ltu "LTU") (leu "LEU") (ne "NE") (geu "GEU") |
916 | (gtu "GTU")]) | |
43e9d192 | 917 | |
384be29f JG |
918 | (define_code_attr fix_trunc_optab [(fix "fix_trunc") |
919 | (unsigned_fix "fixuns_trunc")]) | |
920 | ||
43e9d192 IB |
921 | ;; Optab prefix for sign/zero-extending operations |
922 | (define_code_attr su_optab [(sign_extend "") (zero_extend "u") | |
923 | (div "") (udiv "u") | |
924 | (fix "") (unsigned_fix "u") | |
1709ff9b | 925 | (float "s") (unsigned_float "u") |
43e9d192 IB |
926 | (ss_plus "s") (us_plus "u") |
927 | (ss_minus "s") (us_minus "u")]) | |
928 | ||
929 | ;; Similar for the instruction mnemonics | |
930 | (define_code_attr shift [(ashift "lsl") (ashiftrt "asr") | |
931 | (lshiftrt "lsr") (rotatert "ror")]) | |
932 | ||
933 | ;; Map shift operators onto underlying bit-field instructions | |
934 | (define_code_attr bfshift [(ashift "ubfiz") (ashiftrt "sbfx") | |
935 | (lshiftrt "ubfx") (rotatert "extr")]) | |
936 | ||
937 | ;; Logical operator instruction mnemonics | |
938 | (define_code_attr logical [(and "and") (ior "orr") (xor "eor")]) | |
939 | ||
3204ac98 KT |
940 | ;; Operation names for negate and bitwise complement. |
941 | (define_code_attr neg_not_op [(neg "neg") (not "not")]) | |
942 | ||
43e9d192 IB |
943 | ;; Similar, but when not(op) |
944 | (define_code_attr nlogical [(and "bic") (ior "orn") (xor "eon")]) | |
945 | ||
946 | ;; Sign- or zero-extending load | |
947 | (define_code_attr ldrxt [(sign_extend "ldrs") (zero_extend "ldr")]) | |
948 | ||
949 | ;; Sign- or zero-extending data-op | |
950 | (define_code_attr su [(sign_extend "s") (zero_extend "u") | |
951 | (sign_extract "s") (zero_extract "u") | |
952 | (fix "s") (unsigned_fix "u") | |
998eaf97 JG |
953 | (div "s") (udiv "u") |
954 | (smax "s") (umax "u") | |
955 | (smin "s") (umin "u")]) | |
43e9d192 | 956 | |
096e8448 JW |
957 | ;; Emit conditional branch instructions. |
958 | (define_code_attr bcond [(eq "beq") (ne "bne") (lt "bne") (ge "beq")]) | |
959 | ||
43e9d192 IB |
960 | ;; Emit cbz/cbnz depending on comparison type. |
961 | (define_code_attr cbz [(eq "cbz") (ne "cbnz") (lt "cbnz") (ge "cbz")]) | |
962 | ||
973d2e01 TP |
963 | ;; Emit inverted cbz/cbnz depending on comparison type. |
964 | (define_code_attr inv_cb [(eq "cbnz") (ne "cbz") (lt "cbz") (ge "cbnz")]) | |
965 | ||
43e9d192 IB |
966 | ;; Emit tbz/tbnz depending on comparison type. |
967 | (define_code_attr tbz [(eq "tbz") (ne "tbnz") (lt "tbnz") (ge "tbz")]) | |
968 | ||
973d2e01 TP |
969 | ;; Emit inverted tbz/tbnz depending on comparison type. |
970 | (define_code_attr inv_tb [(eq "tbnz") (ne "tbz") (lt "tbz") (ge "tbnz")]) | |
971 | ||
43e9d192 | 972 | ;; Max/min attributes. |
998eaf97 JG |
973 | (define_code_attr maxmin [(smax "max") |
974 | (smin "min") | |
975 | (umax "max") | |
976 | (umin "min")]) | |
43e9d192 IB |
977 | |
978 | ;; MLA/MLS attributes. | |
979 | (define_code_attr as [(ss_plus "a") (ss_minus "s")]) | |
980 | ||
0462169c SN |
981 | ;; Atomic operations |
982 | (define_code_attr atomic_optab | |
983 | [(ior "or") (xor "xor") (and "and") (plus "add") (minus "sub")]) | |
984 | ||
985 | (define_code_attr atomic_op_operand | |
986 | [(ior "aarch64_logical_operand") | |
987 | (xor "aarch64_logical_operand") | |
988 | (and "aarch64_logical_operand") | |
989 | (plus "aarch64_plus_operand") | |
990 | (minus "aarch64_plus_operand")]) | |
43e9d192 | 991 | |
356c32e2 MW |
992 | ;; Constants acceptable for atomic operations. |
993 | ;; This definition must appear in this file before the iterators it refers to. | |
994 | (define_code_attr const_atomic | |
995 | [(plus "IJ") (minus "IJ") | |
996 | (xor "<lconst_atomic>") (ior "<lconst_atomic>") | |
997 | (and "<lconst_atomic>")]) | |
998 | ||
999 | ;; Attribute to describe constants acceptable in atomic logical operations | |
1000 | (define_mode_attr lconst_atomic [(QI "K") (HI "K") (SI "K") (DI "L")]) | |
1001 | ||
43e9d192 IB |
1002 | ;; ------------------------------------------------------------------- |
1003 | ;; Int Iterators. | |
1004 | ;; ------------------------------------------------------------------- | |
1005 | (define_int_iterator MAXMINV [UNSPEC_UMAXV UNSPEC_UMINV | |
1006 | UNSPEC_SMAXV UNSPEC_SMINV]) | |
1007 | ||
998eaf97 JG |
1008 | (define_int_iterator FMAXMINV [UNSPEC_FMAXV UNSPEC_FMINV |
1009 | UNSPEC_FMAXNMV UNSPEC_FMINNMV]) | |
43e9d192 IB |
1010 | |
1011 | (define_int_iterator HADDSUB [UNSPEC_SHADD UNSPEC_UHADD | |
1012 | UNSPEC_SRHADD UNSPEC_URHADD | |
1013 | UNSPEC_SHSUB UNSPEC_UHSUB | |
1014 | UNSPEC_SRHSUB UNSPEC_URHSUB]) | |
1015 | ||
1016 | ||
1017 | (define_int_iterator ADDSUBHN [UNSPEC_ADDHN UNSPEC_RADDHN | |
1018 | UNSPEC_SUBHN UNSPEC_RSUBHN]) | |
1019 | ||
1020 | (define_int_iterator ADDSUBHN2 [UNSPEC_ADDHN2 UNSPEC_RADDHN2 | |
1021 | UNSPEC_SUBHN2 UNSPEC_RSUBHN2]) | |
1022 | ||
998eaf97 | 1023 | (define_int_iterator FMAXMIN_UNS [UNSPEC_FMAX UNSPEC_FMIN]) |
43e9d192 | 1024 | |
202d0c11 DS |
1025 | (define_int_iterator FMAXMIN [UNSPEC_FMAXNM UNSPEC_FMINNM]) |
1026 | ||
43e9d192 IB |
1027 | (define_int_iterator VQDMULH [UNSPEC_SQDMULH UNSPEC_SQRDMULH]) |
1028 | ||
1029 | (define_int_iterator USSUQADD [UNSPEC_SUQADD UNSPEC_USQADD]) | |
1030 | ||
1031 | (define_int_iterator SUQMOVN [UNSPEC_SQXTN UNSPEC_UQXTN]) | |
1032 | ||
1033 | (define_int_iterator VSHL [UNSPEC_SSHL UNSPEC_USHL | |
1034 | UNSPEC_SRSHL UNSPEC_URSHL]) | |
1035 | ||
1036 | (define_int_iterator VSHLL [UNSPEC_SSHLL UNSPEC_USHLL]) | |
1037 | ||
1038 | (define_int_iterator VQSHL [UNSPEC_SQSHL UNSPEC_UQSHL | |
1039 | UNSPEC_SQRSHL UNSPEC_UQRSHL]) | |
1040 | ||
1041 | (define_int_iterator VSRA [UNSPEC_SSRA UNSPEC_USRA | |
1042 | UNSPEC_SRSRA UNSPEC_URSRA]) | |
1043 | ||
1044 | (define_int_iterator VSLRI [UNSPEC_SSLI UNSPEC_USLI | |
1045 | UNSPEC_SSRI UNSPEC_USRI]) | |
1046 | ||
1047 | ||
1048 | (define_int_iterator VRSHR_N [UNSPEC_SRSHR UNSPEC_URSHR]) | |
1049 | ||
1050 | (define_int_iterator VQSHL_N [UNSPEC_SQSHLU UNSPEC_SQSHL UNSPEC_UQSHL]) | |
1051 | ||
1052 | (define_int_iterator VQSHRN_N [UNSPEC_SQSHRUN UNSPEC_SQRSHRUN | |
1053 | UNSPEC_SQSHRN UNSPEC_UQSHRN | |
1054 | UNSPEC_SQRSHRN UNSPEC_UQRSHRN]) | |
1055 | ||
57b26d65 MW |
1056 | (define_int_iterator SQRDMLH_AS [UNSPEC_SQRDMLAH UNSPEC_SQRDMLSH]) |
1057 | ||
cc4d934f JG |
1058 | (define_int_iterator PERMUTE [UNSPEC_ZIP1 UNSPEC_ZIP2 |
1059 | UNSPEC_TRN1 UNSPEC_TRN2 | |
1060 | UNSPEC_UZP1 UNSPEC_UZP2]) | |
43e9d192 | 1061 | |
923fcec3 AL |
1062 | (define_int_iterator REVERSE [UNSPEC_REV64 UNSPEC_REV32 UNSPEC_REV16]) |
1063 | ||
42fc9a7f | 1064 | (define_int_iterator FRINT [UNSPEC_FRINTZ UNSPEC_FRINTP UNSPEC_FRINTM |
0659ce6f JG |
1065 | UNSPEC_FRINTN UNSPEC_FRINTI UNSPEC_FRINTX |
1066 | UNSPEC_FRINTA]) | |
42fc9a7f JG |
1067 | |
1068 | (define_int_iterator FCVT [UNSPEC_FRINTZ UNSPEC_FRINTP UNSPEC_FRINTM | |
ce966824 | 1069 | UNSPEC_FRINTA UNSPEC_FRINTN]) |
42fc9a7f | 1070 | |
3f598afe JW |
1071 | (define_int_iterator FCVT_F2FIXED [UNSPEC_FCVTZS UNSPEC_FCVTZU]) |
1072 | (define_int_iterator FCVT_FIXED2F [UNSPEC_SCVTF UNSPEC_UCVTF]) | |
1073 | ||
0050faf8 JG |
1074 | (define_int_iterator FRECP [UNSPEC_FRECPE UNSPEC_FRECPX]) |
1075 | ||
5d357f26 KT |
1076 | (define_int_iterator CRC [UNSPEC_CRC32B UNSPEC_CRC32H UNSPEC_CRC32W |
1077 | UNSPEC_CRC32X UNSPEC_CRC32CB UNSPEC_CRC32CH | |
1078 | UNSPEC_CRC32CW UNSPEC_CRC32CX]) | |
1079 | ||
5a7a4e80 TB |
1080 | (define_int_iterator CRYPTO_AES [UNSPEC_AESE UNSPEC_AESD]) |
1081 | (define_int_iterator CRYPTO_AESMC [UNSPEC_AESMC UNSPEC_AESIMC]) | |
1082 | ||
30442682 TB |
1083 | (define_int_iterator CRYPTO_SHA1 [UNSPEC_SHA1C UNSPEC_SHA1M UNSPEC_SHA1P]) |
1084 | ||
b9cb0a44 TB |
1085 | (define_int_iterator CRYPTO_SHA256 [UNSPEC_SHA256H UNSPEC_SHA256H2]) |
1086 | ||
d81cb613 MW |
1087 | ;; Iterators for atomic operations. |
1088 | ||
1089 | (define_int_iterator ATOMIC_LDOP | |
1090 | [UNSPECV_ATOMIC_LDOP_OR UNSPECV_ATOMIC_LDOP_BIC | |
1091 | UNSPECV_ATOMIC_LDOP_XOR UNSPECV_ATOMIC_LDOP_PLUS]) | |
1092 | ||
1093 | (define_int_attr atomic_ldop | |
1094 | [(UNSPECV_ATOMIC_LDOP_OR "set") (UNSPECV_ATOMIC_LDOP_BIC "clr") | |
1095 | (UNSPECV_ATOMIC_LDOP_XOR "eor") (UNSPECV_ATOMIC_LDOP_PLUS "add")]) | |
1096 | ||
43e9d192 IB |
1097 | ;; ------------------------------------------------------------------- |
1098 | ;; Int Iterators Attributes. | |
1099 | ;; ------------------------------------------------------------------- | |
998eaf97 JG |
1100 | (define_int_attr maxmin_uns [(UNSPEC_UMAXV "umax") |
1101 | (UNSPEC_UMINV "umin") | |
1102 | (UNSPEC_SMAXV "smax") | |
1103 | (UNSPEC_SMINV "smin") | |
1104 | (UNSPEC_FMAX "smax_nan") | |
1105 | (UNSPEC_FMAXNMV "smax") | |
1106 | (UNSPEC_FMAXV "smax_nan") | |
1107 | (UNSPEC_FMIN "smin_nan") | |
1108 | (UNSPEC_FMINNMV "smin") | |
1109 | (UNSPEC_FMINV "smin_nan")]) | |
1110 | ||
1111 | (define_int_attr maxmin_uns_op [(UNSPEC_UMAXV "umax") | |
1112 | (UNSPEC_UMINV "umin") | |
1113 | (UNSPEC_SMAXV "smax") | |
1114 | (UNSPEC_SMINV "smin") | |
1115 | (UNSPEC_FMAX "fmax") | |
1116 | (UNSPEC_FMAXNMV "fmaxnm") | |
1117 | (UNSPEC_FMAXV "fmax") | |
1118 | (UNSPEC_FMIN "fmin") | |
1119 | (UNSPEC_FMINNMV "fminnm") | |
1120 | (UNSPEC_FMINV "fmin")]) | |
43e9d192 | 1121 | |
202d0c11 DS |
1122 | (define_int_attr fmaxmin [(UNSPEC_FMAXNM "fmax") |
1123 | (UNSPEC_FMINNM "fmin")]) | |
1124 | ||
1125 | (define_int_attr fmaxmin_op [(UNSPEC_FMAXNM "fmaxnm") | |
1126 | (UNSPEC_FMINNM "fminnm")]) | |
1127 | ||
43e9d192 IB |
1128 | (define_int_attr sur [(UNSPEC_SHADD "s") (UNSPEC_UHADD "u") |
1129 | (UNSPEC_SRHADD "sr") (UNSPEC_URHADD "ur") | |
1130 | (UNSPEC_SHSUB "s") (UNSPEC_UHSUB "u") | |
1131 | (UNSPEC_SRHSUB "sr") (UNSPEC_URHSUB "ur") | |
1132 | (UNSPEC_ADDHN "") (UNSPEC_RADDHN "r") | |
1133 | (UNSPEC_SUBHN "") (UNSPEC_RSUBHN "r") | |
1134 | (UNSPEC_ADDHN2 "") (UNSPEC_RADDHN2 "r") | |
1135 | (UNSPEC_SUBHN2 "") (UNSPEC_RSUBHN2 "r") | |
1136 | (UNSPEC_SQXTN "s") (UNSPEC_UQXTN "u") | |
1137 | (UNSPEC_USQADD "us") (UNSPEC_SUQADD "su") | |
1138 | (UNSPEC_SSLI "s") (UNSPEC_USLI "u") | |
1139 | (UNSPEC_SSRI "s") (UNSPEC_USRI "u") | |
1140 | (UNSPEC_USRA "u") (UNSPEC_SSRA "s") | |
1141 | (UNSPEC_URSRA "ur") (UNSPEC_SRSRA "sr") | |
1142 | (UNSPEC_URSHR "ur") (UNSPEC_SRSHR "sr") | |
1143 | (UNSPEC_SQSHLU "s") (UNSPEC_SQSHL "s") | |
1144 | (UNSPEC_UQSHL "u") | |
1145 | (UNSPEC_SQSHRUN "s") (UNSPEC_SQRSHRUN "s") | |
1146 | (UNSPEC_SQSHRN "s") (UNSPEC_UQSHRN "u") | |
1147 | (UNSPEC_SQRSHRN "s") (UNSPEC_UQRSHRN "u") | |
1148 | (UNSPEC_USHL "u") (UNSPEC_SSHL "s") | |
1149 | (UNSPEC_USHLL "u") (UNSPEC_SSHLL "s") | |
1150 | (UNSPEC_URSHL "ur") (UNSPEC_SRSHL "sr") | |
1151 | (UNSPEC_UQRSHL "u") (UNSPEC_SQRSHL "s") | |
1152 | ]) | |
1153 | ||
1154 | (define_int_attr r [(UNSPEC_SQDMULH "") (UNSPEC_SQRDMULH "r") | |
1155 | (UNSPEC_SQSHRUN "") (UNSPEC_SQRSHRUN "r") | |
1156 | (UNSPEC_SQSHRN "") (UNSPEC_UQSHRN "") | |
1157 | (UNSPEC_SQRSHRN "r") (UNSPEC_UQRSHRN "r") | |
1158 | (UNSPEC_SQSHL "") (UNSPEC_UQSHL "") | |
1159 | (UNSPEC_SQRSHL "r")(UNSPEC_UQRSHL "r") | |
1160 | ]) | |
1161 | ||
1162 | (define_int_attr lr [(UNSPEC_SSLI "l") (UNSPEC_USLI "l") | |
1163 | (UNSPEC_SSRI "r") (UNSPEC_USRI "r")]) | |
1164 | ||
1165 | (define_int_attr u [(UNSPEC_SQSHLU "u") (UNSPEC_SQSHL "") (UNSPEC_UQSHL "") | |
1166 | (UNSPEC_SQSHRUN "u") (UNSPEC_SQRSHRUN "u") | |
1167 | (UNSPEC_SQSHRN "") (UNSPEC_UQSHRN "") | |
1168 | (UNSPEC_SQRSHRN "") (UNSPEC_UQRSHRN "")]) | |
1169 | ||
1170 | (define_int_attr addsub [(UNSPEC_SHADD "add") | |
1171 | (UNSPEC_UHADD "add") | |
1172 | (UNSPEC_SRHADD "add") | |
1173 | (UNSPEC_URHADD "add") | |
1174 | (UNSPEC_SHSUB "sub") | |
1175 | (UNSPEC_UHSUB "sub") | |
1176 | (UNSPEC_SRHSUB "sub") | |
1177 | (UNSPEC_URHSUB "sub") | |
1178 | (UNSPEC_ADDHN "add") | |
1179 | (UNSPEC_SUBHN "sub") | |
1180 | (UNSPEC_RADDHN "add") | |
1181 | (UNSPEC_RSUBHN "sub") | |
1182 | (UNSPEC_ADDHN2 "add") | |
1183 | (UNSPEC_SUBHN2 "sub") | |
1184 | (UNSPEC_RADDHN2 "add") | |
1185 | (UNSPEC_RSUBHN2 "sub")]) | |
1186 | ||
cb23a30c JG |
1187 | (define_int_attr offsetlr [(UNSPEC_SSLI "") (UNSPEC_USLI "") |
1188 | (UNSPEC_SSRI "offset_") | |
1189 | (UNSPEC_USRI "offset_")]) | |
43e9d192 | 1190 | |
42fc9a7f JG |
1191 | ;; Standard pattern names for floating-point rounding instructions. |
1192 | (define_int_attr frint_pattern [(UNSPEC_FRINTZ "btrunc") | |
1193 | (UNSPEC_FRINTP "ceil") | |
1194 | (UNSPEC_FRINTM "floor") | |
1195 | (UNSPEC_FRINTI "nearbyint") | |
1196 | (UNSPEC_FRINTX "rint") | |
0659ce6f JG |
1197 | (UNSPEC_FRINTA "round") |
1198 | (UNSPEC_FRINTN "frintn")]) | |
42fc9a7f JG |
1199 | |
1200 | ;; frint suffix for floating-point rounding instructions. | |
1201 | (define_int_attr frint_suffix [(UNSPEC_FRINTZ "z") (UNSPEC_FRINTP "p") | |
1202 | (UNSPEC_FRINTM "m") (UNSPEC_FRINTI "i") | |
0659ce6f JG |
1203 | (UNSPEC_FRINTX "x") (UNSPEC_FRINTA "a") |
1204 | (UNSPEC_FRINTN "n")]) | |
42fc9a7f JG |
1205 | |
1206 | (define_int_attr fcvt_pattern [(UNSPEC_FRINTZ "btrunc") (UNSPEC_FRINTA "round") | |
ce966824 JG |
1207 | (UNSPEC_FRINTP "ceil") (UNSPEC_FRINTM "floor") |
1208 | (UNSPEC_FRINTN "frintn")]) | |
42fc9a7f | 1209 | |
3f598afe JW |
1210 | (define_int_attr fcvt_fixed_insn [(UNSPEC_SCVTF "scvtf") |
1211 | (UNSPEC_UCVTF "ucvtf") | |
1212 | (UNSPEC_FCVTZS "fcvtzs") | |
1213 | (UNSPEC_FCVTZU "fcvtzu")]) | |
1214 | ||
cc4d934f JG |
1215 | (define_int_attr perm_insn [(UNSPEC_ZIP1 "zip") (UNSPEC_ZIP2 "zip") |
1216 | (UNSPEC_TRN1 "trn") (UNSPEC_TRN2 "trn") | |
1217 | (UNSPEC_UZP1 "uzp") (UNSPEC_UZP2 "uzp")]) | |
1218 | ||
923fcec3 AL |
1219 | ; op code for REV instructions (size within which elements are reversed). |
1220 | (define_int_attr rev_op [(UNSPEC_REV64 "64") (UNSPEC_REV32 "32") | |
1221 | (UNSPEC_REV16 "16")]) | |
1222 | ||
cc4d934f JG |
1223 | (define_int_attr perm_hilo [(UNSPEC_ZIP1 "1") (UNSPEC_ZIP2 "2") |
1224 | (UNSPEC_TRN1 "1") (UNSPEC_TRN2 "2") | |
1225 | (UNSPEC_UZP1 "1") (UNSPEC_UZP2 "2")]) | |
0050faf8 JG |
1226 | |
1227 | (define_int_attr frecp_suffix [(UNSPEC_FRECPE "e") (UNSPEC_FRECPX "x")]) | |
5a7a4e80 | 1228 | |
5d357f26 KT |
1229 | (define_int_attr crc_variant [(UNSPEC_CRC32B "crc32b") (UNSPEC_CRC32H "crc32h") |
1230 | (UNSPEC_CRC32W "crc32w") (UNSPEC_CRC32X "crc32x") | |
1231 | (UNSPEC_CRC32CB "crc32cb") (UNSPEC_CRC32CH "crc32ch") | |
1232 | (UNSPEC_CRC32CW "crc32cw") (UNSPEC_CRC32CX "crc32cx")]) | |
1233 | ||
1234 | (define_int_attr crc_mode [(UNSPEC_CRC32B "QI") (UNSPEC_CRC32H "HI") | |
1235 | (UNSPEC_CRC32W "SI") (UNSPEC_CRC32X "DI") | |
1236 | (UNSPEC_CRC32CB "QI") (UNSPEC_CRC32CH "HI") | |
1237 | (UNSPEC_CRC32CW "SI") (UNSPEC_CRC32CX "DI")]) | |
1238 | ||
5a7a4e80 TB |
1239 | (define_int_attr aes_op [(UNSPEC_AESE "e") (UNSPEC_AESD "d")]) |
1240 | (define_int_attr aesmc_op [(UNSPEC_AESMC "mc") (UNSPEC_AESIMC "imc")]) | |
30442682 TB |
1241 | |
1242 | (define_int_attr sha1_op [(UNSPEC_SHA1C "c") (UNSPEC_SHA1P "p") | |
1243 | (UNSPEC_SHA1M "m")]) | |
b9cb0a44 TB |
1244 | |
1245 | (define_int_attr sha256_op [(UNSPEC_SHA256H "") (UNSPEC_SHA256H2 "2")]) | |
57b26d65 MW |
1246 | |
1247 | (define_int_attr rdma_as [(UNSPEC_SQRDMLAH "a") (UNSPEC_SQRDMLSH "s")]) |