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Change default for jump_table expansion ratio to 8.
[thirdparty/gcc.git] / gcc / config / aarch64 / iterators.md
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43e9d192 1;; Machine description for AArch64 architecture.
85ec4feb 2;; Copyright (C) 2009-2018 Free Software Foundation, Inc.
43e9d192
IB		 3;; Contributed by ARM Ltd.
4;;
5;; This file is part of GCC.
6;;
7;; GCC is free software; you can redistribute it and/or modify it
8;; under the terms of the GNU General Public License as published by
9;; the Free Software Foundation; either version 3, or (at your option)
10;; any later version.
11;;
12;; GCC is distributed in the hope that it will be useful, but
13;; WITHOUT ANY WARRANTY; without even the implied warranty of
14;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15;; General Public License for more details.
16;;
17;; You should have received a copy of the GNU General Public License
18;; along with GCC; see the file COPYING3. If not see
19;; <http://www.gnu.org/licenses/>.
20
21;; -------------------------------------------------------------------
22;; Mode Iterators
23;; -------------------------------------------------------------------
24
25
26;; Iterator for General Purpose Integer registers (32- and 64-bit modes)
27(define_mode_iterator GPI [SI DI])
28
d7f33f07
JW		 29;; Iterator for HI, SI, DI, some instructions can only work on these modes.
30(define_mode_iterator GPI_I16 [(HI "AARCH64_ISA_F16") SI DI])
31
43e9d192
IB		 32;; Iterator for QI and HI modes
33(define_mode_iterator SHORT [QI HI])
34
35;; Iterator for all integer modes (up to 64-bit)
36(define_mode_iterator ALLI [QI HI SI DI])
37
43e9d192
IB		 38;; Iterator for all integer modes that can be extended (up to 64-bit)
39(define_mode_iterator ALLX [QI HI SI])
40
41;; Iterator for General Purpose Floating-point registers (32- and 64-bit modes)
42(define_mode_iterator GPF [SF DF])
43
d7f33f07
JW		 44;; Iterator for all scalar floating point modes (HF, SF, DF)
45(define_mode_iterator GPF_F16 [(HF "AARCH64_ISA_F16") SF DF])
46
90e6443f
TC		 47;; Iterator for all scalar floating point modes (HF, SF, DF)
48(define_mode_iterator GPF_HF [HF SF DF])
49
09fcd8e1
RR		 50;; Iterator for all scalar floating point modes (HF, SF, DF and TF)
51(define_mode_iterator GPF_TF_F16 [HF SF DF TF])
c2ec330c 52
922f9c25
AL		 53;; Double vector modes.
54(define_mode_iterator VDF [V2SF V4HF])
55
b4f50fd4
RR		 56;; Iterator for all scalar floating point modes (SF, DF and TF)
57(define_mode_iterator GPF_TF [SF DF TF])
58
43cacb12 59;; Integer Advanced SIMD modes.
43e9d192
IB		 60(define_mode_iterator VDQ_I [V8QI V16QI V4HI V8HI V2SI V4SI V2DI])
61
43cacb12 62;; Advanced SIMD and scalar, 64 & 128-bit container, all integer modes.
43e9d192
IB		 63(define_mode_iterator VSDQ_I [V8QI V16QI V4HI V8HI V2SI V4SI V2DI QI HI SI DI])
64
43cacb12
RS		 65;; Advanced SIMD and scalar, 64 & 128-bit container: all Advanced SIMD
66;; integer modes; 64-bit scalar integer mode.
43e9d192
IB		 67(define_mode_iterator VSDQ_I_DI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI DI])
68
69;; Double vector modes.
71a11456 70(define_mode_iterator VD [V8QI V4HI V4HF V2SI V2SF])
43e9d192 71
dfe1da23
JW		 72;; All modes stored in registers d0-d31.
73(define_mode_iterator DREG [V8QI V4HI V4HF V2SI V2SF DF])
74
75;; Copy of the above.
76(define_mode_iterator DREG2 [V8QI V4HI V4HF V2SI V2SF DF])
77
43cacb12 78;; Advanced SIMD, 64-bit container, all integer modes.
43e9d192
IB		 79(define_mode_iterator VD_BHSI [V8QI V4HI V2SI])
80
81;; 128 and 64-bit container; 8, 16, 32-bit vector integer modes
82(define_mode_iterator VDQ_BHSI [V8QI V16QI V4HI V8HI V2SI V4SI])
83
84;; Quad vector modes.
71a11456 85(define_mode_iterator VQ [V16QI V8HI V4SI V2DI V8HF V4SF V2DF])
43e9d192 86
d21052eb
TC		 87;; Quad integer vector modes.
88(define_mode_iterator VQ_I [V16QI V8HI V4SI V2DI])
89
51437269 90;; VQ without 2 element modes.
71a11456 91(define_mode_iterator VQ_NO2E [V16QI V8HI V4SI V8HF V4SF])
51437269
GW		 92
93;; Quad vector with only 2 element modes.
94(define_mode_iterator VQ_2E [V2DI V2DF])
95
28514dda
YZ		 96;; This mode iterator allows :P to be used for patterns that operate on
97;; addresses in different modes. In LP64, only DI will match, while in
98;; ILP32, either can match.
99(define_mode_iterator P [(SI "ptr_mode == SImode || Pmode == SImode")
100 (DI "ptr_mode == DImode || Pmode == DImode")])
101
43e9d192
IB		 102;; This mode iterator allows :PTR to be used for patterns that operate on
103;; pointer-sized quantities. Exactly one of the two alternatives will match.
28514dda 104(define_mode_iterator PTR [(SI "ptr_mode == SImode") (DI "ptr_mode == DImode")])
43e9d192 105
43cacb12 106;; Advanced SIMD Float modes suitable for moving, loading and storing.
862abc04
AL		 107(define_mode_iterator VDQF_F16 [V4HF V8HF V2SF V4SF V2DF])
108
43cacb12 109;; Advanced SIMD Float modes.
43e9d192 110(define_mode_iterator VDQF [V2SF V4SF V2DF])
daef0a8c
JW		 111(define_mode_iterator VHSDF [(V4HF "TARGET_SIMD_F16INST")
112 (V8HF "TARGET_SIMD_F16INST")
113 V2SF V4SF V2DF])
43e9d192 114
43cacb12 115;; Advanced SIMD Float modes, and DF.
daef0a8c
JW		 116(define_mode_iterator VHSDF_DF [(V4HF "TARGET_SIMD_F16INST")
117 (V8HF "TARGET_SIMD_F16INST")
118 V2SF V4SF V2DF DF])
d7f33f07
JW		 119(define_mode_iterator VHSDF_HSDF [(V4HF "TARGET_SIMD_F16INST")
120 (V8HF "TARGET_SIMD_F16INST")
121 V2SF V4SF V2DF
122 (HF "TARGET_SIMD_F16INST")
123 SF DF])
f421c516 124
43cacb12 125;; Advanced SIMD single Float modes.
828e70c1
JG		 126(define_mode_iterator VDQSF [V2SF V4SF])
127
03873eb9
AL		 128;; Quad vector Float modes with half/single elements.
129(define_mode_iterator VQ_HSF [V8HF V4SF])
130
fc21784d
JG		 131;; Modes suitable to use as the return type of a vcond expression.
132(define_mode_iterator VDQF_COND [V2SF V2SI V4SF V4SI V2DF V2DI])
133
43cacb12 134;; All scalar and Advanced SIMD Float modes.
889b9412
JG		 135(define_mode_iterator VALLF [V2SF V4SF V2DF SF DF])
136
43cacb12 137;; Advanced SIMD Float modes with 2 elements.
43e9d192
IB		 138(define_mode_iterator V2F [V2SF V2DF])
139
43cacb12 140;; All Advanced SIMD modes on which we support any arithmetic operations.
43e9d192
IB		 141(define_mode_iterator VALL [V8QI V16QI V4HI V8HI V2SI V4SI V2DI V2SF V4SF V2DF])
142
43cacb12 143;; All Advanced SIMD modes suitable for moving, loading, and storing.
71a11456
AL		 144(define_mode_iterator VALL_F16 [V8QI V16QI V4HI V8HI V2SI V4SI V2DI
145 V4HF V8HF V2SF V4SF V2DF])
146
88119b46
KT		 147;; The VALL_F16 modes except the 128-bit 2-element ones.
148(define_mode_iterator VALL_F16_NO_V2Q [V8QI V16QI V4HI V8HI V2SI V4SI
149 V4HF V8HF V2SF V4SF])
150
43cacb12 151;; All Advanced SIMD modes barring HF modes, plus DI.
a50344cb
TB		 152(define_mode_iterator VALLDI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI V2SF V4SF V2DF DI])
153
43cacb12 154;; All Advanced SIMD modes and DI.
71a11456
AL		 155(define_mode_iterator VALLDI_F16 [V8QI V16QI V4HI V8HI V2SI V4SI V2DI
156 V4HF V8HF V2SF V4SF V2DF DI])
157
43cacb12 158;; All Advanced SIMD modes, plus DI and DF.
46e778c4 159(define_mode_iterator VALLDIF [V8QI V16QI V4HI V8HI V2SI V4SI
7c369485 160 V2DI V4HF V8HF V2SF V4SF V2DF DI DF])
46e778c4 161
43cacb12 162;; Advanced SIMD modes for Integer reduction across lanes.
92835317
TB		 163(define_mode_iterator VDQV [V8QI V16QI V4HI V8HI V4SI V2DI])
164
43cacb12 165;; Advanced SIMD modes (except V2DI) for Integer reduction across lanes.
92835317 166(define_mode_iterator VDQV_S [V8QI V16QI V4HI V8HI V4SI])
43e9d192
IB		 167
168;; All double integer narrow-able modes.
169(define_mode_iterator VDN [V4HI V2SI DI])
170
171;; All quad integer narrow-able modes.
172(define_mode_iterator VQN [V8HI V4SI V2DI])
173
43cacb12
RS		 174;; Advanced SIMD and scalar 128-bit container: narrowable 16, 32, 64-bit
175;; integer modes
43e9d192
IB		 176(define_mode_iterator VSQN_HSDI [V8HI V4SI V2DI HI SI DI])
177
178;; All quad integer widen-able modes.
179(define_mode_iterator VQW [V16QI V8HI V4SI])
180
181;; Double vector modes for combines.
7c369485 182(define_mode_iterator VDC [V8QI V4HI V4HF V2SI V2SF DI DF])
43e9d192 183
43cacb12 184;; Advanced SIMD modes except double int.
43e9d192 185(define_mode_iterator VDQIF [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF V2DF])
703bbcdf
JW		 186(define_mode_iterator VDQIF_F16 [V8QI V16QI V4HI V8HI V2SI V4SI
187 V4HF V8HF V2SF V4SF V2DF])
43e9d192 188
43cacb12 189;; Advanced SIMD modes for S type.
58a3bd25
FY		 190(define_mode_iterator VDQ_SI [V2SI V4SI])
191
43cacb12 192;; Advanced SIMD modes for S and D.
2644d4d9
JW		 193(define_mode_iterator VDQ_SDI [V2SI V4SI V2DI])
194
43cacb12 195;; Advanced SIMD modes for H, S and D.
33d72b63
JW		 196(define_mode_iterator VDQ_HSDI [(V4HI "TARGET_SIMD_F16INST")
197 (V8HI "TARGET_SIMD_F16INST")
198 V2SI V4SI V2DI])
199
43cacb12 200;; Scalar and Advanced SIMD modes for S and D.
2644d4d9
JW		 201(define_mode_iterator VSDQ_SDI [V2SI V4SI V2DI SI DI])
202
43cacb12 203;; Scalar and Advanced SIMD modes for S and D, Advanced SIMD modes for H.
33d72b63
JW		 204(define_mode_iterator VSDQ_HSDI [(V4HI "TARGET_SIMD_F16INST")
205 (V8HI "TARGET_SIMD_F16INST")
68ad28c3
JW		 206 V2SI V4SI V2DI
207 (HI "TARGET_SIMD_F16INST")
208 SI DI])
33d72b63 209
43cacb12 210;; Advanced SIMD modes for Q and H types.
66adb8eb
JG		 211(define_mode_iterator VDQQH [V8QI V16QI V4HI V8HI])
212
43cacb12 213;; Advanced SIMD modes for H and S types.
43e9d192
IB		 214(define_mode_iterator VDQHS [V4HI V8HI V2SI V4SI])
215
43cacb12 216;; Advanced SIMD modes for H, S and D types.
c7f28cd5
KT		 217(define_mode_iterator VDQHSD [V4HI V8HI V2SI V4SI V2DI])
218
43cacb12 219;; Advanced SIMD and scalar integer modes for H and S.
43e9d192
IB		 220(define_mode_iterator VSDQ_HSI [V4HI V8HI V2SI V4SI HI SI])
221
43cacb12 222;; Advanced SIMD and scalar 64-bit container: 16, 32-bit integer modes.
43e9d192
IB		 223(define_mode_iterator VSD_HSI [V4HI V2SI HI SI])
224
43cacb12 225;; Advanced SIMD 64-bit container: 16, 32-bit integer modes.
43e9d192
IB		 226(define_mode_iterator VD_HSI [V4HI V2SI])
227
228;; Scalar 64-bit container: 16, 32-bit integer modes
229(define_mode_iterator SD_HSI [HI SI])
230
43cacb12 231;; Advanced SIMD 64-bit container: 16, 32-bit integer modes.
43e9d192
IB		 232(define_mode_iterator VQ_HSI [V8HI V4SI])
233
234;; All byte modes.
235(define_mode_iterator VB [V8QI V16QI])
236
5e32e83b
JW		 237;; 2 and 4 lane SI modes.
238(define_mode_iterator VS [V2SI V4SI])
239
43e9d192
IB		 240(define_mode_iterator TX [TI TF])
241
43cacb12 242;; Advanced SIMD opaque structure modes.
43e9d192
IB		 243(define_mode_iterator VSTRUCT [OI CI XI])
244
245;; Double scalar modes
246(define_mode_iterator DX [DI DF])
247
dfe1da23
JW		 248;; Duplicate of the above
249(define_mode_iterator DX2 [DI DF])
250
251;; Single scalar modes
252(define_mode_iterator SX [SI SF])
253
254;; Duplicate of the above
255(define_mode_iterator SX2 [SI SF])
256
257;; Single and double integer and float modes
258(define_mode_iterator DSX [DF DI SF SI])
259
260
43cacb12 261;; Modes available for Advanced SIMD <f>mul lane operations.
ab2e8f01
JW		 262(define_mode_iterator VMUL [V4HI V8HI V2SI V4SI
263 (V4HF "TARGET_SIMD_F16INST")
264 (V8HF "TARGET_SIMD_F16INST")
265 V2SF V4SF V2DF])
779aea46 266
43cacb12
RS		 267;; Modes available for Advanced SIMD <f>mul lane operations changing lane
268;; count.
779aea46
JG		 269(define_mode_iterator VMUL_CHANGE_NLANES [V4HI V8HI V2SI V4SI V2SF V4SF])
270
43cacb12
RS		 271;; All SVE vector modes.
272(define_mode_iterator SVE_ALL [VNx16QI VNx8HI VNx4SI VNx2DI
273 VNx8HF VNx4SF VNx2DF])
274
9f4cbab8
RS		 275;; All SVE vector structure modes.
276(define_mode_iterator SVE_STRUCT [VNx32QI VNx16HI VNx8SI VNx4DI
277 VNx16HF VNx8SF VNx4DF
278 VNx48QI VNx24HI VNx12SI VNx6DI
279 VNx24HF VNx12SF VNx6DF
280 VNx64QI VNx32HI VNx16SI VNx8DI
281 VNx32HF VNx16SF VNx8DF])
282
43cacb12
RS		 283;; All SVE vector modes that have 8-bit or 16-bit elements.
284(define_mode_iterator SVE_BH [VNx16QI VNx8HI VNx8HF])
285
286;; All SVE vector modes that have 8-bit, 16-bit or 32-bit elements.
287(define_mode_iterator SVE_BHS [VNx16QI VNx8HI VNx4SI VNx8HF VNx4SF])
288
289;; All SVE integer vector modes that have 8-bit, 16-bit or 32-bit elements.
290(define_mode_iterator SVE_BHSI [VNx16QI VNx8HI VNx4SI])
291
292;; All SVE integer vector modes that have 16-bit, 32-bit or 64-bit elements.
293(define_mode_iterator SVE_HSDI [VNx16QI VNx8HI VNx4SI])
294
295;; All SVE floating-point vector modes that have 16-bit or 32-bit elements.
296(define_mode_iterator SVE_HSF [VNx8HF VNx4SF])
297
298;; All SVE vector modes that have 32-bit or 64-bit elements.
299(define_mode_iterator SVE_SD [VNx4SI VNx2DI VNx4SF VNx2DF])
300
bfaa08b7
RS		 301;; All SVE vector modes that have 32-bit elements.
302(define_mode_iterator SVE_S [VNx4SI VNx4SF])
303
304;; All SVE vector modes that have 64-bit elements.
305(define_mode_iterator SVE_D [VNx2DI VNx2DF])
306
43cacb12
RS		 307;; All SVE integer vector modes that have 32-bit or 64-bit elements.
308(define_mode_iterator SVE_SDI [VNx4SI VNx2DI])
309
310;; All SVE integer vector modes.
311(define_mode_iterator SVE_I [VNx16QI VNx8HI VNx4SI VNx2DI])
312
313;; All SVE floating-point vector modes.
314(define_mode_iterator SVE_F [VNx8HF VNx4SF VNx2DF])
315
316;; All SVE predicate modes.
317(define_mode_iterator PRED_ALL [VNx16BI VNx8BI VNx4BI VNx2BI])
318
319;; SVE predicate modes that control 8-bit, 16-bit or 32-bit elements.
320(define_mode_iterator PRED_BHS [VNx16BI VNx8BI VNx4BI])
321
43e9d192
IB		 322;; ------------------------------------------------------------------
323;; Unspec enumerations for Advance SIMD. These could well go into
324;; aarch64.md but for their use in int_iterators here.
325;; ------------------------------------------------------------------
326
327(define_c_enum "unspec"
328 [
329 UNSPEC_ASHIFT_SIGNED ; Used in aarch-simd.md.
330 UNSPEC_ASHIFT_UNSIGNED ; Used in aarch64-simd.md.
285398d2 331 UNSPEC_ABS ; Used in aarch64-simd.md.
998eaf97
JG		 332 UNSPEC_FMAX ; Used in aarch64-simd.md.
333 UNSPEC_FMAXNMV ; Used in aarch64-simd.md.
43e9d192 334 UNSPEC_FMAXV ; Used in aarch64-simd.md.
998eaf97
JG		 335 UNSPEC_FMIN ; Used in aarch64-simd.md.
336 UNSPEC_FMINNMV ; Used in aarch64-simd.md.
43e9d192
IB		 337 UNSPEC_FMINV ; Used in aarch64-simd.md.
338 UNSPEC_FADDV ; Used in aarch64-simd.md.
f5156c3e 339 UNSPEC_ADDV ; Used in aarch64-simd.md.
43e9d192
IB		 340 UNSPEC_SMAXV ; Used in aarch64-simd.md.
341 UNSPEC_SMINV ; Used in aarch64-simd.md.
342 UNSPEC_UMAXV ; Used in aarch64-simd.md.
343 UNSPEC_UMINV ; Used in aarch64-simd.md.
344 UNSPEC_SHADD ; Used in aarch64-simd.md.
345 UNSPEC_UHADD ; Used in aarch64-simd.md.
346 UNSPEC_SRHADD ; Used in aarch64-simd.md.
347 UNSPEC_URHADD ; Used in aarch64-simd.md.
348 UNSPEC_SHSUB ; Used in aarch64-simd.md.
349 UNSPEC_UHSUB ; Used in aarch64-simd.md.
350 UNSPEC_SRHSUB ; Used in aarch64-simd.md.
351 UNSPEC_URHSUB ; Used in aarch64-simd.md.
352 UNSPEC_ADDHN ; Used in aarch64-simd.md.
353 UNSPEC_RADDHN ; Used in aarch64-simd.md.
354 UNSPEC_SUBHN ; Used in aarch64-simd.md.
355 UNSPEC_RSUBHN ; Used in aarch64-simd.md.
356 UNSPEC_ADDHN2 ; Used in aarch64-simd.md.
357 UNSPEC_RADDHN2 ; Used in aarch64-simd.md.
358 UNSPEC_SUBHN2 ; Used in aarch64-simd.md.
359 UNSPEC_RSUBHN2 ; Used in aarch64-simd.md.
360 UNSPEC_SQDMULH ; Used in aarch64-simd.md.
361 UNSPEC_SQRDMULH ; Used in aarch64-simd.md.
362 UNSPEC_PMUL ; Used in aarch64-simd.md.
496ea87d 363 UNSPEC_FMULX ; Used in aarch64-simd.md.
43e9d192
IB		 364 UNSPEC_USQADD ; Used in aarch64-simd.md.
365 UNSPEC_SUQADD ; Used in aarch64-simd.md.
366 UNSPEC_SQXTUN ; Used in aarch64-simd.md.
367 UNSPEC_SQXTN ; Used in aarch64-simd.md.
368 UNSPEC_UQXTN ; Used in aarch64-simd.md.
369 UNSPEC_SSRA ; Used in aarch64-simd.md.
370 UNSPEC_USRA ; Used in aarch64-simd.md.
371 UNSPEC_SRSRA ; Used in aarch64-simd.md.
372 UNSPEC_URSRA ; Used in aarch64-simd.md.
373 UNSPEC_SRSHR ; Used in aarch64-simd.md.
374 UNSPEC_URSHR ; Used in aarch64-simd.md.
375 UNSPEC_SQSHLU ; Used in aarch64-simd.md.
376 UNSPEC_SQSHL ; Used in aarch64-simd.md.
377 UNSPEC_UQSHL ; Used in aarch64-simd.md.
378 UNSPEC_SQSHRUN ; Used in aarch64-simd.md.
379 UNSPEC_SQRSHRUN ; Used in aarch64-simd.md.
380 UNSPEC_SQSHRN ; Used in aarch64-simd.md.
381 UNSPEC_UQSHRN ; Used in aarch64-simd.md.
382 UNSPEC_SQRSHRN ; Used in aarch64-simd.md.
383 UNSPEC_UQRSHRN ; Used in aarch64-simd.md.
384 UNSPEC_SSHL ; Used in aarch64-simd.md.
385 UNSPEC_USHL ; Used in aarch64-simd.md.
386 UNSPEC_SRSHL ; Used in aarch64-simd.md.
387 UNSPEC_URSHL ; Used in aarch64-simd.md.
388 UNSPEC_SQRSHL ; Used in aarch64-simd.md.
389 UNSPEC_UQRSHL ; Used in aarch64-simd.md.
43e9d192
IB		 390 UNSPEC_SSLI ; Used in aarch64-simd.md.
391 UNSPEC_USLI ; Used in aarch64-simd.md.
392 UNSPEC_SSRI ; Used in aarch64-simd.md.
393 UNSPEC_USRI ; Used in aarch64-simd.md.
394 UNSPEC_SSHLL ; Used in aarch64-simd.md.
395 UNSPEC_USHLL ; Used in aarch64-simd.md.
396 UNSPEC_ADDP ; Used in aarch64-simd.md.
88b08073 397 UNSPEC_TBL ; Used in vector permute patterns.
9371aecc 398 UNSPEC_TBX ; Used in vector permute patterns.
88b08073 399 UNSPEC_CONCAT ; Used in vector permute patterns.
3f8334a5
RS		 400
401 ;; The following permute unspecs are generated directly by
402 ;; aarch64_expand_vec_perm_const, so any changes to the underlying
403 ;; instructions would need a corresponding change there.
cc4d934f
JG		 404 UNSPEC_ZIP1 ; Used in vector permute patterns.
405 UNSPEC_ZIP2 ; Used in vector permute patterns.
406 UNSPEC_UZP1 ; Used in vector permute patterns.
407 UNSPEC_UZP2 ; Used in vector permute patterns.
408 UNSPEC_TRN1 ; Used in vector permute patterns.
409 UNSPEC_TRN2 ; Used in vector permute patterns.
3f8334a5 410 UNSPEC_EXT ; Used in vector permute patterns.
923fcec3
AL		 411 UNSPEC_REV64 ; Used in vector reverse patterns (permute).
412 UNSPEC_REV32 ; Used in vector reverse patterns (permute).
413 UNSPEC_REV16 ; Used in vector reverse patterns (permute).
3f8334a5 414
5a7a4e80
TB		 415 UNSPEC_AESE ; Used in aarch64-simd.md.
416 UNSPEC_AESD ; Used in aarch64-simd.md.
417 UNSPEC_AESMC ; Used in aarch64-simd.md.
418 UNSPEC_AESIMC ; Used in aarch64-simd.md.
30442682
TB		 419 UNSPEC_SHA1C ; Used in aarch64-simd.md.
420 UNSPEC_SHA1M ; Used in aarch64-simd.md.
421 UNSPEC_SHA1P ; Used in aarch64-simd.md.
422 UNSPEC_SHA1H ; Used in aarch64-simd.md.
423 UNSPEC_SHA1SU0 ; Used in aarch64-simd.md.
424 UNSPEC_SHA1SU1 ; Used in aarch64-simd.md.
b9cb0a44
TB		 425 UNSPEC_SHA256H ; Used in aarch64-simd.md.
426 UNSPEC_SHA256H2 ; Used in aarch64-simd.md.
427 UNSPEC_SHA256SU0 ; Used in aarch64-simd.md.
428 UNSPEC_SHA256SU1 ; Used in aarch64-simd.md.
7baa225d
TB		 429 UNSPEC_PMULL ; Used in aarch64-simd.md.
430 UNSPEC_PMULL2 ; Used in aarch64-simd.md.
668046d1 431 UNSPEC_REV_REGLIST ; Used in aarch64-simd.md.
9c004c58 432 UNSPEC_VEC_SHR ; Used in aarch64-simd.md.
57b26d65
MW		 433 UNSPEC_SQRDMLAH ; Used in aarch64-simd.md.
434 UNSPEC_SQRDMLSH ; Used in aarch64-simd.md.
202d0c11
DS		 435 UNSPEC_FMAXNM ; Used in aarch64-simd.md.
436 UNSPEC_FMINNM ; Used in aarch64-simd.md.
7a08d813
TC		 437 UNSPEC_SDOT ; Used in aarch64-simd.md.
438 UNSPEC_UDOT ; Used in aarch64-simd.md.
27086ea3
MC		 439 UNSPEC_SM3SS1 ; Used in aarch64-simd.md.
440 UNSPEC_SM3TT1A ; Used in aarch64-simd.md.
441 UNSPEC_SM3TT1B ; Used in aarch64-simd.md.
442 UNSPEC_SM3TT2A ; Used in aarch64-simd.md.
443 UNSPEC_SM3TT2B ; Used in aarch64-simd.md.
444 UNSPEC_SM3PARTW1 ; Used in aarch64-simd.md.
445 UNSPEC_SM3PARTW2 ; Used in aarch64-simd.md.
446 UNSPEC_SM4E ; Used in aarch64-simd.md.
447 UNSPEC_SM4EKEY ; Used in aarch64-simd.md.
448 UNSPEC_SHA512H ; Used in aarch64-simd.md.
449 UNSPEC_SHA512H2 ; Used in aarch64-simd.md.
450 UNSPEC_SHA512SU0 ; Used in aarch64-simd.md.
451 UNSPEC_SHA512SU1 ; Used in aarch64-simd.md.
452 UNSPEC_FMLAL ; Used in aarch64-simd.md.
453 UNSPEC_FMLSL ; Used in aarch64-simd.md.
454 UNSPEC_FMLAL2 ; Used in aarch64-simd.md.
455 UNSPEC_FMLSL2 ; Used in aarch64-simd.md.
43cacb12 456 UNSPEC_SEL ; Used in aarch64-sve.md.
898f07b0
RS		 457 UNSPEC_ANDV ; Used in aarch64-sve.md.
458 UNSPEC_IORV ; Used in aarch64-sve.md.
459 UNSPEC_XORV ; Used in aarch64-sve.md.
43cacb12
RS		 460 UNSPEC_ANDF ; Used in aarch64-sve.md.
461 UNSPEC_IORF ; Used in aarch64-sve.md.
462 UNSPEC_XORF ; Used in aarch64-sve.md.
11e9443f
RS		 463 UNSPEC_SMUL_HIGHPART ; Used in aarch64-sve.md.
464 UNSPEC_UMUL_HIGHPART ; Used in aarch64-sve.md.
0972596e
RS		 465 UNSPEC_COND_ADD ; Used in aarch64-sve.md.
466 UNSPEC_COND_SUB ; Used in aarch64-sve.md.
6c4fd4a9
RS		 467 UNSPEC_COND_MUL ; Used in aarch64-sve.md.
468 UNSPEC_COND_DIV ; Used in aarch64-sve.md.
0d2b3bca
RS		 469 UNSPEC_COND_MAX ; Used in aarch64-sve.md.
470 UNSPEC_COND_MIN ; Used in aarch64-sve.md.
43cacb12
RS		 471 UNSPEC_COND_LT ; Used in aarch64-sve.md.
472 UNSPEC_COND_LE ; Used in aarch64-sve.md.
473 UNSPEC_COND_EQ ; Used in aarch64-sve.md.
474 UNSPEC_COND_NE ; Used in aarch64-sve.md.
475 UNSPEC_COND_GE ; Used in aarch64-sve.md.
476 UNSPEC_COND_GT ; Used in aarch64-sve.md.
43cacb12 477 UNSPEC_LASTB ; Used in aarch64-sve.md.
43e9d192
IB		 478])
479
d81cb613
MW		 480;; ------------------------------------------------------------------
481;; Unspec enumerations for Atomics. They are here so that they can be
482;; used in the int_iterators for atomic operations.
483;; ------------------------------------------------------------------
484
485(define_c_enum "unspecv"
486 [
487 UNSPECV_LX ; Represent a load-exclusive.
488 UNSPECV_SX ; Represent a store-exclusive.
489 UNSPECV_LDA ; Represent an atomic load or load-acquire.
490 UNSPECV_STL ; Represent an atomic store or store-release.
491 UNSPECV_ATOMIC_CMPSW ; Represent an atomic compare swap.
492 UNSPECV_ATOMIC_EXCHG ; Represent an atomic exchange.
493 UNSPECV_ATOMIC_CAS ; Represent an atomic CAS.
494 UNSPECV_ATOMIC_SWP ; Represent an atomic SWP.
495 UNSPECV_ATOMIC_OP ; Represent an atomic operation.
496 UNSPECV_ATOMIC_LDOP ; Represent an atomic load-operation
497 UNSPECV_ATOMIC_LDOP_OR ; Represent an atomic load-or
498 UNSPECV_ATOMIC_LDOP_BIC ; Represent an atomic load-bic
499 UNSPECV_ATOMIC_LDOP_XOR ; Represent an atomic load-xor
500 UNSPECV_ATOMIC_LDOP_PLUS ; Represent an atomic load-add
501])
502
43e9d192
IB		 503;; -------------------------------------------------------------------
504;; Mode attributes
505;; -------------------------------------------------------------------
506
507;; In GPI templates, a string like "%<w>0" will expand to "%w0" in the
508;; 32-bit version and "%x0" in the 64-bit version.
509(define_mode_attr w [(QI "w") (HI "w") (SI "w") (DI "x") (SF "s") (DF "d")])
510
db46a2e6
JG		 511;; The size of access, in bytes.
512(define_mode_attr ldst_sz [(SI "4") (DI "8")])
513;; Likewise for load/store pair.
514(define_mode_attr ldpstp_sz [(SI "8") (DI "16")])
515
0d35c5c2 516;; For inequal width int to float conversion
d7f33f07
JW		 517(define_mode_attr w1 [(HF "w") (SF "w") (DF "x")])
518(define_mode_attr w2 [(HF "x") (SF "x") (DF "w")])
0d35c5c2 519
22be0d08
MC		 520;; For width of fp registers in fcvt instruction
521(define_mode_attr fpw [(DI "s") (SI "d")])
522
2b8568fe
KT		 523(define_mode_attr short_mask [(HI "65535") (QI "255")])
524
051d0e2f
SN		 525;; For constraints used in scalar immediate vector moves
526(define_mode_attr hq [(HI "h") (QI "q")])
527
ef22810a
RH		 528;; For doubling width of an integer mode
529(define_mode_attr DWI [(QI "HI") (HI "SI") (SI "DI") (DI "TI")])
530
22be0d08
MC		 531(define_mode_attr fcvt_change_mode [(SI "df") (DI "sf")])
532
533(define_mode_attr FCVT_CHANGE_MODE [(SI "DF") (DI "SF")])
534
43e9d192
IB		 535;; For scalar usage of vector/FP registers
536(define_mode_attr v [(QI "b") (HI "h") (SI "s") (DI "d")
d7f33f07 537 (HF "h") (SF "s") (DF "d")
43e9d192
IB		 538 (V8QI "") (V16QI "")
539 (V4HI "") (V8HI "")
540 (V2SI "") (V4SI "")
541 (V2DI "") (V2SF "")
daef0a8c
JW		 542 (V4SF "") (V4HF "")
543 (V8HF "") (V2DF "")])
43e9d192
IB		 544
545;; For scalar usage of vector/FP registers, narrowing
546(define_mode_attr vn2 [(QI "") (HI "b") (SI "h") (DI "s")
547 (V8QI "") (V16QI "")
548 (V4HI "") (V8HI "")
549 (V2SI "") (V4SI "")
550 (V2DI "") (V2SF "")
551 (V4SF "") (V2DF "")])
552
553;; For scalar usage of vector/FP registers, widening
554(define_mode_attr vw2 [(DI "") (QI "h") (HI "s") (SI "d")
555 (V8QI "") (V16QI "")
556 (V4HI "") (V8HI "")
557 (V2SI "") (V4SI "")
558 (V2DI "") (V2SF "")
559 (V4SF "") (V2DF "")])
560
89fdc743
IB		 561;; Register Type Name and Vector Arrangement Specifier for when
562;; we are doing scalar for DI and SIMD for SI (ignoring all but
563;; lane 0).
564(define_mode_attr rtn [(DI "d") (SI "")])
565(define_mode_attr vas [(DI "") (SI ".2s")])
566
7ac29c0f
RS		 567;; Map a vector to the number of units in it, if the size of the mode
568;; is constant.
569(define_mode_attr nunits [(V8QI "8") (V16QI "16")
570 (V4HI "4") (V8HI "8")
571 (V2SI "2") (V4SI "4")
572 (V2DI "2")
573 (V4HF "4") (V8HF "8")
574 (V2SF "2") (V4SF "4")
575 (V1DF "1") (V2DF "2")
576 (DI "1") (DF "1")])
577
b187677b
RS		 578;; Map a mode to the number of bits in it, if the size of the mode
579;; is constant.
580(define_mode_attr bitsize [(V8QI "64") (V16QI "128")
581 (V4HI "64") (V8HI "128")
582 (V2SI "64") (V4SI "128")
583 (V2DI "128")])
584
22be0d08
MC		 585;; Map a floating point or integer mode to the appropriate register name prefix
586(define_mode_attr s [(HF "h") (SF "s") (DF "d") (SI "s") (DI "d")])
43e9d192
IB		 587
588;; Give the length suffix letter for a sign- or zero-extension.
589(define_mode_attr size [(QI "b") (HI "h") (SI "w")])
590
591;; Give the number of bits in the mode
592(define_mode_attr sizen [(QI "8") (HI "16") (SI "32") (DI "64")])
593
594;; Give the ordinal of the MSB in the mode
595(define_mode_attr sizem1 [(QI "#7") (HI "#15") (SI "#31") (DI "#63")])
596
597;; Attribute to describe constants acceptable in logical operations
598(define_mode_attr lconst [(SI "K") (DI "L")])
599
43fd192f
MC		 600;; Attribute to describe constants acceptable in logical and operations
601(define_mode_attr lconst2 [(SI "UsO") (DI "UsP")])
602
43e9d192
IB		 603;; Map a mode to a specific constraint character.
604(define_mode_attr cmode [(QI "q") (HI "h") (SI "s") (DI "d")])
605
0603375c
KT		 606;; Map modes to Usg and Usj constraints for SISD right shifts
607(define_mode_attr cmode_simd [(SI "g") (DI "j")])
608
43e9d192
IB		 609(define_mode_attr Vtype [(V8QI "8b") (V16QI "16b")
610 (V4HI "4h") (V8HI "8h")
611 (V2SI "2s") (V4SI "4s")
612 (DI "1d") (DF "1d")
613 (V2DI "2d") (V2SF "2s")
7c369485
AL		 614 (V4SF "4s") (V2DF "2d")
615 (V4HF "4h") (V8HF "8h")])
43e9d192 616
c7f28cd5
KT		 617(define_mode_attr Vrevsuff [(V4HI "16") (V8HI "16") (V2SI "32")
618 (V4SI "32") (V2DI "64")])
619
43e9d192
IB		 620(define_mode_attr Vmtype [(V8QI ".8b") (V16QI ".16b")
621 (V4HI ".4h") (V8HI ".8h")
622 (V2SI ".2s") (V4SI ".4s")
71a11456
AL		 623 (V2DI ".2d") (V4HF ".4h")
624 (V8HF ".8h") (V2SF ".2s")
43e9d192
IB		 625 (V4SF ".4s") (V2DF ".2d")
626 (DI "") (SI "")
627 (HI "") (QI "")
d7f33f07
JW		 628 (TI "") (HF "")
629 (SF "") (DF "")])
43e9d192
IB		 630
631;; Register suffix narrowed modes for VQN.
632(define_mode_attr Vmntype [(V8HI ".8b") (V4SI ".4h")
633 (V2DI ".2s")
634 (DI "") (SI "")
635 (HI "")])
636
637;; Mode-to-individual element type mapping.
43cacb12
RS		 638(define_mode_attr Vetype [(V8QI "b") (V16QI "b") (VNx16QI "b") (VNx16BI "b")
639 (V4HI "h") (V8HI "h") (VNx8HI "h") (VNx8BI "h")
640 (V2SI "s") (V4SI "s") (VNx4SI "s") (VNx4BI "s")
641 (V2DI "d") (VNx2DI "d") (VNx2BI "d")
642 (V4HF "h") (V8HF "h") (VNx8HF "h")
643 (V2SF "s") (V4SF "s") (VNx4SF "s")
644 (V2DF "d") (VNx2DF "d")
d7f33f07 645 (HF "h")
0f686aa9 646 (SF "s") (DF "d")
43e9d192
IB		 647 (QI "b") (HI "h")
648 (SI "s") (DI "d")])
649
43cacb12
RS		 650;; Equivalent of "size" for a vector element.
651(define_mode_attr Vesize [(VNx16QI "b")
9f4cbab8
RS		 652 (VNx8HI "h") (VNx8HF "h")
653 (VNx4SI "w") (VNx4SF "w")
654 (VNx2DI "d") (VNx2DF "d")
655 (VNx32QI "b") (VNx48QI "b") (VNx64QI "b")
656 (VNx16HI "h") (VNx24HI "h") (VNx32HI "h")
657 (VNx16HF "h") (VNx24HF "h") (VNx32HF "h")
658 (VNx8SI "w") (VNx12SI "w") (VNx16SI "w")
659 (VNx8SF "w") (VNx12SF "w") (VNx16SF "w")
660 (VNx4DI "d") (VNx6DI "d") (VNx8DI "d")
661 (VNx4DF "d") (VNx6DF "d") (VNx8DF "d")])
43cacb12 662
daef0a8c
JW		 663;; Vetype is used everywhere in scheduling type and assembly output,
664;; sometimes they are not the same, for example HF modes on some
665;; instructions. stype is defined to represent scheduling type
666;; more accurately.
667(define_mode_attr stype [(V8QI "b") (V16QI "b") (V4HI "s") (V8HI "s")
668 (V2SI "s") (V4SI "s") (V2DI "d") (V4HF "s")
669 (V8HF "s") (V2SF "s") (V4SF "s") (V2DF "d")
670 (HF "s") (SF "s") (DF "d") (QI "b") (HI "s")
671 (SI "s") (DI "d")])
672
43e9d192
IB		 673;; Mode-to-bitwise operation type mapping.
674(define_mode_attr Vbtype [(V8QI "8b") (V16QI "16b")
675 (V4HI "8b") (V8HI "16b")
676 (V2SI "8b") (V4SI "16b")
7c369485
AL		 677 (V2DI "16b") (V4HF "8b")
678 (V8HF "16b") (V2SF "8b")
46e778c4 679 (V4SF "16b") (V2DF "16b")
fe82d1f2
AL		 680 (DI "8b") (DF "8b")
681 (SI "8b")])
43e9d192
IB		 682
683;; Define element mode for each vector mode.
43cacb12
RS		 684(define_mode_attr VEL [(V8QI "QI") (V16QI "QI") (VNx16QI "QI")
685 (V4HI "HI") (V8HI "HI") (VNx8HI "HI")
686 (V2SI "SI") (V4SI "SI") (VNx4SI "SI")
687 (DI "DI") (V2DI "DI") (VNx2DI "DI")
688 (V4HF "HF") (V8HF "HF") (VNx8HF "HF")
689 (V2SF "SF") (V4SF "SF") (VNx4SF "SF")
690 (DF "DF") (V2DF "DF") (VNx2DF "DF")
691 (SI "SI") (HI "HI")
43e9d192
IB		 692 (QI "QI")])
693
ff03930a 694;; Define element mode for each vector mode (lower case).
43cacb12
RS		 695(define_mode_attr Vel [(V8QI "qi") (V16QI "qi") (VNx16QI "qi")
696 (V4HI "hi") (V8HI "hi") (VNx8HI "hi")
697 (V2SI "si") (V4SI "si") (VNx4SI "si")
698 (DI "di") (V2DI "di") (VNx2DI "di")
699 (V4HF "hf") (V8HF "hf") (VNx8HF "hf")
700 (V2SF "sf") (V4SF "sf") (VNx4SF "sf")
701 (V2DF "df") (DF "df") (VNx2DF "df")
ff03930a
JJ		 702 (SI "si") (HI "hi")
703 (QI "qi")])
704
43cacb12
RS		 705;; Element mode with floating-point values replaced by like-sized integers.
706(define_mode_attr VEL_INT [(VNx16QI "QI")
707 (VNx8HI "HI") (VNx8HF "HI")
708 (VNx4SI "SI") (VNx4SF "SI")
709 (VNx2DI "DI") (VNx2DF "DI")])
710
711;; Gives the mode of the 128-bit lowpart of an SVE vector.
712(define_mode_attr V128 [(VNx16QI "V16QI")
713 (VNx8HI "V8HI") (VNx8HF "V8HF")
714 (VNx4SI "V4SI") (VNx4SF "V4SF")
715 (VNx2DI "V2DI") (VNx2DF "V2DF")])
716
717;; ...and again in lower case.
718(define_mode_attr v128 [(VNx16QI "v16qi")
719 (VNx8HI "v8hi") (VNx8HF "v8hf")
720 (VNx4SI "v4si") (VNx4SF "v4sf")
721 (VNx2DI "v2di") (VNx2DF "v2df")])
722
278821f2
KT		 723;; 64-bit container modes the inner or scalar source mode.
724(define_mode_attr VCOND [(HI "V4HI") (SI "V2SI")
725 (V4HI "V4HI") (V8HI "V4HI")
b7d7d917
TB		 726 (V2SI "V2SI") (V4SI "V2SI")
727 (DI "DI") (V2DI "DI")
728 (V2SF "V2SF") (V4SF "V2SF")
729 (V2DF "DF")])
730
278821f2 731;; 128-bit container modes the inner or scalar source mode.
b7d7d917
TB		 732(define_mode_attr VCONQ [(V8QI "V16QI") (V16QI "V16QI")
733 (V4HI "V8HI") (V8HI "V8HI")
734 (V2SI "V4SI") (V4SI "V4SI")
735 (DI "V2DI") (V2DI "V2DI")
71a11456 736 (V4HF "V8HF") (V8HF "V8HF")
b7d7d917
TB		 737 (V2SF "V2SF") (V4SF "V4SF")
738 (V2DF "V2DF") (SI "V4SI")
739 (HI "V8HI") (QI "V16QI")])
740
43e9d192
IB		 741;; Half modes of all vector modes.
742(define_mode_attr VHALF [(V8QI "V4QI") (V16QI "V8QI")
743 (V4HI "V2HI") (V8HI "V4HI")
744 (V2SI "SI") (V4SI "V2SI")
745 (V2DI "DI") (V2SF "SF")
71a11456
AL		 746 (V4SF "V2SF") (V4HF "V2HF")
747 (V8HF "V4HF") (V2DF "DF")])
43e9d192 748
b1b49824
MC		 749;; Half modes of all vector modes, in lower-case.
750(define_mode_attr Vhalf [(V8QI "v4qi") (V16QI "v8qi")
751 (V4HI "v2hi") (V8HI "v4hi")
752 (V2SI "si") (V4SI "v2si")
753 (V2DI "di") (V2SF "sf")
754 (V4SF "v2sf") (V2DF "df")])
755
43e9d192
IB		 756;; Double modes of vector modes.
757(define_mode_attr VDBL [(V8QI "V16QI") (V4HI "V8HI")
71a11456 758 (V4HF "V8HF")
43e9d192
IB		 759 (V2SI "V4SI") (V2SF "V4SF")
760 (SI "V2SI") (DI "V2DI")
761 (DF "V2DF")])
762
922f9c25
AL		 763;; Register suffix for double-length mode.
764(define_mode_attr Vdtype [(V4HF "8h") (V2SF "4s")])
765
43e9d192
IB		 766;; Double modes of vector modes (lower case).
767(define_mode_attr Vdbl [(V8QI "v16qi") (V4HI "v8hi")
7c369485 768 (V4HF "v8hf")
43e9d192 769 (V2SI "v4si") (V2SF "v4sf")
8b033a8a
SN		 770 (SI "v2si") (DI "v2di")
771 (DF "v2df")])
43e9d192 772
b1b49824
MC		 773;; Modes with double-width elements.
774(define_mode_attr VDBLW [(V8QI "V4HI") (V16QI "V8HI")
775 (V4HI "V2SI") (V8HI "V4SI")
776 (V2SI "DI") (V4SI "V2DI")])
777
43e9d192
IB		 778;; Narrowed modes for VDN.
779(define_mode_attr VNARROWD [(V4HI "V8QI") (V2SI "V4HI")
780 (DI "V2SI")])
781
782;; Narrowed double-modes for VQN (Used for XTN).
783(define_mode_attr VNARROWQ [(V8HI "V8QI") (V4SI "V4HI")
784 (V2DI "V2SI")
785 (DI "SI") (SI "HI")
786 (HI "QI")])
787
788;; Narrowed quad-modes for VQN (Used for XTN2).
789(define_mode_attr VNARROWQ2 [(V8HI "V16QI") (V4SI "V8HI")
790 (V2DI "V4SI")])
791
792;; Register suffix narrowed modes for VQN.
793(define_mode_attr Vntype [(V8HI "8b") (V4SI "4h")
794 (V2DI "2s")])
795
796;; Register suffix narrowed modes for VQN.
797(define_mode_attr V2ntype [(V8HI "16b") (V4SI "8h")
798 (V2DI "4s")])
799
800;; Widened modes of vector modes.
43cacb12
RS		 801(define_mode_attr VWIDE [(V8QI "V8HI") (V4HI "V4SI")
802 (V2SI "V2DI") (V16QI "V8HI")
803 (V8HI "V4SI") (V4SI "V2DI")
804 (HI "SI") (SI "DI")
805 (V8HF "V4SF") (V4SF "V2DF")
806 (V4HF "V4SF") (V2SF "V2DF")
807 (VNx8HF "VNx4SF") (VNx4SF "VNx2DF")
808 (VNx16QI "VNx8HI") (VNx8HI "VNx4SI")
809 (VNx4SI "VNx2DI")
810 (VNx16BI "VNx8BI") (VNx8BI "VNx4BI")
811 (VNx4BI "VNx2BI")])
812
813;; Predicate mode associated with VWIDE.
814(define_mode_attr VWIDE_PRED [(VNx8HF "VNx4BI") (VNx4SF "VNx2BI")])
43e9d192 815
03873eb9 816;; Widened modes of vector modes, lowercase
43cacb12
RS		 817(define_mode_attr Vwide [(V2SF "v2df") (V4HF "v4sf")
818 (VNx16QI "vnx8hi") (VNx8HI "vnx4si")
819 (VNx4SI "vnx2di")
820 (VNx8HF "vnx4sf") (VNx4SF "vnx2df")
821 (VNx16BI "vnx8bi") (VNx8BI "vnx4bi")
822 (VNx4BI "vnx2bi")])
03873eb9
AL		 823
824;; Widened mode register suffixes for VD_BHSI/VQW/VQ_HSF.
43e9d192
IB		 825(define_mode_attr Vwtype [(V8QI "8h") (V4HI "4s")
826 (V2SI "2d") (V16QI "8h")
03873eb9
AL		 827 (V8HI "4s") (V4SI "2d")
828 (V8HF "4s") (V4SF "2d")])
43e9d192 829
43cacb12
RS		 830;; SVE vector after widening
831(define_mode_attr Vewtype [(VNx16QI "h")
832 (VNx8HI "s") (VNx8HF "s")
833 (VNx4SI "d") (VNx4SF "d")])
834
43e9d192
IB		 835;; Widened mode register suffixes for VDW/VQW.
836(define_mode_attr Vmwtype [(V8QI ".8h") (V4HI ".4s")
837 (V2SI ".2d") (V16QI ".8h")
838 (V8HI ".4s") (V4SI ".2d")
922f9c25 839 (V4HF ".4s") (V2SF ".2d")
43e9d192
IB		 840 (SI "") (HI "")])
841
03873eb9 842;; Lower part register suffixes for VQW/VQ_HSF.
43e9d192 843(define_mode_attr Vhalftype [(V16QI "8b") (V8HI "4h")
03873eb9
AL		 844 (V4SI "2s") (V8HF "4h")
845 (V4SF "2s")])
43e9d192
IB		 846
847;; Define corresponding core/FP element mode for each vector mode.
43cacb12
RS		 848(define_mode_attr vw [(V8QI "w") (V16QI "w") (VNx16QI "w")
849 (V4HI "w") (V8HI "w") (VNx8HI "w")
850 (V2SI "w") (V4SI "w") (VNx4SI "w")
851 (DI "x") (V2DI "x") (VNx2DI "x")
852 (VNx8HF "h")
853 (V2SF "s") (V4SF "s") (VNx4SF "s")
854 (V2DF "d") (VNx2DF "d")])
43e9d192 855
66adb8eb
JG		 856;; Corresponding core element mode for each vector mode. This is a
857;; variation on <vw> mapping FP modes to GP regs.
43cacb12
RS		 858(define_mode_attr vwcore [(V8QI "w") (V16QI "w") (VNx16QI "w")
859 (V4HI "w") (V8HI "w") (VNx8HI "w")
860 (V2SI "w") (V4SI "w") (VNx4SI "w")
861 (DI "x") (V2DI "x") (VNx2DI "x")
862 (V4HF "w") (V8HF "w") (VNx8HF "w")
863 (V2SF "w") (V4SF "w") (VNx4SF "w")
864 (V2DF "x") (VNx2DF "x")])
66adb8eb 865
43e9d192
IB		 866;; Double vector types for ALLX.
867(define_mode_attr Vallxd [(QI "8b") (HI "4h") (SI "2s")])
868
5f565314
RS		 869;; Mode with floating-point values replaced by like-sized integers.
870(define_mode_attr V_INT_EQUIV [(V8QI "V8QI") (V16QI "V16QI")
871 (V4HI "V4HI") (V8HI "V8HI")
872 (V2SI "V2SI") (V4SI "V4SI")
873 (DI "DI") (V2DI "V2DI")
874 (V4HF "V4HI") (V8HF "V8HI")
875 (V2SF "V2SI") (V4SF "V4SI")
43cacb12 876 (DF "DI") (V2DF "V2DI")
dfe1da23
JW		 877 (SF "SI") (SI "SI")
878 (HF "HI")
43cacb12
RS		 879 (VNx16QI "VNx16QI")
880 (VNx8HI "VNx8HI") (VNx8HF "VNx8HI")
881 (VNx4SI "VNx4SI") (VNx4SF "VNx4SI")
882 (VNx2DI "VNx2DI") (VNx2DF "VNx2DI")
883])
5f565314
RS		 884
885;; Lower case mode with floating-point values replaced by like-sized integers.
886(define_mode_attr v_int_equiv [(V8QI "v8qi") (V16QI "v16qi")
887 (V4HI "v4hi") (V8HI "v8hi")
888 (V2SI "v2si") (V4SI "v4si")
889 (DI "di") (V2DI "v2di")
890 (V4HF "v4hi") (V8HF "v8hi")
891 (V2SF "v2si") (V4SF "v4si")
43cacb12
RS		 892 (DF "di") (V2DF "v2di")
893 (SF "si")
894 (VNx16QI "vnx16qi")
895 (VNx8HI "vnx8hi") (VNx8HF "vnx8hi")
896 (VNx4SI "vnx4si") (VNx4SF "vnx4si")
897 (VNx2DI "vnx2di") (VNx2DF "vnx2di")
898])
899
900;; Floating-point equivalent of selected modes.
901(define_mode_attr V_FP_EQUIV [(VNx4SI "VNx4SF") (VNx4SF "VNx4SF")
902 (VNx2DI "VNx2DF") (VNx2DF "VNx2DF")])
903(define_mode_attr v_fp_equiv [(VNx4SI "vnx4sf") (VNx4SF "vnx4sf")
904 (VNx2DI "vnx2df") (VNx2DF "vnx2df")])
70c67693 905
6c553b76
BC		 906;; Mode for vector conditional operations where the comparison has
907;; different type from the lhs.
908(define_mode_attr V_cmp_mixed [(V2SI "V2SF") (V4SI "V4SF")
909 (V2DI "V2DF") (V2SF "V2SI")
910 (V4SF "V4SI") (V2DF "V2DI")])
911
912(define_mode_attr v_cmp_mixed [(V2SI "v2sf") (V4SI "v4sf")
913 (V2DI "v2df") (V2SF "v2si")
914 (V4SF "v4si") (V2DF "v2di")])
915
cb23a30c
JG		 916;; Lower case element modes (as used in shift immediate patterns).
917(define_mode_attr ve_mode [(V8QI "qi") (V16QI "qi")
918 (V4HI "hi") (V8HI "hi")
919 (V2SI "si") (V4SI "si")
920 (DI "di") (V2DI "di")
921 (QI "qi") (HI "hi")
922 (SI "si")])
923
43e9d192
IB		 924;; Vm for lane instructions is restricted to FP_LO_REGS.
925(define_mode_attr vwx [(V4HI "x") (V8HI "x") (HI "x")
926 (V2SI "w") (V4SI "w") (SI "w")])
927
928(define_mode_attr Vendreg [(OI "T") (CI "U") (XI "V")])
929
97755701
AL		 930;; This is both the number of Q-Registers needed to hold the corresponding
931;; opaque large integer mode, and the number of elements touched by the
932;; ld..._lane and st..._lane operations.
43e9d192
IB		 933(define_mode_attr nregs [(OI "2") (CI "3") (XI "4")])
934
0462169c
SN		 935;; Mode for atomic operation suffixes
936(define_mode_attr atomic_sfx
937 [(QI "b") (HI "h") (SI "") (DI "")])
938
3f598afe 939(define_mode_attr fcvt_target [(V2DF "v2di") (V4SF "v4si") (V2SF "v2si")
2644d4d9 940 (V2DI "v2df") (V4SI "v4sf") (V2SI "v2sf")
daef0a8c
JW		 941 (SF "si") (DF "di") (SI "sf") (DI "df")
942 (V4HF "v4hi") (V8HF "v8hi") (V4HI "v4hf")
68ad28c3 943 (V8HI "v8hf") (HF "hi") (HI "hf")])
3f598afe 944(define_mode_attr FCVT_TARGET [(V2DF "V2DI") (V4SF "V4SI") (V2SF "V2SI")
2644d4d9 945 (V2DI "V2DF") (V4SI "V4SF") (V2SI "V2SF")
daef0a8c
JW		 946 (SF "SI") (DF "DI") (SI "SF") (DI "DF")
947 (V4HF "V4HI") (V8HF "V8HI") (V4HI "V4HF")
68ad28c3 948 (V8HI "V8HF") (HF "HI") (HI "HF")])
3f598afe 949
0d35c5c2
VP		 950
951;; for the inequal width integer to fp conversions
d7f33f07
JW		 952(define_mode_attr fcvt_iesize [(HF "di") (SF "di") (DF "si")])
953(define_mode_attr FCVT_IESIZE [(HF "DI") (SF "DI") (DF "SI")])
42fc9a7f 954
91bd4114
JG		 955(define_mode_attr VSWAP_WIDTH [(V8QI "V16QI") (V16QI "V8QI")
956 (V4HI "V8HI") (V8HI "V4HI")
957 (V2SI "V4SI") (V4SI "V2SI")
958 (DI "V2DI") (V2DI "DI")
959 (V2SF "V4SF") (V4SF "V2SF")
862abc04 960 (V4HF "V8HF") (V8HF "V4HF")
91bd4114
JG		 961 (DF "V2DF") (V2DF "DF")])
962
963(define_mode_attr vswap_width_name [(V8QI "to_128") (V16QI "to_64")
964 (V4HI "to_128") (V8HI "to_64")
965 (V2SI "to_128") (V4SI "to_64")
966 (DI "to_128") (V2DI "to_64")
862abc04 967 (V4HF "to_128") (V8HF "to_64")
91bd4114
JG		 968 (V2SF "to_128") (V4SF "to_64")
969 (DF "to_128") (V2DF "to_64")])
970
779aea46 971;; For certain vector-by-element multiplication instructions we must
6d06971d 972;; constrain the 16-bit cases to use only V0-V15. This is covered by
779aea46
JG		 973;; the 'x' constraint. All other modes may use the 'w' constraint.
974(define_mode_attr h_con [(V2SI "w") (V4SI "w")
975 (V4HI "x") (V8HI "x")
6d06971d 976 (V4HF "x") (V8HF "x")
779aea46
JG		 977 (V2SF "w") (V4SF "w")
978 (V2DF "w") (DF "w")])
979
980;; Defined to 'f' for types whose element type is a float type.
981(define_mode_attr f [(V8QI "") (V16QI "")
982 (V4HI "") (V8HI "")
983 (V2SI "") (V4SI "")
984 (DI "") (V2DI "")
ab2e8f01 985 (V4HF "f") (V8HF "f")
779aea46
JG		 986 (V2SF "f") (V4SF "f")
987 (V2DF "f") (DF "f")])
988
0f686aa9
JG		 989;; Defined to '_fp' for types whose element type is a float type.
990(define_mode_attr fp [(V8QI "") (V16QI "")
991 (V4HI "") (V8HI "")
992 (V2SI "") (V4SI "")
993 (DI "") (V2DI "")
ab2e8f01 994 (V4HF "_fp") (V8HF "_fp")
0f686aa9
JG		 995 (V2SF "_fp") (V4SF "_fp")
996 (V2DF "_fp") (DF "_fp")
997 (SF "_fp")])
998
a9e66678
JG		 999;; Defined to '_q' for 128-bit types.
1000(define_mode_attr q [(V8QI "") (V16QI "_q")
0f686aa9
JG		 1001 (V4HI "") (V8HI "_q")
1002 (V2SI "") (V4SI "_q")
1003 (DI "") (V2DI "_q")
71a11456 1004 (V4HF "") (V8HF "_q")
0f686aa9
JG		 1005 (V2SF "") (V4SF "_q")
1006 (V2DF "_q")
d7f33f07 1007 (QI "") (HI "") (SI "") (DI "") (HF "") (SF "") (DF "")])
a9e66678 1008
92835317
TB		 1009(define_mode_attr vp [(V8QI "v") (V16QI "v")
1010 (V4HI "v") (V8HI "v")
1011 (V2SI "p") (V4SI "v")
703bbcdf
JW		 1012 (V2DI "p") (V2DF "p")
1013 (V2SF "p") (V4SF "v")
1014 (V4HF "v") (V8HF "v")])
92835317 1015
5e32e83b
JW		 1016(define_mode_attr vsi2qi [(V2SI "v8qi") (V4SI "v16qi")])
1017(define_mode_attr VSI2QI [(V2SI "V8QI") (V4SI "V16QI")])
1018
7a08d813
TC		 1019
1020;; Register suffix for DOTPROD input types from the return type.
1021(define_mode_attr Vdottype [(V2SI "8b") (V4SI "16b")])
1022
cd78b3dd 1023;; Sum of lengths of instructions needed to move vector registers of a mode.
668046d1
DS		 1024(define_mode_attr insn_count [(OI "8") (CI "12") (XI "16")])
1025
1b1e81f8
JW		 1026;; -fpic small model GOT reloc modifers: gotpage_lo15/lo14 for ILP64/32.
1027;; No need of iterator for -fPIC as it use got_lo12 for both modes.
1028(define_mode_attr got_modifier [(SI "gotpage_lo14") (DI "gotpage_lo15")])
1029
27086ea3
MC		 1030;; Width of 2nd and 3rd arguments to fp16 vector multiply add/sub
1031(define_mode_attr VFMLA_W [(V2SF "V4HF") (V4SF "V8HF")])
1032
1033(define_mode_attr VFMLA_SEL_W [(V2SF "V2HF") (V4SF "V4HF")])
1034
1035(define_mode_attr f16quad [(V2SF "") (V4SF "q")])
1036
1037(define_code_attr f16mac [(plus "a") (minus "s")])
1038
9f4cbab8
RS		 1039;; The number of subvectors in an SVE_STRUCT.
1040(define_mode_attr vector_count [(VNx32QI "2") (VNx16HI "2")
1041 (VNx8SI "2") (VNx4DI "2")
1042 (VNx16HF "2") (VNx8SF "2") (VNx4DF "2")
1043 (VNx48QI "3") (VNx24HI "3")
1044 (VNx12SI "3") (VNx6DI "3")
1045 (VNx24HF "3") (VNx12SF "3") (VNx6DF "3")
1046 (VNx64QI "4") (VNx32HI "4")
1047 (VNx16SI "4") (VNx8DI "4")
1048 (VNx32HF "4") (VNx16SF "4") (VNx8DF "4")])
1049
1050;; The number of instruction bytes needed for an SVE_STRUCT move. This is
1051;; equal to vector_count * 4.
1052(define_mode_attr insn_length [(VNx32QI "8") (VNx16HI "8")
1053 (VNx8SI "8") (VNx4DI "8")
1054 (VNx16HF "8") (VNx8SF "8") (VNx4DF "8")
1055 (VNx48QI "12") (VNx24HI "12")
1056 (VNx12SI "12") (VNx6DI "12")
1057 (VNx24HF "12") (VNx12SF "12") (VNx6DF "12")
1058 (VNx64QI "16") (VNx32HI "16")
1059 (VNx16SI "16") (VNx8DI "16")
1060 (VNx32HF "16") (VNx16SF "16") (VNx8DF "16")])
1061
1062;; The type of a subvector in an SVE_STRUCT.
1063(define_mode_attr VSINGLE [(VNx32QI "VNx16QI")
1064 (VNx16HI "VNx8HI") (VNx16HF "VNx8HF")
1065 (VNx8SI "VNx4SI") (VNx8SF "VNx4SF")
1066 (VNx4DI "VNx2DI") (VNx4DF "VNx2DF")
1067 (VNx48QI "VNx16QI")
1068 (VNx24HI "VNx8HI") (VNx24HF "VNx8HF")
1069 (VNx12SI "VNx4SI") (VNx12SF "VNx4SF")
1070 (VNx6DI "VNx2DI") (VNx6DF "VNx2DF")
1071 (VNx64QI "VNx16QI")
1072 (VNx32HI "VNx8HI") (VNx32HF "VNx8HF")
1073 (VNx16SI "VNx4SI") (VNx16SF "VNx4SF")
1074 (VNx8DI "VNx2DI") (VNx8DF "VNx2DF")])
1075
1076;; ...and again in lower case.
1077(define_mode_attr vsingle [(VNx32QI "vnx16qi")
1078 (VNx16HI "vnx8hi") (VNx16HF "vnx8hf")
1079 (VNx8SI "vnx4si") (VNx8SF "vnx4sf")
1080 (VNx4DI "vnx2di") (VNx4DF "vnx2df")
1081 (VNx48QI "vnx16qi")
1082 (VNx24HI "vnx8hi") (VNx24HF "vnx8hf")
1083 (VNx12SI "vnx4si") (VNx12SF "vnx4sf")
1084 (VNx6DI "vnx2di") (VNx6DF "vnx2df")
1085 (VNx64QI "vnx16qi")
1086 (VNx32HI "vnx8hi") (VNx32HF "vnx8hf")
1087 (VNx16SI "vnx4si") (VNx16SF "vnx4sf")
1088 (VNx8DI "vnx2di") (VNx8DF "vnx2df")])
1089
1090;; The predicate mode associated with an SVE data mode. For structure modes
1091;; this is equivalent to the <VPRED> of the subvector mode.
43cacb12
RS		 1092(define_mode_attr VPRED [(VNx16QI "VNx16BI")
1093 (VNx8HI "VNx8BI") (VNx8HF "VNx8BI")
1094 (VNx4SI "VNx4BI") (VNx4SF "VNx4BI")
9f4cbab8
RS		 1095 (VNx2DI "VNx2BI") (VNx2DF "VNx2BI")
1096 (VNx32QI "VNx16BI")
1097 (VNx16HI "VNx8BI") (VNx16HF "VNx8BI")
1098 (VNx8SI "VNx4BI") (VNx8SF "VNx4BI")
1099 (VNx4DI "VNx2BI") (VNx4DF "VNx2BI")
1100 (VNx48QI "VNx16BI")
1101 (VNx24HI "VNx8BI") (VNx24HF "VNx8BI")
1102 (VNx12SI "VNx4BI") (VNx12SF "VNx4BI")
1103 (VNx6DI "VNx2BI") (VNx6DF "VNx2BI")
1104 (VNx64QI "VNx16BI")
1105 (VNx32HI "VNx8BI") (VNx32HF "VNx8BI")
1106 (VNx16SI "VNx4BI") (VNx16SF "VNx4BI")
1107 (VNx8DI "VNx2BI") (VNx8DF "VNx2BI")])
43cacb12
RS		 1108
1109;; ...and again in lower case.
1110(define_mode_attr vpred [(VNx16QI "vnx16bi")
1111 (VNx8HI "vnx8bi") (VNx8HF "vnx8bi")
1112 (VNx4SI "vnx4bi") (VNx4SF "vnx4bi")
9f4cbab8
RS		 1113 (VNx2DI "vnx2bi") (VNx2DF "vnx2bi")
1114 (VNx32QI "vnx16bi")
1115 (VNx16HI "vnx8bi") (VNx16HF "vnx8bi")
1116 (VNx8SI "vnx4bi") (VNx8SF "vnx4bi")
1117 (VNx4DI "vnx2bi") (VNx4DF "vnx2bi")
1118 (VNx48QI "vnx16bi")
1119 (VNx24HI "vnx8bi") (VNx24HF "vnx8bi")
1120 (VNx12SI "vnx4bi") (VNx12SF "vnx4bi")
1121 (VNx6DI "vnx2bi") (VNx6DF "vnx2bi")
1122 (VNx64QI "vnx16bi")
1123 (VNx32HI "vnx8bi") (VNx32HF "vnx4bi")
1124 (VNx16SI "vnx4bi") (VNx16SF "vnx4bi")
1125 (VNx8DI "vnx2bi") (VNx8DF "vnx2bi")])
43cacb12 1126
43e9d192
IB		 1127;; -------------------------------------------------------------------
1128;; Code Iterators
1129;; -------------------------------------------------------------------
1130
1131;; This code iterator allows the various shifts supported on the core
1132(define_code_iterator SHIFT [ashift ashiftrt lshiftrt rotatert])
1133
1134;; This code iterator allows the shifts supported in arithmetic instructions
1135(define_code_iterator ASHIFT [ashift ashiftrt lshiftrt])
1136
1137;; Code iterator for logical operations
1138(define_code_iterator LOGICAL [and ior xor])
1139
43cacb12
RS		 1140;; LOGICAL without AND.
1141(define_code_iterator LOGICAL_OR [ior xor])
1142
84be6032
AL		 1143;; Code iterator for logical operations whose :nlogical works on SIMD registers.
1144(define_code_iterator NLOGICAL [and ior])
1145
3204ac98
KT		 1146;; Code iterator for unary negate and bitwise complement.
1147(define_code_iterator NEG_NOT [neg not])
1148
43e9d192
IB		 1149;; Code iterator for sign/zero extension
1150(define_code_iterator ANY_EXTEND [sign_extend zero_extend])
1151
1152;; All division operations (signed/unsigned)
1153(define_code_iterator ANY_DIV [div udiv])
1154
1155;; Code iterator for sign/zero extraction
1156(define_code_iterator ANY_EXTRACT [sign_extract zero_extract])
1157
1158;; Code iterator for equality comparisons
1159(define_code_iterator EQL [eq ne])
1160
1161;; Code iterator for less-than and greater/equal-to
1162(define_code_iterator LTGE [lt ge])
1163
1164;; Iterator for __sync_<op> operations that where the operation can be
1165;; represented directly RTL. This is all of the sync operations bar
1166;; nand.
0462169c 1167(define_code_iterator atomic_op [plus minus ior xor and])
43e9d192
IB		 1168
1169;; Iterator for integer conversions
1170(define_code_iterator FIXUORS [fix unsigned_fix])
1171
1709ff9b
JG		 1172;; Iterator for float conversions
1173(define_code_iterator FLOATUORS [float unsigned_float])
1174
43e9d192
IB		 1175;; Code iterator for variants of vector max and min.
1176(define_code_iterator MAXMIN [smax smin umax umin])
1177
998eaf97
JG		 1178(define_code_iterator FMAXMIN [smax smin])
1179
43e9d192
IB		 1180;; Code iterator for variants of vector max and min.
1181(define_code_iterator ADDSUB [plus minus])
1182
1183;; Code iterator for variants of vector saturating binary ops.
1184(define_code_iterator BINQOPS [ss_plus us_plus ss_minus us_minus])
1185
1186;; Code iterator for variants of vector saturating unary ops.
1187(define_code_iterator UNQOPS [ss_neg ss_abs])
1188
1189;; Code iterator for signed variants of vector saturating binary ops.
1190(define_code_iterator SBINQOPS [ss_plus ss_minus])
1191
889b9412
JG		 1192;; Comparison operators for <F>CM.
1193(define_code_iterator COMPARISONS [lt le eq ge gt])
1194
1195;; Unsigned comparison operators.
1196(define_code_iterator UCOMPARISONS [ltu leu geu gtu])
1197
75dd5ace
JG		 1198;; Unsigned comparison operators.
1199(define_code_iterator FAC_COMPARISONS [lt le ge gt])
1200
43cacb12
RS		 1201;; SVE integer unary operations.
1202(define_code_iterator SVE_INT_UNARY [neg not popcount])
1203
1204;; SVE floating-point unary operations.
1205(define_code_iterator SVE_FP_UNARY [neg abs sqrt])
1206
6c4fd4a9 1207(define_code_iterator SVE_INT_BINARY [plus minus mult smax umax smin umin
9d4ac06e
RS		 1208 and ior xor])
1209
0d2b3bca
RS		 1210(define_code_iterator SVE_INT_BINARY_REV [minus])
1211
c38f7319
RS		 1212(define_code_iterator SVE_INT_BINARY_SD [div udiv])
1213
f22d7973
RS		 1214;; SVE integer comparisons.
1215(define_code_iterator SVE_INT_CMP [lt le eq ne ge gt ltu leu geu gtu])
1216
1217;; SVE floating-point comparisons.
1218(define_code_iterator SVE_FP_CMP [lt le eq ne ge gt])
1219
43e9d192
IB		 1220;; -------------------------------------------------------------------
1221;; Code Attributes
1222;; -------------------------------------------------------------------
1223;; Map rtl objects to optab names
1224(define_code_attr optab [(ashift "ashl")
1225 (ashiftrt "ashr")
1226 (lshiftrt "lshr")
1227 (rotatert "rotr")
1228 (sign_extend "extend")
1229 (zero_extend "zero_extend")
1230 (sign_extract "extv")
1231 (zero_extract "extzv")
384be29f
JG		 1232 (fix "fix")
1233 (unsigned_fix "fixuns")
1709ff9b
JG		 1234 (float "float")
1235 (unsigned_float "floatuns")
43cacb12 1236 (popcount "popcount")
43e9d192
IB		 1237 (and "and")
1238 (ior "ior")
1239 (xor "xor")
1240 (not "one_cmpl")
1241 (neg "neg")
1242 (plus "add")
1243 (minus "sub")
6c4fd4a9 1244 (mult "mul")
c38f7319
RS		 1245 (div "div")
1246 (udiv "udiv")
43e9d192
IB		 1247 (ss_plus "qadd")
1248 (us_plus "qadd")
1249 (ss_minus "qsub")
1250 (us_minus "qsub")
1251 (ss_neg "qneg")
1252 (ss_abs "qabs")
43cacb12
RS		 1253 (smin "smin")
1254 (smax "smax")
1255 (umin "umin")
1256 (umax "umax")
43e9d192
IB		 1257 (eq "eq")
1258 (ne "ne")
1259 (lt "lt")
889b9412
JG		 1260 (ge "ge")
1261 (le "le")
1262 (gt "gt")
1263 (ltu "ltu")
1264 (leu "leu")
1265 (geu "geu")
43cacb12
RS		 1266 (gtu "gtu")
1267 (abs "abs")
1268 (sqrt "sqrt")])
889b9412
JG		 1269
1270;; For comparison operators we use the FCM* and CM* instructions.
1271;; As there are no CMLE or CMLT instructions which act on 3 vector
1272;; operands, we must use CMGE or CMGT and swap the order of the
1273;; source operands.
1274
1275(define_code_attr n_optab [(lt "gt") (le "ge") (eq "eq") (ge "ge") (gt "gt")
1276 (ltu "hi") (leu "hs") (geu "hs") (gtu "hi")])
1277(define_code_attr cmp_1 [(lt "2") (le "2") (eq "1") (ge "1") (gt "1")
1278 (ltu "2") (leu "2") (geu "1") (gtu "1")])
1279(define_code_attr cmp_2 [(lt "1") (le "1") (eq "2") (ge "2") (gt "2")
1280 (ltu "1") (leu "1") (geu "2") (gtu "2")])
1281
1282(define_code_attr CMP [(lt "LT") (le "LE") (eq "EQ") (ge "GE") (gt "GT")
714e1b3b
KT		 1283 (ltu "LTU") (leu "LEU") (ne "NE") (geu "GEU")
1284 (gtu "GTU")])
43e9d192 1285
f22d7973
RS		 1286;; The AArch64 condition associated with an rtl comparison code.
1287(define_code_attr cmp_op [(lt "lt")
1288 (le "le")
1289 (eq "eq")
1290 (ne "ne")
1291 (ge "ge")
1292 (gt "gt")
1293 (ltu "lo")
1294 (leu "ls")
1295 (geu "hs")
1296 (gtu "hi")])
1297
384be29f
JG		 1298(define_code_attr fix_trunc_optab [(fix "fix_trunc")
1299 (unsigned_fix "fixuns_trunc")])
1300
43e9d192
IB		 1301;; Optab prefix for sign/zero-extending operations
1302(define_code_attr su_optab [(sign_extend "") (zero_extend "u")
1303 (div "") (udiv "u")
1304 (fix "") (unsigned_fix "u")
1709ff9b 1305 (float "s") (unsigned_float "u")
43e9d192
IB		 1306 (ss_plus "s") (us_plus "u")
1307 (ss_minus "s") (us_minus "u")])
1308
1309;; Similar for the instruction mnemonics
1310(define_code_attr shift [(ashift "lsl") (ashiftrt "asr")
1311 (lshiftrt "lsr") (rotatert "ror")])
1312
1313;; Map shift operators onto underlying bit-field instructions
1314(define_code_attr bfshift [(ashift "ubfiz") (ashiftrt "sbfx")
1315 (lshiftrt "ubfx") (rotatert "extr")])
1316
1317;; Logical operator instruction mnemonics
1318(define_code_attr logical [(and "and") (ior "orr") (xor "eor")])
1319
3204ac98
KT		 1320;; Operation names for negate and bitwise complement.
1321(define_code_attr neg_not_op [(neg "neg") (not "not")])
1322
43cacb12 1323;; Similar, but when the second operand is inverted.
43e9d192
IB		 1324(define_code_attr nlogical [(and "bic") (ior "orn") (xor "eon")])
1325
43cacb12
RS		 1326;; Similar, but when both operands are inverted.
1327(define_code_attr logical_nn [(and "nor") (ior "nand")])
1328
43e9d192
IB		 1329;; Sign- or zero-extending data-op
1330(define_code_attr su [(sign_extend "s") (zero_extend "u")
1331 (sign_extract "s") (zero_extract "u")
1332 (fix "s") (unsigned_fix "u")
998eaf97
JG		 1333 (div "s") (udiv "u")
1334 (smax "s") (umax "u")
1335 (smin "s") (umin "u")])
43e9d192 1336
43cacb12
RS		 1337;; Whether a shift is left or right.
1338(define_code_attr lr [(ashift "l") (ashiftrt "r") (lshiftrt "r")])
1339
096e8448
JW		 1340;; Emit conditional branch instructions.
1341(define_code_attr bcond [(eq "beq") (ne "bne") (lt "bne") (ge "beq")])
1342
43e9d192
IB		 1343;; Emit cbz/cbnz depending on comparison type.
1344(define_code_attr cbz [(eq "cbz") (ne "cbnz") (lt "cbnz") (ge "cbz")])
1345
973d2e01
TP		 1346;; Emit inverted cbz/cbnz depending on comparison type.
1347(define_code_attr inv_cb [(eq "cbnz") (ne "cbz") (lt "cbz") (ge "cbnz")])
1348
43e9d192
IB		 1349;; Emit tbz/tbnz depending on comparison type.
1350(define_code_attr tbz [(eq "tbz") (ne "tbnz") (lt "tbnz") (ge "tbz")])
1351
973d2e01
TP		 1352;; Emit inverted tbz/tbnz depending on comparison type.
1353(define_code_attr inv_tb [(eq "tbnz") (ne "tbz") (lt "tbz") (ge "tbnz")])
1354
43e9d192 1355;; Max/min attributes.
998eaf97
JG		 1356(define_code_attr maxmin [(smax "max")
1357 (smin "min")
1358 (umax "max")
1359 (umin "min")])
43e9d192
IB		 1360
1361;; MLA/MLS attributes.
1362(define_code_attr as [(ss_plus "a") (ss_minus "s")])
1363
0462169c
SN		 1364;; Atomic operations
1365(define_code_attr atomic_optab
1366 [(ior "or") (xor "xor") (and "and") (plus "add") (minus "sub")])
1367
1368(define_code_attr atomic_op_operand
1369 [(ior "aarch64_logical_operand")
1370 (xor "aarch64_logical_operand")
1371 (and "aarch64_logical_operand")
1372 (plus "aarch64_plus_operand")
1373 (minus "aarch64_plus_operand")])
43e9d192 1374
356c32e2
MW		 1375;; Constants acceptable for atomic operations.
1376;; This definition must appear in this file before the iterators it refers to.
1377(define_code_attr const_atomic
1378 [(plus "IJ") (minus "IJ")
1379 (xor "<lconst_atomic>") (ior "<lconst_atomic>")
1380 (and "<lconst_atomic>")])
1381
1382;; Attribute to describe constants acceptable in atomic logical operations
1383(define_mode_attr lconst_atomic [(QI "K") (HI "K") (SI "K") (DI "L")])
1384
43cacb12
RS		 1385;; The integer SVE instruction that implements an rtx code.
1386(define_code_attr sve_int_op [(plus "add")
9d4ac06e 1387 (minus "sub")
6c4fd4a9 1388 (mult "mul")
c38f7319
RS		 1389 (div "sdiv")
1390 (udiv "udiv")
43cacb12
RS		 1391 (neg "neg")
1392 (smin "smin")
1393 (smax "smax")
1394 (umin "umin")
1395 (umax "umax")
1396 (and "and")
1397 (ior "orr")
1398 (xor "eor")
1399 (not "not")
1400 (popcount "cnt")])
1401
1402;; The floating-point SVE instruction that implements an rtx code.
1403(define_code_attr sve_fp_op [(plus "fadd")
1404 (neg "fneg")
1405 (abs "fabs")
1406 (sqrt "fsqrt")])
1407
f22d7973
RS		 1408;; The SVE immediate constraint to use for an rtl code.
1409(define_code_attr sve_imm_con [(eq "vsc")
1410 (ne "vsc")
1411 (lt "vsc")
1412 (ge "vsc")
1413 (le "vsc")
1414 (gt "vsc")
1415 (ltu "vsd")
1416 (leu "vsd")
1417 (geu "vsd")
1418 (gtu "vsd")])
1419
43e9d192
IB		 1420;; -------------------------------------------------------------------
1421;; Int Iterators.
1422;; -------------------------------------------------------------------
75add2d0
KT		 1423
1424;; The unspec codes for the SABAL, UABAL AdvancedSIMD instructions.
1425(define_int_iterator ABAL [UNSPEC_SABAL UNSPEC_UABAL])
1426
1427;; The unspec codes for the SABDL2, UABDL2 AdvancedSIMD instructions.
1428(define_int_iterator ABDL2 [UNSPEC_SABDL2 UNSPEC_UABDL2])
1429
1430;; The unspec codes for the SADALP, UADALP AdvancedSIMD instructions.
1431(define_int_iterator ADALP [UNSPEC_SADALP UNSPEC_UADALP])
1432
43e9d192
IB		 1433(define_int_iterator MAXMINV [UNSPEC_UMAXV UNSPEC_UMINV
1434 UNSPEC_SMAXV UNSPEC_SMINV])
1435
998eaf97
JG		 1436(define_int_iterator FMAXMINV [UNSPEC_FMAXV UNSPEC_FMINV
1437 UNSPEC_FMAXNMV UNSPEC_FMINNMV])
43e9d192 1438
898f07b0
RS		 1439(define_int_iterator BITWISEV [UNSPEC_ANDV UNSPEC_IORV UNSPEC_XORV])
1440
43cacb12
RS		 1441(define_int_iterator LOGICALF [UNSPEC_ANDF UNSPEC_IORF UNSPEC_XORF])
1442
43e9d192
IB		 1443(define_int_iterator HADDSUB [UNSPEC_SHADD UNSPEC_UHADD
1444 UNSPEC_SRHADD UNSPEC_URHADD
1445 UNSPEC_SHSUB UNSPEC_UHSUB
1446 UNSPEC_SRHSUB UNSPEC_URHSUB])
1447
7a08d813 1448(define_int_iterator DOTPROD [UNSPEC_SDOT UNSPEC_UDOT])
43e9d192
IB		 1449
1450(define_int_iterator ADDSUBHN [UNSPEC_ADDHN UNSPEC_RADDHN
1451 UNSPEC_SUBHN UNSPEC_RSUBHN])
1452
1453(define_int_iterator ADDSUBHN2 [UNSPEC_ADDHN2 UNSPEC_RADDHN2
1454 UNSPEC_SUBHN2 UNSPEC_RSUBHN2])
1455
1efafef3
TC		 1456(define_int_iterator FMAXMIN_UNS [UNSPEC_FMAX UNSPEC_FMIN
1457 UNSPEC_FMAXNM UNSPEC_FMINNM])
202d0c11 1458
db58fd89
JW		 1459(define_int_iterator PAUTH_LR_SP [UNSPEC_PACISP UNSPEC_AUTISP])
1460
1461(define_int_iterator PAUTH_17_16 [UNSPEC_PACI1716 UNSPEC_AUTI1716])
1462
43e9d192
IB		 1463(define_int_iterator VQDMULH [UNSPEC_SQDMULH UNSPEC_SQRDMULH])
1464
1465(define_int_iterator USSUQADD [UNSPEC_SUQADD UNSPEC_USQADD])
1466
1467(define_int_iterator SUQMOVN [UNSPEC_SQXTN UNSPEC_UQXTN])
1468
1469(define_int_iterator VSHL [UNSPEC_SSHL UNSPEC_USHL
1470 UNSPEC_SRSHL UNSPEC_URSHL])
1471
1472(define_int_iterator VSHLL [UNSPEC_SSHLL UNSPEC_USHLL])
1473
1474(define_int_iterator VQSHL [UNSPEC_SQSHL UNSPEC_UQSHL
1475 UNSPEC_SQRSHL UNSPEC_UQRSHL])
1476
1477(define_int_iterator VSRA [UNSPEC_SSRA UNSPEC_USRA
1478 UNSPEC_SRSRA UNSPEC_URSRA])
1479
1480(define_int_iterator VSLRI [UNSPEC_SSLI UNSPEC_USLI
1481 UNSPEC_SSRI UNSPEC_USRI])
1482
1483
1484(define_int_iterator VRSHR_N [UNSPEC_SRSHR UNSPEC_URSHR])
1485
1486(define_int_iterator VQSHL_N [UNSPEC_SQSHLU UNSPEC_SQSHL UNSPEC_UQSHL])
1487
1488(define_int_iterator VQSHRN_N [UNSPEC_SQSHRUN UNSPEC_SQRSHRUN
1489 UNSPEC_SQSHRN UNSPEC_UQSHRN
1490 UNSPEC_SQRSHRN UNSPEC_UQRSHRN])
1491
57b26d65
MW		 1492(define_int_iterator SQRDMLH_AS [UNSPEC_SQRDMLAH UNSPEC_SQRDMLSH])
1493
cc4d934f
JG		 1494(define_int_iterator PERMUTE [UNSPEC_ZIP1 UNSPEC_ZIP2
1495 UNSPEC_TRN1 UNSPEC_TRN2
1496 UNSPEC_UZP1 UNSPEC_UZP2])
43e9d192 1497
43cacb12
RS		 1498(define_int_iterator OPTAB_PERMUTE [UNSPEC_ZIP1 UNSPEC_ZIP2
1499 UNSPEC_UZP1 UNSPEC_UZP2])
1500
923fcec3
AL		 1501(define_int_iterator REVERSE [UNSPEC_REV64 UNSPEC_REV32 UNSPEC_REV16])
1502
42fc9a7f 1503(define_int_iterator FRINT [UNSPEC_FRINTZ UNSPEC_FRINTP UNSPEC_FRINTM
0659ce6f
JG		 1504 UNSPEC_FRINTN UNSPEC_FRINTI UNSPEC_FRINTX
1505 UNSPEC_FRINTA])
42fc9a7f
JG		 1506
1507(define_int_iterator FCVT [UNSPEC_FRINTZ UNSPEC_FRINTP UNSPEC_FRINTM
ce966824 1508 UNSPEC_FRINTA UNSPEC_FRINTN])
42fc9a7f 1509
3f598afe
JW		 1510(define_int_iterator FCVT_F2FIXED [UNSPEC_FCVTZS UNSPEC_FCVTZU])
1511(define_int_iterator FCVT_FIXED2F [UNSPEC_SCVTF UNSPEC_UCVTF])
1512
0050faf8
JG		 1513(define_int_iterator FRECP [UNSPEC_FRECPE UNSPEC_FRECPX])
1514
5d357f26
KT		 1515(define_int_iterator CRC [UNSPEC_CRC32B UNSPEC_CRC32H UNSPEC_CRC32W
1516 UNSPEC_CRC32X UNSPEC_CRC32CB UNSPEC_CRC32CH
1517 UNSPEC_CRC32CW UNSPEC_CRC32CX])
1518
5a7a4e80
TB		 1519(define_int_iterator CRYPTO_AES [UNSPEC_AESE UNSPEC_AESD])
1520(define_int_iterator CRYPTO_AESMC [UNSPEC_AESMC UNSPEC_AESIMC])
1521
30442682
TB		 1522(define_int_iterator CRYPTO_SHA1 [UNSPEC_SHA1C UNSPEC_SHA1M UNSPEC_SHA1P])
1523
b9cb0a44
TB		 1524(define_int_iterator CRYPTO_SHA256 [UNSPEC_SHA256H UNSPEC_SHA256H2])
1525
27086ea3
MC		 1526(define_int_iterator CRYPTO_SHA512 [UNSPEC_SHA512H UNSPEC_SHA512H2])
1527
1528(define_int_iterator CRYPTO_SM3TT [UNSPEC_SM3TT1A UNSPEC_SM3TT1B
1529 UNSPEC_SM3TT2A UNSPEC_SM3TT2B])
1530
1531(define_int_iterator CRYPTO_SM3PART [UNSPEC_SM3PARTW1 UNSPEC_SM3PARTW2])
1532
1533;; Iterators for fp16 operations
1534
1535(define_int_iterator VFMLA16_LOW [UNSPEC_FMLAL UNSPEC_FMLSL])
1536
1537(define_int_iterator VFMLA16_HIGH [UNSPEC_FMLAL2 UNSPEC_FMLSL2])
1538
43cacb12
RS		 1539(define_int_iterator UNPACK [UNSPEC_UNPACKSHI UNSPEC_UNPACKUHI
1540 UNSPEC_UNPACKSLO UNSPEC_UNPACKULO])
1541
1542(define_int_iterator UNPACK_UNSIGNED [UNSPEC_UNPACKULO UNSPEC_UNPACKUHI])
1543
11e9443f
RS		 1544(define_int_iterator MUL_HIGHPART [UNSPEC_SMUL_HIGHPART UNSPEC_UMUL_HIGHPART])
1545
0d2b3bca 1546(define_int_iterator SVE_COND_FP_BINARY [UNSPEC_COND_ADD UNSPEC_COND_SUB
6c4fd4a9 1547 UNSPEC_COND_MUL UNSPEC_COND_DIV
0d2b3bca
RS		 1548 UNSPEC_COND_MAX UNSPEC_COND_MIN])
1549
6c4fd4a9 1550(define_int_iterator SVE_COND_FP_BINARY_REV [UNSPEC_COND_SUB UNSPEC_COND_DIV])
0972596e 1551
43cacb12
RS		 1552(define_int_iterator SVE_COND_FP_CMP [UNSPEC_COND_LT UNSPEC_COND_LE
1553 UNSPEC_COND_EQ UNSPEC_COND_NE
1554 UNSPEC_COND_GE UNSPEC_COND_GT])
1555
d81cb613
MW		 1556;; Iterators for atomic operations.
1557
1558(define_int_iterator ATOMIC_LDOP
1559 [UNSPECV_ATOMIC_LDOP_OR UNSPECV_ATOMIC_LDOP_BIC
1560 UNSPECV_ATOMIC_LDOP_XOR UNSPECV_ATOMIC_LDOP_PLUS])
1561
1562(define_int_attr atomic_ldop
1563 [(UNSPECV_ATOMIC_LDOP_OR "set") (UNSPECV_ATOMIC_LDOP_BIC "clr")
1564 (UNSPECV_ATOMIC_LDOP_XOR "eor") (UNSPECV_ATOMIC_LDOP_PLUS "add")])
1565
43e9d192
IB		 1566;; -------------------------------------------------------------------
1567;; Int Iterators Attributes.
1568;; -------------------------------------------------------------------
43cacb12
RS		 1569
1570;; The optab associated with an operation. Note that for ANDF, IORF
1571;; and XORF, the optab pattern is not actually defined; we just use this
1572;; name for consistency with the integer patterns.
1573(define_int_attr optab [(UNSPEC_ANDF "and")
1574 (UNSPEC_IORF "ior")
898f07b0
RS		 1575 (UNSPEC_XORF "xor")
1576 (UNSPEC_ANDV "and")
1577 (UNSPEC_IORV "ior")
0972596e
RS		 1578 (UNSPEC_XORV "xor")
1579 (UNSPEC_COND_ADD "add")
0d2b3bca 1580 (UNSPEC_COND_SUB "sub")
6c4fd4a9
RS		 1581 (UNSPEC_COND_MUL "mul")
1582 (UNSPEC_COND_DIV "div")
0d2b3bca
RS		 1583 (UNSPEC_COND_MAX "smax")
1584 (UNSPEC_COND_MIN "smin")])
43cacb12 1585
998eaf97
JG		 1586(define_int_attr maxmin_uns [(UNSPEC_UMAXV "umax")
1587 (UNSPEC_UMINV "umin")
1588 (UNSPEC_SMAXV "smax")
1589 (UNSPEC_SMINV "smin")
1590 (UNSPEC_FMAX "smax_nan")
1591 (UNSPEC_FMAXNMV "smax")
1592 (UNSPEC_FMAXV "smax_nan")
1593 (UNSPEC_FMIN "smin_nan")
1594 (UNSPEC_FMINNMV "smin")
1efafef3
TC		 1595 (UNSPEC_FMINV "smin_nan")
1596 (UNSPEC_FMAXNM "fmax")
1597 (UNSPEC_FMINNM "fmin")])
998eaf97
JG		 1598
1599(define_int_attr maxmin_uns_op [(UNSPEC_UMAXV "umax")
1600 (UNSPEC_UMINV "umin")
1601 (UNSPEC_SMAXV "smax")
1602 (UNSPEC_SMINV "smin")
1603 (UNSPEC_FMAX "fmax")
1604 (UNSPEC_FMAXNMV "fmaxnm")
1605 (UNSPEC_FMAXV "fmax")
1606 (UNSPEC_FMIN "fmin")
1607 (UNSPEC_FMINNMV "fminnm")
1efafef3
TC		 1608 (UNSPEC_FMINV "fmin")
1609 (UNSPEC_FMAXNM "fmaxnm")
1610 (UNSPEC_FMINNM "fminnm")])
202d0c11 1611
898f07b0
RS		 1612(define_int_attr bit_reduc_op [(UNSPEC_ANDV "andv")
1613 (UNSPEC_IORV "orv")
1614 (UNSPEC_XORV "eorv")])
1615
43cacb12
RS		 1616;; The SVE logical instruction that implements an unspec.
1617(define_int_attr logicalf_op [(UNSPEC_ANDF "and")
1618 (UNSPEC_IORF "orr")
1619 (UNSPEC_XORF "eor")])
1620
1621;; "s" for signed operations and "u" for unsigned ones.
1622(define_int_attr su [(UNSPEC_UNPACKSHI "s")
1623 (UNSPEC_UNPACKUHI "u")
1624 (UNSPEC_UNPACKSLO "s")
11e9443f
RS		 1625 (UNSPEC_UNPACKULO "u")
1626 (UNSPEC_SMUL_HIGHPART "s")
1627 (UNSPEC_UMUL_HIGHPART "u")])
43cacb12 1628
43e9d192
IB		 1629(define_int_attr sur [(UNSPEC_SHADD "s") (UNSPEC_UHADD "u")
1630 (UNSPEC_SRHADD "sr") (UNSPEC_URHADD "ur")
1631 (UNSPEC_SHSUB "s") (UNSPEC_UHSUB "u")
1632 (UNSPEC_SRHSUB "sr") (UNSPEC_URHSUB "ur")
1633 (UNSPEC_ADDHN "") (UNSPEC_RADDHN "r")
75add2d0
KT		 1634 (UNSPEC_SABAL "s") (UNSPEC_UABAL "u")
1635 (UNSPEC_SABDL2 "s") (UNSPEC_UABDL2 "u")
1636 (UNSPEC_SADALP "s") (UNSPEC_UADALP "u")
43e9d192
IB		 1637 (UNSPEC_SUBHN "") (UNSPEC_RSUBHN "r")
1638 (UNSPEC_ADDHN2 "") (UNSPEC_RADDHN2 "r")
1639 (UNSPEC_SUBHN2 "") (UNSPEC_RSUBHN2 "r")
1640 (UNSPEC_SQXTN "s") (UNSPEC_UQXTN "u")
1641 (UNSPEC_USQADD "us") (UNSPEC_SUQADD "su")
1642 (UNSPEC_SSLI "s") (UNSPEC_USLI "u")
1643 (UNSPEC_SSRI "s") (UNSPEC_USRI "u")
1644 (UNSPEC_USRA "u") (UNSPEC_SSRA "s")
1645 (UNSPEC_URSRA "ur") (UNSPEC_SRSRA "sr")
1646 (UNSPEC_URSHR "ur") (UNSPEC_SRSHR "sr")
1647 (UNSPEC_SQSHLU "s") (UNSPEC_SQSHL "s")
1648 (UNSPEC_UQSHL "u")
1649 (UNSPEC_SQSHRUN "s") (UNSPEC_SQRSHRUN "s")
1650 (UNSPEC_SQSHRN "s") (UNSPEC_UQSHRN "u")
1651 (UNSPEC_SQRSHRN "s") (UNSPEC_UQRSHRN "u")
1652 (UNSPEC_USHL "u") (UNSPEC_SSHL "s")
1653 (UNSPEC_USHLL "u") (UNSPEC_SSHLL "s")
1654 (UNSPEC_URSHL "ur") (UNSPEC_SRSHL "sr")
1655 (UNSPEC_UQRSHL "u") (UNSPEC_SQRSHL "s")
7a08d813 1656 (UNSPEC_SDOT "s") (UNSPEC_UDOT "u")
43e9d192
IB		 1657])
1658
1659(define_int_attr r [(UNSPEC_SQDMULH "") (UNSPEC_SQRDMULH "r")
1660 (UNSPEC_SQSHRUN "") (UNSPEC_SQRSHRUN "r")
1661 (UNSPEC_SQSHRN "") (UNSPEC_UQSHRN "")
1662 (UNSPEC_SQRSHRN "r") (UNSPEC_UQRSHRN "r")
1663 (UNSPEC_SQSHL "") (UNSPEC_UQSHL "")
1664 (UNSPEC_SQRSHL "r")(UNSPEC_UQRSHL "r")
1665])
1666
1667(define_int_attr lr [(UNSPEC_SSLI "l") (UNSPEC_USLI "l")
1668 (UNSPEC_SSRI "r") (UNSPEC_USRI "r")])
1669
1670(define_int_attr u [(UNSPEC_SQSHLU "u") (UNSPEC_SQSHL "") (UNSPEC_UQSHL "")
1671 (UNSPEC_SQSHRUN "u") (UNSPEC_SQRSHRUN "u")
1672 (UNSPEC_SQSHRN "") (UNSPEC_UQSHRN "")
1673 (UNSPEC_SQRSHRN "") (UNSPEC_UQRSHRN "")])
1674
1675(define_int_attr addsub [(UNSPEC_SHADD "add")
1676 (UNSPEC_UHADD "add")
1677 (UNSPEC_SRHADD "add")
1678 (UNSPEC_URHADD "add")
1679 (UNSPEC_SHSUB "sub")
1680 (UNSPEC_UHSUB "sub")
1681 (UNSPEC_SRHSUB "sub")
1682 (UNSPEC_URHSUB "sub")
1683 (UNSPEC_ADDHN "add")
1684 (UNSPEC_SUBHN "sub")
1685 (UNSPEC_RADDHN "add")
1686 (UNSPEC_RSUBHN "sub")
1687 (UNSPEC_ADDHN2 "add")
1688 (UNSPEC_SUBHN2 "sub")
1689 (UNSPEC_RADDHN2 "add")
1690 (UNSPEC_RSUBHN2 "sub")])
1691
cb23a30c
JG		 1692(define_int_attr offsetlr [(UNSPEC_SSLI "") (UNSPEC_USLI "")
1693 (UNSPEC_SSRI "offset_")
1694 (UNSPEC_USRI "offset_")])
43e9d192 1695
42fc9a7f
JG		 1696;; Standard pattern names for floating-point rounding instructions.
1697(define_int_attr frint_pattern [(UNSPEC_FRINTZ "btrunc")
1698 (UNSPEC_FRINTP "ceil")
1699 (UNSPEC_FRINTM "floor")
1700 (UNSPEC_FRINTI "nearbyint")
1701 (UNSPEC_FRINTX "rint")
0659ce6f
JG		 1702 (UNSPEC_FRINTA "round")
1703 (UNSPEC_FRINTN "frintn")])
42fc9a7f
JG		 1704
1705;; frint suffix for floating-point rounding instructions.
1706(define_int_attr frint_suffix [(UNSPEC_FRINTZ "z") (UNSPEC_FRINTP "p")
1707 (UNSPEC_FRINTM "m") (UNSPEC_FRINTI "i")
0659ce6f
JG		 1708 (UNSPEC_FRINTX "x") (UNSPEC_FRINTA "a")
1709 (UNSPEC_FRINTN "n")])
42fc9a7f
JG		 1710
1711(define_int_attr fcvt_pattern [(UNSPEC_FRINTZ "btrunc") (UNSPEC_FRINTA "round")
ce966824
JG		 1712 (UNSPEC_FRINTP "ceil") (UNSPEC_FRINTM "floor")
1713 (UNSPEC_FRINTN "frintn")])
42fc9a7f 1714
3f598afe
JW		 1715(define_int_attr fcvt_fixed_insn [(UNSPEC_SCVTF "scvtf")
1716 (UNSPEC_UCVTF "ucvtf")
1717 (UNSPEC_FCVTZS "fcvtzs")
1718 (UNSPEC_FCVTZU "fcvtzu")])
1719
db58fd89
JW		 1720;; Pointer authentication mnemonic prefix.
1721(define_int_attr pauth_mnem_prefix [(UNSPEC_PACISP "paci")
1722 (UNSPEC_AUTISP "auti")
1723 (UNSPEC_PACI1716 "paci")
1724 (UNSPEC_AUTI1716 "auti")])
1725
1726;; Pointer authentication HINT number for NOP space instructions using A Key.
1727(define_int_attr pauth_hint_num_a [(UNSPEC_PACISP "25")
1728 (UNSPEC_AUTISP "29")
1729 (UNSPEC_PACI1716 "8")
1730 (UNSPEC_AUTI1716 "12")])
1731
cc4d934f
JG		 1732(define_int_attr perm_insn [(UNSPEC_ZIP1 "zip") (UNSPEC_ZIP2 "zip")
1733 (UNSPEC_TRN1 "trn") (UNSPEC_TRN2 "trn")
1734 (UNSPEC_UZP1 "uzp") (UNSPEC_UZP2 "uzp")])
1735
923fcec3
AL		 1736; op code for REV instructions (size within which elements are reversed).
1737(define_int_attr rev_op [(UNSPEC_REV64 "64") (UNSPEC_REV32 "32")
1738 (UNSPEC_REV16 "16")])
1739
cc4d934f
JG		 1740(define_int_attr perm_hilo [(UNSPEC_ZIP1 "1") (UNSPEC_ZIP2 "2")
1741 (UNSPEC_TRN1 "1") (UNSPEC_TRN2 "2")
43cacb12
RS		 1742 (UNSPEC_UZP1 "1") (UNSPEC_UZP2 "2")
1743 (UNSPEC_UNPACKSHI "hi") (UNSPEC_UNPACKUHI "hi")
1744 (UNSPEC_UNPACKSLO "lo") (UNSPEC_UNPACKULO "lo")])
0050faf8 1745
9bfb28ed
RS		 1746;; Return true if the associated optab refers to the high-numbered lanes,
1747;; false if it refers to the low-numbered lanes. The convention is for
1748;; "hi" to refer to the low-numbered lanes (the first ones in memory)
1749;; for big-endian.
1750(define_int_attr hi_lanes_optab [(UNSPEC_UNPACKSHI "!BYTES_BIG_ENDIAN")
1751 (UNSPEC_UNPACKUHI "!BYTES_BIG_ENDIAN")
1752 (UNSPEC_UNPACKSLO "BYTES_BIG_ENDIAN")
1753 (UNSPEC_UNPACKULO "BYTES_BIG_ENDIAN")])
1754
0050faf8 1755(define_int_attr frecp_suffix [(UNSPEC_FRECPE "e") (UNSPEC_FRECPX "x")])
5a7a4e80 1756
5d357f26
KT		 1757(define_int_attr crc_variant [(UNSPEC_CRC32B "crc32b") (UNSPEC_CRC32H "crc32h")
1758 (UNSPEC_CRC32W "crc32w") (UNSPEC_CRC32X "crc32x")
1759 (UNSPEC_CRC32CB "crc32cb") (UNSPEC_CRC32CH "crc32ch")
1760 (UNSPEC_CRC32CW "crc32cw") (UNSPEC_CRC32CX "crc32cx")])
1761
1762(define_int_attr crc_mode [(UNSPEC_CRC32B "QI") (UNSPEC_CRC32H "HI")
1763 (UNSPEC_CRC32W "SI") (UNSPEC_CRC32X "DI")
1764 (UNSPEC_CRC32CB "QI") (UNSPEC_CRC32CH "HI")
1765 (UNSPEC_CRC32CW "SI") (UNSPEC_CRC32CX "DI")])
1766
5a7a4e80
TB		 1767(define_int_attr aes_op [(UNSPEC_AESE "e") (UNSPEC_AESD "d")])
1768(define_int_attr aesmc_op [(UNSPEC_AESMC "mc") (UNSPEC_AESIMC "imc")])
30442682
TB		 1769
1770(define_int_attr sha1_op [(UNSPEC_SHA1C "c") (UNSPEC_SHA1P "p")
1771 (UNSPEC_SHA1M "m")])
b9cb0a44
TB		 1772
1773(define_int_attr sha256_op [(UNSPEC_SHA256H "") (UNSPEC_SHA256H2 "2")])
57b26d65
MW		 1774
1775(define_int_attr rdma_as [(UNSPEC_SQRDMLAH "a") (UNSPEC_SQRDMLSH "s")])
27086ea3
MC		 1776
1777(define_int_attr sha512_op [(UNSPEC_SHA512H "") (UNSPEC_SHA512H2 "2")])
1778
1779(define_int_attr sm3tt_op [(UNSPEC_SM3TT1A "1a") (UNSPEC_SM3TT1B "1b")
1780 (UNSPEC_SM3TT2A "2a") (UNSPEC_SM3TT2B "2b")])
1781
1782(define_int_attr sm3part_op [(UNSPEC_SM3PARTW1 "1") (UNSPEC_SM3PARTW2 "2")])
1783
1784(define_int_attr f16mac1 [(UNSPEC_FMLAL "a") (UNSPEC_FMLSL "s")
1785 (UNSPEC_FMLAL2 "a") (UNSPEC_FMLSL2 "s")])
43cacb12
RS		 1786
1787;; The condition associated with an UNSPEC_COND_<xx>.
1788(define_int_attr cmp_op [(UNSPEC_COND_LT "lt")
1789 (UNSPEC_COND_LE "le")
1790 (UNSPEC_COND_EQ "eq")
1791 (UNSPEC_COND_NE "ne")
1792 (UNSPEC_COND_GE "ge")
f22d7973 1793 (UNSPEC_COND_GT "gt")])
0972596e 1794
0972596e 1795(define_int_attr sve_fp_op [(UNSPEC_COND_ADD "fadd")
0d2b3bca 1796 (UNSPEC_COND_SUB "fsub")
6c4fd4a9
RS		 1797 (UNSPEC_COND_MUL "fmul")
1798 (UNSPEC_COND_DIV "fdiv")
0d2b3bca
RS		 1799 (UNSPEC_COND_MAX "fmaxnm")
1800 (UNSPEC_COND_MIN "fminnm")])
1801
1802(define_int_attr commutative [(UNSPEC_COND_ADD "true")
1803 (UNSPEC_COND_SUB "false")
6c4fd4a9
RS		 1804 (UNSPEC_COND_MUL "true")
1805 (UNSPEC_COND_DIV "false")
0d2b3bca
RS		 1806 (UNSPEC_COND_MIN "true")
1807 (UNSPEC_COND_MAX "true")])
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