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aarch64: Extend %R for integer registers
[thirdparty/gcc.git] / gcc / config / aarch64 / iterators.md
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43e9d192 1;; Machine description for AArch64 architecture.
a5544970 2;; Copyright (C) 2009-2019 Free Software Foundation, Inc.
43e9d192
IB		 3;; Contributed by ARM Ltd.
4;;
5;; This file is part of GCC.
6;;
7;; GCC is free software; you can redistribute it and/or modify it
8;; under the terms of the GNU General Public License as published by
9;; the Free Software Foundation; either version 3, or (at your option)
10;; any later version.
11;;
12;; GCC is distributed in the hope that it will be useful, but
13;; WITHOUT ANY WARRANTY; without even the implied warranty of
14;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15;; General Public License for more details.
16;;
17;; You should have received a copy of the GNU General Public License
18;; along with GCC; see the file COPYING3. If not see
19;; <http://www.gnu.org/licenses/>.
20
21;; -------------------------------------------------------------------
22;; Mode Iterators
23;; -------------------------------------------------------------------
24
25
26;; Iterator for General Purpose Integer registers (32- and 64-bit modes)
27(define_mode_iterator GPI [SI DI])
28
d7f33f07
JW		 29;; Iterator for HI, SI, DI, some instructions can only work on these modes.
30(define_mode_iterator GPI_I16 [(HI "AARCH64_ISA_F16") SI DI])
31
43e9d192
IB		 32;; Iterator for QI and HI modes
33(define_mode_iterator SHORT [QI HI])
34
35;; Iterator for all integer modes (up to 64-bit)
36(define_mode_iterator ALLI [QI HI SI DI])
37
c0111dc4
RE		 38;; Iterator for all integer modes (up to 128-bit)
39(define_mode_iterator ALLI_TI [QI HI SI DI TI])
40
43e9d192
IB		 41;; Iterator for all integer modes that can be extended (up to 64-bit)
42(define_mode_iterator ALLX [QI HI SI])
43
44;; Iterator for General Purpose Floating-point registers (32- and 64-bit modes)
45(define_mode_iterator GPF [SF DF])
46
d7f33f07
JW		 47;; Iterator for all scalar floating point modes (HF, SF, DF)
48(define_mode_iterator GPF_F16 [(HF "AARCH64_ISA_F16") SF DF])
49
90e6443f
TC		 50;; Iterator for all scalar floating point modes (HF, SF, DF)
51(define_mode_iterator GPF_HF [HF SF DF])
52
09fcd8e1
RR		 53;; Iterator for all scalar floating point modes (HF, SF, DF and TF)
54(define_mode_iterator GPF_TF_F16 [HF SF DF TF])
c2ec330c 55
922f9c25
AL		 56;; Double vector modes.
57(define_mode_iterator VDF [V2SF V4HF])
58
b4f50fd4
RR		 59;; Iterator for all scalar floating point modes (SF, DF and TF)
60(define_mode_iterator GPF_TF [SF DF TF])
61
43cacb12 62;; Integer Advanced SIMD modes.
43e9d192
IB		 63(define_mode_iterator VDQ_I [V8QI V16QI V4HI V8HI V2SI V4SI V2DI])
64
43cacb12 65;; Advanced SIMD and scalar, 64 & 128-bit container, all integer modes.
43e9d192
IB		 66(define_mode_iterator VSDQ_I [V8QI V16QI V4HI V8HI V2SI V4SI V2DI QI HI SI DI])
67
43cacb12
RS		 68;; Advanced SIMD and scalar, 64 & 128-bit container: all Advanced SIMD
69;; integer modes; 64-bit scalar integer mode.
43e9d192
IB		 70(define_mode_iterator VSDQ_I_DI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI DI])
71
72;; Double vector modes.
71a11456 73(define_mode_iterator VD [V8QI V4HI V4HF V2SI V2SF])
43e9d192 74
dfe1da23
JW		 75;; All modes stored in registers d0-d31.
76(define_mode_iterator DREG [V8QI V4HI V4HF V2SI V2SF DF])
77
78;; Copy of the above.
79(define_mode_iterator DREG2 [V8QI V4HI V4HF V2SI V2SF DF])
80
43cacb12 81;; Advanced SIMD, 64-bit container, all integer modes.
43e9d192
IB		 82(define_mode_iterator VD_BHSI [V8QI V4HI V2SI])
83
84;; 128 and 64-bit container; 8, 16, 32-bit vector integer modes
85(define_mode_iterator VDQ_BHSI [V8QI V16QI V4HI V8HI V2SI V4SI])
86
87;; Quad vector modes.
71a11456 88(define_mode_iterator VQ [V16QI V8HI V4SI V2DI V8HF V4SF V2DF])
43e9d192 89
9f5361c8
KT		 90;; Copy of the above.
91(define_mode_iterator VQ2 [V16QI V8HI V4SI V2DI V8HF V4SF V2DF])
92
d21052eb
TC		 93;; Quad integer vector modes.
94(define_mode_iterator VQ_I [V16QI V8HI V4SI V2DI])
95
51437269 96;; VQ without 2 element modes.
71a11456 97(define_mode_iterator VQ_NO2E [V16QI V8HI V4SI V8HF V4SF])
51437269
GW		 98
99;; Quad vector with only 2 element modes.
100(define_mode_iterator VQ_2E [V2DI V2DF])
101
28514dda
YZ		 102;; This mode iterator allows :P to be used for patterns that operate on
103;; addresses in different modes. In LP64, only DI will match, while in
104;; ILP32, either can match.
105(define_mode_iterator P [(SI "ptr_mode == SImode || Pmode == SImode")
106 (DI "ptr_mode == DImode || Pmode == DImode")])
107
43e9d192
IB		 108;; This mode iterator allows :PTR to be used for patterns that operate on
109;; pointer-sized quantities. Exactly one of the two alternatives will match.
28514dda 110(define_mode_iterator PTR [(SI "ptr_mode == SImode") (DI "ptr_mode == DImode")])
43e9d192 111
43cacb12 112;; Advanced SIMD Float modes suitable for moving, loading and storing.
862abc04
AL		 113(define_mode_iterator VDQF_F16 [V4HF V8HF V2SF V4SF V2DF])
114
43cacb12 115;; Advanced SIMD Float modes.
43e9d192 116(define_mode_iterator VDQF [V2SF V4SF V2DF])
daef0a8c
JW		 117(define_mode_iterator VHSDF [(V4HF "TARGET_SIMD_F16INST")
118 (V8HF "TARGET_SIMD_F16INST")
119 V2SF V4SF V2DF])
43e9d192 120
43cacb12 121;; Advanced SIMD Float modes, and DF.
daef0a8c
JW		 122(define_mode_iterator VHSDF_DF [(V4HF "TARGET_SIMD_F16INST")
123 (V8HF "TARGET_SIMD_F16INST")
124 V2SF V4SF V2DF DF])
d7f33f07
JW		 125(define_mode_iterator VHSDF_HSDF [(V4HF "TARGET_SIMD_F16INST")
126 (V8HF "TARGET_SIMD_F16INST")
127 V2SF V4SF V2DF
128 (HF "TARGET_SIMD_F16INST")
129 SF DF])
f421c516 130
10bd1d96
KT		 131;; Scalar and vetor modes for SF, DF.
132(define_mode_iterator VSFDF [V2SF V4SF V2DF DF SF])
133
43cacb12 134;; Advanced SIMD single Float modes.
828e70c1
JG		 135(define_mode_iterator VDQSF [V2SF V4SF])
136
03873eb9
AL		 137;; Quad vector Float modes with half/single elements.
138(define_mode_iterator VQ_HSF [V8HF V4SF])
139
fc21784d
JG		 140;; Modes suitable to use as the return type of a vcond expression.
141(define_mode_iterator VDQF_COND [V2SF V2SI V4SF V4SI V2DF V2DI])
142
43cacb12 143;; All scalar and Advanced SIMD Float modes.
889b9412
JG		 144(define_mode_iterator VALLF [V2SF V4SF V2DF SF DF])
145
43cacb12 146;; Advanced SIMD Float modes with 2 elements.
43e9d192
IB		 147(define_mode_iterator V2F [V2SF V2DF])
148
43cacb12 149;; All Advanced SIMD modes on which we support any arithmetic operations.
43e9d192
IB		 150(define_mode_iterator VALL [V8QI V16QI V4HI V8HI V2SI V4SI V2DI V2SF V4SF V2DF])
151
43cacb12 152;; All Advanced SIMD modes suitable for moving, loading, and storing.
71a11456
AL		 153(define_mode_iterator VALL_F16 [V8QI V16QI V4HI V8HI V2SI V4SI V2DI
154 V4HF V8HF V2SF V4SF V2DF])
155
88119b46
KT		 156;; The VALL_F16 modes except the 128-bit 2-element ones.
157(define_mode_iterator VALL_F16_NO_V2Q [V8QI V16QI V4HI V8HI V2SI V4SI
158 V4HF V8HF V2SF V4SF])
159
43cacb12 160;; All Advanced SIMD modes barring HF modes, plus DI.
a50344cb
TB		 161(define_mode_iterator VALLDI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI V2SF V4SF V2DF DI])
162
43cacb12 163;; All Advanced SIMD modes and DI.
71a11456
AL		 164(define_mode_iterator VALLDI_F16 [V8QI V16QI V4HI V8HI V2SI V4SI V2DI
165 V4HF V8HF V2SF V4SF V2DF DI])
166
43cacb12 167;; All Advanced SIMD modes, plus DI and DF.
46e778c4 168(define_mode_iterator VALLDIF [V8QI V16QI V4HI V8HI V2SI V4SI
7c369485 169 V2DI V4HF V8HF V2SF V4SF V2DF DI DF])
46e778c4 170
43cacb12 171;; Advanced SIMD modes for Integer reduction across lanes.
92835317
TB		 172(define_mode_iterator VDQV [V8QI V16QI V4HI V8HI V4SI V2DI])
173
43cacb12 174;; Advanced SIMD modes (except V2DI) for Integer reduction across lanes.
92835317 175(define_mode_iterator VDQV_S [V8QI V16QI V4HI V8HI V4SI])
43e9d192
IB		 176
177;; All double integer narrow-able modes.
178(define_mode_iterator VDN [V4HI V2SI DI])
179
180;; All quad integer narrow-able modes.
181(define_mode_iterator VQN [V8HI V4SI V2DI])
182
43cacb12
RS		 183;; Advanced SIMD and scalar 128-bit container: narrowable 16, 32, 64-bit
184;; integer modes
43e9d192
IB		 185(define_mode_iterator VSQN_HSDI [V8HI V4SI V2DI HI SI DI])
186
187;; All quad integer widen-able modes.
188(define_mode_iterator VQW [V16QI V8HI V4SI])
189
190;; Double vector modes for combines.
7c369485 191(define_mode_iterator VDC [V8QI V4HI V4HF V2SI V2SF DI DF])
43e9d192 192
43cacb12 193;; Advanced SIMD modes except double int.
43e9d192 194(define_mode_iterator VDQIF [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF V2DF])
703bbcdf
JW		 195(define_mode_iterator VDQIF_F16 [V8QI V16QI V4HI V8HI V2SI V4SI
196 V4HF V8HF V2SF V4SF V2DF])
43e9d192 197
43cacb12 198;; Advanced SIMD modes for S type.
58a3bd25
FY		 199(define_mode_iterator VDQ_SI [V2SI V4SI])
200
43cacb12 201;; Advanced SIMD modes for S and D.
2644d4d9
JW		 202(define_mode_iterator VDQ_SDI [V2SI V4SI V2DI])
203
43cacb12 204;; Advanced SIMD modes for H, S and D.
33d72b63
JW		 205(define_mode_iterator VDQ_HSDI [(V4HI "TARGET_SIMD_F16INST")
206 (V8HI "TARGET_SIMD_F16INST")
207 V2SI V4SI V2DI])
208
43cacb12 209;; Scalar and Advanced SIMD modes for S and D.
2644d4d9
JW		 210(define_mode_iterator VSDQ_SDI [V2SI V4SI V2DI SI DI])
211
43cacb12 212;; Scalar and Advanced SIMD modes for S and D, Advanced SIMD modes for H.
33d72b63
JW		 213(define_mode_iterator VSDQ_HSDI [(V4HI "TARGET_SIMD_F16INST")
214 (V8HI "TARGET_SIMD_F16INST")
68ad28c3
JW		 215 V2SI V4SI V2DI
216 (HI "TARGET_SIMD_F16INST")
217 SI DI])
33d72b63 218
43cacb12 219;; Advanced SIMD modes for Q and H types.
66adb8eb
JG		 220(define_mode_iterator VDQQH [V8QI V16QI V4HI V8HI])
221
43cacb12 222;; Advanced SIMD modes for H and S types.
43e9d192
IB		 223(define_mode_iterator VDQHS [V4HI V8HI V2SI V4SI])
224
43cacb12 225;; Advanced SIMD modes for H, S and D types.
c7f28cd5
KT		 226(define_mode_iterator VDQHSD [V4HI V8HI V2SI V4SI V2DI])
227
43cacb12 228;; Advanced SIMD and scalar integer modes for H and S.
43e9d192
IB		 229(define_mode_iterator VSDQ_HSI [V4HI V8HI V2SI V4SI HI SI])
230
43cacb12 231;; Advanced SIMD and scalar 64-bit container: 16, 32-bit integer modes.
43e9d192
IB		 232(define_mode_iterator VSD_HSI [V4HI V2SI HI SI])
233
43cacb12 234;; Advanced SIMD 64-bit container: 16, 32-bit integer modes.
43e9d192
IB		 235(define_mode_iterator VD_HSI [V4HI V2SI])
236
237;; Scalar 64-bit container: 16, 32-bit integer modes
238(define_mode_iterator SD_HSI [HI SI])
239
43cacb12 240;; Advanced SIMD 64-bit container: 16, 32-bit integer modes.
43e9d192
IB		 241(define_mode_iterator VQ_HSI [V8HI V4SI])
242
243;; All byte modes.
244(define_mode_iterator VB [V8QI V16QI])
245
5e32e83b
JW		 246;; 2 and 4 lane SI modes.
247(define_mode_iterator VS [V2SI V4SI])
248
43e9d192
IB		 249(define_mode_iterator TX [TI TF])
250
43cacb12 251;; Advanced SIMD opaque structure modes.
43e9d192
IB		 252(define_mode_iterator VSTRUCT [OI CI XI])
253
254;; Double scalar modes
255(define_mode_iterator DX [DI DF])
256
dfe1da23
JW		 257;; Duplicate of the above
258(define_mode_iterator DX2 [DI DF])
259
260;; Single scalar modes
261(define_mode_iterator SX [SI SF])
262
263;; Duplicate of the above
264(define_mode_iterator SX2 [SI SF])
265
266;; Single and double integer and float modes
267(define_mode_iterator DSX [DF DI SF SI])
268
269
43cacb12 270;; Modes available for Advanced SIMD <f>mul lane operations.
ab2e8f01
JW		 271(define_mode_iterator VMUL [V4HI V8HI V2SI V4SI
272 (V4HF "TARGET_SIMD_F16INST")
273 (V8HF "TARGET_SIMD_F16INST")
274 V2SF V4SF V2DF])
779aea46 275
43cacb12
RS		 276;; Modes available for Advanced SIMD <f>mul lane operations changing lane
277;; count.
779aea46
JG		 278(define_mode_iterator VMUL_CHANGE_NLANES [V4HI V8HI V2SI V4SI V2SF V4SF])
279
43cacb12
RS		 280;; All SVE vector modes.
281(define_mode_iterator SVE_ALL [VNx16QI VNx8HI VNx4SI VNx2DI
282 VNx8HF VNx4SF VNx2DF])
283
95eb5537
RS		 284;; Iterators for single modes, for "@" patterns.
285(define_mode_iterator VNx4SI_ONLY [VNx4SI])
286(define_mode_iterator VNx2DF_ONLY [VNx2DF])
287
9f4cbab8
RS		 288;; All SVE vector structure modes.
289(define_mode_iterator SVE_STRUCT [VNx32QI VNx16HI VNx8SI VNx4DI
290 VNx16HF VNx8SF VNx4DF
291 VNx48QI VNx24HI VNx12SI VNx6DI
292 VNx24HF VNx12SF VNx6DF
293 VNx64QI VNx32HI VNx16SI VNx8DI
294 VNx32HF VNx16SF VNx8DF])
295
43cacb12
RS		 296;; All SVE vector modes that have 8-bit or 16-bit elements.
297(define_mode_iterator SVE_BH [VNx16QI VNx8HI VNx8HF])
298
299;; All SVE vector modes that have 8-bit, 16-bit or 32-bit elements.
300(define_mode_iterator SVE_BHS [VNx16QI VNx8HI VNx4SI VNx8HF VNx4SF])
301
95eb5537 302;; SVE integer vector modes that have 8-bit, 16-bit or 32-bit elements.
43cacb12
RS		 303(define_mode_iterator SVE_BHSI [VNx16QI VNx8HI VNx4SI])
304
95eb5537
RS		 305;; SVE integer vector modes that have 16-bit, 32-bit or 64-bit elements.
306(define_mode_iterator SVE_HSDI [VNx8HI VNx4SI VNx2DI])
43cacb12 307
95eb5537 308;; SVE floating-point vector modes that have 16-bit or 32-bit elements.
43cacb12
RS		 309(define_mode_iterator SVE_HSF [VNx8HF VNx4SF])
310
95eb5537
RS		 311;; SVE integer vector modes that have 32-bit or 64-bit elements.
312(define_mode_iterator SVE_SDI [VNx4SI VNx2DI])
313
314;; SVE floating-point vector modes that have 32-bit or 64-bit elements.
315(define_mode_iterator SVE_SDF [VNx4SF VNx2DF])
316
a70965b1
RS		 317;; All SVE vector modes that have 16-bit, 32-bit or 64-bit elements.
318(define_mode_iterator SVE_HSD [VNx8HI VNx4SI VNx2DI VNx8HF VNx4SF VNx2DF])
319
43cacb12
RS		 320;; All SVE vector modes that have 32-bit or 64-bit elements.
321(define_mode_iterator SVE_SD [VNx4SI VNx2DI VNx4SF VNx2DF])
322
bfaa08b7
RS		 323;; All SVE vector modes that have 32-bit elements.
324(define_mode_iterator SVE_S [VNx4SI VNx4SF])
325
326;; All SVE vector modes that have 64-bit elements.
327(define_mode_iterator SVE_D [VNx2DI VNx2DF])
328
43cacb12
RS		 329;; All SVE integer vector modes.
330(define_mode_iterator SVE_I [VNx16QI VNx8HI VNx4SI VNx2DI])
331
332;; All SVE floating-point vector modes.
333(define_mode_iterator SVE_F [VNx8HF VNx4SF VNx2DF])
334
335;; All SVE predicate modes.
336(define_mode_iterator PRED_ALL [VNx16BI VNx8BI VNx4BI VNx2BI])
337
338;; SVE predicate modes that control 8-bit, 16-bit or 32-bit elements.
339(define_mode_iterator PRED_BHS [VNx16BI VNx8BI VNx4BI])
340
43e9d192
IB		 341;; ------------------------------------------------------------------
342;; Unspec enumerations for Advance SIMD. These could well go into
343;; aarch64.md but for their use in int_iterators here.
344;; ------------------------------------------------------------------
345
346(define_c_enum "unspec"
347 [
348 UNSPEC_ASHIFT_SIGNED ; Used in aarch-simd.md.
349 UNSPEC_ASHIFT_UNSIGNED ; Used in aarch64-simd.md.
285398d2 350 UNSPEC_ABS ; Used in aarch64-simd.md.
998eaf97
JG		 351 UNSPEC_FMAX ; Used in aarch64-simd.md.
352 UNSPEC_FMAXNMV ; Used in aarch64-simd.md.
43e9d192 353 UNSPEC_FMAXV ; Used in aarch64-simd.md.
998eaf97
JG		 354 UNSPEC_FMIN ; Used in aarch64-simd.md.
355 UNSPEC_FMINNMV ; Used in aarch64-simd.md.
43e9d192
IB		 356 UNSPEC_FMINV ; Used in aarch64-simd.md.
357 UNSPEC_FADDV ; Used in aarch64-simd.md.
f5156c3e 358 UNSPEC_ADDV ; Used in aarch64-simd.md.
43e9d192
IB		 359 UNSPEC_SMAXV ; Used in aarch64-simd.md.
360 UNSPEC_SMINV ; Used in aarch64-simd.md.
361 UNSPEC_UMAXV ; Used in aarch64-simd.md.
362 UNSPEC_UMINV ; Used in aarch64-simd.md.
363 UNSPEC_SHADD ; Used in aarch64-simd.md.
364 UNSPEC_UHADD ; Used in aarch64-simd.md.
365 UNSPEC_SRHADD ; Used in aarch64-simd.md.
366 UNSPEC_URHADD ; Used in aarch64-simd.md.
367 UNSPEC_SHSUB ; Used in aarch64-simd.md.
368 UNSPEC_UHSUB ; Used in aarch64-simd.md.
369 UNSPEC_SRHSUB ; Used in aarch64-simd.md.
370 UNSPEC_URHSUB ; Used in aarch64-simd.md.
371 UNSPEC_ADDHN ; Used in aarch64-simd.md.
372 UNSPEC_RADDHN ; Used in aarch64-simd.md.
373 UNSPEC_SUBHN ; Used in aarch64-simd.md.
374 UNSPEC_RSUBHN ; Used in aarch64-simd.md.
375 UNSPEC_ADDHN2 ; Used in aarch64-simd.md.
376 UNSPEC_RADDHN2 ; Used in aarch64-simd.md.
377 UNSPEC_SUBHN2 ; Used in aarch64-simd.md.
378 UNSPEC_RSUBHN2 ; Used in aarch64-simd.md.
379 UNSPEC_SQDMULH ; Used in aarch64-simd.md.
380 UNSPEC_SQRDMULH ; Used in aarch64-simd.md.
58cc9876
YW		 381 UNSPEC_SMULLB ; Used in aarch64-sve2.md.
382 UNSPEC_SMULLT ; Used in aarch64-sve2.md.
383 UNSPEC_UMULLB ; Used in aarch64-sve2.md.
384 UNSPEC_UMULLT ; Used in aarch64-sve2.md.
43e9d192 385 UNSPEC_PMUL ; Used in aarch64-simd.md.
496ea87d 386 UNSPEC_FMULX ; Used in aarch64-simd.md.
43e9d192
IB		 387 UNSPEC_USQADD ; Used in aarch64-simd.md.
388 UNSPEC_SUQADD ; Used in aarch64-simd.md.
389 UNSPEC_SQXTUN ; Used in aarch64-simd.md.
390 UNSPEC_SQXTN ; Used in aarch64-simd.md.
391 UNSPEC_UQXTN ; Used in aarch64-simd.md.
392 UNSPEC_SSRA ; Used in aarch64-simd.md.
393 UNSPEC_USRA ; Used in aarch64-simd.md.
394 UNSPEC_SRSRA ; Used in aarch64-simd.md.
395 UNSPEC_URSRA ; Used in aarch64-simd.md.
396 UNSPEC_SRSHR ; Used in aarch64-simd.md.
397 UNSPEC_URSHR ; Used in aarch64-simd.md.
398 UNSPEC_SQSHLU ; Used in aarch64-simd.md.
399 UNSPEC_SQSHL ; Used in aarch64-simd.md.
400 UNSPEC_UQSHL ; Used in aarch64-simd.md.
401 UNSPEC_SQSHRUN ; Used in aarch64-simd.md.
402 UNSPEC_SQRSHRUN ; Used in aarch64-simd.md.
403 UNSPEC_SQSHRN ; Used in aarch64-simd.md.
404 UNSPEC_UQSHRN ; Used in aarch64-simd.md.
405 UNSPEC_SQRSHRN ; Used in aarch64-simd.md.
406 UNSPEC_UQRSHRN ; Used in aarch64-simd.md.
58cc9876
YW		 407 UNSPEC_SHRNB ; Used in aarch64-sve2.md.
408 UNSPEC_SHRNT ; Used in aarch64-sve2.md.
409 UNSPEC_RSHRNB ; Used in aarch64-sve2.md.
410 UNSPEC_RSHRNT ; Used in aarch64-sve2.md.
43e9d192
IB		 411 UNSPEC_SSHL ; Used in aarch64-simd.md.
412 UNSPEC_USHL ; Used in aarch64-simd.md.
413 UNSPEC_SRSHL ; Used in aarch64-simd.md.
414 UNSPEC_URSHL ; Used in aarch64-simd.md.
415 UNSPEC_SQRSHL ; Used in aarch64-simd.md.
416 UNSPEC_UQRSHL ; Used in aarch64-simd.md.
43e9d192
IB		 417 UNSPEC_SSLI ; Used in aarch64-simd.md.
418 UNSPEC_USLI ; Used in aarch64-simd.md.
419 UNSPEC_SSRI ; Used in aarch64-simd.md.
420 UNSPEC_USRI ; Used in aarch64-simd.md.
421 UNSPEC_SSHLL ; Used in aarch64-simd.md.
422 UNSPEC_USHLL ; Used in aarch64-simd.md.
423 UNSPEC_ADDP ; Used in aarch64-simd.md.
88b08073 424 UNSPEC_TBL ; Used in vector permute patterns.
9371aecc 425 UNSPEC_TBX ; Used in vector permute patterns.
88b08073 426 UNSPEC_CONCAT ; Used in vector permute patterns.
3f8334a5
RS		 427
428 ;; The following permute unspecs are generated directly by
429 ;; aarch64_expand_vec_perm_const, so any changes to the underlying
430 ;; instructions would need a corresponding change there.
cc4d934f
JG		 431 UNSPEC_ZIP1 ; Used in vector permute patterns.
432 UNSPEC_ZIP2 ; Used in vector permute patterns.
433 UNSPEC_UZP1 ; Used in vector permute patterns.
434 UNSPEC_UZP2 ; Used in vector permute patterns.
435 UNSPEC_TRN1 ; Used in vector permute patterns.
436 UNSPEC_TRN2 ; Used in vector permute patterns.
3f8334a5 437 UNSPEC_EXT ; Used in vector permute patterns.
923fcec3
AL		 438 UNSPEC_REV64 ; Used in vector reverse patterns (permute).
439 UNSPEC_REV32 ; Used in vector reverse patterns (permute).
440 UNSPEC_REV16 ; Used in vector reverse patterns (permute).
3f8334a5 441
5a7a4e80
TB		 442 UNSPEC_AESE ; Used in aarch64-simd.md.
443 UNSPEC_AESD ; Used in aarch64-simd.md.
444 UNSPEC_AESMC ; Used in aarch64-simd.md.
445 UNSPEC_AESIMC ; Used in aarch64-simd.md.
30442682
TB		 446 UNSPEC_SHA1C ; Used in aarch64-simd.md.
447 UNSPEC_SHA1M ; Used in aarch64-simd.md.
448 UNSPEC_SHA1P ; Used in aarch64-simd.md.
449 UNSPEC_SHA1H ; Used in aarch64-simd.md.
450 UNSPEC_SHA1SU0 ; Used in aarch64-simd.md.
451 UNSPEC_SHA1SU1 ; Used in aarch64-simd.md.
b9cb0a44
TB		 452 UNSPEC_SHA256H ; Used in aarch64-simd.md.
453 UNSPEC_SHA256H2 ; Used in aarch64-simd.md.
454 UNSPEC_SHA256SU0 ; Used in aarch64-simd.md.
455 UNSPEC_SHA256SU1 ; Used in aarch64-simd.md.
7baa225d
TB		 456 UNSPEC_PMULL ; Used in aarch64-simd.md.
457 UNSPEC_PMULL2 ; Used in aarch64-simd.md.
668046d1 458 UNSPEC_REV_REGLIST ; Used in aarch64-simd.md.
9c004c58 459 UNSPEC_VEC_SHR ; Used in aarch64-simd.md.
57b26d65
MW		 460 UNSPEC_SQRDMLAH ; Used in aarch64-simd.md.
461 UNSPEC_SQRDMLSH ; Used in aarch64-simd.md.
202d0c11
DS		 462 UNSPEC_FMAXNM ; Used in aarch64-simd.md.
463 UNSPEC_FMINNM ; Used in aarch64-simd.md.
7a08d813
TC		 464 UNSPEC_SDOT ; Used in aarch64-simd.md.
465 UNSPEC_UDOT ; Used in aarch64-simd.md.
27086ea3
MC		 466 UNSPEC_SM3SS1 ; Used in aarch64-simd.md.
467 UNSPEC_SM3TT1A ; Used in aarch64-simd.md.
468 UNSPEC_SM3TT1B ; Used in aarch64-simd.md.
469 UNSPEC_SM3TT2A ; Used in aarch64-simd.md.
470 UNSPEC_SM3TT2B ; Used in aarch64-simd.md.
471 UNSPEC_SM3PARTW1 ; Used in aarch64-simd.md.
472 UNSPEC_SM3PARTW2 ; Used in aarch64-simd.md.
473 UNSPEC_SM4E ; Used in aarch64-simd.md.
474 UNSPEC_SM4EKEY ; Used in aarch64-simd.md.
475 UNSPEC_SHA512H ; Used in aarch64-simd.md.
476 UNSPEC_SHA512H2 ; Used in aarch64-simd.md.
477 UNSPEC_SHA512SU0 ; Used in aarch64-simd.md.
478 UNSPEC_SHA512SU1 ; Used in aarch64-simd.md.
479 UNSPEC_FMLAL ; Used in aarch64-simd.md.
480 UNSPEC_FMLSL ; Used in aarch64-simd.md.
481 UNSPEC_FMLAL2 ; Used in aarch64-simd.md.
482 UNSPEC_FMLSL2 ; Used in aarch64-simd.md.
43cacb12 483 UNSPEC_SEL ; Used in aarch64-sve.md.
898f07b0
RS		 484 UNSPEC_ANDV ; Used in aarch64-sve.md.
485 UNSPEC_IORV ; Used in aarch64-sve.md.
486 UNSPEC_XORV ; Used in aarch64-sve.md.
43cacb12
RS		 487 UNSPEC_ANDF ; Used in aarch64-sve.md.
488 UNSPEC_IORF ; Used in aarch64-sve.md.
489 UNSPEC_XORF ; Used in aarch64-sve.md.
d7a09c44
RS		 490 UNSPEC_REVB ; Used in aarch64-sve.md.
491 UNSPEC_REVH ; Used in aarch64-sve.md.
492 UNSPEC_REVW ; Used in aarch64-sve.md.
11e9443f
RS		 493 UNSPEC_SMUL_HIGHPART ; Used in aarch64-sve.md.
494 UNSPEC_UMUL_HIGHPART ; Used in aarch64-sve.md.
d45b20a5 495 UNSPEC_COND_FABS ; Used in aarch64-sve.md.
cb18e86d
RS		 496 UNSPEC_COND_FADD ; Used in aarch64-sve.md.
497 UNSPEC_COND_FCMEQ ; Used in aarch64-sve.md.
498 UNSPEC_COND_FCMGE ; Used in aarch64-sve.md.
499 UNSPEC_COND_FCMGT ; Used in aarch64-sve.md.
500 UNSPEC_COND_FCMLE ; Used in aarch64-sve.md.
501 UNSPEC_COND_FCMLT ; Used in aarch64-sve.md.
502 UNSPEC_COND_FCMNE ; Used in aarch64-sve.md.
4a942af6 503 UNSPEC_COND_FCMUO ; Used in aarch64-sve.md.
99361551
RS		 504 UNSPEC_COND_FCVT ; Used in aarch64-sve.md.
505 UNSPEC_COND_FCVTZS ; Used in aarch64-sve.md.
506 UNSPEC_COND_FCVTZU ; Used in aarch64-sve.md.
cb18e86d
RS		 507 UNSPEC_COND_FDIV ; Used in aarch64-sve.md.
508 UNSPEC_COND_FMAXNM ; Used in aarch64-sve.md.
509 UNSPEC_COND_FMINNM ; Used in aarch64-sve.md.
b41d1f6e
RS		 510 UNSPEC_COND_FMLA ; Used in aarch64-sve.md.
511 UNSPEC_COND_FMLS ; Used in aarch64-sve.md.
cb18e86d 512 UNSPEC_COND_FMUL ; Used in aarch64-sve.md.
d45b20a5 513 UNSPEC_COND_FNEG ; Used in aarch64-sve.md.
b41d1f6e
RS		 514 UNSPEC_COND_FNMLA ; Used in aarch64-sve.md.
515 UNSPEC_COND_FNMLS ; Used in aarch64-sve.md.
d45b20a5
RS		 516 UNSPEC_COND_FRINTA ; Used in aarch64-sve.md.
517 UNSPEC_COND_FRINTI ; Used in aarch64-sve.md.
518 UNSPEC_COND_FRINTM ; Used in aarch64-sve.md.
519 UNSPEC_COND_FRINTN ; Used in aarch64-sve.md.
520 UNSPEC_COND_FRINTP ; Used in aarch64-sve.md.
521 UNSPEC_COND_FRINTX ; Used in aarch64-sve.md.
522 UNSPEC_COND_FRINTZ ; Used in aarch64-sve.md.
523 UNSPEC_COND_FSQRT ; Used in aarch64-sve.md.
cb18e86d 524 UNSPEC_COND_FSUB ; Used in aarch64-sve.md.
99361551
RS		 525 UNSPEC_COND_SCVTF ; Used in aarch64-sve.md.
526 UNSPEC_COND_UCVTF ; Used in aarch64-sve.md.
43cacb12 527 UNSPEC_LASTB ; Used in aarch64-sve.md.
9d63f43b
TC		 528 UNSPEC_FCADD90 ; Used in aarch64-simd.md.
529 UNSPEC_FCADD270 ; Used in aarch64-simd.md.
530 UNSPEC_FCMLA ; Used in aarch64-simd.md.
531 UNSPEC_FCMLA90 ; Used in aarch64-simd.md.
532 UNSPEC_FCMLA180 ; Used in aarch64-simd.md.
533 UNSPEC_FCMLA270 ; Used in aarch64-simd.md.
58cc9876
YW		 534 UNSPEC_SMULHS ; Used in aarch64-sve2.md.
535 UNSPEC_SMULHRS ; Used in aarch64-sve2.md.
536 UNSPEC_UMULHS ; Used in aarch64-sve2.md.
537 UNSPEC_UMULHRS ; Used in aarch64-sve2.md.
43e9d192
IB		 538])
539
d81cb613
MW		 540;; ------------------------------------------------------------------
541;; Unspec enumerations for Atomics. They are here so that they can be
542;; used in the int_iterators for atomic operations.
543;; ------------------------------------------------------------------
544
545(define_c_enum "unspecv"
546 [
547 UNSPECV_LX ; Represent a load-exclusive.
548 UNSPECV_SX ; Represent a store-exclusive.
549 UNSPECV_LDA ; Represent an atomic load or load-acquire.
550 UNSPECV_STL ; Represent an atomic store or store-release.
551 UNSPECV_ATOMIC_CMPSW ; Represent an atomic compare swap.
552 UNSPECV_ATOMIC_EXCHG ; Represent an atomic exchange.
553 UNSPECV_ATOMIC_CAS ; Represent an atomic CAS.
554 UNSPECV_ATOMIC_SWP ; Represent an atomic SWP.
555 UNSPECV_ATOMIC_OP ; Represent an atomic operation.
d81cb613
MW		 556 UNSPECV_ATOMIC_LDOP_OR ; Represent an atomic load-or
557 UNSPECV_ATOMIC_LDOP_BIC ; Represent an atomic load-bic
558 UNSPECV_ATOMIC_LDOP_XOR ; Represent an atomic load-xor
559 UNSPECV_ATOMIC_LDOP_PLUS ; Represent an atomic load-add
560])
561
43e9d192
IB		 562;; -------------------------------------------------------------------
563;; Mode attributes
564;; -------------------------------------------------------------------
565
566;; In GPI templates, a string like "%<w>0" will expand to "%w0" in the
567;; 32-bit version and "%x0" in the 64-bit version.
568(define_mode_attr w [(QI "w") (HI "w") (SI "w") (DI "x") (SF "s") (DF "d")])
569
db46a2e6
JG		 570;; The size of access, in bytes.
571(define_mode_attr ldst_sz [(SI "4") (DI "8")])
572;; Likewise for load/store pair.
573(define_mode_attr ldpstp_sz [(SI "8") (DI "16")])
574
0d35c5c2 575;; For inequal width int to float conversion
d7f33f07
JW		 576(define_mode_attr w1 [(HF "w") (SF "w") (DF "x")])
577(define_mode_attr w2 [(HF "x") (SF "x") (DF "w")])
0d35c5c2 578
22be0d08
MC		 579;; For width of fp registers in fcvt instruction
580(define_mode_attr fpw [(DI "s") (SI "d")])
581
2b8568fe
KT		 582(define_mode_attr short_mask [(HI "65535") (QI "255")])
583
051d0e2f
SN		 584;; For constraints used in scalar immediate vector moves
585(define_mode_attr hq [(HI "h") (QI "q")])
586
ef22810a
RH		 587;; For doubling width of an integer mode
588(define_mode_attr DWI [(QI "HI") (HI "SI") (SI "DI") (DI "TI")])
589
22be0d08
MC		 590(define_mode_attr fcvt_change_mode [(SI "df") (DI "sf")])
591
592(define_mode_attr FCVT_CHANGE_MODE [(SI "DF") (DI "SF")])
593
43e9d192
IB		 594;; For scalar usage of vector/FP registers
595(define_mode_attr v [(QI "b") (HI "h") (SI "s") (DI "d")
d7f33f07 596 (HF "h") (SF "s") (DF "d")
43e9d192
IB		 597 (V8QI "") (V16QI "")
598 (V4HI "") (V8HI "")
599 (V2SI "") (V4SI "")
600 (V2DI "") (V2SF "")
daef0a8c
JW		 601 (V4SF "") (V4HF "")
602 (V8HF "") (V2DF "")])
43e9d192
IB		 603
604;; For scalar usage of vector/FP registers, narrowing
605(define_mode_attr vn2 [(QI "") (HI "b") (SI "h") (DI "s")
606 (V8QI "") (V16QI "")
607 (V4HI "") (V8HI "")
608 (V2SI "") (V4SI "")
609 (V2DI "") (V2SF "")
610 (V4SF "") (V2DF "")])
611
612;; For scalar usage of vector/FP registers, widening
613(define_mode_attr vw2 [(DI "") (QI "h") (HI "s") (SI "d")
614 (V8QI "") (V16QI "")
615 (V4HI "") (V8HI "")
616 (V2SI "") (V4SI "")
617 (V2DI "") (V2SF "")
618 (V4SF "") (V2DF "")])
619
89fdc743
IB		 620;; Register Type Name and Vector Arrangement Specifier for when
621;; we are doing scalar for DI and SIMD for SI (ignoring all but
622;; lane 0).
623(define_mode_attr rtn [(DI "d") (SI "")])
624(define_mode_attr vas [(DI "") (SI ".2s")])
625
7ac29c0f
RS		 626;; Map a vector to the number of units in it, if the size of the mode
627;; is constant.
628(define_mode_attr nunits [(V8QI "8") (V16QI "16")
629 (V4HI "4") (V8HI "8")
630 (V2SI "2") (V4SI "4")
631 (V2DI "2")
632 (V4HF "4") (V8HF "8")
633 (V2SF "2") (V4SF "4")
634 (V1DF "1") (V2DF "2")
635 (DI "1") (DF "1")])
636
b187677b
RS		 637;; Map a mode to the number of bits in it, if the size of the mode
638;; is constant.
639(define_mode_attr bitsize [(V8QI "64") (V16QI "128")
640 (V4HI "64") (V8HI "128")
641 (V2SI "64") (V4SI "128")
642 (V2DI "128")])
643
22be0d08
MC		 644;; Map a floating point or integer mode to the appropriate register name prefix
645(define_mode_attr s [(HF "h") (SF "s") (DF "d") (SI "s") (DI "d")])
43e9d192
IB		 646
647;; Give the length suffix letter for a sign- or zero-extension.
648(define_mode_attr size [(QI "b") (HI "h") (SI "w")])
649
650;; Give the number of bits in the mode
651(define_mode_attr sizen [(QI "8") (HI "16") (SI "32") (DI "64")])
652
653;; Give the ordinal of the MSB in the mode
315fdae8
RE		 654(define_mode_attr sizem1 [(QI "#7") (HI "#15") (SI "#31") (DI "#63")
655 (HF "#15") (SF "#31") (DF "#63")])
43e9d192 656
95eb5537
RS		 657;; The number of bits in a vector element, or controlled by a predicate
658;; element.
d7a09c44
RS		 659(define_mode_attr elem_bits [(VNx16BI "8") (VNx8BI "16")
660 (VNx4BI "32") (VNx2BI "64")
661 (VNx16QI "8") (VNx8HI "16")
662 (VNx4SI "32") (VNx2DI "64")
95eb5537
RS		 663 (VNx8HF "16") (VNx4SF "32") (VNx2DF "64")])
664
43e9d192
IB		 665;; Attribute to describe constants acceptable in logical operations
666(define_mode_attr lconst [(SI "K") (DI "L")])
667
43fd192f
MC		 668;; Attribute to describe constants acceptable in logical and operations
669(define_mode_attr lconst2 [(SI "UsO") (DI "UsP")])
670
43e9d192
IB		 671;; Map a mode to a specific constraint character.
672(define_mode_attr cmode [(QI "q") (HI "h") (SI "s") (DI "d")])
673
0603375c
KT		 674;; Map modes to Usg and Usj constraints for SISD right shifts
675(define_mode_attr cmode_simd [(SI "g") (DI "j")])
676
43e9d192
IB		 677(define_mode_attr Vtype [(V8QI "8b") (V16QI "16b")
678 (V4HI "4h") (V8HI "8h")
679 (V2SI "2s") (V4SI "4s")
680 (DI "1d") (DF "1d")
681 (V2DI "2d") (V2SF "2s")
7c369485
AL		 682 (V4SF "4s") (V2DF "2d")
683 (V4HF "4h") (V8HF "8h")])
43e9d192 684
c7f28cd5
KT		 685(define_mode_attr Vrevsuff [(V4HI "16") (V8HI "16") (V2SI "32")
686 (V4SI "32") (V2DI "64")])
687
43e9d192
IB		 688(define_mode_attr Vmtype [(V8QI ".8b") (V16QI ".16b")
689 (V4HI ".4h") (V8HI ".8h")
690 (V2SI ".2s") (V4SI ".4s")
71a11456
AL		 691 (V2DI ".2d") (V4HF ".4h")
692 (V8HF ".8h") (V2SF ".2s")
43e9d192
IB		 693 (V4SF ".4s") (V2DF ".2d")
694 (DI "") (SI "")
695 (HI "") (QI "")
d7f33f07
JW		 696 (TI "") (HF "")
697 (SF "") (DF "")])
43e9d192
IB		 698
699;; Register suffix narrowed modes for VQN.
700(define_mode_attr Vmntype [(V8HI ".8b") (V4SI ".4h")
701 (V2DI ".2s")
702 (DI "") (SI "")
703 (HI "")])
704
705;; Mode-to-individual element type mapping.
43cacb12
RS		 706(define_mode_attr Vetype [(V8QI "b") (V16QI "b") (VNx16QI "b") (VNx16BI "b")
707 (V4HI "h") (V8HI "h") (VNx8HI "h") (VNx8BI "h")
708 (V2SI "s") (V4SI "s") (VNx4SI "s") (VNx4BI "s")
709 (V2DI "d") (VNx2DI "d") (VNx2BI "d")
710 (V4HF "h") (V8HF "h") (VNx8HF "h")
711 (V2SF "s") (V4SF "s") (VNx4SF "s")
712 (V2DF "d") (VNx2DF "d")
d7f33f07 713 (HF "h")
0f686aa9 714 (SF "s") (DF "d")
43e9d192
IB		 715 (QI "b") (HI "h")
716 (SI "s") (DI "d")])
717
9feeafd7
AM		 718;; Like Vetype, but map to types that are a quarter of the element size.
719(define_mode_attr Vetype_fourth [(VNx4SI "b") (VNx2DI "h")])
720
43cacb12
RS		 721;; Equivalent of "size" for a vector element.
722(define_mode_attr Vesize [(VNx16QI "b")
9f4cbab8
RS		 723 (VNx8HI "h") (VNx8HF "h")
724 (VNx4SI "w") (VNx4SF "w")
725 (VNx2DI "d") (VNx2DF "d")
726 (VNx32QI "b") (VNx48QI "b") (VNx64QI "b")
727 (VNx16HI "h") (VNx24HI "h") (VNx32HI "h")
728 (VNx16HF "h") (VNx24HF "h") (VNx32HF "h")
729 (VNx8SI "w") (VNx12SI "w") (VNx16SI "w")
730 (VNx8SF "w") (VNx12SF "w") (VNx16SF "w")
731 (VNx4DI "d") (VNx6DI "d") (VNx8DI "d")
732 (VNx4DF "d") (VNx6DF "d") (VNx8DF "d")])
43cacb12 733
daef0a8c
JW		 734;; Vetype is used everywhere in scheduling type and assembly output,
735;; sometimes they are not the same, for example HF modes on some
736;; instructions. stype is defined to represent scheduling type
737;; more accurately.
738(define_mode_attr stype [(V8QI "b") (V16QI "b") (V4HI "s") (V8HI "s")
739 (V2SI "s") (V4SI "s") (V2DI "d") (V4HF "s")
740 (V8HF "s") (V2SF "s") (V4SF "s") (V2DF "d")
741 (HF "s") (SF "s") (DF "d") (QI "b") (HI "s")
742 (SI "s") (DI "d")])
743
43e9d192
IB		 744;; Mode-to-bitwise operation type mapping.
745(define_mode_attr Vbtype [(V8QI "8b") (V16QI "16b")
746 (V4HI "8b") (V8HI "16b")
747 (V2SI "8b") (V4SI "16b")
7c369485
AL		 748 (V2DI "16b") (V4HF "8b")
749 (V8HF "16b") (V2SF "8b")
46e778c4 750 (V4SF "16b") (V2DF "16b")
fe82d1f2 751 (DI "8b") (DF "8b")
315fdae8 752 (SI "8b") (SF "8b")])
43e9d192
IB		 753
754;; Define element mode for each vector mode.
43cacb12
RS		 755(define_mode_attr VEL [(V8QI "QI") (V16QI "QI") (VNx16QI "QI")
756 (V4HI "HI") (V8HI "HI") (VNx8HI "HI")
757 (V2SI "SI") (V4SI "SI") (VNx4SI "SI")
758 (DI "DI") (V2DI "DI") (VNx2DI "DI")
759 (V4HF "HF") (V8HF "HF") (VNx8HF "HF")
760 (V2SF "SF") (V4SF "SF") (VNx4SF "SF")
761 (DF "DF") (V2DF "DF") (VNx2DF "DF")
762 (SI "SI") (HI "HI")
43e9d192
IB		 763 (QI "QI")])
764
ff03930a 765;; Define element mode for each vector mode (lower case).
43cacb12
RS		 766(define_mode_attr Vel [(V8QI "qi") (V16QI "qi") (VNx16QI "qi")
767 (V4HI "hi") (V8HI "hi") (VNx8HI "hi")
768 (V2SI "si") (V4SI "si") (VNx4SI "si")
769 (DI "di") (V2DI "di") (VNx2DI "di")
770 (V4HF "hf") (V8HF "hf") (VNx8HF "hf")
771 (V2SF "sf") (V4SF "sf") (VNx4SF "sf")
772 (V2DF "df") (DF "df") (VNx2DF "df")
ff03930a
JJ		 773 (SI "si") (HI "hi")
774 (QI "qi")])
775
43cacb12
RS		 776;; Element mode with floating-point values replaced by like-sized integers.
777(define_mode_attr VEL_INT [(VNx16QI "QI")
778 (VNx8HI "HI") (VNx8HF "HI")
779 (VNx4SI "SI") (VNx4SF "SI")
780 (VNx2DI "DI") (VNx2DF "DI")])
781
782;; Gives the mode of the 128-bit lowpart of an SVE vector.
783(define_mode_attr V128 [(VNx16QI "V16QI")
784 (VNx8HI "V8HI") (VNx8HF "V8HF")
785 (VNx4SI "V4SI") (VNx4SF "V4SF")
786 (VNx2DI "V2DI") (VNx2DF "V2DF")])
787
788;; ...and again in lower case.
789(define_mode_attr v128 [(VNx16QI "v16qi")
790 (VNx8HI "v8hi") (VNx8HF "v8hf")
791 (VNx4SI "v4si") (VNx4SF "v4sf")
792 (VNx2DI "v2di") (VNx2DF "v2df")])
793
278821f2
KT		 794;; 64-bit container modes the inner or scalar source mode.
795(define_mode_attr VCOND [(HI "V4HI") (SI "V2SI")
796 (V4HI "V4HI") (V8HI "V4HI")
b7d7d917
TB		 797 (V2SI "V2SI") (V4SI "V2SI")
798 (DI "DI") (V2DI "DI")
799 (V2SF "V2SF") (V4SF "V2SF")
800 (V2DF "DF")])
801
278821f2 802;; 128-bit container modes the inner or scalar source mode.
b7d7d917
TB		 803(define_mode_attr VCONQ [(V8QI "V16QI") (V16QI "V16QI")
804 (V4HI "V8HI") (V8HI "V8HI")
805 (V2SI "V4SI") (V4SI "V4SI")
806 (DI "V2DI") (V2DI "V2DI")
71a11456 807 (V4HF "V8HF") (V8HF "V8HF")
b7d7d917
TB		 808 (V2SF "V2SF") (V4SF "V4SF")
809 (V2DF "V2DF") (SI "V4SI")
810 (HI "V8HI") (QI "V16QI")])
811
43e9d192
IB		 812;; Half modes of all vector modes.
813(define_mode_attr VHALF [(V8QI "V4QI") (V16QI "V8QI")
814 (V4HI "V2HI") (V8HI "V4HI")
815 (V2SI "SI") (V4SI "V2SI")
816 (V2DI "DI") (V2SF "SF")
71a11456
AL		 817 (V4SF "V2SF") (V4HF "V2HF")
818 (V8HF "V4HF") (V2DF "DF")])
43e9d192 819
b1b49824
MC		 820;; Half modes of all vector modes, in lower-case.
821(define_mode_attr Vhalf [(V8QI "v4qi") (V16QI "v8qi")
822 (V4HI "v2hi") (V8HI "v4hi")
41dab855 823 (V8HF "v4hf")
b1b49824
MC		 824 (V2SI "si") (V4SI "v2si")
825 (V2DI "di") (V2SF "sf")
826 (V4SF "v2sf") (V2DF "df")])
827
43e9d192
IB		 828;; Double modes of vector modes.
829(define_mode_attr VDBL [(V8QI "V16QI") (V4HI "V8HI")
71a11456 830 (V4HF "V8HF")
43e9d192
IB		 831 (V2SI "V4SI") (V2SF "V4SF")
832 (SI "V2SI") (DI "V2DI")
833 (DF "V2DF")])
834
922f9c25
AL		 835;; Register suffix for double-length mode.
836(define_mode_attr Vdtype [(V4HF "8h") (V2SF "4s")])
837
43e9d192
IB		 838;; Double modes of vector modes (lower case).
839(define_mode_attr Vdbl [(V8QI "v16qi") (V4HI "v8hi")
7c369485 840 (V4HF "v8hf")
43e9d192 841 (V2SI "v4si") (V2SF "v4sf")
8b033a8a
SN		 842 (SI "v2si") (DI "v2di")
843 (DF "v2df")])
43e9d192 844
b1b49824
MC		 845;; Modes with double-width elements.
846(define_mode_attr VDBLW [(V8QI "V4HI") (V16QI "V8HI")
847 (V4HI "V2SI") (V8HI "V4SI")
848 (V2SI "DI") (V4SI "V2DI")])
849
43e9d192
IB		 850;; Narrowed modes for VDN.
851(define_mode_attr VNARROWD [(V4HI "V8QI") (V2SI "V4HI")
852 (DI "V2SI")])
853
854;; Narrowed double-modes for VQN (Used for XTN).
855(define_mode_attr VNARROWQ [(V8HI "V8QI") (V4SI "V4HI")
856 (V2DI "V2SI")
857 (DI "SI") (SI "HI")
858 (HI "QI")])
859
860;; Narrowed quad-modes for VQN (Used for XTN2).
861(define_mode_attr VNARROWQ2 [(V8HI "V16QI") (V4SI "V8HI")
862 (V2DI "V4SI")])
863
864;; Register suffix narrowed modes for VQN.
865(define_mode_attr Vntype [(V8HI "8b") (V4SI "4h")
866 (V2DI "2s")])
867
868;; Register suffix narrowed modes for VQN.
869(define_mode_attr V2ntype [(V8HI "16b") (V4SI "8h")
870 (V2DI "4s")])
871
872;; Widened modes of vector modes.
43cacb12
RS		 873(define_mode_attr VWIDE [(V8QI "V8HI") (V4HI "V4SI")
874 (V2SI "V2DI") (V16QI "V8HI")
875 (V8HI "V4SI") (V4SI "V2DI")
876 (HI "SI") (SI "DI")
877 (V8HF "V4SF") (V4SF "V2DF")
878 (V4HF "V4SF") (V2SF "V2DF")
879 (VNx8HF "VNx4SF") (VNx4SF "VNx2DF")
880 (VNx16QI "VNx8HI") (VNx8HI "VNx4SI")
881 (VNx4SI "VNx2DI")
882 (VNx16BI "VNx8BI") (VNx8BI "VNx4BI")
883 (VNx4BI "VNx2BI")])
884
885;; Predicate mode associated with VWIDE.
886(define_mode_attr VWIDE_PRED [(VNx8HF "VNx4BI") (VNx4SF "VNx2BI")])
43e9d192 887
03873eb9 888;; Widened modes of vector modes, lowercase
43cacb12
RS		 889(define_mode_attr Vwide [(V2SF "v2df") (V4HF "v4sf")
890 (VNx16QI "vnx8hi") (VNx8HI "vnx4si")
891 (VNx4SI "vnx2di")
892 (VNx8HF "vnx4sf") (VNx4SF "vnx2df")
893 (VNx16BI "vnx8bi") (VNx8BI "vnx4bi")
894 (VNx4BI "vnx2bi")])
03873eb9
AL		 895
896;; Widened mode register suffixes for VD_BHSI/VQW/VQ_HSF.
43e9d192
IB		 897(define_mode_attr Vwtype [(V8QI "8h") (V4HI "4s")
898 (V2SI "2d") (V16QI "8h")
03873eb9
AL		 899 (V8HI "4s") (V4SI "2d")
900 (V8HF "4s") (V4SF "2d")])
43e9d192 901
43cacb12
RS		 902;; SVE vector after widening
903(define_mode_attr Vewtype [(VNx16QI "h")
904 (VNx8HI "s") (VNx8HF "s")
905 (VNx4SI "d") (VNx4SF "d")])
906
43e9d192
IB		 907;; Widened mode register suffixes for VDW/VQW.
908(define_mode_attr Vmwtype [(V8QI ".8h") (V4HI ".4s")
909 (V2SI ".2d") (V16QI ".8h")
910 (V8HI ".4s") (V4SI ".2d")
922f9c25 911 (V4HF ".4s") (V2SF ".2d")
43e9d192
IB		 912 (SI "") (HI "")])
913
03873eb9 914;; Lower part register suffixes for VQW/VQ_HSF.
43e9d192 915(define_mode_attr Vhalftype [(V16QI "8b") (V8HI "4h")
03873eb9
AL		 916 (V4SI "2s") (V8HF "4h")
917 (V4SF "2s")])
43e9d192
IB		 918
919;; Define corresponding core/FP element mode for each vector mode.
43cacb12
RS		 920(define_mode_attr vw [(V8QI "w") (V16QI "w") (VNx16QI "w")
921 (V4HI "w") (V8HI "w") (VNx8HI "w")
922 (V2SI "w") (V4SI "w") (VNx4SI "w")
923 (DI "x") (V2DI "x") (VNx2DI "x")
924 (VNx8HF "h")
925 (V2SF "s") (V4SF "s") (VNx4SF "s")
926 (V2DF "d") (VNx2DF "d")])
43e9d192 927
66adb8eb
JG		 928;; Corresponding core element mode for each vector mode. This is a
929;; variation on <vw> mapping FP modes to GP regs.
43cacb12
RS		 930(define_mode_attr vwcore [(V8QI "w") (V16QI "w") (VNx16QI "w")
931 (V4HI "w") (V8HI "w") (VNx8HI "w")
932 (V2SI "w") (V4SI "w") (VNx4SI "w")
933 (DI "x") (V2DI "x") (VNx2DI "x")
934 (V4HF "w") (V8HF "w") (VNx8HF "w")
935 (V2SF "w") (V4SF "w") (VNx4SF "w")
936 (V2DF "x") (VNx2DF "x")])
66adb8eb 937
43e9d192
IB		 938;; Double vector types for ALLX.
939(define_mode_attr Vallxd [(QI "8b") (HI "4h") (SI "2s")])
940
5f565314
RS		 941;; Mode with floating-point values replaced by like-sized integers.
942(define_mode_attr V_INT_EQUIV [(V8QI "V8QI") (V16QI "V16QI")
943 (V4HI "V4HI") (V8HI "V8HI")
944 (V2SI "V2SI") (V4SI "V4SI")
945 (DI "DI") (V2DI "V2DI")
946 (V4HF "V4HI") (V8HF "V8HI")
947 (V2SF "V2SI") (V4SF "V4SI")
43cacb12 948 (DF "DI") (V2DF "V2DI")
dfe1da23
JW		 949 (SF "SI") (SI "SI")
950 (HF "HI")
43cacb12
RS		 951 (VNx16QI "VNx16QI")
952 (VNx8HI "VNx8HI") (VNx8HF "VNx8HI")
953 (VNx4SI "VNx4SI") (VNx4SF "VNx4SI")
954 (VNx2DI "VNx2DI") (VNx2DF "VNx2DI")
955])
5f565314
RS		 956
957;; Lower case mode with floating-point values replaced by like-sized integers.
958(define_mode_attr v_int_equiv [(V8QI "v8qi") (V16QI "v16qi")
959 (V4HI "v4hi") (V8HI "v8hi")
960 (V2SI "v2si") (V4SI "v4si")
961 (DI "di") (V2DI "v2di")
962 (V4HF "v4hi") (V8HF "v8hi")
963 (V2SF "v2si") (V4SF "v4si")
43cacb12
RS		 964 (DF "di") (V2DF "v2di")
965 (SF "si")
966 (VNx16QI "vnx16qi")
967 (VNx8HI "vnx8hi") (VNx8HF "vnx8hi")
968 (VNx4SI "vnx4si") (VNx4SF "vnx4si")
969 (VNx2DI "vnx2di") (VNx2DF "vnx2di")
970])
971
972;; Floating-point equivalent of selected modes.
a70965b1
RS		 973(define_mode_attr V_FP_EQUIV [(VNx8HI "VNx8HF") (VNx8HF "VNx8HF")
974 (VNx4SI "VNx4SF") (VNx4SF "VNx4SF")
43cacb12 975 (VNx2DI "VNx2DF") (VNx2DF "VNx2DF")])
a70965b1
RS		 976(define_mode_attr v_fp_equiv [(VNx8HI "vnx8hf") (VNx8HF "vnx8hf")
977 (VNx4SI "vnx4sf") (VNx4SF "vnx4sf")
43cacb12 978 (VNx2DI "vnx2df") (VNx2DF "vnx2df")])
70c67693 979
6c553b76
BC		 980;; Mode for vector conditional operations where the comparison has
981;; different type from the lhs.
982(define_mode_attr V_cmp_mixed [(V2SI "V2SF") (V4SI "V4SF")
983 (V2DI "V2DF") (V2SF "V2SI")
984 (V4SF "V4SI") (V2DF "V2DI")])
985
986(define_mode_attr v_cmp_mixed [(V2SI "v2sf") (V4SI "v4sf")
987 (V2DI "v2df") (V2SF "v2si")
988 (V4SF "v4si") (V2DF "v2di")])
989
cb23a30c
JG		 990;; Lower case element modes (as used in shift immediate patterns).
991(define_mode_attr ve_mode [(V8QI "qi") (V16QI "qi")
992 (V4HI "hi") (V8HI "hi")
993 (V2SI "si") (V4SI "si")
994 (DI "di") (V2DI "di")
995 (QI "qi") (HI "hi")
996 (SI "si")])
997
43e9d192
IB		 998;; Vm for lane instructions is restricted to FP_LO_REGS.
999(define_mode_attr vwx [(V4HI "x") (V8HI "x") (HI "x")
1000 (V2SI "w") (V4SI "w") (SI "w")])
1001
1002(define_mode_attr Vendreg [(OI "T") (CI "U") (XI "V")])
1003
97755701
AL		 1004;; This is both the number of Q-Registers needed to hold the corresponding
1005;; opaque large integer mode, and the number of elements touched by the
1006;; ld..._lane and st..._lane operations.
43e9d192
IB		 1007(define_mode_attr nregs [(OI "2") (CI "3") (XI "4")])
1008
0462169c
SN		 1009;; Mode for atomic operation suffixes
1010(define_mode_attr atomic_sfx
1011 [(QI "b") (HI "h") (SI "") (DI "")])
1012
3f598afe 1013(define_mode_attr fcvt_target [(V2DF "v2di") (V4SF "v4si") (V2SF "v2si")
2644d4d9 1014 (V2DI "v2df") (V4SI "v4sf") (V2SI "v2sf")
daef0a8c
JW		 1015 (SF "si") (DF "di") (SI "sf") (DI "df")
1016 (V4HF "v4hi") (V8HF "v8hi") (V4HI "v4hf")
68ad28c3 1017 (V8HI "v8hf") (HF "hi") (HI "hf")])
3f598afe 1018(define_mode_attr FCVT_TARGET [(V2DF "V2DI") (V4SF "V4SI") (V2SF "V2SI")
2644d4d9 1019 (V2DI "V2DF") (V4SI "V4SF") (V2SI "V2SF")
daef0a8c
JW		 1020 (SF "SI") (DF "DI") (SI "SF") (DI "DF")
1021 (V4HF "V4HI") (V8HF "V8HI") (V4HI "V4HF")
68ad28c3 1022 (V8HI "V8HF") (HF "HI") (HI "HF")])
3f598afe 1023
0d35c5c2
VP		 1024
1025;; for the inequal width integer to fp conversions
d7f33f07
JW		 1026(define_mode_attr fcvt_iesize [(HF "di") (SF "di") (DF "si")])
1027(define_mode_attr FCVT_IESIZE [(HF "DI") (SF "DI") (DF "SI")])
42fc9a7f 1028
91bd4114
JG		 1029(define_mode_attr VSWAP_WIDTH [(V8QI "V16QI") (V16QI "V8QI")
1030 (V4HI "V8HI") (V8HI "V4HI")
1031 (V2SI "V4SI") (V4SI "V2SI")
1032 (DI "V2DI") (V2DI "DI")
1033 (V2SF "V4SF") (V4SF "V2SF")
862abc04 1034 (V4HF "V8HF") (V8HF "V4HF")
91bd4114
JG		 1035 (DF "V2DF") (V2DF "DF")])
1036
1037(define_mode_attr vswap_width_name [(V8QI "to_128") (V16QI "to_64")
1038 (V4HI "to_128") (V8HI "to_64")
1039 (V2SI "to_128") (V4SI "to_64")
1040 (DI "to_128") (V2DI "to_64")
862abc04 1041 (V4HF "to_128") (V8HF "to_64")
91bd4114
JG		 1042 (V2SF "to_128") (V4SF "to_64")
1043 (DF "to_128") (V2DF "to_64")])
1044
779aea46 1045;; For certain vector-by-element multiplication instructions we must
6d06971d 1046;; constrain the 16-bit cases to use only V0-V15. This is covered by
779aea46
JG		 1047;; the 'x' constraint. All other modes may use the 'w' constraint.
1048(define_mode_attr h_con [(V2SI "w") (V4SI "w")
1049 (V4HI "x") (V8HI "x")
6d06971d 1050 (V4HF "x") (V8HF "x")
779aea46
JG		 1051 (V2SF "w") (V4SF "w")
1052 (V2DF "w") (DF "w")])
1053
1054;; Defined to 'f' for types whose element type is a float type.
1055(define_mode_attr f [(V8QI "") (V16QI "")
1056 (V4HI "") (V8HI "")
1057 (V2SI "") (V4SI "")
1058 (DI "") (V2DI "")
ab2e8f01 1059 (V4HF "f") (V8HF "f")
779aea46
JG		 1060 (V2SF "f") (V4SF "f")
1061 (V2DF "f") (DF "f")])
1062
0f686aa9
JG		 1063;; Defined to '_fp' for types whose element type is a float type.
1064(define_mode_attr fp [(V8QI "") (V16QI "")
1065 (V4HI "") (V8HI "")
1066 (V2SI "") (V4SI "")
1067 (DI "") (V2DI "")
ab2e8f01 1068 (V4HF "_fp") (V8HF "_fp")
0f686aa9
JG		 1069 (V2SF "_fp") (V4SF "_fp")
1070 (V2DF "_fp") (DF "_fp")
1071 (SF "_fp")])
1072
a9e66678
JG		 1073;; Defined to '_q' for 128-bit types.
1074(define_mode_attr q [(V8QI "") (V16QI "_q")
0f686aa9
JG		 1075 (V4HI "") (V8HI "_q")
1076 (V2SI "") (V4SI "_q")
1077 (DI "") (V2DI "_q")
71a11456 1078 (V4HF "") (V8HF "_q")
0f686aa9
JG		 1079 (V2SF "") (V4SF "_q")
1080 (V2DF "_q")
d7f33f07 1081 (QI "") (HI "") (SI "") (DI "") (HF "") (SF "") (DF "")])
a9e66678 1082
92835317
TB		 1083(define_mode_attr vp [(V8QI "v") (V16QI "v")
1084 (V4HI "v") (V8HI "v")
1085 (V2SI "p") (V4SI "v")
703bbcdf
JW		 1086 (V2DI "p") (V2DF "p")
1087 (V2SF "p") (V4SF "v")
1088 (V4HF "v") (V8HF "v")])
92835317 1089
9feeafd7
AM		 1090(define_mode_attr vsi2qi [(V2SI "v8qi") (V4SI "v16qi")
1091 (VNx4SI "vnx16qi") (VNx2DI "vnx8hi")])
1092(define_mode_attr VSI2QI [(V2SI "V8QI") (V4SI "V16QI")
1093 (VNx4SI "VNx16QI") (VNx2DI "VNx8HI")])
5e32e83b 1094
7a08d813
TC		 1095
1096;; Register suffix for DOTPROD input types from the return type.
1097(define_mode_attr Vdottype [(V2SI "8b") (V4SI "16b")])
1098
cd78b3dd 1099;; Sum of lengths of instructions needed to move vector registers of a mode.
668046d1
DS		 1100(define_mode_attr insn_count [(OI "8") (CI "12") (XI "16")])
1101
1b1e81f8
JW		 1102;; -fpic small model GOT reloc modifers: gotpage_lo15/lo14 for ILP64/32.
1103;; No need of iterator for -fPIC as it use got_lo12 for both modes.
1104(define_mode_attr got_modifier [(SI "gotpage_lo14") (DI "gotpage_lo15")])
1105
27086ea3
MC		 1106;; Width of 2nd and 3rd arguments to fp16 vector multiply add/sub
1107(define_mode_attr VFMLA_W [(V2SF "V4HF") (V4SF "V8HF")])
1108
1109(define_mode_attr VFMLA_SEL_W [(V2SF "V2HF") (V4SF "V4HF")])
1110
1111(define_mode_attr f16quad [(V2SF "") (V4SF "q")])
1112
1113(define_code_attr f16mac [(plus "a") (minus "s")])
1114
8544ed6e
KT		 1115;; Map smax to smin and umax to umin.
1116(define_code_attr max_opp [(smax "smin") (umax "umin")])
1117
a9fad8fe
AM		 1118;; Same as above, but louder.
1119(define_code_attr MAX_OPP [(smax "SMIN") (umax "UMIN")])
1120
9f4cbab8
RS		 1121;; The number of subvectors in an SVE_STRUCT.
1122(define_mode_attr vector_count [(VNx32QI "2") (VNx16HI "2")
1123 (VNx8SI "2") (VNx4DI "2")
1124 (VNx16HF "2") (VNx8SF "2") (VNx4DF "2")
1125 (VNx48QI "3") (VNx24HI "3")
1126 (VNx12SI "3") (VNx6DI "3")
1127 (VNx24HF "3") (VNx12SF "3") (VNx6DF "3")
1128 (VNx64QI "4") (VNx32HI "4")
1129 (VNx16SI "4") (VNx8DI "4")
1130 (VNx32HF "4") (VNx16SF "4") (VNx8DF "4")])
1131
1132;; The number of instruction bytes needed for an SVE_STRUCT move. This is
1133;; equal to vector_count * 4.
1134(define_mode_attr insn_length [(VNx32QI "8") (VNx16HI "8")
1135 (VNx8SI "8") (VNx4DI "8")
1136 (VNx16HF "8") (VNx8SF "8") (VNx4DF "8")
1137 (VNx48QI "12") (VNx24HI "12")
1138 (VNx12SI "12") (VNx6DI "12")
1139 (VNx24HF "12") (VNx12SF "12") (VNx6DF "12")
1140 (VNx64QI "16") (VNx32HI "16")
1141 (VNx16SI "16") (VNx8DI "16")
1142 (VNx32HF "16") (VNx16SF "16") (VNx8DF "16")])
1143
1144;; The type of a subvector in an SVE_STRUCT.
1145(define_mode_attr VSINGLE [(VNx32QI "VNx16QI")
1146 (VNx16HI "VNx8HI") (VNx16HF "VNx8HF")
1147 (VNx8SI "VNx4SI") (VNx8SF "VNx4SF")
1148 (VNx4DI "VNx2DI") (VNx4DF "VNx2DF")
1149 (VNx48QI "VNx16QI")
1150 (VNx24HI "VNx8HI") (VNx24HF "VNx8HF")
1151 (VNx12SI "VNx4SI") (VNx12SF "VNx4SF")
1152 (VNx6DI "VNx2DI") (VNx6DF "VNx2DF")
1153 (VNx64QI "VNx16QI")
1154 (VNx32HI "VNx8HI") (VNx32HF "VNx8HF")
1155 (VNx16SI "VNx4SI") (VNx16SF "VNx4SF")
1156 (VNx8DI "VNx2DI") (VNx8DF "VNx2DF")])
1157
1158;; ...and again in lower case.
1159(define_mode_attr vsingle [(VNx32QI "vnx16qi")
1160 (VNx16HI "vnx8hi") (VNx16HF "vnx8hf")
1161 (VNx8SI "vnx4si") (VNx8SF "vnx4sf")
1162 (VNx4DI "vnx2di") (VNx4DF "vnx2df")
1163 (VNx48QI "vnx16qi")
1164 (VNx24HI "vnx8hi") (VNx24HF "vnx8hf")
1165 (VNx12SI "vnx4si") (VNx12SF "vnx4sf")
1166 (VNx6DI "vnx2di") (VNx6DF "vnx2df")
1167 (VNx64QI "vnx16qi")
1168 (VNx32HI "vnx8hi") (VNx32HF "vnx8hf")
1169 (VNx16SI "vnx4si") (VNx16SF "vnx4sf")
1170 (VNx8DI "vnx2di") (VNx8DF "vnx2df")])
1171
1172;; The predicate mode associated with an SVE data mode. For structure modes
1173;; this is equivalent to the <VPRED> of the subvector mode.
43cacb12
RS		 1174(define_mode_attr VPRED [(VNx16QI "VNx16BI")
1175 (VNx8HI "VNx8BI") (VNx8HF "VNx8BI")
1176 (VNx4SI "VNx4BI") (VNx4SF "VNx4BI")
9f4cbab8
RS		 1177 (VNx2DI "VNx2BI") (VNx2DF "VNx2BI")
1178 (VNx32QI "VNx16BI")
1179 (VNx16HI "VNx8BI") (VNx16HF "VNx8BI")
1180 (VNx8SI "VNx4BI") (VNx8SF "VNx4BI")
1181 (VNx4DI "VNx2BI") (VNx4DF "VNx2BI")
1182 (VNx48QI "VNx16BI")
1183 (VNx24HI "VNx8BI") (VNx24HF "VNx8BI")
1184 (VNx12SI "VNx4BI") (VNx12SF "VNx4BI")
1185 (VNx6DI "VNx2BI") (VNx6DF "VNx2BI")
1186 (VNx64QI "VNx16BI")
1187 (VNx32HI "VNx8BI") (VNx32HF "VNx8BI")
1188 (VNx16SI "VNx4BI") (VNx16SF "VNx4BI")
1189 (VNx8DI "VNx2BI") (VNx8DF "VNx2BI")])
43cacb12
RS		 1190
1191;; ...and again in lower case.
1192(define_mode_attr vpred [(VNx16QI "vnx16bi")
1193 (VNx8HI "vnx8bi") (VNx8HF "vnx8bi")
1194 (VNx4SI "vnx4bi") (VNx4SF "vnx4bi")
9f4cbab8
RS		 1195 (VNx2DI "vnx2bi") (VNx2DF "vnx2bi")
1196 (VNx32QI "vnx16bi")
1197 (VNx16HI "vnx8bi") (VNx16HF "vnx8bi")
1198 (VNx8SI "vnx4bi") (VNx8SF "vnx4bi")
1199 (VNx4DI "vnx2bi") (VNx4DF "vnx2bi")
1200 (VNx48QI "vnx16bi")
1201 (VNx24HI "vnx8bi") (VNx24HF "vnx8bi")
1202 (VNx12SI "vnx4bi") (VNx12SF "vnx4bi")
1203 (VNx6DI "vnx2bi") (VNx6DF "vnx2bi")
1204 (VNx64QI "vnx16bi")
1205 (VNx32HI "vnx8bi") (VNx32HF "vnx4bi")
1206 (VNx16SI "vnx4bi") (VNx16SF "vnx4bi")
1207 (VNx8DI "vnx2bi") (VNx8DF "vnx2bi")])
43cacb12 1208
9d63f43b
TC		 1209;; On AArch64 the By element instruction doesn't have a 2S variant.
1210;; However because the instruction always selects a pair of values
1211;; The normal 3SAME instruction can be used here instead.
1212(define_mode_attr FCMLA_maybe_lane [(V2SF "<Vtype>") (V4SF "<Vetype>[%4]")
1213 (V4HF "<Vetype>[%4]") (V8HF "<Vetype>[%4]")
1214 ])
1215
34467289
RS		 1216;; The number of bytes controlled by a predicate
1217(define_mode_attr data_bytes [(VNx16BI "1") (VNx8BI "2")
1218 (VNx4BI "4") (VNx2BI "8")])
1219
43e9d192
IB		 1220;; -------------------------------------------------------------------
1221;; Code Iterators
1222;; -------------------------------------------------------------------
1223
1224;; This code iterator allows the various shifts supported on the core
1225(define_code_iterator SHIFT [ashift ashiftrt lshiftrt rotatert])
1226
1227;; This code iterator allows the shifts supported in arithmetic instructions
1228(define_code_iterator ASHIFT [ashift ashiftrt lshiftrt])
1229
462e6f9a
ST		 1230(define_code_iterator SHIFTRT [ashiftrt lshiftrt])
1231
43e9d192
IB		 1232;; Code iterator for logical operations
1233(define_code_iterator LOGICAL [and ior xor])
1234
43cacb12
RS		 1235;; LOGICAL without AND.
1236(define_code_iterator LOGICAL_OR [ior xor])
1237
84be6032
AL		 1238;; Code iterator for logical operations whose :nlogical works on SIMD registers.
1239(define_code_iterator NLOGICAL [and ior])
1240
3204ac98
KT		 1241;; Code iterator for unary negate and bitwise complement.
1242(define_code_iterator NEG_NOT [neg not])
1243
43e9d192
IB		 1244;; Code iterator for sign/zero extension
1245(define_code_iterator ANY_EXTEND [sign_extend zero_extend])
1246
1247;; All division operations (signed/unsigned)
1248(define_code_iterator ANY_DIV [div udiv])
1249
1250;; Code iterator for sign/zero extraction
1251(define_code_iterator ANY_EXTRACT [sign_extract zero_extract])
1252
1253;; Code iterator for equality comparisons
1254(define_code_iterator EQL [eq ne])
1255
1256;; Code iterator for less-than and greater/equal-to
1257(define_code_iterator LTGE [lt ge])
1258
1259;; Iterator for __sync_<op> operations that where the operation can be
1260;; represented directly RTL. This is all of the sync operations bar
1261;; nand.
0462169c 1262(define_code_iterator atomic_op [plus minus ior xor and])
43e9d192
IB		 1263
1264;; Iterator for integer conversions
1265(define_code_iterator FIXUORS [fix unsigned_fix])
1266
1709ff9b
JG		 1267;; Iterator for float conversions
1268(define_code_iterator FLOATUORS [float unsigned_float])
1269
43e9d192
IB		 1270;; Code iterator for variants of vector max and min.
1271(define_code_iterator MAXMIN [smax smin umax umin])
1272
998eaf97
JG		 1273(define_code_iterator FMAXMIN [smax smin])
1274
8544ed6e
KT		 1275;; Signed and unsigned max operations.
1276(define_code_iterator USMAX [smax umax])
1277
dd550c99 1278;; Code iterator for plus and minus.
43e9d192
IB		 1279(define_code_iterator ADDSUB [plus minus])
1280
1281;; Code iterator for variants of vector saturating binary ops.
1282(define_code_iterator BINQOPS [ss_plus us_plus ss_minus us_minus])
1283
1284;; Code iterator for variants of vector saturating unary ops.
1285(define_code_iterator UNQOPS [ss_neg ss_abs])
1286
1287;; Code iterator for signed variants of vector saturating binary ops.
1288(define_code_iterator SBINQOPS [ss_plus ss_minus])
1289
889b9412
JG		 1290;; Comparison operators for <F>CM.
1291(define_code_iterator COMPARISONS [lt le eq ge gt])
1292
1293;; Unsigned comparison operators.
1294(define_code_iterator UCOMPARISONS [ltu leu geu gtu])
1295
75dd5ace
JG		 1296;; Unsigned comparison operators.
1297(define_code_iterator FAC_COMPARISONS [lt le ge gt])
1298
43cacb12 1299;; SVE integer unary operations.
bca5a997 1300(define_code_iterator SVE_INT_UNARY [abs neg not clrsb clz popcount])
43cacb12 1301
a08acce8 1302;; SVE integer binary operations.
6c4fd4a9 1303(define_code_iterator SVE_INT_BINARY [plus minus mult smax umax smin umin
20103c0e 1304 ashift ashiftrt lshiftrt
9d4ac06e
RS		 1305 and ior xor])
1306
a08acce8 1307;; SVE integer binary division operations.
c38f7319
RS		 1308(define_code_iterator SVE_INT_BINARY_SD [div udiv])
1309
f8c22a8b
RS		 1310;; SVE integer binary operations that have an immediate form.
1311(define_code_iterator SVE_INT_BINARY_IMM [mult smax smin umax umin])
1312
740c1ed7
RS		 1313;; SVE floating-point operations with an unpredicated all-register form.
1314(define_code_iterator SVE_UNPRED_FP_BINARY [plus minus mult])
1315
f22d7973
RS		 1316;; SVE integer comparisons.
1317(define_code_iterator SVE_INT_CMP [lt le eq ne ge gt ltu leu geu gtu])
1318
43e9d192
IB		 1319;; -------------------------------------------------------------------
1320;; Code Attributes
1321;; -------------------------------------------------------------------
1322;; Map rtl objects to optab names
1323(define_code_attr optab [(ashift "ashl")
1324 (ashiftrt "ashr")
1325 (lshiftrt "lshr")
1326 (rotatert "rotr")
1327 (sign_extend "extend")
1328 (zero_extend "zero_extend")
1329 (sign_extract "extv")
1330 (zero_extract "extzv")
384be29f
JG		 1331 (fix "fix")
1332 (unsigned_fix "fixuns")
1709ff9b
JG		 1333 (float "float")
1334 (unsigned_float "floatuns")
bca5a997
RS		 1335 (clrsb "clrsb")
1336 (clz "clz")
43cacb12 1337 (popcount "popcount")
43e9d192
IB		 1338 (and "and")
1339 (ior "ior")
1340 (xor "xor")
1341 (not "one_cmpl")
1342 (neg "neg")
1343 (plus "add")
1344 (minus "sub")
6c4fd4a9 1345 (mult "mul")
c38f7319
RS		 1346 (div "div")
1347 (udiv "udiv")
43e9d192
IB		 1348 (ss_plus "qadd")
1349 (us_plus "qadd")
1350 (ss_minus "qsub")
1351 (us_minus "qsub")
1352 (ss_neg "qneg")
1353 (ss_abs "qabs")
43cacb12
RS		 1354 (smin "smin")
1355 (smax "smax")
1356 (umin "umin")
1357 (umax "umax")
43e9d192
IB		 1358 (eq "eq")
1359 (ne "ne")
1360 (lt "lt")
889b9412
JG		 1361 (ge "ge")
1362 (le "le")
1363 (gt "gt")
1364 (ltu "ltu")
1365 (leu "leu")
1366 (geu "geu")
43cacb12 1367 (gtu "gtu")
d45b20a5 1368 (abs "abs")])
889b9412
JG		 1369
1370;; For comparison operators we use the FCM* and CM* instructions.
1371;; As there are no CMLE or CMLT instructions which act on 3 vector
1372;; operands, we must use CMGE or CMGT and swap the order of the
1373;; source operands.
1374
1375(define_code_attr n_optab [(lt "gt") (le "ge") (eq "eq") (ge "ge") (gt "gt")
1376 (ltu "hi") (leu "hs") (geu "hs") (gtu "hi")])
1377(define_code_attr cmp_1 [(lt "2") (le "2") (eq "1") (ge "1") (gt "1")
1378 (ltu "2") (leu "2") (geu "1") (gtu "1")])
1379(define_code_attr cmp_2 [(lt "1") (le "1") (eq "2") (ge "2") (gt "2")
1380 (ltu "1") (leu "1") (geu "2") (gtu "2")])
1381
1382(define_code_attr CMP [(lt "LT") (le "LE") (eq "EQ") (ge "GE") (gt "GT")
714e1b3b
KT		 1383 (ltu "LTU") (leu "LEU") (ne "NE") (geu "GEU")
1384 (gtu "GTU")])
43e9d192 1385
f22d7973
RS		 1386;; The AArch64 condition associated with an rtl comparison code.
1387(define_code_attr cmp_op [(lt "lt")
1388 (le "le")
1389 (eq "eq")
1390 (ne "ne")
1391 (ge "ge")
1392 (gt "gt")
1393 (ltu "lo")
1394 (leu "ls")
1395 (geu "hs")
1396 (gtu "hi")])
1397
384be29f
JG		 1398(define_code_attr fix_trunc_optab [(fix "fix_trunc")
1399 (unsigned_fix "fixuns_trunc")])
1400
43e9d192
IB		 1401;; Optab prefix for sign/zero-extending operations
1402(define_code_attr su_optab [(sign_extend "") (zero_extend "u")
1403 (div "") (udiv "u")
1404 (fix "") (unsigned_fix "u")
1709ff9b 1405 (float "s") (unsigned_float "u")
43e9d192
IB		 1406 (ss_plus "s") (us_plus "u")
1407 (ss_minus "s") (us_minus "u")])
1408
1409;; Similar for the instruction mnemonics
1410(define_code_attr shift [(ashift "lsl") (ashiftrt "asr")
1411 (lshiftrt "lsr") (rotatert "ror")])
1412
462e6f9a
ST		 1413;; Op prefix for shift right and accumulate.
1414(define_code_attr sra_op [(ashiftrt "s") (lshiftrt "u")])
1415
43e9d192
IB		 1416;; Map shift operators onto underlying bit-field instructions
1417(define_code_attr bfshift [(ashift "ubfiz") (ashiftrt "sbfx")
1418 (lshiftrt "ubfx") (rotatert "extr")])
1419
1420;; Logical operator instruction mnemonics
1421(define_code_attr logical [(and "and") (ior "orr") (xor "eor")])
1422
3204ac98
KT		 1423;; Operation names for negate and bitwise complement.
1424(define_code_attr neg_not_op [(neg "neg") (not "not")])
1425
43cacb12 1426;; Similar, but when the second operand is inverted.
43e9d192
IB		 1427(define_code_attr nlogical [(and "bic") (ior "orn") (xor "eon")])
1428
43cacb12
RS		 1429;; Similar, but when both operands are inverted.
1430(define_code_attr logical_nn [(and "nor") (ior "nand")])
1431
43e9d192
IB		 1432;; Sign- or zero-extending data-op
1433(define_code_attr su [(sign_extend "s") (zero_extend "u")
1434 (sign_extract "s") (zero_extract "u")
1435 (fix "s") (unsigned_fix "u")
998eaf97
JG		 1436 (div "s") (udiv "u")
1437 (smax "s") (umax "u")
1438 (smin "s") (umin "u")])
43e9d192 1439
43cacb12
RS		 1440;; Whether a shift is left or right.
1441(define_code_attr lr [(ashift "l") (ashiftrt "r") (lshiftrt "r")])
1442
096e8448
JW		 1443;; Emit conditional branch instructions.
1444(define_code_attr bcond [(eq "beq") (ne "bne") (lt "bne") (ge "beq")])
1445
43e9d192
IB		 1446;; Emit cbz/cbnz depending on comparison type.
1447(define_code_attr cbz [(eq "cbz") (ne "cbnz") (lt "cbnz") (ge "cbz")])
1448
973d2e01
TP		 1449;; Emit inverted cbz/cbnz depending on comparison type.
1450(define_code_attr inv_cb [(eq "cbnz") (ne "cbz") (lt "cbz") (ge "cbnz")])
1451
43e9d192
IB		 1452;; Emit tbz/tbnz depending on comparison type.
1453(define_code_attr tbz [(eq "tbz") (ne "tbnz") (lt "tbnz") (ge "tbz")])
1454
973d2e01
TP		 1455;; Emit inverted tbz/tbnz depending on comparison type.
1456(define_code_attr inv_tb [(eq "tbnz") (ne "tbz") (lt "tbz") (ge "tbnz")])
1457
43e9d192 1458;; Max/min attributes.
998eaf97
JG		 1459(define_code_attr maxmin [(smax "max")
1460 (smin "min")
1461 (umax "max")
1462 (umin "min")])
43e9d192
IB		 1463
1464;; MLA/MLS attributes.
1465(define_code_attr as [(ss_plus "a") (ss_minus "s")])
1466
0462169c
SN		 1467;; Atomic operations
1468(define_code_attr atomic_optab
1469 [(ior "or") (xor "xor") (and "and") (plus "add") (minus "sub")])
1470
1471(define_code_attr atomic_op_operand
1472 [(ior "aarch64_logical_operand")
1473 (xor "aarch64_logical_operand")
1474 (and "aarch64_logical_operand")
1475 (plus "aarch64_plus_operand")
1476 (minus "aarch64_plus_operand")])
43e9d192 1477
356c32e2
MW		 1478;; Constants acceptable for atomic operations.
1479;; This definition must appear in this file before the iterators it refers to.
1480(define_code_attr const_atomic
1481 [(plus "IJ") (minus "IJ")
1482 (xor "<lconst_atomic>") (ior "<lconst_atomic>")
1483 (and "<lconst_atomic>")])
1484
1485;; Attribute to describe constants acceptable in atomic logical operations
1486(define_mode_attr lconst_atomic [(QI "K") (HI "K") (SI "K") (DI "L")])
1487
43cacb12
RS		 1488;; The integer SVE instruction that implements an rtx code.
1489(define_code_attr sve_int_op [(plus "add")
9d4ac06e 1490 (minus "sub")
6c4fd4a9 1491 (mult "mul")
c38f7319
RS		 1492 (div "sdiv")
1493 (udiv "udiv")
69c5fdcf 1494 (abs "abs")
43cacb12
RS		 1495 (neg "neg")
1496 (smin "smin")
1497 (smax "smax")
1498 (umin "umin")
1499 (umax "umax")
20103c0e
RS		 1500 (ashift "lsl")
1501 (ashiftrt "asr")
1502 (lshiftrt "lsr")
43cacb12
RS		 1503 (and "and")
1504 (ior "orr")
1505 (xor "eor")
1506 (not "not")
bca5a997
RS		 1507 (clrsb "cls")
1508 (clz "clz")
43cacb12
RS		 1509 (popcount "cnt")])
1510
a08acce8 1511(define_code_attr sve_int_op_rev [(plus "add")
20103c0e
RS		 1512 (minus "subr")
1513 (mult "mul")
1514 (div "sdivr")
1515 (udiv "udivr")
1516 (smin "smin")
1517 (smax "smax")
1518 (umin "umin")
1519 (umax "umax")
1520 (ashift "lslr")
1521 (ashiftrt "asrr")
1522 (lshiftrt "lsrr")
1523 (and "and")
1524 (ior "orr")
1525 (xor "eor")])
a08acce8 1526
43cacb12
RS		 1527;; The floating-point SVE instruction that implements an rtx code.
1528(define_code_attr sve_fp_op [(plus "fadd")
740c1ed7 1529 (minus "fsub")
d45b20a5 1530 (mult "fmul")])
43cacb12 1531
f22d7973 1532;; The SVE immediate constraint to use for an rtl code.
f8c22a8b
RS		 1533(define_code_attr sve_imm_con [(mult "vsm")
1534 (smax "vsm")
1535 (smin "vsm")
1536 (umax "vsb")
1537 (umin "vsb")
1538 (eq "vsc")
f22d7973
RS		 1539 (ne "vsc")
1540 (lt "vsc")
1541 (ge "vsc")
1542 (le "vsc")
1543 (gt "vsc")
1544 (ltu "vsd")
1545 (leu "vsd")
1546 (geu "vsd")
1547 (gtu "vsd")])
1548
f8c22a8b
RS		 1549;; The prefix letter to use when printing an immediate operand.
1550(define_code_attr sve_imm_prefix [(mult "")
1551 (smax "")
1552 (smin "")
1553 (umax "D")
1554 (umin "D")])
1555
d113ece6
RS		 1556;; The predicate to use for the second input operand in a cond_<optab><mode>
1557;; pattern.
1558(define_code_attr sve_pred_int_rhs2_operand
1559 [(plus "register_operand")
1560 (minus "register_operand")
1561 (mult "register_operand")
1562 (smax "register_operand")
1563 (umax "register_operand")
1564 (smin "register_operand")
1565 (umin "register_operand")
20103c0e
RS		 1566 (ashift "aarch64_sve_lshift_operand")
1567 (ashiftrt "aarch64_sve_rshift_operand")
1568 (lshiftrt "aarch64_sve_rshift_operand")
d113ece6
RS		 1569 (and "aarch64_sve_pred_and_operand")
1570 (ior "register_operand")
1571 (xor "register_operand")])
1572
43e9d192
IB		 1573;; -------------------------------------------------------------------
1574;; Int Iterators.
1575;; -------------------------------------------------------------------
75add2d0
KT		 1576
1577;; The unspec codes for the SABAL, UABAL AdvancedSIMD instructions.
1578(define_int_iterator ABAL [UNSPEC_SABAL UNSPEC_UABAL])
1579
1580;; The unspec codes for the SABDL2, UABDL2 AdvancedSIMD instructions.
1581(define_int_iterator ABDL2 [UNSPEC_SABDL2 UNSPEC_UABDL2])
1582
1583;; The unspec codes for the SADALP, UADALP AdvancedSIMD instructions.
1584(define_int_iterator ADALP [UNSPEC_SADALP UNSPEC_UADALP])
1585
43e9d192
IB		 1586(define_int_iterator MAXMINV [UNSPEC_UMAXV UNSPEC_UMINV
1587 UNSPEC_SMAXV UNSPEC_SMINV])
1588
998eaf97
JG		 1589(define_int_iterator FMAXMINV [UNSPEC_FMAXV UNSPEC_FMINV
1590 UNSPEC_FMAXNMV UNSPEC_FMINNMV])
43e9d192 1591
43cacb12
RS		 1592(define_int_iterator LOGICALF [UNSPEC_ANDF UNSPEC_IORF UNSPEC_XORF])
1593
43e9d192
IB		 1594(define_int_iterator HADDSUB [UNSPEC_SHADD UNSPEC_UHADD
1595 UNSPEC_SRHADD UNSPEC_URHADD
1596 UNSPEC_SHSUB UNSPEC_UHSUB
1597 UNSPEC_SRHSUB UNSPEC_URHSUB])
1598
42addb5a
RS		 1599(define_int_iterator HADD [UNSPEC_SHADD UNSPEC_UHADD])
1600
1601(define_int_iterator RHADD [UNSPEC_SRHADD UNSPEC_URHADD])
1602
58cc9876
YW		 1603(define_int_iterator MULLBT [UNSPEC_SMULLB UNSPEC_UMULLB
1604 UNSPEC_SMULLT UNSPEC_UMULLT])
1605
1606(define_int_iterator SHRNB [UNSPEC_SHRNB UNSPEC_RSHRNB])
1607
1608(define_int_iterator SHRNT [UNSPEC_SHRNT UNSPEC_RSHRNT])
1609
7a08d813 1610(define_int_iterator DOTPROD [UNSPEC_SDOT UNSPEC_UDOT])
43e9d192
IB		 1611
1612(define_int_iterator ADDSUBHN [UNSPEC_ADDHN UNSPEC_RADDHN
1613 UNSPEC_SUBHN UNSPEC_RSUBHN])
1614
1615(define_int_iterator ADDSUBHN2 [UNSPEC_ADDHN2 UNSPEC_RADDHN2
1616 UNSPEC_SUBHN2 UNSPEC_RSUBHN2])
1617
1efafef3
TC		 1618(define_int_iterator FMAXMIN_UNS [UNSPEC_FMAX UNSPEC_FMIN
1619 UNSPEC_FMAXNM UNSPEC_FMINNM])
202d0c11 1620
8fc16d72
ST		 1621(define_int_iterator PAUTH_LR_SP [UNSPEC_PACIASP UNSPEC_AUTIASP
1622 UNSPEC_PACIBSP UNSPEC_AUTIBSP])
db58fd89 1623
8fc16d72
ST		 1624(define_int_iterator PAUTH_17_16 [UNSPEC_PACIA1716 UNSPEC_AUTIA1716
1625 UNSPEC_PACIB1716 UNSPEC_AUTIB1716])
db58fd89 1626
43e9d192
IB		 1627(define_int_iterator VQDMULH [UNSPEC_SQDMULH UNSPEC_SQRDMULH])
1628
58cc9876
YW		 1629(define_int_iterator MULHRS [UNSPEC_SMULHS UNSPEC_UMULHS
1630 UNSPEC_SMULHRS UNSPEC_UMULHRS])
1631
43e9d192
IB		 1632(define_int_iterator USSUQADD [UNSPEC_SUQADD UNSPEC_USQADD])
1633
1634(define_int_iterator SUQMOVN [UNSPEC_SQXTN UNSPEC_UQXTN])
1635
1636(define_int_iterator VSHL [UNSPEC_SSHL UNSPEC_USHL
1637 UNSPEC_SRSHL UNSPEC_URSHL])
1638
1639(define_int_iterator VSHLL [UNSPEC_SSHLL UNSPEC_USHLL])
1640
1641(define_int_iterator VQSHL [UNSPEC_SQSHL UNSPEC_UQSHL
1642 UNSPEC_SQRSHL UNSPEC_UQRSHL])
1643
1644(define_int_iterator VSRA [UNSPEC_SSRA UNSPEC_USRA
1645 UNSPEC_SRSRA UNSPEC_URSRA])
1646
1647(define_int_iterator VSLRI [UNSPEC_SSLI UNSPEC_USLI
1648 UNSPEC_SSRI UNSPEC_USRI])
1649
1650
1651(define_int_iterator VRSHR_N [UNSPEC_SRSHR UNSPEC_URSHR])
1652
1653(define_int_iterator VQSHL_N [UNSPEC_SQSHLU UNSPEC_SQSHL UNSPEC_UQSHL])
1654
1655(define_int_iterator VQSHRN_N [UNSPEC_SQSHRUN UNSPEC_SQRSHRUN
1656 UNSPEC_SQSHRN UNSPEC_UQSHRN
1657 UNSPEC_SQRSHRN UNSPEC_UQRSHRN])
1658
57b26d65
MW		 1659(define_int_iterator SQRDMLH_AS [UNSPEC_SQRDMLAH UNSPEC_SQRDMLSH])
1660
cc4d934f
JG		 1661(define_int_iterator PERMUTE [UNSPEC_ZIP1 UNSPEC_ZIP2
1662 UNSPEC_TRN1 UNSPEC_TRN2
1663 UNSPEC_UZP1 UNSPEC_UZP2])
43e9d192 1664
43cacb12
RS		 1665(define_int_iterator OPTAB_PERMUTE [UNSPEC_ZIP1 UNSPEC_ZIP2
1666 UNSPEC_UZP1 UNSPEC_UZP2])
1667
923fcec3
AL		 1668(define_int_iterator REVERSE [UNSPEC_REV64 UNSPEC_REV32 UNSPEC_REV16])
1669
42fc9a7f 1670(define_int_iterator FRINT [UNSPEC_FRINTZ UNSPEC_FRINTP UNSPEC_FRINTM
0659ce6f
JG		 1671 UNSPEC_FRINTN UNSPEC_FRINTI UNSPEC_FRINTX
1672 UNSPEC_FRINTA])
42fc9a7f
JG		 1673
1674(define_int_iterator FCVT [UNSPEC_FRINTZ UNSPEC_FRINTP UNSPEC_FRINTM
ce966824 1675 UNSPEC_FRINTA UNSPEC_FRINTN])
42fc9a7f 1676
3f598afe
JW		 1677(define_int_iterator FCVT_F2FIXED [UNSPEC_FCVTZS UNSPEC_FCVTZU])
1678(define_int_iterator FCVT_FIXED2F [UNSPEC_SCVTF UNSPEC_UCVTF])
1679
5d357f26
KT		 1680(define_int_iterator CRC [UNSPEC_CRC32B UNSPEC_CRC32H UNSPEC_CRC32W
1681 UNSPEC_CRC32X UNSPEC_CRC32CB UNSPEC_CRC32CH
1682 UNSPEC_CRC32CW UNSPEC_CRC32CX])
1683
5a7a4e80
TB		 1684(define_int_iterator CRYPTO_AES [UNSPEC_AESE UNSPEC_AESD])
1685(define_int_iterator CRYPTO_AESMC [UNSPEC_AESMC UNSPEC_AESIMC])
1686
30442682
TB		 1687(define_int_iterator CRYPTO_SHA1 [UNSPEC_SHA1C UNSPEC_SHA1M UNSPEC_SHA1P])
1688
b9cb0a44
TB		 1689(define_int_iterator CRYPTO_SHA256 [UNSPEC_SHA256H UNSPEC_SHA256H2])
1690
27086ea3
MC		 1691(define_int_iterator CRYPTO_SHA512 [UNSPEC_SHA512H UNSPEC_SHA512H2])
1692
1693(define_int_iterator CRYPTO_SM3TT [UNSPEC_SM3TT1A UNSPEC_SM3TT1B
1694 UNSPEC_SM3TT2A UNSPEC_SM3TT2B])
1695
1696(define_int_iterator CRYPTO_SM3PART [UNSPEC_SM3PARTW1 UNSPEC_SM3PARTW2])
1697
1698;; Iterators for fp16 operations
1699
1700(define_int_iterator VFMLA16_LOW [UNSPEC_FMLAL UNSPEC_FMLSL])
1701
1702(define_int_iterator VFMLA16_HIGH [UNSPEC_FMLAL2 UNSPEC_FMLSL2])
1703
43cacb12
RS		 1704(define_int_iterator UNPACK [UNSPEC_UNPACKSHI UNSPEC_UNPACKUHI
1705 UNSPEC_UNPACKSLO UNSPEC_UNPACKULO])
1706
1707(define_int_iterator UNPACK_UNSIGNED [UNSPEC_UNPACKULO UNSPEC_UNPACKUHI])
1708
11e9443f
RS		 1709(define_int_iterator MUL_HIGHPART [UNSPEC_SMUL_HIGHPART UNSPEC_UMUL_HIGHPART])
1710
d7a09c44
RS		 1711(define_int_iterator SVE_INT_UNARY [UNSPEC_REVB UNSPEC_REVH UNSPEC_REVW])
1712
b0760a40
RS		 1713(define_int_iterator SVE_INT_REDUCTION [UNSPEC_ANDV
1714 UNSPEC_IORV
1715 UNSPEC_SMAXV
1716 UNSPEC_SMINV
1717 UNSPEC_UMAXV
1718 UNSPEC_UMINV
1719 UNSPEC_XORV])
1720
1721(define_int_iterator SVE_FP_REDUCTION [UNSPEC_FADDV
1722 UNSPEC_FMAXV
1723 UNSPEC_FMAXNMV
1724 UNSPEC_FMINV
1725 UNSPEC_FMINNMV])
1726
d45b20a5
RS		 1727(define_int_iterator SVE_COND_FP_UNARY [UNSPEC_COND_FABS
1728 UNSPEC_COND_FNEG
1729 UNSPEC_COND_FRINTA
1730 UNSPEC_COND_FRINTI
1731 UNSPEC_COND_FRINTM
1732 UNSPEC_COND_FRINTN
1733 UNSPEC_COND_FRINTP
1734 UNSPEC_COND_FRINTX
1735 UNSPEC_COND_FRINTZ
1736 UNSPEC_COND_FSQRT])
1737
95eb5537 1738(define_int_iterator SVE_COND_FCVT [UNSPEC_COND_FCVT])
99361551
RS		 1739(define_int_iterator SVE_COND_FCVTI [UNSPEC_COND_FCVTZS UNSPEC_COND_FCVTZU])
1740(define_int_iterator SVE_COND_ICVTF [UNSPEC_COND_SCVTF UNSPEC_COND_UCVTF])
1741
cb18e86d
RS		 1742(define_int_iterator SVE_COND_FP_BINARY [UNSPEC_COND_FADD
1743 UNSPEC_COND_FDIV
1744 UNSPEC_COND_FMAXNM
1745 UNSPEC_COND_FMINNM
1746 UNSPEC_COND_FMUL
1747 UNSPEC_COND_FSUB])
0d2b3bca 1748
a19ba9e1
RS		 1749(define_int_iterator SVE_COND_FP_BINARY_I1 [UNSPEC_COND_FMAXNM
1750 UNSPEC_COND_FMINNM
1751 UNSPEC_COND_FMUL])
1752
0254ed79
RS		 1753(define_int_iterator SVE_COND_FP_BINARY_REG [UNSPEC_COND_FDIV])
1754
214c42fa
RS		 1755;; Floating-point max/min operations that correspond to optabs,
1756;; as opposed to those that are internal to the port.
1757(define_int_iterator SVE_COND_FP_MAXMIN_PUBLIC [UNSPEC_COND_FMAXNM
1758 UNSPEC_COND_FMINNM])
1759
b41d1f6e
RS		 1760(define_int_iterator SVE_COND_FP_TERNARY [UNSPEC_COND_FMLA
1761 UNSPEC_COND_FMLS
1762 UNSPEC_COND_FNMLA
1763 UNSPEC_COND_FNMLS])
1764
4a942af6
RS		 1765;; SVE FP comparisons that accept #0.0.
1766(define_int_iterator SVE_COND_FP_CMP_I0 [UNSPEC_COND_FCMEQ
1767 UNSPEC_COND_FCMGE
1768 UNSPEC_COND_FCMGT
1769 UNSPEC_COND_FCMLE
1770 UNSPEC_COND_FCMLT
1771 UNSPEC_COND_FCMNE])
43cacb12 1772
42b4e87d
RS		 1773(define_int_iterator SVE_COND_FP_ABS_CMP [UNSPEC_COND_FCMGE
1774 UNSPEC_COND_FCMGT
1775 UNSPEC_COND_FCMLE
1776 UNSPEC_COND_FCMLT])
1777
9d63f43b
TC		 1778(define_int_iterator FCADD [UNSPEC_FCADD90
1779 UNSPEC_FCADD270])
1780
1781(define_int_iterator FCMLA [UNSPEC_FCMLA
1782 UNSPEC_FCMLA90
1783 UNSPEC_FCMLA180
1784 UNSPEC_FCMLA270])
1785
10bd1d96
KT		 1786(define_int_iterator FRINTNZX [UNSPEC_FRINT32Z UNSPEC_FRINT32X
1787 UNSPEC_FRINT64Z UNSPEC_FRINT64X])
1788
d81cb613
MW		 1789;; Iterators for atomic operations.
1790
1791(define_int_iterator ATOMIC_LDOP
1792 [UNSPECV_ATOMIC_LDOP_OR UNSPECV_ATOMIC_LDOP_BIC
1793 UNSPECV_ATOMIC_LDOP_XOR UNSPECV_ATOMIC_LDOP_PLUS])
1794
1795(define_int_attr atomic_ldop
1796 [(UNSPECV_ATOMIC_LDOP_OR "set") (UNSPECV_ATOMIC_LDOP_BIC "clr")
1797 (UNSPECV_ATOMIC_LDOP_XOR "eor") (UNSPECV_ATOMIC_LDOP_PLUS "add")])
1798
7803ec5e
RH		 1799(define_int_attr atomic_ldoptab
1800 [(UNSPECV_ATOMIC_LDOP_OR "ior") (UNSPECV_ATOMIC_LDOP_BIC "bic")
1801 (UNSPECV_ATOMIC_LDOP_XOR "xor") (UNSPECV_ATOMIC_LDOP_PLUS "add")])
1802
43e9d192
IB		 1803;; -------------------------------------------------------------------
1804;; Int Iterators Attributes.
1805;; -------------------------------------------------------------------
43cacb12
RS		 1806
1807;; The optab associated with an operation. Note that for ANDF, IORF
1808;; and XORF, the optab pattern is not actually defined; we just use this
1809;; name for consistency with the integer patterns.
1810(define_int_attr optab [(UNSPEC_ANDF "and")
1811 (UNSPEC_IORF "ior")
898f07b0
RS		 1812 (UNSPEC_XORF "xor")
1813 (UNSPEC_ANDV "and")
1814 (UNSPEC_IORV "ior")
0972596e 1815 (UNSPEC_XORV "xor")
d7a09c44
RS		 1816 (UNSPEC_REVB "revb")
1817 (UNSPEC_REVH "revh")
1818 (UNSPEC_REVW "revw")
b0760a40
RS		 1819 (UNSPEC_UMAXV "umax")
1820 (UNSPEC_UMINV "umin")
1821 (UNSPEC_SMAXV "smax")
1822 (UNSPEC_SMINV "smin")
1823 (UNSPEC_FADDV "plus")
1824 (UNSPEC_FMAXNMV "smax")
1825 (UNSPEC_FMAXV "smax_nan")
1826 (UNSPEC_FMINNMV "smin")
1827 (UNSPEC_FMINV "smin_nan")
d45b20a5 1828 (UNSPEC_COND_FABS "abs")
cb18e86d 1829 (UNSPEC_COND_FADD "add")
99361551
RS		 1830 (UNSPEC_COND_FCVT "fcvt")
1831 (UNSPEC_COND_FCVTZS "fix_trunc")
1832 (UNSPEC_COND_FCVTZU "fixuns_trunc")
cb18e86d
RS		 1833 (UNSPEC_COND_FDIV "div")
1834 (UNSPEC_COND_FMAXNM "smax")
1835 (UNSPEC_COND_FMINNM "smin")
b41d1f6e
RS		 1836 (UNSPEC_COND_FMLA "fma")
1837 (UNSPEC_COND_FMLS "fnma")
cb18e86d 1838 (UNSPEC_COND_FMUL "mul")
d45b20a5 1839 (UNSPEC_COND_FNEG "neg")
b41d1f6e 1840 (UNSPEC_COND_FNMLA "fnms")
cb18e86d 1841 (UNSPEC_COND_FNMLS "fms")
d45b20a5
RS		 1842 (UNSPEC_COND_FRINTA "round")
1843 (UNSPEC_COND_FRINTI "nearbyint")
1844 (UNSPEC_COND_FRINTM "floor")
1845 (UNSPEC_COND_FRINTN "frintn")
1846 (UNSPEC_COND_FRINTP "ceil")
1847 (UNSPEC_COND_FRINTX "rint")
1848 (UNSPEC_COND_FRINTZ "btrunc")
1849 (UNSPEC_COND_FSQRT "sqrt")
99361551
RS		 1850 (UNSPEC_COND_FSUB "sub")
1851 (UNSPEC_COND_SCVTF "float")
1852 (UNSPEC_COND_UCVTF "floatuns")])
43cacb12 1853
998eaf97
JG		 1854(define_int_attr maxmin_uns [(UNSPEC_UMAXV "umax")
1855 (UNSPEC_UMINV "umin")
1856 (UNSPEC_SMAXV "smax")
1857 (UNSPEC_SMINV "smin")
1858 (UNSPEC_FMAX "smax_nan")
1859 (UNSPEC_FMAXNMV "smax")
1860 (UNSPEC_FMAXV "smax_nan")
1861 (UNSPEC_FMIN "smin_nan")
1862 (UNSPEC_FMINNMV "smin")
1efafef3
TC		 1863 (UNSPEC_FMINV "smin_nan")
1864 (UNSPEC_FMAXNM "fmax")
214c42fa
RS		 1865 (UNSPEC_FMINNM "fmin")
1866 (UNSPEC_COND_FMAXNM "fmax")
1867 (UNSPEC_COND_FMINNM "fmin")])
998eaf97
JG		 1868
1869(define_int_attr maxmin_uns_op [(UNSPEC_UMAXV "umax")
1870 (UNSPEC_UMINV "umin")
1871 (UNSPEC_SMAXV "smax")
1872 (UNSPEC_SMINV "smin")
1873 (UNSPEC_FMAX "fmax")
1874 (UNSPEC_FMAXNMV "fmaxnm")
1875 (UNSPEC_FMAXV "fmax")
1876 (UNSPEC_FMIN "fmin")
1877 (UNSPEC_FMINNMV "fminnm")
1efafef3
TC		 1878 (UNSPEC_FMINV "fmin")
1879 (UNSPEC_FMAXNM "fmaxnm")
1880 (UNSPEC_FMINNM "fminnm")])
202d0c11 1881
43cacb12
RS		 1882;; The SVE logical instruction that implements an unspec.
1883(define_int_attr logicalf_op [(UNSPEC_ANDF "and")
1884 (UNSPEC_IORF "orr")
1885 (UNSPEC_XORF "eor")])
1886
1887;; "s" for signed operations and "u" for unsigned ones.
1888(define_int_attr su [(UNSPEC_UNPACKSHI "s")
1889 (UNSPEC_UNPACKUHI "u")
1890 (UNSPEC_UNPACKSLO "s")
11e9443f
RS		 1891 (UNSPEC_UNPACKULO "u")
1892 (UNSPEC_SMUL_HIGHPART "s")
99361551
RS		 1893 (UNSPEC_UMUL_HIGHPART "u")
1894 (UNSPEC_COND_FCVTZS "s")
1895 (UNSPEC_COND_FCVTZU "u")
1896 (UNSPEC_COND_SCVTF "s")
58cc9876
YW		 1897 (UNSPEC_COND_UCVTF "u")
1898 (UNSPEC_SMULLB "s") (UNSPEC_UMULLB "u")
1899 (UNSPEC_SMULLT "s") (UNSPEC_UMULLT "u")
1900 (UNSPEC_SMULHS "s") (UNSPEC_UMULHS "u")
1901 (UNSPEC_SMULHRS "s") (UNSPEC_UMULHRS "u")])
43cacb12 1902
43e9d192
IB		 1903(define_int_attr sur [(UNSPEC_SHADD "s") (UNSPEC_UHADD "u")
1904 (UNSPEC_SRHADD "sr") (UNSPEC_URHADD "ur")
1905 (UNSPEC_SHSUB "s") (UNSPEC_UHSUB "u")
1906 (UNSPEC_SRHSUB "sr") (UNSPEC_URHSUB "ur")
1907 (UNSPEC_ADDHN "") (UNSPEC_RADDHN "r")
75add2d0
KT		 1908 (UNSPEC_SABAL "s") (UNSPEC_UABAL "u")
1909 (UNSPEC_SABDL2 "s") (UNSPEC_UABDL2 "u")
1910 (UNSPEC_SADALP "s") (UNSPEC_UADALP "u")
43e9d192
IB		 1911 (UNSPEC_SUBHN "") (UNSPEC_RSUBHN "r")
1912 (UNSPEC_ADDHN2 "") (UNSPEC_RADDHN2 "r")
1913 (UNSPEC_SUBHN2 "") (UNSPEC_RSUBHN2 "r")
1914 (UNSPEC_SQXTN "s") (UNSPEC_UQXTN "u")
1915 (UNSPEC_USQADD "us") (UNSPEC_SUQADD "su")
1916 (UNSPEC_SSLI "s") (UNSPEC_USLI "u")
1917 (UNSPEC_SSRI "s") (UNSPEC_USRI "u")
1918 (UNSPEC_USRA "u") (UNSPEC_SSRA "s")
1919 (UNSPEC_URSRA "ur") (UNSPEC_SRSRA "sr")
1920 (UNSPEC_URSHR "ur") (UNSPEC_SRSHR "sr")
1921 (UNSPEC_SQSHLU "s") (UNSPEC_SQSHL "s")
1922 (UNSPEC_UQSHL "u")
1923 (UNSPEC_SQSHRUN "s") (UNSPEC_SQRSHRUN "s")
1924 (UNSPEC_SQSHRN "s") (UNSPEC_UQSHRN "u")
1925 (UNSPEC_SQRSHRN "s") (UNSPEC_UQRSHRN "u")
1926 (UNSPEC_USHL "u") (UNSPEC_SSHL "s")
1927 (UNSPEC_USHLL "u") (UNSPEC_SSHLL "s")
1928 (UNSPEC_URSHL "ur") (UNSPEC_SRSHL "sr")
1929 (UNSPEC_UQRSHL "u") (UNSPEC_SQRSHL "s")
7a08d813 1930 (UNSPEC_SDOT "s") (UNSPEC_UDOT "u")
43e9d192
IB		 1931])
1932
1933(define_int_attr r [(UNSPEC_SQDMULH "") (UNSPEC_SQRDMULH "r")
1934 (UNSPEC_SQSHRUN "") (UNSPEC_SQRSHRUN "r")
1935 (UNSPEC_SQSHRN "") (UNSPEC_UQSHRN "")
1936 (UNSPEC_SQRSHRN "r") (UNSPEC_UQRSHRN "r")
1937 (UNSPEC_SQSHL "") (UNSPEC_UQSHL "")
1938 (UNSPEC_SQRSHL "r")(UNSPEC_UQRSHL "r")
58cc9876
YW		 1939 (UNSPEC_SHRNB "") (UNSPEC_SHRNT "")
1940 (UNSPEC_RSHRNB "r") (UNSPEC_RSHRNT "r")
1941 (UNSPEC_SMULHS "") (UNSPEC_UMULHS "")
1942 (UNSPEC_SMULHRS "r") (UNSPEC_UMULHRS "r")
43e9d192
IB		 1943])
1944
1945(define_int_attr lr [(UNSPEC_SSLI "l") (UNSPEC_USLI "l")
1946 (UNSPEC_SSRI "r") (UNSPEC_USRI "r")])
1947
1948(define_int_attr u [(UNSPEC_SQSHLU "u") (UNSPEC_SQSHL "") (UNSPEC_UQSHL "")
1949 (UNSPEC_SQSHRUN "u") (UNSPEC_SQRSHRUN "u")
42addb5a
RS		 1950 (UNSPEC_SQSHRN "") (UNSPEC_UQSHRN "")
1951 (UNSPEC_SQRSHRN "") (UNSPEC_UQRSHRN "")
1952 (UNSPEC_SHADD "") (UNSPEC_UHADD "u")
1953 (UNSPEC_SRHADD "") (UNSPEC_URHADD "u")])
43e9d192 1954
58cc9876
YW		 1955(define_int_attr bt [(UNSPEC_SMULLB "b") (UNSPEC_UMULLB "b")
1956 (UNSPEC_SMULLT "t") (UNSPEC_UMULLT "t")])
1957
43e9d192
IB		 1958(define_int_attr addsub [(UNSPEC_SHADD "add")
1959 (UNSPEC_UHADD "add")
1960 (UNSPEC_SRHADD "add")
1961 (UNSPEC_URHADD "add")
1962 (UNSPEC_SHSUB "sub")
1963 (UNSPEC_UHSUB "sub")
1964 (UNSPEC_SRHSUB "sub")
1965 (UNSPEC_URHSUB "sub")
1966 (UNSPEC_ADDHN "add")
1967 (UNSPEC_SUBHN "sub")
1968 (UNSPEC_RADDHN "add")
1969 (UNSPEC_RSUBHN "sub")
1970 (UNSPEC_ADDHN2 "add")
1971 (UNSPEC_SUBHN2 "sub")
1972 (UNSPEC_RADDHN2 "add")
1973 (UNSPEC_RSUBHN2 "sub")])
1974
cb23a30c
JG		 1975(define_int_attr offsetlr [(UNSPEC_SSLI "") (UNSPEC_USLI "")
1976 (UNSPEC_SSRI "offset_")
1977 (UNSPEC_USRI "offset_")])
43e9d192 1978
42fc9a7f
JG		 1979;; Standard pattern names for floating-point rounding instructions.
1980(define_int_attr frint_pattern [(UNSPEC_FRINTZ "btrunc")
1981 (UNSPEC_FRINTP "ceil")
1982 (UNSPEC_FRINTM "floor")
1983 (UNSPEC_FRINTI "nearbyint")
1984 (UNSPEC_FRINTX "rint")
0659ce6f
JG		 1985 (UNSPEC_FRINTA "round")
1986 (UNSPEC_FRINTN "frintn")])
42fc9a7f
JG		 1987
1988;; frint suffix for floating-point rounding instructions.
1989(define_int_attr frint_suffix [(UNSPEC_FRINTZ "z") (UNSPEC_FRINTP "p")
1990 (UNSPEC_FRINTM "m") (UNSPEC_FRINTI "i")
0659ce6f
JG		 1991 (UNSPEC_FRINTX "x") (UNSPEC_FRINTA "a")
1992 (UNSPEC_FRINTN "n")])
42fc9a7f
JG		 1993
1994(define_int_attr fcvt_pattern [(UNSPEC_FRINTZ "btrunc") (UNSPEC_FRINTA "round")
ce966824
JG		 1995 (UNSPEC_FRINTP "ceil") (UNSPEC_FRINTM "floor")
1996 (UNSPEC_FRINTN "frintn")])
42fc9a7f 1997
3f598afe
JW		 1998(define_int_attr fcvt_fixed_insn [(UNSPEC_SCVTF "scvtf")
1999 (UNSPEC_UCVTF "ucvtf")
2000 (UNSPEC_FCVTZS "fcvtzs")
2001 (UNSPEC_FCVTZU "fcvtzu")])
2002
db58fd89 2003;; Pointer authentication mnemonic prefix.
8fc16d72
ST		 2004(define_int_attr pauth_mnem_prefix [(UNSPEC_PACIASP "pacia")
2005 (UNSPEC_PACIBSP "pacib")
2006 (UNSPEC_PACIA1716 "pacia")
2007 (UNSPEC_PACIB1716 "pacib")
2008 (UNSPEC_AUTIASP "autia")
2009 (UNSPEC_AUTIBSP "autib")
2010 (UNSPEC_AUTIA1716 "autia")
2011 (UNSPEC_AUTIB1716 "autib")])
2012
2013(define_int_attr pauth_key [(UNSPEC_PACIASP "AARCH64_KEY_A")
2014 (UNSPEC_PACIBSP "AARCH64_KEY_B")
2015 (UNSPEC_PACIA1716 "AARCH64_KEY_A")
2016 (UNSPEC_PACIB1716 "AARCH64_KEY_B")
2017 (UNSPEC_AUTIASP "AARCH64_KEY_A")
2018 (UNSPEC_AUTIBSP "AARCH64_KEY_B")
2019 (UNSPEC_AUTIA1716 "AARCH64_KEY_A")
2020 (UNSPEC_AUTIB1716 "AARCH64_KEY_B")])
2021
2022;; Pointer authentication HINT number for NOP space instructions using A and
2023;; B key.
2024(define_int_attr pauth_hint_num [(UNSPEC_PACIASP "25")
2025 (UNSPEC_PACIBSP "27")
2026 (UNSPEC_AUTIASP "29")
2027 (UNSPEC_AUTIBSP "31")
2028 (UNSPEC_PACIA1716 "8")
2029 (UNSPEC_PACIB1716 "10")
2030 (UNSPEC_AUTIA1716 "12")
2031 (UNSPEC_AUTIB1716 "14")])
db58fd89 2032
3e2751ce
RS		 2033(define_int_attr perm_insn [(UNSPEC_ZIP1 "zip1") (UNSPEC_ZIP2 "zip2")
2034 (UNSPEC_TRN1 "trn1") (UNSPEC_TRN2 "trn2")
2035 (UNSPEC_UZP1 "uzp1") (UNSPEC_UZP2 "uzp2")])
cc4d934f 2036
923fcec3
AL		 2037; op code for REV instructions (size within which elements are reversed).
2038(define_int_attr rev_op [(UNSPEC_REV64 "64") (UNSPEC_REV32 "32")
2039 (UNSPEC_REV16 "16")])
2040
3e2751ce 2041(define_int_attr perm_hilo [(UNSPEC_UNPACKSHI "hi") (UNSPEC_UNPACKUHI "hi")
43cacb12 2042 (UNSPEC_UNPACKSLO "lo") (UNSPEC_UNPACKULO "lo")])
0050faf8 2043
9bfb28ed
RS		 2044;; Return true if the associated optab refers to the high-numbered lanes,
2045;; false if it refers to the low-numbered lanes. The convention is for
2046;; "hi" to refer to the low-numbered lanes (the first ones in memory)
2047;; for big-endian.
2048(define_int_attr hi_lanes_optab [(UNSPEC_UNPACKSHI "!BYTES_BIG_ENDIAN")
2049 (UNSPEC_UNPACKUHI "!BYTES_BIG_ENDIAN")
2050 (UNSPEC_UNPACKSLO "BYTES_BIG_ENDIAN")
2051 (UNSPEC_UNPACKULO "BYTES_BIG_ENDIAN")])
2052
5d357f26
KT		 2053(define_int_attr crc_variant [(UNSPEC_CRC32B "crc32b") (UNSPEC_CRC32H "crc32h")
2054 (UNSPEC_CRC32W "crc32w") (UNSPEC_CRC32X "crc32x")
2055 (UNSPEC_CRC32CB "crc32cb") (UNSPEC_CRC32CH "crc32ch")
2056 (UNSPEC_CRC32CW "crc32cw") (UNSPEC_CRC32CX "crc32cx")])
2057
2058(define_int_attr crc_mode [(UNSPEC_CRC32B "QI") (UNSPEC_CRC32H "HI")
2059 (UNSPEC_CRC32W "SI") (UNSPEC_CRC32X "DI")
2060 (UNSPEC_CRC32CB "QI") (UNSPEC_CRC32CH "HI")
2061 (UNSPEC_CRC32CW "SI") (UNSPEC_CRC32CX "DI")])
2062
5a7a4e80
TB		 2063(define_int_attr aes_op [(UNSPEC_AESE "e") (UNSPEC_AESD "d")])
2064(define_int_attr aesmc_op [(UNSPEC_AESMC "mc") (UNSPEC_AESIMC "imc")])
30442682
TB		 2065
2066(define_int_attr sha1_op [(UNSPEC_SHA1C "c") (UNSPEC_SHA1P "p")
2067 (UNSPEC_SHA1M "m")])
b9cb0a44
TB		 2068
2069(define_int_attr sha256_op [(UNSPEC_SHA256H "") (UNSPEC_SHA256H2 "2")])
57b26d65
MW		 2070
2071(define_int_attr rdma_as [(UNSPEC_SQRDMLAH "a") (UNSPEC_SQRDMLSH "s")])
27086ea3
MC		 2072
2073(define_int_attr sha512_op [(UNSPEC_SHA512H "") (UNSPEC_SHA512H2 "2")])
2074
2075(define_int_attr sm3tt_op [(UNSPEC_SM3TT1A "1a") (UNSPEC_SM3TT1B "1b")
2076 (UNSPEC_SM3TT2A "2a") (UNSPEC_SM3TT2B "2b")])
2077
2078(define_int_attr sm3part_op [(UNSPEC_SM3PARTW1 "1") (UNSPEC_SM3PARTW2 "2")])
2079
2080(define_int_attr f16mac1 [(UNSPEC_FMLAL "a") (UNSPEC_FMLSL "s")
2081 (UNSPEC_FMLAL2 "a") (UNSPEC_FMLSL2 "s")])
43cacb12 2082
10bd1d96
KT		 2083(define_int_attr frintnzs_op [(UNSPEC_FRINT32Z "frint32z") (UNSPEC_FRINT32X "frint32x")
2084 (UNSPEC_FRINT64Z "frint64z") (UNSPEC_FRINT64X "frint64x")])
2085
43cacb12 2086;; The condition associated with an UNSPEC_COND_<xx>.
cb18e86d
RS		 2087(define_int_attr cmp_op [(UNSPEC_COND_FCMEQ "eq")
2088 (UNSPEC_COND_FCMGE "ge")
2089 (UNSPEC_COND_FCMGT "gt")
2090 (UNSPEC_COND_FCMLE "le")
2091 (UNSPEC_COND_FCMLT "lt")
4a942af6
RS		 2092 (UNSPEC_COND_FCMNE "ne")
2093 (UNSPEC_COND_FCMUO "uo")])
cb18e86d 2094
b0760a40
RS		 2095(define_int_attr sve_int_op [(UNSPEC_ANDV "andv")
2096 (UNSPEC_IORV "orv")
2097 (UNSPEC_XORV "eorv")
2098 (UNSPEC_UMAXV "umaxv")
2099 (UNSPEC_UMINV "uminv")
2100 (UNSPEC_SMAXV "smaxv")
d7a09c44
RS		 2101 (UNSPEC_SMINV "sminv")
2102 (UNSPEC_REVB "revb")
2103 (UNSPEC_REVH "revh")
2104 (UNSPEC_REVW "revw")])
b0760a40
RS		 2105
2106(define_int_attr sve_fp_op [(UNSPEC_FADDV "faddv")
2107 (UNSPEC_FMAXNMV "fmaxnmv")
2108 (UNSPEC_FMAXV "fmaxv")
2109 (UNSPEC_FMINNMV "fminnmv")
2110 (UNSPEC_FMINV "fminv")
2111 (UNSPEC_COND_FABS "fabs")
d45b20a5 2112 (UNSPEC_COND_FADD "fadd")
cb18e86d
RS		 2113 (UNSPEC_COND_FDIV "fdiv")
2114 (UNSPEC_COND_FMAXNM "fmaxnm")
2115 (UNSPEC_COND_FMINNM "fminnm")
2116 (UNSPEC_COND_FMUL "fmul")
d45b20a5
RS		 2117 (UNSPEC_COND_FNEG "fneg")
2118 (UNSPEC_COND_FRINTA "frinta")
2119 (UNSPEC_COND_FRINTI "frinti")
2120 (UNSPEC_COND_FRINTM "frintm")
2121 (UNSPEC_COND_FRINTN "frintn")
2122 (UNSPEC_COND_FRINTP "frintp")
2123 (UNSPEC_COND_FRINTX "frintx")
2124 (UNSPEC_COND_FRINTZ "frintz")
2125 (UNSPEC_COND_FSQRT "fsqrt")
cb18e86d
RS		 2126 (UNSPEC_COND_FSUB "fsub")])
2127
2128(define_int_attr sve_fp_op_rev [(UNSPEC_COND_FADD "fadd")
2129 (UNSPEC_COND_FDIV "fdivr")
2130 (UNSPEC_COND_FMAXNM "fmaxnm")
2131 (UNSPEC_COND_FMINNM "fminnm")
2132 (UNSPEC_COND_FMUL "fmul")
2133 (UNSPEC_COND_FSUB "fsubr")])
a08acce8 2134
9d63f43b
TC		 2135(define_int_attr rot [(UNSPEC_FCADD90 "90")
2136 (UNSPEC_FCADD270 "270")
2137 (UNSPEC_FCMLA "0")
2138 (UNSPEC_FCMLA90 "90")
2139 (UNSPEC_FCMLA180 "180")
2140 (UNSPEC_FCMLA270 "270")])
2141
b41d1f6e
RS		 2142(define_int_attr sve_fmla_op [(UNSPEC_COND_FMLA "fmla")
2143 (UNSPEC_COND_FMLS "fmls")
2144 (UNSPEC_COND_FNMLA "fnmla")
2145 (UNSPEC_COND_FNMLS "fnmls")])
2146
2147(define_int_attr sve_fmad_op [(UNSPEC_COND_FMLA "fmad")
2148 (UNSPEC_COND_FMLS "fmsb")
2149 (UNSPEC_COND_FNMLA "fnmad")
2150 (UNSPEC_COND_FNMLS "fnmsb")])
0254ed79
RS		 2151
2152;; The predicate to use for the first input operand in a floating-point
2153;; <optab><mode>3 pattern.
2154(define_int_attr sve_pred_fp_rhs1_operand
2155 [(UNSPEC_COND_FADD "register_operand")
2156 (UNSPEC_COND_FDIV "register_operand")
2157 (UNSPEC_COND_FMAXNM "register_operand")
2158 (UNSPEC_COND_FMINNM "register_operand")
2159 (UNSPEC_COND_FMUL "register_operand")
2160 (UNSPEC_COND_FSUB "aarch64_sve_float_arith_operand")])
2161
2162;; The predicate to use for the second input operand in a floating-point
2163;; <optab><mode>3 pattern.
2164(define_int_attr sve_pred_fp_rhs2_operand
2165 [(UNSPEC_COND_FADD "aarch64_sve_float_arith_with_sub_operand")
2166 (UNSPEC_COND_FDIV "register_operand")
75079ddf
RS		 2167 (UNSPEC_COND_FMAXNM "aarch64_sve_float_maxmin_operand")
2168 (UNSPEC_COND_FMINNM "aarch64_sve_float_maxmin_operand")
0254ed79
RS		 2169 (UNSPEC_COND_FMUL "aarch64_sve_float_mul_operand")
2170 (UNSPEC_COND_FSUB "register_operand")])
a19ba9e1
RS		 2171
2172;; Likewise for immediates only.
2173(define_int_attr sve_pred_fp_rhs2_immediate
2174 [(UNSPEC_COND_FMAXNM "aarch64_sve_float_maxmin_immediate")
2175 (UNSPEC_COND_FMINNM "aarch64_sve_float_maxmin_immediate")
2176 (UNSPEC_COND_FMUL "aarch64_sve_float_mul_immediate")])
d7a09c44
RS		 2177
2178;; The minimum number of element bits that an instruction can handle.
2179(define_int_attr min_elem_bits [(UNSPEC_REVB "16")
2180 (UNSPEC_REVH "32")
2181 (UNSPEC_REVW "64")])
Mirror of https://gcc.gnu.org/git/gcc.git