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[AArch64] Add gather loads for partial SVE modes
[thirdparty/gcc.git] / gcc / config / aarch64 / iterators.md
CommitLineData
43e9d192 1;; Machine description for AArch64 architecture.
a5544970 2;; Copyright (C) 2009-2019 Free Software Foundation, Inc.
43e9d192
IB		 3;; Contributed by ARM Ltd.
4;;
5;; This file is part of GCC.
6;;
7;; GCC is free software; you can redistribute it and/or modify it
8;; under the terms of the GNU General Public License as published by
9;; the Free Software Foundation; either version 3, or (at your option)
10;; any later version.
11;;
12;; GCC is distributed in the hope that it will be useful, but
13;; WITHOUT ANY WARRANTY; without even the implied warranty of
14;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15;; General Public License for more details.
16;;
17;; You should have received a copy of the GNU General Public License
18;; along with GCC; see the file COPYING3. If not see
19;; <http://www.gnu.org/licenses/>.
20
21;; -------------------------------------------------------------------
22;; Mode Iterators
23;; -------------------------------------------------------------------
24
25
26;; Iterator for General Purpose Integer registers (32- and 64-bit modes)
27(define_mode_iterator GPI [SI DI])
28
d7f33f07
JW		 29;; Iterator for HI, SI, DI, some instructions can only work on these modes.
30(define_mode_iterator GPI_I16 [(HI "AARCH64_ISA_F16") SI DI])
31
4a2095eb
RH		 32;; "Iterator" for just TI -- features like @pattern only work with iterators.
33(define_mode_iterator JUST_TI [TI])
34
43e9d192
IB		 35;; Iterator for QI and HI modes
36(define_mode_iterator SHORT [QI HI])
37
624d0f07
RS		 38;; Iterators for single modes, for "@" patterns.
39(define_mode_iterator SI_ONLY [SI])
40(define_mode_iterator DI_ONLY [DI])
41
43e9d192
IB		 42;; Iterator for all integer modes (up to 64-bit)
43(define_mode_iterator ALLI [QI HI SI DI])
44
c0111dc4
RE		 45;; Iterator for all integer modes (up to 128-bit)
46(define_mode_iterator ALLI_TI [QI HI SI DI TI])
47
43e9d192
IB		 48;; Iterator for all integer modes that can be extended (up to 64-bit)
49(define_mode_iterator ALLX [QI HI SI])
50
51;; Iterator for General Purpose Floating-point registers (32- and 64-bit modes)
52(define_mode_iterator GPF [SF DF])
53
d7f33f07
JW		 54;; Iterator for all scalar floating point modes (HF, SF, DF)
55(define_mode_iterator GPF_F16 [(HF "AARCH64_ISA_F16") SF DF])
56
90e6443f
TC		 57;; Iterator for all scalar floating point modes (HF, SF, DF)
58(define_mode_iterator GPF_HF [HF SF DF])
59
09fcd8e1
RR		 60;; Iterator for all scalar floating point modes (HF, SF, DF and TF)
61(define_mode_iterator GPF_TF_F16 [HF SF DF TF])
c2ec330c 62
922f9c25
AL		 63;; Double vector modes.
64(define_mode_iterator VDF [V2SF V4HF])
65
b4f50fd4
RR		 66;; Iterator for all scalar floating point modes (SF, DF and TF)
67(define_mode_iterator GPF_TF [SF DF TF])
68
43cacb12 69;; Integer Advanced SIMD modes.
43e9d192
IB		 70(define_mode_iterator VDQ_I [V8QI V16QI V4HI V8HI V2SI V4SI V2DI])
71
43cacb12 72;; Advanced SIMD and scalar, 64 & 128-bit container, all integer modes.
43e9d192
IB		 73(define_mode_iterator VSDQ_I [V8QI V16QI V4HI V8HI V2SI V4SI V2DI QI HI SI DI])
74
43cacb12
RS		 75;; Advanced SIMD and scalar, 64 & 128-bit container: all Advanced SIMD
76;; integer modes; 64-bit scalar integer mode.
43e9d192
IB		 77(define_mode_iterator VSDQ_I_DI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI DI])
78
79;; Double vector modes.
71a11456 80(define_mode_iterator VD [V8QI V4HI V4HF V2SI V2SF])
43e9d192 81
dfe1da23
JW		 82;; All modes stored in registers d0-d31.
83(define_mode_iterator DREG [V8QI V4HI V4HF V2SI V2SF DF])
84
85;; Copy of the above.
86(define_mode_iterator DREG2 [V8QI V4HI V4HF V2SI V2SF DF])
87
43cacb12 88;; Advanced SIMD, 64-bit container, all integer modes.
43e9d192
IB		 89(define_mode_iterator VD_BHSI [V8QI V4HI V2SI])
90
91;; 128 and 64-bit container; 8, 16, 32-bit vector integer modes
92(define_mode_iterator VDQ_BHSI [V8QI V16QI V4HI V8HI V2SI V4SI])
93
94;; Quad vector modes.
71a11456 95(define_mode_iterator VQ [V16QI V8HI V4SI V2DI V8HF V4SF V2DF])
43e9d192 96
9f5361c8
KT		 97;; Copy of the above.
98(define_mode_iterator VQ2 [V16QI V8HI V4SI V2DI V8HF V4SF V2DF])
99
d21052eb
TC		 100;; Quad integer vector modes.
101(define_mode_iterator VQ_I [V16QI V8HI V4SI V2DI])
102
51437269 103;; VQ without 2 element modes.
71a11456 104(define_mode_iterator VQ_NO2E [V16QI V8HI V4SI V8HF V4SF])
51437269
GW		 105
106;; Quad vector with only 2 element modes.
107(define_mode_iterator VQ_2E [V2DI V2DF])
108
28514dda
YZ		 109;; This mode iterator allows :P to be used for patterns that operate on
110;; addresses in different modes. In LP64, only DI will match, while in
111;; ILP32, either can match.
112(define_mode_iterator P [(SI "ptr_mode == SImode || Pmode == SImode")
113 (DI "ptr_mode == DImode || Pmode == DImode")])
114
43e9d192
IB		 115;; This mode iterator allows :PTR to be used for patterns that operate on
116;; pointer-sized quantities. Exactly one of the two alternatives will match.
28514dda 117(define_mode_iterator PTR [(SI "ptr_mode == SImode") (DI "ptr_mode == DImode")])
43e9d192 118
43cacb12 119;; Advanced SIMD Float modes suitable for moving, loading and storing.
862abc04
AL		 120(define_mode_iterator VDQF_F16 [V4HF V8HF V2SF V4SF V2DF])
121
43cacb12 122;; Advanced SIMD Float modes.
43e9d192 123(define_mode_iterator VDQF [V2SF V4SF V2DF])
daef0a8c
JW		 124(define_mode_iterator VHSDF [(V4HF "TARGET_SIMD_F16INST")
125 (V8HF "TARGET_SIMD_F16INST")
126 V2SF V4SF V2DF])
43e9d192 127
43cacb12 128;; Advanced SIMD Float modes, and DF.
daef0a8c
JW		 129(define_mode_iterator VHSDF_DF [(V4HF "TARGET_SIMD_F16INST")
130 (V8HF "TARGET_SIMD_F16INST")
131 V2SF V4SF V2DF DF])
d7f33f07
JW		 132(define_mode_iterator VHSDF_HSDF [(V4HF "TARGET_SIMD_F16INST")
133 (V8HF "TARGET_SIMD_F16INST")
134 V2SF V4SF V2DF
135 (HF "TARGET_SIMD_F16INST")
136 SF DF])
f421c516 137
10bd1d96
KT		 138;; Scalar and vetor modes for SF, DF.
139(define_mode_iterator VSFDF [V2SF V4SF V2DF DF SF])
140
43cacb12 141;; Advanced SIMD single Float modes.
828e70c1
JG		 142(define_mode_iterator VDQSF [V2SF V4SF])
143
03873eb9
AL		 144;; Quad vector Float modes with half/single elements.
145(define_mode_iterator VQ_HSF [V8HF V4SF])
146
fc21784d
JG		 147;; Modes suitable to use as the return type of a vcond expression.
148(define_mode_iterator VDQF_COND [V2SF V2SI V4SF V4SI V2DF V2DI])
149
43cacb12 150;; All scalar and Advanced SIMD Float modes.
889b9412
JG		 151(define_mode_iterator VALLF [V2SF V4SF V2DF SF DF])
152
43cacb12 153;; Advanced SIMD Float modes with 2 elements.
43e9d192
IB		 154(define_mode_iterator V2F [V2SF V2DF])
155
43cacb12 156;; All Advanced SIMD modes on which we support any arithmetic operations.
43e9d192
IB		 157(define_mode_iterator VALL [V8QI V16QI V4HI V8HI V2SI V4SI V2DI V2SF V4SF V2DF])
158
43cacb12 159;; All Advanced SIMD modes suitable for moving, loading, and storing.
71a11456
AL		 160(define_mode_iterator VALL_F16 [V8QI V16QI V4HI V8HI V2SI V4SI V2DI
161 V4HF V8HF V2SF V4SF V2DF])
162
88119b46
KT		 163;; The VALL_F16 modes except the 128-bit 2-element ones.
164(define_mode_iterator VALL_F16_NO_V2Q [V8QI V16QI V4HI V8HI V2SI V4SI
165 V4HF V8HF V2SF V4SF])
166
43cacb12 167;; All Advanced SIMD modes barring HF modes, plus DI.
a50344cb
TB		 168(define_mode_iterator VALLDI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI V2SF V4SF V2DF DI])
169
43cacb12 170;; All Advanced SIMD modes and DI.
71a11456
AL		 171(define_mode_iterator VALLDI_F16 [V8QI V16QI V4HI V8HI V2SI V4SI V2DI
172 V4HF V8HF V2SF V4SF V2DF DI])
173
43cacb12 174;; All Advanced SIMD modes, plus DI and DF.
46e778c4 175(define_mode_iterator VALLDIF [V8QI V16QI V4HI V8HI V2SI V4SI
7c369485 176 V2DI V4HF V8HF V2SF V4SF V2DF DI DF])
46e778c4 177
43cacb12 178;; Advanced SIMD modes for Integer reduction across lanes.
92835317
TB		 179(define_mode_iterator VDQV [V8QI V16QI V4HI V8HI V4SI V2DI])
180
43cacb12 181;; Advanced SIMD modes (except V2DI) for Integer reduction across lanes.
92835317 182(define_mode_iterator VDQV_S [V8QI V16QI V4HI V8HI V4SI])
43e9d192
IB		 183
184;; All double integer narrow-able modes.
185(define_mode_iterator VDN [V4HI V2SI DI])
186
187;; All quad integer narrow-able modes.
188(define_mode_iterator VQN [V8HI V4SI V2DI])
189
43cacb12
RS		 190;; Advanced SIMD and scalar 128-bit container: narrowable 16, 32, 64-bit
191;; integer modes
43e9d192
IB		 192(define_mode_iterator VSQN_HSDI [V8HI V4SI V2DI HI SI DI])
193
194;; All quad integer widen-able modes.
195(define_mode_iterator VQW [V16QI V8HI V4SI])
196
197;; Double vector modes for combines.
7c369485 198(define_mode_iterator VDC [V8QI V4HI V4HF V2SI V2SF DI DF])
43e9d192 199
43cacb12 200;; Advanced SIMD modes except double int.
43e9d192 201(define_mode_iterator VDQIF [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF V2DF])
703bbcdf
JW		 202(define_mode_iterator VDQIF_F16 [V8QI V16QI V4HI V8HI V2SI V4SI
203 V4HF V8HF V2SF V4SF V2DF])
43e9d192 204
43cacb12 205;; Advanced SIMD modes for S type.
58a3bd25
FY		 206(define_mode_iterator VDQ_SI [V2SI V4SI])
207
43cacb12 208;; Advanced SIMD modes for S and D.
2644d4d9
JW		 209(define_mode_iterator VDQ_SDI [V2SI V4SI V2DI])
210
43cacb12 211;; Advanced SIMD modes for H, S and D.
33d72b63
JW		 212(define_mode_iterator VDQ_HSDI [(V4HI "TARGET_SIMD_F16INST")
213 (V8HI "TARGET_SIMD_F16INST")
214 V2SI V4SI V2DI])
215
43cacb12 216;; Scalar and Advanced SIMD modes for S and D.
2644d4d9
JW		 217(define_mode_iterator VSDQ_SDI [V2SI V4SI V2DI SI DI])
218
43cacb12 219;; Scalar and Advanced SIMD modes for S and D, Advanced SIMD modes for H.
33d72b63
JW		 220(define_mode_iterator VSDQ_HSDI [(V4HI "TARGET_SIMD_F16INST")
221 (V8HI "TARGET_SIMD_F16INST")
68ad28c3
JW		 222 V2SI V4SI V2DI
223 (HI "TARGET_SIMD_F16INST")
224 SI DI])
33d72b63 225
43cacb12 226;; Advanced SIMD modes for Q and H types.
66adb8eb
JG		 227(define_mode_iterator VDQQH [V8QI V16QI V4HI V8HI])
228
43cacb12 229;; Advanced SIMD modes for H and S types.
43e9d192
IB		 230(define_mode_iterator VDQHS [V4HI V8HI V2SI V4SI])
231
43cacb12 232;; Advanced SIMD modes for H, S and D types.
c7f28cd5
KT		 233(define_mode_iterator VDQHSD [V4HI V8HI V2SI V4SI V2DI])
234
43cacb12 235;; Advanced SIMD and scalar integer modes for H and S.
43e9d192
IB		 236(define_mode_iterator VSDQ_HSI [V4HI V8HI V2SI V4SI HI SI])
237
43cacb12 238;; Advanced SIMD and scalar 64-bit container: 16, 32-bit integer modes.
43e9d192
IB		 239(define_mode_iterator VSD_HSI [V4HI V2SI HI SI])
240
43cacb12 241;; Advanced SIMD 64-bit container: 16, 32-bit integer modes.
43e9d192
IB		 242(define_mode_iterator VD_HSI [V4HI V2SI])
243
244;; Scalar 64-bit container: 16, 32-bit integer modes
245(define_mode_iterator SD_HSI [HI SI])
246
43cacb12 247;; Advanced SIMD 64-bit container: 16, 32-bit integer modes.
43e9d192
IB		 248(define_mode_iterator VQ_HSI [V8HI V4SI])
249
250;; All byte modes.
251(define_mode_iterator VB [V8QI V16QI])
252
5e32e83b
JW		 253;; 2 and 4 lane SI modes.
254(define_mode_iterator VS [V2SI V4SI])
255
43e9d192
IB		 256(define_mode_iterator TX [TI TF])
257
43cacb12 258;; Advanced SIMD opaque structure modes.
43e9d192
IB		 259(define_mode_iterator VSTRUCT [OI CI XI])
260
261;; Double scalar modes
262(define_mode_iterator DX [DI DF])
263
dfe1da23
JW		 264;; Duplicate of the above
265(define_mode_iterator DX2 [DI DF])
266
267;; Single scalar modes
268(define_mode_iterator SX [SI SF])
269
270;; Duplicate of the above
271(define_mode_iterator SX2 [SI SF])
272
273;; Single and double integer and float modes
274(define_mode_iterator DSX [DF DI SF SI])
275
276
43cacb12 277;; Modes available for Advanced SIMD <f>mul lane operations.
ab2e8f01
JW		 278(define_mode_iterator VMUL [V4HI V8HI V2SI V4SI
279 (V4HF "TARGET_SIMD_F16INST")
280 (V8HF "TARGET_SIMD_F16INST")
281 V2SF V4SF V2DF])
779aea46 282
43cacb12
RS		 283;; Modes available for Advanced SIMD <f>mul lane operations changing lane
284;; count.
779aea46
JG		 285(define_mode_iterator VMUL_CHANGE_NLANES [V4HI V8HI V2SI V4SI V2SF V4SF])
286
95eb5537 287;; Iterators for single modes, for "@" patterns.
624d0f07 288(define_mode_iterator VNx8HI_ONLY [VNx8HI])
95eb5537 289(define_mode_iterator VNx4SI_ONLY [VNx4SI])
624d0f07 290(define_mode_iterator VNx2DI_ONLY [VNx2DI])
95eb5537
RS		 291(define_mode_iterator VNx2DF_ONLY [VNx2DF])
292
9f4cbab8
RS		 293;; All SVE vector structure modes.
294(define_mode_iterator SVE_STRUCT [VNx32QI VNx16HI VNx8SI VNx4DI
295 VNx16HF VNx8SF VNx4DF
296 VNx48QI VNx24HI VNx12SI VNx6DI
297 VNx24HF VNx12SF VNx6DF
298 VNx64QI VNx32HI VNx16SI VNx8DI
299 VNx32HF VNx16SF VNx8DF])
300
f75cdd2c
RS		 301;; All fully-packed SVE vector modes.
302(define_mode_iterator SVE_FULL [VNx16QI VNx8HI VNx4SI VNx2DI
303 VNx8HF VNx4SF VNx2DF])
304
305;; All fully-packed SVE integer vector modes.
306(define_mode_iterator SVE_FULL_I [VNx16QI VNx8HI VNx4SI VNx2DI])
43cacb12 307
f75cdd2c
RS		 308;; All fully-packed SVE floating-point vector modes.
309(define_mode_iterator SVE_FULL_F [VNx8HF VNx4SF VNx2DF])
43cacb12 310
f75cdd2c
RS		 311;; Fully-packed SVE integer vector modes that have 8-bit, 16-bit or 32-bit
312;; elements.
313(define_mode_iterator SVE_FULL_BHSI [VNx16QI VNx8HI VNx4SI])
43cacb12 314
f75cdd2c
RS		 315;; Fully-packed SVE vector modes that have 16-bit, 32-bit or 64-bit elements.
316(define_mode_iterator SVE_FULL_HSD [VNx8HI VNx4SI VNx2DI VNx8HF VNx4SF VNx2DF])
95eb5537 317
f75cdd2c
RS		 318;; Fully-packed SVE integer vector modes that have 16-bit, 32-bit or 64-bit
319;; elements.
320(define_mode_iterator SVE_FULL_HSDI [VNx8HI VNx4SI VNx2DI])
95eb5537 321
f75cdd2c
RS		 322;; Fully-packed SVE floating-point vector modes that have 16-bit or 32-bit
323;; elements.
324(define_mode_iterator SVE_FULL_HSF [VNx8HF VNx4SF])
a70965b1 325
f75cdd2c
RS		 326;; Fully-packed SVE vector modes that have 32-bit or 64-bit elements.
327(define_mode_iterator SVE_FULL_SD [VNx4SI VNx2DI VNx4SF VNx2DF])
43cacb12 328
f75cdd2c
RS		 329;; Fully-packed SVE integer vector modes that have 32-bit or 64-bit elements.
330(define_mode_iterator SVE_FULL_SDI [VNx4SI VNx2DI])
bfaa08b7 331
f75cdd2c
RS		 332;; Fully-packed SVE floating-point vector modes that have 32-bit or 64-bit
333;; elements.
334(define_mode_iterator SVE_FULL_SDF [VNx4SF VNx2DF])
bfaa08b7 335
f75cdd2c
RS		 336;; Fully-packed SVE vector modes that have 32-bit elements.
337(define_mode_iterator SVE_FULL_S [VNx4SI VNx4SF])
43cacb12 338
f75cdd2c
RS		 339;; Fully-packed SVE vector modes that have 64-bit elements.
340(define_mode_iterator SVE_FULL_D [VNx2DI VNx2DF])
43cacb12 341
6544cb52
RS		 342;; All partial SVE integer modes.
343(define_mode_iterator SVE_PARTIAL_I [VNx8QI VNx4QI VNx2QI
344 VNx4HI VNx2HI
345 VNx2SI])
624d0f07 346
cc68f7c2
RS		 347;; All SVE vector modes.
348(define_mode_iterator SVE_ALL [VNx16QI VNx8QI VNx4QI VNx2QI
349 VNx8HI VNx4HI VNx2HI
350 VNx8HF VNx4HF VNx2HF
351 VNx4SI VNx2SI
352 VNx4SF VNx2SF
353 VNx2DI
354 VNx2DF])
355
356;; All SVE integer vector modes.
357(define_mode_iterator SVE_I [VNx16QI VNx8QI VNx4QI VNx2QI
358 VNx8HI VNx4HI VNx2HI
359 VNx4SI VNx2SI
360 VNx2DI])
361
e58703e2
RS		 362;; SVE integer vector modes whose elements are 16 bits or wider.
363(define_mode_iterator SVE_HSDI [VNx8HI VNx4HI VNx2HI
364 VNx4SI VNx2SI
365 VNx2DI])
366
f8186eea
RS		 367;; SVE modes with 2 or 4 elements.
368(define_mode_iterator SVE_24 [VNx2QI VNx2HI VNx2HF VNx2SI VNx2SF VNx2DI VNx2DF
369 VNx4QI VNx4HI VNx4HF VNx4SI VNx4SF])
370
371;; SVE modes with 2 elements.
372(define_mode_iterator SVE_2 [VNx2QI VNx2HI VNx2HF VNx2SI VNx2SF VNx2DI VNx2DF])
373
374;; SVE modes with 4 elements.
375(define_mode_iterator SVE_4 [VNx4QI VNx4HI VNx4HF VNx4SI VNx4SF])
376
624d0f07
RS		 377;; Modes involved in extending or truncating SVE data, for 8 elements per
378;; 128-bit block.
379(define_mode_iterator VNx8_NARROW [VNx8QI])
380(define_mode_iterator VNx8_WIDE [VNx8HI])
381
382;; ...same for 4 elements per 128-bit block.
383(define_mode_iterator VNx4_NARROW [VNx4QI VNx4HI])
384(define_mode_iterator VNx4_WIDE [VNx4SI])
385
386;; ...same for 2 elements per 128-bit block.
387(define_mode_iterator VNx2_NARROW [VNx2QI VNx2HI VNx2SI])
388(define_mode_iterator VNx2_WIDE [VNx2DI])
389
43cacb12
RS		 390;; All SVE predicate modes.
391(define_mode_iterator PRED_ALL [VNx16BI VNx8BI VNx4BI VNx2BI])
392
393;; SVE predicate modes that control 8-bit, 16-bit or 32-bit elements.
394(define_mode_iterator PRED_BHS [VNx16BI VNx8BI VNx4BI])
395
624d0f07
RS		 396;; SVE predicate modes that control 16-bit, 32-bit or 64-bit elements.
397(define_mode_iterator PRED_HSD [VNx8BI VNx4BI VNx2BI])
398
43e9d192
IB		 399;; ------------------------------------------------------------------
400;; Unspec enumerations for Advance SIMD. These could well go into
401;; aarch64.md but for their use in int_iterators here.
402;; ------------------------------------------------------------------
403
404(define_c_enum "unspec"
405 [
406 UNSPEC_ASHIFT_SIGNED ; Used in aarch-simd.md.
407 UNSPEC_ASHIFT_UNSIGNED ; Used in aarch64-simd.md.
285398d2 408 UNSPEC_ABS ; Used in aarch64-simd.md.
998eaf97
JG		 409 UNSPEC_FMAX ; Used in aarch64-simd.md.
410 UNSPEC_FMAXNMV ; Used in aarch64-simd.md.
43e9d192 411 UNSPEC_FMAXV ; Used in aarch64-simd.md.
998eaf97
JG		 412 UNSPEC_FMIN ; Used in aarch64-simd.md.
413 UNSPEC_FMINNMV ; Used in aarch64-simd.md.
43e9d192
IB		 414 UNSPEC_FMINV ; Used in aarch64-simd.md.
415 UNSPEC_FADDV ; Used in aarch64-simd.md.
f5156c3e 416 UNSPEC_ADDV ; Used in aarch64-simd.md.
43e9d192
IB		 417 UNSPEC_SMAXV ; Used in aarch64-simd.md.
418 UNSPEC_SMINV ; Used in aarch64-simd.md.
419 UNSPEC_UMAXV ; Used in aarch64-simd.md.
420 UNSPEC_UMINV ; Used in aarch64-simd.md.
421 UNSPEC_SHADD ; Used in aarch64-simd.md.
422 UNSPEC_UHADD ; Used in aarch64-simd.md.
423 UNSPEC_SRHADD ; Used in aarch64-simd.md.
424 UNSPEC_URHADD ; Used in aarch64-simd.md.
425 UNSPEC_SHSUB ; Used in aarch64-simd.md.
426 UNSPEC_UHSUB ; Used in aarch64-simd.md.
427 UNSPEC_SRHSUB ; Used in aarch64-simd.md.
428 UNSPEC_URHSUB ; Used in aarch64-simd.md.
429 UNSPEC_ADDHN ; Used in aarch64-simd.md.
430 UNSPEC_RADDHN ; Used in aarch64-simd.md.
431 UNSPEC_SUBHN ; Used in aarch64-simd.md.
432 UNSPEC_RSUBHN ; Used in aarch64-simd.md.
433 UNSPEC_ADDHN2 ; Used in aarch64-simd.md.
434 UNSPEC_RADDHN2 ; Used in aarch64-simd.md.
435 UNSPEC_SUBHN2 ; Used in aarch64-simd.md.
436 UNSPEC_RSUBHN2 ; Used in aarch64-simd.md.
437 UNSPEC_SQDMULH ; Used in aarch64-simd.md.
438 UNSPEC_SQRDMULH ; Used in aarch64-simd.md.
58cc9876
YW		 439 UNSPEC_SMULLB ; Used in aarch64-sve2.md.
440 UNSPEC_SMULLT ; Used in aarch64-sve2.md.
441 UNSPEC_UMULLB ; Used in aarch64-sve2.md.
442 UNSPEC_UMULLT ; Used in aarch64-sve2.md.
43e9d192 443 UNSPEC_PMUL ; Used in aarch64-simd.md.
496ea87d 444 UNSPEC_FMULX ; Used in aarch64-simd.md.
43e9d192
IB		 445 UNSPEC_USQADD ; Used in aarch64-simd.md.
446 UNSPEC_SUQADD ; Used in aarch64-simd.md.
447 UNSPEC_SQXTUN ; Used in aarch64-simd.md.
448 UNSPEC_SQXTN ; Used in aarch64-simd.md.
449 UNSPEC_UQXTN ; Used in aarch64-simd.md.
450 UNSPEC_SSRA ; Used in aarch64-simd.md.
451 UNSPEC_USRA ; Used in aarch64-simd.md.
452 UNSPEC_SRSRA ; Used in aarch64-simd.md.
453 UNSPEC_URSRA ; Used in aarch64-simd.md.
454 UNSPEC_SRSHR ; Used in aarch64-simd.md.
455 UNSPEC_URSHR ; Used in aarch64-simd.md.
456 UNSPEC_SQSHLU ; Used in aarch64-simd.md.
457 UNSPEC_SQSHL ; Used in aarch64-simd.md.
458 UNSPEC_UQSHL ; Used in aarch64-simd.md.
459 UNSPEC_SQSHRUN ; Used in aarch64-simd.md.
460 UNSPEC_SQRSHRUN ; Used in aarch64-simd.md.
461 UNSPEC_SQSHRN ; Used in aarch64-simd.md.
462 UNSPEC_UQSHRN ; Used in aarch64-simd.md.
463 UNSPEC_SQRSHRN ; Used in aarch64-simd.md.
464 UNSPEC_UQRSHRN ; Used in aarch64-simd.md.
58cc9876
YW		 465 UNSPEC_SHRNB ; Used in aarch64-sve2.md.
466 UNSPEC_SHRNT ; Used in aarch64-sve2.md.
467 UNSPEC_RSHRNB ; Used in aarch64-sve2.md.
468 UNSPEC_RSHRNT ; Used in aarch64-sve2.md.
43e9d192
IB		 469 UNSPEC_SSHL ; Used in aarch64-simd.md.
470 UNSPEC_USHL ; Used in aarch64-simd.md.
471 UNSPEC_SRSHL ; Used in aarch64-simd.md.
472 UNSPEC_URSHL ; Used in aarch64-simd.md.
473 UNSPEC_SQRSHL ; Used in aarch64-simd.md.
474 UNSPEC_UQRSHL ; Used in aarch64-simd.md.
43e9d192
IB		 475 UNSPEC_SSLI ; Used in aarch64-simd.md.
476 UNSPEC_USLI ; Used in aarch64-simd.md.
477 UNSPEC_SSRI ; Used in aarch64-simd.md.
478 UNSPEC_USRI ; Used in aarch64-simd.md.
479 UNSPEC_SSHLL ; Used in aarch64-simd.md.
480 UNSPEC_USHLL ; Used in aarch64-simd.md.
481 UNSPEC_ADDP ; Used in aarch64-simd.md.
88b08073 482 UNSPEC_TBL ; Used in vector permute patterns.
9371aecc 483 UNSPEC_TBX ; Used in vector permute patterns.
88b08073 484 UNSPEC_CONCAT ; Used in vector permute patterns.
3f8334a5
RS		 485
486 ;; The following permute unspecs are generated directly by
487 ;; aarch64_expand_vec_perm_const, so any changes to the underlying
488 ;; instructions would need a corresponding change there.
cc4d934f
JG		 489 UNSPEC_ZIP1 ; Used in vector permute patterns.
490 UNSPEC_ZIP2 ; Used in vector permute patterns.
491 UNSPEC_UZP1 ; Used in vector permute patterns.
492 UNSPEC_UZP2 ; Used in vector permute patterns.
493 UNSPEC_TRN1 ; Used in vector permute patterns.
494 UNSPEC_TRN2 ; Used in vector permute patterns.
3f8334a5 495 UNSPEC_EXT ; Used in vector permute patterns.
923fcec3
AL		 496 UNSPEC_REV64 ; Used in vector reverse patterns (permute).
497 UNSPEC_REV32 ; Used in vector reverse patterns (permute).
498 UNSPEC_REV16 ; Used in vector reverse patterns (permute).
3f8334a5 499
5a7a4e80
TB		 500 UNSPEC_AESE ; Used in aarch64-simd.md.
501 UNSPEC_AESD ; Used in aarch64-simd.md.
502 UNSPEC_AESMC ; Used in aarch64-simd.md.
503 UNSPEC_AESIMC ; Used in aarch64-simd.md.
30442682
TB		 504 UNSPEC_SHA1C ; Used in aarch64-simd.md.
505 UNSPEC_SHA1M ; Used in aarch64-simd.md.
506 UNSPEC_SHA1P ; Used in aarch64-simd.md.
507 UNSPEC_SHA1H ; Used in aarch64-simd.md.
508 UNSPEC_SHA1SU0 ; Used in aarch64-simd.md.
509 UNSPEC_SHA1SU1 ; Used in aarch64-simd.md.
b9cb0a44
TB		 510 UNSPEC_SHA256H ; Used in aarch64-simd.md.
511 UNSPEC_SHA256H2 ; Used in aarch64-simd.md.
512 UNSPEC_SHA256SU0 ; Used in aarch64-simd.md.
513 UNSPEC_SHA256SU1 ; Used in aarch64-simd.md.
7baa225d
TB		 514 UNSPEC_PMULL ; Used in aarch64-simd.md.
515 UNSPEC_PMULL2 ; Used in aarch64-simd.md.
668046d1 516 UNSPEC_REV_REGLIST ; Used in aarch64-simd.md.
9c004c58 517 UNSPEC_VEC_SHR ; Used in aarch64-simd.md.
57b26d65
MW		 518 UNSPEC_SQRDMLAH ; Used in aarch64-simd.md.
519 UNSPEC_SQRDMLSH ; Used in aarch64-simd.md.
202d0c11
DS		 520 UNSPEC_FMAXNM ; Used in aarch64-simd.md.
521 UNSPEC_FMINNM ; Used in aarch64-simd.md.
7a08d813
TC		 522 UNSPEC_SDOT ; Used in aarch64-simd.md.
523 UNSPEC_UDOT ; Used in aarch64-simd.md.
27086ea3
MC		 524 UNSPEC_SM3SS1 ; Used in aarch64-simd.md.
525 UNSPEC_SM3TT1A ; Used in aarch64-simd.md.
526 UNSPEC_SM3TT1B ; Used in aarch64-simd.md.
527 UNSPEC_SM3TT2A ; Used in aarch64-simd.md.
528 UNSPEC_SM3TT2B ; Used in aarch64-simd.md.
529 UNSPEC_SM3PARTW1 ; Used in aarch64-simd.md.
530 UNSPEC_SM3PARTW2 ; Used in aarch64-simd.md.
531 UNSPEC_SM4E ; Used in aarch64-simd.md.
532 UNSPEC_SM4EKEY ; Used in aarch64-simd.md.
533 UNSPEC_SHA512H ; Used in aarch64-simd.md.
534 UNSPEC_SHA512H2 ; Used in aarch64-simd.md.
535 UNSPEC_SHA512SU0 ; Used in aarch64-simd.md.
536 UNSPEC_SHA512SU1 ; Used in aarch64-simd.md.
537 UNSPEC_FMLAL ; Used in aarch64-simd.md.
538 UNSPEC_FMLSL ; Used in aarch64-simd.md.
539 UNSPEC_FMLAL2 ; Used in aarch64-simd.md.
540 UNSPEC_FMLSL2 ; Used in aarch64-simd.md.
624d0f07 541 UNSPEC_ADR ; Used in aarch64-sve.md.
43cacb12 542 UNSPEC_SEL ; Used in aarch64-sve.md.
624d0f07
RS		 543 UNSPEC_BRKA ; Used in aarch64-sve.md.
544 UNSPEC_BRKB ; Used in aarch64-sve.md.
545 UNSPEC_BRKN ; Used in aarch64-sve.md.
546 UNSPEC_BRKPA ; Used in aarch64-sve.md.
547 UNSPEC_BRKPB ; Used in aarch64-sve.md.
548 UNSPEC_PFIRST ; Used in aarch64-sve.md.
549 UNSPEC_PNEXT ; Used in aarch64-sve.md.
550 UNSPEC_CNTP ; Used in aarch64-sve.md.
551 UNSPEC_SADDV ; Used in aarch64-sve.md.
552 UNSPEC_UADDV ; Used in aarch64-sve.md.
898f07b0
RS		 553 UNSPEC_ANDV ; Used in aarch64-sve.md.
554 UNSPEC_IORV ; Used in aarch64-sve.md.
555 UNSPEC_XORV ; Used in aarch64-sve.md.
43cacb12
RS		 556 UNSPEC_ANDF ; Used in aarch64-sve.md.
557 UNSPEC_IORF ; Used in aarch64-sve.md.
558 UNSPEC_XORF ; Used in aarch64-sve.md.
d7a09c44
RS		 559 UNSPEC_REVB ; Used in aarch64-sve.md.
560 UNSPEC_REVH ; Used in aarch64-sve.md.
561 UNSPEC_REVW ; Used in aarch64-sve.md.
11e9443f
RS		 562 UNSPEC_SMUL_HIGHPART ; Used in aarch64-sve.md.
563 UNSPEC_UMUL_HIGHPART ; Used in aarch64-sve.md.
624d0f07
RS		 564 UNSPEC_FMLA ; Used in aarch64-sve.md.
565 UNSPEC_FMLS ; Used in aarch64-sve.md.
566 UNSPEC_FEXPA ; Used in aarch64-sve.md.
567 UNSPEC_FTMAD ; Used in aarch64-sve.md.
568 UNSPEC_FTSMUL ; Used in aarch64-sve.md.
569 UNSPEC_FTSSEL ; Used in aarch64-sve.md.
570 UNSPEC_COND_CMPEQ_WIDE ; Used in aarch64-sve.md.
571 UNSPEC_COND_CMPGE_WIDE ; Used in aarch64-sve.md.
572 UNSPEC_COND_CMPGT_WIDE ; Used in aarch64-sve.md.
573 UNSPEC_COND_CMPHI_WIDE ; Used in aarch64-sve.md.
574 UNSPEC_COND_CMPHS_WIDE ; Used in aarch64-sve.md.
575 UNSPEC_COND_CMPLE_WIDE ; Used in aarch64-sve.md.
576 UNSPEC_COND_CMPLO_WIDE ; Used in aarch64-sve.md.
577 UNSPEC_COND_CMPLS_WIDE ; Used in aarch64-sve.md.
578 UNSPEC_COND_CMPLT_WIDE ; Used in aarch64-sve.md.
579 UNSPEC_COND_CMPNE_WIDE ; Used in aarch64-sve.md.
d45b20a5 580 UNSPEC_COND_FABS ; Used in aarch64-sve.md.
cb18e86d 581 UNSPEC_COND_FADD ; Used in aarch64-sve.md.
624d0f07
RS		 582 UNSPEC_COND_FCADD90 ; Used in aarch64-sve.md.
583 UNSPEC_COND_FCADD270 ; Used in aarch64-sve.md.
cb18e86d
RS		 584 UNSPEC_COND_FCMEQ ; Used in aarch64-sve.md.
585 UNSPEC_COND_FCMGE ; Used in aarch64-sve.md.
586 UNSPEC_COND_FCMGT ; Used in aarch64-sve.md.
624d0f07
RS		 587 UNSPEC_COND_FCMLA ; Used in aarch64-sve.md.
588 UNSPEC_COND_FCMLA90 ; Used in aarch64-sve.md.
589 UNSPEC_COND_FCMLA180 ; Used in aarch64-sve.md.
590 UNSPEC_COND_FCMLA270 ; Used in aarch64-sve.md.
cb18e86d
RS		 591 UNSPEC_COND_FCMLE ; Used in aarch64-sve.md.
592 UNSPEC_COND_FCMLT ; Used in aarch64-sve.md.
593 UNSPEC_COND_FCMNE ; Used in aarch64-sve.md.
4a942af6 594 UNSPEC_COND_FCMUO ; Used in aarch64-sve.md.
99361551
RS		 595 UNSPEC_COND_FCVT ; Used in aarch64-sve.md.
596 UNSPEC_COND_FCVTZS ; Used in aarch64-sve.md.
597 UNSPEC_COND_FCVTZU ; Used in aarch64-sve.md.
cb18e86d 598 UNSPEC_COND_FDIV ; Used in aarch64-sve.md.
624d0f07 599 UNSPEC_COND_FMAX ; Used in aarch64-sve.md.
cb18e86d 600 UNSPEC_COND_FMAXNM ; Used in aarch64-sve.md.
624d0f07 601 UNSPEC_COND_FMIN ; Used in aarch64-sve.md.
cb18e86d 602 UNSPEC_COND_FMINNM ; Used in aarch64-sve.md.
b41d1f6e
RS		 603 UNSPEC_COND_FMLA ; Used in aarch64-sve.md.
604 UNSPEC_COND_FMLS ; Used in aarch64-sve.md.
cb18e86d 605 UNSPEC_COND_FMUL ; Used in aarch64-sve.md.
624d0f07 606 UNSPEC_COND_FMULX ; Used in aarch64-sve.md.
d45b20a5 607 UNSPEC_COND_FNEG ; Used in aarch64-sve.md.
b41d1f6e
RS		 608 UNSPEC_COND_FNMLA ; Used in aarch64-sve.md.
609 UNSPEC_COND_FNMLS ; Used in aarch64-sve.md.
624d0f07 610 UNSPEC_COND_FRECPX ; Used in aarch64-sve.md.
d45b20a5
RS		 611 UNSPEC_COND_FRINTA ; Used in aarch64-sve.md.
612 UNSPEC_COND_FRINTI ; Used in aarch64-sve.md.
613 UNSPEC_COND_FRINTM ; Used in aarch64-sve.md.
614 UNSPEC_COND_FRINTN ; Used in aarch64-sve.md.
615 UNSPEC_COND_FRINTP ; Used in aarch64-sve.md.
616 UNSPEC_COND_FRINTX ; Used in aarch64-sve.md.
617 UNSPEC_COND_FRINTZ ; Used in aarch64-sve.md.
624d0f07 618 UNSPEC_COND_FSCALE ; Used in aarch64-sve.md.
d45b20a5 619 UNSPEC_COND_FSQRT ; Used in aarch64-sve.md.
cb18e86d 620 UNSPEC_COND_FSUB ; Used in aarch64-sve.md.
99361551
RS		 621 UNSPEC_COND_SCVTF ; Used in aarch64-sve.md.
622 UNSPEC_COND_UCVTF ; Used in aarch64-sve.md.
624d0f07 623 UNSPEC_LASTA ; Used in aarch64-sve.md.
43cacb12 624 UNSPEC_LASTB ; Used in aarch64-sve.md.
624d0f07
RS		 625 UNSPEC_ASHIFT_WIDE ; Used in aarch64-sve.md.
626 UNSPEC_ASHIFTRT_WIDE ; Used in aarch64-sve.md.
627 UNSPEC_LSHIFTRT_WIDE ; Used in aarch64-sve.md.
628 UNSPEC_LDFF1 ; Used in aarch64-sve.md.
629 UNSPEC_LDNF1 ; Used in aarch64-sve.md.
9d63f43b
TC		 630 UNSPEC_FCADD90 ; Used in aarch64-simd.md.
631 UNSPEC_FCADD270 ; Used in aarch64-simd.md.
632 UNSPEC_FCMLA ; Used in aarch64-simd.md.
633 UNSPEC_FCMLA90 ; Used in aarch64-simd.md.
634 UNSPEC_FCMLA180 ; Used in aarch64-simd.md.
635 UNSPEC_FCMLA270 ; Used in aarch64-simd.md.
58cc9876
YW		 636 UNSPEC_SMULHS ; Used in aarch64-sve2.md.
637 UNSPEC_SMULHRS ; Used in aarch64-sve2.md.
638 UNSPEC_UMULHS ; Used in aarch64-sve2.md.
639 UNSPEC_UMULHRS ; Used in aarch64-sve2.md.
c0c2f013 640 UNSPEC_ASRD ; Used in aarch64-sve.md.
43e9d192
IB		 641])
642
d81cb613
MW		 643;; ------------------------------------------------------------------
644;; Unspec enumerations for Atomics. They are here so that they can be
645;; used in the int_iterators for atomic operations.
646;; ------------------------------------------------------------------
647
648(define_c_enum "unspecv"
649 [
650 UNSPECV_LX ; Represent a load-exclusive.
651 UNSPECV_SX ; Represent a store-exclusive.
652 UNSPECV_LDA ; Represent an atomic load or load-acquire.
653 UNSPECV_STL ; Represent an atomic store or store-release.
654 UNSPECV_ATOMIC_CMPSW ; Represent an atomic compare swap.
655 UNSPECV_ATOMIC_EXCHG ; Represent an atomic exchange.
656 UNSPECV_ATOMIC_CAS ; Represent an atomic CAS.
657 UNSPECV_ATOMIC_SWP ; Represent an atomic SWP.
658 UNSPECV_ATOMIC_OP ; Represent an atomic operation.
d81cb613
MW		 659 UNSPECV_ATOMIC_LDOP_OR ; Represent an atomic load-or
660 UNSPECV_ATOMIC_LDOP_BIC ; Represent an atomic load-bic
661 UNSPECV_ATOMIC_LDOP_XOR ; Represent an atomic load-xor
662 UNSPECV_ATOMIC_LDOP_PLUS ; Represent an atomic load-add
663])
664
43e9d192
IB		 665;; -------------------------------------------------------------------
666;; Mode attributes
667;; -------------------------------------------------------------------
668
669;; In GPI templates, a string like "%<w>0" will expand to "%w0" in the
670;; 32-bit version and "%x0" in the 64-bit version.
671(define_mode_attr w [(QI "w") (HI "w") (SI "w") (DI "x") (SF "s") (DF "d")])
672
db46a2e6
JG		 673;; The size of access, in bytes.
674(define_mode_attr ldst_sz [(SI "4") (DI "8")])
675;; Likewise for load/store pair.
676(define_mode_attr ldpstp_sz [(SI "8") (DI "16")])
677
0d35c5c2 678;; For inequal width int to float conversion
d7f33f07
JW		 679(define_mode_attr w1 [(HF "w") (SF "w") (DF "x")])
680(define_mode_attr w2 [(HF "x") (SF "x") (DF "w")])
0d35c5c2 681
22be0d08
MC		 682;; For width of fp registers in fcvt instruction
683(define_mode_attr fpw [(DI "s") (SI "d")])
684
2b8568fe
KT		 685(define_mode_attr short_mask [(HI "65535") (QI "255")])
686
051d0e2f
SN		 687;; For constraints used in scalar immediate vector moves
688(define_mode_attr hq [(HI "h") (QI "q")])
689
ef22810a
RH		 690;; For doubling width of an integer mode
691(define_mode_attr DWI [(QI "HI") (HI "SI") (SI "DI") (DI "TI")])
692
22be0d08
MC		 693(define_mode_attr fcvt_change_mode [(SI "df") (DI "sf")])
694
695(define_mode_attr FCVT_CHANGE_MODE [(SI "DF") (DI "SF")])
696
43e9d192
IB		 697;; For scalar usage of vector/FP registers
698(define_mode_attr v [(QI "b") (HI "h") (SI "s") (DI "d")
d7f33f07 699 (HF "h") (SF "s") (DF "d")
43e9d192
IB		 700 (V8QI "") (V16QI "")
701 (V4HI "") (V8HI "")
702 (V2SI "") (V4SI "")
703 (V2DI "") (V2SF "")
daef0a8c
JW		 704 (V4SF "") (V4HF "")
705 (V8HF "") (V2DF "")])
43e9d192
IB		 706
707;; For scalar usage of vector/FP registers, narrowing
708(define_mode_attr vn2 [(QI "") (HI "b") (SI "h") (DI "s")
709 (V8QI "") (V16QI "")
710 (V4HI "") (V8HI "")
711 (V2SI "") (V4SI "")
712 (V2DI "") (V2SF "")
713 (V4SF "") (V2DF "")])
714
715;; For scalar usage of vector/FP registers, widening
716(define_mode_attr vw2 [(DI "") (QI "h") (HI "s") (SI "d")
717 (V8QI "") (V16QI "")
718 (V4HI "") (V8HI "")
719 (V2SI "") (V4SI "")
720 (V2DI "") (V2SF "")
721 (V4SF "") (V2DF "")])
722
89fdc743
IB		 723;; Register Type Name and Vector Arrangement Specifier for when
724;; we are doing scalar for DI and SIMD for SI (ignoring all but
725;; lane 0).
726(define_mode_attr rtn [(DI "d") (SI "")])
727(define_mode_attr vas [(DI "") (SI ".2s")])
728
7ac29c0f
RS		 729;; Map a vector to the number of units in it, if the size of the mode
730;; is constant.
731(define_mode_attr nunits [(V8QI "8") (V16QI "16")
732 (V4HI "4") (V8HI "8")
733 (V2SI "2") (V4SI "4")
734 (V2DI "2")
735 (V4HF "4") (V8HF "8")
736 (V2SF "2") (V4SF "4")
737 (V1DF "1") (V2DF "2")
738 (DI "1") (DF "1")])
739
b187677b
RS		 740;; Map a mode to the number of bits in it, if the size of the mode
741;; is constant.
742(define_mode_attr bitsize [(V8QI "64") (V16QI "128")
743 (V4HI "64") (V8HI "128")
744 (V2SI "64") (V4SI "128")
745 (V2DI "128")])
746
22be0d08
MC		 747;; Map a floating point or integer mode to the appropriate register name prefix
748(define_mode_attr s [(HF "h") (SF "s") (DF "d") (SI "s") (DI "d")])
43e9d192
IB		 749
750;; Give the length suffix letter for a sign- or zero-extension.
751(define_mode_attr size [(QI "b") (HI "h") (SI "w")])
752
753;; Give the number of bits in the mode
754(define_mode_attr sizen [(QI "8") (HI "16") (SI "32") (DI "64")])
755
756;; Give the ordinal of the MSB in the mode
315fdae8
RE		 757(define_mode_attr sizem1 [(QI "#7") (HI "#15") (SI "#31") (DI "#63")
758 (HF "#15") (SF "#31") (DF "#63")])
43e9d192 759
95eb5537
RS		 760;; The number of bits in a vector element, or controlled by a predicate
761;; element.
d7a09c44
RS		 762(define_mode_attr elem_bits [(VNx16BI "8") (VNx8BI "16")
763 (VNx4BI "32") (VNx2BI "64")
764 (VNx16QI "8") (VNx8HI "16")
765 (VNx4SI "32") (VNx2DI "64")
95eb5537
RS		 766 (VNx8HF "16") (VNx4SF "32") (VNx2DF "64")])
767
43e9d192
IB		 768;; Attribute to describe constants acceptable in logical operations
769(define_mode_attr lconst [(SI "K") (DI "L")])
770
43fd192f
MC		 771;; Attribute to describe constants acceptable in logical and operations
772(define_mode_attr lconst2 [(SI "UsO") (DI "UsP")])
773
43e9d192
IB		 774;; Map a mode to a specific constraint character.
775(define_mode_attr cmode [(QI "q") (HI "h") (SI "s") (DI "d")])
776
0603375c
KT		 777;; Map modes to Usg and Usj constraints for SISD right shifts
778(define_mode_attr cmode_simd [(SI "g") (DI "j")])
779
43e9d192
IB		 780(define_mode_attr Vtype [(V8QI "8b") (V16QI "16b")
781 (V4HI "4h") (V8HI "8h")
782 (V2SI "2s") (V4SI "4s")
783 (DI "1d") (DF "1d")
784 (V2DI "2d") (V2SF "2s")
7c369485
AL		 785 (V4SF "4s") (V2DF "2d")
786 (V4HF "4h") (V8HF "8h")])
43e9d192 787
c7f28cd5
KT		 788(define_mode_attr Vrevsuff [(V4HI "16") (V8HI "16") (V2SI "32")
789 (V4SI "32") (V2DI "64")])
790
43e9d192
IB		 791(define_mode_attr Vmtype [(V8QI ".8b") (V16QI ".16b")
792 (V4HI ".4h") (V8HI ".8h")
793 (V2SI ".2s") (V4SI ".4s")
71a11456
AL		 794 (V2DI ".2d") (V4HF ".4h")
795 (V8HF ".8h") (V2SF ".2s")
43e9d192
IB		 796 (V4SF ".4s") (V2DF ".2d")
797 (DI "") (SI "")
798 (HI "") (QI "")
d7f33f07
JW		 799 (TI "") (HF "")
800 (SF "") (DF "")])
43e9d192
IB		 801
802;; Register suffix narrowed modes for VQN.
803(define_mode_attr Vmntype [(V8HI ".8b") (V4SI ".4h")
804 (V2DI ".2s")
805 (DI "") (SI "")
806 (HI "")])
807
808;; Mode-to-individual element type mapping.
cc68f7c2
RS		 809(define_mode_attr Vetype [(V8QI "b") (V16QI "b")
810 (V4HI "h") (V8HI "h")
811 (V2SI "s") (V4SI "s")
812 (V2DI "d")
813 (V4HF "h") (V8HF "h")
814 (V2SF "s") (V4SF "s")
815 (V2DF "d")
816 (VNx16BI "b") (VNx8BI "h") (VNx4BI "s") (VNx2BI "d")
817 (VNx16QI "b") (VNx8QI "b") (VNx4QI "b") (VNx2QI "b")
818 (VNx8HI "h") (VNx4HI "h") (VNx2HI "h")
819 (VNx8HF "h") (VNx4HF "h") (VNx2HF "h")
820 (VNx4SI "s") (VNx2SI "s")
821 (VNx4SF "s") (VNx2SF "s")
822 (VNx2DI "d")
823 (VNx2DF "d")
824 (HF "h")
825 (SF "s") (DF "d")
826 (QI "b") (HI "h")
827 (SI "s") (DI "d")])
43e9d192 828
9feeafd7
AM		 829;; Like Vetype, but map to types that are a quarter of the element size.
830(define_mode_attr Vetype_fourth [(VNx4SI "b") (VNx2DI "h")])
831
43cacb12 832;; Equivalent of "size" for a vector element.
cc68f7c2
RS		 833(define_mode_attr Vesize [(VNx16QI "b") (VNx8QI "b") (VNx4QI "b") (VNx2QI "b")
834 (VNx8HI "h") (VNx4HI "h") (VNx2HI "h")
835 (VNx8HF "h") (VNx4HF "h") (VNx2HF "h")
836 (VNx4SI "w") (VNx2SI "w")
837 (VNx4SF "w") (VNx2SF "w")
838 (VNx2DI "d")
839 (VNx2DF "d")
9f4cbab8
RS		 840 (VNx32QI "b") (VNx48QI "b") (VNx64QI "b")
841 (VNx16HI "h") (VNx24HI "h") (VNx32HI "h")
842 (VNx16HF "h") (VNx24HF "h") (VNx32HF "h")
843 (VNx8SI "w") (VNx12SI "w") (VNx16SI "w")
844 (VNx8SF "w") (VNx12SF "w") (VNx16SF "w")
845 (VNx4DI "d") (VNx6DI "d") (VNx8DI "d")
846 (VNx4DF "d") (VNx6DF "d") (VNx8DF "d")])
43cacb12 847
cc68f7c2
RS		 848;; The Z register suffix for an SVE mode's element container, i.e. the
849;; Vetype of full SVE modes that have the same number of elements.
850(define_mode_attr Vctype [(VNx16QI "b") (VNx8QI "h") (VNx4QI "s") (VNx2QI "d")
851 (VNx8HI "h") (VNx4HI "s") (VNx2HI "d")
852 (VNx8HF "h") (VNx4HF "s") (VNx2HF "d")
853 (VNx4SI "s") (VNx2SI "d")
854 (VNx4SF "s") (VNx2SF "d")
855 (VNx2DI "d")
856 (VNx2DF "d")])
857
daef0a8c
JW		 858;; Vetype is used everywhere in scheduling type and assembly output,
859;; sometimes they are not the same, for example HF modes on some
860;; instructions. stype is defined to represent scheduling type
861;; more accurately.
862(define_mode_attr stype [(V8QI "b") (V16QI "b") (V4HI "s") (V8HI "s")
863 (V2SI "s") (V4SI "s") (V2DI "d") (V4HF "s")
864 (V8HF "s") (V2SF "s") (V4SF "s") (V2DF "d")
865 (HF "s") (SF "s") (DF "d") (QI "b") (HI "s")
866 (SI "s") (DI "d")])
867
43e9d192
IB		 868;; Mode-to-bitwise operation type mapping.
869(define_mode_attr Vbtype [(V8QI "8b") (V16QI "16b")
870 (V4HI "8b") (V8HI "16b")
871 (V2SI "8b") (V4SI "16b")
7c369485
AL		 872 (V2DI "16b") (V4HF "8b")
873 (V8HF "16b") (V2SF "8b")
46e778c4 874 (V4SF "16b") (V2DF "16b")
fe82d1f2 875 (DI "8b") (DF "8b")
315fdae8 876 (SI "8b") (SF "8b")])
43e9d192
IB		 877
878;; Define element mode for each vector mode.
cc68f7c2
RS		 879(define_mode_attr VEL [(V8QI "QI") (V16QI "QI")
880 (V4HI "HI") (V8HI "HI")
881 (V2SI "SI") (V4SI "SI")
882 (DI "DI") (V2DI "DI")
883 (V4HF "HF") (V8HF "HF")
884 (V2SF "SF") (V4SF "SF")
885 (DF "DF") (V2DF "DF")
886 (SI "SI") (HI "HI")
887 (QI "QI")
888 (VNx16QI "QI") (VNx8QI "QI") (VNx4QI "QI") (VNx2QI "QI")
889 (VNx8HI "HI") (VNx4HI "HI") (VNx2HI "HI")
890 (VNx8HF "HF") (VNx4HF "HF") (VNx2HF "HF")
891 (VNx4SI "SI") (VNx2SI "SI")
892 (VNx4SF "SF") (VNx2SF "SF")
893 (VNx2DI "DI")
894 (VNx2DF "DF")])
43e9d192 895
ff03930a 896;; Define element mode for each vector mode (lower case).
cc68f7c2
RS		 897(define_mode_attr Vel [(V8QI "qi") (V16QI "qi")
898 (V4HI "hi") (V8HI "hi")
899 (V2SI "si") (V4SI "si")
900 (DI "di") (V2DI "di")
901 (V4HF "hf") (V8HF "hf")
902 (V2SF "sf") (V4SF "sf")
903 (V2DF "df") (DF "df")
904 (SI "si") (HI "hi")
905 (QI "qi")
906 (VNx16QI "qi") (VNx8QI "qi") (VNx4QI "qi") (VNx2QI "qi")
907 (VNx8HI "hi") (VNx4HI "hi") (VNx2HI "hi")
908 (VNx8HF "hf") (VNx4HF "hf") (VNx2HF "hf")
909 (VNx4SI "si") (VNx2SI "si")
910 (VNx4SF "sf") (VNx2SF "sf")
911 (VNx2DI "di")
912 (VNx2DF "df")])
ff03930a 913
43cacb12
RS		 914;; Element mode with floating-point values replaced by like-sized integers.
915(define_mode_attr VEL_INT [(VNx16QI "QI")
916 (VNx8HI "HI") (VNx8HF "HI")
917 (VNx4SI "SI") (VNx4SF "SI")
918 (VNx2DI "DI") (VNx2DF "DI")])
919
920;; Gives the mode of the 128-bit lowpart of an SVE vector.
921(define_mode_attr V128 [(VNx16QI "V16QI")
922 (VNx8HI "V8HI") (VNx8HF "V8HF")
923 (VNx4SI "V4SI") (VNx4SF "V4SF")
924 (VNx2DI "V2DI") (VNx2DF "V2DF")])
925
926;; ...and again in lower case.
927(define_mode_attr v128 [(VNx16QI "v16qi")
928 (VNx8HI "v8hi") (VNx8HF "v8hf")
929 (VNx4SI "v4si") (VNx4SF "v4sf")
930 (VNx2DI "v2di") (VNx2DF "v2df")])
931
278821f2
KT		 932;; 64-bit container modes the inner or scalar source mode.
933(define_mode_attr VCOND [(HI "V4HI") (SI "V2SI")
934 (V4HI "V4HI") (V8HI "V4HI")
b7d7d917
TB		 935 (V2SI "V2SI") (V4SI "V2SI")
936 (DI "DI") (V2DI "DI")
937 (V2SF "V2SF") (V4SF "V2SF")
938 (V2DF "DF")])
939
278821f2 940;; 128-bit container modes the inner or scalar source mode.
b7d7d917
TB		 941(define_mode_attr VCONQ [(V8QI "V16QI") (V16QI "V16QI")
942 (V4HI "V8HI") (V8HI "V8HI")
943 (V2SI "V4SI") (V4SI "V4SI")
944 (DI "V2DI") (V2DI "V2DI")
71a11456 945 (V4HF "V8HF") (V8HF "V8HF")
b7d7d917
TB		 946 (V2SF "V2SF") (V4SF "V4SF")
947 (V2DF "V2DF") (SI "V4SI")
948 (HI "V8HI") (QI "V16QI")])
949
43e9d192
IB		 950;; Half modes of all vector modes.
951(define_mode_attr VHALF [(V8QI "V4QI") (V16QI "V8QI")
952 (V4HI "V2HI") (V8HI "V4HI")
953 (V2SI "SI") (V4SI "V2SI")
954 (V2DI "DI") (V2SF "SF")
71a11456
AL		 955 (V4SF "V2SF") (V4HF "V2HF")
956 (V8HF "V4HF") (V2DF "DF")])
43e9d192 957
b1b49824
MC		 958;; Half modes of all vector modes, in lower-case.
959(define_mode_attr Vhalf [(V8QI "v4qi") (V16QI "v8qi")
960 (V4HI "v2hi") (V8HI "v4hi")
41dab855 961 (V8HF "v4hf")
b1b49824
MC		 962 (V2SI "si") (V4SI "v2si")
963 (V2DI "di") (V2SF "sf")
964 (V4SF "v2sf") (V2DF "df")])
965
43e9d192
IB		 966;; Double modes of vector modes.
967(define_mode_attr VDBL [(V8QI "V16QI") (V4HI "V8HI")
71a11456 968 (V4HF "V8HF")
43e9d192
IB		 969 (V2SI "V4SI") (V2SF "V4SF")
970 (SI "V2SI") (DI "V2DI")
971 (DF "V2DF")])
972
922f9c25
AL		 973;; Register suffix for double-length mode.
974(define_mode_attr Vdtype [(V4HF "8h") (V2SF "4s")])
975
43e9d192
IB		 976;; Double modes of vector modes (lower case).
977(define_mode_attr Vdbl [(V8QI "v16qi") (V4HI "v8hi")
7c369485 978 (V4HF "v8hf")
43e9d192 979 (V2SI "v4si") (V2SF "v4sf")
8b033a8a
SN		 980 (SI "v2si") (DI "v2di")
981 (DF "v2df")])
43e9d192 982
b1b49824
MC		 983;; Modes with double-width elements.
984(define_mode_attr VDBLW [(V8QI "V4HI") (V16QI "V8HI")
985 (V4HI "V2SI") (V8HI "V4SI")
986 (V2SI "DI") (V4SI "V2DI")])
987
43e9d192
IB		 988;; Narrowed modes for VDN.
989(define_mode_attr VNARROWD [(V4HI "V8QI") (V2SI "V4HI")
990 (DI "V2SI")])
991
992;; Narrowed double-modes for VQN (Used for XTN).
993(define_mode_attr VNARROWQ [(V8HI "V8QI") (V4SI "V4HI")
994 (V2DI "V2SI")
995 (DI "SI") (SI "HI")
996 (HI "QI")])
9c437a10
RS		 997(define_mode_attr Vnarrowq [(V8HI "v8qi") (V4SI "v4hi")
998 (V2DI "v2si")])
43e9d192
IB		 999
1000;; Narrowed quad-modes for VQN (Used for XTN2).
1001(define_mode_attr VNARROWQ2 [(V8HI "V16QI") (V4SI "V8HI")
1002 (V2DI "V4SI")])
1003
1004;; Register suffix narrowed modes for VQN.
1005(define_mode_attr Vntype [(V8HI "8b") (V4SI "4h")
1006 (V2DI "2s")])
1007
1008;; Register suffix narrowed modes for VQN.
1009(define_mode_attr V2ntype [(V8HI "16b") (V4SI "8h")
1010 (V2DI "4s")])
1011
1012;; Widened modes of vector modes.
43cacb12
RS		 1013(define_mode_attr VWIDE [(V8QI "V8HI") (V4HI "V4SI")
1014 (V2SI "V2DI") (V16QI "V8HI")
1015 (V8HI "V4SI") (V4SI "V2DI")
1016 (HI "SI") (SI "DI")
1017 (V8HF "V4SF") (V4SF "V2DF")
1018 (V4HF "V4SF") (V2SF "V2DF")
1019 (VNx8HF "VNx4SF") (VNx4SF "VNx2DF")
1020 (VNx16QI "VNx8HI") (VNx8HI "VNx4SI")
1021 (VNx4SI "VNx2DI")
1022 (VNx16BI "VNx8BI") (VNx8BI "VNx4BI")
1023 (VNx4BI "VNx2BI")])
1024
1025;; Predicate mode associated with VWIDE.
1026(define_mode_attr VWIDE_PRED [(VNx8HF "VNx4BI") (VNx4SF "VNx2BI")])
43e9d192 1027
03873eb9 1028;; Widened modes of vector modes, lowercase
43cacb12
RS		 1029(define_mode_attr Vwide [(V2SF "v2df") (V4HF "v4sf")
1030 (VNx16QI "vnx8hi") (VNx8HI "vnx4si")
1031 (VNx4SI "vnx2di")
1032 (VNx8HF "vnx4sf") (VNx4SF "vnx2df")
1033 (VNx16BI "vnx8bi") (VNx8BI "vnx4bi")
1034 (VNx4BI "vnx2bi")])
03873eb9
AL		 1035
1036;; Widened mode register suffixes for VD_BHSI/VQW/VQ_HSF.
43e9d192
IB		 1037(define_mode_attr Vwtype [(V8QI "8h") (V4HI "4s")
1038 (V2SI "2d") (V16QI "8h")
03873eb9
AL		 1039 (V8HI "4s") (V4SI "2d")
1040 (V8HF "4s") (V4SF "2d")])
43e9d192 1041
43cacb12
RS		 1042;; SVE vector after widening
1043(define_mode_attr Vewtype [(VNx16QI "h")
1044 (VNx8HI "s") (VNx8HF "s")
1045 (VNx4SI "d") (VNx4SF "d")])
1046
43e9d192
IB		 1047;; Widened mode register suffixes for VDW/VQW.
1048(define_mode_attr Vmwtype [(V8QI ".8h") (V4HI ".4s")
1049 (V2SI ".2d") (V16QI ".8h")
1050 (V8HI ".4s") (V4SI ".2d")
922f9c25 1051 (V4HF ".4s") (V2SF ".2d")
43e9d192
IB		 1052 (SI "") (HI "")])
1053
03873eb9 1054;; Lower part register suffixes for VQW/VQ_HSF.
43e9d192 1055(define_mode_attr Vhalftype [(V16QI "8b") (V8HI "4h")
03873eb9
AL		 1056 (V4SI "2s") (V8HF "4h")
1057 (V4SF "2s")])
43e9d192
IB		 1058
1059;; Define corresponding core/FP element mode for each vector mode.
cc68f7c2
RS		 1060(define_mode_attr vw [(V8QI "w") (V16QI "w")
1061 (V4HI "w") (V8HI "w")
1062 (V2SI "w") (V4SI "w")
1063 (DI "x") (V2DI "x")
1064 (V2SF "s") (V4SF "s")
1065 (V2DF "d")])
43e9d192 1066
66adb8eb
JG		 1067;; Corresponding core element mode for each vector mode. This is a
1068;; variation on <vw> mapping FP modes to GP regs.
cc68f7c2
RS		 1069(define_mode_attr vwcore [(V8QI "w") (V16QI "w")
1070 (V4HI "w") (V8HI "w")
1071 (V2SI "w") (V4SI "w")
1072 (DI "x") (V2DI "x")
1073 (V4HF "w") (V8HF "w")
1074 (V2SF "w") (V4SF "w")
1075 (V2DF "x")
1076 (VNx16QI "w") (VNx8QI "w") (VNx4QI "w") (VNx2QI "w")
1077 (VNx8HI "w") (VNx4HI "w") (VNx2HI "w")
1078 (VNx8HF "w") (VNx4HF "w") (VNx2HF "w")
1079 (VNx4SI "w") (VNx2SI "w")
1080 (VNx4SF "w") (VNx2SF "w")
1081 (VNx2DI "x")
1082 (VNx2DF "x")])
66adb8eb 1083
43e9d192
IB		 1084;; Double vector types for ALLX.
1085(define_mode_attr Vallxd [(QI "8b") (HI "4h") (SI "2s")])
1086
5f565314
RS		 1087;; Mode with floating-point values replaced by like-sized integers.
1088(define_mode_attr V_INT_EQUIV [(V8QI "V8QI") (V16QI "V16QI")
1089 (V4HI "V4HI") (V8HI "V8HI")
1090 (V2SI "V2SI") (V4SI "V4SI")
1091 (DI "DI") (V2DI "V2DI")
1092 (V4HF "V4HI") (V8HF "V8HI")
1093 (V2SF "V2SI") (V4SF "V4SI")
43cacb12 1094 (DF "DI") (V2DF "V2DI")
dfe1da23
JW		 1095 (SF "SI") (SI "SI")
1096 (HF "HI")
43cacb12
RS		 1097 (VNx16QI "VNx16QI")
1098 (VNx8HI "VNx8HI") (VNx8HF "VNx8HI")
1099 (VNx4SI "VNx4SI") (VNx4SF "VNx4SI")
1100 (VNx2DI "VNx2DI") (VNx2DF "VNx2DI")
1101])
5f565314
RS		 1102
1103;; Lower case mode with floating-point values replaced by like-sized integers.
1104(define_mode_attr v_int_equiv [(V8QI "v8qi") (V16QI "v16qi")
1105 (V4HI "v4hi") (V8HI "v8hi")
1106 (V2SI "v2si") (V4SI "v4si")
1107 (DI "di") (V2DI "v2di")
1108 (V4HF "v4hi") (V8HF "v8hi")
1109 (V2SF "v2si") (V4SF "v4si")
43cacb12
RS		 1110 (DF "di") (V2DF "v2di")
1111 (SF "si")
1112 (VNx16QI "vnx16qi")
1113 (VNx8HI "vnx8hi") (VNx8HF "vnx8hi")
1114 (VNx4SI "vnx4si") (VNx4SF "vnx4si")
1115 (VNx2DI "vnx2di") (VNx2DF "vnx2di")
1116])
1117
1118;; Floating-point equivalent of selected modes.
a70965b1
RS		 1119(define_mode_attr V_FP_EQUIV [(VNx8HI "VNx8HF") (VNx8HF "VNx8HF")
1120 (VNx4SI "VNx4SF") (VNx4SF "VNx4SF")
43cacb12 1121 (VNx2DI "VNx2DF") (VNx2DF "VNx2DF")])
a70965b1
RS		 1122(define_mode_attr v_fp_equiv [(VNx8HI "vnx8hf") (VNx8HF "vnx8hf")
1123 (VNx4SI "vnx4sf") (VNx4SF "vnx4sf")
43cacb12 1124 (VNx2DI "vnx2df") (VNx2DF "vnx2df")])
70c67693 1125
f8186eea
RS		 1126;; Maps full and partial vector modes of any element type to a full-vector
1127;; integer mode with the same number of units.
1128(define_mode_attr V_INT_CONTAINER [(VNx16QI "VNx16QI") (VNx8QI "VNx8HI")
1129 (VNx4QI "VNx4SI") (VNx2QI "VNx2DI")
1130 (VNx8HI "VNx8HI") (VNx4HI "VNx4SI")
1131 (VNx2HI "VNx2DI")
1132 (VNx4SI "VNx4SI") (VNx2SI "VNx2DI")
1133 (VNx2DI "VNx2DI")
1134 (VNx8HF "VNx8HI") (VNx4HF "VNx4SI")
1135 (VNx2HF "VNx2DI")
1136 (VNx4SF "VNx4SI") (VNx2SF "VNx2SI")
1137 (VNx2DF "VNx2DI")])
1138
1139;; Lower-case version of V_INT_CONTAINER.
1140(define_mode_attr v_int_container [(VNx16QI "vnx16qi") (VNx8QI "vnx8hi")
1141 (VNx4QI "vnx4si") (VNx2QI "vnx2di")
1142 (VNx8HI "vnx8hi") (VNx4HI "vnx4si")
1143 (VNx2HI "vnx2di")
1144 (VNx4SI "vnx4si") (VNx2SI "vnx2di")
1145 (VNx2DI "vnx2di")
1146 (VNx8HF "vnx8hi") (VNx4HF "vnx4si")
1147 (VNx2HF "vnx2di")
1148 (VNx4SF "vnx4si") (VNx2SF "vnx2di")
1149 (VNx2DF "vnx2di")])
1150
6c553b76
BC		 1151;; Mode for vector conditional operations where the comparison has
1152;; different type from the lhs.
1153(define_mode_attr V_cmp_mixed [(V2SI "V2SF") (V4SI "V4SF")
1154 (V2DI "V2DF") (V2SF "V2SI")
1155 (V4SF "V4SI") (V2DF "V2DI")])
1156
1157(define_mode_attr v_cmp_mixed [(V2SI "v2sf") (V4SI "v4sf")
1158 (V2DI "v2df") (V2SF "v2si")
1159 (V4SF "v4si") (V2DF "v2di")])
1160
cb23a30c
JG		 1161;; Lower case element modes (as used in shift immediate patterns).
1162(define_mode_attr ve_mode [(V8QI "qi") (V16QI "qi")
1163 (V4HI "hi") (V8HI "hi")
1164 (V2SI "si") (V4SI "si")
1165 (DI "di") (V2DI "di")
1166 (QI "qi") (HI "hi")
1167 (SI "si")])
1168
43e9d192
IB		 1169;; Vm for lane instructions is restricted to FP_LO_REGS.
1170(define_mode_attr vwx [(V4HI "x") (V8HI "x") (HI "x")
1171 (V2SI "w") (V4SI "w") (SI "w")])
1172
1173(define_mode_attr Vendreg [(OI "T") (CI "U") (XI "V")])
1174
97755701
AL		 1175;; This is both the number of Q-Registers needed to hold the corresponding
1176;; opaque large integer mode, and the number of elements touched by the
1177;; ld..._lane and st..._lane operations.
43e9d192
IB		 1178(define_mode_attr nregs [(OI "2") (CI "3") (XI "4")])
1179
0462169c
SN		 1180;; Mode for atomic operation suffixes
1181(define_mode_attr atomic_sfx
1182 [(QI "b") (HI "h") (SI "") (DI "")])
1183
3f598afe 1184(define_mode_attr fcvt_target [(V2DF "v2di") (V4SF "v4si") (V2SF "v2si")
2644d4d9 1185 (V2DI "v2df") (V4SI "v4sf") (V2SI "v2sf")
daef0a8c
JW		 1186 (SF "si") (DF "di") (SI "sf") (DI "df")
1187 (V4HF "v4hi") (V8HF "v8hi") (V4HI "v4hf")
68ad28c3 1188 (V8HI "v8hf") (HF "hi") (HI "hf")])
3f598afe 1189(define_mode_attr FCVT_TARGET [(V2DF "V2DI") (V4SF "V4SI") (V2SF "V2SI")
2644d4d9 1190 (V2DI "V2DF") (V4SI "V4SF") (V2SI "V2SF")
daef0a8c
JW		 1191 (SF "SI") (DF "DI") (SI "SF") (DI "DF")
1192 (V4HF "V4HI") (V8HF "V8HI") (V4HI "V4HF")
68ad28c3 1193 (V8HI "V8HF") (HF "HI") (HI "HF")])
3f598afe 1194
0d35c5c2
VP		 1195
1196;; for the inequal width integer to fp conversions
d7f33f07
JW		 1197(define_mode_attr fcvt_iesize [(HF "di") (SF "di") (DF "si")])
1198(define_mode_attr FCVT_IESIZE [(HF "DI") (SF "DI") (DF "SI")])
42fc9a7f 1199
91bd4114
JG		 1200(define_mode_attr VSWAP_WIDTH [(V8QI "V16QI") (V16QI "V8QI")
1201 (V4HI "V8HI") (V8HI "V4HI")
1202 (V2SI "V4SI") (V4SI "V2SI")
1203 (DI "V2DI") (V2DI "DI")
1204 (V2SF "V4SF") (V4SF "V2SF")
862abc04 1205 (V4HF "V8HF") (V8HF "V4HF")
91bd4114
JG		 1206 (DF "V2DF") (V2DF "DF")])
1207
1208(define_mode_attr vswap_width_name [(V8QI "to_128") (V16QI "to_64")
1209 (V4HI "to_128") (V8HI "to_64")
1210 (V2SI "to_128") (V4SI "to_64")
1211 (DI "to_128") (V2DI "to_64")
862abc04 1212 (V4HF "to_128") (V8HF "to_64")
91bd4114
JG		 1213 (V2SF "to_128") (V4SF "to_64")
1214 (DF "to_128") (V2DF "to_64")])
1215
779aea46 1216;; For certain vector-by-element multiplication instructions we must
6d06971d 1217;; constrain the 16-bit cases to use only V0-V15. This is covered by
779aea46
JG		 1218;; the 'x' constraint. All other modes may use the 'w' constraint.
1219(define_mode_attr h_con [(V2SI "w") (V4SI "w")
1220 (V4HI "x") (V8HI "x")
6d06971d 1221 (V4HF "x") (V8HF "x")
779aea46
JG		 1222 (V2SF "w") (V4SF "w")
1223 (V2DF "w") (DF "w")])
1224
1225;; Defined to 'f' for types whose element type is a float type.
1226(define_mode_attr f [(V8QI "") (V16QI "")
1227 (V4HI "") (V8HI "")
1228 (V2SI "") (V4SI "")
1229 (DI "") (V2DI "")
ab2e8f01 1230 (V4HF "f") (V8HF "f")
779aea46
JG		 1231 (V2SF "f") (V4SF "f")
1232 (V2DF "f") (DF "f")])
1233
0f686aa9
JG		 1234;; Defined to '_fp' for types whose element type is a float type.
1235(define_mode_attr fp [(V8QI "") (V16QI "")
1236 (V4HI "") (V8HI "")
1237 (V2SI "") (V4SI "")
1238 (DI "") (V2DI "")
ab2e8f01 1239 (V4HF "_fp") (V8HF "_fp")
0f686aa9
JG		 1240 (V2SF "_fp") (V4SF "_fp")
1241 (V2DF "_fp") (DF "_fp")
1242 (SF "_fp")])
1243
a9e66678
JG		 1244;; Defined to '_q' for 128-bit types.
1245(define_mode_attr q [(V8QI "") (V16QI "_q")
0f686aa9
JG		 1246 (V4HI "") (V8HI "_q")
1247 (V2SI "") (V4SI "_q")
1248 (DI "") (V2DI "_q")
71a11456 1249 (V4HF "") (V8HF "_q")
0f686aa9
JG		 1250 (V2SF "") (V4SF "_q")
1251 (V2DF "_q")
d7f33f07 1252 (QI "") (HI "") (SI "") (DI "") (HF "") (SF "") (DF "")])
a9e66678 1253
92835317
TB		 1254(define_mode_attr vp [(V8QI "v") (V16QI "v")
1255 (V4HI "v") (V8HI "v")
1256 (V2SI "p") (V4SI "v")
703bbcdf
JW		 1257 (V2DI "p") (V2DF "p")
1258 (V2SF "p") (V4SF "v")
1259 (V4HF "v") (V8HF "v")])
92835317 1260
9feeafd7
AM		 1261(define_mode_attr vsi2qi [(V2SI "v8qi") (V4SI "v16qi")
1262 (VNx4SI "vnx16qi") (VNx2DI "vnx8hi")])
1263(define_mode_attr VSI2QI [(V2SI "V8QI") (V4SI "V16QI")
1264 (VNx4SI "VNx16QI") (VNx2DI "VNx8HI")])
5e32e83b 1265
7a08d813
TC		 1266
1267;; Register suffix for DOTPROD input types from the return type.
1268(define_mode_attr Vdottype [(V2SI "8b") (V4SI "16b")])
1269
cd78b3dd 1270;; Sum of lengths of instructions needed to move vector registers of a mode.
668046d1
DS		 1271(define_mode_attr insn_count [(OI "8") (CI "12") (XI "16")])
1272
1b1e81f8
JW		 1273;; -fpic small model GOT reloc modifers: gotpage_lo15/lo14 for ILP64/32.
1274;; No need of iterator for -fPIC as it use got_lo12 for both modes.
1275(define_mode_attr got_modifier [(SI "gotpage_lo14") (DI "gotpage_lo15")])
1276
27086ea3
MC		 1277;; Width of 2nd and 3rd arguments to fp16 vector multiply add/sub
1278(define_mode_attr VFMLA_W [(V2SF "V4HF") (V4SF "V8HF")])
1279
1280(define_mode_attr VFMLA_SEL_W [(V2SF "V2HF") (V4SF "V4HF")])
1281
1282(define_mode_attr f16quad [(V2SF "") (V4SF "q")])
1283
1284(define_code_attr f16mac [(plus "a") (minus "s")])
1285
8544ed6e
KT		 1286;; Map smax to smin and umax to umin.
1287(define_code_attr max_opp [(smax "smin") (umax "umin")])
1288
a9fad8fe
AM		 1289;; Same as above, but louder.
1290(define_code_attr MAX_OPP [(smax "SMIN") (umax "UMIN")])
1291
9f4cbab8
RS		 1292;; The number of subvectors in an SVE_STRUCT.
1293(define_mode_attr vector_count [(VNx32QI "2") (VNx16HI "2")
1294 (VNx8SI "2") (VNx4DI "2")
1295 (VNx16HF "2") (VNx8SF "2") (VNx4DF "2")
1296 (VNx48QI "3") (VNx24HI "3")
1297 (VNx12SI "3") (VNx6DI "3")
1298 (VNx24HF "3") (VNx12SF "3") (VNx6DF "3")
1299 (VNx64QI "4") (VNx32HI "4")
1300 (VNx16SI "4") (VNx8DI "4")
1301 (VNx32HF "4") (VNx16SF "4") (VNx8DF "4")])
1302
1303;; The number of instruction bytes needed for an SVE_STRUCT move. This is
1304;; equal to vector_count * 4.
1305(define_mode_attr insn_length [(VNx32QI "8") (VNx16HI "8")
1306 (VNx8SI "8") (VNx4DI "8")
1307 (VNx16HF "8") (VNx8SF "8") (VNx4DF "8")
1308 (VNx48QI "12") (VNx24HI "12")
1309 (VNx12SI "12") (VNx6DI "12")
1310 (VNx24HF "12") (VNx12SF "12") (VNx6DF "12")
1311 (VNx64QI "16") (VNx32HI "16")
1312 (VNx16SI "16") (VNx8DI "16")
1313 (VNx32HF "16") (VNx16SF "16") (VNx8DF "16")])
1314
1315;; The type of a subvector in an SVE_STRUCT.
1316(define_mode_attr VSINGLE [(VNx32QI "VNx16QI")
1317 (VNx16HI "VNx8HI") (VNx16HF "VNx8HF")
1318 (VNx8SI "VNx4SI") (VNx8SF "VNx4SF")
1319 (VNx4DI "VNx2DI") (VNx4DF "VNx2DF")
1320 (VNx48QI "VNx16QI")
1321 (VNx24HI "VNx8HI") (VNx24HF "VNx8HF")
1322 (VNx12SI "VNx4SI") (VNx12SF "VNx4SF")
1323 (VNx6DI "VNx2DI") (VNx6DF "VNx2DF")
1324 (VNx64QI "VNx16QI")
1325 (VNx32HI "VNx8HI") (VNx32HF "VNx8HF")
1326 (VNx16SI "VNx4SI") (VNx16SF "VNx4SF")
1327 (VNx8DI "VNx2DI") (VNx8DF "VNx2DF")])
1328
1329;; ...and again in lower case.
1330(define_mode_attr vsingle [(VNx32QI "vnx16qi")
1331 (VNx16HI "vnx8hi") (VNx16HF "vnx8hf")
1332 (VNx8SI "vnx4si") (VNx8SF "vnx4sf")
1333 (VNx4DI "vnx2di") (VNx4DF "vnx2df")
1334 (VNx48QI "vnx16qi")
1335 (VNx24HI "vnx8hi") (VNx24HF "vnx8hf")
1336 (VNx12SI "vnx4si") (VNx12SF "vnx4sf")
1337 (VNx6DI "vnx2di") (VNx6DF "vnx2df")
1338 (VNx64QI "vnx16qi")
1339 (VNx32HI "vnx8hi") (VNx32HF "vnx8hf")
1340 (VNx16SI "vnx4si") (VNx16SF "vnx4sf")
1341 (VNx8DI "vnx2di") (VNx8DF "vnx2df")])
1342
1343;; The predicate mode associated with an SVE data mode. For structure modes
1344;; this is equivalent to the <VPRED> of the subvector mode.
cc68f7c2
RS		 1345(define_mode_attr VPRED [(VNx16QI "VNx16BI") (VNx8QI "VNx8BI")
1346 (VNx4QI "VNx4BI") (VNx2QI "VNx2BI")
1347 (VNx8HI "VNx8BI") (VNx4HI "VNx4BI") (VNx2HI "VNx2BI")
1348 (VNx8HF "VNx8BI") (VNx4HF "VNx4BI") (VNx2HF "VNx2BI")
1349 (VNx4SI "VNx4BI") (VNx2SI "VNx2BI")
1350 (VNx4SF "VNx4BI") (VNx2SF "VNx2BI")
1351 (VNx2DI "VNx2BI")
1352 (VNx2DF "VNx2BI")
9f4cbab8
RS		 1353 (VNx32QI "VNx16BI")
1354 (VNx16HI "VNx8BI") (VNx16HF "VNx8BI")
1355 (VNx8SI "VNx4BI") (VNx8SF "VNx4BI")
1356 (VNx4DI "VNx2BI") (VNx4DF "VNx2BI")
1357 (VNx48QI "VNx16BI")
1358 (VNx24HI "VNx8BI") (VNx24HF "VNx8BI")
1359 (VNx12SI "VNx4BI") (VNx12SF "VNx4BI")
1360 (VNx6DI "VNx2BI") (VNx6DF "VNx2BI")
1361 (VNx64QI "VNx16BI")
1362 (VNx32HI "VNx8BI") (VNx32HF "VNx8BI")
1363 (VNx16SI "VNx4BI") (VNx16SF "VNx4BI")
1364 (VNx8DI "VNx2BI") (VNx8DF "VNx2BI")])
43cacb12
RS		 1365
1366;; ...and again in lower case.
cc68f7c2
RS		 1367(define_mode_attr vpred [(VNx16QI "vnx16bi") (VNx8QI "vnx8bi")
1368 (VNx4QI "vnx4bi") (VNx2QI "vnx2bi")
1369 (VNx8HI "vnx8bi") (VNx4HI "vnx4bi") (VNx2HI "vnx2bi")
1370 (VNx8HF "vnx8bi") (VNx4HF "vnx4bi") (VNx2HF "vnx2bi")
1371 (VNx4SI "vnx4bi") (VNx2SI "vnx2bi")
1372 (VNx4SF "vnx4bi") (VNx2SF "vnx2bi")
1373 (VNx2DI "vnx2bi")
1374 (VNx2DF "vnx2bi")
9f4cbab8
RS		 1375 (VNx32QI "vnx16bi")
1376 (VNx16HI "vnx8bi") (VNx16HF "vnx8bi")
1377 (VNx8SI "vnx4bi") (VNx8SF "vnx4bi")
1378 (VNx4DI "vnx2bi") (VNx4DF "vnx2bi")
1379 (VNx48QI "vnx16bi")
1380 (VNx24HI "vnx8bi") (VNx24HF "vnx8bi")
1381 (VNx12SI "vnx4bi") (VNx12SF "vnx4bi")
1382 (VNx6DI "vnx2bi") (VNx6DF "vnx2bi")
1383 (VNx64QI "vnx16bi")
1384 (VNx32HI "vnx8bi") (VNx32HF "vnx4bi")
1385 (VNx16SI "vnx4bi") (VNx16SF "vnx4bi")
1386 (VNx8DI "vnx2bi") (VNx8DF "vnx2bi")])
43cacb12 1387
9d63f43b
TC		 1388;; On AArch64 the By element instruction doesn't have a 2S variant.
1389;; However because the instruction always selects a pair of values
1390;; The normal 3SAME instruction can be used here instead.
1391(define_mode_attr FCMLA_maybe_lane [(V2SF "<Vtype>") (V4SF "<Vetype>[%4]")
1392 (V4HF "<Vetype>[%4]") (V8HF "<Vetype>[%4]")
1393 ])
1394
34467289
RS		 1395;; The number of bytes controlled by a predicate
1396(define_mode_attr data_bytes [(VNx16BI "1") (VNx8BI "2")
1397 (VNx4BI "4") (VNx2BI "8")])
1398
624d0f07
RS		 1399;; Two-nybble mask for partial vector modes: nunits, byte size.
1400(define_mode_attr self_mask [(VNx8QI "0x81")
1401 (VNx4QI "0x41")
1402 (VNx2QI "0x21")
1403 (VNx4HI "0x42")
1404 (VNx2HI "0x22")
1405 (VNx2SI "0x24")])
1406
e58703e2
RS		 1407;; For SVE_HSDI vector modes, the mask of narrower modes, encoded as above.
1408(define_mode_attr narrower_mask [(VNx8HI "0x81") (VNx4HI "0x41")
1409 (VNx2HI "0x21")
1410 (VNx4SI "0x43") (VNx2SI "0x23")
624d0f07
RS		 1411 (VNx2DI "0x27")])
1412
1413;; The constraint to use for an SVE [SU]DOT, FMUL, FMLA or FMLS lane index.
1414(define_mode_attr sve_lane_con [(VNx4SI "y") (VNx2DI "x")
1415 (VNx8HF "y") (VNx4SF "y") (VNx2DF "x")])
1416
1417;; The constraint to use for an SVE FCMLA lane index.
1418(define_mode_attr sve_lane_pair_con [(VNx8HF "y") (VNx4SF "x")])
1419
43e9d192
IB		 1420;; -------------------------------------------------------------------
1421;; Code Iterators
1422;; -------------------------------------------------------------------
1423
1424;; This code iterator allows the various shifts supported on the core
1425(define_code_iterator SHIFT [ashift ashiftrt lshiftrt rotatert])
1426
1427;; This code iterator allows the shifts supported in arithmetic instructions
1428(define_code_iterator ASHIFT [ashift ashiftrt lshiftrt])
1429
462e6f9a
ST		 1430(define_code_iterator SHIFTRT [ashiftrt lshiftrt])
1431
43e9d192
IB		 1432;; Code iterator for logical operations
1433(define_code_iterator LOGICAL [and ior xor])
1434
43cacb12
RS		 1435;; LOGICAL without AND.
1436(define_code_iterator LOGICAL_OR [ior xor])
1437
84be6032
AL		 1438;; Code iterator for logical operations whose :nlogical works on SIMD registers.
1439(define_code_iterator NLOGICAL [and ior])
1440
3204ac98
KT		 1441;; Code iterator for unary negate and bitwise complement.
1442(define_code_iterator NEG_NOT [neg not])
1443
43e9d192
IB		 1444;; Code iterator for sign/zero extension
1445(define_code_iterator ANY_EXTEND [sign_extend zero_extend])
1446
1447;; All division operations (signed/unsigned)
1448(define_code_iterator ANY_DIV [div udiv])
1449
1450;; Code iterator for sign/zero extraction
1451(define_code_iterator ANY_EXTRACT [sign_extract zero_extract])
1452
1453;; Code iterator for equality comparisons
1454(define_code_iterator EQL [eq ne])
1455
1456;; Code iterator for less-than and greater/equal-to
1457(define_code_iterator LTGE [lt ge])
1458
1459;; Iterator for __sync_<op> operations that where the operation can be
1460;; represented directly RTL. This is all of the sync operations bar
1461;; nand.
0462169c 1462(define_code_iterator atomic_op [plus minus ior xor and])
43e9d192
IB		 1463
1464;; Iterator for integer conversions
1465(define_code_iterator FIXUORS [fix unsigned_fix])
1466
1709ff9b
JG		 1467;; Iterator for float conversions
1468(define_code_iterator FLOATUORS [float unsigned_float])
1469
43e9d192
IB		 1470;; Code iterator for variants of vector max and min.
1471(define_code_iterator MAXMIN [smax smin umax umin])
1472
998eaf97
JG		 1473(define_code_iterator FMAXMIN [smax smin])
1474
8544ed6e
KT		 1475;; Signed and unsigned max operations.
1476(define_code_iterator USMAX [smax umax])
1477
dd550c99 1478;; Code iterator for plus and minus.
43e9d192
IB		 1479(define_code_iterator ADDSUB [plus minus])
1480
1481;; Code iterator for variants of vector saturating binary ops.
1482(define_code_iterator BINQOPS [ss_plus us_plus ss_minus us_minus])
1483
1484;; Code iterator for variants of vector saturating unary ops.
1485(define_code_iterator UNQOPS [ss_neg ss_abs])
1486
1487;; Code iterator for signed variants of vector saturating binary ops.
1488(define_code_iterator SBINQOPS [ss_plus ss_minus])
1489
624d0f07
RS		 1490;; Code iterator for unsigned variants of vector saturating binary ops.
1491(define_code_iterator UBINQOPS [us_plus us_minus])
1492
1493;; Modular and saturating addition.
1494(define_code_iterator ANY_PLUS [plus ss_plus us_plus])
1495
1496;; Saturating addition.
1497(define_code_iterator SAT_PLUS [ss_plus us_plus])
1498
1499;; Modular and saturating subtraction.
1500(define_code_iterator ANY_MINUS [minus ss_minus us_minus])
1501
1502;; Saturating subtraction.
1503(define_code_iterator SAT_MINUS [ss_minus us_minus])
1504
889b9412
JG		 1505;; Comparison operators for <F>CM.
1506(define_code_iterator COMPARISONS [lt le eq ge gt])
1507
1508;; Unsigned comparison operators.
1509(define_code_iterator UCOMPARISONS [ltu leu geu gtu])
1510
75dd5ace
JG		 1511;; Unsigned comparison operators.
1512(define_code_iterator FAC_COMPARISONS [lt le ge gt])
1513
43cacb12 1514;; SVE integer unary operations.
bca5a997 1515(define_code_iterator SVE_INT_UNARY [abs neg not clrsb clz popcount])
43cacb12 1516
a08acce8 1517;; SVE integer binary operations.
6c4fd4a9 1518(define_code_iterator SVE_INT_BINARY [plus minus mult smax umax smin umin
20103c0e 1519 ashift ashiftrt lshiftrt
9d4ac06e
RS		 1520 and ior xor])
1521
a08acce8 1522;; SVE integer binary division operations.
c38f7319
RS		 1523(define_code_iterator SVE_INT_BINARY_SD [div udiv])
1524
f8c22a8b
RS		 1525;; SVE integer binary operations that have an immediate form.
1526(define_code_iterator SVE_INT_BINARY_IMM [mult smax smin umax umin])
1527
740c1ed7
RS		 1528;; SVE floating-point operations with an unpredicated all-register form.
1529(define_code_iterator SVE_UNPRED_FP_BINARY [plus minus mult])
1530
f22d7973
RS		 1531;; SVE integer comparisons.
1532(define_code_iterator SVE_INT_CMP [lt le eq ne ge gt ltu leu geu gtu])
1533
43e9d192
IB		 1534;; -------------------------------------------------------------------
1535;; Code Attributes
1536;; -------------------------------------------------------------------
1537;; Map rtl objects to optab names
1538(define_code_attr optab [(ashift "ashl")
1539 (ashiftrt "ashr")
1540 (lshiftrt "lshr")
1541 (rotatert "rotr")
1542 (sign_extend "extend")
1543 (zero_extend "zero_extend")
1544 (sign_extract "extv")
1545 (zero_extract "extzv")
384be29f
JG		 1546 (fix "fix")
1547 (unsigned_fix "fixuns")
1709ff9b
JG		 1548 (float "float")
1549 (unsigned_float "floatuns")
bca5a997
RS		 1550 (clrsb "clrsb")
1551 (clz "clz")
43cacb12 1552 (popcount "popcount")
43e9d192
IB		 1553 (and "and")
1554 (ior "ior")
1555 (xor "xor")
1556 (not "one_cmpl")
1557 (neg "neg")
1558 (plus "add")
1559 (minus "sub")
6c4fd4a9 1560 (mult "mul")
c38f7319
RS		 1561 (div "div")
1562 (udiv "udiv")
43e9d192
IB		 1563 (ss_plus "qadd")
1564 (us_plus "qadd")
1565 (ss_minus "qsub")
1566 (us_minus "qsub")
1567 (ss_neg "qneg")
1568 (ss_abs "qabs")
43cacb12
RS		 1569 (smin "smin")
1570 (smax "smax")
1571 (umin "umin")
1572 (umax "umax")
43e9d192
IB		 1573 (eq "eq")
1574 (ne "ne")
1575 (lt "lt")
889b9412
JG		 1576 (ge "ge")
1577 (le "le")
1578 (gt "gt")
1579 (ltu "ltu")
1580 (leu "leu")
1581 (geu "geu")
43cacb12 1582 (gtu "gtu")
d45b20a5 1583 (abs "abs")])
889b9412
JG		 1584
1585;; For comparison operators we use the FCM* and CM* instructions.
1586;; As there are no CMLE or CMLT instructions which act on 3 vector
1587;; operands, we must use CMGE or CMGT and swap the order of the
1588;; source operands.
1589
1590(define_code_attr n_optab [(lt "gt") (le "ge") (eq "eq") (ge "ge") (gt "gt")
1591 (ltu "hi") (leu "hs") (geu "hs") (gtu "hi")])
1592(define_code_attr cmp_1 [(lt "2") (le "2") (eq "1") (ge "1") (gt "1")
1593 (ltu "2") (leu "2") (geu "1") (gtu "1")])
1594(define_code_attr cmp_2 [(lt "1") (le "1") (eq "2") (ge "2") (gt "2")
1595 (ltu "1") (leu "1") (geu "2") (gtu "2")])
1596
1597(define_code_attr CMP [(lt "LT") (le "LE") (eq "EQ") (ge "GE") (gt "GT")
714e1b3b
KT		 1598 (ltu "LTU") (leu "LEU") (ne "NE") (geu "GEU")
1599 (gtu "GTU")])
43e9d192 1600
f22d7973
RS		 1601;; The AArch64 condition associated with an rtl comparison code.
1602(define_code_attr cmp_op [(lt "lt")
1603 (le "le")
1604 (eq "eq")
1605 (ne "ne")
1606 (ge "ge")
1607 (gt "gt")
1608 (ltu "lo")
1609 (leu "ls")
1610 (geu "hs")
1611 (gtu "hi")])
1612
384be29f
JG		 1613(define_code_attr fix_trunc_optab [(fix "fix_trunc")
1614 (unsigned_fix "fixuns_trunc")])
1615
43e9d192
IB		 1616;; Optab prefix for sign/zero-extending operations
1617(define_code_attr su_optab [(sign_extend "") (zero_extend "u")
1618 (div "") (udiv "u")
1619 (fix "") (unsigned_fix "u")
1709ff9b 1620 (float "s") (unsigned_float "u")
43e9d192
IB		 1621 (ss_plus "s") (us_plus "u")
1622 (ss_minus "s") (us_minus "u")])
1623
1624;; Similar for the instruction mnemonics
1625(define_code_attr shift [(ashift "lsl") (ashiftrt "asr")
1626 (lshiftrt "lsr") (rotatert "ror")])
1627
462e6f9a
ST		 1628;; Op prefix for shift right and accumulate.
1629(define_code_attr sra_op [(ashiftrt "s") (lshiftrt "u")])
1630
43e9d192
IB		 1631;; Map shift operators onto underlying bit-field instructions
1632(define_code_attr bfshift [(ashift "ubfiz") (ashiftrt "sbfx")
1633 (lshiftrt "ubfx") (rotatert "extr")])
1634
1635;; Logical operator instruction mnemonics
1636(define_code_attr logical [(and "and") (ior "orr") (xor "eor")])
1637
3204ac98
KT		 1638;; Operation names for negate and bitwise complement.
1639(define_code_attr neg_not_op [(neg "neg") (not "not")])
1640
43cacb12 1641;; Similar, but when the second operand is inverted.
43e9d192
IB		 1642(define_code_attr nlogical [(and "bic") (ior "orn") (xor "eon")])
1643
43cacb12
RS		 1644;; Similar, but when both operands are inverted.
1645(define_code_attr logical_nn [(and "nor") (ior "nand")])
1646
43e9d192
IB		 1647;; Sign- or zero-extending data-op
1648(define_code_attr su [(sign_extend "s") (zero_extend "u")
1649 (sign_extract "s") (zero_extract "u")
1650 (fix "s") (unsigned_fix "u")
998eaf97
JG		 1651 (div "s") (udiv "u")
1652 (smax "s") (umax "u")
1653 (smin "s") (umin "u")])
43e9d192 1654
624d0f07
RS		 1655;; "s" for signed ops, empty for unsigned ones.
1656(define_code_attr s [(sign_extend "s") (zero_extend "")])
1657
1658;; Map signed/unsigned ops to the corresponding extension.
1659(define_code_attr paired_extend [(ss_plus "sign_extend")
1660 (us_plus "zero_extend")
1661 (ss_minus "sign_extend")
1662 (us_minus "zero_extend")])
1663
43cacb12
RS		 1664;; Whether a shift is left or right.
1665(define_code_attr lr [(ashift "l") (ashiftrt "r") (lshiftrt "r")])
1666
096e8448
JW		 1667;; Emit conditional branch instructions.
1668(define_code_attr bcond [(eq "beq") (ne "bne") (lt "bne") (ge "beq")])
1669
43e9d192
IB		 1670;; Emit cbz/cbnz depending on comparison type.
1671(define_code_attr cbz [(eq "cbz") (ne "cbnz") (lt "cbnz") (ge "cbz")])
1672
973d2e01
TP		 1673;; Emit inverted cbz/cbnz depending on comparison type.
1674(define_code_attr inv_cb [(eq "cbnz") (ne "cbz") (lt "cbz") (ge "cbnz")])
1675
43e9d192
IB		 1676;; Emit tbz/tbnz depending on comparison type.
1677(define_code_attr tbz [(eq "tbz") (ne "tbnz") (lt "tbnz") (ge "tbz")])
1678
973d2e01
TP		 1679;; Emit inverted tbz/tbnz depending on comparison type.
1680(define_code_attr inv_tb [(eq "tbnz") (ne "tbz") (lt "tbz") (ge "tbnz")])
1681
43e9d192 1682;; Max/min attributes.
998eaf97
JG		 1683(define_code_attr maxmin [(smax "max")
1684 (smin "min")
1685 (umax "max")
1686 (umin "min")])
43e9d192
IB		 1687
1688;; MLA/MLS attributes.
1689(define_code_attr as [(ss_plus "a") (ss_minus "s")])
1690
0462169c
SN		 1691;; Atomic operations
1692(define_code_attr atomic_optab
1693 [(ior "or") (xor "xor") (and "and") (plus "add") (minus "sub")])
1694
1695(define_code_attr atomic_op_operand
1696 [(ior "aarch64_logical_operand")
1697 (xor "aarch64_logical_operand")
1698 (and "aarch64_logical_operand")
1699 (plus "aarch64_plus_operand")
1700 (minus "aarch64_plus_operand")])
43e9d192 1701
356c32e2
MW		 1702;; Constants acceptable for atomic operations.
1703;; This definition must appear in this file before the iterators it refers to.
1704(define_code_attr const_atomic
1705 [(plus "IJ") (minus "IJ")
1706 (xor "<lconst_atomic>") (ior "<lconst_atomic>")
1707 (and "<lconst_atomic>")])
1708
1709;; Attribute to describe constants acceptable in atomic logical operations
1710(define_mode_attr lconst_atomic [(QI "K") (HI "K") (SI "K") (DI "L")])
1711
43cacb12
RS		 1712;; The integer SVE instruction that implements an rtx code.
1713(define_code_attr sve_int_op [(plus "add")
9d4ac06e 1714 (minus "sub")
6c4fd4a9 1715 (mult "mul")
c38f7319
RS		 1716 (div "sdiv")
1717 (udiv "udiv")
69c5fdcf 1718 (abs "abs")
43cacb12
RS		 1719 (neg "neg")
1720 (smin "smin")
1721 (smax "smax")
1722 (umin "umin")
1723 (umax "umax")
20103c0e
RS		 1724 (ashift "lsl")
1725 (ashiftrt "asr")
1726 (lshiftrt "lsr")
43cacb12
RS		 1727 (and "and")
1728 (ior "orr")
1729 (xor "eor")
1730 (not "not")
bca5a997
RS		 1731 (clrsb "cls")
1732 (clz "clz")
43cacb12
RS		 1733 (popcount "cnt")])
1734
a08acce8 1735(define_code_attr sve_int_op_rev [(plus "add")
20103c0e
RS		 1736 (minus "subr")
1737 (mult "mul")
1738 (div "sdivr")
1739 (udiv "udivr")
1740 (smin "smin")
1741 (smax "smax")
1742 (umin "umin")
1743 (umax "umax")
1744 (ashift "lslr")
1745 (ashiftrt "asrr")
1746 (lshiftrt "lsrr")
1747 (and "and")
1748 (ior "orr")
1749 (xor "eor")])
a08acce8 1750
43cacb12
RS		 1751;; The floating-point SVE instruction that implements an rtx code.
1752(define_code_attr sve_fp_op [(plus "fadd")
740c1ed7 1753 (minus "fsub")
d45b20a5 1754 (mult "fmul")])
43cacb12 1755
f22d7973 1756;; The SVE immediate constraint to use for an rtl code.
f8c22a8b
RS		 1757(define_code_attr sve_imm_con [(mult "vsm")
1758 (smax "vsm")
1759 (smin "vsm")
1760 (umax "vsb")
1761 (umin "vsb")
1762 (eq "vsc")
f22d7973
RS		 1763 (ne "vsc")
1764 (lt "vsc")
1765 (ge "vsc")
1766 (le "vsc")
1767 (gt "vsc")
1768 (ltu "vsd")
1769 (leu "vsd")
1770 (geu "vsd")
1771 (gtu "vsd")])
1772
f8c22a8b
RS		 1773;; The prefix letter to use when printing an immediate operand.
1774(define_code_attr sve_imm_prefix [(mult "")
1775 (smax "")
1776 (smin "")
1777 (umax "D")
1778 (umin "D")])
1779
d113ece6
RS		 1780;; The predicate to use for the second input operand in a cond_<optab><mode>
1781;; pattern.
1782(define_code_attr sve_pred_int_rhs2_operand
1783 [(plus "register_operand")
1784 (minus "register_operand")
1785 (mult "register_operand")
1786 (smax "register_operand")
1787 (umax "register_operand")
1788 (smin "register_operand")
1789 (umin "register_operand")
20103c0e
RS		 1790 (ashift "aarch64_sve_lshift_operand")
1791 (ashiftrt "aarch64_sve_rshift_operand")
1792 (lshiftrt "aarch64_sve_rshift_operand")
d113ece6
RS		 1793 (and "aarch64_sve_pred_and_operand")
1794 (ior "register_operand")
1795 (xor "register_operand")])
1796
624d0f07
RS		 1797(define_code_attr inc_dec [(minus "dec") (ss_minus "sqdec") (us_minus "uqdec")
1798 (plus "inc") (ss_plus "sqinc") (us_plus "uqinc")])
1799
43e9d192
IB		 1800;; -------------------------------------------------------------------
1801;; Int Iterators.
1802;; -------------------------------------------------------------------
75add2d0
KT		 1803
1804;; The unspec codes for the SABAL, UABAL AdvancedSIMD instructions.
1805(define_int_iterator ABAL [UNSPEC_SABAL UNSPEC_UABAL])
1806
1807;; The unspec codes for the SABDL2, UABDL2 AdvancedSIMD instructions.
1808(define_int_iterator ABDL2 [UNSPEC_SABDL2 UNSPEC_UABDL2])
1809
1810;; The unspec codes for the SADALP, UADALP AdvancedSIMD instructions.
1811(define_int_iterator ADALP [UNSPEC_SADALP UNSPEC_UADALP])
1812
43e9d192
IB		 1813(define_int_iterator MAXMINV [UNSPEC_UMAXV UNSPEC_UMINV
1814 UNSPEC_SMAXV UNSPEC_SMINV])
1815
998eaf97
JG		 1816(define_int_iterator FMAXMINV [UNSPEC_FMAXV UNSPEC_FMINV
1817 UNSPEC_FMAXNMV UNSPEC_FMINNMV])
43e9d192 1818
624d0f07
RS		 1819(define_int_iterator SVE_INT_ADDV [UNSPEC_SADDV UNSPEC_UADDV])
1820
43cacb12
RS		 1821(define_int_iterator LOGICALF [UNSPEC_ANDF UNSPEC_IORF UNSPEC_XORF])
1822
43e9d192
IB		 1823(define_int_iterator HADDSUB [UNSPEC_SHADD UNSPEC_UHADD
1824 UNSPEC_SRHADD UNSPEC_URHADD
1825 UNSPEC_SHSUB UNSPEC_UHSUB
1826 UNSPEC_SRHSUB UNSPEC_URHSUB])
1827
42addb5a
RS		 1828(define_int_iterator HADD [UNSPEC_SHADD UNSPEC_UHADD])
1829
1830(define_int_iterator RHADD [UNSPEC_SRHADD UNSPEC_URHADD])
1831
58cc9876
YW		 1832(define_int_iterator MULLBT [UNSPEC_SMULLB UNSPEC_UMULLB
1833 UNSPEC_SMULLT UNSPEC_UMULLT])
1834
1835(define_int_iterator SHRNB [UNSPEC_SHRNB UNSPEC_RSHRNB])
1836
1837(define_int_iterator SHRNT [UNSPEC_SHRNT UNSPEC_RSHRNT])
1838
2d57b12e
YW		 1839(define_int_iterator BSL_DUP [1 2])
1840
7a08d813 1841(define_int_iterator DOTPROD [UNSPEC_SDOT UNSPEC_UDOT])
43e9d192
IB		 1842
1843(define_int_iterator ADDSUBHN [UNSPEC_ADDHN UNSPEC_RADDHN
1844 UNSPEC_SUBHN UNSPEC_RSUBHN])
1845
1846(define_int_iterator ADDSUBHN2 [UNSPEC_ADDHN2 UNSPEC_RADDHN2
1847 UNSPEC_SUBHN2 UNSPEC_RSUBHN2])
1848
1efafef3
TC		 1849(define_int_iterator FMAXMIN_UNS [UNSPEC_FMAX UNSPEC_FMIN
1850 UNSPEC_FMAXNM UNSPEC_FMINNM])
202d0c11 1851
8fc16d72
ST		 1852(define_int_iterator PAUTH_LR_SP [UNSPEC_PACIASP UNSPEC_AUTIASP
1853 UNSPEC_PACIBSP UNSPEC_AUTIBSP])
db58fd89 1854
8fc16d72
ST		 1855(define_int_iterator PAUTH_17_16 [UNSPEC_PACIA1716 UNSPEC_AUTIA1716
1856 UNSPEC_PACIB1716 UNSPEC_AUTIB1716])
db58fd89 1857
43e9d192
IB		 1858(define_int_iterator VQDMULH [UNSPEC_SQDMULH UNSPEC_SQRDMULH])
1859
58cc9876
YW		 1860(define_int_iterator MULHRS [UNSPEC_SMULHS UNSPEC_UMULHS
1861 UNSPEC_SMULHRS UNSPEC_UMULHRS])
1862
43e9d192
IB		 1863(define_int_iterator USSUQADD [UNSPEC_SUQADD UNSPEC_USQADD])
1864
1865(define_int_iterator SUQMOVN [UNSPEC_SQXTN UNSPEC_UQXTN])
1866
1867(define_int_iterator VSHL [UNSPEC_SSHL UNSPEC_USHL
1868 UNSPEC_SRSHL UNSPEC_URSHL])
1869
1870(define_int_iterator VSHLL [UNSPEC_SSHLL UNSPEC_USHLL])
1871
1872(define_int_iterator VQSHL [UNSPEC_SQSHL UNSPEC_UQSHL
1873 UNSPEC_SQRSHL UNSPEC_UQRSHL])
1874
1875(define_int_iterator VSRA [UNSPEC_SSRA UNSPEC_USRA
1876 UNSPEC_SRSRA UNSPEC_URSRA])
1877
1878(define_int_iterator VSLRI [UNSPEC_SSLI UNSPEC_USLI
1879 UNSPEC_SSRI UNSPEC_USRI])
1880
1881
1882(define_int_iterator VRSHR_N [UNSPEC_SRSHR UNSPEC_URSHR])
1883
1884(define_int_iterator VQSHL_N [UNSPEC_SQSHLU UNSPEC_SQSHL UNSPEC_UQSHL])
1885
1886(define_int_iterator VQSHRN_N [UNSPEC_SQSHRUN UNSPEC_SQRSHRUN
1887 UNSPEC_SQSHRN UNSPEC_UQSHRN
1888 UNSPEC_SQRSHRN UNSPEC_UQRSHRN])
1889
57b26d65
MW		 1890(define_int_iterator SQRDMLH_AS [UNSPEC_SQRDMLAH UNSPEC_SQRDMLSH])
1891
cc4d934f
JG		 1892(define_int_iterator PERMUTE [UNSPEC_ZIP1 UNSPEC_ZIP2
1893 UNSPEC_TRN1 UNSPEC_TRN2
1894 UNSPEC_UZP1 UNSPEC_UZP2])
43e9d192 1895
43cacb12
RS		 1896(define_int_iterator OPTAB_PERMUTE [UNSPEC_ZIP1 UNSPEC_ZIP2
1897 UNSPEC_UZP1 UNSPEC_UZP2])
1898
923fcec3
AL		 1899(define_int_iterator REVERSE [UNSPEC_REV64 UNSPEC_REV32 UNSPEC_REV16])
1900
42fc9a7f 1901(define_int_iterator FRINT [UNSPEC_FRINTZ UNSPEC_FRINTP UNSPEC_FRINTM
0659ce6f
JG		 1902 UNSPEC_FRINTN UNSPEC_FRINTI UNSPEC_FRINTX
1903 UNSPEC_FRINTA])
42fc9a7f
JG		 1904
1905(define_int_iterator FCVT [UNSPEC_FRINTZ UNSPEC_FRINTP UNSPEC_FRINTM
ce966824 1906 UNSPEC_FRINTA UNSPEC_FRINTN])
42fc9a7f 1907
3f598afe
JW		 1908(define_int_iterator FCVT_F2FIXED [UNSPEC_FCVTZS UNSPEC_FCVTZU])
1909(define_int_iterator FCVT_FIXED2F [UNSPEC_SCVTF UNSPEC_UCVTF])
1910
5d357f26
KT		 1911(define_int_iterator CRC [UNSPEC_CRC32B UNSPEC_CRC32H UNSPEC_CRC32W
1912 UNSPEC_CRC32X UNSPEC_CRC32CB UNSPEC_CRC32CH
1913 UNSPEC_CRC32CW UNSPEC_CRC32CX])
1914
5a7a4e80
TB		 1915(define_int_iterator CRYPTO_AES [UNSPEC_AESE UNSPEC_AESD])
1916(define_int_iterator CRYPTO_AESMC [UNSPEC_AESMC UNSPEC_AESIMC])
1917
30442682
TB		 1918(define_int_iterator CRYPTO_SHA1 [UNSPEC_SHA1C UNSPEC_SHA1M UNSPEC_SHA1P])
1919
b9cb0a44
TB		 1920(define_int_iterator CRYPTO_SHA256 [UNSPEC_SHA256H UNSPEC_SHA256H2])
1921
27086ea3
MC		 1922(define_int_iterator CRYPTO_SHA512 [UNSPEC_SHA512H UNSPEC_SHA512H2])
1923
1924(define_int_iterator CRYPTO_SM3TT [UNSPEC_SM3TT1A UNSPEC_SM3TT1B
1925 UNSPEC_SM3TT2A UNSPEC_SM3TT2B])
1926
1927(define_int_iterator CRYPTO_SM3PART [UNSPEC_SM3PARTW1 UNSPEC_SM3PARTW2])
1928
1929;; Iterators for fp16 operations
1930
1931(define_int_iterator VFMLA16_LOW [UNSPEC_FMLAL UNSPEC_FMLSL])
1932
1933(define_int_iterator VFMLA16_HIGH [UNSPEC_FMLAL2 UNSPEC_FMLSL2])
1934
43cacb12
RS		 1935(define_int_iterator UNPACK [UNSPEC_UNPACKSHI UNSPEC_UNPACKUHI
1936 UNSPEC_UNPACKSLO UNSPEC_UNPACKULO])
1937
1938(define_int_iterator UNPACK_UNSIGNED [UNSPEC_UNPACKULO UNSPEC_UNPACKUHI])
1939
11e9443f
RS		 1940(define_int_iterator MUL_HIGHPART [UNSPEC_SMUL_HIGHPART UNSPEC_UMUL_HIGHPART])
1941
624d0f07
RS		 1942(define_int_iterator CLAST [UNSPEC_CLASTA UNSPEC_CLASTB])
1943
1944(define_int_iterator LAST [UNSPEC_LASTA UNSPEC_LASTB])
1945
1946(define_int_iterator SVE_INT_UNARY [UNSPEC_RBIT UNSPEC_REVB
1947 UNSPEC_REVH UNSPEC_REVW])
1948
1949(define_int_iterator SVE_FP_UNARY [UNSPEC_FRECPE UNSPEC_RSQRTE])
1950
1951(define_int_iterator SVE_FP_UNARY_INT [UNSPEC_FEXPA])
1952
1953(define_int_iterator SVE_FP_BINARY [UNSPEC_FRECPS UNSPEC_RSQRTS])
1954
1955(define_int_iterator SVE_FP_BINARY_INT [UNSPEC_FTSMUL UNSPEC_FTSSEL])
d7a09c44 1956
b0760a40
RS		 1957(define_int_iterator SVE_INT_REDUCTION [UNSPEC_ANDV
1958 UNSPEC_IORV
1959 UNSPEC_SMAXV
1960 UNSPEC_SMINV
1961 UNSPEC_UMAXV
1962 UNSPEC_UMINV
1963 UNSPEC_XORV])
1964
1965(define_int_iterator SVE_FP_REDUCTION [UNSPEC_FADDV
1966 UNSPEC_FMAXV
1967 UNSPEC_FMAXNMV
1968 UNSPEC_FMINV
1969 UNSPEC_FMINNMV])
1970
d45b20a5
RS		 1971(define_int_iterator SVE_COND_FP_UNARY [UNSPEC_COND_FABS
1972 UNSPEC_COND_FNEG
624d0f07 1973 UNSPEC_COND_FRECPX
d45b20a5
RS		 1974 UNSPEC_COND_FRINTA
1975 UNSPEC_COND_FRINTI
1976 UNSPEC_COND_FRINTM
1977 UNSPEC_COND_FRINTN
1978 UNSPEC_COND_FRINTP
1979 UNSPEC_COND_FRINTX
1980 UNSPEC_COND_FRINTZ
1981 UNSPEC_COND_FSQRT])
1982
95eb5537 1983(define_int_iterator SVE_COND_FCVT [UNSPEC_COND_FCVT])
99361551
RS		 1984(define_int_iterator SVE_COND_FCVTI [UNSPEC_COND_FCVTZS UNSPEC_COND_FCVTZU])
1985(define_int_iterator SVE_COND_ICVTF [UNSPEC_COND_SCVTF UNSPEC_COND_UCVTF])
1986
cb18e86d
RS		 1987(define_int_iterator SVE_COND_FP_BINARY [UNSPEC_COND_FADD
1988 UNSPEC_COND_FDIV
624d0f07 1989 UNSPEC_COND_FMAX
cb18e86d 1990 UNSPEC_COND_FMAXNM
624d0f07 1991 UNSPEC_COND_FMIN
cb18e86d
RS		 1992 UNSPEC_COND_FMINNM
1993 UNSPEC_COND_FMUL
624d0f07 1994 UNSPEC_COND_FMULX
cb18e86d 1995 UNSPEC_COND_FSUB])
0d2b3bca 1996
624d0f07
RS		 1997(define_int_iterator SVE_COND_FP_BINARY_INT [UNSPEC_COND_FSCALE])
1998
1999(define_int_iterator SVE_COND_FP_ADD [UNSPEC_COND_FADD])
2000(define_int_iterator SVE_COND_FP_SUB [UNSPEC_COND_FSUB])
2001(define_int_iterator SVE_COND_FP_MUL [UNSPEC_COND_FMUL])
2002
2003(define_int_iterator SVE_COND_FP_BINARY_I1 [UNSPEC_COND_FMAX
2004 UNSPEC_COND_FMAXNM
2005 UNSPEC_COND_FMIN
a19ba9e1
RS		 2006 UNSPEC_COND_FMINNM
2007 UNSPEC_COND_FMUL])
2008
624d0f07
RS		 2009(define_int_iterator SVE_COND_FP_BINARY_REG [UNSPEC_COND_FDIV
2010 UNSPEC_COND_FMULX])
2011
2012(define_int_iterator SVE_COND_FCADD [UNSPEC_COND_FCADD90
2013 UNSPEC_COND_FCADD270])
2014
2015(define_int_iterator SVE_COND_FP_MAXMIN [UNSPEC_COND_FMAX
2016 UNSPEC_COND_FMAXNM
2017 UNSPEC_COND_FMIN
2018 UNSPEC_COND_FMINNM])
0254ed79 2019
214c42fa
RS		 2020;; Floating-point max/min operations that correspond to optabs,
2021;; as opposed to those that are internal to the port.
2022(define_int_iterator SVE_COND_FP_MAXMIN_PUBLIC [UNSPEC_COND_FMAXNM
2023 UNSPEC_COND_FMINNM])
2024
b41d1f6e
RS		 2025(define_int_iterator SVE_COND_FP_TERNARY [UNSPEC_COND_FMLA
2026 UNSPEC_COND_FMLS
2027 UNSPEC_COND_FNMLA
2028 UNSPEC_COND_FNMLS])
2029
624d0f07
RS		 2030(define_int_iterator SVE_COND_FCMLA [UNSPEC_COND_FCMLA
2031 UNSPEC_COND_FCMLA90
2032 UNSPEC_COND_FCMLA180
2033 UNSPEC_COND_FCMLA270])
2034
2035(define_int_iterator SVE_COND_INT_CMP_WIDE [UNSPEC_COND_CMPEQ_WIDE
2036 UNSPEC_COND_CMPGE_WIDE
2037 UNSPEC_COND_CMPGT_WIDE
2038 UNSPEC_COND_CMPHI_WIDE
2039 UNSPEC_COND_CMPHS_WIDE
2040 UNSPEC_COND_CMPLE_WIDE
2041 UNSPEC_COND_CMPLO_WIDE
2042 UNSPEC_COND_CMPLS_WIDE
2043 UNSPEC_COND_CMPLT_WIDE
2044 UNSPEC_COND_CMPNE_WIDE])
2045
4a942af6
RS		 2046;; SVE FP comparisons that accept #0.0.
2047(define_int_iterator SVE_COND_FP_CMP_I0 [UNSPEC_COND_FCMEQ
2048 UNSPEC_COND_FCMGE
2049 UNSPEC_COND_FCMGT
2050 UNSPEC_COND_FCMLE
2051 UNSPEC_COND_FCMLT
2052 UNSPEC_COND_FCMNE])
43cacb12 2053
42b4e87d
RS		 2054(define_int_iterator SVE_COND_FP_ABS_CMP [UNSPEC_COND_FCMGE
2055 UNSPEC_COND_FCMGT
2056 UNSPEC_COND_FCMLE
2057 UNSPEC_COND_FCMLT])
2058
624d0f07
RS		 2059(define_int_iterator SVE_FP_TERNARY_LANE [UNSPEC_FMLA UNSPEC_FMLS])
2060
2061(define_int_iterator SVE_CFP_TERNARY_LANE [UNSPEC_FCMLA UNSPEC_FCMLA90
2062 UNSPEC_FCMLA180 UNSPEC_FCMLA270])
2063
2064(define_int_iterator SVE_WHILE [UNSPEC_WHILE_LE UNSPEC_WHILE_LO
2065 UNSPEC_WHILE_LS UNSPEC_WHILE_LT])
2066
2067(define_int_iterator SVE_SHIFT_WIDE [UNSPEC_ASHIFT_WIDE
2068 UNSPEC_ASHIFTRT_WIDE
2069 UNSPEC_LSHIFTRT_WIDE])
2070
2071(define_int_iterator SVE_LDFF1_LDNF1 [UNSPEC_LDFF1 UNSPEC_LDNF1])
2072
9d63f43b
TC		 2073(define_int_iterator FCADD [UNSPEC_FCADD90
2074 UNSPEC_FCADD270])
2075
2076(define_int_iterator FCMLA [UNSPEC_FCMLA
2077 UNSPEC_FCMLA90
2078 UNSPEC_FCMLA180
2079 UNSPEC_FCMLA270])
2080
10bd1d96
KT		 2081(define_int_iterator FRINTNZX [UNSPEC_FRINT32Z UNSPEC_FRINT32X
2082 UNSPEC_FRINT64Z UNSPEC_FRINT64X])
2083
624d0f07
RS		 2084(define_int_iterator SVE_BRK_UNARY [UNSPEC_BRKA UNSPEC_BRKB])
2085
2086(define_int_iterator SVE_BRK_BINARY [UNSPEC_BRKN UNSPEC_BRKPA UNSPEC_BRKPB])
2087
2088(define_int_iterator SVE_PITER [UNSPEC_PFIRST UNSPEC_PNEXT])
2089
d81cb613
MW		 2090;; Iterators for atomic operations.
2091
2092(define_int_iterator ATOMIC_LDOP
2093 [UNSPECV_ATOMIC_LDOP_OR UNSPECV_ATOMIC_LDOP_BIC
2094 UNSPECV_ATOMIC_LDOP_XOR UNSPECV_ATOMIC_LDOP_PLUS])
2095
2096(define_int_attr atomic_ldop
2097 [(UNSPECV_ATOMIC_LDOP_OR "set") (UNSPECV_ATOMIC_LDOP_BIC "clr")
2098 (UNSPECV_ATOMIC_LDOP_XOR "eor") (UNSPECV_ATOMIC_LDOP_PLUS "add")])
2099
7803ec5e
RH		 2100(define_int_attr atomic_ldoptab
2101 [(UNSPECV_ATOMIC_LDOP_OR "ior") (UNSPECV_ATOMIC_LDOP_BIC "bic")
2102 (UNSPECV_ATOMIC_LDOP_XOR "xor") (UNSPECV_ATOMIC_LDOP_PLUS "add")])
2103
43e9d192
IB		 2104;; -------------------------------------------------------------------
2105;; Int Iterators Attributes.
2106;; -------------------------------------------------------------------
43cacb12
RS		 2107
2108;; The optab associated with an operation. Note that for ANDF, IORF
2109;; and XORF, the optab pattern is not actually defined; we just use this
2110;; name for consistency with the integer patterns.
2111(define_int_attr optab [(UNSPEC_ANDF "and")
2112 (UNSPEC_IORF "ior")
898f07b0 2113 (UNSPEC_XORF "xor")
624d0f07
RS		 2114 (UNSPEC_SADDV "sadd")
2115 (UNSPEC_UADDV "uadd")
898f07b0
RS		 2116 (UNSPEC_ANDV "and")
2117 (UNSPEC_IORV "ior")
0972596e 2118 (UNSPEC_XORV "xor")
624d0f07
RS		 2119 (UNSPEC_FRECPE "frecpe")
2120 (UNSPEC_FRECPS "frecps")
2121 (UNSPEC_RSQRTE "frsqrte")
2122 (UNSPEC_RSQRTS "frsqrts")
2123 (UNSPEC_RBIT "rbit")
d7a09c44
RS		 2124 (UNSPEC_REVB "revb")
2125 (UNSPEC_REVH "revh")
2126 (UNSPEC_REVW "revw")
b0760a40
RS		 2127 (UNSPEC_UMAXV "umax")
2128 (UNSPEC_UMINV "umin")
2129 (UNSPEC_SMAXV "smax")
2130 (UNSPEC_SMINV "smin")
2131 (UNSPEC_FADDV "plus")
2132 (UNSPEC_FMAXNMV "smax")
2133 (UNSPEC_FMAXV "smax_nan")
2134 (UNSPEC_FMINNMV "smin")
2135 (UNSPEC_FMINV "smin_nan")
624d0f07
RS		 2136 (UNSPEC_SMUL_HIGHPART "smulh")
2137 (UNSPEC_UMUL_HIGHPART "umulh")
2138 (UNSPEC_FMLA "fma")
2139 (UNSPEC_FMLS "fnma")
2140 (UNSPEC_FCMLA "fcmla")
2141 (UNSPEC_FCMLA90 "fcmla90")
2142 (UNSPEC_FCMLA180 "fcmla180")
2143 (UNSPEC_FCMLA270 "fcmla270")
2144 (UNSPEC_FEXPA "fexpa")
2145 (UNSPEC_FTSMUL "ftsmul")
2146 (UNSPEC_FTSSEL "ftssel")
d45b20a5 2147 (UNSPEC_COND_FABS "abs")
cb18e86d 2148 (UNSPEC_COND_FADD "add")
624d0f07
RS		 2149 (UNSPEC_COND_FCADD90 "cadd90")
2150 (UNSPEC_COND_FCADD270 "cadd270")
2151 (UNSPEC_COND_FCMLA "fcmla")
2152 (UNSPEC_COND_FCMLA90 "fcmla90")
2153 (UNSPEC_COND_FCMLA180 "fcmla180")
2154 (UNSPEC_COND_FCMLA270 "fcmla270")
99361551
RS		 2155 (UNSPEC_COND_FCVT "fcvt")
2156 (UNSPEC_COND_FCVTZS "fix_trunc")
2157 (UNSPEC_COND_FCVTZU "fixuns_trunc")
cb18e86d 2158 (UNSPEC_COND_FDIV "div")
624d0f07 2159 (UNSPEC_COND_FMAX "smax_nan")
cb18e86d 2160 (UNSPEC_COND_FMAXNM "smax")
624d0f07 2161 (UNSPEC_COND_FMIN "smin_nan")
cb18e86d 2162 (UNSPEC_COND_FMINNM "smin")
b41d1f6e
RS		 2163 (UNSPEC_COND_FMLA "fma")
2164 (UNSPEC_COND_FMLS "fnma")
cb18e86d 2165 (UNSPEC_COND_FMUL "mul")
624d0f07 2166 (UNSPEC_COND_FMULX "mulx")
d45b20a5 2167 (UNSPEC_COND_FNEG "neg")
b41d1f6e 2168 (UNSPEC_COND_FNMLA "fnms")
cb18e86d 2169 (UNSPEC_COND_FNMLS "fms")
624d0f07 2170 (UNSPEC_COND_FRECPX "frecpx")
d45b20a5
RS		 2171 (UNSPEC_COND_FRINTA "round")
2172 (UNSPEC_COND_FRINTI "nearbyint")
2173 (UNSPEC_COND_FRINTM "floor")
2174 (UNSPEC_COND_FRINTN "frintn")
2175 (UNSPEC_COND_FRINTP "ceil")
2176 (UNSPEC_COND_FRINTX "rint")
2177 (UNSPEC_COND_FRINTZ "btrunc")
624d0f07 2178 (UNSPEC_COND_FSCALE "fscale")
d45b20a5 2179 (UNSPEC_COND_FSQRT "sqrt")
99361551
RS		 2180 (UNSPEC_COND_FSUB "sub")
2181 (UNSPEC_COND_SCVTF "float")
2182 (UNSPEC_COND_UCVTF "floatuns")])
43cacb12 2183
998eaf97
JG		 2184(define_int_attr maxmin_uns [(UNSPEC_UMAXV "umax")
2185 (UNSPEC_UMINV "umin")
2186 (UNSPEC_SMAXV "smax")
2187 (UNSPEC_SMINV "smin")
2188 (UNSPEC_FMAX "smax_nan")
2189 (UNSPEC_FMAXNMV "smax")
2190 (UNSPEC_FMAXV "smax_nan")
2191 (UNSPEC_FMIN "smin_nan")
2192 (UNSPEC_FMINNMV "smin")
1efafef3
TC		 2193 (UNSPEC_FMINV "smin_nan")
2194 (UNSPEC_FMAXNM "fmax")
214c42fa 2195 (UNSPEC_FMINNM "fmin")
624d0f07 2196 (UNSPEC_COND_FMAX "fmax_nan")
214c42fa 2197 (UNSPEC_COND_FMAXNM "fmax")
624d0f07 2198 (UNSPEC_COND_FMIN "fmin_nan")
214c42fa 2199 (UNSPEC_COND_FMINNM "fmin")])
998eaf97
JG		 2200
2201(define_int_attr maxmin_uns_op [(UNSPEC_UMAXV "umax")
2202 (UNSPEC_UMINV "umin")
2203 (UNSPEC_SMAXV "smax")
2204 (UNSPEC_SMINV "smin")
2205 (UNSPEC_FMAX "fmax")
2206 (UNSPEC_FMAXNMV "fmaxnm")
2207 (UNSPEC_FMAXV "fmax")
2208 (UNSPEC_FMIN "fmin")
2209 (UNSPEC_FMINNMV "fminnm")
1efafef3
TC		 2210 (UNSPEC_FMINV "fmin")
2211 (UNSPEC_FMAXNM "fmaxnm")
2212 (UNSPEC_FMINNM "fminnm")])
202d0c11 2213
624d0f07
RS		 2214(define_code_attr binqops_op [(ss_plus "sqadd")
2215 (us_plus "uqadd")
2216 (ss_minus "sqsub")
2217 (us_minus "uqsub")])
2218
2219(define_code_attr binqops_op_rev [(ss_plus "sqsub")
2220 (ss_minus "sqadd")])
2221
43cacb12
RS		 2222;; The SVE logical instruction that implements an unspec.
2223(define_int_attr logicalf_op [(UNSPEC_ANDF "and")
2224 (UNSPEC_IORF "orr")
2225 (UNSPEC_XORF "eor")])
2226
624d0f07
RS		 2227(define_int_attr last_op [(UNSPEC_CLASTA "after_last")
2228 (UNSPEC_CLASTB "last")
2229 (UNSPEC_LASTA "after_last")
2230 (UNSPEC_LASTB "last")])
2231
43cacb12 2232;; "s" for signed operations and "u" for unsigned ones.
624d0f07
RS		 2233(define_int_attr su [(UNSPEC_SADDV "s")
2234 (UNSPEC_UADDV "u")
2235 (UNSPEC_UNPACKSHI "s")
43cacb12
RS		 2236 (UNSPEC_UNPACKUHI "u")
2237 (UNSPEC_UNPACKSLO "s")
11e9443f
RS		 2238 (UNSPEC_UNPACKULO "u")
2239 (UNSPEC_SMUL_HIGHPART "s")
99361551
RS		 2240 (UNSPEC_UMUL_HIGHPART "u")
2241 (UNSPEC_COND_FCVTZS "s")
2242 (UNSPEC_COND_FCVTZU "u")
2243 (UNSPEC_COND_SCVTF "s")
58cc9876
YW		 2244 (UNSPEC_COND_UCVTF "u")
2245 (UNSPEC_SMULLB "s") (UNSPEC_UMULLB "u")
2246 (UNSPEC_SMULLT "s") (UNSPEC_UMULLT "u")
2247 (UNSPEC_SMULHS "s") (UNSPEC_UMULHS "u")
2248 (UNSPEC_SMULHRS "s") (UNSPEC_UMULHRS "u")])
43cacb12 2249
43e9d192
IB		 2250(define_int_attr sur [(UNSPEC_SHADD "s") (UNSPEC_UHADD "u")
2251 (UNSPEC_SRHADD "sr") (UNSPEC_URHADD "ur")
2252 (UNSPEC_SHSUB "s") (UNSPEC_UHSUB "u")
2253 (UNSPEC_SRHSUB "sr") (UNSPEC_URHSUB "ur")
2254 (UNSPEC_ADDHN "") (UNSPEC_RADDHN "r")
75add2d0
KT		 2255 (UNSPEC_SABAL "s") (UNSPEC_UABAL "u")
2256 (UNSPEC_SABDL2 "s") (UNSPEC_UABDL2 "u")
2257 (UNSPEC_SADALP "s") (UNSPEC_UADALP "u")
43e9d192
IB		 2258 (UNSPEC_SUBHN "") (UNSPEC_RSUBHN "r")
2259 (UNSPEC_ADDHN2 "") (UNSPEC_RADDHN2 "r")
2260 (UNSPEC_SUBHN2 "") (UNSPEC_RSUBHN2 "r")
2261 (UNSPEC_SQXTN "s") (UNSPEC_UQXTN "u")
2262 (UNSPEC_USQADD "us") (UNSPEC_SUQADD "su")
2263 (UNSPEC_SSLI "s") (UNSPEC_USLI "u")
2264 (UNSPEC_SSRI "s") (UNSPEC_USRI "u")
2265 (UNSPEC_USRA "u") (UNSPEC_SSRA "s")
2266 (UNSPEC_URSRA "ur") (UNSPEC_SRSRA "sr")
2267 (UNSPEC_URSHR "ur") (UNSPEC_SRSHR "sr")
2268 (UNSPEC_SQSHLU "s") (UNSPEC_SQSHL "s")
2269 (UNSPEC_UQSHL "u")
2270 (UNSPEC_SQSHRUN "s") (UNSPEC_SQRSHRUN "s")
2271 (UNSPEC_SQSHRN "s") (UNSPEC_UQSHRN "u")
2272 (UNSPEC_SQRSHRN "s") (UNSPEC_UQRSHRN "u")
2273 (UNSPEC_USHL "u") (UNSPEC_SSHL "s")
2274 (UNSPEC_USHLL "u") (UNSPEC_SSHLL "s")
2275 (UNSPEC_URSHL "ur") (UNSPEC_SRSHL "sr")
2276 (UNSPEC_UQRSHL "u") (UNSPEC_SQRSHL "s")
7a08d813 2277 (UNSPEC_SDOT "s") (UNSPEC_UDOT "u")
43e9d192
IB		 2278])
2279
2280(define_int_attr r [(UNSPEC_SQDMULH "") (UNSPEC_SQRDMULH "r")
2281 (UNSPEC_SQSHRUN "") (UNSPEC_SQRSHRUN "r")
2282 (UNSPEC_SQSHRN "") (UNSPEC_UQSHRN "")
2283 (UNSPEC_SQRSHRN "r") (UNSPEC_UQRSHRN "r")
2284 (UNSPEC_SQSHL "") (UNSPEC_UQSHL "")
2285 (UNSPEC_SQRSHL "r")(UNSPEC_UQRSHL "r")
58cc9876
YW		 2286 (UNSPEC_SHRNB "") (UNSPEC_SHRNT "")
2287 (UNSPEC_RSHRNB "r") (UNSPEC_RSHRNT "r")
2288 (UNSPEC_SMULHS "") (UNSPEC_UMULHS "")
2289 (UNSPEC_SMULHRS "r") (UNSPEC_UMULHRS "r")
43e9d192
IB		 2290])
2291
2292(define_int_attr lr [(UNSPEC_SSLI "l") (UNSPEC_USLI "l")
2293 (UNSPEC_SSRI "r") (UNSPEC_USRI "r")])
2294
2295(define_int_attr u [(UNSPEC_SQSHLU "u") (UNSPEC_SQSHL "") (UNSPEC_UQSHL "")
2296 (UNSPEC_SQSHRUN "u") (UNSPEC_SQRSHRUN "u")
42addb5a
RS		 2297 (UNSPEC_SQSHRN "") (UNSPEC_UQSHRN "")
2298 (UNSPEC_SQRSHRN "") (UNSPEC_UQRSHRN "")
2299 (UNSPEC_SHADD "") (UNSPEC_UHADD "u")
2300 (UNSPEC_SRHADD "") (UNSPEC_URHADD "u")])
43e9d192 2301
58cc9876
YW		 2302(define_int_attr bt [(UNSPEC_SMULLB "b") (UNSPEC_UMULLB "b")
2303 (UNSPEC_SMULLT "t") (UNSPEC_UMULLT "t")])
2304
624d0f07
RS		 2305(define_int_attr fn [(UNSPEC_LDFF1 "f") (UNSPEC_LDNF1 "n")])
2306
2307(define_int_attr ab [(UNSPEC_CLASTA "a") (UNSPEC_CLASTB "b")
2308 (UNSPEC_LASTA "a") (UNSPEC_LASTB "b")])
2309
43e9d192
IB		 2310(define_int_attr addsub [(UNSPEC_SHADD "add")
2311 (UNSPEC_UHADD "add")
2312 (UNSPEC_SRHADD "add")
2313 (UNSPEC_URHADD "add")
2314 (UNSPEC_SHSUB "sub")
2315 (UNSPEC_UHSUB "sub")
2316 (UNSPEC_SRHSUB "sub")
2317 (UNSPEC_URHSUB "sub")
2318 (UNSPEC_ADDHN "add")
2319 (UNSPEC_SUBHN "sub")
2320 (UNSPEC_RADDHN "add")
2321 (UNSPEC_RSUBHN "sub")
2322 (UNSPEC_ADDHN2 "add")
2323 (UNSPEC_SUBHN2 "sub")
2324 (UNSPEC_RADDHN2 "add")
2325 (UNSPEC_RSUBHN2 "sub")])
2326
2d57b12e
YW		 2327;; BSL variants: first commutative operand.
2328(define_int_attr bsl_1st [(1 "w") (2 "0")])
2329
2330;; BSL variants: second commutative operand.
2331(define_int_attr bsl_2nd [(1 "0") (2 "w")])
2332
2333;; BSL variants: duplicated input operand.
2334(define_int_attr bsl_dup [(1 "1") (2 "2")])
2335
2336;; BSL variants: operand which requires preserving via movprfx.
2337(define_int_attr bsl_mov [(1 "2") (2 "1")])
2338
cb23a30c
JG		 2339(define_int_attr offsetlr [(UNSPEC_SSLI "") (UNSPEC_USLI "")
2340 (UNSPEC_SSRI "offset_")
2341 (UNSPEC_USRI "offset_")])
43e9d192 2342
42fc9a7f
JG		 2343;; Standard pattern names for floating-point rounding instructions.
2344(define_int_attr frint_pattern [(UNSPEC_FRINTZ "btrunc")
2345 (UNSPEC_FRINTP "ceil")
2346 (UNSPEC_FRINTM "floor")
2347 (UNSPEC_FRINTI "nearbyint")
2348 (UNSPEC_FRINTX "rint")
0659ce6f
JG		 2349 (UNSPEC_FRINTA "round")
2350 (UNSPEC_FRINTN "frintn")])
42fc9a7f
JG		 2351
2352;; frint suffix for floating-point rounding instructions.
2353(define_int_attr frint_suffix [(UNSPEC_FRINTZ "z") (UNSPEC_FRINTP "p")
2354 (UNSPEC_FRINTM "m") (UNSPEC_FRINTI "i")
0659ce6f
JG		 2355 (UNSPEC_FRINTX "x") (UNSPEC_FRINTA "a")
2356 (UNSPEC_FRINTN "n")])
42fc9a7f
JG		 2357
2358(define_int_attr fcvt_pattern [(UNSPEC_FRINTZ "btrunc") (UNSPEC_FRINTA "round")
ce966824
JG		 2359 (UNSPEC_FRINTP "ceil") (UNSPEC_FRINTM "floor")
2360 (UNSPEC_FRINTN "frintn")])
42fc9a7f 2361
3f598afe
JW		 2362(define_int_attr fcvt_fixed_insn [(UNSPEC_SCVTF "scvtf")
2363 (UNSPEC_UCVTF "ucvtf")
2364 (UNSPEC_FCVTZS "fcvtzs")
2365 (UNSPEC_FCVTZU "fcvtzu")])
2366
db58fd89 2367;; Pointer authentication mnemonic prefix.
8fc16d72
ST		 2368(define_int_attr pauth_mnem_prefix [(UNSPEC_PACIASP "pacia")
2369 (UNSPEC_PACIBSP "pacib")
2370 (UNSPEC_PACIA1716 "pacia")
2371 (UNSPEC_PACIB1716 "pacib")
2372 (UNSPEC_AUTIASP "autia")
2373 (UNSPEC_AUTIBSP "autib")
2374 (UNSPEC_AUTIA1716 "autia")
2375 (UNSPEC_AUTIB1716 "autib")])
2376
2377(define_int_attr pauth_key [(UNSPEC_PACIASP "AARCH64_KEY_A")
2378 (UNSPEC_PACIBSP "AARCH64_KEY_B")
2379 (UNSPEC_PACIA1716 "AARCH64_KEY_A")
2380 (UNSPEC_PACIB1716 "AARCH64_KEY_B")
2381 (UNSPEC_AUTIASP "AARCH64_KEY_A")
2382 (UNSPEC_AUTIBSP "AARCH64_KEY_B")
2383 (UNSPEC_AUTIA1716 "AARCH64_KEY_A")
2384 (UNSPEC_AUTIB1716 "AARCH64_KEY_B")])
2385
2386;; Pointer authentication HINT number for NOP space instructions using A and
2387;; B key.
2388(define_int_attr pauth_hint_num [(UNSPEC_PACIASP "25")
2389 (UNSPEC_PACIBSP "27")
2390 (UNSPEC_AUTIASP "29")
2391 (UNSPEC_AUTIBSP "31")
2392 (UNSPEC_PACIA1716 "8")
2393 (UNSPEC_PACIB1716 "10")
2394 (UNSPEC_AUTIA1716 "12")
2395 (UNSPEC_AUTIB1716 "14")])
db58fd89 2396
3e2751ce
RS		 2397(define_int_attr perm_insn [(UNSPEC_ZIP1 "zip1") (UNSPEC_ZIP2 "zip2")
2398 (UNSPEC_TRN1 "trn1") (UNSPEC_TRN2 "trn2")
2399 (UNSPEC_UZP1 "uzp1") (UNSPEC_UZP2 "uzp2")])
cc4d934f 2400
923fcec3
AL		 2401; op code for REV instructions (size within which elements are reversed).
2402(define_int_attr rev_op [(UNSPEC_REV64 "64") (UNSPEC_REV32 "32")
2403 (UNSPEC_REV16 "16")])
2404
3e2751ce 2405(define_int_attr perm_hilo [(UNSPEC_UNPACKSHI "hi") (UNSPEC_UNPACKUHI "hi")
43cacb12 2406 (UNSPEC_UNPACKSLO "lo") (UNSPEC_UNPACKULO "lo")])
0050faf8 2407
9bfb28ed
RS		 2408;; Return true if the associated optab refers to the high-numbered lanes,
2409;; false if it refers to the low-numbered lanes. The convention is for
2410;; "hi" to refer to the low-numbered lanes (the first ones in memory)
2411;; for big-endian.
2412(define_int_attr hi_lanes_optab [(UNSPEC_UNPACKSHI "!BYTES_BIG_ENDIAN")
2413 (UNSPEC_UNPACKUHI "!BYTES_BIG_ENDIAN")
2414 (UNSPEC_UNPACKSLO "BYTES_BIG_ENDIAN")
2415 (UNSPEC_UNPACKULO "BYTES_BIG_ENDIAN")])
2416
5d357f26
KT		 2417(define_int_attr crc_variant [(UNSPEC_CRC32B "crc32b") (UNSPEC_CRC32H "crc32h")
2418 (UNSPEC_CRC32W "crc32w") (UNSPEC_CRC32X "crc32x")
2419 (UNSPEC_CRC32CB "crc32cb") (UNSPEC_CRC32CH "crc32ch")
2420 (UNSPEC_CRC32CW "crc32cw") (UNSPEC_CRC32CX "crc32cx")])
2421
2422(define_int_attr crc_mode [(UNSPEC_CRC32B "QI") (UNSPEC_CRC32H "HI")
2423 (UNSPEC_CRC32W "SI") (UNSPEC_CRC32X "DI")
2424 (UNSPEC_CRC32CB "QI") (UNSPEC_CRC32CH "HI")
2425 (UNSPEC_CRC32CW "SI") (UNSPEC_CRC32CX "DI")])
2426
5a7a4e80
TB		 2427(define_int_attr aes_op [(UNSPEC_AESE "e") (UNSPEC_AESD "d")])
2428(define_int_attr aesmc_op [(UNSPEC_AESMC "mc") (UNSPEC_AESIMC "imc")])
30442682
TB		 2429
2430(define_int_attr sha1_op [(UNSPEC_SHA1C "c") (UNSPEC_SHA1P "p")
2431 (UNSPEC_SHA1M "m")])
b9cb0a44
TB		 2432
2433(define_int_attr sha256_op [(UNSPEC_SHA256H "") (UNSPEC_SHA256H2 "2")])
57b26d65
MW		 2434
2435(define_int_attr rdma_as [(UNSPEC_SQRDMLAH "a") (UNSPEC_SQRDMLSH "s")])
27086ea3
MC		 2436
2437(define_int_attr sha512_op [(UNSPEC_SHA512H "") (UNSPEC_SHA512H2 "2")])
2438
2439(define_int_attr sm3tt_op [(UNSPEC_SM3TT1A "1a") (UNSPEC_SM3TT1B "1b")
2440 (UNSPEC_SM3TT2A "2a") (UNSPEC_SM3TT2B "2b")])
2441
2442(define_int_attr sm3part_op [(UNSPEC_SM3PARTW1 "1") (UNSPEC_SM3PARTW2 "2")])
2443
2444(define_int_attr f16mac1 [(UNSPEC_FMLAL "a") (UNSPEC_FMLSL "s")
2445 (UNSPEC_FMLAL2 "a") (UNSPEC_FMLSL2 "s")])
43cacb12 2446
10bd1d96
KT		 2447(define_int_attr frintnzs_op [(UNSPEC_FRINT32Z "frint32z") (UNSPEC_FRINT32X "frint32x")
2448 (UNSPEC_FRINT64Z "frint64z") (UNSPEC_FRINT64X "frint64x")])
2449
43cacb12 2450;; The condition associated with an UNSPEC_COND_<xx>.
624d0f07
RS		 2451(define_int_attr cmp_op [(UNSPEC_COND_CMPEQ_WIDE "eq")
2452 (UNSPEC_COND_CMPGE_WIDE "ge")
2453 (UNSPEC_COND_CMPGT_WIDE "gt")
2454 (UNSPEC_COND_CMPHI_WIDE "hi")
2455 (UNSPEC_COND_CMPHS_WIDE "hs")
2456 (UNSPEC_COND_CMPLE_WIDE "le")
2457 (UNSPEC_COND_CMPLO_WIDE "lo")
2458 (UNSPEC_COND_CMPLS_WIDE "ls")
2459 (UNSPEC_COND_CMPLT_WIDE "lt")
2460 (UNSPEC_COND_CMPNE_WIDE "ne")
2461 (UNSPEC_COND_FCMEQ "eq")
cb18e86d
RS		 2462 (UNSPEC_COND_FCMGE "ge")
2463 (UNSPEC_COND_FCMGT "gt")
2464 (UNSPEC_COND_FCMLE "le")
2465 (UNSPEC_COND_FCMLT "lt")
4a942af6 2466 (UNSPEC_COND_FCMNE "ne")
624d0f07
RS		 2467 (UNSPEC_WHILE_LE "le")
2468 (UNSPEC_WHILE_LO "lo")
2469 (UNSPEC_WHILE_LS "ls")
2470 (UNSPEC_WHILE_LT "lt")])
2471
2472(define_int_attr while_optab_cmp [(UNSPEC_WHILE_LE "le")
2473 (UNSPEC_WHILE_LO "ult")
2474 (UNSPEC_WHILE_LS "ule")
2475 (UNSPEC_WHILE_LT "lt")])
2476
2477(define_int_attr brk_op [(UNSPEC_BRKA "a") (UNSPEC_BRKB "b")
2478 (UNSPEC_BRKN "n")
2479 (UNSPEC_BRKPA "pa") (UNSPEC_BRKPB "pb")])
2480
2481(define_int_attr sve_pred_op [(UNSPEC_PFIRST "pfirst") (UNSPEC_PNEXT "pnext")])
cb18e86d 2482
b0760a40
RS		 2483(define_int_attr sve_int_op [(UNSPEC_ANDV "andv")
2484 (UNSPEC_IORV "orv")
2485 (UNSPEC_XORV "eorv")
2486 (UNSPEC_UMAXV "umaxv")
2487 (UNSPEC_UMINV "uminv")
2488 (UNSPEC_SMAXV "smaxv")
d7a09c44 2489 (UNSPEC_SMINV "sminv")
624d0f07
RS		 2490 (UNSPEC_SMUL_HIGHPART "smulh")
2491 (UNSPEC_UMUL_HIGHPART "umulh")
2492 (UNSPEC_ASHIFT_WIDE "lsl")
2493 (UNSPEC_ASHIFTRT_WIDE "asr")
2494 (UNSPEC_LSHIFTRT_WIDE "lsr")
2495 (UNSPEC_RBIT "rbit")
d7a09c44
RS		 2496 (UNSPEC_REVB "revb")
2497 (UNSPEC_REVH "revh")
2498 (UNSPEC_REVW "revw")])
b0760a40 2499
624d0f07
RS		 2500(define_int_attr sve_fp_op [(UNSPEC_FRECPE "frecpe")
2501 (UNSPEC_FRECPS "frecps")
2502 (UNSPEC_RSQRTE "frsqrte")
2503 (UNSPEC_RSQRTS "frsqrts")
2504 (UNSPEC_FADDV "faddv")
b0760a40
RS		 2505 (UNSPEC_FMAXNMV "fmaxnmv")
2506 (UNSPEC_FMAXV "fmaxv")
2507 (UNSPEC_FMINNMV "fminnmv")
2508 (UNSPEC_FMINV "fminv")
624d0f07
RS		 2509 (UNSPEC_FMLA "fmla")
2510 (UNSPEC_FMLS "fmls")
2511 (UNSPEC_FEXPA "fexpa")
2512 (UNSPEC_FTSMUL "ftsmul")
2513 (UNSPEC_FTSSEL "ftssel")
b0760a40 2514 (UNSPEC_COND_FABS "fabs")
d45b20a5 2515 (UNSPEC_COND_FADD "fadd")
cb18e86d 2516 (UNSPEC_COND_FDIV "fdiv")
624d0f07 2517 (UNSPEC_COND_FMAX "fmax")
cb18e86d 2518 (UNSPEC_COND_FMAXNM "fmaxnm")
624d0f07 2519 (UNSPEC_COND_FMIN "fmin")
cb18e86d
RS		 2520 (UNSPEC_COND_FMINNM "fminnm")
2521 (UNSPEC_COND_FMUL "fmul")
624d0f07 2522 (UNSPEC_COND_FMULX "fmulx")
d45b20a5 2523 (UNSPEC_COND_FNEG "fneg")
624d0f07 2524 (UNSPEC_COND_FRECPX "frecpx")
d45b20a5
RS		 2525 (UNSPEC_COND_FRINTA "frinta")
2526 (UNSPEC_COND_FRINTI "frinti")
2527 (UNSPEC_COND_FRINTM "frintm")
2528 (UNSPEC_COND_FRINTN "frintn")
2529 (UNSPEC_COND_FRINTP "frintp")
2530 (UNSPEC_COND_FRINTX "frintx")
2531 (UNSPEC_COND_FRINTZ "frintz")
624d0f07 2532 (UNSPEC_COND_FSCALE "fscale")
d45b20a5 2533 (UNSPEC_COND_FSQRT "fsqrt")
cb18e86d
RS		 2534 (UNSPEC_COND_FSUB "fsub")])
2535
2536(define_int_attr sve_fp_op_rev [(UNSPEC_COND_FADD "fadd")
2537 (UNSPEC_COND_FDIV "fdivr")
624d0f07 2538 (UNSPEC_COND_FMAX "fmax")
cb18e86d 2539 (UNSPEC_COND_FMAXNM "fmaxnm")
624d0f07 2540 (UNSPEC_COND_FMIN "fmin")
cb18e86d
RS		 2541 (UNSPEC_COND_FMINNM "fminnm")
2542 (UNSPEC_COND_FMUL "fmul")
624d0f07 2543 (UNSPEC_COND_FMULX "fmulx")
cb18e86d 2544 (UNSPEC_COND_FSUB "fsubr")])
a08acce8 2545
9d63f43b
TC		 2546(define_int_attr rot [(UNSPEC_FCADD90 "90")
2547 (UNSPEC_FCADD270 "270")
2548 (UNSPEC_FCMLA "0")
2549 (UNSPEC_FCMLA90 "90")
2550 (UNSPEC_FCMLA180 "180")
624d0f07
RS		 2551 (UNSPEC_FCMLA270 "270")
2552 (UNSPEC_COND_FCADD90 "90")
2553 (UNSPEC_COND_FCADD270 "270")
2554 (UNSPEC_COND_FCMLA "0")
2555 (UNSPEC_COND_FCMLA90 "90")
2556 (UNSPEC_COND_FCMLA180 "180")
2557 (UNSPEC_COND_FCMLA270 "270")])
9d63f43b 2558
b41d1f6e
RS		 2559(define_int_attr sve_fmla_op [(UNSPEC_COND_FMLA "fmla")
2560 (UNSPEC_COND_FMLS "fmls")
2561 (UNSPEC_COND_FNMLA "fnmla")
2562 (UNSPEC_COND_FNMLS "fnmls")])
2563
2564(define_int_attr sve_fmad_op [(UNSPEC_COND_FMLA "fmad")
2565 (UNSPEC_COND_FMLS "fmsb")
2566 (UNSPEC_COND_FNMLA "fnmad")
2567 (UNSPEC_COND_FNMLS "fnmsb")])
0254ed79 2568
624d0f07
RS		 2569;; The register constraint to use for the final operand in a binary BRK.
2570(define_int_attr brk_reg_con [(UNSPEC_BRKN "0")
2571 (UNSPEC_BRKPA "Upa") (UNSPEC_BRKPB "Upa")])
2572
2573;; The register number to print for the above.
2574(define_int_attr brk_reg_opno [(UNSPEC_BRKN "0")
2575 (UNSPEC_BRKPA "3") (UNSPEC_BRKPB "3")])
2576
0254ed79
RS		 2577;; The predicate to use for the first input operand in a floating-point
2578;; <optab><mode>3 pattern.
2579(define_int_attr sve_pred_fp_rhs1_operand
2580 [(UNSPEC_COND_FADD "register_operand")
2581 (UNSPEC_COND_FDIV "register_operand")
624d0f07 2582 (UNSPEC_COND_FMAX "register_operand")
0254ed79 2583 (UNSPEC_COND_FMAXNM "register_operand")
624d0f07 2584 (UNSPEC_COND_FMIN "register_operand")
0254ed79
RS		 2585 (UNSPEC_COND_FMINNM "register_operand")
2586 (UNSPEC_COND_FMUL "register_operand")
624d0f07 2587 (UNSPEC_COND_FMULX "register_operand")
0254ed79
RS		 2588 (UNSPEC_COND_FSUB "aarch64_sve_float_arith_operand")])
2589
2590;; The predicate to use for the second input operand in a floating-point
2591;; <optab><mode>3 pattern.
2592(define_int_attr sve_pred_fp_rhs2_operand
2593 [(UNSPEC_COND_FADD "aarch64_sve_float_arith_with_sub_operand")
2594 (UNSPEC_COND_FDIV "register_operand")
624d0f07 2595 (UNSPEC_COND_FMAX "aarch64_sve_float_maxmin_operand")
75079ddf 2596 (UNSPEC_COND_FMAXNM "aarch64_sve_float_maxmin_operand")
624d0f07 2597 (UNSPEC_COND_FMIN "aarch64_sve_float_maxmin_operand")
75079ddf 2598 (UNSPEC_COND_FMINNM "aarch64_sve_float_maxmin_operand")
0254ed79 2599 (UNSPEC_COND_FMUL "aarch64_sve_float_mul_operand")
624d0f07 2600 (UNSPEC_COND_FMULX "register_operand")
0254ed79 2601 (UNSPEC_COND_FSUB "register_operand")])
a19ba9e1
RS		 2602
2603;; Likewise for immediates only.
2604(define_int_attr sve_pred_fp_rhs2_immediate
624d0f07
RS		 2605 [(UNSPEC_COND_FMAX "aarch64_sve_float_maxmin_immediate")
2606 (UNSPEC_COND_FMAXNM "aarch64_sve_float_maxmin_immediate")
2607 (UNSPEC_COND_FMIN "aarch64_sve_float_maxmin_immediate")
a19ba9e1
RS		 2608 (UNSPEC_COND_FMINNM "aarch64_sve_float_maxmin_immediate")
2609 (UNSPEC_COND_FMUL "aarch64_sve_float_mul_immediate")])
d7a09c44 2610
624d0f07
RS		 2611;; The maximum number of element bits that an instruction can handle.
2612(define_int_attr max_elem_bits [(UNSPEC_UADDV "64") (UNSPEC_SADDV "32")
2613 (UNSPEC_PFIRST "8") (UNSPEC_PNEXT "64")])
2614
d7a09c44 2615;; The minimum number of element bits that an instruction can handle.
624d0f07
RS		 2616(define_int_attr min_elem_bits [(UNSPEC_RBIT "8")
2617 (UNSPEC_REVB "16")
d7a09c44
RS		 2618 (UNSPEC_REVH "32")
2619 (UNSPEC_REVW "64")])
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