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8108dfde | 1 | ;; tsv110 pipeline description |
2 | ;; Copyright (C) 2018 Free Software Foundation, Inc. | |
3 | ;; | |
4 | ;; This file is part of GCC. | |
5 | ;; | |
6 | ;; GCC is free software; you can redistribute it and/or modify it | |
7 | ;; under the terms of the GNU General Public License as published by | |
8 | ;; the Free Software Foundation; either version 3, or (at your option) | |
9 | ;; any later version. | |
10 | ;; | |
11 | ;; GCC is distributed in the hope that it will be useful, but | |
12 | ;; WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | ;; General Public License for more details. | |
15 | ;; | |
16 | ;; You should have received a copy of the GNU General Public License | |
17 | ;; along with GCC; see the file COPYING3. If not see | |
18 | ;; <http://www.gnu.org/licenses/>. | |
19 | ||
20 | (define_automaton "tsv110") | |
21 | ||
22 | (define_attr "tsv110_neon_type" | |
23 | "neon_arith_acc, neon_arith_acc_q, | |
24 | neon_arith_basic, neon_arith_complex, | |
25 | neon_reduc_add_acc, neon_multiply, neon_multiply_q, | |
26 | neon_multiply_long, neon_mla, neon_mla_q, neon_mla_long, | |
27 | neon_sat_mla_long, neon_shift_acc, neon_shift_imm_basic, | |
28 | neon_shift_imm_complex, | |
29 | neon_shift_reg_basic, neon_shift_reg_basic_q, neon_shift_reg_complex, | |
30 | neon_shift_reg_complex_q, neon_fp_negabs, neon_fp_arith, | |
31 | neon_fp_arith_q, neon_fp_reductions_q, neon_fp_cvt_int, | |
32 | neon_fp_cvt_int_q, neon_fp_cvt16, neon_fp_minmax, neon_fp_mul, | |
33 | neon_fp_mul_q, neon_fp_mla, neon_fp_mla_q, neon_fp_recpe_rsqrte, | |
34 | neon_fp_recpe_rsqrte_q, neon_fp_recps_rsqrts, neon_fp_recps_rsqrts_q, | |
35 | neon_bitops, neon_bitops_q, neon_from_gp, | |
36 | neon_from_gp_q, neon_move, neon_tbl3_tbl4, neon_zip_q, neon_to_gp, | |
37 | neon_load_a, neon_load_b, neon_load_c, neon_load_d, neon_load_e, | |
38 | neon_load_f, neon_store_a, neon_store_b, neon_store_complex, | |
39 | unknown" | |
40 | (cond [ | |
41 | (eq_attr "type" "neon_arith_acc, neon_reduc_add_acc,\ | |
42 | neon_reduc_add_acc_q") | |
43 | (const_string "neon_arith_acc") | |
44 | (eq_attr "type" "neon_arith_acc_q") | |
45 | (const_string "neon_arith_acc_q") | |
46 | (eq_attr "type" "neon_abs,neon_abs_q,neon_add, neon_add_q, neon_add_long,\ | |
47 | neon_add_widen, neon_neg, neon_neg_q,\ | |
48 | neon_reduc_add, neon_reduc_add_q,\ | |
49 | neon_reduc_add_long, neon_sub, neon_sub_q,\ | |
50 | neon_sub_long, neon_sub_widen, neon_logic,\ | |
51 | neon_logic_q, neon_tst, neon_tst_q,\ | |
52 | neon_compare, neon_compare_q,\ | |
53 | neon_compare_zero, neon_compare_zero_q,\ | |
54 | neon_minmax, neon_minmax_q, neon_reduc_minmax,\ | |
55 | neon_reduc_minmax_q") | |
56 | (const_string "neon_arith_basic") | |
57 | (eq_attr "type" "neon_add_halve_narrow_q,\ | |
58 | neon_add_halve, neon_add_halve_q,\ | |
59 | neon_sub_halve, neon_sub_halve_q, neon_qabs,\ | |
60 | neon_qabs_q, neon_qadd, neon_qadd_q, neon_qneg,\ | |
61 | neon_qneg_q, neon_qsub, neon_qsub_q,\ | |
62 | neon_sub_halve_narrow_q") | |
63 | (const_string "neon_arith_complex") | |
64 | ||
65 | (eq_attr "type" "neon_mul_b, neon_mul_h, neon_mul_s,\ | |
66 | neon_mul_h_scalar, neon_mul_s_scalar,\ | |
67 | neon_sat_mul_b, neon_sat_mul_h,\ | |
68 | neon_sat_mul_s, neon_sat_mul_h_scalar,\ | |
69 | neon_sat_mul_s_scalar,\ | |
70 | neon_mul_b_long, neon_mul_h_long,\ | |
71 | neon_mul_s_long,\ | |
72 | neon_mul_h_scalar_long, neon_mul_s_scalar_long,\ | |
73 | neon_sat_mul_b_long, neon_sat_mul_h_long,\ | |
74 | neon_sat_mul_s_long, neon_sat_mul_h_scalar_long,\ | |
75 | neon_sat_mul_s_scalar_long,\ | |
76 | neon_mla_b, neon_mla_h, neon_mla_s,\ | |
77 | neon_mla_h_scalar, neon_mla_s_scalar,\ | |
78 | neon_mla_b_long, neon_mla_h_long,\ | |
79 | neon_mla_s_long,\ | |
80 | neon_mla_h_scalar_long, neon_mla_s_scalar_long,\ | |
81 | neon_sat_mla_b_long, neon_sat_mla_h_long,\ | |
82 | neon_sat_mla_s_long, neon_sat_mla_h_scalar_long,\ | |
83 | neon_sat_mla_s_scalar_long") | |
84 | (const_string "neon_multiply") | |
85 | (eq_attr "type" "neon_mul_b_q, neon_mul_h_q, neon_mul_s_q,\ | |
86 | neon_mul_h_scalar_q, neon_mul_s_scalar_q,\ | |
87 | neon_sat_mul_b_q, neon_sat_mul_h_q,\ | |
88 | neon_sat_mul_s_q, neon_sat_mul_h_scalar_q,\ | |
89 | neon_sat_mul_s_scalar_q,\ | |
90 | neon_mla_b_q, neon_mla_h_q, neon_mla_s_q,\ | |
91 | neon_mla_h_scalar_q, neon_mla_s_scalar_q") | |
92 | (const_string "neon_multiply_q") | |
93 | ||
94 | (eq_attr "type" "neon_shift_acc, neon_shift_acc_q") | |
95 | (const_string "neon_shift_acc") | |
96 | (eq_attr "type" "neon_shift_imm, neon_shift_imm_q,\ | |
97 | neon_shift_imm_narrow_q, neon_shift_imm_long") | |
98 | (const_string "neon_shift_imm_basic") | |
99 | (eq_attr "type" "neon_sat_shift_imm, neon_sat_shift_imm_q,\ | |
100 | neon_sat_shift_imm_narrow_q") | |
101 | (const_string "neon_shift_imm_complex") | |
102 | (eq_attr "type" "neon_shift_reg") | |
103 | (const_string "neon_shift_reg_basic") | |
104 | (eq_attr "type" "neon_shift_reg_q") | |
105 | (const_string "neon_shift_reg_basic_q") | |
106 | (eq_attr "type" "neon_sat_shift_reg") | |
107 | (const_string "neon_shift_reg_complex") | |
108 | (eq_attr "type" "neon_sat_shift_reg_q") | |
109 | (const_string "neon_shift_reg_complex_q") | |
110 | ||
111 | (eq_attr "type" "neon_fp_neg_s, neon_fp_neg_s_q,\ | |
112 | neon_fp_abs_s, neon_fp_abs_s_q,\ | |
113 | neon_fp_neg_d, neon_fp_neg_d_q,\ | |
114 | neon_fp_abs_d, neon_fp_abs_d_q,\ | |
115 | neon_fp_minmax_s,neon_fp_minmax_d,\ | |
116 | neon_fp_reduc_minmax_s,neon_fp_reduc_minmax_d") | |
117 | (const_string "neon_fp_negabs") | |
118 | (eq_attr "type" "neon_fp_addsub_s, neon_fp_abd_s,\ | |
119 | neon_fp_reduc_add_s, neon_fp_compare_s,\ | |
120 | neon_fp_round_s,\ | |
121 | neon_fp_addsub_d, neon_fp_abd_d,\ | |
122 | neon_fp_reduc_add_d, neon_fp_compare_d,\ | |
123 | neon_fp_round_d") | |
124 | (const_string "neon_fp_arith") | |
125 | (eq_attr "type" "neon_fp_addsub_s_q, neon_fp_abd_s_q,\ | |
126 | neon_fp_reduc_add_s_q, neon_fp_compare_s_q,\ | |
127 | neon_fp_minmax_s_q, neon_fp_round_s_q,\ | |
128 | neon_fp_addsub_d_q, neon_fp_abd_d_q,\ | |
129 | neon_fp_reduc_add_d_q, neon_fp_compare_d_q,\ | |
130 | neon_fp_minmax_d_q, neon_fp_round_d_q") | |
131 | (const_string "neon_fp_arith_q") | |
132 | (eq_attr "type" "neon_fp_reduc_minmax_s_q,\ | |
133 | neon_fp_reduc_minmax_d_q,\ | |
134 | neon_fp_reduc_add_s_q, neon_fp_reduc_add_d_q") | |
135 | (const_string "neon_fp_reductions_q") | |
136 | (eq_attr "type" "neon_fp_to_int_s, neon_int_to_fp_s,\ | |
137 | neon_fp_to_int_d, neon_int_to_fp_d") | |
138 | (const_string "neon_fp_cvt_int") | |
139 | (eq_attr "type" "neon_fp_to_int_s_q, neon_int_to_fp_s_q,\ | |
140 | neon_fp_to_int_d_q, neon_int_to_fp_d_q") | |
141 | (const_string "neon_fp_cvt_int_q") | |
142 | (eq_attr "type" "neon_fp_cvt_narrow_s_q, neon_fp_cvt_widen_h") | |
143 | (const_string "neon_fp_cvt16") | |
144 | (eq_attr "type" "neon_fp_mul_s, neon_fp_mul_s_scalar,\ | |
145 | neon_fp_mul_d") | |
146 | (const_string "neon_fp_mul") | |
147 | (eq_attr "type" "neon_fp_mul_s_q, neon_fp_mul_s_scalar_q,\ | |
148 | neon_fp_mul_d_q, neon_fp_mul_d_scalar_q") | |
149 | (const_string "neon_fp_mul_q") | |
150 | (eq_attr "type" "neon_fp_mla_s, neon_fp_mla_s_scalar,\ | |
151 | neon_fp_mla_d") | |
152 | (const_string "neon_fp_mla") | |
153 | (eq_attr "type" "neon_fp_mla_s_q, neon_fp_mla_s_scalar_q, | |
154 | neon_fp_mla_d_q, neon_fp_mla_d_scalar_q") | |
155 | (const_string "neon_fp_mla_q") | |
156 | (eq_attr "type" "neon_fp_recpe_s, neon_fp_rsqrte_s,\ | |
157 | neon_fp_recpx_s,\ | |
158 | neon_fp_recpe_d, neon_fp_rsqrte_d,\ | |
159 | neon_fp_recpx_d") | |
160 | (const_string "neon_fp_recpe_rsqrte") | |
161 | (eq_attr "type" "neon_fp_recpe_s_q, neon_fp_rsqrte_s_q,\ | |
162 | neon_fp_recpx_s_q,\ | |
163 | neon_fp_recpe_d_q, neon_fp_rsqrte_d_q,\ | |
164 | neon_fp_recpx_d_q") | |
165 | (const_string "neon_fp_recpe_rsqrte_q") | |
166 | (eq_attr "type" "neon_fp_recps_s, neon_fp_rsqrts_s,\ | |
167 | neon_fp_recps_d, neon_fp_rsqrts_d") | |
168 | (const_string "neon_fp_recps_rsqrts") | |
169 | (eq_attr "type" "neon_fp_recps_s_q, neon_fp_rsqrts_s_q,\ | |
170 | neon_fp_recps_d_q, neon_fp_rsqrts_d_q") | |
171 | (const_string "neon_fp_recps_rsqrts_q") | |
172 | (eq_attr "type" "neon_bsl, neon_cls, neon_cnt,\ | |
173 | neon_rev, neon_permute, neon_rbit,\ | |
174 | neon_tbl1, neon_tbl2, neon_zip,\ | |
175 | neon_dup, neon_dup_q, neon_ext, neon_ext_q,\ | |
176 | neon_move, neon_move_q, neon_move_narrow_q") | |
177 | (const_string "neon_bitops") | |
178 | (eq_attr "type" "neon_bsl_q, neon_cls_q, neon_cnt_q,\ | |
179 | neon_rev_q, neon_permute_q, neon_rbit_q") | |
180 | (const_string "neon_bitops_q") | |
181 | (eq_attr "type" "neon_from_gp,f_mcr,f_mcrr") | |
182 | (const_string "neon_from_gp") | |
183 | (eq_attr "type" "neon_from_gp_q") | |
184 | (const_string "neon_from_gp_q") | |
185 | ||
186 | (eq_attr "type" "f_loads, f_loadd,\ | |
187 | neon_load1_1reg, neon_load1_1reg_q,\ | |
188 | neon_load1_2reg, neon_load1_2reg_q") | |
189 | (const_string "neon_load_a") | |
190 | (eq_attr "type" "neon_load1_3reg, neon_load1_3reg_q,\ | |
191 | neon_load1_4reg, neon_load1_4reg_q") | |
192 | (const_string "neon_load_b") | |
193 | (eq_attr "type" "neon_load1_one_lane, neon_load1_one_lane_q,\ | |
194 | neon_load1_all_lanes, neon_load1_all_lanes_q,\ | |
195 | neon_load2_2reg, neon_load2_2reg_q,\ | |
196 | neon_load2_all_lanes, neon_load2_all_lanes_q") | |
197 | (const_string "neon_load_c") | |
198 | (eq_attr "type" "neon_load2_4reg, neon_load2_4reg_q,\ | |
199 | neon_load3_3reg, neon_load3_3reg_q,\ | |
200 | neon_load3_one_lane, neon_load3_one_lane_q,\ | |
201 | neon_load4_4reg, neon_load4_4reg_q") | |
202 | (const_string "neon_load_d") | |
203 | (eq_attr "type" "neon_load2_one_lane, neon_load2_one_lane_q,\ | |
204 | neon_load3_all_lanes, neon_load3_all_lanes_q,\ | |
205 | neon_load4_all_lanes, neon_load4_all_lanes_q") | |
206 | (const_string "neon_load_e") | |
207 | (eq_attr "type" "neon_load4_one_lane, neon_load4_one_lane_q") | |
208 | (const_string "neon_load_f") | |
209 | ||
210 | (eq_attr "type" "f_stores, f_stored,\ | |
211 | neon_store1_1reg") | |
212 | (const_string "neon_store_a") | |
213 | (eq_attr "type" "neon_store1_2reg, neon_store1_1reg_q") | |
214 | (const_string "neon_store_b") | |
215 | (eq_attr "type" "neon_store1_3reg, neon_store1_3reg_q,\ | |
216 | neon_store3_3reg, neon_store3_3reg_q,\ | |
217 | neon_store2_4reg, neon_store2_4reg_q,\ | |
218 | neon_store4_4reg, neon_store4_4reg_q,\ | |
219 | neon_store2_2reg, neon_store2_2reg_q,\ | |
220 | neon_store3_one_lane, neon_store3_one_lane_q,\ | |
221 | neon_store4_one_lane, neon_store4_one_lane_q,\ | |
222 | neon_store1_4reg, neon_store1_4reg_q,\ | |
223 | neon_store1_one_lane, neon_store1_one_lane_q,\ | |
224 | neon_store2_one_lane, neon_store2_one_lane_q") | |
225 | (const_string "neon_store_complex")] | |
226 | (const_string "unknown"))) | |
227 | ||
228 | ;; The tsv110 core is modelled as issues pipeline that has | |
229 | ;; the following functional units. | |
230 | ;; 1. Three pipelines for integer operations: ALU1, ALU2, ALU3 | |
231 | ||
232 | (define_cpu_unit "tsv110_alu1_issue" "tsv110") | |
233 | (define_reservation "tsv110_alu1" "tsv110_alu1_issue") | |
234 | ||
235 | (define_cpu_unit "tsv110_alu2_issue" "tsv110") | |
236 | (define_reservation "tsv110_alu2" "tsv110_alu2_issue") | |
237 | ||
238 | (define_cpu_unit "tsv110_alu3_issue" "tsv110") | |
239 | (define_reservation "tsv110_alu3" "tsv110_alu3_issue") | |
240 | ||
241 | ;; 2. One pipeline for complex integer operations: MDU | |
242 | ||
243 | (define_cpu_unit "tsv110_mdu_issue" "tsv110") | |
244 | (define_reservation "tsv110_mdu" "tsv110_mdu_issue") | |
245 | ||
246 | ;; 3. Two asymmetric pipelines for Asimd and FP operations: FSU1, FSU2 | |
247 | (define_automaton "tsv110_fsu") | |
248 | ||
249 | (define_cpu_unit "tsv110_fsu1_issue" | |
250 | "tsv110_fsu") | |
251 | (define_cpu_unit "tsv110_fsu2_issue" | |
252 | "tsv110_fsu") | |
253 | ||
254 | (define_reservation "tsv110_fsu1" "tsv110_fsu1_issue") | |
255 | (define_reservation "tsv110_fsu2" "tsv110_fsu2_issue") | |
256 | ||
257 | ;; 4. Two pipeline for branch operations but same with alu2 and alu3: BRU1, BRU2 | |
258 | ||
259 | ;; 5. Two pipelines for load and store operations: LS1, LS2. | |
260 | ||
261 | (define_cpu_unit "tsv110_ls1_issue" "tsv110") | |
262 | (define_cpu_unit "tsv110_ls2_issue" "tsv110") | |
263 | (define_reservation "tsv110_ls1" "tsv110_ls1_issue") | |
264 | (define_reservation "tsv110_ls2" "tsv110_ls2_issue") | |
265 | ||
266 | ;; Block all issue queues. | |
267 | ||
268 | (define_reservation "tsv110_block" "tsv110_fsu1_issue + tsv110_fsu2_issue | |
269 | + tsv110_mdu_issue + tsv110_alu1_issue | |
270 | + tsv110_alu2_issue + tsv110_alu3_issue + tsv110_ls1_issue + tsv110_ls2_issue") | |
271 | ||
272 | ;; Simple Execution Unit: | |
273 | ;; | |
274 | ;; Simple ALU without shift | |
275 | (define_insn_reservation "tsv110_alu" 1 | |
276 | (and (eq_attr "tune" "tsv110") | |
277 | (eq_attr "type" "alu_imm,logic_imm,\ | |
278 | alu_sreg,logic_reg,\ | |
279 | adc_imm,adc_reg,\ | |
280 | adr,bfm,clz,rbit,rev,\ | |
281 | shift_imm,shift_reg,\ | |
282 | mov_imm,mov_reg,\ | |
283 | mvn_imm,mvn_reg,\ | |
284 | mrs,multiple,no_insn")) | |
285 | "tsv110_alu1|tsv110_alu2|tsv110_alu3") | |
286 | ||
287 | (define_insn_reservation "tsv110_alus" 1 | |
288 | (and (eq_attr "tune" "tsv110") | |
289 | (eq_attr "type" "alus_imm,logics_imm,\ | |
290 | alus_sreg,logics_reg,\ | |
291 | adcs_imm,adcs_reg")) | |
292 | "tsv110_alu2|tsv110_alu3") | |
293 | ||
294 | ;; ALU ops with shift | |
295 | (define_insn_reservation "tsv110_alu_shift" 2 | |
296 | (and (eq_attr "tune" "tsv110") | |
297 | (eq_attr "type" "extend,\ | |
298 | alu_shift_imm,alu_shift_reg,\ | |
299 | crc,logic_shift_imm,logic_shift_reg,\ | |
300 | mov_shift,mvn_shift,\ | |
301 | mov_shift_reg,mvn_shift_reg")) | |
302 | "tsv110_mdu") | |
303 | ||
304 | (define_insn_reservation "tsv110_alus_shift" 2 | |
305 | (and (eq_attr "tune" "tsv110") | |
306 | (eq_attr "type" "alus_shift_imm,alus_shift_reg,\ | |
307 | logics_shift_imm,logics_shift_reg")) | |
308 | "tsv110_alu2|tsv110_alu3") | |
309 | ||
310 | ;; Multiplies instructions | |
311 | (define_insn_reservation "tsv110_mult" 3 | |
312 | (and (eq_attr "tune" "tsv110") | |
313 | (ior (eq_attr "mul32" "yes") | |
314 | (eq_attr "widen_mul64" "yes"))) | |
315 | "tsv110_mdu") | |
316 | ||
317 | ;; Integer divide | |
318 | (define_insn_reservation "tsv110_div" 10 | |
319 | (and (eq_attr "tune" "tsv110") | |
320 | (eq_attr "type" "udiv,sdiv")) | |
321 | "tsv110_mdu") | |
322 | ||
323 | ;; Block all issue pipes for a cycle | |
324 | (define_insn_reservation "tsv110_block" 1 | |
325 | (and (eq_attr "tune" "tsv110") | |
326 | (eq_attr "type" "block")) | |
327 | "tsv110_block") | |
328 | ||
329 | ;; Branch execution Unit | |
330 | ;; | |
331 | ;; Branches take two issue slot. | |
332 | ;; No latency as there is no result | |
333 | (define_insn_reservation "tsv110_branch" 0 | |
334 | (and (eq_attr "tune" "tsv110") | |
335 | (eq_attr "type" "branch")) | |
336 | "tsv110_alu2|tsv110_alu3") | |
337 | ||
338 | ;; Load-store execution Unit | |
339 | ;; | |
340 | ;; Loads of up to two words. | |
341 | (define_insn_reservation "tsv110_load1" 4 | |
342 | (and (eq_attr "tune" "tsv110") | |
343 | (eq_attr "type" "load_4,load_8")) | |
344 | "tsv110_ls1|tsv110_ls2") | |
345 | ||
346 | ;; Stores of up to two words. | |
347 | (define_insn_reservation "tsv110_store1" 0 | |
348 | (and (eq_attr "tune" "tsv110") | |
349 | (eq_attr "type" "store_4,store_8")) | |
350 | "tsv110_ls1|tsv110_ls2") | |
351 | ||
352 | ;; Advanced SIMD Unit - Integer Arithmetic Instructions. | |
353 | ||
354 | (define_insn_reservation "tsv110_neon_abd_aba" 4 | |
355 | (and (eq_attr "tune" "tsv110") | |
356 | (eq_attr "type" "neon_abd,neon_arith_acc")) | |
357 | "tsv110_fsu1|tsv110_fsu2") | |
358 | ||
359 | (define_insn_reservation "tsv110_neon_abd_aba_q" 4 | |
360 | (and (eq_attr "tune" "tsv110") | |
361 | (eq_attr "type" "neon_arith_acc_q")) | |
362 | "tsv110_fsu1|tsv110_fsu2") | |
363 | ||
364 | (define_insn_reservation "tsv110_neon_arith_basic" 2 | |
365 | (and (eq_attr "tune" "tsv110") | |
366 | (eq_attr "tsv110_neon_type" "neon_arith_basic")) | |
367 | "tsv110_fsu1|tsv110_fsu2") | |
368 | ||
369 | (define_insn_reservation "tsv110_neon_arith_complex" 4 | |
370 | (and (eq_attr "tune" "tsv110") | |
371 | (eq_attr "tsv110_neon_type" "neon_arith_complex")) | |
372 | "tsv110_fsu1|tsv110_fsu2") | |
373 | ||
374 | ;; Integer Multiply Instructions. | |
375 | ;; D-form | |
376 | (define_insn_reservation "tsv110_neon_multiply" 4 | |
377 | (and (eq_attr "tune" "tsv110") | |
378 | (eq_attr "tsv110_neon_type" "neon_multiply")) | |
379 | "tsv110_fsu1") | |
380 | ||
381 | (define_insn_reservation "tsv110_neon_multiply_dlong" 2 | |
382 | (and (eq_attr "tune" "tsv110") | |
383 | (eq_attr "type" "neon_mul_d_long")) | |
384 | "tsv110_fsu1") | |
385 | ||
386 | ;; Q-form | |
387 | (define_insn_reservation "tsv110_neon_multiply_q" 8 | |
388 | (and (eq_attr "tune" "tsv110") | |
389 | (eq_attr "tsv110_neon_type" "neon_multiply_q")) | |
390 | "tsv110_fsu1") | |
391 | ||
392 | ;; Integer Shift Instructions. | |
393 | ||
394 | (define_insn_reservation | |
395 | "tsv110_neon_shift_acc" 4 | |
396 | (and (eq_attr "tune" "tsv110") | |
397 | (eq_attr "tsv110_neon_type" "neon_shift_acc,\ | |
398 | neon_shift_imm_basic,neon_shift_imm_complex,neon_shift_reg_basic,\ | |
399 | neon_shift_reg_complex")) | |
400 | "tsv110_fsu1") | |
401 | ||
402 | (define_insn_reservation | |
403 | "tsv110_neon_shift_acc_q" 4 | |
404 | (and (eq_attr "tune" "tsv110") | |
405 | (eq_attr "tsv110_neon_type" "neon_shift_reg_basic_q,\ | |
406 | neon_shift_reg_complex_q")) | |
407 | "tsv110_fsu1") | |
408 | ||
409 | ;; Floating Point Instructions. | |
410 | ||
411 | (define_insn_reservation | |
412 | "tsv110_neon_fp_negabs" 2 | |
413 | (and (eq_attr "tune" "tsv110") | |
414 | (eq_attr "tsv110_neon_type" "neon_fp_negabs")) | |
415 | "(tsv110_fsu1|tsv110_fsu2)") | |
416 | ||
417 | (define_insn_reservation | |
418 | "tsv110_neon_fp_arith" 4 | |
419 | (and (eq_attr "tune" "tsv110") | |
420 | (eq_attr "tsv110_neon_type" "neon_fp_arith")) | |
421 | "(tsv110_fsu1|tsv110_fsu2)") | |
422 | ||
423 | (define_insn_reservation | |
424 | "tsv110_neon_fp_arith_q" 4 | |
425 | (and (eq_attr "tune" "tsv110") | |
426 | (eq_attr "tsv110_neon_type" "neon_fp_arith_q")) | |
427 | "tsv110_fsu1|tsv110_fsu2") | |
428 | ||
429 | (define_insn_reservation | |
430 | "tsv110_neon_fp_minmax_q" 2 | |
431 | (and (eq_attr "tune" "tsv110") | |
432 | (eq_attr "type" "neon_fp_minmax_s_q,neon_fp_minmax_d_q")) | |
433 | "tsv110_fsu1|tsv110_fsu2") | |
434 | ||
435 | (define_insn_reservation | |
436 | "tsv110_neon_fp_reductions_q" 4 | |
437 | (and (eq_attr "tune" "tsv110") | |
438 | (eq_attr "tsv110_neon_type" "neon_fp_reductions_q")) | |
439 | "tsv110_fsu1|tsv110_fsu2") | |
440 | ||
441 | (define_insn_reservation | |
442 | "tsv110_neon_fp_cvt_int" 2 | |
443 | (and (eq_attr "tune" "tsv110") | |
444 | (eq_attr "tsv110_neon_type" "neon_fp_cvt_int,neon_fp_cvt_int_q")) | |
445 | "tsv110_fsu1|tsv110_fsu2") | |
446 | ||
447 | (define_insn_reservation | |
448 | "tsv110_neon_fp_mul" 5 | |
449 | (and (eq_attr "tune" "tsv110") | |
450 | (eq_attr "tsv110_neon_type" "neon_fp_mul")) | |
451 | "tsv110_fsu1|tsv110_fsu2") | |
452 | ||
453 | (define_insn_reservation | |
454 | "tsv110_neon_fp_mul_q" 5 | |
455 | (and (eq_attr "tune" "tsv110") | |
456 | (eq_attr "tsv110_neon_type" "neon_fp_mul_q")) | |
457 | "tsv110_fsu1|tsv110_fsu2") | |
458 | ||
459 | (define_insn_reservation | |
460 | "tsv110_neon_fp_mla" 7 | |
461 | (and (eq_attr "tune" "tsv110") | |
462 | (eq_attr "tsv110_neon_type" "neon_fp_mla,\ | |
463 | neon_fp_recps_rsqrts")) | |
464 | "tsv110_fsu1|tsv110_fsu2") | |
465 | ||
466 | (define_insn_reservation | |
467 | "tsv110_neon_fp_recpe_rsqrte" 3 | |
468 | (and (eq_attr "tune" "tsv110") | |
469 | (eq_attr "tsv110_neon_type" "neon_fp_recpe_rsqrte")) | |
470 | "tsv110_fsu1|tsv110_fsu2") | |
471 | ||
472 | (define_insn_reservation | |
473 | "tsv110_neon_fp_mla_q" 7 | |
474 | (and (eq_attr "tune" "tsv110") | |
475 | (eq_attr "tsv110_neon_type" "neon_fp_mla_q,\ | |
476 | neon_fp_recps_rsqrts_q")) | |
477 | "tsv110_fsu1|tsv110_fsu2") | |
478 | ||
479 | (define_insn_reservation | |
480 | "tsv110_neon_fp_recpe_rsqrte_q" 3 | |
481 | (and (eq_attr "tune" "tsv110") | |
482 | (eq_attr "tsv110_neon_type" "neon_fp_recpe_rsqrte_q")) | |
483 | "tsv110_fsu1|tsv110_fsu2") | |
484 | ||
485 | ;; Miscellaneous Instructions. | |
486 | ||
487 | (define_insn_reservation | |
488 | "tsv110_neon_bitops" 2 | |
489 | (and (eq_attr "tune" "tsv110") | |
490 | (eq_attr "tsv110_neon_type" "neon_bitops")) | |
491 | "tsv110_fsu1|tsv110_fsu2") | |
492 | ||
493 | (define_insn_reservation | |
494 | "tsv110_neon_dup" 2 | |
495 | (and (eq_attr "tune" "tsv110") | |
496 | (eq_attr "type" "neon_from_gp,f_mcr")) | |
497 | "tsv110_fsu1|tsv110_fsu2") | |
498 | ||
499 | (define_insn_reservation | |
500 | "tsv110_neon_mov" 2 | |
501 | (and (eq_attr "tune" "tsv110") | |
502 | (eq_attr "type" "f_mcrr")) | |
503 | "tsv110_fsu1|tsv110_fsu2") | |
504 | ||
505 | (define_insn_reservation | |
506 | "tsv110_neon_bitops_q" 2 | |
507 | (and (eq_attr "tune" "tsv110") | |
508 | (eq_attr "tsv110_neon_type" "neon_bitops_q")) | |
509 | "tsv110_fsu1|tsv110_fsu2") | |
510 | ||
511 | (define_insn_reservation | |
512 | "tsv110_neon_from_gp_q" 4 | |
513 | (and (eq_attr "tune" "tsv110") | |
514 | (eq_attr "tsv110_neon_type" "neon_from_gp_q")) | |
515 | "(tsv110_alu1+tsv110_fsu1)|(tsv110_alu1+tsv110_fsu2)") | |
516 | ||
517 | (define_insn_reservation | |
518 | "tsv110_neon_to_gp" 3 | |
519 | (and (eq_attr "tune" "tsv110") | |
520 | (eq_attr "type" "neon_to_gp,neon_to_gp_q")) | |
521 | "tsv110_fsu1") | |
522 | ||
523 | ;; Load Instructions. | |
524 | ||
525 | (define_insn_reservation | |
526 | "tsv110_neon_ld1_lane" 8 | |
527 | (and (eq_attr "tune" "tsv110") | |
528 | (eq_attr "type" "neon_load1_one_lane,neon_load1_one_lane_q,\ | |
529 | neon_load1_all_lanes,neon_load1_all_lanes_q")) | |
530 | "(tsv110_ls1 + tsv110_fsu1)|(tsv110_ls1 + tsv110_fsu2)|(tsv110_ls2 + tsv110_fsu1)|(tsv110_ls2 + tsv110_fsu2)") | |
531 | ||
532 | (define_insn_reservation | |
533 | "tsv110_neon_ld1_reg1" 6 | |
534 | (and (eq_attr "tune" "tsv110") | |
535 | (eq_attr "type" "f_loads,f_loadd,neon_load1_1reg,neon_load1_1reg_q")) | |
536 | "tsv110_ls1|tsv110_ls2") | |
537 | ||
538 | (define_insn_reservation | |
539 | "tsv110_neon_ld1_reg2" 6 | |
540 | (and (eq_attr "tune" "tsv110") | |
541 | (eq_attr "type" "neon_load1_2reg,neon_load1_2reg_q")) | |
542 | "tsv110_ls1|tsv110_ls2") | |
543 | ||
544 | (define_insn_reservation | |
545 | "tsv110_neon_ld1_reg3" 7 | |
546 | (and (eq_attr "tune" "tsv110") | |
547 | (eq_attr "type" "neon_load1_3reg,neon_load1_3reg_q")) | |
548 | "tsv110_ls1|tsv110_ls2") | |
549 | ||
550 | (define_insn_reservation | |
551 | "tsv110_neon_ld1_reg4" 7 | |
552 | (and (eq_attr "tune" "tsv110") | |
553 | (eq_attr "type" "neon_load1_4reg,neon_load1_4reg_q")) | |
554 | "tsv110_ls1|tsv110_ls2") | |
555 | ||
556 | (define_insn_reservation | |
557 | "tsv110_neon_ld2" 8 | |
558 | (and (eq_attr "tune" "tsv110") | |
559 | (eq_attr "type" "neon_load1_2reg,neon_load1_2reg_q,\ | |
560 | neon_load2_2reg,neon_load2_2reg_q,neon_load2_all_lanes,\ | |
561 | neon_load2_all_lanes_q,neon_load2_one_lane,neon_load2_one_lane_q")) | |
562 | "(tsv110_ls1 + tsv110_fsu1)|(tsv110_ls1 + tsv110_fsu2)|(tsv110_ls2 + tsv110_fsu1)|(tsv110_ls2 + tsv110_fsu2)") | |
563 | ||
564 | (define_insn_reservation | |
565 | "tsv110_neon_ld3" 9 | |
566 | (and (eq_attr "tune" "tsv110") | |
567 | (eq_attr "type" "neon_load3_3reg,neon_load3_3reg_q,\ | |
568 | neon_load3_one_lane,neon_load3_one_lane_q,\ | |
569 | neon_load3_all_lanes,neon_load3_all_lanes_q")) | |
570 | "(tsv110_ls1 + tsv110_fsu1)|(tsv110_ls1 + tsv110_fsu2)|(tsv110_ls2 + tsv110_fsu1)|(tsv110_ls2 + tsv110_fsu2)") | |
571 | ||
572 | (define_insn_reservation | |
573 | "tsv110_neon_ld4_lane" 9 | |
574 | (and (eq_attr "tune" "tsv110") | |
575 | (eq_attr "type" "neon_load4_all_lanes,neon_load4_all_lanes_q,\ | |
576 | neon_load4_one_lane,neon_load4_one_lane_q")) | |
577 | "(tsv110_ls1 + tsv110_fsu1)|(tsv110_ls1 + tsv110_fsu2)|(tsv110_ls2 + tsv110_fsu1)|(tsv110_ls2 + tsv110_fsu2)") | |
578 | ||
579 | (define_insn_reservation | |
580 | "tsv110_neon_ld4_reg" 11 | |
581 | (and (eq_attr "tune" "tsv110") | |
582 | (eq_attr "type" "neon_load4_all_lanes,neon_load4_all_lanes_q,\ | |
583 | neon_load4_one_lane,neon_load4_one_lane_q")) | |
584 | "(tsv110_ls1 + tsv110_fsu1)|(tsv110_ls1 + tsv110_fsu2)|(tsv110_ls2 + tsv110_fsu1)|(tsv110_ls2 + tsv110_fsu2)") | |
585 | ||
586 | ;; Store Instructions. | |
587 | ||
588 | (define_insn_reservation | |
589 | "tsv110_neon_store_a" 0 | |
590 | (and (eq_attr "tune" "tsv110") | |
591 | (eq_attr "tsv110_neon_type" "neon_store_a")) | |
592 | "tsv110_fsu1|tsv110_fsu2") | |
593 | ||
594 | (define_insn_reservation | |
595 | "tsv110_neon_store_b" 0 | |
596 | (and (eq_attr "tune" "tsv110") | |
597 | (eq_attr "tsv110_neon_type" "neon_store_b")) | |
598 | "tsv110_fsu1|tsv110_fsu2") | |
599 | ||
600 | ;; These block issue for a number of cycles proportional to the number | |
601 | ;; of 64-bit chunks they will store, we don't attempt to model that | |
602 | ;; precisely, treat them as blocking execution for two cycles when | |
603 | ;; issued. | |
604 | (define_insn_reservation | |
605 | "tsv110_neon_store_complex" 0 | |
606 | (and (eq_attr "tune" "tsv110") | |
607 | (eq_attr "tsv110_neon_type" "neon_store_complex")) | |
608 | "tsv110_block*2") | |
609 | ||
610 | ;; Floating-Point Operations. | |
611 | ||
612 | (define_insn_reservation "tsv110_fp_const" 2 | |
613 | (and (eq_attr "tune" "tsv110") | |
614 | (eq_attr "type" "fconsts,fconstd,fmov")) | |
615 | "tsv110_fsu1|tsv110_fsu2") | |
616 | ||
617 | (define_insn_reservation "tsv110_fp_add_sub" 5 | |
618 | (and (eq_attr "tune" "tsv110") | |
619 | (eq_attr "type" "fadds,faddd,fmuls,fmuld")) | |
620 | "tsv110_fsu1|tsv110_fsu2") | |
621 | ||
622 | (define_insn_reservation "tsv110_fp_mac" 7 | |
623 | (and (eq_attr "tune" "tsv110") | |
624 | (eq_attr "type" "fmacs,ffmas,fmacd,ffmad")) | |
625 | "tsv110_fsu1|tsv110_fsu2") | |
626 | ||
627 | (define_insn_reservation "tsv110_fp_cvt" 3 | |
628 | (and (eq_attr "tune" "tsv110") | |
629 | (eq_attr "type" "f_cvt")) | |
630 | "tsv110_fsu1|tsv110_fsu2") | |
631 | ||
632 | (define_insn_reservation "tsv110_fp_cvtf2i" 4 | |
633 | (and (eq_attr "tune" "tsv110") | |
634 | (eq_attr "type" "f_cvtf2i")) | |
635 | "tsv110_fsu1") | |
636 | ||
637 | (define_insn_reservation "tsv110_fp_cvti2f" 5 | |
638 | (and (eq_attr "tune" "tsv110") | |
639 | (eq_attr "type" "f_cvti2f")) | |
640 | "(tsv110_alu1+tsv110_fsu1)|(tsv110_alu1+tsv110_fsu2)") | |
641 | ||
642 | (define_insn_reservation "tsv110_fp_cmp" 4 | |
643 | (and (eq_attr "tune" "tsv110") | |
644 | (eq_attr "type" "fcmps,fcmpd")) | |
645 | "tsv110_fsu1|tsv110_fsu2") | |
646 | ||
647 | (define_insn_reservation "tsv110_fp_arith" 2 | |
648 | (and (eq_attr "tune" "tsv110") | |
649 | (eq_attr "type" "ffariths,ffarithd")) | |
650 | "tsv110_fsu1|tsv110_fsu2") | |
651 | ||
652 | (define_insn_reservation "tsv110_fp_divs" 12 | |
653 | (and (eq_attr "tune" "tsv110") | |
654 | (eq_attr "type" "fdivs,neon_fp_div_s,fdivd,neon_fp_div_d,\ | |
655 | neon_fp_div_s_q,neon_fp_div_d_q")) | |
656 | "tsv110_fsu1") | |
657 | ||
658 | (define_insn_reservation "tsv110_fp_sqrts" 24 | |
659 | (and (eq_attr "tune" "tsv110") | |
660 | (eq_attr "type" "fsqrts,neon_fp_sqrt_s,fsqrtd,neon_fp_sqrt_d,\ | |
661 | neon_fp_sqrt_s_q,neon_fp_sqrt_d_q")) | |
662 | "tsv110_fsu2") | |
663 | ||
664 | (define_insn_reservation "tsv110_crypto_aes" 3 | |
665 | (and (eq_attr "tune" "tsv110") | |
666 | (eq_attr "type" "crypto_aese,crypto_aesmc")) | |
667 | "tsv110_fsu1") | |
668 | ||
669 | (define_insn_reservation "tsv110_crypto_sha1_fast" 2 | |
670 | (and (eq_attr "tune" "tsv110") | |
671 | (eq_attr "type" "crypto_sha1_fast,crypto_sha1_xor")) | |
672 | "(tsv110_fsu1|tsv110_fsu2)") | |
673 | ||
674 | (define_insn_reservation "tsv110_crypto_sha256_fast" 2 | |
675 | (and (eq_attr "tune" "tsv110") | |
676 | (eq_attr "type" "crypto_sha256_fast")) | |
677 | "tsv110_fsu1") | |
678 | ||
679 | (define_insn_reservation "tsv110_crypto_complex" 5 | |
680 | (and (eq_attr "tune" "tsv110") | |
681 | (eq_attr "type" "crypto_sha1_slow,crypto_sha256_slow")) | |
682 | "tsv110_fsu1") | |
683 | ||
684 | ;; We lie with calls. They take up all issue slots, but are otherwise | |
685 | ;; not harmful. | |
686 | (define_insn_reservation "tsv110_call" 1 | |
687 | (and (eq_attr "tune" "tsv110") | |
688 | (eq_attr "type" "call")) | |
689 | "tsv110_alu1_issue+tsv110_alu2_issue+tsv110_alu3_issue+tsv110_fsu1_issue+tsv110_fsu2_issue\ | |
690 | +tsv110_mdu_issue+tsv110_ls1_issue+tsv110_ls2_issue" | |
691 | ) | |
692 | ||
693 | ;; Simple execution unit bypasses | |
694 | (define_bypass 1 "tsv110_alu" | |
695 | "tsv110_alu,tsv110_alu_shift") | |
696 | (define_bypass 2 "tsv110_alu_shift" | |
697 | "tsv110_alu,tsv110_alu_shift") | |
698 | ||
699 | ;; An MLA or a MUL can feed a dependent MLA. | |
700 | (define_bypass 3 "tsv110_neon_*mla*,tsv110_neon_*mul*" | |
701 | "tsv110_neon_*mla*") | |
702 | ||
703 | ;; We don't need to care about control hazards, either the branch is | |
704 | ;; predicted in which case we pay no penalty, or the branch is | |
705 | ;; mispredicted in which case instruction scheduling will be unlikely to | |
706 | ;; help. | |
707 | (define_bypass 1 "tsv110_*" | |
708 | "tsv110_call,tsv110_branch") |