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bf2a98b3 | 1 | /* Subroutines used for code generation on the DEC Alpha. |
b657e73a | 2 | Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, |
7cf0dbf3 | 3 | 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010 |
292add68 | 4 | Free Software Foundation, Inc. |
0e0a0e7a | 5 | Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) |
bf2a98b3 | 6 | |
187b36cf | 7 | This file is part of GCC. |
bf2a98b3 | 8 | |
187b36cf | 9 | GCC is free software; you can redistribute it and/or modify |
bf2a98b3 | 10 | it under the terms of the GNU General Public License as published by |
038d1e19 | 11 | the Free Software Foundation; either version 3, or (at your option) |
bf2a98b3 | 12 | any later version. |
13 | ||
187b36cf | 14 | GCC is distributed in the hope that it will be useful, |
bf2a98b3 | 15 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License | |
038d1e19 | 20 | along with GCC; see the file COPYING3. If not see |
21 | <http://www.gnu.org/licenses/>. */ | |
bf2a98b3 | 22 | |
23 | ||
bf2a98b3 | 24 | #include "config.h" |
769ea120 | 25 | #include "system.h" |
805e22b2 | 26 | #include "coretypes.h" |
27 | #include "tm.h" | |
bf2a98b3 | 28 | #include "rtl.h" |
d8fc4d0b | 29 | #include "tree.h" |
bf2a98b3 | 30 | #include "regs.h" |
31 | #include "hard-reg-set.h" | |
32 | #include "real.h" | |
33 | #include "insn-config.h" | |
34 | #include "conditions.h" | |
bf2a98b3 | 35 | #include "output.h" |
36 | #include "insn-attr.h" | |
37 | #include "flags.h" | |
38 | #include "recog.h" | |
bf2a98b3 | 39 | #include "expr.h" |
d8fc4d0b | 40 | #include "optabs.h" |
41 | #include "reload.h" | |
bf2a98b3 | 42 | #include "obstack.h" |
0c0464e6 | 43 | #include "except.h" |
44 | #include "function.h" | |
769ea120 | 45 | #include "toplev.h" |
11016d99 | 46 | #include "ggc.h" |
0f37b7a2 | 47 | #include "integrate.h" |
0d50f0b7 | 48 | #include "tm_p.h" |
a767736d | 49 | #include "target.h" |
50 | #include "target-def.h" | |
961d6ddd | 51 | #include "debug.h" |
a1f71e15 | 52 | #include "langhooks.h" |
573aba85 | 53 | #include <splay-tree.h> |
356907d3 | 54 | #include "cfglayout.h" |
75a70cf9 | 55 | #include "gimple.h" |
a6c787e5 | 56 | #include "tree-flow.h" |
57 | #include "tree-stdarg.h" | |
1dffd068 | 58 | #include "tm-constrs.h" |
3072d30e | 59 | #include "df.h" |
2db66e7c | 60 | #include "libfuncs.h" |
0c0464e6 | 61 | |
65abff06 | 62 | /* Specify which cpu to schedule for. */ |
fb64edde | 63 | enum processor_type alpha_tune; |
0c0464e6 | 64 | |
fb64edde | 65 | /* Which cpu we're generating code for. */ |
f141a8b4 | 66 | enum processor_type alpha_cpu; |
fb64edde | 67 | |
9e7454d0 | 68 | static const char * const alpha_cpu_name[] = |
07c1a295 | 69 | { |
70 | "ev4", "ev5", "ev6" | |
71 | }; | |
0c5845b3 | 72 | |
c4622276 | 73 | /* Specify how accurate floating-point traps need to be. */ |
74 | ||
75 | enum alpha_trap_precision alpha_tp; | |
76 | ||
77 | /* Specify the floating-point rounding mode. */ | |
78 | ||
79 | enum alpha_fp_rounding_mode alpha_fprm; | |
80 | ||
81 | /* Specify which things cause traps. */ | |
82 | ||
83 | enum alpha_fp_trap_mode alpha_fptm; | |
84 | ||
e3e08e7f | 85 | /* Nonzero if inside of a function, because the Alpha asm can't |
449b7f2d | 86 | handle .files inside of functions. */ |
87 | ||
88 | static int inside_function = FALSE; | |
89 | ||
07c1a295 | 90 | /* The number of cycles of latency we should assume on memory reads. */ |
91 | ||
92 | int alpha_memory_latency = 3; | |
93 | ||
b9a5aa8e | 94 | /* Whether the function needs the GP. */ |
95 | ||
96 | static int alpha_function_needs_gp; | |
97 | ||
849674a3 | 98 | /* The alias set for prologue/epilogue register save/restore. */ |
99 | ||
32c2fdea | 100 | static GTY(()) alias_set_type alpha_sr_alias_set; |
849674a3 | 101 | |
a314eb5e | 102 | /* The assembler name of the current function. */ |
103 | ||
104 | static const char *alpha_fnname; | |
105 | ||
1f0ce6a6 | 106 | /* The next explicit relocation sequence number. */ |
9de382d9 | 107 | extern GTY(()) int alpha_next_sequence_number; |
1f0ce6a6 | 108 | int alpha_next_sequence_number = 1; |
109 | ||
110 | /* The literal and gpdisp sequence numbers for this insn, as printed | |
111 | by %# and %* respectively. */ | |
9de382d9 | 112 | extern GTY(()) int alpha_this_literal_sequence_number; |
113 | extern GTY(()) int alpha_this_gpdisp_sequence_number; | |
1f0ce6a6 | 114 | int alpha_this_literal_sequence_number; |
115 | int alpha_this_gpdisp_sequence_number; | |
116 | ||
fab7adbf | 117 | /* Costs of various operations on the different architectures. */ |
118 | ||
119 | struct alpha_rtx_cost_data | |
120 | { | |
121 | unsigned char fp_add; | |
122 | unsigned char fp_mult; | |
123 | unsigned char fp_div_sf; | |
124 | unsigned char fp_div_df; | |
125 | unsigned char int_mult_si; | |
126 | unsigned char int_mult_di; | |
127 | unsigned char int_shift; | |
128 | unsigned char int_cmov; | |
d7cf2331 | 129 | unsigned short int_div; |
fab7adbf | 130 | }; |
131 | ||
132 | static struct alpha_rtx_cost_data const alpha_rtx_cost_data[PROCESSOR_MAX] = | |
133 | { | |
134 | { /* EV4 */ | |
135 | COSTS_N_INSNS (6), /* fp_add */ | |
136 | COSTS_N_INSNS (6), /* fp_mult */ | |
137 | COSTS_N_INSNS (34), /* fp_div_sf */ | |
138 | COSTS_N_INSNS (63), /* fp_div_df */ | |
139 | COSTS_N_INSNS (23), /* int_mult_si */ | |
140 | COSTS_N_INSNS (23), /* int_mult_di */ | |
141 | COSTS_N_INSNS (2), /* int_shift */ | |
142 | COSTS_N_INSNS (2), /* int_cmov */ | |
f6777b0a | 143 | COSTS_N_INSNS (97), /* int_div */ |
fab7adbf | 144 | }, |
145 | { /* EV5 */ | |
146 | COSTS_N_INSNS (4), /* fp_add */ | |
147 | COSTS_N_INSNS (4), /* fp_mult */ | |
148 | COSTS_N_INSNS (15), /* fp_div_sf */ | |
149 | COSTS_N_INSNS (22), /* fp_div_df */ | |
150 | COSTS_N_INSNS (8), /* int_mult_si */ | |
151 | COSTS_N_INSNS (12), /* int_mult_di */ | |
152 | COSTS_N_INSNS (1) + 1, /* int_shift */ | |
153 | COSTS_N_INSNS (1), /* int_cmov */ | |
f6777b0a | 154 | COSTS_N_INSNS (83), /* int_div */ |
fab7adbf | 155 | }, |
156 | { /* EV6 */ | |
157 | COSTS_N_INSNS (4), /* fp_add */ | |
158 | COSTS_N_INSNS (4), /* fp_mult */ | |
159 | COSTS_N_INSNS (12), /* fp_div_sf */ | |
160 | COSTS_N_INSNS (15), /* fp_div_df */ | |
161 | COSTS_N_INSNS (7), /* int_mult_si */ | |
162 | COSTS_N_INSNS (7), /* int_mult_di */ | |
163 | COSTS_N_INSNS (1), /* int_shift */ | |
164 | COSTS_N_INSNS (2), /* int_cmov */ | |
f6777b0a | 165 | COSTS_N_INSNS (86), /* int_div */ |
fab7adbf | 166 | }, |
167 | }; | |
168 | ||
d7cf2331 | 169 | /* Similar but tuned for code size instead of execution latency. The |
170 | extra +N is fractional cost tuning based on latency. It's used to | |
171 | encourage use of cheaper insns like shift, but only if there's just | |
172 | one of them. */ | |
173 | ||
174 | static struct alpha_rtx_cost_data const alpha_rtx_cost_size = | |
175 | { | |
176 | COSTS_N_INSNS (1), /* fp_add */ | |
177 | COSTS_N_INSNS (1), /* fp_mult */ | |
178 | COSTS_N_INSNS (1), /* fp_div_sf */ | |
179 | COSTS_N_INSNS (1) + 1, /* fp_div_df */ | |
180 | COSTS_N_INSNS (1) + 1, /* int_mult_si */ | |
181 | COSTS_N_INSNS (1) + 2, /* int_mult_di */ | |
182 | COSTS_N_INSNS (1), /* int_shift */ | |
183 | COSTS_N_INSNS (1), /* int_cmov */ | |
184 | COSTS_N_INSNS (6), /* int_div */ | |
185 | }; | |
186 | ||
0dbd1c74 | 187 | /* Get the number of args of a function in one of two ways. */ |
9caef960 | 188 | #if TARGET_ABI_OPEN_VMS || TARGET_ABI_UNICOSMK |
abe32cce | 189 | #define NUM_ARGS crtl->args.info.num_args |
0dbd1c74 | 190 | #else |
abe32cce | 191 | #define NUM_ARGS crtl->args.info |
0dbd1c74 | 192 | #endif |
d2832bd8 | 193 | |
d2832bd8 | 194 | #define REG_PV 27 |
195 | #define REG_RA 26 | |
f2cc13dc | 196 | |
92643d95 | 197 | /* Declarations of static functions. */ |
198 | static struct machine_function *alpha_init_machine_status (void); | |
8c3428a6 | 199 | static rtx alpha_emit_xfloating_compare (enum rtx_code *, rtx, rtx); |
805e22b2 | 200 | |
92643d95 | 201 | #if TARGET_ABI_OPEN_VMS |
202 | static void alpha_write_linkage (FILE *, const char *, tree); | |
656ad977 | 203 | static bool vms_valid_pointer_mode (enum machine_mode); |
6988553d | 204 | #endif |
205 | ||
92643d95 | 206 | static void unicosmk_output_deferred_case_vectors (FILE *); |
207 | static void unicosmk_gen_dsib (unsigned long *); | |
208 | static void unicosmk_output_ssib (FILE *, const char *); | |
209 | static int unicosmk_need_dex (rtx); | |
a767736d | 210 | \f |
fb64edde | 211 | /* Implement TARGET_HANDLE_OPTION. */ |
212 | ||
213 | static bool | |
214 | alpha_handle_option (size_t code, const char *arg, int value) | |
215 | { | |
216 | switch (code) | |
217 | { | |
218 | case OPT_mfp_regs: | |
219 | if (value == 0) | |
220 | target_flags |= MASK_SOFT_FP; | |
221 | break; | |
222 | ||
223 | case OPT_mieee: | |
224 | case OPT_mieee_with_inexact: | |
225 | target_flags |= MASK_IEEE_CONFORMANT; | |
226 | break; | |
227 | ||
fb64edde | 228 | case OPT_mtls_size_: |
0fe44c73 | 229 | if (value != 16 && value != 32 && value != 64) |
fb64edde | 230 | error ("bad value %qs for -mtls-size switch", arg); |
231 | break; | |
232 | } | |
233 | ||
234 | return true; | |
235 | } | |
236 | ||
4257b08a | 237 | #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING |
eddcdde1 | 238 | /* Implement TARGET_MANGLE_TYPE. */ |
4257b08a | 239 | |
240 | static const char * | |
a9f1838b | 241 | alpha_mangle_type (const_tree type) |
4257b08a | 242 | { |
243 | if (TYPE_MAIN_VARIANT (type) == long_double_type_node | |
244 | && TARGET_LONG_DOUBLE_128) | |
245 | return "g"; | |
246 | ||
247 | /* For all other types, use normal C++ mangling. */ | |
248 | return NULL; | |
249 | } | |
250 | #endif | |
251 | ||
65abff06 | 252 | /* Parse target option strings. */ |
c4622276 | 253 | |
254 | void | |
92643d95 | 255 | override_options (void) |
c4622276 | 256 | { |
e99c3a1d | 257 | static const struct cpu_table { |
258 | const char *const name; | |
259 | const enum processor_type processor; | |
260 | const int flags; | |
27de1488 | 261 | } cpu_table[] = { |
27de1488 | 262 | { "ev4", PROCESSOR_EV4, 0 }, |
263 | { "ev45", PROCESSOR_EV4, 0 }, | |
264 | { "21064", PROCESSOR_EV4, 0 }, | |
fb64edde | 265 | { "ev5", PROCESSOR_EV5, 0 }, |
266 | { "21164", PROCESSOR_EV5, 0 }, | |
267 | { "ev56", PROCESSOR_EV5, MASK_BWX }, | |
268 | { "21164a", PROCESSOR_EV5, MASK_BWX }, | |
269 | { "pca56", PROCESSOR_EV5, MASK_BWX|MASK_MAX }, | |
270 | { "21164PC",PROCESSOR_EV5, MASK_BWX|MASK_MAX }, | |
271 | { "21164pc",PROCESSOR_EV5, MASK_BWX|MASK_MAX }, | |
272 | { "ev6", PROCESSOR_EV6, MASK_BWX|MASK_MAX|MASK_FIX }, | |
273 | { "21264", PROCESSOR_EV6, MASK_BWX|MASK_MAX|MASK_FIX }, | |
274 | { "ev67", PROCESSOR_EV6, MASK_BWX|MASK_MAX|MASK_FIX|MASK_CIX }, | |
afba4ec8 | 275 | { "21264a", PROCESSOR_EV6, MASK_BWX|MASK_MAX|MASK_FIX|MASK_CIX } |
27de1488 | 276 | }; |
9e7454d0 | 277 | |
afba4ec8 | 278 | int const ct_size = ARRAY_SIZE (cpu_table); |
fb64edde | 279 | int i; |
280 | ||
9caef960 | 281 | /* Unicos/Mk doesn't have shared libraries. */ |
282 | if (TARGET_ABI_UNICOSMK && flag_pic) | |
283 | { | |
c3ceba8e | 284 | warning (0, "-f%s ignored for Unicos/Mk (not supported)", |
9caef960 | 285 | (flag_pic > 1) ? "PIC" : "pic"); |
286 | flag_pic = 0; | |
287 | } | |
288 | ||
9e7454d0 | 289 | /* On Unicos/Mk, the native compiler consistently generates /d suffices for |
9caef960 | 290 | floating-point instructions. Make that the default for this target. */ |
291 | if (TARGET_ABI_UNICOSMK) | |
292 | alpha_fprm = ALPHA_FPRM_DYN; | |
293 | else | |
294 | alpha_fprm = ALPHA_FPRM_NORM; | |
295 | ||
c4622276 | 296 | alpha_tp = ALPHA_TP_PROG; |
c4622276 | 297 | alpha_fptm = ALPHA_FPTM_N; |
298 | ||
9e7454d0 | 299 | /* We cannot use su and sui qualifiers for conversion instructions on |
9caef960 | 300 | Unicos/Mk. I'm not sure if this is due to assembler or hardware |
301 | limitations. Right now, we issue a warning if -mieee is specified | |
302 | and then ignore it; eventually, we should either get it right or | |
303 | disable the option altogether. */ | |
304 | ||
c4622276 | 305 | if (TARGET_IEEE) |
306 | { | |
9caef960 | 307 | if (TARGET_ABI_UNICOSMK) |
c3ceba8e | 308 | warning (0, "-mieee not supported on Unicos/Mk"); |
9caef960 | 309 | else |
310 | { | |
311 | alpha_tp = ALPHA_TP_INSN; | |
312 | alpha_fptm = ALPHA_FPTM_SU; | |
313 | } | |
c4622276 | 314 | } |
315 | ||
316 | if (TARGET_IEEE_WITH_INEXACT) | |
317 | { | |
9caef960 | 318 | if (TARGET_ABI_UNICOSMK) |
c3ceba8e | 319 | warning (0, "-mieee-with-inexact not supported on Unicos/Mk"); |
9caef960 | 320 | else |
321 | { | |
322 | alpha_tp = ALPHA_TP_INSN; | |
323 | alpha_fptm = ALPHA_FPTM_SUI; | |
324 | } | |
c4622276 | 325 | } |
326 | ||
327 | if (alpha_tp_string) | |
264f7d8c | 328 | { |
329 | if (! strcmp (alpha_tp_string, "p")) | |
c4622276 | 330 | alpha_tp = ALPHA_TP_PROG; |
264f7d8c | 331 | else if (! strcmp (alpha_tp_string, "f")) |
c4622276 | 332 | alpha_tp = ALPHA_TP_FUNC; |
264f7d8c | 333 | else if (! strcmp (alpha_tp_string, "i")) |
c4622276 | 334 | alpha_tp = ALPHA_TP_INSN; |
264f7d8c | 335 | else |
1e5fcbe2 | 336 | error ("bad value %qs for -mtrap-precision switch", alpha_tp_string); |
264f7d8c | 337 | } |
c4622276 | 338 | |
339 | if (alpha_fprm_string) | |
264f7d8c | 340 | { |
341 | if (! strcmp (alpha_fprm_string, "n")) | |
c4622276 | 342 | alpha_fprm = ALPHA_FPRM_NORM; |
264f7d8c | 343 | else if (! strcmp (alpha_fprm_string, "m")) |
c4622276 | 344 | alpha_fprm = ALPHA_FPRM_MINF; |
264f7d8c | 345 | else if (! strcmp (alpha_fprm_string, "c")) |
c4622276 | 346 | alpha_fprm = ALPHA_FPRM_CHOP; |
264f7d8c | 347 | else if (! strcmp (alpha_fprm_string,"d")) |
c4622276 | 348 | alpha_fprm = ALPHA_FPRM_DYN; |
264f7d8c | 349 | else |
1e5fcbe2 | 350 | error ("bad value %qs for -mfp-rounding-mode switch", |
c4622276 | 351 | alpha_fprm_string); |
264f7d8c | 352 | } |
c4622276 | 353 | |
354 | if (alpha_fptm_string) | |
264f7d8c | 355 | { |
356 | if (strcmp (alpha_fptm_string, "n") == 0) | |
357 | alpha_fptm = ALPHA_FPTM_N; | |
358 | else if (strcmp (alpha_fptm_string, "u") == 0) | |
359 | alpha_fptm = ALPHA_FPTM_U; | |
360 | else if (strcmp (alpha_fptm_string, "su") == 0) | |
361 | alpha_fptm = ALPHA_FPTM_SU; | |
362 | else if (strcmp (alpha_fptm_string, "sui") == 0) | |
363 | alpha_fptm = ALPHA_FPTM_SUI; | |
364 | else | |
1e5fcbe2 | 365 | error ("bad value %qs for -mfp-trap-mode switch", alpha_fptm_string); |
264f7d8c | 366 | } |
c4622276 | 367 | |
cbd8ec27 | 368 | if (alpha_cpu_string) |
369 | { | |
afba4ec8 | 370 | for (i = 0; i < ct_size; i++) |
27de1488 | 371 | if (! strcmp (alpha_cpu_string, cpu_table [i].name)) |
372 | { | |
fb64edde | 373 | alpha_tune = alpha_cpu = cpu_table [i].processor; |
374 | target_flags &= ~ (MASK_BWX | MASK_MAX | MASK_FIX | MASK_CIX); | |
27de1488 | 375 | target_flags |= cpu_table [i].flags; |
376 | break; | |
377 | } | |
afba4ec8 | 378 | if (i == ct_size) |
1e5fcbe2 | 379 | error ("bad value %qs for -mcpu switch", alpha_cpu_string); |
cbd8ec27 | 380 | } |
381 | ||
27de1488 | 382 | if (alpha_tune_string) |
383 | { | |
afba4ec8 | 384 | for (i = 0; i < ct_size; i++) |
27de1488 | 385 | if (! strcmp (alpha_tune_string, cpu_table [i].name)) |
386 | { | |
fb64edde | 387 | alpha_tune = cpu_table [i].processor; |
27de1488 | 388 | break; |
389 | } | |
afba4ec8 | 390 | if (i == ct_size) |
89b3c92a | 391 | error ("bad value %qs for -mtune switch", alpha_tune_string); |
27de1488 | 392 | } |
393 | ||
65abff06 | 394 | /* Do some sanity checks on the above options. */ |
c4622276 | 395 | |
9caef960 | 396 | if (TARGET_ABI_UNICOSMK && alpha_fptm != ALPHA_FPTM_N) |
397 | { | |
c3ceba8e | 398 | warning (0, "trap mode not supported on Unicos/Mk"); |
9caef960 | 399 | alpha_fptm = ALPHA_FPTM_N; |
400 | } | |
401 | ||
264f7d8c | 402 | if ((alpha_fptm == ALPHA_FPTM_SU || alpha_fptm == ALPHA_FPTM_SUI) |
fb64edde | 403 | && alpha_tp != ALPHA_TP_INSN && alpha_cpu != PROCESSOR_EV6) |
c4622276 | 404 | { |
c3ceba8e | 405 | warning (0, "fp software completion requires -mtrap-precision=i"); |
c4622276 | 406 | alpha_tp = ALPHA_TP_INSN; |
407 | } | |
8df4a58b | 408 | |
fb64edde | 409 | if (alpha_cpu == PROCESSOR_EV6) |
bc16f0c1 | 410 | { |
411 | /* Except for EV6 pass 1 (not released), we always have precise | |
412 | arithmetic traps. Which means we can do software completion | |
413 | without minding trap shadows. */ | |
414 | alpha_tp = ALPHA_TP_PROG; | |
415 | } | |
416 | ||
8df4a58b | 417 | if (TARGET_FLOAT_VAX) |
418 | { | |
419 | if (alpha_fprm == ALPHA_FPRM_MINF || alpha_fprm == ALPHA_FPRM_DYN) | |
420 | { | |
c3ceba8e | 421 | warning (0, "rounding mode not supported for VAX floats"); |
8df4a58b | 422 | alpha_fprm = ALPHA_FPRM_NORM; |
423 | } | |
424 | if (alpha_fptm == ALPHA_FPTM_SUI) | |
425 | { | |
c3ceba8e | 426 | warning (0, "trap mode not supported for VAX floats"); |
8df4a58b | 427 | alpha_fptm = ALPHA_FPTM_SU; |
428 | } | |
ef76af46 | 429 | if (target_flags_explicit & MASK_LONG_DOUBLE_128) |
c3ceba8e | 430 | warning (0, "128-bit long double not supported for VAX floats"); |
ef76af46 | 431 | target_flags &= ~MASK_LONG_DOUBLE_128; |
8df4a58b | 432 | } |
07c1a295 | 433 | |
434 | { | |
435 | char *end; | |
436 | int lat; | |
437 | ||
438 | if (!alpha_mlat_string) | |
439 | alpha_mlat_string = "L1"; | |
440 | ||
14184418 | 441 | if (ISDIGIT ((unsigned char)alpha_mlat_string[0]) |
07c1a295 | 442 | && (lat = strtol (alpha_mlat_string, &end, 10), *end == '\0')) |
443 | ; | |
444 | else if ((alpha_mlat_string[0] == 'L' || alpha_mlat_string[0] == 'l') | |
14184418 | 445 | && ISDIGIT ((unsigned char)alpha_mlat_string[1]) |
07c1a295 | 446 | && alpha_mlat_string[2] == '\0') |
447 | { | |
9e7454d0 | 448 | static int const cache_latency[][4] = |
07c1a295 | 449 | { |
450 | { 3, 30, -1 }, /* ev4 -- Bcache is a guess */ | |
451 | { 2, 12, 38 }, /* ev5 -- Bcache from PC164 LMbench numbers */ | |
65abff06 | 452 | { 3, 12, 30 }, /* ev6 -- Bcache from DS20 LMbench. */ |
07c1a295 | 453 | }; |
454 | ||
455 | lat = alpha_mlat_string[1] - '0'; | |
fb64edde | 456 | if (lat <= 0 || lat > 3 || cache_latency[alpha_tune][lat-1] == -1) |
07c1a295 | 457 | { |
c3ceba8e | 458 | warning (0, "L%d cache latency unknown for %s", |
fb64edde | 459 | lat, alpha_cpu_name[alpha_tune]); |
07c1a295 | 460 | lat = 3; |
461 | } | |
462 | else | |
fb64edde | 463 | lat = cache_latency[alpha_tune][lat-1]; |
07c1a295 | 464 | } |
465 | else if (! strcmp (alpha_mlat_string, "main")) | |
466 | { | |
467 | /* Most current memories have about 370ns latency. This is | |
468 | a reasonable guess for a fast cpu. */ | |
469 | lat = 150; | |
470 | } | |
471 | else | |
472 | { | |
c3ceba8e | 473 | warning (0, "bad value %qs for -mmemory-latency", alpha_mlat_string); |
07c1a295 | 474 | lat = 3; |
475 | } | |
476 | ||
477 | alpha_memory_latency = lat; | |
478 | } | |
a9fa9190 | 479 | |
480 | /* Default the definition of "small data" to 8 bytes. */ | |
481 | if (!g_switch_set) | |
482 | g_switch_value = 8; | |
849674a3 | 483 | |
5dcb037d | 484 | /* Infer TARGET_SMALL_DATA from -fpic/-fPIC. */ |
485 | if (flag_pic == 1) | |
486 | target_flags |= MASK_SMALL_DATA; | |
487 | else if (flag_pic == 2) | |
488 | target_flags &= ~MASK_SMALL_DATA; | |
489 | ||
0ea5169b | 490 | /* Align labels and loops for optimal branching. */ |
491 | /* ??? Kludge these by not doing anything if we don't optimize and also if | |
65abff06 | 492 | we are writing ECOFF symbols to work around a bug in DEC's assembler. */ |
0ea5169b | 493 | if (optimize > 0 && write_symbols != SDB_DEBUG) |
494 | { | |
495 | if (align_loops <= 0) | |
496 | align_loops = 16; | |
497 | if (align_jumps <= 0) | |
498 | align_jumps = 16; | |
499 | } | |
500 | if (align_functions <= 0) | |
501 | align_functions = 16; | |
502 | ||
849674a3 | 503 | /* Acquire a unique set number for our register saves and restores. */ |
504 | alpha_sr_alias_set = new_alias_set (); | |
9caef960 | 505 | |
506 | /* Register variables and functions with the garbage collector. */ | |
507 | ||
9caef960 | 508 | /* Set up function hooks. */ |
509 | init_machine_status = alpha_init_machine_status; | |
1268285a | 510 | |
511 | /* Tell the compiler when we're using VAX floating point. */ | |
512 | if (TARGET_FLOAT_VAX) | |
513 | { | |
0021bea9 | 514 | REAL_MODE_FORMAT (SFmode) = &vax_f_format; |
515 | REAL_MODE_FORMAT (DFmode) = &vax_g_format; | |
516 | REAL_MODE_FORMAT (TFmode) = NULL; | |
1268285a | 517 | } |
2dde0cc6 | 518 | |
519 | #ifdef TARGET_DEFAULT_LONG_DOUBLE_128 | |
520 | if (!(target_flags_explicit & MASK_LONG_DOUBLE_128)) | |
521 | target_flags |= MASK_LONG_DOUBLE_128; | |
522 | #endif | |
8a58ed0a | 523 | |
524 | /* If using typedef char *va_list, signal that __builtin_va_start (&ap, 0) | |
525 | can be optimized to ap = __builtin_next_arg (0). */ | |
526 | if (TARGET_ABI_UNICOSMK) | |
527 | targetm.expand_builtin_va_start = NULL; | |
c4622276 | 528 | } |
529 | \f | |
bf2a98b3 | 530 | /* Returns 1 if VALUE is a mask that contains full bytes of zero or ones. */ |
531 | ||
532 | int | |
92643d95 | 533 | zap_mask (HOST_WIDE_INT value) |
bf2a98b3 | 534 | { |
535 | int i; | |
536 | ||
537 | for (i = 0; i < HOST_BITS_PER_WIDE_INT / HOST_BITS_PER_CHAR; | |
538 | i++, value >>= 8) | |
539 | if ((value & 0xff) != 0 && (value & 0xff) != 0xff) | |
540 | return 0; | |
541 | ||
542 | return 1; | |
543 | } | |
544 | ||
9e7454d0 | 545 | /* Return true if OP is valid for a particular TLS relocation. |
41421c64 | 546 | We are already guaranteed that OP is a CONST. */ |
bf2a98b3 | 547 | |
548 | int | |
41421c64 | 549 | tls_symbolic_operand_1 (rtx op, int size, int unspec) |
bf2a98b3 | 550 | { |
5f7b9df8 | 551 | op = XEXP (op, 0); |
552 | ||
553 | if (GET_CODE (op) != UNSPEC || XINT (op, 1) != unspec) | |
554 | return 0; | |
555 | op = XVECEXP (op, 0, 0); | |
556 | ||
557 | if (GET_CODE (op) != SYMBOL_REF) | |
558 | return 0; | |
5f7b9df8 | 559 | |
09a1f342 | 560 | switch (SYMBOL_REF_TLS_MODEL (op)) |
9bdcc1e5 | 561 | { |
09a1f342 | 562 | case TLS_MODEL_LOCAL_DYNAMIC: |
ea284d73 | 563 | return unspec == UNSPEC_DTPREL && size == alpha_tls_size; |
09a1f342 | 564 | case TLS_MODEL_INITIAL_EXEC: |
9bdcc1e5 | 565 | return unspec == UNSPEC_TPREL && size == 64; |
09a1f342 | 566 | case TLS_MODEL_LOCAL_EXEC: |
ea284d73 | 567 | return unspec == UNSPEC_TPREL && size == alpha_tls_size; |
9bdcc1e5 | 568 | default: |
4d10b463 | 569 | gcc_unreachable (); |
9bdcc1e5 | 570 | } |
5f7b9df8 | 571 | } |
572 | ||
41421c64 | 573 | /* Used by aligned_memory_operand and unaligned_memory_operand to |
574 | resolve what reload is going to do with OP if it's a register. */ | |
bbf31a61 | 575 | |
41421c64 | 576 | rtx |
577 | resolve_reload_operand (rtx op) | |
bf2a98b3 | 578 | { |
cc215844 | 579 | if (reload_in_progress) |
bf2a98b3 | 580 | { |
cc215844 | 581 | rtx tmp = op; |
582 | if (GET_CODE (tmp) == SUBREG) | |
583 | tmp = SUBREG_REG (tmp); | |
c933fb42 | 584 | if (REG_P (tmp) |
cc215844 | 585 | && REGNO (tmp) >= FIRST_PSEUDO_REGISTER) |
586 | { | |
587 | op = reg_equiv_memory_loc[REGNO (tmp)]; | |
588 | if (op == 0) | |
589 | return 0; | |
590 | } | |
bf2a98b3 | 591 | } |
41421c64 | 592 | return op; |
14f7bc98 | 593 | } |
594 | ||
b2aef146 | 595 | /* The scalar modes supported differs from the default check-what-c-supports |
596 | version in that sometimes TFmode is available even when long double | |
597 | indicates only DFmode. On unicosmk, we have the situation that HImode | |
598 | doesn't map to any C type, but of course we still support that. */ | |
599 | ||
600 | static bool | |
601 | alpha_scalar_mode_supported_p (enum machine_mode mode) | |
602 | { | |
603 | switch (mode) | |
604 | { | |
605 | case QImode: | |
606 | case HImode: | |
607 | case SImode: | |
608 | case DImode: | |
609 | case TImode: /* via optabs.c */ | |
610 | return true; | |
611 | ||
612 | case SFmode: | |
613 | case DFmode: | |
614 | return true; | |
615 | ||
616 | case TFmode: | |
617 | return TARGET_HAS_XFLOATING_LIBS; | |
618 | ||
619 | default: | |
620 | return false; | |
621 | } | |
622 | } | |
623 | ||
624 | /* Alpha implements a couple of integer vector mode operations when | |
b739144f | 625 | TARGET_MAX is enabled. We do not check TARGET_MAX here, however, |
626 | which allows the vectorizer to operate on e.g. move instructions, | |
627 | or when expand_vector_operations can do something useful. */ | |
b2aef146 | 628 | |
9e7454d0 | 629 | static bool |
630 | alpha_vector_mode_supported_p (enum machine_mode mode) | |
631 | { | |
b739144f | 632 | return mode == V8QImode || mode == V4HImode || mode == V2SImode; |
9e7454d0 | 633 | } |
634 | ||
550e415f | 635 | /* Return 1 if this function can directly return via $26. */ |
636 | ||
637 | int | |
92643d95 | 638 | direct_return (void) |
550e415f | 639 | { |
9caef960 | 640 | return (! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK |
1467e953 | 641 | && reload_completed |
642 | && alpha_sa_size () == 0 | |
550e415f | 643 | && get_frame_size () == 0 |
abe32cce | 644 | && crtl->outgoing_args_size == 0 |
645 | && crtl->args.pretend_args_size == 0); | |
550e415f | 646 | } |
ecb98d40 | 647 | |
648 | /* Return the ADDR_VEC associated with a tablejump insn. */ | |
649 | ||
650 | rtx | |
92643d95 | 651 | alpha_tablejump_addr_vec (rtx insn) |
ecb98d40 | 652 | { |
653 | rtx tmp; | |
654 | ||
655 | tmp = JUMP_LABEL (insn); | |
656 | if (!tmp) | |
657 | return NULL_RTX; | |
658 | tmp = NEXT_INSN (tmp); | |
659 | if (!tmp) | |
660 | return NULL_RTX; | |
c933fb42 | 661 | if (JUMP_P (tmp) |
ecb98d40 | 662 | && GET_CODE (PATTERN (tmp)) == ADDR_DIFF_VEC) |
663 | return PATTERN (tmp); | |
664 | return NULL_RTX; | |
665 | } | |
666 | ||
667 | /* Return the label of the predicted edge, or CONST0_RTX if we don't know. */ | |
668 | ||
669 | rtx | |
92643d95 | 670 | alpha_tablejump_best_label (rtx insn) |
ecb98d40 | 671 | { |
672 | rtx jump_table = alpha_tablejump_addr_vec (insn); | |
673 | rtx best_label = NULL_RTX; | |
674 | ||
675 | /* ??? Once the CFG doesn't keep getting completely rebuilt, look | |
676 | there for edge frequency counts from profile data. */ | |
677 | ||
678 | if (jump_table) | |
679 | { | |
680 | int n_labels = XVECLEN (jump_table, 1); | |
681 | int best_count = -1; | |
682 | int i, j; | |
683 | ||
684 | for (i = 0; i < n_labels; i++) | |
685 | { | |
686 | int count = 1; | |
687 | ||
688 | for (j = i + 1; j < n_labels; j++) | |
689 | if (XEXP (XVECEXP (jump_table, 1, i), 0) | |
690 | == XEXP (XVECEXP (jump_table, 1, j), 0)) | |
691 | count++; | |
692 | ||
693 | if (count > best_count) | |
694 | best_count = count, best_label = XVECEXP (jump_table, 1, i); | |
695 | } | |
696 | } | |
697 | ||
698 | return best_label ? best_label : const0_rtx; | |
699 | } | |
5f7b9df8 | 700 | |
701 | /* Return the TLS model to use for SYMBOL. */ | |
702 | ||
703 | static enum tls_model | |
92643d95 | 704 | tls_symbolic_operand_type (rtx symbol) |
5f7b9df8 | 705 | { |
09a1f342 | 706 | enum tls_model model; |
5f7b9df8 | 707 | |
708 | if (GET_CODE (symbol) != SYMBOL_REF) | |
afba4ec8 | 709 | return TLS_MODEL_NONE; |
09a1f342 | 710 | model = SYMBOL_REF_TLS_MODEL (symbol); |
5f7b9df8 | 711 | |
09a1f342 | 712 | /* Local-exec with a 64-bit size is the same code as initial-exec. */ |
713 | if (model == TLS_MODEL_LOCAL_EXEC && alpha_tls_size == 64) | |
714 | model = TLS_MODEL_INITIAL_EXEC; | |
5f7b9df8 | 715 | |
09a1f342 | 716 | return model; |
5f7b9df8 | 717 | } |
14f7bc98 | 718 | \f |
9bdcc1e5 | 719 | /* Return true if the function DECL will share the same GP as any |
720 | function in the current unit of translation. */ | |
721 | ||
722 | static bool | |
a9f1838b | 723 | decl_has_samegp (const_tree decl) |
9bdcc1e5 | 724 | { |
725 | /* Functions that are not local can be overridden, and thus may | |
726 | not share the same gp. */ | |
727 | if (!(*targetm.binds_local_p) (decl)) | |
728 | return false; | |
729 | ||
730 | /* If -msmall-data is in effect, assume that there is only one GP | |
731 | for the module, and so any local symbol has this property. We | |
732 | need explicit relocations to be able to enforce this for symbols | |
733 | not defined in this unit of translation, however. */ | |
734 | if (TARGET_EXPLICIT_RELOCS && TARGET_SMALL_DATA) | |
735 | return true; | |
736 | ||
737 | /* Functions that are not external are defined in this UoT. */ | |
cf1d67e3 | 738 | /* ??? Irritatingly, static functions not yet emitted are still |
739 | marked "external". Apply this to non-static functions only. */ | |
740 | return !TREE_PUBLIC (decl) || !DECL_EXTERNAL (decl); | |
9bdcc1e5 | 741 | } |
742 | ||
52470889 | 743 | /* Return true if EXP should be placed in the small data section. */ |
744 | ||
745 | static bool | |
a9f1838b | 746 | alpha_in_small_data_p (const_tree exp) |
52470889 | 747 | { |
0aad4cd2 | 748 | /* We want to merge strings, so we never consider them small data. */ |
749 | if (TREE_CODE (exp) == STRING_CST) | |
750 | return false; | |
751 | ||
6ac09a46 | 752 | /* Functions are never in the small data area. Duh. */ |
753 | if (TREE_CODE (exp) == FUNCTION_DECL) | |
754 | return false; | |
755 | ||
52470889 | 756 | if (TREE_CODE (exp) == VAR_DECL && DECL_SECTION_NAME (exp)) |
757 | { | |
758 | const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (exp)); | |
759 | if (strcmp (section, ".sdata") == 0 | |
760 | || strcmp (section, ".sbss") == 0) | |
761 | return true; | |
762 | } | |
763 | else | |
764 | { | |
765 | HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (exp)); | |
766 | ||
767 | /* If this is an incomplete type with size 0, then we can't put it | |
768 | in sdata because it might be too big when completed. */ | |
3be2f219 | 769 | if (size > 0 && (unsigned HOST_WIDE_INT) size <= g_switch_value) |
52470889 | 770 | return true; |
771 | } | |
772 | ||
773 | return false; | |
774 | } | |
775 | ||
cf73d31f | 776 | #if TARGET_ABI_OPEN_VMS |
656ad977 | 777 | static bool |
778 | vms_valid_pointer_mode (enum machine_mode mode) | |
779 | { | |
780 | return (mode == SImode || mode == DImode); | |
781 | } | |
782 | ||
cf73d31f | 783 | static bool |
92643d95 | 784 | alpha_linkage_symbol_p (const char *symname) |
cf73d31f | 785 | { |
786 | int symlen = strlen (symname); | |
787 | ||
788 | if (symlen > 4) | |
789 | return strcmp (&symname [symlen - 4], "..lk") == 0; | |
790 | ||
791 | return false; | |
792 | } | |
793 | ||
794 | #define LINKAGE_SYMBOL_REF_P(X) \ | |
795 | ((GET_CODE (X) == SYMBOL_REF \ | |
796 | && alpha_linkage_symbol_p (XSTR (X, 0))) \ | |
797 | || (GET_CODE (X) == CONST \ | |
798 | && GET_CODE (XEXP (X, 0)) == PLUS \ | |
799 | && GET_CODE (XEXP (XEXP (X, 0), 0)) == SYMBOL_REF \ | |
800 | && alpha_linkage_symbol_p (XSTR (XEXP (XEXP (X, 0), 0), 0)))) | |
801 | #endif | |
802 | ||
24b3c0ed | 803 | /* legitimate_address_p recognizes an RTL expression that is a valid |
804 | memory address for an instruction. The MODE argument is the | |
805 | machine mode for the MEM expression that wants to use this address. | |
806 | ||
807 | For Alpha, we have either a constant address or the sum of a | |
808 | register and a constant address, or just a register. For DImode, | |
809 | any of those forms can be surrounded with an AND that clear the | |
810 | low-order three bits; this is an "unaligned" access. */ | |
811 | ||
fd50b071 | 812 | static bool |
813 | alpha_legitimate_address_p (enum machine_mode mode, rtx x, bool strict) | |
24b3c0ed | 814 | { |
815 | /* If this is an ldq_u type address, discard the outer AND. */ | |
816 | if (mode == DImode | |
817 | && GET_CODE (x) == AND | |
c933fb42 | 818 | && CONST_INT_P (XEXP (x, 1)) |
24b3c0ed | 819 | && INTVAL (XEXP (x, 1)) == -8) |
820 | x = XEXP (x, 0); | |
821 | ||
822 | /* Discard non-paradoxical subregs. */ | |
823 | if (GET_CODE (x) == SUBREG | |
824 | && (GET_MODE_SIZE (GET_MODE (x)) | |
825 | < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))) | |
826 | x = SUBREG_REG (x); | |
827 | ||
828 | /* Unadorned general registers are valid. */ | |
829 | if (REG_P (x) | |
830 | && (strict | |
831 | ? STRICT_REG_OK_FOR_BASE_P (x) | |
832 | : NONSTRICT_REG_OK_FOR_BASE_P (x))) | |
833 | return true; | |
834 | ||
835 | /* Constant addresses (i.e. +/- 32k) are valid. */ | |
836 | if (CONSTANT_ADDRESS_P (x)) | |
837 | return true; | |
838 | ||
cf73d31f | 839 | #if TARGET_ABI_OPEN_VMS |
840 | if (LINKAGE_SYMBOL_REF_P (x)) | |
841 | return true; | |
842 | #endif | |
843 | ||
24b3c0ed | 844 | /* Register plus a small constant offset is valid. */ |
845 | if (GET_CODE (x) == PLUS) | |
846 | { | |
847 | rtx ofs = XEXP (x, 1); | |
848 | x = XEXP (x, 0); | |
849 | ||
850 | /* Discard non-paradoxical subregs. */ | |
851 | if (GET_CODE (x) == SUBREG | |
852 | && (GET_MODE_SIZE (GET_MODE (x)) | |
853 | < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))) | |
854 | x = SUBREG_REG (x); | |
855 | ||
856 | if (REG_P (x)) | |
857 | { | |
858 | if (! strict | |
859 | && NONSTRICT_REG_OK_FP_BASE_P (x) | |
c933fb42 | 860 | && CONST_INT_P (ofs)) |
24b3c0ed | 861 | return true; |
862 | if ((strict | |
863 | ? STRICT_REG_OK_FOR_BASE_P (x) | |
864 | : NONSTRICT_REG_OK_FOR_BASE_P (x)) | |
865 | && CONSTANT_ADDRESS_P (ofs)) | |
866 | return true; | |
867 | } | |
24b3c0ed | 868 | } |
869 | ||
d6c48eee | 870 | /* If we're managing explicit relocations, LO_SUM is valid, as are small |
871 | data symbols. Avoid explicit relocations of modes larger than word | |
872 | mode since i.e. $LC0+8($1) can fold around +/- 32k offset. */ | |
873 | else if (TARGET_EXPLICIT_RELOCS | |
874 | && GET_MODE_SIZE (mode) <= UNITS_PER_WORD) | |
1f0ce6a6 | 875 | { |
f5a60074 | 876 | if (small_symbolic_operand (x, Pmode)) |
1f0ce6a6 | 877 | return true; |
f5a60074 | 878 | |
879 | if (GET_CODE (x) == LO_SUM) | |
880 | { | |
881 | rtx ofs = XEXP (x, 1); | |
882 | x = XEXP (x, 0); | |
883 | ||
884 | /* Discard non-paradoxical subregs. */ | |
885 | if (GET_CODE (x) == SUBREG | |
886 | && (GET_MODE_SIZE (GET_MODE (x)) | |
887 | < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))) | |
888 | x = SUBREG_REG (x); | |
889 | ||
890 | /* Must have a valid base register. */ | |
891 | if (! (REG_P (x) | |
892 | && (strict | |
893 | ? STRICT_REG_OK_FOR_BASE_P (x) | |
894 | : NONSTRICT_REG_OK_FOR_BASE_P (x)))) | |
895 | return false; | |
896 | ||
897 | /* The symbol must be local. */ | |
5f7b9df8 | 898 | if (local_symbolic_operand (ofs, Pmode) |
899 | || dtp32_symbolic_operand (ofs, Pmode) | |
900 | || tp32_symbolic_operand (ofs, Pmode)) | |
f5a60074 | 901 | return true; |
902 | } | |
1f0ce6a6 | 903 | } |
904 | ||
24b3c0ed | 905 | return false; |
906 | } | |
907 | ||
09a1f342 | 908 | /* Build the SYMBOL_REF for __tls_get_addr. */ |
909 | ||
910 | static GTY(()) rtx tls_get_addr_libfunc; | |
911 | ||
912 | static rtx | |
92643d95 | 913 | get_tls_get_addr (void) |
09a1f342 | 914 | { |
915 | if (!tls_get_addr_libfunc) | |
916 | tls_get_addr_libfunc = init_one_libfunc ("__tls_get_addr"); | |
917 | return tls_get_addr_libfunc; | |
918 | } | |
919 | ||
0d50f0b7 | 920 | /* Try machine-dependent ways of modifying an illegitimate address |
921 | to be legitimate. If we find one, return the new, valid address. */ | |
922 | ||
41e3a0c7 | 923 | static rtx |
924 | alpha_legitimize_address_1 (rtx x, rtx scratch, enum machine_mode mode) | |
0d50f0b7 | 925 | { |
926 | HOST_WIDE_INT addend; | |
927 | ||
928 | /* If the address is (plus reg const_int) and the CONST_INT is not a | |
929 | valid offset, compute the high part of the constant and add it to | |
930 | the register. Then our address is (plus temp low-part-const). */ | |
931 | if (GET_CODE (x) == PLUS | |
c933fb42 | 932 | && REG_P (XEXP (x, 0)) |
933 | && CONST_INT_P (XEXP (x, 1)) | |
0d50f0b7 | 934 | && ! CONSTANT_ADDRESS_P (XEXP (x, 1))) |
935 | { | |
936 | addend = INTVAL (XEXP (x, 1)); | |
937 | x = XEXP (x, 0); | |
938 | goto split_addend; | |
939 | } | |
940 | ||
941 | /* If the address is (const (plus FOO const_int)), find the low-order | |
942 | part of the CONST_INT. Then load FOO plus any high-order part of the | |
943 | CONST_INT into a register. Our address is (plus reg low-part-const). | |
944 | This is done to reduce the number of GOT entries. */ | |
e1ba4a27 | 945 | if (can_create_pseudo_p () |
f5a60074 | 946 | && GET_CODE (x) == CONST |
0d50f0b7 | 947 | && GET_CODE (XEXP (x, 0)) == PLUS |
c933fb42 | 948 | && CONST_INT_P (XEXP (XEXP (x, 0), 1))) |
0d50f0b7 | 949 | { |
950 | addend = INTVAL (XEXP (XEXP (x, 0), 1)); | |
951 | x = force_reg (Pmode, XEXP (XEXP (x, 0), 0)); | |
952 | goto split_addend; | |
953 | } | |
954 | ||
955 | /* If we have a (plus reg const), emit the load as in (2), then add | |
956 | the two registers, and finally generate (plus reg low-part-const) as | |
957 | our address. */ | |
e1ba4a27 | 958 | if (can_create_pseudo_p () |
f5a60074 | 959 | && GET_CODE (x) == PLUS |
c933fb42 | 960 | && REG_P (XEXP (x, 0)) |
0d50f0b7 | 961 | && GET_CODE (XEXP (x, 1)) == CONST |
962 | && GET_CODE (XEXP (XEXP (x, 1), 0)) == PLUS | |
c933fb42 | 963 | && CONST_INT_P (XEXP (XEXP (XEXP (x, 1), 0), 1))) |
0d50f0b7 | 964 | { |
965 | addend = INTVAL (XEXP (XEXP (XEXP (x, 1), 0), 1)); | |
966 | x = expand_simple_binop (Pmode, PLUS, XEXP (x, 0), | |
967 | XEXP (XEXP (XEXP (x, 1), 0), 0), | |
968 | NULL_RTX, 1, OPTAB_LIB_WIDEN); | |
969 | goto split_addend; | |
970 | } | |
971 | ||
d6c48eee | 972 | /* If this is a local symbol, split the address into HIGH/LO_SUM parts. |
973 | Avoid modes larger than word mode since i.e. $LC0+8($1) can fold | |
974 | around +/- 32k offset. */ | |
975 | if (TARGET_EXPLICIT_RELOCS | |
976 | && GET_MODE_SIZE (mode) <= UNITS_PER_WORD | |
977 | && symbolic_operand (x, Pmode)) | |
1f0ce6a6 | 978 | { |
5f7b9df8 | 979 | rtx r0, r16, eqv, tga, tp, insn, dest, seq; |
980 | ||
981 | switch (tls_symbolic_operand_type (x)) | |
982 | { | |
dda53cd5 | 983 | case TLS_MODEL_NONE: |
984 | break; | |
985 | ||
5f7b9df8 | 986 | case TLS_MODEL_GLOBAL_DYNAMIC: |
987 | start_sequence (); | |
988 | ||
989 | r0 = gen_rtx_REG (Pmode, 0); | |
990 | r16 = gen_rtx_REG (Pmode, 16); | |
09a1f342 | 991 | tga = get_tls_get_addr (); |
5f7b9df8 | 992 | dest = gen_reg_rtx (Pmode); |
993 | seq = GEN_INT (alpha_next_sequence_number++); | |
9e7454d0 | 994 | |
5f7b9df8 | 995 | emit_insn (gen_movdi_er_tlsgd (r16, pic_offset_table_rtx, x, seq)); |
996 | insn = gen_call_value_osf_tlsgd (r0, tga, seq); | |
997 | insn = emit_call_insn (insn); | |
9c2a0c05 | 998 | RTL_CONST_CALL_P (insn) = 1; |
5f7b9df8 | 999 | use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r16); |
1000 | ||
1001 | insn = get_insns (); | |
1002 | end_sequence (); | |
1003 | ||
1004 | emit_libcall_block (insn, dest, r0, x); | |
1005 | return dest; | |
1006 | ||
1007 | case TLS_MODEL_LOCAL_DYNAMIC: | |
1008 | start_sequence (); | |
1009 | ||
1010 | r0 = gen_rtx_REG (Pmode, 0); | |
1011 | r16 = gen_rtx_REG (Pmode, 16); | |
09a1f342 | 1012 | tga = get_tls_get_addr (); |
5f7b9df8 | 1013 | scratch = gen_reg_rtx (Pmode); |
1014 | seq = GEN_INT (alpha_next_sequence_number++); | |
1015 | ||
1016 | emit_insn (gen_movdi_er_tlsldm (r16, pic_offset_table_rtx, seq)); | |
1017 | insn = gen_call_value_osf_tlsldm (r0, tga, seq); | |
1018 | insn = emit_call_insn (insn); | |
9c2a0c05 | 1019 | RTL_CONST_CALL_P (insn) = 1; |
5f7b9df8 | 1020 | use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r16); |
1021 | ||
1022 | insn = get_insns (); | |
1023 | end_sequence (); | |
1024 | ||
1025 | eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), | |
1026 | UNSPEC_TLSLDM_CALL); | |
1027 | emit_libcall_block (insn, scratch, r0, eqv); | |
1028 | ||
1029 | eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), UNSPEC_DTPREL); | |
1030 | eqv = gen_rtx_CONST (Pmode, eqv); | |
1031 | ||
1032 | if (alpha_tls_size == 64) | |
1033 | { | |
1034 | dest = gen_reg_rtx (Pmode); | |
1035 | emit_insn (gen_rtx_SET (VOIDmode, dest, eqv)); | |
1036 | emit_insn (gen_adddi3 (dest, dest, scratch)); | |
1037 | return dest; | |
1038 | } | |
1039 | if (alpha_tls_size == 32) | |
1040 | { | |
1041 | insn = gen_rtx_HIGH (Pmode, eqv); | |
1042 | insn = gen_rtx_PLUS (Pmode, scratch, insn); | |
1043 | scratch = gen_reg_rtx (Pmode); | |
1044 | emit_insn (gen_rtx_SET (VOIDmode, scratch, insn)); | |
1045 | } | |
1046 | return gen_rtx_LO_SUM (Pmode, scratch, eqv); | |
1047 | ||
1048 | case TLS_MODEL_INITIAL_EXEC: | |
1049 | eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), UNSPEC_TPREL); | |
1050 | eqv = gen_rtx_CONST (Pmode, eqv); | |
1051 | tp = gen_reg_rtx (Pmode); | |
1052 | scratch = gen_reg_rtx (Pmode); | |
1053 | dest = gen_reg_rtx (Pmode); | |
1054 | ||
1055 | emit_insn (gen_load_tp (tp)); | |
1056 | emit_insn (gen_rtx_SET (VOIDmode, scratch, eqv)); | |
1057 | emit_insn (gen_adddi3 (dest, tp, scratch)); | |
1058 | return dest; | |
1059 | ||
1060 | case TLS_MODEL_LOCAL_EXEC: | |
1061 | eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), UNSPEC_TPREL); | |
1062 | eqv = gen_rtx_CONST (Pmode, eqv); | |
1063 | tp = gen_reg_rtx (Pmode); | |
1064 | ||
1065 | emit_insn (gen_load_tp (tp)); | |
1066 | if (alpha_tls_size == 32) | |
1067 | { | |
1068 | insn = gen_rtx_HIGH (Pmode, eqv); | |
1069 | insn = gen_rtx_PLUS (Pmode, tp, insn); | |
1070 | tp = gen_reg_rtx (Pmode); | |
1071 | emit_insn (gen_rtx_SET (VOIDmode, tp, insn)); | |
1072 | } | |
1073 | return gen_rtx_LO_SUM (Pmode, tp, eqv); | |
dda53cd5 | 1074 | |
1075 | default: | |
1076 | gcc_unreachable (); | |
5f7b9df8 | 1077 | } |
1078 | ||
8afb6db4 | 1079 | if (local_symbolic_operand (x, Pmode)) |
1080 | { | |
1081 | if (small_symbolic_operand (x, Pmode)) | |
f5a60074 | 1082 | return x; |
8afb6db4 | 1083 | else |
1084 | { | |
e1ba4a27 | 1085 | if (can_create_pseudo_p ()) |
f5a60074 | 1086 | scratch = gen_reg_rtx (Pmode); |
1087 | emit_insn (gen_rtx_SET (VOIDmode, scratch, | |
1088 | gen_rtx_HIGH (Pmode, x))); | |
1089 | return gen_rtx_LO_SUM (Pmode, scratch, x); | |
8afb6db4 | 1090 | } |
5dcb037d | 1091 | } |
1f0ce6a6 | 1092 | } |
1093 | ||
0d50f0b7 | 1094 | return NULL; |
1095 | ||
1096 | split_addend: | |
1097 | { | |
f5a60074 | 1098 | HOST_WIDE_INT low, high; |
1099 | ||
1100 | low = ((addend & 0xffff) ^ 0x8000) - 0x8000; | |
1101 | addend -= low; | |
1102 | high = ((addend & 0xffffffff) ^ 0x80000000) - 0x80000000; | |
1103 | addend -= high; | |
1104 | ||
1105 | if (addend) | |
1106 | x = expand_simple_binop (Pmode, PLUS, x, GEN_INT (addend), | |
e1ba4a27 | 1107 | (!can_create_pseudo_p () ? scratch : NULL_RTX), |
f5a60074 | 1108 | 1, OPTAB_LIB_WIDEN); |
1109 | if (high) | |
1110 | x = expand_simple_binop (Pmode, PLUS, x, GEN_INT (high), | |
e1ba4a27 | 1111 | (!can_create_pseudo_p () ? scratch : NULL_RTX), |
f5a60074 | 1112 | 1, OPTAB_LIB_WIDEN); |
1113 | ||
1114 | return plus_constant (x, low); | |
0d50f0b7 | 1115 | } |
1116 | } | |
1117 | ||
41e3a0c7 | 1118 | |
1119 | /* Try machine-dependent ways of modifying an illegitimate address | |
1120 | to be legitimate. Return X or the new, valid address. */ | |
1121 | ||
1122 | static rtx | |
1123 | alpha_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, | |
1124 | enum machine_mode mode) | |
1125 | { | |
1126 | rtx new_x = alpha_legitimize_address_1 (x, NULL_RTX, mode); | |
1127 | return new_x ? new_x : x; | |
1128 | } | |
1129 | ||
c0da4391 | 1130 | /* Primarily this is required for TLS symbols, but given that our move |
1131 | patterns *ought* to be able to handle any symbol at any time, we | |
1132 | should never be spilling symbolic operands to the constant pool, ever. */ | |
1133 | ||
1134 | static bool | |
1135 | alpha_cannot_force_const_mem (rtx x) | |
1136 | { | |
1137 | enum rtx_code code = GET_CODE (x); | |
1138 | return code == SYMBOL_REF || code == LABEL_REF || code == CONST; | |
1139 | } | |
1140 | ||
805e22b2 | 1141 | /* We do not allow indirect calls to be optimized into sibling calls, nor |
9bdcc1e5 | 1142 | can we allow a call to a function with a different GP to be optimized |
1143 | into a sibcall. */ | |
1144 | ||
805e22b2 | 1145 | static bool |
92643d95 | 1146 | alpha_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED) |
805e22b2 | 1147 | { |
9bdcc1e5 | 1148 | /* Can't do indirect tail calls, since we don't know if the target |
1149 | uses the same GP. */ | |
1150 | if (!decl) | |
1151 | return false; | |
1152 | ||
1153 | /* Otherwise, we can make a tail call if the target function shares | |
1154 | the same GP. */ | |
1155 | return decl_has_samegp (decl); | |
805e22b2 | 1156 | } |
1157 | ||
b71b0310 | 1158 | int |
1159 | some_small_symbolic_operand_int (rtx *px, void *data ATTRIBUTE_UNUSED) | |
367e2ab3 | 1160 | { |
1161 | rtx x = *px; | |
f5a60074 | 1162 | |
792433e3 | 1163 | /* Don't re-split. */ |
1164 | if (GET_CODE (x) == LO_SUM) | |
1165 | return -1; | |
367e2ab3 | 1166 | |
792433e3 | 1167 | return small_symbolic_operand (x, Pmode) != 0; |
f5a60074 | 1168 | } |
1169 | ||
367e2ab3 | 1170 | static int |
92643d95 | 1171 | split_small_symbolic_operand_1 (rtx *px, void *data ATTRIBUTE_UNUSED) |
367e2ab3 | 1172 | { |
1173 | rtx x = *px; | |
443bb1a6 | 1174 | |
792433e3 | 1175 | /* Don't re-split. */ |
1176 | if (GET_CODE (x) == LO_SUM) | |
1177 | return -1; | |
f5a60074 | 1178 | |
367e2ab3 | 1179 | if (small_symbolic_operand (x, Pmode)) |
1180 | { | |
1181 | x = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, x); | |
1182 | *px = x; | |
792433e3 | 1183 | return -1; |
367e2ab3 | 1184 | } |
1185 | ||
792433e3 | 1186 | return 0; |
f5a60074 | 1187 | } |
1188 | ||
92643d95 | 1189 | rtx |
1190 | split_small_symbolic_operand (rtx x) | |
1191 | { | |
1192 | x = copy_insn (x); | |
1193 | for_each_rtx (&x, split_small_symbolic_operand_1, NULL); | |
1194 | return x; | |
1195 | } | |
1196 | ||
2f58af60 | 1197 | /* Indicate that INSN cannot be duplicated. This is true for any insn |
1198 | that we've marked with gpdisp relocs, since those have to stay in | |
1199 | 1-1 correspondence with one another. | |
1200 | ||
5910bb95 | 1201 | Technically we could copy them if we could set up a mapping from one |
2f58af60 | 1202 | sequence number to another, across the set of insns to be duplicated. |
1203 | This seems overly complicated and error-prone since interblock motion | |
b55f2ed8 | 1204 | from sched-ebb could move one of the pair of insns to a different block. |
1205 | ||
1206 | Also cannot allow jsr insns to be duplicated. If they throw exceptions, | |
1207 | then they'll be in a different block from their ldgp. Which could lead | |
1208 | the bb reorder code to think that it would be ok to copy just the block | |
1209 | containing the call and branch to the block containing the ldgp. */ | |
2f58af60 | 1210 | |
1211 | static bool | |
92643d95 | 1212 | alpha_cannot_copy_insn_p (rtx insn) |
2f58af60 | 1213 | { |
2f58af60 | 1214 | if (!reload_completed || !TARGET_EXPLICIT_RELOCS) |
1215 | return false; | |
b55f2ed8 | 1216 | if (recog_memoized (insn) >= 0) |
1217 | return get_attr_cannot_copy (insn); | |
1218 | else | |
2f58af60 | 1219 | return false; |
2f58af60 | 1220 | } |
1221 | ||
9e7454d0 | 1222 | |
0d50f0b7 | 1223 | /* Try a machine-dependent way of reloading an illegitimate address |
1224 | operand. If we find one, push the reload and return the new rtx. */ | |
9e7454d0 | 1225 | |
0d50f0b7 | 1226 | rtx |
92643d95 | 1227 | alpha_legitimize_reload_address (rtx x, |
1228 | enum machine_mode mode ATTRIBUTE_UNUSED, | |
1229 | int opnum, int type, | |
1230 | int ind_levels ATTRIBUTE_UNUSED) | |
0d50f0b7 | 1231 | { |
1232 | /* We must recognize output that we have already generated ourselves. */ | |
1233 | if (GET_CODE (x) == PLUS | |
1234 | && GET_CODE (XEXP (x, 0)) == PLUS | |
c933fb42 | 1235 | && REG_P (XEXP (XEXP (x, 0), 0)) |
1236 | && CONST_INT_P (XEXP (XEXP (x, 0), 1)) | |
1237 | && CONST_INT_P (XEXP (x, 1))) | |
0d50f0b7 | 1238 | { |
1239 | push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL, | |
1240 | BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0, | |
0a48089c | 1241 | opnum, (enum reload_type) type); |
0d50f0b7 | 1242 | return x; |
1243 | } | |
1244 | ||
1245 | /* We wish to handle large displacements off a base register by | |
1246 | splitting the addend across an ldah and the mem insn. This | |
1247 | cuts number of extra insns needed from 3 to 1. */ | |
1248 | if (GET_CODE (x) == PLUS | |
c933fb42 | 1249 | && REG_P (XEXP (x, 0)) |
0d50f0b7 | 1250 | && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER |
1251 | && REGNO_OK_FOR_BASE_P (REGNO (XEXP (x, 0))) | |
1252 | && GET_CODE (XEXP (x, 1)) == CONST_INT) | |
1253 | { | |
1254 | HOST_WIDE_INT val = INTVAL (XEXP (x, 1)); | |
1255 | HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; | |
1256 | HOST_WIDE_INT high | |
1257 | = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000; | |
1258 | ||
1259 | /* Check for 32-bit overflow. */ | |
1260 | if (high + low != val) | |
1261 | return NULL_RTX; | |
1262 | ||
1263 | /* Reload the high part into a base reg; leave the low part | |
1264 | in the mem directly. */ | |
1265 | x = gen_rtx_PLUS (GET_MODE (x), | |
1266 | gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0), | |
1267 | GEN_INT (high)), | |
1268 | GEN_INT (low)); | |
1269 | ||
1270 | push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL, | |
1271 | BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0, | |
0a48089c | 1272 | opnum, (enum reload_type) type); |
0d50f0b7 | 1273 | return x; |
1274 | } | |
1275 | ||
1276 | return NULL_RTX; | |
1277 | } | |
1278 | \f | |
fab7adbf | 1279 | /* Compute a (partial) cost for rtx X. Return true if the complete |
1280 | cost has been computed, and false if subexpressions should be | |
1281 | scanned. In either case, *TOTAL contains the cost result. */ | |
1282 | ||
1283 | static bool | |
f529eb25 | 1284 | alpha_rtx_costs (rtx x, int code, int outer_code, int *total, |
1285 | bool speed) | |
fab7adbf | 1286 | { |
1287 | enum machine_mode mode = GET_MODE (x); | |
1288 | bool float_mode_p = FLOAT_MODE_P (mode); | |
d7cf2331 | 1289 | const struct alpha_rtx_cost_data *cost_data; |
1290 | ||
f529eb25 | 1291 | if (!speed) |
d7cf2331 | 1292 | cost_data = &alpha_rtx_cost_size; |
1293 | else | |
fb64edde | 1294 | cost_data = &alpha_rtx_cost_data[alpha_tune]; |
fab7adbf | 1295 | |
1296 | switch (code) | |
1297 | { | |
d7cf2331 | 1298 | case CONST_INT: |
fab7adbf | 1299 | /* If this is an 8-bit constant, return zero since it can be used |
1300 | nearly anywhere with no cost. If it is a valid operand for an | |
1301 | ADD or AND, likewise return 0 if we know it will be used in that | |
1302 | context. Otherwise, return 2 since it might be used there later. | |
1303 | All other constants take at least two insns. */ | |
fab7adbf | 1304 | if (INTVAL (x) >= 0 && INTVAL (x) < 256) |
1305 | { | |
1306 | *total = 0; | |
1307 | return true; | |
1308 | } | |
8e262b5e | 1309 | /* FALLTHRU */ |
fab7adbf | 1310 | |
1311 | case CONST_DOUBLE: | |
1312 | if (x == CONST0_RTX (mode)) | |
1313 | *total = 0; | |
1314 | else if ((outer_code == PLUS && add_operand (x, VOIDmode)) | |
1315 | || (outer_code == AND && and_operand (x, VOIDmode))) | |
1316 | *total = 0; | |
1317 | else if (add_operand (x, VOIDmode) || and_operand (x, VOIDmode)) | |
1318 | *total = 2; | |
1319 | else | |
1320 | *total = COSTS_N_INSNS (2); | |
1321 | return true; | |
9e7454d0 | 1322 | |
fab7adbf | 1323 | case CONST: |
1324 | case SYMBOL_REF: | |
1325 | case LABEL_REF: | |
1326 | if (TARGET_EXPLICIT_RELOCS && small_symbolic_operand (x, VOIDmode)) | |
1327 | *total = COSTS_N_INSNS (outer_code != MEM); | |
1328 | else if (TARGET_EXPLICIT_RELOCS && local_symbolic_operand (x, VOIDmode)) | |
1329 | *total = COSTS_N_INSNS (1 + (outer_code != MEM)); | |
1330 | else if (tls_symbolic_operand_type (x)) | |
1331 | /* Estimate of cost for call_pal rduniq. */ | |
d7cf2331 | 1332 | /* ??? How many insns do we emit here? More than one... */ |
fab7adbf | 1333 | *total = COSTS_N_INSNS (15); |
1334 | else | |
1335 | /* Otherwise we do a load from the GOT. */ | |
f529eb25 | 1336 | *total = COSTS_N_INSNS (!speed ? 1 : alpha_memory_latency); |
fab7adbf | 1337 | return true; |
9e7454d0 | 1338 | |
91bc47b0 | 1339 | case HIGH: |
1340 | /* This is effectively an add_operand. */ | |
1341 | *total = 2; | |
1342 | return true; | |
1343 | ||
fab7adbf | 1344 | case PLUS: |
1345 | case MINUS: | |
1346 | if (float_mode_p) | |
d7cf2331 | 1347 | *total = cost_data->fp_add; |
fab7adbf | 1348 | else if (GET_CODE (XEXP (x, 0)) == MULT |
1349 | && const48_operand (XEXP (XEXP (x, 0), 1), VOIDmode)) | |
1350 | { | |
0a48089c | 1351 | *total = (rtx_cost (XEXP (XEXP (x, 0), 0), |
1352 | (enum rtx_code) outer_code, speed) | |
1353 | + rtx_cost (XEXP (x, 1), | |
1354 | (enum rtx_code) outer_code, speed) | |
1355 | + COSTS_N_INSNS (1)); | |
fab7adbf | 1356 | return true; |
1357 | } | |
1358 | return false; | |
1359 | ||
1360 | case MULT: | |
1361 | if (float_mode_p) | |
d7cf2331 | 1362 | *total = cost_data->fp_mult; |
fab7adbf | 1363 | else if (mode == DImode) |
d7cf2331 | 1364 | *total = cost_data->int_mult_di; |
fab7adbf | 1365 | else |
d7cf2331 | 1366 | *total = cost_data->int_mult_si; |
fab7adbf | 1367 | return false; |
1368 | ||
1369 | case ASHIFT: | |
c933fb42 | 1370 | if (CONST_INT_P (XEXP (x, 1)) |
fab7adbf | 1371 | && INTVAL (XEXP (x, 1)) <= 3) |
1372 | { | |
1373 | *total = COSTS_N_INSNS (1); | |
1374 | return false; | |
1375 | } | |
8e262b5e | 1376 | /* FALLTHRU */ |
fab7adbf | 1377 | |
1378 | case ASHIFTRT: | |
1379 | case LSHIFTRT: | |
d7cf2331 | 1380 | *total = cost_data->int_shift; |
fab7adbf | 1381 | return false; |
1382 | ||
1383 | case IF_THEN_ELSE: | |
1384 | if (float_mode_p) | |
d7cf2331 | 1385 | *total = cost_data->fp_add; |
fab7adbf | 1386 | else |
d7cf2331 | 1387 | *total = cost_data->int_cmov; |
fab7adbf | 1388 | return false; |
1389 | ||
1390 | case DIV: | |
1391 | case UDIV: | |
1392 | case MOD: | |
1393 | case UMOD: | |
1394 | if (!float_mode_p) | |
d7cf2331 | 1395 | *total = cost_data->int_div; |
fab7adbf | 1396 | else if (mode == SFmode) |
d7cf2331 | 1397 | *total = cost_data->fp_div_sf; |
fab7adbf | 1398 | else |
d7cf2331 | 1399 | *total = cost_data->fp_div_df; |
fab7adbf | 1400 | return false; |
1401 | ||
1402 | case MEM: | |
f529eb25 | 1403 | *total = COSTS_N_INSNS (!speed ? 1 : alpha_memory_latency); |
fab7adbf | 1404 | return true; |
1405 | ||
1406 | case NEG: | |
1407 | if (! float_mode_p) | |
1408 | { | |
1409 | *total = COSTS_N_INSNS (1); | |
1410 | return false; | |
1411 | } | |
8e262b5e | 1412 | /* FALLTHRU */ |
fab7adbf | 1413 | |
1414 | case ABS: | |
1415 | if (! float_mode_p) | |
1416 | { | |
d7cf2331 | 1417 | *total = COSTS_N_INSNS (1) + cost_data->int_cmov; |
fab7adbf | 1418 | return false; |
1419 | } | |
8e262b5e | 1420 | /* FALLTHRU */ |
fab7adbf | 1421 | |
1422 | case FLOAT: | |
1423 | case UNSIGNED_FLOAT: | |
1424 | case FIX: | |
1425 | case UNSIGNED_FIX: | |
fab7adbf | 1426 | case FLOAT_TRUNCATE: |
d7cf2331 | 1427 | *total = cost_data->fp_add; |
fab7adbf | 1428 | return false; |
1429 | ||
5fc4edde | 1430 | case FLOAT_EXTEND: |
c933fb42 | 1431 | if (MEM_P (XEXP (x, 0))) |
5fc4edde | 1432 | *total = 0; |
1433 | else | |
1434 | *total = cost_data->fp_add; | |
1435 | return false; | |
1436 | ||
fab7adbf | 1437 | default: |
1438 | return false; | |
1439 | } | |
1440 | } | |
1441 | \f | |
bf2a98b3 | 1442 | /* REF is an alignable memory location. Place an aligned SImode |
1443 | reference into *PALIGNED_MEM and the number of bits to shift into | |
a99a652b | 1444 | *PBITNUM. SCRATCH is a free register for use in reloading out |
1445 | of range stack slots. */ | |
bf2a98b3 | 1446 | |
1447 | void | |
92643d95 | 1448 | get_aligned_mem (rtx ref, rtx *paligned_mem, rtx *pbitnum) |
bf2a98b3 | 1449 | { |
1450 | rtx base; | |
a3fed3d2 | 1451 | HOST_WIDE_INT disp, offset; |
bf2a98b3 | 1452 | |
c933fb42 | 1453 | gcc_assert (MEM_P (ref)); |
bf2a98b3 | 1454 | |
cc215844 | 1455 | if (reload_in_progress |
1456 | && ! memory_address_p (GET_MODE (ref), XEXP (ref, 0))) | |
a99a652b | 1457 | { |
cc215844 | 1458 | base = find_replacement (&XEXP (ref, 0)); |
4d10b463 | 1459 | gcc_assert (memory_address_p (GET_MODE (ref), base)); |
a99a652b | 1460 | } |
bf2a98b3 | 1461 | else |
4d10b463 | 1462 | base = XEXP (ref, 0); |
bf2a98b3 | 1463 | |
1464 | if (GET_CODE (base) == PLUS) | |
a3fed3d2 | 1465 | disp = INTVAL (XEXP (base, 1)), base = XEXP (base, 0); |
1466 | else | |
1467 | disp = 0; | |
1468 | ||
1469 | /* Find the byte offset within an aligned word. If the memory itself is | |
1470 | claimed to be aligned, believe it. Otherwise, aligned_memory_operand | |
1471 | will have examined the base register and determined it is aligned, and | |
1472 | thus displacements from it are naturally alignable. */ | |
1473 | if (MEM_ALIGN (ref) >= 32) | |
1474 | offset = 0; | |
1475 | else | |
1476 | offset = disp & 3; | |
bf2a98b3 | 1477 | |
5e46378b | 1478 | /* The location should not cross aligned word boundary. */ |
1479 | gcc_assert (offset + GET_MODE_SIZE (GET_MODE (ref)) | |
1480 | <= GET_MODE_SIZE (SImode)); | |
1481 | ||
a3fed3d2 | 1482 | /* Access the entire aligned word. */ |
1483 | *paligned_mem = widen_memory_access (ref, SImode, -offset); | |
bf2a98b3 | 1484 | |
a3fed3d2 | 1485 | /* Convert the byte offset within the word to a bit offset. */ |
9caef960 | 1486 | if (WORDS_BIG_ENDIAN) |
a3fed3d2 | 1487 | offset = 32 - (GET_MODE_BITSIZE (GET_MODE (ref)) + offset * 8); |
9caef960 | 1488 | else |
a3fed3d2 | 1489 | offset *= 8; |
1490 | *pbitnum = GEN_INT (offset); | |
bf2a98b3 | 1491 | } |
1492 | ||
9e7454d0 | 1493 | /* Similar, but just get the address. Handle the two reload cases. |
b044f41c | 1494 | Add EXTRA_OFFSET to the address we return. */ |
bf2a98b3 | 1495 | |
1496 | rtx | |
0934d969 | 1497 | get_unaligned_address (rtx ref) |
bf2a98b3 | 1498 | { |
1499 | rtx base; | |
1500 | HOST_WIDE_INT offset = 0; | |
1501 | ||
c933fb42 | 1502 | gcc_assert (MEM_P (ref)); |
bf2a98b3 | 1503 | |
cc215844 | 1504 | if (reload_in_progress |
1505 | && ! memory_address_p (GET_MODE (ref), XEXP (ref, 0))) | |
a99a652b | 1506 | { |
a99a652b | 1507 | base = find_replacement (&XEXP (ref, 0)); |
cc215844 | 1508 | |
4d10b463 | 1509 | gcc_assert (memory_address_p (GET_MODE (ref), base)); |
a99a652b | 1510 | } |
bf2a98b3 | 1511 | else |
4d10b463 | 1512 | base = XEXP (ref, 0); |
bf2a98b3 | 1513 | |
1514 | if (GET_CODE (base) == PLUS) | |
1515 | offset += INTVAL (XEXP (base, 1)), base = XEXP (base, 0); | |
1516 | ||
0934d969 | 1517 | return plus_constant (base, offset); |
1518 | } | |
1519 | ||
1520 | /* Compute a value X, such that X & 7 == (ADDR + OFS) & 7. | |
1521 | X is always returned in a register. */ | |
1522 | ||
1523 | rtx | |
1524 | get_unaligned_offset (rtx addr, HOST_WIDE_INT ofs) | |
1525 | { | |
1526 | if (GET_CODE (addr) == PLUS) | |
1527 | { | |
1528 | ofs += INTVAL (XEXP (addr, 1)); | |
1529 | addr = XEXP (addr, 0); | |
1530 | } | |
1531 | ||
1532 | return expand_simple_binop (Pmode, PLUS, addr, GEN_INT (ofs & 7), | |
1533 | NULL_RTX, 1, OPTAB_LIB_WIDEN); | |
bf2a98b3 | 1534 | } |
14f7bc98 | 1535 | |
f5a60074 | 1536 | /* On the Alpha, all (non-symbolic) constants except zero go into |
9e7454d0 | 1537 | a floating-point register via memory. Note that we cannot |
8deb3959 | 1538 | return anything that is not a subset of RCLASS, and that some |
f5a60074 | 1539 | symbolic constants cannot be dropped to memory. */ |
1540 | ||
1541 | enum reg_class | |
8deb3959 | 1542 | alpha_preferred_reload_class(rtx x, enum reg_class rclass) |
f5a60074 | 1543 | { |
1544 | /* Zero is present in any register class. */ | |
1545 | if (x == CONST0_RTX (GET_MODE (x))) | |
8deb3959 | 1546 | return rclass; |
f5a60074 | 1547 | |
1548 | /* These sorts of constants we can easily drop to memory. */ | |
c933fb42 | 1549 | if (CONST_INT_P (x) |
91bc47b0 | 1550 | || GET_CODE (x) == CONST_DOUBLE |
1551 | || GET_CODE (x) == CONST_VECTOR) | |
f5a60074 | 1552 | { |
8deb3959 | 1553 | if (rclass == FLOAT_REGS) |
f5a60074 | 1554 | return NO_REGS; |
8deb3959 | 1555 | if (rclass == ALL_REGS) |
f5a60074 | 1556 | return GENERAL_REGS; |
8deb3959 | 1557 | return rclass; |
f5a60074 | 1558 | } |
1559 | ||
1560 | /* All other kinds of constants should not (and in the case of HIGH | |
1561 | cannot) be dropped to memory -- instead we use a GENERAL_REGS | |
1562 | secondary reload. */ | |
1563 | if (CONSTANT_P (x)) | |
8deb3959 | 1564 | return (rclass == ALL_REGS ? GENERAL_REGS : rclass); |
f5a60074 | 1565 | |
8deb3959 | 1566 | return rclass; |
f5a60074 | 1567 | } |
1568 | ||
0d96cd2b | 1569 | /* Inform reload about cases where moving X with a mode MODE to a register in |
8deb3959 | 1570 | RCLASS requires an extra scratch or immediate register. Return the class |
0d96cd2b | 1571 | needed for the immediate register. */ |
14f7bc98 | 1572 | |
0d96cd2b | 1573 | static enum reg_class |
8deb3959 | 1574 | alpha_secondary_reload (bool in_p, rtx x, enum reg_class rclass, |
0d96cd2b | 1575 | enum machine_mode mode, secondary_reload_info *sri) |
14f7bc98 | 1576 | { |
0d96cd2b | 1577 | /* Loading and storing HImode or QImode values to and from memory |
1578 | usually requires a scratch register. */ | |
1579 | if (!TARGET_BWX && (mode == QImode || mode == HImode || mode == CQImode)) | |
d2494d49 | 1580 | { |
0d96cd2b | 1581 | if (any_memory_operand (x, mode)) |
d2494d49 | 1582 | { |
0d96cd2b | 1583 | if (in_p) |
1584 | { | |
1585 | if (!aligned_memory_operand (x, mode)) | |
1586 | sri->icode = reload_in_optab[mode]; | |
1587 | } | |
1588 | else | |
1589 | sri->icode = reload_out_optab[mode]; | |
1590 | return NO_REGS; | |
d2494d49 | 1591 | } |
1592 | } | |
14f7bc98 | 1593 | |
0d96cd2b | 1594 | /* We also cannot do integral arithmetic into FP regs, as might result |
1595 | from register elimination into a DImode fp register. */ | |
8deb3959 | 1596 | if (rclass == FLOAT_REGS) |
14f7bc98 | 1597 | { |
0d96cd2b | 1598 | if (MEM_P (x) && GET_CODE (XEXP (x, 0)) == AND) |
14f7bc98 | 1599 | return GENERAL_REGS; |
0d96cd2b | 1600 | if (in_p && INTEGRAL_MODE_P (mode) |
1601 | && !MEM_P (x) && !REG_P (x) && !CONST_INT_P (x)) | |
14f7bc98 | 1602 | return GENERAL_REGS; |
1603 | } | |
1604 | ||
1605 | return NO_REGS; | |
1606 | } | |
bf2a98b3 | 1607 | \f |
1608 | /* Subfunction of the following function. Update the flags of any MEM | |
1609 | found in part of X. */ | |
1610 | ||
b04fab2a | 1611 | static int |
1612 | alpha_set_memflags_1 (rtx *xp, void *data) | |
bf2a98b3 | 1613 | { |
b04fab2a | 1614 | rtx x = *xp, orig = (rtx) data; |
bf2a98b3 | 1615 | |
c933fb42 | 1616 | if (!MEM_P (x)) |
b04fab2a | 1617 | return 0; |
bf2a98b3 | 1618 | |
b04fab2a | 1619 | MEM_VOLATILE_P (x) = MEM_VOLATILE_P (orig); |
1620 | MEM_IN_STRUCT_P (x) = MEM_IN_STRUCT_P (orig); | |
1621 | MEM_SCALAR_P (x) = MEM_SCALAR_P (orig); | |
1622 | MEM_NOTRAP_P (x) = MEM_NOTRAP_P (orig); | |
1623 | MEM_READONLY_P (x) = MEM_READONLY_P (orig); | |
bf2a98b3 | 1624 | |
b04fab2a | 1625 | /* Sadly, we cannot use alias sets because the extra aliasing |
1626 | produced by the AND interferes. Given that two-byte quantities | |
1627 | are the only thing we would be able to differentiate anyway, | |
1628 | there does not seem to be any point in convoluting the early | |
1629 | out of the alias check. */ | |
99c14947 | 1630 | |
b04fab2a | 1631 | return -1; |
bf2a98b3 | 1632 | } |
1633 | ||
7ca8bc48 | 1634 | /* Given SEQ, which is an INSN list, look for any MEMs in either |
31d3e01c | 1635 | a SET_DEST or a SET_SRC and copy the in-struct, unchanging, and |
1636 | volatile flags from REF into each of the MEMs found. If REF is not | |
1637 | a MEM, don't do anything. */ | |
bf2a98b3 | 1638 | |
1639 | void | |
7ca8bc48 | 1640 | alpha_set_memflags (rtx seq, rtx ref) |
bf2a98b3 | 1641 | { |
7ca8bc48 | 1642 | rtx insn; |
849674a3 | 1643 | |
7ca8bc48 | 1644 | if (!MEM_P (ref)) |
bf2a98b3 | 1645 | return; |
1646 | ||
9e7454d0 | 1647 | /* This is only called from alpha.md, after having had something |
849674a3 | 1648 | generated from one of the insn patterns. So if everything is |
1649 | zero, the pattern is already up-to-date. */ | |
b04fab2a | 1650 | if (!MEM_VOLATILE_P (ref) |
1651 | && !MEM_IN_STRUCT_P (ref) | |
1652 | && !MEM_SCALAR_P (ref) | |
1653 | && !MEM_NOTRAP_P (ref) | |
1654 | && !MEM_READONLY_P (ref)) | |
849674a3 | 1655 | return; |
1656 | ||
7ca8bc48 | 1657 | for (insn = seq; insn; insn = NEXT_INSN (insn)) |
1658 | if (INSN_P (insn)) | |
1659 | for_each_rtx (&PATTERN (insn), alpha_set_memflags_1, (void *) ref); | |
1660 | else | |
1661 | gcc_unreachable (); | |
bf2a98b3 | 1662 | } |
1663 | \f | |
91bc47b0 | 1664 | static rtx alpha_emit_set_const (rtx, enum machine_mode, HOST_WIDE_INT, |
1665 | int, bool); | |
1666 | ||
1667 | /* Internal routine for alpha_emit_set_const to check for N or below insns. | |
1668 | If NO_OUTPUT is true, then we only check to see if N insns are possible, | |
1669 | and return pc_rtx if successful. */ | |
6f86cb15 | 1670 | |
1671 | static rtx | |
92643d95 | 1672 | alpha_emit_set_const_1 (rtx target, enum machine_mode mode, |
91bc47b0 | 1673 | HOST_WIDE_INT c, int n, bool no_output) |
bf2a98b3 | 1674 | { |
8deb3959 | 1675 | HOST_WIDE_INT new_const; |
bf2a98b3 | 1676 | int i, bits; |
ea5db00c | 1677 | /* Use a pseudo if highly optimizing and still generating RTL. */ |
1678 | rtx subtarget | |
e1ba4a27 | 1679 | = (flag_expensive_optimizations && can_create_pseudo_p () ? 0 : target); |
301416af | 1680 | rtx temp, insn; |
bf2a98b3 | 1681 | |
bf2a98b3 | 1682 | /* If this is a sign-extended 32-bit constant, we can do this in at most |
1683 | three insns, so do it if we have enough insns left. We always have | |
65abff06 | 1684 | a sign-extended 32-bit constant when compiling on a narrow machine. */ |
bf2a98b3 | 1685 | |
3bc2043a | 1686 | if (HOST_BITS_PER_WIDE_INT != 64 |
1687 | || c >> 31 == -1 || c >> 31 == 0) | |
bf2a98b3 | 1688 | { |
bdb19034 | 1689 | HOST_WIDE_INT low = ((c & 0xffff) ^ 0x8000) - 0x8000; |
bf2a98b3 | 1690 | HOST_WIDE_INT tmp1 = c - low; |
bdb19034 | 1691 | HOST_WIDE_INT high = (((tmp1 >> 16) & 0xffff) ^ 0x8000) - 0x8000; |
bf2a98b3 | 1692 | HOST_WIDE_INT extra = 0; |
1693 | ||
81d03ebd | 1694 | /* If HIGH will be interpreted as negative but the constant is |
1695 | positive, we must adjust it to do two ldha insns. */ | |
1696 | ||
1697 | if ((high & 0x8000) != 0 && c >= 0) | |
bf2a98b3 | 1698 | { |
1699 | extra = 0x4000; | |
1700 | tmp1 -= 0x40000000; | |
1701 | high = ((tmp1 >> 16) & 0xffff) - 2 * ((tmp1 >> 16) & 0x8000); | |
1702 | } | |
1703 | ||
1704 | if (c == low || (low == 0 && extra == 0)) | |
3bc2043a | 1705 | { |
1706 | /* We used to use copy_to_suggested_reg (GEN_INT (c), target, mode) | |
1707 | but that meant that we can't handle INT_MIN on 32-bit machines | |
9e7454d0 | 1708 | (like NT/Alpha), because we recurse indefinitely through |
3bc2043a | 1709 | emit_move_insn to gen_movdi. So instead, since we know exactly |
1710 | what we want, create it explicitly. */ | |
1711 | ||
91bc47b0 | 1712 | if (no_output) |
1713 | return pc_rtx; | |
3bc2043a | 1714 | if (target == NULL) |
1715 | target = gen_reg_rtx (mode); | |
941522d6 | 1716 | emit_insn (gen_rtx_SET (VOIDmode, target, GEN_INT (c))); |
3bc2043a | 1717 | return target; |
1718 | } | |
6f86cb15 | 1719 | else if (n >= 2 + (extra != 0)) |
bf2a98b3 | 1720 | { |
91bc47b0 | 1721 | if (no_output) |
1722 | return pc_rtx; | |
e1ba4a27 | 1723 | if (!can_create_pseudo_p ()) |
5b952578 | 1724 | { |
1725 | emit_insn (gen_rtx_SET (VOIDmode, target, GEN_INT (high << 16))); | |
1726 | temp = target; | |
1727 | } | |
1728 | else | |
1729 | temp = copy_to_suggested_reg (GEN_INT (high << 16), | |
1730 | subtarget, mode); | |
ea5db00c | 1731 | |
301416af | 1732 | /* As of 2002-02-23, addsi3 is only available when not optimizing. |
1733 | This means that if we go through expand_binop, we'll try to | |
1734 | generate extensions, etc, which will require new pseudos, which | |
1735 | will fail during some split phases. The SImode add patterns | |
1736 | still exist, but are not named. So build the insns by hand. */ | |
1737 | ||
bf2a98b3 | 1738 | if (extra != 0) |
301416af | 1739 | { |
1740 | if (! subtarget) | |
1741 | subtarget = gen_reg_rtx (mode); | |
1742 | insn = gen_rtx_PLUS (mode, temp, GEN_INT (extra << 16)); | |
1743 | insn = gen_rtx_SET (VOIDmode, subtarget, insn); | |
1744 | emit_insn (insn); | |
b8585446 | 1745 | temp = subtarget; |
301416af | 1746 | } |
bf2a98b3 | 1747 | |
301416af | 1748 | if (target == NULL) |
1749 | target = gen_reg_rtx (mode); | |
1750 | insn = gen_rtx_PLUS (mode, temp, GEN_INT (low)); | |
1751 | insn = gen_rtx_SET (VOIDmode, target, insn); | |
1752 | emit_insn (insn); | |
1753 | return target; | |
bf2a98b3 | 1754 | } |
1755 | } | |
1756 | ||
dacd345b | 1757 | /* If we couldn't do it that way, try some other methods. But if we have |
07014ed9 | 1758 | no instructions left, don't bother. Likewise, if this is SImode and |
1759 | we can't make pseudos, we can't do anything since the expand_binop | |
1760 | and expand_unop calls will widen and try to make pseudos. */ | |
bf2a98b3 | 1761 | |
e1ba4a27 | 1762 | if (n == 1 || (mode == SImode && !can_create_pseudo_p ())) |
bf2a98b3 | 1763 | return 0; |
1764 | ||
dacd345b | 1765 | /* Next, see if we can load a related constant and then shift and possibly |
bf2a98b3 | 1766 | negate it to get the constant we want. Try this once each increasing |
1767 | numbers of insns. */ | |
1768 | ||
1769 | for (i = 1; i < n; i++) | |
1770 | { | |
bdb19034 | 1771 | /* First, see if minus some low bits, we've an easy load of |
1772 | high bits. */ | |
1773 | ||
8deb3959 | 1774 | new_const = ((c & 0xffff) ^ 0x8000) - 0x8000; |
1775 | if (new_const != 0) | |
91bc47b0 | 1776 | { |
8deb3959 | 1777 | temp = alpha_emit_set_const (subtarget, mode, c - new_const, i, no_output); |
91bc47b0 | 1778 | if (temp) |
1779 | { | |
1780 | if (no_output) | |
1781 | return temp; | |
8deb3959 | 1782 | return expand_binop (mode, add_optab, temp, GEN_INT (new_const), |
91bc47b0 | 1783 | target, 0, OPTAB_WIDEN); |
1784 | } | |
1785 | } | |
bdb19034 | 1786 | |
1787 | /* Next try complementing. */ | |
91bc47b0 | 1788 | temp = alpha_emit_set_const (subtarget, mode, ~c, i, no_output); |
1789 | if (temp) | |
1790 | { | |
1791 | if (no_output) | |
1792 | return temp; | |
1793 | return expand_unop (mode, one_cmpl_optab, temp, target, 0); | |
1794 | } | |
bf2a98b3 | 1795 | |
ea5db00c | 1796 | /* Next try to form a constant and do a left shift. We can do this |
bf2a98b3 | 1797 | if some low-order bits are zero; the exact_log2 call below tells |
1798 | us that information. The bits we are shifting out could be any | |
1799 | value, but here we'll just try the 0- and sign-extended forms of | |
1800 | the constant. To try to increase the chance of having the same | |
1801 | constant in more than one insn, start at the highest number of | |
1802 | bits to shift, but try all possibilities in case a ZAPNOT will | |
1803 | be useful. */ | |
1804 | ||
91bc47b0 | 1805 | bits = exact_log2 (c & -c); |
1806 | if (bits > 0) | |
bf2a98b3 | 1807 | for (; bits > 0; bits--) |
91bc47b0 | 1808 | { |
8deb3959 | 1809 | new_const = c >> bits; |
1810 | temp = alpha_emit_set_const (subtarget, mode, new_const, i, no_output); | |
91bc47b0 | 1811 | if (!temp && c < 0) |
1812 | { | |
8deb3959 | 1813 | new_const = (unsigned HOST_WIDE_INT)c >> bits; |
1814 | temp = alpha_emit_set_const (subtarget, mode, new_const, | |
91bc47b0 | 1815 | i, no_output); |
1816 | } | |
1817 | if (temp) | |
1818 | { | |
1819 | if (no_output) | |
1820 | return temp; | |
1821 | return expand_binop (mode, ashl_optab, temp, GEN_INT (bits), | |
1822 | target, 0, OPTAB_WIDEN); | |
1823 | } | |
1824 | } | |
bf2a98b3 | 1825 | |
1826 | /* Now try high-order zero bits. Here we try the shifted-in bits as | |
066efb8d | 1827 | all zero and all ones. Be careful to avoid shifting outside the |
1828 | mode and to avoid shifting outside the host wide int size. */ | |
3bc2043a | 1829 | /* On narrow hosts, don't shift a 1 into the high bit, since we'll |
1830 | confuse the recursive call and set all of the high 32 bits. */ | |
bf2a98b3 | 1831 | |
91bc47b0 | 1832 | bits = (MIN (HOST_BITS_PER_WIDE_INT, GET_MODE_SIZE (mode) * 8) |
1833 | - floor_log2 (c) - 1 - (HOST_BITS_PER_WIDE_INT < 64)); | |
1834 | if (bits > 0) | |
bf2a98b3 | 1835 | for (; bits > 0; bits--) |
91bc47b0 | 1836 | { |
8deb3959 | 1837 | new_const = c << bits; |
1838 | temp = alpha_emit_set_const (subtarget, mode, new_const, i, no_output); | |
91bc47b0 | 1839 | if (!temp) |
1840 | { | |
8deb3959 | 1841 | new_const = (c << bits) | (((HOST_WIDE_INT) 1 << bits) - 1); |
1842 | temp = alpha_emit_set_const (subtarget, mode, new_const, | |
91bc47b0 | 1843 | i, no_output); |
1844 | } | |
1845 | if (temp) | |
1846 | { | |
1847 | if (no_output) | |
1848 | return temp; | |
1849 | return expand_binop (mode, lshr_optab, temp, GEN_INT (bits), | |
1850 | target, 1, OPTAB_WIDEN); | |
1851 | } | |
1852 | } | |
bf2a98b3 | 1853 | |
1854 | /* Now try high-order 1 bits. We get that with a sign-extension. | |
066efb8d | 1855 | But one bit isn't enough here. Be careful to avoid shifting outside |
65abff06 | 1856 | the mode and to avoid shifting outside the host wide int size. */ |
9caef960 | 1857 | |
91bc47b0 | 1858 | bits = (MIN (HOST_BITS_PER_WIDE_INT, GET_MODE_SIZE (mode) * 8) |
1859 | - floor_log2 (~ c) - 2); | |
1860 | if (bits > 0) | |
bf2a98b3 | 1861 | for (; bits > 0; bits--) |
91bc47b0 | 1862 | { |
8deb3959 | 1863 | new_const = c << bits; |
1864 | temp = alpha_emit_set_const (subtarget, mode, new_const, i, no_output); | |
91bc47b0 | 1865 | if (!temp) |
1866 | { | |
8deb3959 | 1867 | new_const = (c << bits) | (((HOST_WIDE_INT) 1 << bits) - 1); |
1868 | temp = alpha_emit_set_const (subtarget, mode, new_const, | |
91bc47b0 | 1869 | i, no_output); |
1870 | } | |
1871 | if (temp) | |
1872 | { | |
1873 | if (no_output) | |
1874 | return temp; | |
1875 | return expand_binop (mode, ashr_optab, temp, GEN_INT (bits), | |
1876 | target, 0, OPTAB_WIDEN); | |
1877 | } | |
1878 | } | |
bf2a98b3 | 1879 | } |
1880 | ||
bdb19034 | 1881 | #if HOST_BITS_PER_WIDE_INT == 64 |
1882 | /* Finally, see if can load a value into the target that is the same as the | |
1883 | constant except that all bytes that are 0 are changed to be 0xff. If we | |
1884 | can, then we can do a ZAPNOT to obtain the desired constant. */ | |
1885 | ||
8deb3959 | 1886 | new_const = c; |
bdb19034 | 1887 | for (i = 0; i < 64; i += 8) |
8deb3959 | 1888 | if ((new_const & ((HOST_WIDE_INT) 0xff << i)) == 0) |
1889 | new_const |= (HOST_WIDE_INT) 0xff << i; | |
e52799e9 | 1890 | |
bdb19034 | 1891 | /* We are only called for SImode and DImode. If this is SImode, ensure that |
1892 | we are sign extended to a full word. */ | |
1893 | ||
1894 | if (mode == SImode) | |
8deb3959 | 1895 | new_const = ((new_const & 0xffffffff) ^ 0x80000000) - 0x80000000; |
bdb19034 | 1896 | |
8deb3959 | 1897 | if (new_const != c) |
91bc47b0 | 1898 | { |
8deb3959 | 1899 | temp = alpha_emit_set_const (subtarget, mode, new_const, n - 1, no_output); |
91bc47b0 | 1900 | if (temp) |
1901 | { | |
1902 | if (no_output) | |
1903 | return temp; | |
8deb3959 | 1904 | return expand_binop (mode, and_optab, temp, GEN_INT (c | ~ new_const), |
91bc47b0 | 1905 | target, 0, OPTAB_WIDEN); |
1906 | } | |
1907 | } | |
bdb19034 | 1908 | #endif |
e52799e9 | 1909 | |
bf2a98b3 | 1910 | return 0; |
1911 | } | |
996a379d | 1912 | |
92643d95 | 1913 | /* Try to output insns to set TARGET equal to the constant C if it can be |
1914 | done in less than N insns. Do all computations in MODE. Returns the place | |
1915 | where the output has been placed if it can be done and the insns have been | |
1916 | emitted. If it would take more than N insns, zero is returned and no | |
1917 | insns and emitted. */ | |
1918 | ||
91bc47b0 | 1919 | static rtx |
92643d95 | 1920 | alpha_emit_set_const (rtx target, enum machine_mode mode, |
91bc47b0 | 1921 | HOST_WIDE_INT c, int n, bool no_output) |
92643d95 | 1922 | { |
91bc47b0 | 1923 | enum machine_mode orig_mode = mode; |
92643d95 | 1924 | rtx orig_target = target; |
91bc47b0 | 1925 | rtx result = 0; |
92643d95 | 1926 | int i; |
1927 | ||
1928 | /* If we can't make any pseudos, TARGET is an SImode hard register, we | |
1929 | can't load this constant in one insn, do this in DImode. */ | |
e1ba4a27 | 1930 | if (!can_create_pseudo_p () && mode == SImode |
c933fb42 | 1931 | && REG_P (target) && REGNO (target) < FIRST_PSEUDO_REGISTER) |
92643d95 | 1932 | { |
91bc47b0 | 1933 | result = alpha_emit_set_const_1 (target, mode, c, 1, no_output); |
1934 | if (result) | |
1935 | return result; | |
1936 | ||
1937 | target = no_output ? NULL : gen_lowpart (DImode, target); | |
1938 | mode = DImode; | |
1939 | } | |
1940 | else if (mode == V8QImode || mode == V4HImode || mode == V2SImode) | |
1941 | { | |
1942 | target = no_output ? NULL : gen_lowpart (DImode, target); | |
92643d95 | 1943 | mode = DImode; |
1944 | } | |
1945 | ||
1946 | /* Try 1 insn, then 2, then up to N. */ | |
1947 | for (i = 1; i <= n; i++) | |
1948 | { | |
91bc47b0 | 1949 | result = alpha_emit_set_const_1 (target, mode, c, i, no_output); |
92643d95 | 1950 | if (result) |
1951 | { | |
91bc47b0 | 1952 | rtx insn, set; |
1953 | ||
1954 | if (no_output) | |
1955 | return result; | |
1956 | ||
1957 | insn = get_last_insn (); | |
1958 | set = single_set (insn); | |
92643d95 | 1959 | if (! CONSTANT_P (SET_SRC (set))) |
1960 | set_unique_reg_note (get_last_insn (), REG_EQUAL, GEN_INT (c)); | |
1961 | break; | |
1962 | } | |
1963 | } | |
1964 | ||
1965 | /* Allow for the case where we changed the mode of TARGET. */ | |
91bc47b0 | 1966 | if (result) |
1967 | { | |
1968 | if (result == target) | |
1969 | result = orig_target; | |
1970 | else if (mode != orig_mode) | |
1971 | result = gen_lowpart (orig_mode, result); | |
1972 | } | |
92643d95 | 1973 | |
1974 | return result; | |
1975 | } | |
1976 | ||
2612f626 | 1977 | /* Having failed to find a 3 insn sequence in alpha_emit_set_const, |
1978 | fall back to a straight forward decomposition. We do this to avoid | |
1979 | exponential run times encountered when looking for longer sequences | |
1980 | with alpha_emit_set_const. */ | |
1981 | ||
91bc47b0 | 1982 | static rtx |
92643d95 | 1983 | alpha_emit_set_long_const (rtx target, HOST_WIDE_INT c1, HOST_WIDE_INT c2) |
2612f626 | 1984 | { |
2612f626 | 1985 | HOST_WIDE_INT d1, d2, d3, d4; |
2612f626 | 1986 | |
1987 | /* Decompose the entire word */ | |
af792316 | 1988 | #if HOST_BITS_PER_WIDE_INT >= 64 |
4d10b463 | 1989 | gcc_assert (c2 == -(c1 < 0)); |
af792316 | 1990 | d1 = ((c1 & 0xffff) ^ 0x8000) - 0x8000; |
1991 | c1 -= d1; | |
1992 | d2 = ((c1 & 0xffffffff) ^ 0x80000000) - 0x80000000; | |
1993 | c1 = (c1 - d2) >> 32; | |
1994 | d3 = ((c1 & 0xffff) ^ 0x8000) - 0x8000; | |
1995 | c1 -= d3; | |
1996 | d4 = ((c1 & 0xffffffff) ^ 0x80000000) - 0x80000000; | |
4d10b463 | 1997 | gcc_assert (c1 == d4); |
af792316 | 1998 | #else |
1999 | d1 = ((c1 & 0xffff) ^ 0x8000) - 0x8000; | |
2000 | c1 -= d1; | |
2001 | d2 = ((c1 & 0xffffffff) ^ 0x80000000) - 0x80000000; | |
4d10b463 | 2002 | gcc_assert (c1 == d2); |
af792316 | 2003 | c2 += (d2 < 0); |
2004 | d3 = ((c2 & 0xffff) ^ 0x8000) - 0x8000; | |
2005 | c2 -= d3; | |
2006 | d4 = ((c2 & 0xffffffff) ^ 0x80000000) - 0x80000000; | |
4d10b463 | 2007 | gcc_assert (c2 == d4); |
af792316 | 2008 | #endif |
2612f626 | 2009 | |
2010 | /* Construct the high word */ | |
af792316 | 2011 | if (d4) |
2012 | { | |
2013 | emit_move_insn (target, GEN_INT (d4)); | |
2014 | if (d3) | |
2015 | emit_move_insn (target, gen_rtx_PLUS (DImode, target, GEN_INT (d3))); | |
2016 | } | |
2612f626 | 2017 | else |
af792316 | 2018 | emit_move_insn (target, GEN_INT (d3)); |
2612f626 | 2019 | |
2020 | /* Shift it into place */ | |
af792316 | 2021 | emit_move_insn (target, gen_rtx_ASHIFT (DImode, target, GEN_INT (32))); |
2612f626 | 2022 | |
af792316 | 2023 | /* Add in the low bits. */ |
2024 | if (d2) | |
2025 | emit_move_insn (target, gen_rtx_PLUS (DImode, target, GEN_INT (d2))); | |
2026 | if (d1) | |
2027 | emit_move_insn (target, gen_rtx_PLUS (DImode, target, GEN_INT (d1))); | |
2612f626 | 2028 | |
af792316 | 2029 | return target; |
2612f626 | 2030 | } |
2612f626 | 2031 | |
91bc47b0 | 2032 | /* Given an integral CONST_INT, CONST_DOUBLE, or CONST_VECTOR, return |
2033 | the low 64 bits. */ | |
2034 | ||
2035 | static void | |
2036 | alpha_extract_integer (rtx x, HOST_WIDE_INT *p0, HOST_WIDE_INT *p1) | |
2037 | { | |
2038 | HOST_WIDE_INT i0, i1; | |
2039 | ||
2040 | if (GET_CODE (x) == CONST_VECTOR) | |
2041 | x = simplify_subreg (DImode, x, GET_MODE (x), 0); | |
2042 | ||
2043 | ||
c933fb42 | 2044 | if (CONST_INT_P (x)) |
91bc47b0 | 2045 | { |
2046 | i0 = INTVAL (x); | |
2047 | i1 = -(i0 < 0); | |
2048 | } | |
2049 | else if (HOST_BITS_PER_WIDE_INT >= 64) | |
2050 | { | |
2051 | i0 = CONST_DOUBLE_LOW (x); | |
2052 | i1 = -(i0 < 0); | |
2053 | } | |
2054 | else | |
2055 | { | |
2056 | i0 = CONST_DOUBLE_LOW (x); | |
2057 | i1 = CONST_DOUBLE_HIGH (x); | |
2058 | } | |
2059 | ||
2060 | *p0 = i0; | |
2061 | *p1 = i1; | |
2062 | } | |
2063 | ||
2064 | /* Implement LEGITIMATE_CONSTANT_P. This is all constants for which we | |
2065 | are willing to load the value into a register via a move pattern. | |
2066 | Normally this is all symbolic constants, integral constants that | |
2067 | take three or fewer instructions, and floating-point zero. */ | |
2068 | ||
2069 | bool | |
2070 | alpha_legitimate_constant_p (rtx x) | |
2071 | { | |
2072 | enum machine_mode mode = GET_MODE (x); | |
2073 | HOST_WIDE_INT i0, i1; | |
2074 | ||
2075 | switch (GET_CODE (x)) | |
2076 | { | |
91bc47b0 | 2077 | case LABEL_REF: |
91bc47b0 | 2078 | case HIGH: |
2079 | return true; | |
2080 | ||
75645350 | 2081 | case CONST: |
2082 | if (GET_CODE (XEXP (x, 0)) == PLUS | |
2083 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT) | |
2084 | x = XEXP (XEXP (x, 0), 0); | |
2085 | else | |
2086 | return true; | |
2087 | ||
2088 | if (GET_CODE (x) != SYMBOL_REF) | |
2089 | return true; | |
2090 | ||
2091 | /* FALLTHRU */ | |
2092 | ||
b5c0ec3d | 2093 | case SYMBOL_REF: |
2094 | /* TLS symbols are never valid. */ | |
2095 | return SYMBOL_REF_TLS_MODEL (x) == 0; | |
2096 | ||
91bc47b0 | 2097 | case CONST_DOUBLE: |
2098 | if (x == CONST0_RTX (mode)) | |
2099 | return true; | |
2100 | if (FLOAT_MODE_P (mode)) | |
2101 | return false; | |
2102 | goto do_integer; | |
2103 | ||
2104 | case CONST_VECTOR: | |
2105 | if (x == CONST0_RTX (mode)) | |
2106 | return true; | |
2107 | if (GET_MODE_CLASS (mode) != MODE_VECTOR_INT) | |
2108 | return false; | |
2109 | if (GET_MODE_SIZE (mode) != 8) | |
2110 | return false; | |
2111 | goto do_integer; | |
2112 | ||
2113 | case CONST_INT: | |
2114 | do_integer: | |
2115 | if (TARGET_BUILD_CONSTANTS) | |
2116 | return true; | |
2117 | alpha_extract_integer (x, &i0, &i1); | |
2118 | if (HOST_BITS_PER_WIDE_INT >= 64 || i1 == (-i0 < 0)) | |
2119 | return alpha_emit_set_const_1 (x, mode, i0, 3, true) != NULL; | |
2120 | return false; | |
2121 | ||
2122 | default: | |
2123 | return false; | |
2124 | } | |
2125 | } | |
2126 | ||
2127 | /* Operand 1 is known to be a constant, and should require more than one | |
2128 | instruction to load. Emit that multi-part load. */ | |
2129 | ||
2130 | bool | |
2131 | alpha_split_const_mov (enum machine_mode mode, rtx *operands) | |
2132 | { | |
2133 | HOST_WIDE_INT i0, i1; | |
2134 | rtx temp = NULL_RTX; | |
2135 | ||
2136 | alpha_extract_integer (operands[1], &i0, &i1); | |
2137 | ||
2138 | if (HOST_BITS_PER_WIDE_INT >= 64 || i1 == -(i0 < 0)) | |
2139 | temp = alpha_emit_set_const (operands[0], mode, i0, 3, false); | |
2140 | ||
2141 | if (!temp && TARGET_BUILD_CONSTANTS) | |
2142 | temp = alpha_emit_set_long_const (operands[0], i0, i1); | |
2143 | ||
2144 | if (temp) | |
2145 | { | |
2146 | if (!rtx_equal_p (operands[0], temp)) | |
2147 | emit_move_insn (operands[0], temp); | |
2148 | return true; | |
2149 | } | |
2150 | ||
2151 | return false; | |
2152 | } | |
2153 | ||
cb6e3ae1 | 2154 | /* Expand a move instruction; return true if all work is done. |
2155 | We don't handle non-bwx subword loads here. */ | |
2156 | ||
2157 | bool | |
92643d95 | 2158 | alpha_expand_mov (enum machine_mode mode, rtx *operands) |
cb6e3ae1 | 2159 | { |
f8fff44e | 2160 | rtx tmp; |
2161 | ||
cb6e3ae1 | 2162 | /* If the output is not a register, the input must be. */ |
c933fb42 | 2163 | if (MEM_P (operands[0]) |
cb6e3ae1 | 2164 | && ! reg_or_0_operand (operands[1], mode)) |
2165 | operands[1] = force_reg (mode, operands[1]); | |
2166 | ||
f5a60074 | 2167 | /* Allow legitimize_address to perform some simplifications. */ |
62e050c6 | 2168 | if (mode == Pmode && symbolic_operand (operands[1], mode)) |
1f0ce6a6 | 2169 | { |
41e3a0c7 | 2170 | tmp = alpha_legitimize_address_1 (operands[1], operands[0], mode); |
f5a60074 | 2171 | if (tmp) |
5dcb037d | 2172 | { |
5f7b9df8 | 2173 | if (tmp == operands[0]) |
2174 | return true; | |
f5a60074 | 2175 | operands[1] = tmp; |
8afb6db4 | 2176 | return false; |
2177 | } | |
1f0ce6a6 | 2178 | } |
2179 | ||
cb6e3ae1 | 2180 | /* Early out for non-constants and valid constants. */ |
2181 | if (! CONSTANT_P (operands[1]) || input_operand (operands[1], mode)) | |
2182 | return false; | |
2183 | ||
2184 | /* Split large integers. */ | |
c933fb42 | 2185 | if (CONST_INT_P (operands[1]) |
91bc47b0 | 2186 | || GET_CODE (operands[1]) == CONST_DOUBLE |
2187 | || GET_CODE (operands[1]) == CONST_VECTOR) | |
cb6e3ae1 | 2188 | { |
91bc47b0 | 2189 | if (alpha_split_const_mov (mode, operands)) |
2190 | return true; | |
cb6e3ae1 | 2191 | } |
2192 | ||
2193 | /* Otherwise we've nothing left but to drop the thing to memory. */ | |
f8fff44e | 2194 | tmp = force_const_mem (mode, operands[1]); |
2195 | ||
2196 | if (tmp == NULL_RTX) | |
2197 | return false; | |
2198 | ||
cb6e3ae1 | 2199 | if (reload_in_progress) |
2200 | { | |
f8fff44e | 2201 | emit_move_insn (operands[0], XEXP (tmp, 0)); |
2202 | operands[1] = replace_equiv_address (tmp, operands[0]); | |
cb6e3ae1 | 2203 | } |
2204 | else | |
f8fff44e | 2205 | operands[1] = validize_mem (tmp); |
cb6e3ae1 | 2206 | return false; |
2207 | } | |
2208 | ||
2209 | /* Expand a non-bwx QImode or HImode move instruction; | |
2210 | return true if all work is done. */ | |
2211 | ||
2212 | bool | |
92643d95 | 2213 | alpha_expand_mov_nobwx (enum machine_mode mode, rtx *operands) |
cb6e3ae1 | 2214 | { |
0d96cd2b | 2215 | rtx seq; |
2216 | ||
cb6e3ae1 | 2217 | /* If the output is not a register, the input must be. */ |
0d96cd2b | 2218 | if (MEM_P (operands[0])) |
cb6e3ae1 | 2219 | operands[1] = force_reg (mode, operands[1]); |
2220 | ||
2221 | /* Handle four memory cases, unaligned and aligned for either the input | |
2222 | or the output. The only case where we can be called during reload is | |
2223 | for aligned loads; all other cases require temporaries. */ | |
2224 | ||
0d96cd2b | 2225 | if (any_memory_operand (operands[1], mode)) |
cb6e3ae1 | 2226 | { |
2227 | if (aligned_memory_operand (operands[1], mode)) | |
2228 | { | |
2229 | if (reload_in_progress) | |
2230 | { | |
0d96cd2b | 2231 | if (mode == QImode) |
2232 | seq = gen_reload_inqi_aligned (operands[0], operands[1]); | |
2233 | else | |
2234 | seq = gen_reload_inhi_aligned (operands[0], operands[1]); | |
2235 | emit_insn (seq); | |
cb6e3ae1 | 2236 | } |
2237 | else | |
2238 | { | |
2239 | rtx aligned_mem, bitnum; | |
2240 | rtx scratch = gen_reg_rtx (SImode); | |
d67e1866 | 2241 | rtx subtarget; |
2242 | bool copyout; | |
cb6e3ae1 | 2243 | |
2244 | get_aligned_mem (operands[1], &aligned_mem, &bitnum); | |
2245 | ||
d67e1866 | 2246 | subtarget = operands[0]; |
c933fb42 | 2247 | if (REG_P (subtarget)) |
d67e1866 | 2248 | subtarget = gen_lowpart (DImode, subtarget), copyout = false; |
2249 | else | |
2250 | subtarget = gen_reg_rtx (DImode), copyout = true; | |
2251 | ||
0d96cd2b | 2252 | if (mode == QImode) |
2253 | seq = gen_aligned_loadqi (subtarget, aligned_mem, | |
2254 | bitnum, scratch); | |
2255 | else | |
2256 | seq = gen_aligned_loadhi (subtarget, aligned_mem, | |
2257 | bitnum, scratch); | |
2258 | emit_insn (seq); | |
d67e1866 | 2259 | |
2260 | if (copyout) | |
2261 | emit_move_insn (operands[0], gen_lowpart (mode, subtarget)); | |
cb6e3ae1 | 2262 | } |
2263 | } | |
2264 | else | |
2265 | { | |
2266 | /* Don't pass these as parameters since that makes the generated | |
2267 | code depend on parameter evaluation order which will cause | |
2268 | bootstrap failures. */ | |
2269 | ||
0d96cd2b | 2270 | rtx temp1, temp2, subtarget, ua; |
d67e1866 | 2271 | bool copyout; |
2272 | ||
2273 | temp1 = gen_reg_rtx (DImode); | |
2274 | temp2 = gen_reg_rtx (DImode); | |
cb6e3ae1 | 2275 | |
d67e1866 | 2276 | subtarget = operands[0]; |
c933fb42 | 2277 | if (REG_P (subtarget)) |
d67e1866 | 2278 | subtarget = gen_lowpart (DImode, subtarget), copyout = false; |
2279 | else | |
2280 | subtarget = gen_reg_rtx (DImode), copyout = true; | |
2281 | ||
0d96cd2b | 2282 | ua = get_unaligned_address (operands[1]); |
2283 | if (mode == QImode) | |
2284 | seq = gen_unaligned_loadqi (subtarget, ua, temp1, temp2); | |
2285 | else | |
2286 | seq = gen_unaligned_loadhi (subtarget, ua, temp1, temp2); | |
2287 | ||
cb6e3ae1 | 2288 | alpha_set_memflags (seq, operands[1]); |
2289 | emit_insn (seq); | |
d67e1866 | 2290 | |
2291 | if (copyout) | |
2292 | emit_move_insn (operands[0], gen_lowpart (mode, subtarget)); | |
cb6e3ae1 | 2293 | } |
2294 | return true; | |
2295 | } | |
2296 | ||
0d96cd2b | 2297 | if (any_memory_operand (operands[0], mode)) |
cb6e3ae1 | 2298 | { |
2299 | if (aligned_memory_operand (operands[0], mode)) | |
2300 | { | |
2301 | rtx aligned_mem, bitnum; | |
2302 | rtx temp1 = gen_reg_rtx (SImode); | |
2303 | rtx temp2 = gen_reg_rtx (SImode); | |
2304 | ||
2305 | get_aligned_mem (operands[0], &aligned_mem, &bitnum); | |
2306 | ||
2307 | emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum, | |
2308 | temp1, temp2)); | |
2309 | } | |
2310 | else | |
2311 | { | |
2312 | rtx temp1 = gen_reg_rtx (DImode); | |
2313 | rtx temp2 = gen_reg_rtx (DImode); | |
2314 | rtx temp3 = gen_reg_rtx (DImode); | |
0d96cd2b | 2315 | rtx ua = get_unaligned_address (operands[0]); |
2316 | ||
2317 | if (mode == QImode) | |
2318 | seq = gen_unaligned_storeqi (ua, operands[1], temp1, temp2, temp3); | |
2319 | else | |
2320 | seq = gen_unaligned_storehi (ua, operands[1], temp1, temp2, temp3); | |
cb6e3ae1 | 2321 | |
2322 | alpha_set_memflags (seq, operands[0]); | |
2323 | emit_insn (seq); | |
2324 | } | |
2325 | return true; | |
2326 | } | |
2327 | ||
2328 | return false; | |
2329 | } | |
2330 | ||
a31688d7 | 2331 | /* Implement the movmisalign patterns. One of the operands is a memory |
84846cff | 2332 | that is not naturally aligned. Emit instructions to load it. */ |
a31688d7 | 2333 | |
2334 | void | |
2335 | alpha_expand_movmisalign (enum machine_mode mode, rtx *operands) | |
2336 | { | |
2337 | /* Honor misaligned loads, for those we promised to do so. */ | |
2338 | if (MEM_P (operands[1])) | |
2339 | { | |
2340 | rtx tmp; | |
2341 | ||
2342 | if (register_operand (operands[0], mode)) | |
2343 | tmp = operands[0]; | |
2344 | else | |
2345 | tmp = gen_reg_rtx (mode); | |
2346 | ||
2347 | alpha_expand_unaligned_load (tmp, operands[1], 8, 0, 0); | |
2348 | if (tmp != operands[0]) | |
2349 | emit_move_insn (operands[0], tmp); | |
2350 | } | |
2351 | else if (MEM_P (operands[0])) | |
2352 | { | |
2353 | if (!reg_or_0_operand (operands[1], mode)) | |
2354 | operands[1] = force_reg (mode, operands[1]); | |
2355 | alpha_expand_unaligned_store (operands[0], operands[1], 8, 0); | |
2356 | } | |
2357 | else | |
2358 | gcc_unreachable (); | |
2359 | } | |
2360 | ||
2a42ba09 | 2361 | /* Generate an unsigned DImode to FP conversion. This is the same code |
2362 | optabs would emit if we didn't have TFmode patterns. | |
2363 | ||
2364 | For SFmode, this is the only construction I've found that can pass | |
2365 | gcc.c-torture/execute/ieee/rbug.c. No scenario that uses DFmode | |
2366 | intermediates will work, because you'll get intermediate rounding | |
2367 | that ruins the end result. Some of this could be fixed by turning | |
2368 | on round-to-positive-infinity, but that requires diddling the fpsr, | |
2369 | which kills performance. I tried turning this around and converting | |
2370 | to a negative number, so that I could turn on /m, but either I did | |
2371 | it wrong or there's something else cause I wound up with the exact | |
2372 | same single-bit error. There is a branch-less form of this same code: | |
2373 | ||
2374 | srl $16,1,$1 | |
2375 | and $16,1,$2 | |
2376 | cmplt $16,0,$3 | |
2377 | or $1,$2,$2 | |
2378 | cmovge $16,$16,$2 | |
2379 | itoft $3,$f10 | |
2380 | itoft $2,$f11 | |
2381 | cvtqs $f11,$f11 | |
2382 | adds $f11,$f11,$f0 | |
2383 | fcmoveq $f10,$f11,$f0 | |
2384 | ||
2385 | I'm not using it because it's the same number of instructions as | |
2386 | this branch-full form, and it has more serialized long latency | |
2387 | instructions on the critical path. | |
2388 | ||
2389 | For DFmode, we can avoid rounding errors by breaking up the word | |
2390 | into two pieces, converting them separately, and adding them back: | |
2391 | ||
2392 | LC0: .long 0,0x5f800000 | |
2393 | ||
2394 | itoft $16,$f11 | |
2395 | lda $2,LC0 | |
093c0196 | 2396 | cmplt $16,0,$1 |
2a42ba09 | 2397 | cpyse $f11,$f31,$f10 |
2398 | cpyse $f31,$f11,$f11 | |
2399 | s4addq $1,$2,$1 | |
2400 | lds $f12,0($1) | |
2401 | cvtqt $f10,$f10 | |
2402 | cvtqt $f11,$f11 | |
2403 | addt $f12,$f10,$f0 | |
2404 | addt $f0,$f11,$f0 | |
2405 | ||
2406 | This doesn't seem to be a clear-cut win over the optabs form. | |
2407 | It probably all depends on the distribution of numbers being | |
2408 | converted -- in the optabs form, all but high-bit-set has a | |
2409 | much lower minimum execution time. */ | |
2410 | ||
2411 | void | |
92643d95 | 2412 | alpha_emit_floatuns (rtx operands[2]) |
2a42ba09 | 2413 | { |
2414 | rtx neglab, donelab, i0, i1, f0, in, out; | |
2415 | enum machine_mode mode; | |
2416 | ||
2417 | out = operands[0]; | |
8e2025b4 | 2418 | in = force_reg (DImode, operands[1]); |
2a42ba09 | 2419 | mode = GET_MODE (out); |
2420 | neglab = gen_label_rtx (); | |
2421 | donelab = gen_label_rtx (); | |
2422 | i0 = gen_reg_rtx (DImode); | |
2423 | i1 = gen_reg_rtx (DImode); | |
2424 | f0 = gen_reg_rtx (mode); | |
2425 | ||
7e69f45b | 2426 | emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, DImode, 0, neglab); |
2a42ba09 | 2427 | |
2428 | emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_FLOAT (mode, in))); | |
2429 | emit_jump_insn (gen_jump (donelab)); | |
093c0196 | 2430 | emit_barrier (); |
2a42ba09 | 2431 | |
2432 | emit_label (neglab); | |
2433 | ||
2434 | emit_insn (gen_lshrdi3 (i0, in, const1_rtx)); | |
2435 | emit_insn (gen_anddi3 (i1, in, const1_rtx)); | |
2436 | emit_insn (gen_iordi3 (i0, i0, i1)); | |
2437 | emit_insn (gen_rtx_SET (VOIDmode, f0, gen_rtx_FLOAT (mode, i0))); | |
2438 | emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_PLUS (mode, f0, f0))); | |
2439 | ||
2440 | emit_label (donelab); | |
2441 | } | |
2442 | ||
3a2a3a7f | 2443 | /* Generate the comparison for a conditional branch. */ |
2444 | ||
74f4459c | 2445 | void |
2446 | alpha_emit_conditional_branch (rtx operands[], enum machine_mode cmp_mode) | |
3a2a3a7f | 2447 | { |
2448 | enum rtx_code cmp_code, branch_code; | |
74f4459c | 2449 | enum machine_mode branch_mode = VOIDmode; |
2450 | enum rtx_code code = GET_CODE (operands[0]); | |
2451 | rtx op0 = operands[1], op1 = operands[2]; | |
3a2a3a7f | 2452 | rtx tem; |
2453 | ||
74f4459c | 2454 | if (cmp_mode == TFmode) |
915c336f | 2455 | { |
8c3428a6 | 2456 | op0 = alpha_emit_xfloating_compare (&code, op0, op1); |
915c336f | 2457 | op1 = const0_rtx; |
74f4459c | 2458 | cmp_mode = DImode; |
915c336f | 2459 | } |
2460 | ||
3a2a3a7f | 2461 | /* The general case: fold the comparison code to the types of compares |
2462 | that we have, choosing the branch as necessary. */ | |
2463 | switch (code) | |
2464 | { | |
2465 | case EQ: case LE: case LT: case LEU: case LTU: | |
a4110d9a | 2466 | case UNORDERED: |
3a2a3a7f | 2467 | /* We have these compares: */ |
2468 | cmp_code = code, branch_code = NE; | |
2469 | break; | |
2470 | ||
2471 | case NE: | |
a4110d9a | 2472 | case ORDERED: |
65abff06 | 2473 | /* These must be reversed. */ |
a4110d9a | 2474 | cmp_code = reverse_condition (code), branch_code = EQ; |
3a2a3a7f | 2475 | break; |
2476 | ||
2477 | case GE: case GT: case GEU: case GTU: | |
2478 | /* For FP, we swap them, for INT, we reverse them. */ | |
74f4459c | 2479 | if (cmp_mode == DFmode) |
3a2a3a7f | 2480 | { |
2481 | cmp_code = swap_condition (code); | |
2482 | branch_code = NE; | |
2483 | tem = op0, op0 = op1, op1 = tem; | |
2484 | } | |
2485 | else | |
2486 | { | |
2487 | cmp_code = reverse_condition (code); | |
2488 | branch_code = EQ; | |
2489 | } | |
2490 | break; | |
2491 | ||
2492 | default: | |
4d10b463 | 2493 | gcc_unreachable (); |
3a2a3a7f | 2494 | } |
2495 | ||
74f4459c | 2496 | if (cmp_mode == DFmode) |
3a2a3a7f | 2497 | { |
70ce4162 | 2498 | if (flag_unsafe_math_optimizations && cmp_code != UNORDERED) |
3a2a3a7f | 2499 | { |
2500 | /* When we are not as concerned about non-finite values, and we | |
2501 | are comparing against zero, we can branch directly. */ | |
2502 | if (op1 == CONST0_RTX (DFmode)) | |
21f1e711 | 2503 | cmp_code = UNKNOWN, branch_code = code; |
3a2a3a7f | 2504 | else if (op0 == CONST0_RTX (DFmode)) |
2505 | { | |
2506 | /* Undo the swap we probably did just above. */ | |
2507 | tem = op0, op0 = op1, op1 = tem; | |
4899654e | 2508 | branch_code = swap_condition (cmp_code); |
21f1e711 | 2509 | cmp_code = UNKNOWN; |
3a2a3a7f | 2510 | } |
2511 | } | |
2512 | else | |
2513 | { | |
d30e015b | 2514 | /* ??? We mark the branch mode to be CCmode to prevent the |
9e7454d0 | 2515 | compare and branch from being combined, since the compare |
3a2a3a7f | 2516 | insn follows IEEE rules that the branch does not. */ |
2517 | branch_mode = CCmode; | |
2518 | } | |
2519 | } | |
2520 | else | |
2521 | { | |
3a2a3a7f | 2522 | /* The following optimizations are only for signed compares. */ |
2523 | if (code != LEU && code != LTU && code != GEU && code != GTU) | |
2524 | { | |
2525 | /* Whee. Compare and branch against 0 directly. */ | |
2526 | if (op1 == const0_rtx) | |
21f1e711 | 2527 | cmp_code = UNKNOWN, branch_code = code; |
3a2a3a7f | 2528 | |
3a2f3420 | 2529 | /* If the constants doesn't fit into an immediate, but can |
2530 | be generated by lda/ldah, we adjust the argument and | |
2531 | compare against zero, so we can use beq/bne directly. */ | |
62350d6c | 2532 | /* ??? Don't do this when comparing against symbols, otherwise |
2533 | we'll reduce (&x == 0x1234) to (&x-0x1234 == 0), which will | |
2534 | be declared false out of hand (at least for non-weak). */ | |
c933fb42 | 2535 | else if (CONST_INT_P (op1) |
62350d6c | 2536 | && (code == EQ || code == NE) |
2537 | && !(symbolic_operand (op0, VOIDmode) | |
c933fb42 | 2538 | || (REG_P (op0) && REG_POINTER (op0)))) |
3a2a3a7f | 2539 | { |
1dffd068 | 2540 | rtx n_op1 = GEN_INT (-INTVAL (op1)); |
2541 | ||
2542 | if (! satisfies_constraint_I (op1) | |
2543 | && (satisfies_constraint_K (n_op1) | |
2544 | || satisfies_constraint_L (n_op1))) | |
2545 | cmp_code = PLUS, branch_code = code, op1 = n_op1; | |
3a2a3a7f | 2546 | } |
2547 | } | |
3a2a3a7f | 2548 | |
d74ce6fa | 2549 | if (!reg_or_0_operand (op0, DImode)) |
2550 | op0 = force_reg (DImode, op0); | |
2551 | if (cmp_code != PLUS && !reg_or_8bit_operand (op1, DImode)) | |
2552 | op1 = force_reg (DImode, op1); | |
2553 | } | |
3a2a3a7f | 2554 | |
2555 | /* Emit an initial compare instruction, if necessary. */ | |
2556 | tem = op0; | |
21f1e711 | 2557 | if (cmp_code != UNKNOWN) |
3a2a3a7f | 2558 | { |
2559 | tem = gen_reg_rtx (cmp_mode); | |
2560 | emit_move_insn (tem, gen_rtx_fmt_ee (cmp_code, cmp_mode, op0, op1)); | |
2561 | } | |
2562 | ||
74f4459c | 2563 | /* Emit the branch instruction. */ |
2564 | tem = gen_rtx_SET (VOIDmode, pc_rtx, | |
2565 | gen_rtx_IF_THEN_ELSE (VOIDmode, | |
2566 | gen_rtx_fmt_ee (branch_code, | |
2567 | branch_mode, tem, | |
2568 | CONST0_RTX (cmp_mode)), | |
2569 | gen_rtx_LABEL_REF (VOIDmode, | |
2570 | operands[3]), | |
2571 | pc_rtx)); | |
2572 | emit_jump_insn (tem); | |
3a2a3a7f | 2573 | } |
2574 | ||
d74ce6fa | 2575 | /* Certain simplifications can be done to make invalid setcc operations |
2576 | valid. Return the final comparison, or NULL if we can't work. */ | |
2577 | ||
74f4459c | 2578 | bool |
2579 | alpha_emit_setcc (rtx operands[], enum machine_mode cmp_mode) | |
d74ce6fa | 2580 | { |
2581 | enum rtx_code cmp_code; | |
74f4459c | 2582 | enum rtx_code code = GET_CODE (operands[1]); |
2583 | rtx op0 = operands[2], op1 = operands[3]; | |
d74ce6fa | 2584 | rtx tmp; |
2585 | ||
74f4459c | 2586 | if (cmp_mode == TFmode) |
d74ce6fa | 2587 | { |
8c3428a6 | 2588 | op0 = alpha_emit_xfloating_compare (&code, op0, op1); |
d74ce6fa | 2589 | op1 = const0_rtx; |
74f4459c | 2590 | cmp_mode = DImode; |
d74ce6fa | 2591 | } |
2592 | ||
74f4459c | 2593 | if (cmp_mode == DFmode && !TARGET_FIX) |
2594 | return 0; | |
d74ce6fa | 2595 | |
2596 | /* The general case: fold the comparison code to the types of compares | |
2597 | that we have, choosing the branch as necessary. */ | |
2598 | ||
21f1e711 | 2599 | cmp_code = UNKNOWN; |
d74ce6fa | 2600 | switch (code) |
2601 | { | |
2602 | case EQ: case LE: case LT: case LEU: case LTU: | |
2603 | case UNORDERED: | |
2604 | /* We have these compares. */ | |
74f4459c | 2605 | if (cmp_mode == DFmode) |
d74ce6fa | 2606 | cmp_code = code, code = NE; |
2607 | break; | |
2608 | ||
2609 | case NE: | |
74f4459c | 2610 | if (cmp_mode == DImode && op1 == const0_rtx) |
d74ce6fa | 2611 | break; |
8e262b5e | 2612 | /* FALLTHRU */ |
d74ce6fa | 2613 | |
2614 | case ORDERED: | |
2615 | cmp_code = reverse_condition (code); | |
2616 | code = EQ; | |
2617 | break; | |
2618 | ||
2619 | case GE: case GT: case GEU: case GTU: | |
75b3314a | 2620 | /* These normally need swapping, but for integer zero we have |
bc882521 | 2621 | special patterns that recognize swapped operands. */ |
74f4459c | 2622 | if (cmp_mode == DImode && op1 == const0_rtx) |
bc882521 | 2623 | break; |
d74ce6fa | 2624 | code = swap_condition (code); |
74f4459c | 2625 | if (cmp_mode == DFmode) |
d74ce6fa | 2626 | cmp_code = code, code = NE; |
2627 | tmp = op0, op0 = op1, op1 = tmp; | |
2628 | break; | |
2629 | ||
2630 | default: | |
4d10b463 | 2631 | gcc_unreachable (); |
d74ce6fa | 2632 | } |
2633 | ||
74f4459c | 2634 | if (cmp_mode == DImode) |
d74ce6fa | 2635 | { |
bc882521 | 2636 | if (!register_operand (op0, DImode)) |
d74ce6fa | 2637 | op0 = force_reg (DImode, op0); |
2638 | if (!reg_or_8bit_operand (op1, DImode)) | |
2639 | op1 = force_reg (DImode, op1); | |
2640 | } | |
2641 | ||
2642 | /* Emit an initial compare instruction, if necessary. */ | |
21f1e711 | 2643 | if (cmp_code != UNKNOWN) |
d74ce6fa | 2644 | { |
74f4459c | 2645 | tmp = gen_reg_rtx (cmp_mode); |
d74ce6fa | 2646 | emit_insn (gen_rtx_SET (VOIDmode, tmp, |
74f4459c | 2647 | gen_rtx_fmt_ee (cmp_code, cmp_mode, op0, op1))); |
d74ce6fa | 2648 | |
eb0e7e5d | 2649 | op0 = cmp_mode != DImode ? gen_lowpart (DImode, tmp) : tmp; |
d74ce6fa | 2650 | op1 = const0_rtx; |
2651 | } | |
2652 | ||
74f4459c | 2653 | /* Emit the setcc instruction. */ |
2654 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], | |
2655 | gen_rtx_fmt_ee (code, DImode, op0, op1))); | |
2656 | return true; | |
d74ce6fa | 2657 | } |
2658 | ||
3a2a3a7f | 2659 | |
996a379d | 2660 | /* Rewrite a comparison against zero CMP of the form |
2661 | (CODE (cc0) (const_int 0)) so it can be written validly in | |
2662 | a conditional move (if_then_else CMP ...). | |
e3e08e7f | 2663 | If both of the operands that set cc0 are nonzero we must emit |
996a379d | 2664 | an insn to perform the compare (it can't be done within |
65abff06 | 2665 | the conditional move). */ |
92643d95 | 2666 | |
996a379d | 2667 | rtx |
92643d95 | 2668 | alpha_emit_conditional_move (rtx cmp, enum machine_mode mode) |
996a379d | 2669 | { |
23be97c5 | 2670 | enum rtx_code code = GET_CODE (cmp); |
c60bc286 | 2671 | enum rtx_code cmov_code = NE; |
74f4459c | 2672 | rtx op0 = XEXP (cmp, 0); |
2673 | rtx op1 = XEXP (cmp, 1); | |
23be97c5 | 2674 | enum machine_mode cmp_mode |
2675 | = (GET_MODE (op0) == VOIDmode ? DImode : GET_MODE (op0)); | |
3a2a3a7f | 2676 | enum machine_mode cmov_mode = VOIDmode; |
7f3be425 | 2677 | int local_fast_math = flag_unsafe_math_optimizations; |
23be97c5 | 2678 | rtx tem; |
996a379d | 2679 | |
a717c371 | 2680 | if (cmp_mode == TFmode) |
2681 | { | |
2682 | op0 = alpha_emit_xfloating_compare (&code, op0, op1); | |
2683 | op1 = const0_rtx; | |
2684 | cmp_mode = DImode; | |
2685 | } | |
2686 | ||
74f4459c | 2687 | gcc_assert (cmp_mode == DFmode || cmp_mode == DImode); |
b18b881f | 2688 | |
74f4459c | 2689 | if (FLOAT_MODE_P (cmp_mode) != FLOAT_MODE_P (mode)) |
d6cc9868 | 2690 | { |
2691 | enum rtx_code cmp_code; | |
2692 | ||
2693 | if (! TARGET_FIX) | |
2694 | return 0; | |
2695 | ||
2696 | /* If we have fp<->int register move instructions, do a cmov by | |
2697 | performing the comparison in fp registers, and move the | |
e3e08e7f | 2698 | zero/nonzero value to integer registers, where we can then |
d6cc9868 | 2699 | use a normal cmov, or vice-versa. */ |
2700 | ||
2701 | switch (code) | |
2702 | { | |
2703 | case EQ: case LE: case LT: case LEU: case LTU: | |
2704 | /* We have these compares. */ | |
2705 | cmp_code = code, code = NE; | |
2706 | break; | |
2707 | ||
2708 | case NE: | |
2709 | /* This must be reversed. */ | |
2710 | cmp_code = EQ, code = EQ; | |
2711 | break; | |
2712 | ||
2713 | case GE: case GT: case GEU: case GTU: | |
75b3314a | 2714 | /* These normally need swapping, but for integer zero we have |
2715 | special patterns that recognize swapped operands. */ | |
74f4459c | 2716 | if (cmp_mode == DImode && op1 == const0_rtx) |
88f8f2a2 | 2717 | cmp_code = code, code = NE; |
2718 | else | |
2719 | { | |
2720 | cmp_code = swap_condition (code); | |
2721 | code = NE; | |
2722 | tem = op0, op0 = op1, op1 = tem; | |
2723 | } | |
d6cc9868 | 2724 | break; |
2725 | ||
2726 | default: | |
4d10b463 | 2727 | gcc_unreachable (); |
d6cc9868 | 2728 | } |
2729 | ||
74f4459c | 2730 | tem = gen_reg_rtx (cmp_mode); |
d6cc9868 | 2731 | emit_insn (gen_rtx_SET (VOIDmode, tem, |
74f4459c | 2732 | gen_rtx_fmt_ee (cmp_code, cmp_mode, |
d6cc9868 | 2733 | op0, op1))); |
2734 | ||
74f4459c | 2735 | cmp_mode = cmp_mode == DImode ? DFmode : DImode; |
2736 | op0 = gen_lowpart (cmp_mode, tem); | |
2737 | op1 = CONST0_RTX (cmp_mode); | |
d6cc9868 | 2738 | local_fast_math = 1; |
2739 | } | |
996a379d | 2740 | |
2741 | /* We may be able to use a conditional move directly. | |
65abff06 | 2742 | This avoids emitting spurious compares. */ |
2a42ba09 | 2743 | if (signed_comparison_operator (cmp, VOIDmode) |
74f4459c | 2744 | && (cmp_mode == DImode || local_fast_math) |
23be97c5 | 2745 | && (op0 == CONST0_RTX (cmp_mode) || op1 == CONST0_RTX (cmp_mode))) |
941522d6 | 2746 | return gen_rtx_fmt_ee (code, VOIDmode, op0, op1); |
996a379d | 2747 | |
3029ee00 | 2748 | /* We can't put the comparison inside the conditional move; |
996a379d | 2749 | emit a compare instruction and put that inside the |
23be97c5 | 2750 | conditional move. Make sure we emit only comparisons we have; |
2751 | swap or reverse as necessary. */ | |
996a379d | 2752 | |
e1ba4a27 | 2753 | if (!can_create_pseudo_p ()) |
3029ee00 | 2754 | return NULL_RTX; |
2755 | ||
996a379d | 2756 | switch (code) |
2757 | { | |
23be97c5 | 2758 | case EQ: case LE: case LT: case LEU: case LTU: |
2759 | /* We have these compares: */ | |
996a379d | 2760 | break; |
23be97c5 | 2761 | |
996a379d | 2762 | case NE: |
65abff06 | 2763 | /* This must be reversed. */ |
23be97c5 | 2764 | code = reverse_condition (code); |
c60bc286 | 2765 | cmov_code = EQ; |
996a379d | 2766 | break; |
23be97c5 | 2767 | |
2768 | case GE: case GT: case GEU: case GTU: | |
d74ce6fa | 2769 | /* These must be swapped. */ |
88f8f2a2 | 2770 | if (op1 != CONST0_RTX (cmp_mode)) |
2771 | { | |
2772 | code = swap_condition (code); | |
2773 | tem = op0, op0 = op1, op1 = tem; | |
2774 | } | |
996a379d | 2775 | break; |
23be97c5 | 2776 | |
996a379d | 2777 | default: |
4d10b463 | 2778 | gcc_unreachable (); |
996a379d | 2779 | } |
2780 | ||
74f4459c | 2781 | if (cmp_mode == DImode) |
d74ce6fa | 2782 | { |
2783 | if (!reg_or_0_operand (op0, DImode)) | |
2784 | op0 = force_reg (DImode, op0); | |
2785 | if (!reg_or_8bit_operand (op1, DImode)) | |
2786 | op1 = force_reg (DImode, op1); | |
2787 | } | |
2788 | ||
b9b4428b | 2789 | /* ??? We mark the branch mode to be CCmode to prevent the compare |
3a2a3a7f | 2790 | and cmov from being combined, since the compare insn follows IEEE |
2791 | rules that the cmov does not. */ | |
74f4459c | 2792 | if (cmp_mode == DFmode && !local_fast_math) |
3a2a3a7f | 2793 | cmov_mode = CCmode; |
2794 | ||
74f4459c | 2795 | tem = gen_reg_rtx (cmp_mode); |
2796 | emit_move_insn (tem, gen_rtx_fmt_ee (code, cmp_mode, op0, op1)); | |
2797 | return gen_rtx_fmt_ee (cmov_code, cmov_mode, tem, CONST0_RTX (cmp_mode)); | |
996a379d | 2798 | } |
bbf31a61 | 2799 | |
2800 | /* Simplify a conditional move of two constants into a setcc with | |
2801 | arithmetic. This is done with a splitter since combine would | |
2802 | just undo the work if done during code generation. It also catches | |
2803 | cases we wouldn't have before cse. */ | |
2804 | ||
2805 | int | |
92643d95 | 2806 | alpha_split_conditional_move (enum rtx_code code, rtx dest, rtx cond, |
2807 | rtx t_rtx, rtx f_rtx) | |
bbf31a61 | 2808 | { |
2809 | HOST_WIDE_INT t, f, diff; | |
2810 | enum machine_mode mode; | |
2811 | rtx target, subtarget, tmp; | |
2812 | ||
2813 | mode = GET_MODE (dest); | |
2814 | t = INTVAL (t_rtx); | |
2815 | f = INTVAL (f_rtx); | |
2816 | diff = t - f; | |
2817 | ||
2818 | if (((code == NE || code == EQ) && diff < 0) | |
2819 | || (code == GE || code == GT)) | |
2820 | { | |
2821 | code = reverse_condition (code); | |
2822 | diff = t, t = f, f = diff; | |
2823 | diff = t - f; | |
2824 | } | |
2825 | ||
2826 | subtarget = target = dest; | |
2827 | if (mode != DImode) | |
2828 | { | |
2829 | target = gen_lowpart (DImode, dest); | |
e1ba4a27 | 2830 | if (can_create_pseudo_p ()) |
bbf31a61 | 2831 | subtarget = gen_reg_rtx (DImode); |
2832 | else | |
2833 | subtarget = target; | |
2834 | } | |
64656695 | 2835 | /* Below, we must be careful to use copy_rtx on target and subtarget |
2836 | in intermediate insns, as they may be a subreg rtx, which may not | |
2837 | be shared. */ | |
bbf31a61 | 2838 | |
2839 | if (f == 0 && exact_log2 (diff) > 0 | |
8d232dc7 | 2840 | /* On EV6, we've got enough shifters to make non-arithmetic shifts |
bbf31a61 | 2841 | viable over a longer latency cmove. On EV5, the E0 slot is a |
65abff06 | 2842 | scarce resource, and on EV4 shift has the same latency as a cmove. */ |
fb64edde | 2843 | && (diff <= 8 || alpha_tune == PROCESSOR_EV6)) |
bbf31a61 | 2844 | { |
2845 | tmp = gen_rtx_fmt_ee (code, DImode, cond, const0_rtx); | |
64656695 | 2846 | emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (subtarget), tmp)); |
bbf31a61 | 2847 | |
64656695 | 2848 | tmp = gen_rtx_ASHIFT (DImode, copy_rtx (subtarget), |
2849 | GEN_INT (exact_log2 (t))); | |
bbf31a61 | 2850 | emit_insn (gen_rtx_SET (VOIDmode, target, tmp)); |
2851 | } | |
2852 | else if (f == 0 && t == -1) | |
2853 | { | |
2854 | tmp = gen_rtx_fmt_ee (code, DImode, cond, const0_rtx); | |
64656695 | 2855 | emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (subtarget), tmp)); |
bbf31a61 | 2856 | |
64656695 | 2857 | emit_insn (gen_negdi2 (target, copy_rtx (subtarget))); |
bbf31a61 | 2858 | } |
2859 | else if (diff == 1 || diff == 4 || diff == 8) | |
2860 | { | |
2861 | rtx add_op; | |
2862 | ||
2863 | tmp = gen_rtx_fmt_ee (code, DImode, cond, const0_rtx); | |
64656695 | 2864 | emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (subtarget), tmp)); |
bbf31a61 | 2865 | |
2866 | if (diff == 1) | |
64656695 | 2867 | emit_insn (gen_adddi3 (target, copy_rtx (subtarget), GEN_INT (f))); |
bbf31a61 | 2868 | else |
2869 | { | |
2870 | add_op = GEN_INT (f); | |
2871 | if (sext_add_operand (add_op, mode)) | |
2872 | { | |
64656695 | 2873 | tmp = gen_rtx_MULT (DImode, copy_rtx (subtarget), |
2874 | GEN_INT (diff)); | |
bbf31a61 | 2875 | tmp = gen_rtx_PLUS (DImode, tmp, add_op); |
2876 | emit_insn (gen_rtx_SET (VOIDmode, target, tmp)); | |
2877 | } | |
2878 | else | |
2879 | return 0; | |
2880 | } | |
2881 | } | |
2882 | else | |
2883 | return 0; | |
2884 | ||
2885 | return 1; | |
2886 | } | |
34377880 | 2887 | \f |
915c336f | 2888 | /* Look up the function X_floating library function name for the |
2889 | given operation. */ | |
2890 | ||
fb1e4f4a | 2891 | struct GTY(()) xfloating_op |
2d7c492e | 2892 | { |
2893 | const enum rtx_code code; | |
7035b2ab | 2894 | const char *const GTY((skip)) osf_func; |
2895 | const char *const GTY((skip)) vms_func; | |
2d7c492e | 2896 | rtx libcall; |
2897 | }; | |
2898 | ||
9e7454d0 | 2899 | static GTY(()) struct xfloating_op xfloating_ops[] = |
2d7c492e | 2900 | { |
2901 | { PLUS, "_OtsAddX", "OTS$ADD_X", 0 }, | |
2902 | { MINUS, "_OtsSubX", "OTS$SUB_X", 0 }, | |
2903 | { MULT, "_OtsMulX", "OTS$MUL_X", 0 }, | |
2904 | { DIV, "_OtsDivX", "OTS$DIV_X", 0 }, | |
2905 | { EQ, "_OtsEqlX", "OTS$EQL_X", 0 }, | |
2906 | { NE, "_OtsNeqX", "OTS$NEQ_X", 0 }, | |
2907 | { LT, "_OtsLssX", "OTS$LSS_X", 0 }, | |
2908 | { LE, "_OtsLeqX", "OTS$LEQ_X", 0 }, | |
2909 | { GT, "_OtsGtrX", "OTS$GTR_X", 0 }, | |
2910 | { GE, "_OtsGeqX", "OTS$GEQ_X", 0 }, | |
2911 | { FIX, "_OtsCvtXQ", "OTS$CVTXQ", 0 }, | |
2912 | { FLOAT, "_OtsCvtQX", "OTS$CVTQX", 0 }, | |
2913 | { UNSIGNED_FLOAT, "_OtsCvtQUX", "OTS$CVTQUX", 0 }, | |
2914 | { FLOAT_EXTEND, "_OtsConvertFloatTX", "OTS$CVT_FLOAT_T_X", 0 }, | |
2915 | { FLOAT_TRUNCATE, "_OtsConvertFloatXT", "OTS$CVT_FLOAT_X_T", 0 } | |
2916 | }; | |
2917 | ||
2918 | static GTY(()) struct xfloating_op vax_cvt_ops[] = | |
2919 | { | |
2920 | { FLOAT_EXTEND, "_OtsConvertFloatGX", "OTS$CVT_FLOAT_G_X", 0 }, | |
2921 | { FLOAT_TRUNCATE, "_OtsConvertFloatXG", "OTS$CVT_FLOAT_X_G", 0 } | |
2922 | }; | |
2923 | ||
2924 | static rtx | |
92643d95 | 2925 | alpha_lookup_xfloating_lib_func (enum rtx_code code) |
915c336f | 2926 | { |
2d7c492e | 2927 | struct xfloating_op *ops = xfloating_ops; |
2928 | long n = ARRAY_SIZE (xfloating_ops); | |
915c336f | 2929 | long i; |
2930 | ||
8c3428a6 | 2931 | gcc_assert (TARGET_HAS_XFLOATING_LIBS); |
2932 | ||
2d7c492e | 2933 | /* How irritating. Nothing to key off for the main table. */ |
2934 | if (TARGET_FLOAT_VAX && (code == FLOAT_EXTEND || code == FLOAT_TRUNCATE)) | |
915c336f | 2935 | { |
2d7c492e | 2936 | ops = vax_cvt_ops; |
2937 | n = ARRAY_SIZE (vax_cvt_ops); | |
915c336f | 2938 | } |
2939 | ||
2d7c492e | 2940 | for (i = 0; i < n; ++i, ++ops) |
2941 | if (ops->code == code) | |
2942 | { | |
2943 | rtx func = ops->libcall; | |
2944 | if (!func) | |
2945 | { | |
2946 | func = init_one_libfunc (TARGET_ABI_OPEN_VMS | |
2947 | ? ops->vms_func : ops->osf_func); | |
2948 | ops->libcall = func; | |
2949 | } | |
2950 | return func; | |
2951 | } | |
915c336f | 2952 | |
4d10b463 | 2953 | gcc_unreachable (); |
915c336f | 2954 | } |
2955 | ||
2956 | /* Most X_floating operations take the rounding mode as an argument. | |
2957 | Compute that here. */ | |
2958 | ||
2959 | static int | |
92643d95 | 2960 | alpha_compute_xfloating_mode_arg (enum rtx_code code, |
2961 | enum alpha_fp_rounding_mode round) | |
915c336f | 2962 | { |
2963 | int mode; | |
2964 | ||
2965 | switch (round) | |
2966 | { | |
2967 | case ALPHA_FPRM_NORM: | |
2968 | mode = 2; | |
2969 | break; | |
2970 | case ALPHA_FPRM_MINF: | |
2971 | mode = 1; | |
2972 | break; | |
2973 | case ALPHA_FPRM_CHOP: | |
2974 | mode = 0; | |
2975 | break; | |
2976 | case ALPHA_FPRM_DYN: | |
2977 | mode = 4; | |
2978 | break; | |
2979 | default: | |
4d10b463 | 2980 | gcc_unreachable (); |
915c336f | 2981 | |
2982 | /* XXX For reference, round to +inf is mode = 3. */ | |
2983 | } | |
2984 | ||
2985 | if (code == FLOAT_TRUNCATE && alpha_fptm == ALPHA_FPTM_N) | |
2986 | mode |= 0x10000; | |
2987 | ||
2988 | return mode; | |
2989 | } | |
2990 | ||
2991 | /* Emit an X_floating library function call. | |
2992 | ||
2993 | Note that these functions do not follow normal calling conventions: | |
2994 | TFmode arguments are passed in two integer registers (as opposed to | |
9e7454d0 | 2995 | indirect); TFmode return values appear in R16+R17. |
915c336f | 2996 | |
2d7c492e | 2997 | FUNC is the function to call. |
915c336f | 2998 | TARGET is where the output belongs. |
2999 | OPERANDS are the inputs. | |
3000 | NOPERANDS is the count of inputs. | |
3001 | EQUIV is the expression equivalent for the function. | |
3002 | */ | |
3003 | ||
3004 | static void | |
2d7c492e | 3005 | alpha_emit_xfloating_libcall (rtx func, rtx target, rtx operands[], |
92643d95 | 3006 | int noperands, rtx equiv) |
915c336f | 3007 | { |
3008 | rtx usage = NULL_RTX, tmp, reg; | |
3009 | int regno = 16, i; | |
3010 | ||
3011 | start_sequence (); | |
3012 | ||
3013 | for (i = 0; i < noperands; ++i) | |
3014 | { | |
3015 | switch (GET_MODE (operands[i])) | |
3016 | { | |
3017 | case TFmode: | |
3018 | reg = gen_rtx_REG (TFmode, regno); | |
3019 | regno += 2; | |
3020 | break; | |
3021 | ||
3022 | case DFmode: | |
3023 | reg = gen_rtx_REG (DFmode, regno + 32); | |
3024 | regno += 1; | |
3025 | break; | |
3026 | ||
3027 | case VOIDmode: | |
c933fb42 | 3028 | gcc_assert (CONST_INT_P (operands[i])); |
8e262b5e | 3029 | /* FALLTHRU */ |
915c336f | 3030 | case DImode: |
3031 | reg = gen_rtx_REG (DImode, regno); | |
3032 | regno += 1; | |
3033 | break; | |
3034 | ||
3035 | default: | |
4d10b463 | 3036 | gcc_unreachable (); |
915c336f | 3037 | } |
3038 | ||
3039 | emit_move_insn (reg, operands[i]); | |
3040 | usage = alloc_EXPR_LIST (0, gen_rtx_USE (VOIDmode, reg), usage); | |
3041 | } | |
3042 | ||
3043 | switch (GET_MODE (target)) | |
3044 | { | |
3045 | case TFmode: | |
3046 | reg = gen_rtx_REG (TFmode, 16); | |
3047 | break; | |
3048 | case DFmode: | |
3049 | reg = gen_rtx_REG (DFmode, 32); | |
3050 | break; | |
3051 | case DImode: | |
3052 | reg = gen_rtx_REG (DImode, 0); | |
3053 | break; | |
3054 | default: | |
4d10b463 | 3055 | gcc_unreachable (); |
915c336f | 3056 | } |
3057 | ||
2d7c492e | 3058 | tmp = gen_rtx_MEM (QImode, func); |
2c6f8e4d | 3059 | tmp = emit_call_insn (GEN_CALL_VALUE (reg, tmp, const0_rtx, |
915c336f | 3060 | const0_rtx, const0_rtx)); |
3061 | CALL_INSN_FUNCTION_USAGE (tmp) = usage; | |
9c2a0c05 | 3062 | RTL_CONST_CALL_P (tmp) = 1; |
915c336f | 3063 | |
3064 | tmp = get_insns (); | |
3065 | end_sequence (); | |
3066 | ||
3067 | emit_libcall_block (tmp, target, reg, equiv); | |
3068 | } | |
3069 | ||
3070 | /* Emit an X_floating library function call for arithmetic (+,-,*,/). */ | |
3071 | ||
3072 | void | |
92643d95 | 3073 | alpha_emit_xfloating_arith (enum rtx_code code, rtx operands[]) |
915c336f | 3074 | { |
2d7c492e | 3075 | rtx func; |
915c336f | 3076 | int mode; |
b90b6519 | 3077 | rtx out_operands[3]; |
915c336f | 3078 | |
3079 | func = alpha_lookup_xfloating_lib_func (code); | |
3080 | mode = alpha_compute_xfloating_mode_arg (code, alpha_fprm); | |
3081 | ||
b90b6519 | 3082 | out_operands[0] = operands[1]; |
3083 | out_operands[1] = operands[2]; | |
3084 | out_operands[2] = GEN_INT (mode); | |
9e7454d0 | 3085 | alpha_emit_xfloating_libcall (func, operands[0], out_operands, 3, |
915c336f | 3086 | gen_rtx_fmt_ee (code, TFmode, operands[1], |
3087 | operands[2])); | |
3088 | } | |
3089 | ||
3090 | /* Emit an X_floating library function call for a comparison. */ | |
3091 | ||
3092 | static rtx | |
8c3428a6 | 3093 | alpha_emit_xfloating_compare (enum rtx_code *pcode, rtx op0, rtx op1) |
915c336f | 3094 | { |
8c3428a6 | 3095 | enum rtx_code cmp_code, res_code; |
e8e27646 | 3096 | rtx func, out, operands[2], note; |
915c336f | 3097 | |
8c3428a6 | 3098 | /* X_floating library comparison functions return |
3099 | -1 unordered | |
3100 | 0 false | |
3101 | 1 true | |
3102 | Convert the compare against the raw return value. */ | |
3103 | ||
3104 | cmp_code = *pcode; | |
3105 | switch (cmp_code) | |
3106 | { | |
3107 | case UNORDERED: | |
3108 | cmp_code = EQ; | |
3109 | res_code = LT; | |
3110 | break; | |
3111 | case ORDERED: | |
3112 | cmp_code = EQ; | |
3113 | res_code = GE; | |
3114 | break; | |
3115 | case NE: | |
3116 | res_code = NE; | |
3117 | break; | |
3118 | case EQ: | |
3119 | case LT: | |
3120 | case GT: | |
3121 | case LE: | |
3122 | case GE: | |
3123 | res_code = GT; | |
3124 | break; | |
3125 | default: | |
3126 | gcc_unreachable (); | |
3127 | } | |
3128 | *pcode = res_code; | |
3129 | ||
3130 | func = alpha_lookup_xfloating_lib_func (cmp_code); | |
915c336f | 3131 | |
3132 | operands[0] = op0; | |
3133 | operands[1] = op1; | |
3134 | out = gen_reg_rtx (DImode); | |
3135 | ||
e8e27646 | 3136 | /* What's actually returned is -1,0,1, not a proper boolean value, |
3137 | so use an EXPR_LIST as with a generic libcall instead of a | |
3138 | comparison type expression. */ | |
3139 | note = gen_rtx_EXPR_LIST (VOIDmode, op1, NULL_RTX); | |
3140 | note = gen_rtx_EXPR_LIST (VOIDmode, op0, note); | |
3141 | note = gen_rtx_EXPR_LIST (VOIDmode, func, note); | |
3142 | alpha_emit_xfloating_libcall (func, out, operands, 2, note); | |
915c336f | 3143 | |
3144 | return out; | |
3145 | } | |
3146 | ||
3147 | /* Emit an X_floating library function call for a conversion. */ | |
3148 | ||
3149 | void | |
caf6f044 | 3150 | alpha_emit_xfloating_cvt (enum rtx_code orig_code, rtx operands[]) |
915c336f | 3151 | { |
3152 | int noperands = 1, mode; | |
b90b6519 | 3153 | rtx out_operands[2]; |
2d7c492e | 3154 | rtx func; |
caf6f044 | 3155 | enum rtx_code code = orig_code; |
3156 | ||
3157 | if (code == UNSIGNED_FIX) | |
3158 | code = FIX; | |
915c336f | 3159 | |
3160 | func = alpha_lookup_xfloating_lib_func (code); | |
3161 | ||
b90b6519 | 3162 | out_operands[0] = operands[1]; |
3163 | ||
915c336f | 3164 | switch (code) |
3165 | { | |
3166 | case FIX: | |
3167 | mode = alpha_compute_xfloating_mode_arg (code, ALPHA_FPRM_CHOP); | |
b90b6519 | 3168 | out_operands[1] = GEN_INT (mode); |
8581412d | 3169 | noperands = 2; |
915c336f | 3170 | break; |
3171 | case FLOAT_TRUNCATE: | |
3172 | mode = alpha_compute_xfloating_mode_arg (code, alpha_fprm); | |
b90b6519 | 3173 | out_operands[1] = GEN_INT (mode); |
8581412d | 3174 | noperands = 2; |
915c336f | 3175 | break; |
3176 | default: | |
3177 | break; | |
3178 | } | |
3179 | ||
b90b6519 | 3180 | alpha_emit_xfloating_libcall (func, operands[0], out_operands, noperands, |
caf6f044 | 3181 | gen_rtx_fmt_e (orig_code, |
3182 | GET_MODE (operands[0]), | |
915c336f | 3183 | operands[1])); |
3184 | } | |
3420680b | 3185 | |
10c77d2b | 3186 | /* Split a TImode or TFmode move from OP[1] to OP[0] into a pair of |
3187 | DImode moves from OP[2,3] to OP[0,1]. If FIXUP_OVERLAP is true, | |
3188 | guarantee that the sequence | |
3189 | set (OP[0] OP[2]) | |
3190 | set (OP[1] OP[3]) | |
3191 | is valid. Naturally, output operand ordering is little-endian. | |
3192 | This is used by *movtf_internal and *movti_internal. */ | |
3193 | ||
3420680b | 3194 | void |
10c77d2b | 3195 | alpha_split_tmode_pair (rtx operands[4], enum machine_mode mode, |
3196 | bool fixup_overlap) | |
3420680b | 3197 | { |
4d10b463 | 3198 | switch (GET_CODE (operands[1])) |
3420680b | 3199 | { |
4d10b463 | 3200 | case REG: |
3420680b | 3201 | operands[3] = gen_rtx_REG (DImode, REGNO (operands[1]) + 1); |
3202 | operands[2] = gen_rtx_REG (DImode, REGNO (operands[1])); | |
4d10b463 | 3203 | break; |
3204 | ||
3205 | case MEM: | |
e513d163 | 3206 | operands[3] = adjust_address (operands[1], DImode, 8); |
3207 | operands[2] = adjust_address (operands[1], DImode, 0); | |
4d10b463 | 3208 | break; |
3209 | ||
10c77d2b | 3210 | case CONST_INT: |
e4a93d80 | 3211 | case CONST_DOUBLE: |
10c77d2b | 3212 | gcc_assert (operands[1] == CONST0_RTX (mode)); |
4d10b463 | 3213 | operands[2] = operands[3] = const0_rtx; |
3214 | break; | |
3215 | ||
3216 | default: | |
3217 | gcc_unreachable (); | |
3420680b | 3218 | } |
3420680b | 3219 | |
4d10b463 | 3220 | switch (GET_CODE (operands[0])) |
3420680b | 3221 | { |
4d10b463 | 3222 | case REG: |
3420680b | 3223 | operands[1] = gen_rtx_REG (DImode, REGNO (operands[0]) + 1); |
3224 | operands[0] = gen_rtx_REG (DImode, REGNO (operands[0])); | |
4d10b463 | 3225 | break; |
3226 | ||
3227 | case MEM: | |
e513d163 | 3228 | operands[1] = adjust_address (operands[0], DImode, 8); |
3229 | operands[0] = adjust_address (operands[0], DImode, 0); | |
4d10b463 | 3230 | break; |
3231 | ||
3232 | default: | |
3233 | gcc_unreachable (); | |
3420680b | 3234 | } |
10c77d2b | 3235 | |
3236 | if (fixup_overlap && reg_overlap_mentioned_p (operands[0], operands[3])) | |
3237 | { | |
3238 | rtx tmp; | |
3239 | tmp = operands[0], operands[0] = operands[1], operands[1] = tmp; | |
3240 | tmp = operands[2], operands[2] = operands[3], operands[3] = tmp; | |
3241 | } | |
3420680b | 3242 | } |
2267ca84 | 3243 | |
9e7454d0 | 3244 | /* Implement negtf2 or abstf2. Op0 is destination, op1 is source, |
3245 | op2 is a register containing the sign bit, operation is the | |
2267ca84 | 3246 | logical operation to be performed. */ |
3247 | ||
3248 | void | |
92643d95 | 3249 | alpha_split_tfmode_frobsign (rtx operands[3], rtx (*operation) (rtx, rtx, rtx)) |
2267ca84 | 3250 | { |
3251 | rtx high_bit = operands[2]; | |
3252 | rtx scratch; | |
3253 | int move; | |
3254 | ||
10c77d2b | 3255 | alpha_split_tmode_pair (operands, TFmode, false); |
2267ca84 | 3256 | |
e3e08e7f | 3257 | /* Detect three flavors of operand overlap. */ |
2267ca84 | 3258 | move = 1; |
3259 | if (rtx_equal_p (operands[0], operands[2])) | |
3260 | move = 0; | |
3261 | else if (rtx_equal_p (operands[1], operands[2])) | |
3262 | { | |
3263 | if (rtx_equal_p (operands[0], high_bit)) | |
3264 | move = 2; | |
3265 | else | |
3266 | move = -1; | |
3267 | } | |
3268 | ||
3269 | if (move < 0) | |
3270 | emit_move_insn (operands[0], operands[2]); | |
3271 | ||
3272 | /* ??? If the destination overlaps both source tf and high_bit, then | |
3273 | assume source tf is dead in its entirety and use the other half | |
3274 | for a scratch register. Otherwise "scratch" is just the proper | |
3275 | destination register. */ | |
3276 | scratch = operands[move < 2 ? 1 : 3]; | |
3277 | ||
3278 | emit_insn ((*operation) (scratch, high_bit, operands[3])); | |
3279 | ||
3280 | if (move > 0) | |
3281 | { | |
3282 | emit_move_insn (operands[0], operands[2]); | |
3283 | if (move > 1) | |
3284 | emit_move_insn (operands[1], scratch); | |
3285 | } | |
3286 | } | |
915c336f | 3287 | \f |
34377880 | 3288 | /* Use ext[wlq][lh] as the Architecture Handbook describes for extracting |
3289 | unaligned data: | |
3290 | ||
3291 | unsigned: signed: | |
3292 | word: ldq_u r1,X(r11) ldq_u r1,X(r11) | |
3293 | ldq_u r2,X+1(r11) ldq_u r2,X+1(r11) | |
3294 | lda r3,X(r11) lda r3,X+2(r11) | |
3295 | extwl r1,r3,r1 extql r1,r3,r1 | |
3296 | extwh r2,r3,r2 extqh r2,r3,r2 | |
3297 | or r1.r2.r1 or r1,r2,r1 | |
3298 | sra r1,48,r1 | |
3299 | ||
3300 | long: ldq_u r1,X(r11) ldq_u r1,X(r11) | |
3301 | ldq_u r2,X+3(r11) ldq_u r2,X+3(r11) | |
3302 | lda r3,X(r11) lda r3,X(r11) | |
3303 | extll r1,r3,r1 extll r1,r3,r1 | |
3304 | extlh r2,r3,r2 extlh r2,r3,r2 | |
3305 | or r1.r2.r1 addl r1,r2,r1 | |
3306 | ||
3307 | quad: ldq_u r1,X(r11) | |
3308 | ldq_u r2,X+7(r11) | |
3309 | lda r3,X(r11) | |
3310 | extql r1,r3,r1 | |
3311 | extqh r2,r3,r2 | |
3312 | or r1.r2.r1 | |
3313 | */ | |
3314 | ||
3315 | void | |
92643d95 | 3316 | alpha_expand_unaligned_load (rtx tgt, rtx mem, HOST_WIDE_INT size, |
3317 | HOST_WIDE_INT ofs, int sign) | |
34377880 | 3318 | { |
1f0ce6a6 | 3319 | rtx meml, memh, addr, extl, exth, tmp, mema; |
2cc46ade | 3320 | enum machine_mode mode; |
34377880 | 3321 | |
9467fa25 | 3322 | if (TARGET_BWX && size == 2) |
3323 | { | |
b83bea6c | 3324 | meml = adjust_address (mem, QImode, ofs); |
3325 | memh = adjust_address (mem, QImode, ofs+1); | |
9467fa25 | 3326 | if (BYTES_BIG_ENDIAN) |
3327 | tmp = meml, meml = memh, memh = tmp; | |
3328 | extl = gen_reg_rtx (DImode); | |
3329 | exth = gen_reg_rtx (DImode); | |
3330 | emit_insn (gen_zero_extendqidi2 (extl, meml)); | |
3331 | emit_insn (gen_zero_extendqidi2 (exth, memh)); | |
3332 | exth = expand_simple_binop (DImode, ASHIFT, exth, GEN_INT (8), | |
3333 | NULL, 1, OPTAB_LIB_WIDEN); | |
3334 | addr = expand_simple_binop (DImode, IOR, extl, exth, | |
3335 | NULL, 1, OPTAB_LIB_WIDEN); | |
3336 | ||
3337 | if (sign && GET_MODE (tgt) != HImode) | |
3338 | { | |
3339 | addr = gen_lowpart (HImode, addr); | |
3340 | emit_insn (gen_extend_insn (tgt, addr, GET_MODE (tgt), HImode, 0)); | |
3341 | } | |
3342 | else | |
3343 | { | |
3344 | if (GET_MODE (tgt) != DImode) | |
3345 | addr = gen_lowpart (GET_MODE (tgt), addr); | |
3346 | emit_move_insn (tgt, addr); | |
3347 | } | |
3348 | return; | |
3349 | } | |
3350 | ||
34377880 | 3351 | meml = gen_reg_rtx (DImode); |
3352 | memh = gen_reg_rtx (DImode); | |
3353 | addr = gen_reg_rtx (DImode); | |
3354 | extl = gen_reg_rtx (DImode); | |
3355 | exth = gen_reg_rtx (DImode); | |
3356 | ||
1f0ce6a6 | 3357 | mema = XEXP (mem, 0); |
3358 | if (GET_CODE (mema) == LO_SUM) | |
3359 | mema = force_reg (Pmode, mema); | |
3360 | ||
3024e9f8 | 3361 | /* AND addresses cannot be in any alias set, since they may implicitly |
9e7454d0 | 3362 | alias surrounding code. Ideally we'd have some alias set that |
3024e9f8 | 3363 | covered all types except those with alignment 8 or higher. */ |
3364 | ||
3365 | tmp = change_address (mem, DImode, | |
9e7454d0 | 3366 | gen_rtx_AND (DImode, |
1f0ce6a6 | 3367 | plus_constant (mema, ofs), |
3024e9f8 | 3368 | GEN_INT (-8))); |
ab6ab77e | 3369 | set_mem_alias_set (tmp, 0); |
3024e9f8 | 3370 | emit_move_insn (meml, tmp); |
3371 | ||
3372 | tmp = change_address (mem, DImode, | |
9e7454d0 | 3373 | gen_rtx_AND (DImode, |
1f0ce6a6 | 3374 | plus_constant (mema, ofs + size - 1), |
3024e9f8 | 3375 | GEN_INT (-8))); |
ab6ab77e | 3376 | set_mem_alias_set (tmp, 0); |
3024e9f8 | 3377 | emit_move_insn (memh, tmp); |
34377880 | 3378 | |
9caef960 | 3379 | if (WORDS_BIG_ENDIAN && sign && (size == 2 || size == 4)) |
3380 | { | |
3381 | emit_move_insn (addr, plus_constant (mema, -1)); | |
3382 | ||
3383 | emit_insn (gen_extqh_be (extl, meml, addr)); | |
3384 | emit_insn (gen_extxl_be (exth, memh, GEN_INT (64), addr)); | |
3385 | ||
3386 | addr = expand_binop (DImode, ior_optab, extl, exth, tgt, 1, OPTAB_WIDEN); | |
3387 | addr = expand_binop (DImode, ashr_optab, addr, GEN_INT (64 - size*8), | |
3388 | addr, 1, OPTAB_WIDEN); | |
3389 | } | |
3390 | else if (sign && size == 2) | |
34377880 | 3391 | { |
1f0ce6a6 | 3392 | emit_move_insn (addr, plus_constant (mema, ofs+2)); |
34377880 | 3393 | |
9caef960 | 3394 | emit_insn (gen_extxl_le (extl, meml, GEN_INT (64), addr)); |
3395 | emit_insn (gen_extqh_le (exth, memh, addr)); | |
34377880 | 3396 | |
ba4a7733 | 3397 | /* We must use tgt here for the target. Alpha-vms port fails if we use |
3398 | addr for the target, because addr is marked as a pointer and combine | |
85c36fd1 | 3399 | knows that pointers are always sign-extended 32-bit values. */ |
ba4a7733 | 3400 | addr = expand_binop (DImode, ior_optab, extl, exth, tgt, 1, OPTAB_WIDEN); |
9e7454d0 | 3401 | addr = expand_binop (DImode, ashr_optab, addr, GEN_INT (48), |
2cc46ade | 3402 | addr, 1, OPTAB_WIDEN); |
34377880 | 3403 | } |
2cc46ade | 3404 | else |
34377880 | 3405 | { |
9caef960 | 3406 | if (WORDS_BIG_ENDIAN) |
2cc46ade | 3407 | { |
9caef960 | 3408 | emit_move_insn (addr, plus_constant (mema, ofs+size-1)); |
3409 | switch ((int) size) | |
3410 | { | |
3411 | case 2: | |
3412 | emit_insn (gen_extwh_be (extl, meml, addr)); | |
3413 | mode = HImode; | |
3414 | break; | |
34377880 | 3415 | |
9caef960 | 3416 | case 4: |
3417 | emit_insn (gen_extlh_be (extl, meml, addr)); | |
3418 | mode = SImode; | |
3419 | break; | |
34377880 | 3420 | |
9caef960 | 3421 | case 8: |
3422 | emit_insn (gen_extqh_be (extl, meml, addr)); | |
3423 | mode = DImode; | |
3424 | break; | |
915c336f | 3425 | |
9caef960 | 3426 | default: |
4d10b463 | 3427 | gcc_unreachable (); |
9caef960 | 3428 | } |
3429 | emit_insn (gen_extxl_be (exth, memh, GEN_INT (size*8), addr)); | |
3430 | } | |
3431 | else | |
3432 | { | |
3433 | emit_move_insn (addr, plus_constant (mema, ofs)); | |
3434 | emit_insn (gen_extxl_le (extl, meml, GEN_INT (size*8), addr)); | |
3435 | switch ((int) size) | |
3436 | { | |
3437 | case 2: | |
3438 | emit_insn (gen_extwh_le (exth, memh, addr)); | |
3439 | mode = HImode; | |
3440 | break; | |
3441 | ||
3442 | case 4: | |
3443 | emit_insn (gen_extlh_le (exth, memh, addr)); | |
3444 | mode = SImode; | |
3445 | break; | |
3446 | ||
3447 | case 8: | |
3448 | emit_insn (gen_extqh_le (exth, memh, addr)); | |
3449 | mode = DImode; | |
3450 | break; | |
3451 | ||
3452 | default: | |
4d10b463 | 3453 | gcc_unreachable (); |
9caef960 | 3454 | } |
2cc46ade | 3455 | } |
3456 | ||
3457 | addr = expand_binop (mode, ior_optab, gen_lowpart (mode, extl), | |
3458 | gen_lowpart (mode, exth), gen_lowpart (mode, tgt), | |
3459 | sign, OPTAB_WIDEN); | |
34377880 | 3460 | } |
3461 | ||
2cc46ade | 3462 | if (addr != tgt) |
9467fa25 | 3463 | emit_move_insn (tgt, gen_lowpart (GET_MODE (tgt), addr)); |
34377880 | 3464 | } |
3465 | ||
3466 | /* Similarly, use ins and msk instructions to perform unaligned stores. */ | |
3467 | ||
3468 | void | |
92643d95 | 3469 | alpha_expand_unaligned_store (rtx dst, rtx src, |
3470 | HOST_WIDE_INT size, HOST_WIDE_INT ofs) | |
34377880 | 3471 | { |
1f0ce6a6 | 3472 | rtx dstl, dsth, addr, insl, insh, meml, memh, dsta; |
9e7454d0 | 3473 | |
9467fa25 | 3474 | if (TARGET_BWX && size == 2) |
3475 | { | |
3476 | if (src != const0_rtx) | |
3477 | { | |
3478 | dstl = gen_lowpart (QImode, src); | |
3479 | dsth = expand_simple_binop (DImode, LSHIFTRT, src, GEN_INT (8), | |
3480 | NULL, 1, OPTAB_LIB_WIDEN); | |
3481 | dsth = gen_lowpart (QImode, dsth); | |
3482 | } | |
3483 | else | |
3484 | dstl = dsth = const0_rtx; | |
3485 | ||
b83bea6c | 3486 | meml = adjust_address (dst, QImode, ofs); |
3487 | memh = adjust_address (dst, QImode, ofs+1); | |
9467fa25 | 3488 | if (BYTES_BIG_ENDIAN) |
3489 | addr = meml, meml = memh, memh = addr; | |
3490 | ||
3491 | emit_move_insn (meml, dstl); | |
3492 | emit_move_insn (memh, dsth); | |
3493 | return; | |
3494 | } | |
3495 | ||
34377880 | 3496 | dstl = gen_reg_rtx (DImode); |
3497 | dsth = gen_reg_rtx (DImode); | |
3498 | insl = gen_reg_rtx (DImode); | |
3499 | insh = gen_reg_rtx (DImode); | |
3500 | ||
1f0ce6a6 | 3501 | dsta = XEXP (dst, 0); |
3502 | if (GET_CODE (dsta) == LO_SUM) | |
3503 | dsta = force_reg (Pmode, dsta); | |
3504 | ||
3024e9f8 | 3505 | /* AND addresses cannot be in any alias set, since they may implicitly |
9e7454d0 | 3506 | alias surrounding code. Ideally we'd have some alias set that |
3024e9f8 | 3507 | covered all types except those with alignment 8 or higher. */ |
3508 | ||
34377880 | 3509 | meml = change_address (dst, DImode, |
9e7454d0 | 3510 | gen_rtx_AND (DImode, |
1f0ce6a6 | 3511 | plus_constant (dsta, ofs), |
941522d6 | 3512 | GEN_INT (-8))); |
ab6ab77e | 3513 | set_mem_alias_set (meml, 0); |
3024e9f8 | 3514 | |
34377880 | 3515 | memh = change_address (dst, DImode, |
9e7454d0 | 3516 | gen_rtx_AND (DImode, |
1f0ce6a6 | 3517 | plus_constant (dsta, ofs + size - 1), |
941522d6 | 3518 | GEN_INT (-8))); |
ab6ab77e | 3519 | set_mem_alias_set (memh, 0); |
34377880 | 3520 | |
3521 | emit_move_insn (dsth, memh); | |
3522 | emit_move_insn (dstl, meml); | |
9caef960 | 3523 | if (WORDS_BIG_ENDIAN) |
34377880 | 3524 | { |
9caef960 | 3525 | addr = copy_addr_to_reg (plus_constant (dsta, ofs+size-1)); |
3526 | ||
3527 | if (src != const0_rtx) | |
3528 | { | |
3529 | switch ((int) size) | |
3530 | { | |
3531 | case 2: | |
3532 | emit_insn (gen_inswl_be (insh, gen_lowpart (HImode,src), addr)); | |
3533 | break; | |
3534 | case 4: | |
3535 | emit_insn (gen_insll_be (insh, gen_lowpart (SImode,src), addr)); | |
3536 | break; | |
3537 | case 8: | |
3538 | emit_insn (gen_insql_be (insh, gen_lowpart (DImode,src), addr)); | |
3539 | break; | |
3540 | } | |
3541 | emit_insn (gen_insxh (insl, gen_lowpart (DImode, src), | |
3542 | GEN_INT (size*8), addr)); | |
3543 | } | |
34377880 | 3544 | |
29768226 | 3545 | switch ((int) size) |
34377880 | 3546 | { |
3547 | case 2: | |
9caef960 | 3548 | emit_insn (gen_mskxl_be (dsth, dsth, GEN_INT (0xffff), addr)); |
34377880 | 3549 | break; |
3550 | case 4: | |
9caef960 | 3551 | { |
ae4cd3a5 | 3552 | rtx msk = immed_double_const (0xffffffff, 0, DImode); |
9caef960 | 3553 | emit_insn (gen_mskxl_be (dsth, dsth, msk, addr)); |
ae4cd3a5 | 3554 | break; |
9caef960 | 3555 | } |
ae4cd3a5 | 3556 | case 8: |
3557 | emit_insn (gen_mskxl_be (dsth, dsth, constm1_rtx, addr)); | |
34377880 | 3558 | break; |
3559 | } | |
9caef960 | 3560 | |
3561 | emit_insn (gen_mskxh (dstl, dstl, GEN_INT (size*8), addr)); | |
34377880 | 3562 | } |
9caef960 | 3563 | else |
3564 | { | |
3565 | addr = copy_addr_to_reg (plus_constant (dsta, ofs)); | |
34377880 | 3566 | |
b739144f | 3567 | if (src != CONST0_RTX (GET_MODE (src))) |
9caef960 | 3568 | { |
3569 | emit_insn (gen_insxh (insh, gen_lowpart (DImode, src), | |
3570 | GEN_INT (size*8), addr)); | |
34377880 | 3571 | |
9caef960 | 3572 | switch ((int) size) |
3573 | { | |
3574 | case 2: | |
3575 | emit_insn (gen_inswl_le (insl, gen_lowpart (HImode, src), addr)); | |
3576 | break; | |
3577 | case 4: | |
3578 | emit_insn (gen_insll_le (insl, gen_lowpart (SImode, src), addr)); | |
3579 | break; | |
3580 | case 8: | |
b8340ddc | 3581 | emit_insn (gen_insql_le (insl, gen_lowpart (DImode, src), addr)); |
9caef960 | 3582 | break; |
3583 | } | |
3584 | } | |
3585 | ||
3586 | emit_insn (gen_mskxh (dsth, dsth, GEN_INT (size*8), addr)); | |
3587 | ||
3588 | switch ((int) size) | |
3589 | { | |
3590 | case 2: | |
3591 | emit_insn (gen_mskxl_le (dstl, dstl, GEN_INT (0xffff), addr)); | |
3592 | break; | |
3593 | case 4: | |
9caef960 | 3594 | { |
ae4cd3a5 | 3595 | rtx msk = immed_double_const (0xffffffff, 0, DImode); |
9caef960 | 3596 | emit_insn (gen_mskxl_le (dstl, dstl, msk, addr)); |
ae4cd3a5 | 3597 | break; |
9caef960 | 3598 | } |
ae4cd3a5 | 3599 | case 8: |
3600 | emit_insn (gen_mskxl_le (dstl, dstl, constm1_rtx, addr)); | |
9caef960 | 3601 | break; |
3602 | } | |
34377880 | 3603 | } |
3604 | ||
b739144f | 3605 | if (src != CONST0_RTX (GET_MODE (src))) |
34377880 | 3606 | { |
2cc46ade | 3607 | dsth = expand_binop (DImode, ior_optab, insh, dsth, dsth, 0, OPTAB_WIDEN); |
3608 | dstl = expand_binop (DImode, ior_optab, insl, dstl, dstl, 0, OPTAB_WIDEN); | |
34377880 | 3609 | } |
9e7454d0 | 3610 | |
9caef960 | 3611 | if (WORDS_BIG_ENDIAN) |
3612 | { | |
3613 | emit_move_insn (meml, dstl); | |
3614 | emit_move_insn (memh, dsth); | |
3615 | } | |
3616 | else | |
3617 | { | |
3618 | /* Must store high before low for degenerate case of aligned. */ | |
3619 | emit_move_insn (memh, dsth); | |
3620 | emit_move_insn (meml, dstl); | |
3621 | } | |
34377880 | 3622 | } |
3623 | ||
2cc46ade | 3624 | /* The block move code tries to maximize speed by separating loads and |
3625 | stores at the expense of register pressure: we load all of the data | |
3626 | before we store it back out. There are two secondary effects worth | |
3627 | mentioning, that this speeds copying to/from aligned and unaligned | |
3628 | buffers, and that it makes the code significantly easier to write. */ | |
34377880 | 3629 | |
2cc46ade | 3630 | #define MAX_MOVE_WORDS 8 |
3631 | ||
3632 | /* Load an integral number of consecutive unaligned quadwords. */ | |
34377880 | 3633 | |
3634 | static void | |
92643d95 | 3635 | alpha_expand_unaligned_load_words (rtx *out_regs, rtx smem, |
3636 | HOST_WIDE_INT words, HOST_WIDE_INT ofs) | |
34377880 | 3637 | { |
3638 | rtx const im8 = GEN_INT (-8); | |
3639 | rtx const i64 = GEN_INT (64); | |
2cc46ade | 3640 | rtx ext_tmps[MAX_MOVE_WORDS], data_regs[MAX_MOVE_WORDS+1]; |
1f0ce6a6 | 3641 | rtx sreg, areg, tmp, smema; |
34377880 | 3642 | HOST_WIDE_INT i; |
3643 | ||
1f0ce6a6 | 3644 | smema = XEXP (smem, 0); |
3645 | if (GET_CODE (smema) == LO_SUM) | |
3646 | smema = force_reg (Pmode, smema); | |
3647 | ||
34377880 | 3648 | /* Generate all the tmp registers we need. */ |
3649 | for (i = 0; i < words; ++i) | |
2cc46ade | 3650 | { |
3651 | data_regs[i] = out_regs[i]; | |
3652 | ext_tmps[i] = gen_reg_rtx (DImode); | |
3653 | } | |
3654 | data_regs[words] = gen_reg_rtx (DImode); | |
3655 | ||
3656 | if (ofs != 0) | |
e513d163 | 3657 | smem = adjust_address (smem, GET_MODE (smem), ofs); |
9e7454d0 | 3658 | |
34377880 | 3659 | /* Load up all of the source data. */ |
3660 | for (i = 0; i < words; ++i) | |
3661 | { | |
3024e9f8 | 3662 | tmp = change_address (smem, DImode, |
3663 | gen_rtx_AND (DImode, | |
1f0ce6a6 | 3664 | plus_constant (smema, 8*i), |
3024e9f8 | 3665 | im8)); |
ab6ab77e | 3666 | set_mem_alias_set (tmp, 0); |
3024e9f8 | 3667 | emit_move_insn (data_regs[i], tmp); |
34377880 | 3668 | } |
3024e9f8 | 3669 | |
3670 | tmp = change_address (smem, DImode, | |
3671 | gen_rtx_AND (DImode, | |
1f0ce6a6 | 3672 | plus_constant (smema, 8*words - 1), |
3024e9f8 | 3673 | im8)); |
ab6ab77e | 3674 | set_mem_alias_set (tmp, 0); |
3024e9f8 | 3675 | emit_move_insn (data_regs[words], tmp); |
34377880 | 3676 | |
3677 | /* Extract the half-word fragments. Unfortunately DEC decided to make | |
9e7454d0 | 3678 | extxh with offset zero a noop instead of zeroing the register, so |
34377880 | 3679 | we must take care of that edge condition ourselves with cmov. */ |
3680 | ||
1f0ce6a6 | 3681 | sreg = copy_addr_to_reg (smema); |
9e7454d0 | 3682 | areg = expand_binop (DImode, and_optab, sreg, GEN_INT (7), NULL, |
2cc46ade | 3683 | 1, OPTAB_WIDEN); |
9caef960 | 3684 | if (WORDS_BIG_ENDIAN) |
3685 | emit_move_insn (sreg, plus_constant (sreg, 7)); | |
34377880 | 3686 | for (i = 0; i < words; ++i) |
3687 | { | |
9caef960 | 3688 | if (WORDS_BIG_ENDIAN) |
3689 | { | |
3690 | emit_insn (gen_extqh_be (data_regs[i], data_regs[i], sreg)); | |
3691 | emit_insn (gen_extxl_be (ext_tmps[i], data_regs[i+1], i64, sreg)); | |
3692 | } | |
3693 | else | |
3694 | { | |
3695 | emit_insn (gen_extxl_le (data_regs[i], data_regs[i], i64, sreg)); | |
3696 | emit_insn (gen_extqh_le (ext_tmps[i], data_regs[i+1], sreg)); | |
3697 | } | |
941522d6 | 3698 | emit_insn (gen_rtx_SET (VOIDmode, ext_tmps[i], |
3699 | gen_rtx_IF_THEN_ELSE (DImode, | |
2cc46ade | 3700 | gen_rtx_EQ (DImode, areg, |
3701 | const0_rtx), | |
941522d6 | 3702 | const0_rtx, ext_tmps[i]))); |
34377880 | 3703 | } |
3704 | ||
3705 | /* Merge the half-words into whole words. */ | |
3706 | for (i = 0; i < words; ++i) | |
3707 | { | |
2cc46ade | 3708 | out_regs[i] = expand_binop (DImode, ior_optab, data_regs[i], |
3709 | ext_tmps[i], data_regs[i], 1, OPTAB_WIDEN); | |
34377880 | 3710 | } |
3711 | } | |
3712 | ||
3713 | /* Store an integral number of consecutive unaligned quadwords. DATA_REGS | |
3714 | may be NULL to store zeros. */ | |
3715 | ||
3716 | static void | |
92643d95 | 3717 | alpha_expand_unaligned_store_words (rtx *data_regs, rtx dmem, |
3718 | HOST_WIDE_INT words, HOST_WIDE_INT ofs) | |
34377880 | 3719 | { |
3720 | rtx const im8 = GEN_INT (-8); | |
3721 | rtx const i64 = GEN_INT (64); | |
34377880 | 3722 | rtx ins_tmps[MAX_MOVE_WORDS]; |
2cc46ade | 3723 | rtx st_tmp_1, st_tmp_2, dreg; |
1f0ce6a6 | 3724 | rtx st_addr_1, st_addr_2, dmema; |
34377880 | 3725 | HOST_WIDE_INT i; |
3726 | ||
1f0ce6a6 | 3727 | dmema = XEXP (dmem, 0); |
3728 | if (GET_CODE (dmema) == LO_SUM) | |
3729 | dmema = force_reg (Pmode, dmema); | |
3730 | ||
34377880 | 3731 | /* Generate all the tmp registers we need. */ |
3732 | if (data_regs != NULL) | |
3733 | for (i = 0; i < words; ++i) | |
3734 | ins_tmps[i] = gen_reg_rtx(DImode); | |
3735 | st_tmp_1 = gen_reg_rtx(DImode); | |
3736 | st_tmp_2 = gen_reg_rtx(DImode); | |
9e7454d0 | 3737 | |
2cc46ade | 3738 | if (ofs != 0) |
e513d163 | 3739 | dmem = adjust_address (dmem, GET_MODE (dmem), ofs); |
2cc46ade | 3740 | |
3741 | st_addr_2 = change_address (dmem, DImode, | |
941522d6 | 3742 | gen_rtx_AND (DImode, |
1f0ce6a6 | 3743 | plus_constant (dmema, words*8 - 1), |
34377880 | 3744 | im8)); |
ab6ab77e | 3745 | set_mem_alias_set (st_addr_2, 0); |
3024e9f8 | 3746 | |
2cc46ade | 3747 | st_addr_1 = change_address (dmem, DImode, |
1f0ce6a6 | 3748 | gen_rtx_AND (DImode, dmema, im8)); |
ab6ab77e | 3749 | set_mem_alias_set (st_addr_1, 0); |
34377880 | 3750 | |
3751 | /* Load up the destination end bits. */ | |
3752 | emit_move_insn (st_tmp_2, st_addr_2); | |
3753 | emit_move_insn (st_tmp_1, st_addr_1); | |
3754 | ||
3755 | /* Shift the input data into place. */ | |
1f0ce6a6 | 3756 | dreg = copy_addr_to_reg (dmema); |
9caef960 | 3757 | if (WORDS_BIG_ENDIAN) |
3758 | emit_move_insn (dreg, plus_constant (dreg, 7)); | |
34377880 | 3759 | if (data_regs != NULL) |
3760 | { | |
3761 | for (i = words-1; i >= 0; --i) | |
3762 | { | |
9caef960 | 3763 | if (WORDS_BIG_ENDIAN) |
3764 | { | |
3765 | emit_insn (gen_insql_be (ins_tmps[i], data_regs[i], dreg)); | |
3766 | emit_insn (gen_insxh (data_regs[i], data_regs[i], i64, dreg)); | |
3767 | } | |
3768 | else | |
3769 | { | |
3770 | emit_insn (gen_insxh (ins_tmps[i], data_regs[i], i64, dreg)); | |
3771 | emit_insn (gen_insql_le (data_regs[i], data_regs[i], dreg)); | |
3772 | } | |
34377880 | 3773 | } |
34377880 | 3774 | for (i = words-1; i > 0; --i) |
3775 | { | |
2cc46ade | 3776 | ins_tmps[i-1] = expand_binop (DImode, ior_optab, data_regs[i], |
3777 | ins_tmps[i-1], ins_tmps[i-1], 1, | |
3778 | OPTAB_WIDEN); | |
34377880 | 3779 | } |
3780 | } | |
3781 | ||
3782 | /* Split and merge the ends with the destination data. */ | |
9caef960 | 3783 | if (WORDS_BIG_ENDIAN) |
3784 | { | |
ae4cd3a5 | 3785 | emit_insn (gen_mskxl_be (st_tmp_2, st_tmp_2, constm1_rtx, dreg)); |
9caef960 | 3786 | emit_insn (gen_mskxh (st_tmp_1, st_tmp_1, i64, dreg)); |
3787 | } | |
3788 | else | |
3789 | { | |
3790 | emit_insn (gen_mskxh (st_tmp_2, st_tmp_2, i64, dreg)); | |
ae4cd3a5 | 3791 | emit_insn (gen_mskxl_le (st_tmp_1, st_tmp_1, constm1_rtx, dreg)); |
9caef960 | 3792 | } |
34377880 | 3793 | |
3794 | if (data_regs != NULL) | |
3795 | { | |
2cc46ade | 3796 | st_tmp_2 = expand_binop (DImode, ior_optab, st_tmp_2, ins_tmps[words-1], |
3797 | st_tmp_2, 1, OPTAB_WIDEN); | |
3798 | st_tmp_1 = expand_binop (DImode, ior_optab, st_tmp_1, data_regs[0], | |
3799 | st_tmp_1, 1, OPTAB_WIDEN); | |
34377880 | 3800 | } |
3801 | ||
3802 | /* Store it all. */ | |
9caef960 | 3803 | if (WORDS_BIG_ENDIAN) |
3804 | emit_move_insn (st_addr_1, st_tmp_1); | |
3805 | else | |
3806 | emit_move_insn (st_addr_2, st_tmp_2); | |
34377880 | 3807 | for (i = words-1; i > 0; --i) |
3808 | { | |
3024e9f8 | 3809 | rtx tmp = change_address (dmem, DImode, |
3810 | gen_rtx_AND (DImode, | |
9caef960 | 3811 | plus_constant(dmema, |
3812 | WORDS_BIG_ENDIAN ? i*8-1 : i*8), | |
3024e9f8 | 3813 | im8)); |
ab6ab77e | 3814 | set_mem_alias_set (tmp, 0); |
3024e9f8 | 3815 | emit_move_insn (tmp, data_regs ? ins_tmps[i-1] : const0_rtx); |
34377880 | 3816 | } |
9caef960 | 3817 | if (WORDS_BIG_ENDIAN) |
3818 | emit_move_insn (st_addr_2, st_tmp_2); | |
3819 | else | |
3820 | emit_move_insn (st_addr_1, st_tmp_1); | |
34377880 | 3821 | } |
3822 | ||
3823 | ||
3824 | /* Expand string/block move operations. | |
3825 | ||
3826 | operands[0] is the pointer to the destination. | |
3827 | operands[1] is the pointer to the source. | |
3828 | operands[2] is the number of bytes to move. | |
3829 | operands[3] is the alignment. */ | |
3830 | ||
3831 | int | |
92643d95 | 3832 | alpha_expand_block_move (rtx operands[]) |
34377880 | 3833 | { |
3834 | rtx bytes_rtx = operands[2]; | |
3835 | rtx align_rtx = operands[3]; | |
d94b545b | 3836 | HOST_WIDE_INT orig_bytes = INTVAL (bytes_rtx); |
a9aaae37 | 3837 | HOST_WIDE_INT bytes = orig_bytes; |
3838 | HOST_WIDE_INT src_align = INTVAL (align_rtx) * BITS_PER_UNIT; | |
3839 | HOST_WIDE_INT dst_align = src_align; | |
80909c64 | 3840 | rtx orig_src = operands[1]; |
3841 | rtx orig_dst = operands[0]; | |
3842 | rtx data_regs[2 * MAX_MOVE_WORDS + 16]; | |
2cc46ade | 3843 | rtx tmp; |
1f0ce6a6 | 3844 | unsigned int i, words, ofs, nregs = 0; |
9e7454d0 | 3845 | |
80909c64 | 3846 | if (orig_bytes <= 0) |
34377880 | 3847 | return 1; |
a9aaae37 | 3848 | else if (orig_bytes > MAX_MOVE_WORDS * UNITS_PER_WORD) |
34377880 | 3849 | return 0; |
3850 | ||
2cc46ade | 3851 | /* Look for additional alignment information from recorded register info. */ |
3852 | ||
3853 | tmp = XEXP (orig_src, 0); | |
c933fb42 | 3854 | if (REG_P (tmp)) |
80909c64 | 3855 | src_align = MAX (src_align, REGNO_POINTER_ALIGN (REGNO (tmp))); |
2cc46ade | 3856 | else if (GET_CODE (tmp) == PLUS |
c933fb42 | 3857 | && REG_P (XEXP (tmp, 0)) |
3858 | && CONST_INT_P (XEXP (tmp, 1))) | |
2cc46ade | 3859 | { |
80909c64 | 3860 | unsigned HOST_WIDE_INT c = INTVAL (XEXP (tmp, 1)); |
3861 | unsigned int a = REGNO_POINTER_ALIGN (REGNO (XEXP (tmp, 0))); | |
2cc46ade | 3862 | |
3863 | if (a > src_align) | |
3864 | { | |
80909c64 | 3865 | if (a >= 64 && c % 8 == 0) |
3866 | src_align = 64; | |
3867 | else if (a >= 32 && c % 4 == 0) | |
3868 | src_align = 32; | |
3869 | else if (a >= 16 && c % 2 == 0) | |
3870 | src_align = 16; | |
2cc46ade | 3871 | } |
3872 | } | |
9e7454d0 | 3873 | |
2cc46ade | 3874 | tmp = XEXP (orig_dst, 0); |
c933fb42 | 3875 | if (REG_P (tmp)) |
80909c64 | 3876 | dst_align = MAX (dst_align, REGNO_POINTER_ALIGN (REGNO (tmp))); |
2cc46ade | 3877 | else if (GET_CODE (tmp) == PLUS |
c933fb42 | 3878 | && REG_P (XEXP (tmp, 0)) |
3879 | && CONST_INT_P (XEXP (tmp, 1))) | |
2cc46ade | 3880 | { |
80909c64 | 3881 | unsigned HOST_WIDE_INT c = INTVAL (XEXP (tmp, 1)); |
3882 | unsigned int a = REGNO_POINTER_ALIGN (REGNO (XEXP (tmp, 0))); | |
2cc46ade | 3883 | |
3884 | if (a > dst_align) | |
3885 | { | |
80909c64 | 3886 | if (a >= 64 && c % 8 == 0) |
3887 | dst_align = 64; | |
3888 | else if (a >= 32 && c % 4 == 0) | |
3889 | dst_align = 32; | |
3890 | else if (a >= 16 && c % 2 == 0) | |
3891 | dst_align = 16; | |
2cc46ade | 3892 | } |
3893 | } | |
3894 | ||
2cc46ade | 3895 | ofs = 0; |
80909c64 | 3896 | if (src_align >= 64 && bytes >= 8) |
34377880 | 3897 | { |
3898 | words = bytes / 8; | |
3899 | ||
34377880 | 3900 | for (i = 0; i < words; ++i) |
27d0c333 | 3901 | data_regs[nregs + i] = gen_reg_rtx (DImode); |
34377880 | 3902 | |
34377880 | 3903 | for (i = 0; i < words; ++i) |
80909c64 | 3904 | emit_move_insn (data_regs[nregs + i], |
e513d163 | 3905 | adjust_address (orig_src, DImode, ofs + i * 8)); |
34377880 | 3906 | |
2cc46ade | 3907 | nregs += words; |
34377880 | 3908 | bytes -= words * 8; |
7597afe9 | 3909 | ofs += words * 8; |
34377880 | 3910 | } |
80909c64 | 3911 | |
3912 | if (src_align >= 32 && bytes >= 4) | |
34377880 | 3913 | { |
3914 | words = bytes / 4; | |
3915 | ||
34377880 | 3916 | for (i = 0; i < words; ++i) |
27d0c333 | 3917 | data_regs[nregs + i] = gen_reg_rtx (SImode); |
34377880 | 3918 | |
34377880 | 3919 | for (i = 0; i < words; ++i) |
80909c64 | 3920 | emit_move_insn (data_regs[nregs + i], |
537ffcfc | 3921 | adjust_address (orig_src, SImode, ofs + i * 4)); |
34377880 | 3922 | |
2cc46ade | 3923 | nregs += words; |
34377880 | 3924 | bytes -= words * 4; |
7597afe9 | 3925 | ofs += words * 4; |
34377880 | 3926 | } |
80909c64 | 3927 | |
a9aaae37 | 3928 | if (bytes >= 8) |
34377880 | 3929 | { |
3930 | words = bytes / 8; | |
3931 | ||
34377880 | 3932 | for (i = 0; i < words+1; ++i) |
27d0c333 | 3933 | data_regs[nregs + i] = gen_reg_rtx (DImode); |
34377880 | 3934 | |
b47268cf | 3935 | alpha_expand_unaligned_load_words (data_regs + nregs, orig_src, |
3936 | words, ofs); | |
34377880 | 3937 | |
2cc46ade | 3938 | nregs += words; |
34377880 | 3939 | bytes -= words * 8; |
7597afe9 | 3940 | ofs += words * 8; |
34377880 | 3941 | } |
80909c64 | 3942 | |
80909c64 | 3943 | if (! TARGET_BWX && bytes >= 4) |
34377880 | 3944 | { |
2cc46ade | 3945 | data_regs[nregs++] = tmp = gen_reg_rtx (SImode); |
34377880 | 3946 | alpha_expand_unaligned_load (tmp, orig_src, 4, ofs, 0); |
34377880 | 3947 | bytes -= 4; |
3948 | ofs += 4; | |
3949 | } | |
80909c64 | 3950 | |
34377880 | 3951 | if (bytes >= 2) |
3952 | { | |
80909c64 | 3953 | if (src_align >= 16) |
34377880 | 3954 | { |
3955 | do { | |
2cc46ade | 3956 | data_regs[nregs++] = tmp = gen_reg_rtx (HImode); |
e513d163 | 3957 | emit_move_insn (tmp, adjust_address (orig_src, HImode, ofs)); |
34377880 | 3958 | bytes -= 2; |
3959 | ofs += 2; | |
3960 | } while (bytes >= 2); | |
3961 | } | |
80909c64 | 3962 | else if (! TARGET_BWX) |
34377880 | 3963 | { |
2cc46ade | 3964 | data_regs[nregs++] = tmp = gen_reg_rtx (HImode); |
34377880 | 3965 | alpha_expand_unaligned_load (tmp, orig_src, 2, ofs, 0); |
34377880 | 3966 | bytes -= 2; |
3967 | ofs += 2; | |
3968 | } | |
3969 | } | |
80909c64 | 3970 | |
34377880 | 3971 | while (bytes > 0) |
3972 | { | |
2cc46ade | 3973 | data_regs[nregs++] = tmp = gen_reg_rtx (QImode); |
e513d163 | 3974 | emit_move_insn (tmp, adjust_address (orig_src, QImode, ofs)); |
34377880 | 3975 | bytes -= 1; |
3976 | ofs += 1; | |
3977 | } | |
80909c64 | 3978 | |
4d10b463 | 3979 | gcc_assert (nregs <= ARRAY_SIZE (data_regs)); |
2cc46ade | 3980 | |
80909c64 | 3981 | /* Now save it back out again. */ |
2cc46ade | 3982 | |
3983 | i = 0, ofs = 0; | |
3984 | ||
2cc46ade | 3985 | /* Write out the data in whatever chunks reading the source allowed. */ |
80909c64 | 3986 | if (dst_align >= 64) |
2cc46ade | 3987 | { |
3988 | while (i < nregs && GET_MODE (data_regs[i]) == DImode) | |
3989 | { | |
e513d163 | 3990 | emit_move_insn (adjust_address (orig_dst, DImode, ofs), |
2cc46ade | 3991 | data_regs[i]); |
3992 | ofs += 8; | |
3993 | i++; | |
3994 | } | |
3995 | } | |
80909c64 | 3996 | |
3997 | if (dst_align >= 32) | |
2cc46ade | 3998 | { |
3999 | /* If the source has remaining DImode regs, write them out in | |
4000 | two pieces. */ | |
4001 | while (i < nregs && GET_MODE (data_regs[i]) == DImode) | |
4002 | { | |
4003 | tmp = expand_binop (DImode, lshr_optab, data_regs[i], GEN_INT (32), | |
4004 | NULL_RTX, 1, OPTAB_WIDEN); | |
4005 | ||
e513d163 | 4006 | emit_move_insn (adjust_address (orig_dst, SImode, ofs), |
2cc46ade | 4007 | gen_lowpart (SImode, data_regs[i])); |
e513d163 | 4008 | emit_move_insn (adjust_address (orig_dst, SImode, ofs + 4), |
2cc46ade | 4009 | gen_lowpart (SImode, tmp)); |
4010 | ofs += 8; | |
4011 | i++; | |
4012 | } | |
4013 | ||
4014 | while (i < nregs && GET_MODE (data_regs[i]) == SImode) | |
4015 | { | |
e513d163 | 4016 | emit_move_insn (adjust_address (orig_dst, SImode, ofs), |
2cc46ade | 4017 | data_regs[i]); |
4018 | ofs += 4; | |
4019 | i++; | |
4020 | } | |
4021 | } | |
80909c64 | 4022 | |
2cc46ade | 4023 | if (i < nregs && GET_MODE (data_regs[i]) == DImode) |
4024 | { | |
4025 | /* Write out a remaining block of words using unaligned methods. */ | |
4026 | ||
80909c64 | 4027 | for (words = 1; i + words < nregs; words++) |
4028 | if (GET_MODE (data_regs[i + words]) != DImode) | |
2cc46ade | 4029 | break; |
4030 | ||
4031 | if (words == 1) | |
4032 | alpha_expand_unaligned_store (orig_dst, data_regs[i], 8, ofs); | |
4033 | else | |
80909c64 | 4034 | alpha_expand_unaligned_store_words (data_regs + i, orig_dst, |
4035 | words, ofs); | |
9e7454d0 | 4036 | |
2cc46ade | 4037 | i += words; |
4038 | ofs += words * 8; | |
4039 | } | |
4040 | ||
4041 | /* Due to the above, this won't be aligned. */ | |
4042 | /* ??? If we have more than one of these, consider constructing full | |
4043 | words in registers and using alpha_expand_unaligned_store_words. */ | |
4044 | while (i < nregs && GET_MODE (data_regs[i]) == SImode) | |
4045 | { | |
4046 | alpha_expand_unaligned_store (orig_dst, data_regs[i], 4, ofs); | |
4047 | ofs += 4; | |
4048 | i++; | |
4049 | } | |
4050 | ||
80909c64 | 4051 | if (dst_align >= 16) |
2cc46ade | 4052 | while (i < nregs && GET_MODE (data_regs[i]) == HImode) |
4053 | { | |
e513d163 | 4054 | emit_move_insn (adjust_address (orig_dst, HImode, ofs), data_regs[i]); |
2cc46ade | 4055 | i++; |
4056 | ofs += 2; | |
4057 | } | |
4058 | else | |
4059 | while (i < nregs && GET_MODE (data_regs[i]) == HImode) | |
4060 | { | |
4061 | alpha_expand_unaligned_store (orig_dst, data_regs[i], 2, ofs); | |
4062 | i++; | |
4063 | ofs += 2; | |
4064 | } | |
80909c64 | 4065 | |
4d10b463 | 4066 | /* The remainder must be byte copies. */ |
4067 | while (i < nregs) | |
2cc46ade | 4068 | { |
4d10b463 | 4069 | gcc_assert (GET_MODE (data_regs[i]) == QImode); |
e513d163 | 4070 | emit_move_insn (adjust_address (orig_dst, QImode, ofs), data_regs[i]); |
2cc46ade | 4071 | i++; |
4072 | ofs += 1; | |
4073 | } | |
80909c64 | 4074 | |
34377880 | 4075 | return 1; |
4076 | } | |
4077 | ||
4078 | int | |
92643d95 | 4079 | alpha_expand_block_clear (rtx operands[]) |
34377880 | 4080 | { |
4081 | rtx bytes_rtx = operands[1]; | |
7a3e5564 | 4082 | rtx align_rtx = operands[3]; |
80909c64 | 4083 | HOST_WIDE_INT orig_bytes = INTVAL (bytes_rtx); |
a9aaae37 | 4084 | HOST_WIDE_INT bytes = orig_bytes; |
4085 | HOST_WIDE_INT align = INTVAL (align_rtx) * BITS_PER_UNIT; | |
4086 | HOST_WIDE_INT alignofs = 0; | |
80909c64 | 4087 | rtx orig_dst = operands[0]; |
2cc46ade | 4088 | rtx tmp; |
a9aaae37 | 4089 | int i, words, ofs = 0; |
9e7454d0 | 4090 | |
80909c64 | 4091 | if (orig_bytes <= 0) |
34377880 | 4092 | return 1; |
a9aaae37 | 4093 | if (orig_bytes > MAX_MOVE_WORDS * UNITS_PER_WORD) |
34377880 | 4094 | return 0; |
4095 | ||
2cc46ade | 4096 | /* Look for stricter alignment. */ |
2cc46ade | 4097 | tmp = XEXP (orig_dst, 0); |
c933fb42 | 4098 | if (REG_P (tmp)) |
80909c64 | 4099 | align = MAX (align, REGNO_POINTER_ALIGN (REGNO (tmp))); |
2cc46ade | 4100 | else if (GET_CODE (tmp) == PLUS |
c933fb42 | 4101 | && REG_P (XEXP (tmp, 0)) |
4102 | && CONST_INT_P (XEXP (tmp, 1))) | |
2cc46ade | 4103 | { |
a9aaae37 | 4104 | HOST_WIDE_INT c = INTVAL (XEXP (tmp, 1)); |
4105 | int a = REGNO_POINTER_ALIGN (REGNO (XEXP (tmp, 0))); | |
2cc46ade | 4106 | |
4107 | if (a > align) | |
4108 | { | |
a9aaae37 | 4109 | if (a >= 64) |
4110 | align = a, alignofs = 8 - c % 8; | |
4111 | else if (a >= 32) | |
4112 | align = a, alignofs = 4 - c % 4; | |
4113 | else if (a >= 16) | |
4114 | align = a, alignofs = 2 - c % 2; | |
2cc46ade | 4115 | } |
4116 | } | |
4117 | ||
a9aaae37 | 4118 | /* Handle an unaligned prefix first. */ |
4119 | ||
4120 | if (alignofs > 0) | |
4121 | { | |
4122 | #if HOST_BITS_PER_WIDE_INT >= 64 | |
4123 | /* Given that alignofs is bounded by align, the only time BWX could | |
4124 | generate three stores is for a 7 byte fill. Prefer two individual | |
4125 | stores over a load/mask/store sequence. */ | |
4126 | if ((!TARGET_BWX || alignofs == 7) | |
4127 | && align >= 32 | |
4128 | && !(alignofs == 4 && bytes >= 4)) | |
4129 | { | |
4130 | enum machine_mode mode = (align >= 64 ? DImode : SImode); | |
4131 | int inv_alignofs = (align >= 64 ? 8 : 4) - alignofs; | |
4132 | rtx mem, tmp; | |
4133 | HOST_WIDE_INT mask; | |
4134 | ||
e513d163 | 4135 | mem = adjust_address (orig_dst, mode, ofs - inv_alignofs); |
ab6ab77e | 4136 | set_mem_alias_set (mem, 0); |
a9aaae37 | 4137 | |
4138 | mask = ~(~(HOST_WIDE_INT)0 << (inv_alignofs * 8)); | |
4139 | if (bytes < alignofs) | |
4140 | { | |
4141 | mask |= ~(HOST_WIDE_INT)0 << ((inv_alignofs + bytes) * 8); | |
4142 | ofs += bytes; | |
4143 | bytes = 0; | |
4144 | } | |
4145 | else | |
4146 | { | |
4147 | bytes -= alignofs; | |
4148 | ofs += alignofs; | |
4149 | } | |
4150 | alignofs = 0; | |
4151 | ||
4152 | tmp = expand_binop (mode, and_optab, mem, GEN_INT (mask), | |
4153 | NULL_RTX, 1, OPTAB_WIDEN); | |
4154 | ||
4155 | emit_move_insn (mem, tmp); | |
4156 | } | |
4157 | #endif | |
4158 | ||
4159 | if (TARGET_BWX && (alignofs & 1) && bytes >= 1) | |
4160 | { | |
e513d163 | 4161 | emit_move_insn (adjust_address (orig_dst, QImode, ofs), const0_rtx); |
a9aaae37 | 4162 | bytes -= 1; |
4163 | ofs += 1; | |
4164 | alignofs -= 1; | |
4165 | } | |
4166 | if (TARGET_BWX && align >= 16 && (alignofs & 3) == 2 && bytes >= 2) | |
4167 | { | |
e513d163 | 4168 | emit_move_insn (adjust_address (orig_dst, HImode, ofs), const0_rtx); |
a9aaae37 | 4169 | bytes -= 2; |
4170 | ofs += 2; | |
4171 | alignofs -= 2; | |
4172 | } | |
4173 | if (alignofs == 4 && bytes >= 4) | |
4174 | { | |
e513d163 | 4175 | emit_move_insn (adjust_address (orig_dst, SImode, ofs), const0_rtx); |
a9aaae37 | 4176 | bytes -= 4; |
4177 | ofs += 4; | |
4178 | alignofs = 0; | |
4179 | } | |
4180 | ||
4181 | /* If we've not used the extra lead alignment information by now, | |
4182 | we won't be able to. Downgrade align to match what's left over. */ | |
4183 | if (alignofs > 0) | |
4184 | { | |
4185 | alignofs = alignofs & -alignofs; | |
4186 | align = MIN (align, alignofs * BITS_PER_UNIT); | |
4187 | } | |
4188 | } | |
4189 | ||
4190 | /* Handle a block of contiguous long-words. */ | |
34377880 | 4191 | |
80909c64 | 4192 | if (align >= 64 && bytes >= 8) |
34377880 | 4193 | { |
4194 | words = bytes / 8; | |
4195 | ||
4196 | for (i = 0; i < words; ++i) | |
1f0ce6a6 | 4197 | emit_move_insn (adjust_address (orig_dst, DImode, ofs + i * 8), |
e513d163 | 4198 | const0_rtx); |
34377880 | 4199 | |
4200 | bytes -= words * 8; | |
7597afe9 | 4201 | ofs += words * 8; |
34377880 | 4202 | } |
80909c64 | 4203 | |
a9aaae37 | 4204 | /* If the block is large and appropriately aligned, emit a single |
4205 | store followed by a sequence of stq_u insns. */ | |
4206 | ||
4207 | if (align >= 32 && bytes > 16) | |
4208 | { | |
1f0ce6a6 | 4209 | rtx orig_dsta; |
4210 | ||
e513d163 | 4211 | emit_move_insn (adjust_address (orig_dst, SImode, ofs), const0_rtx); |
a9aaae37 | 4212 | bytes -= 4; |
4213 | ofs += 4; | |
4214 | ||
1f0ce6a6 | 4215 | orig_dsta = XEXP (orig_dst, 0); |
4216 | if (GET_CODE (orig_dsta) == LO_SUM) | |
4217 | orig_dsta = force_reg (Pmode, orig_dsta); | |
4218 | ||
a9aaae37 | 4219 | words = bytes / 8; |
4220 | for (i = 0; i < words; ++i) | |
4221 | { | |
ab6ab77e | 4222 | rtx mem |
4223 | = change_address (orig_dst, DImode, | |
4224 | gen_rtx_AND (DImode, | |
1f0ce6a6 | 4225 | plus_constant (orig_dsta, ofs + i*8), |
ab6ab77e | 4226 | GEN_INT (-8))); |
4227 | set_mem_alias_set (mem, 0); | |
a9aaae37 | 4228 | emit_move_insn (mem, const0_rtx); |
4229 | } | |
4230 | ||
4231 | /* Depending on the alignment, the first stq_u may have overlapped | |
4232 | with the initial stl, which means that the last stq_u didn't | |
4233 | write as much as it would appear. Leave those questionable bytes | |
4234 | unaccounted for. */ | |
4235 | bytes -= words * 8 - 4; | |
4236 | ofs += words * 8 - 4; | |
4237 | } | |
4238 | ||
4239 | /* Handle a smaller block of aligned words. */ | |
4240 | ||
4241 | if ((align >= 64 && bytes == 4) | |
4242 | || (align == 32 && bytes >= 4)) | |
34377880 | 4243 | { |
4244 | words = bytes / 4; | |
4245 | ||
4246 | for (i = 0; i < words; ++i) | |
e513d163 | 4247 | emit_move_insn (adjust_address (orig_dst, SImode, ofs + i * 4), |
80909c64 | 4248 | const0_rtx); |
34377880 | 4249 | |
4250 | bytes -= words * 4; | |
7597afe9 | 4251 | ofs += words * 4; |
34377880 | 4252 | } |
80909c64 | 4253 | |
a9aaae37 | 4254 | /* An unaligned block uses stq_u stores for as many as possible. */ |
4255 | ||
4256 | if (bytes >= 8) | |
34377880 | 4257 | { |
4258 | words = bytes / 8; | |
4259 | ||
7597afe9 | 4260 | alpha_expand_unaligned_store_words (NULL, orig_dst, words, ofs); |
34377880 | 4261 | |
4262 | bytes -= words * 8; | |
7597afe9 | 4263 | ofs += words * 8; |
34377880 | 4264 | } |
4265 | ||
a9aaae37 | 4266 | /* Next clean up any trailing pieces. */ |
34377880 | 4267 | |
a9aaae37 | 4268 | #if HOST_BITS_PER_WIDE_INT >= 64 |
4269 | /* Count the number of bits in BYTES for which aligned stores could | |
4270 | be emitted. */ | |
4271 | words = 0; | |
4272 | for (i = (TARGET_BWX ? 1 : 4); i * BITS_PER_UNIT <= align ; i <<= 1) | |
4273 | if (bytes & i) | |
4274 | words += 1; | |
4275 | ||
4276 | /* If we have appropriate alignment (and it wouldn't take too many | |
4277 | instructions otherwise), mask out the bytes we need. */ | |
4278 | if (TARGET_BWX ? words > 2 : bytes > 0) | |
4279 | { | |
4280 | if (align >= 64) | |
4281 | { | |
4282 | rtx mem, tmp; | |
4283 | HOST_WIDE_INT mask; | |
4284 | ||
e513d163 | 4285 | mem = adjust_address (orig_dst, DImode, ofs); |
ab6ab77e | 4286 | set_mem_alias_set (mem, 0); |
a9aaae37 | 4287 | |
4288 | mask = ~(HOST_WIDE_INT)0 << (bytes * 8); | |
4289 | ||
4290 | tmp = expand_binop (DImode, and_optab, mem, GEN_INT (mask), | |
4291 | NULL_RTX, 1, OPTAB_WIDEN); | |
4292 | ||
4293 | emit_move_insn (mem, tmp); | |
4294 | return 1; | |
4295 | } | |
4296 | else if (align >= 32 && bytes < 4) | |
4297 | { | |
4298 | rtx mem, tmp; | |
4299 | HOST_WIDE_INT mask; | |
4300 | ||
e513d163 | 4301 | mem = adjust_address (orig_dst, SImode, ofs); |
ab6ab77e | 4302 | set_mem_alias_set (mem, 0); |
a9aaae37 | 4303 | |
4304 | mask = ~(HOST_WIDE_INT)0 << (bytes * 8); | |
4305 | ||
4306 | tmp = expand_binop (SImode, and_optab, mem, GEN_INT (mask), | |
4307 | NULL_RTX, 1, OPTAB_WIDEN); | |
4308 | ||
4309 | emit_move_insn (mem, tmp); | |
4310 | return 1; | |
4311 | } | |
34377880 | 4312 | } |
a9aaae37 | 4313 | #endif |
80909c64 | 4314 | |
34377880 | 4315 | if (!TARGET_BWX && bytes >= 4) |
4316 | { | |
4317 | alpha_expand_unaligned_store (orig_dst, const0_rtx, 4, ofs); | |
4318 | bytes -= 4; | |
4319 | ofs += 4; | |
4320 | } | |
80909c64 | 4321 | |
34377880 | 4322 | if (bytes >= 2) |
4323 | { | |
80909c64 | 4324 | if (align >= 16) |
34377880 | 4325 | { |
4326 | do { | |
e513d163 | 4327 | emit_move_insn (adjust_address (orig_dst, HImode, ofs), |
34377880 | 4328 | const0_rtx); |
4329 | bytes -= 2; | |
4330 | ofs += 2; | |
4331 | } while (bytes >= 2); | |
4332 | } | |
80909c64 | 4333 | else if (! TARGET_BWX) |
34377880 | 4334 | { |
4335 | alpha_expand_unaligned_store (orig_dst, const0_rtx, 2, ofs); | |
4336 | bytes -= 2; | |
4337 | ofs += 2; | |
4338 | } | |
4339 | } | |
80909c64 | 4340 | |
34377880 | 4341 | while (bytes > 0) |
4342 | { | |
e513d163 | 4343 | emit_move_insn (adjust_address (orig_dst, QImode, ofs), const0_rtx); |
34377880 | 4344 | bytes -= 1; |
4345 | ofs += 1; | |
4346 | } | |
4347 | ||
4348 | return 1; | |
4349 | } | |
f2cc13dc | 4350 | |
4351 | /* Returns a mask so that zap(x, value) == x & mask. */ | |
4352 | ||
4353 | rtx | |
92643d95 | 4354 | alpha_expand_zap_mask (HOST_WIDE_INT value) |
f2cc13dc | 4355 | { |
4356 | rtx result; | |
4357 | int i; | |
4358 | ||
4359 | if (HOST_BITS_PER_WIDE_INT >= 64) | |
4360 | { | |
4361 | HOST_WIDE_INT mask = 0; | |
4362 | ||
4363 | for (i = 7; i >= 0; --i) | |
4364 | { | |
4365 | mask <<= 8; | |
4366 | if (!((value >> i) & 1)) | |
4367 | mask |= 0xff; | |
4368 | } | |
4369 | ||
4370 | result = gen_int_mode (mask, DImode); | |
4371 | } | |
4d10b463 | 4372 | else |
f2cc13dc | 4373 | { |
4374 | HOST_WIDE_INT mask_lo = 0, mask_hi = 0; | |
4375 | ||
4d10b463 | 4376 | gcc_assert (HOST_BITS_PER_WIDE_INT == 32); |
4377 | ||
f2cc13dc | 4378 | for (i = 7; i >= 4; --i) |
4379 | { | |
4380 | mask_hi <<= 8; | |
4381 | if (!((value >> i) & 1)) | |
4382 | mask_hi |= 0xff; | |
4383 | } | |
4384 | ||
4385 | for (i = 3; i >= 0; --i) | |
4386 | { | |
4387 | mask_lo <<= 8; | |
4388 | if (!((value >> i) & 1)) | |
4389 | mask_lo |= 0xff; | |
4390 | } | |
4391 | ||
4392 | result = immed_double_const (mask_lo, mask_hi, DImode); | |
4393 | } | |
f2cc13dc | 4394 | |
4395 | return result; | |
4396 | } | |
4397 | ||
4398 | void | |
92643d95 | 4399 | alpha_expand_builtin_vector_binop (rtx (*gen) (rtx, rtx, rtx), |
4400 | enum machine_mode mode, | |
4401 | rtx op0, rtx op1, rtx op2) | |
f2cc13dc | 4402 | { |
4403 | op0 = gen_lowpart (mode, op0); | |
4404 | ||
4405 | if (op1 == const0_rtx) | |
4406 | op1 = CONST0_RTX (mode); | |
4407 | else | |
4408 | op1 = gen_lowpart (mode, op1); | |
ae4cd3a5 | 4409 | |
4410 | if (op2 == const0_rtx) | |
f2cc13dc | 4411 | op2 = CONST0_RTX (mode); |
4412 | else | |
4413 | op2 = gen_lowpart (mode, op2); | |
4414 | ||
4415 | emit_insn ((*gen) (op0, op1, op2)); | |
4416 | } | |
f155876e | 4417 | |
032caa7b | 4418 | /* A subroutine of the atomic operation splitters. Jump to LABEL if |
4419 | COND is true. Mark the jump as unlikely to be taken. */ | |
4420 | ||
4421 | static void | |
4422 | emit_unlikely_jump (rtx cond, rtx label) | |
4423 | { | |
4424 | rtx very_unlikely = GEN_INT (REG_BR_PROB_BASE / 100 - 1); | |
4425 | rtx x; | |
4426 | ||
4427 | x = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, label, pc_rtx); | |
4428 | x = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, x)); | |
0a48089c | 4429 | add_reg_note (x, REG_BR_PROB, very_unlikely); |
032caa7b | 4430 | } |
4431 | ||
4432 | /* A subroutine of the atomic operation splitters. Emit a load-locked | |
4433 | instruction in MODE. */ | |
4434 | ||
4435 | static void | |
4436 | emit_load_locked (enum machine_mode mode, rtx reg, rtx mem) | |
4437 | { | |
4438 | rtx (*fn) (rtx, rtx) = NULL; | |
4439 | if (mode == SImode) | |
4440 | fn = gen_load_locked_si; | |
4441 | else if (mode == DImode) | |
4442 | fn = gen_load_locked_di; | |
4443 | emit_insn (fn (reg, mem)); | |
4444 | } | |
4445 | ||
4446 | /* A subroutine of the atomic operation splitters. Emit a store-conditional | |
4447 | instruction in MODE. */ | |
4448 | ||
4449 | static void | |
4450 | emit_store_conditional (enum machine_mode mode, rtx res, rtx mem, rtx val) | |
4451 | { | |
4452 | rtx (*fn) (rtx, rtx, rtx) = NULL; | |
4453 | if (mode == SImode) | |
4454 | fn = gen_store_conditional_si; | |
4455 | else if (mode == DImode) | |
4456 | fn = gen_store_conditional_di; | |
4457 | emit_insn (fn (res, mem, val)); | |
4458 | } | |
4459 | ||
596d3184 | 4460 | /* A subroutine of the atomic operation splitters. Emit an insxl |
4461 | instruction in MODE. */ | |
4462 | ||
4463 | static rtx | |
4464 | emit_insxl (enum machine_mode mode, rtx op1, rtx op2) | |
4465 | { | |
4466 | rtx ret = gen_reg_rtx (DImode); | |
4467 | rtx (*fn) (rtx, rtx, rtx); | |
4468 | ||
4469 | if (WORDS_BIG_ENDIAN) | |
4470 | { | |
4471 | if (mode == QImode) | |
4472 | fn = gen_insbl_be; | |
4473 | else | |
4474 | fn = gen_inswl_be; | |
4475 | } | |
4476 | else | |
4477 | { | |
4478 | if (mode == QImode) | |
4479 | fn = gen_insbl_le; | |
4480 | else | |
4481 | fn = gen_inswl_le; | |
4482 | } | |
9a6f4ddd | 4483 | /* The insbl and inswl patterns require a register operand. */ |
4484 | op1 = force_reg (mode, op1); | |
596d3184 | 4485 | emit_insn (fn (ret, op1, op2)); |
4486 | ||
4487 | return ret; | |
4488 | } | |
4489 | ||
85694bac | 4490 | /* Expand an atomic fetch-and-operate pattern. CODE is the binary operation |
f155876e | 4491 | to perform. MEM is the memory on which to operate. VAL is the second |
4492 | operand of the binary operator. BEFORE and AFTER are optional locations to | |
4493 | return the value of MEM either before of after the operation. SCRATCH is | |
4494 | a scratch register. */ | |
4495 | ||
4496 | void | |
4497 | alpha_split_atomic_op (enum rtx_code code, rtx mem, rtx val, | |
4498 | rtx before, rtx after, rtx scratch) | |
4499 | { | |
4500 | enum machine_mode mode = GET_MODE (mem); | |
032caa7b | 4501 | rtx label, x, cond = gen_rtx_REG (DImode, REGNO (scratch)); |
f155876e | 4502 | |
4503 | emit_insn (gen_memory_barrier ()); | |
4504 | ||
4505 | label = gen_label_rtx (); | |
4506 | emit_label (label); | |
4507 | label = gen_rtx_LABEL_REF (DImode, label); | |
4508 | ||
4509 | if (before == NULL) | |
4510 | before = scratch; | |
032caa7b | 4511 | emit_load_locked (mode, before, mem); |
f155876e | 4512 | |
4513 | if (code == NOT) | |
6f7e6aa3 | 4514 | { |
4515 | x = gen_rtx_AND (mode, before, val); | |
4516 | emit_insn (gen_rtx_SET (VOIDmode, val, x)); | |
4517 | ||
4518 | x = gen_rtx_NOT (mode, val); | |
4519 | } | |
f155876e | 4520 | else |
4521 | x = gen_rtx_fmt_ee (code, mode, before, val); | |
f155876e | 4522 | if (after) |
4523 | emit_insn (gen_rtx_SET (VOIDmode, after, copy_rtx (x))); | |
87121034 | 4524 | emit_insn (gen_rtx_SET (VOIDmode, scratch, x)); |
f155876e | 4525 | |
032caa7b | 4526 | emit_store_conditional (mode, cond, mem, scratch); |
4527 | ||
4528 | x = gen_rtx_EQ (DImode, cond, const0_rtx); | |
4529 | emit_unlikely_jump (x, label); | |
4530 | ||
4531 | emit_insn (gen_memory_barrier ()); | |
4532 | } | |
4533 | ||
4534 | /* Expand a compare and swap operation. */ | |
4535 | ||
4536 | void | |
4537 | alpha_split_compare_and_swap (rtx retval, rtx mem, rtx oldval, rtx newval, | |
4538 | rtx scratch) | |
4539 | { | |
4540 | enum machine_mode mode = GET_MODE (mem); | |
4541 | rtx label1, label2, x, cond = gen_lowpart (DImode, scratch); | |
4542 | ||
4543 | emit_insn (gen_memory_barrier ()); | |
4544 | ||
4545 | label1 = gen_rtx_LABEL_REF (DImode, gen_label_rtx ()); | |
4546 | label2 = gen_rtx_LABEL_REF (DImode, gen_label_rtx ()); | |
4547 | emit_label (XEXP (label1, 0)); | |
4548 | ||
4549 | emit_load_locked (mode, retval, mem); | |
4550 | ||
4551 | x = gen_lowpart (DImode, retval); | |
4552 | if (oldval == const0_rtx) | |
4553 | x = gen_rtx_NE (DImode, x, const0_rtx); | |
f155876e | 4554 | else |
032caa7b | 4555 | { |
4556 | x = gen_rtx_EQ (DImode, x, oldval); | |
4557 | emit_insn (gen_rtx_SET (VOIDmode, cond, x)); | |
4558 | x = gen_rtx_EQ (DImode, cond, const0_rtx); | |
4559 | } | |
4560 | emit_unlikely_jump (x, label2); | |
4561 | ||
4562 | emit_move_insn (scratch, newval); | |
4563 | emit_store_conditional (mode, cond, mem, scratch); | |
f155876e | 4564 | |
4565 | x = gen_rtx_EQ (DImode, cond, const0_rtx); | |
032caa7b | 4566 | emit_unlikely_jump (x, label1); |
4567 | ||
4568 | emit_insn (gen_memory_barrier ()); | |
4569 | emit_label (XEXP (label2, 0)); | |
4570 | } | |
4571 | ||
596d3184 | 4572 | void |
4573 | alpha_expand_compare_and_swap_12 (rtx dst, rtx mem, rtx oldval, rtx newval) | |
4574 | { | |
4575 | enum machine_mode mode = GET_MODE (mem); | |
4576 | rtx addr, align, wdst; | |
4577 | rtx (*fn5) (rtx, rtx, rtx, rtx, rtx); | |
4578 | ||
4579 | addr = force_reg (DImode, XEXP (mem, 0)); | |
4580 | align = expand_simple_binop (Pmode, AND, addr, GEN_INT (-8), | |
4581 | NULL_RTX, 1, OPTAB_DIRECT); | |
4582 | ||
4583 | oldval = convert_modes (DImode, mode, oldval, 1); | |
4584 | newval = emit_insxl (mode, newval, addr); | |
4585 | ||
4586 | wdst = gen_reg_rtx (DImode); | |
4587 | if (mode == QImode) | |
4588 | fn5 = gen_sync_compare_and_swapqi_1; | |
4589 | else | |
4590 | fn5 = gen_sync_compare_and_swaphi_1; | |
4591 | emit_insn (fn5 (wdst, addr, oldval, newval, align)); | |
4592 | ||
4593 | emit_move_insn (dst, gen_lowpart (mode, wdst)); | |
4594 | } | |
4595 | ||
4596 | void | |
4597 | alpha_split_compare_and_swap_12 (enum machine_mode mode, rtx dest, rtx addr, | |
4598 | rtx oldval, rtx newval, rtx align, | |
4599 | rtx scratch, rtx cond) | |
4600 | { | |
4601 | rtx label1, label2, mem, width, mask, x; | |
4602 | ||
4603 | mem = gen_rtx_MEM (DImode, align); | |
4604 | MEM_VOLATILE_P (mem) = 1; | |
4605 | ||
4606 | emit_insn (gen_memory_barrier ()); | |
4607 | label1 = gen_rtx_LABEL_REF (DImode, gen_label_rtx ()); | |
4608 | label2 = gen_rtx_LABEL_REF (DImode, gen_label_rtx ()); | |
4609 | emit_label (XEXP (label1, 0)); | |
4610 | ||
4611 | emit_load_locked (DImode, scratch, mem); | |
4612 | ||
4613 | width = GEN_INT (GET_MODE_BITSIZE (mode)); | |
4614 | mask = GEN_INT (mode == QImode ? 0xff : 0xffff); | |
4615 | if (WORDS_BIG_ENDIAN) | |
4616 | emit_insn (gen_extxl_be (dest, scratch, width, addr)); | |
4617 | else | |
4618 | emit_insn (gen_extxl_le (dest, scratch, width, addr)); | |
4619 | ||
4620 | if (oldval == const0_rtx) | |
4621 | x = gen_rtx_NE (DImode, dest, const0_rtx); | |
4622 | else | |
4623 | { | |
4624 | x = gen_rtx_EQ (DImode, dest, oldval); | |
4625 | emit_insn (gen_rtx_SET (VOIDmode, cond, x)); | |
4626 | x = gen_rtx_EQ (DImode, cond, const0_rtx); | |
4627 | } | |
4628 | emit_unlikely_jump (x, label2); | |
4629 | ||
4630 | if (WORDS_BIG_ENDIAN) | |
4631 | emit_insn (gen_mskxl_be (scratch, scratch, mask, addr)); | |
4632 | else | |
4633 | emit_insn (gen_mskxl_le (scratch, scratch, mask, addr)); | |
4634 | emit_insn (gen_iordi3 (scratch, scratch, newval)); | |
4635 | ||
4636 | emit_store_conditional (DImode, scratch, mem, scratch); | |
4637 | ||
4638 | x = gen_rtx_EQ (DImode, scratch, const0_rtx); | |
4639 | emit_unlikely_jump (x, label1); | |
4640 | ||
4641 | emit_insn (gen_memory_barrier ()); | |
4642 | emit_label (XEXP (label2, 0)); | |
4643 | } | |
4644 | ||
032caa7b | 4645 | /* Expand an atomic exchange operation. */ |
4646 | ||
4647 | void | |
4648 | alpha_split_lock_test_and_set (rtx retval, rtx mem, rtx val, rtx scratch) | |
4649 | { | |
4650 | enum machine_mode mode = GET_MODE (mem); | |
4651 | rtx label, x, cond = gen_lowpart (DImode, scratch); | |
f155876e | 4652 | |
032caa7b | 4653 | label = gen_rtx_LABEL_REF (DImode, gen_label_rtx ()); |
4654 | emit_label (XEXP (label, 0)); | |
4655 | ||
4656 | emit_load_locked (mode, retval, mem); | |
4657 | emit_move_insn (scratch, val); | |
4658 | emit_store_conditional (mode, cond, mem, scratch); | |
4659 | ||
4660 | x = gen_rtx_EQ (DImode, cond, const0_rtx); | |
4661 | emit_unlikely_jump (x, label); | |
a15b4a3c | 4662 | |
4663 | emit_insn (gen_memory_barrier ()); | |
f155876e | 4664 | } |
596d3184 | 4665 | |
4666 | void | |
4667 | alpha_expand_lock_test_and_set_12 (rtx dst, rtx mem, rtx val) | |
4668 | { | |
4669 | enum machine_mode mode = GET_MODE (mem); | |
4670 | rtx addr, align, wdst; | |
4671 | rtx (*fn4) (rtx, rtx, rtx, rtx); | |
4672 | ||
4673 | /* Force the address into a register. */ | |
4674 | addr = force_reg (DImode, XEXP (mem, 0)); | |
4675 | ||
4676 | /* Align it to a multiple of 8. */ | |
4677 | align = expand_simple_binop (Pmode, AND, addr, GEN_INT (-8), | |
4678 | NULL_RTX, 1, OPTAB_DIRECT); | |
4679 | ||
4680 | /* Insert val into the correct byte location within the word. */ | |
4681 | val = emit_insxl (mode, val, addr); | |
4682 | ||
4683 | wdst = gen_reg_rtx (DImode); | |
4684 | if (mode == QImode) | |
4685 | fn4 = gen_sync_lock_test_and_setqi_1; | |
4686 | else | |
4687 | fn4 = gen_sync_lock_test_and_sethi_1; | |
4688 | emit_insn (fn4 (wdst, addr, val, align)); | |
4689 | ||
4690 | emit_move_insn (dst, gen_lowpart (mode, wdst)); | |
4691 | } | |
4692 | ||
4693 | void | |
4694 | alpha_split_lock_test_and_set_12 (enum machine_mode mode, rtx dest, rtx addr, | |
4695 | rtx val, rtx align, rtx scratch) | |
4696 | { | |
4697 | rtx label, mem, width, mask, x; | |
4698 | ||
4699 | mem = gen_rtx_MEM (DImode, align); | |
4700 | MEM_VOLATILE_P (mem) = 1; | |
4701 | ||
596d3184 | 4702 | label = gen_rtx_LABEL_REF (DImode, gen_label_rtx ()); |
4703 | emit_label (XEXP (label, 0)); | |
4704 | ||
4705 | emit_load_locked (DImode, scratch, mem); | |
4706 | ||
4707 | width = GEN_INT (GET_MODE_BITSIZE (mode)); | |
4708 | mask = GEN_INT (mode == QImode ? 0xff : 0xffff); | |
4709 | if (WORDS_BIG_ENDIAN) | |
4710 | { | |
4711 | emit_insn (gen_extxl_be (dest, scratch, width, addr)); | |
4712 | emit_insn (gen_mskxl_be (scratch, scratch, mask, addr)); | |
4713 | } | |
4714 | else | |
4715 | { | |
4716 | emit_insn (gen_extxl_le (dest, scratch, width, addr)); | |
4717 | emit_insn (gen_mskxl_le (scratch, scratch, mask, addr)); | |
4718 | } | |
4719 | emit_insn (gen_iordi3 (scratch, scratch, val)); | |
4720 | ||
4721 | emit_store_conditional (DImode, scratch, mem, scratch); | |
4722 | ||
4723 | x = gen_rtx_EQ (DImode, scratch, const0_rtx); | |
4724 | emit_unlikely_jump (x, label); | |
a15b4a3c | 4725 | |
4726 | emit_insn (gen_memory_barrier ()); | |
596d3184 | 4727 | } |
bf2a98b3 | 4728 | \f |
4729 | /* Adjust the cost of a scheduling dependency. Return the new cost of | |
4730 | a dependency LINK or INSN on DEP_INSN. COST is the current cost. */ | |
4731 | ||
747af5e7 | 4732 | static int |
92643d95 | 4733 | alpha_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost) |
bf2a98b3 | 4734 | { |
f5e8a4bc | 4735 | enum attr_type dep_insn_type; |
bf2a98b3 | 4736 | |
4737 | /* If the dependence is an anti-dependence, there is no cost. For an | |
4738 | output dependence, there is sometimes a cost, but it doesn't seem | |
4739 | worth handling those few cases. */ | |
bf2a98b3 | 4740 | if (REG_NOTE_KIND (link) != 0) |
7eb0c947 | 4741 | return cost; |
bf2a98b3 | 4742 | |
d2832bd8 | 4743 | /* If we can't recognize the insns, we can't really do anything. */ |
4744 | if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0) | |
4745 | return cost; | |
4746 | ||
d2832bd8 | 4747 | dep_insn_type = get_attr_type (dep_insn); |
4748 | ||
07c1a295 | 4749 | /* Bring in the user-defined memory latency. */ |
e7a69d05 | 4750 | if (dep_insn_type == TYPE_ILD |
4751 | || dep_insn_type == TYPE_FLD | |
4752 | || dep_insn_type == TYPE_LDSYM) | |
07c1a295 | 4753 | cost += alpha_memory_latency-1; |
4754 | ||
7eb0c947 | 4755 | /* Everything else handled in DFA bypasses now. */ |
3680ac41 | 4756 | |
bf2a98b3 | 4757 | return cost; |
4758 | } | |
747af5e7 | 4759 | |
7eb0c947 | 4760 | /* The number of instructions that can be issued per cycle. */ |
4761 | ||
747af5e7 | 4762 | static int |
92643d95 | 4763 | alpha_issue_rate (void) |
747af5e7 | 4764 | { |
fb64edde | 4765 | return (alpha_tune == PROCESSOR_EV4 ? 2 : 4); |
747af5e7 | 4766 | } |
4767 | ||
7eb0c947 | 4768 | /* How many alternative schedules to try. This should be as wide as the |
4769 | scheduling freedom in the DFA, but no wider. Making this value too | |
4770 | large results extra work for the scheduler. | |
4771 | ||
4772 | For EV4, loads can be issued to either IB0 or IB1, thus we have 2 | |
4773 | alternative schedules. For EV5, we can choose between E0/E1 and | |
8d232dc7 | 4774 | FA/FM. For EV6, an arithmetic insn can be issued to U0/U1/L0/L1. */ |
7eb0c947 | 4775 | |
4776 | static int | |
92643d95 | 4777 | alpha_multipass_dfa_lookahead (void) |
7eb0c947 | 4778 | { |
fb64edde | 4779 | return (alpha_tune == PROCESSOR_EV6 ? 4 : 2); |
7eb0c947 | 4780 | } |
0c0464e6 | 4781 | \f |
5f7b9df8 | 4782 | /* Machine-specific function data. */ |
4783 | ||
fb1e4f4a | 4784 | struct GTY(()) machine_function |
5f7b9df8 | 4785 | { |
674a8f0b | 4786 | /* For unicosmk. */ |
5f7b9df8 | 4787 | /* List of call information words for calls from this function. */ |
4788 | struct rtx_def *first_ciw; | |
4789 | struct rtx_def *last_ciw; | |
4790 | int ciw_count; | |
4791 | ||
4792 | /* List of deferred case vectors. */ | |
4793 | struct rtx_def *addr_list; | |
1f3233d1 | 4794 | |
674a8f0b | 4795 | /* For OSF. */ |
5f7b9df8 | 4796 | const char *some_ld_name; |
a221313c | 4797 | |
4798 | /* For TARGET_LD_BUGGY_LDGP. */ | |
4799 | struct rtx_def *gp_save_rtx; | |
50f36bdb | 4800 | |
4801 | /* For VMS condition handlers. */ | |
4802 | bool uses_condition_handler; | |
5f7b9df8 | 4803 | }; |
4804 | ||
1f3233d1 | 4805 | /* How to allocate a 'struct machine_function'. */ |
9caef960 | 4806 | |
1f3233d1 | 4807 | static struct machine_function * |
92643d95 | 4808 | alpha_init_machine_status (void) |
9caef960 | 4809 | { |
9e7454d0 | 4810 | return ((struct machine_function *) |
1f3233d1 | 4811 | ggc_alloc_cleared (sizeof (struct machine_function))); |
9caef960 | 4812 | } |
9caef960 | 4813 | |
50f36bdb | 4814 | /* Support for frame based VMS condition handlers. */ |
4815 | ||
4816 | /* A VMS condition handler may be established for a function with a call to | |
4817 | __builtin_establish_vms_condition_handler, and cancelled with a call to | |
4818 | __builtin_revert_vms_condition_handler. | |
4819 | ||
4820 | The VMS Condition Handling Facility knows about the existence of a handler | |
4821 | from the procedure descriptor .handler field. As the VMS native compilers, | |
4822 | we store the user specified handler's address at a fixed location in the | |
4823 | stack frame and point the procedure descriptor at a common wrapper which | |
4824 | fetches the real handler's address and issues an indirect call. | |
4825 | ||
4826 | The indirection wrapper is "__gcc_shell_handler", provided by libgcc. | |
4827 | ||
4828 | We force the procedure kind to PT_STACK, and the fixed frame location is | |
4829 | fp+8, just before the register save area. We use the handler_data field in | |
4830 | the procedure descriptor to state the fp offset at which the installed | |
4831 | handler address can be found. */ | |
4832 | ||
4833 | #define VMS_COND_HANDLER_FP_OFFSET 8 | |
4834 | ||
4835 | /* Expand code to store the currently installed user VMS condition handler | |
4836 | into TARGET and install HANDLER as the new condition handler. */ | |
4837 | ||
4838 | void | |
4839 | alpha_expand_builtin_establish_vms_condition_handler (rtx target, rtx handler) | |
4840 | { | |
4841 | rtx handler_slot_address | |
4842 | = plus_constant (hard_frame_pointer_rtx, VMS_COND_HANDLER_FP_OFFSET); | |
4843 | ||
4844 | rtx handler_slot | |
4845 | = gen_rtx_MEM (DImode, handler_slot_address); | |
4846 | ||
4847 | emit_move_insn (target, handler_slot); | |
4848 | emit_move_insn (handler_slot, handler); | |
4849 | ||
4850 | /* Notify the start/prologue/epilogue emitters that the condition handler | |
4851 | slot is needed. In addition to reserving the slot space, this will force | |
4852 | the procedure kind to PT_STACK so ensure that the hard_frame_pointer_rtx | |
4853 | use above is correct. */ | |
4854 | cfun->machine->uses_condition_handler = true; | |
4855 | } | |
4856 | ||
4857 | /* Expand code to store the current VMS condition handler into TARGET and | |
4858 | nullify it. */ | |
4859 | ||
4860 | void | |
4861 | alpha_expand_builtin_revert_vms_condition_handler (rtx target) | |
4862 | { | |
4863 | /* We implement this by establishing a null condition handler, with the tiny | |
4864 | side effect of setting uses_condition_handler. This is a little bit | |
4865 | pessimistic if no actual builtin_establish call is ever issued, which is | |
4866 | not a real problem and expected never to happen anyway. */ | |
4867 | ||
4868 | alpha_expand_builtin_establish_vms_condition_handler (target, const0_rtx); | |
4869 | } | |
4870 | ||
0c0464e6 | 4871 | /* Functions to save and restore alpha_return_addr_rtx. */ |
4872 | ||
0c0464e6 | 4873 | /* Start the ball rolling with RETURN_ADDR_RTX. */ |
4874 | ||
4875 | rtx | |
92643d95 | 4876 | alpha_return_addr (int count, rtx frame ATTRIBUTE_UNUSED) |
0c0464e6 | 4877 | { |
0c0464e6 | 4878 | if (count != 0) |
4879 | return const0_rtx; | |
4880 | ||
0f37b7a2 | 4881 | return get_hard_reg_initial_val (Pmode, REG_RA); |
0c0464e6 | 4882 | } |
4883 | ||
a221313c | 4884 | /* Return or create a memory slot containing the gp value for the current |
66561750 | 4885 | function. Needed only if TARGET_LD_BUGGY_LDGP. */ |
4886 | ||
4887 | rtx | |
92643d95 | 4888 | alpha_gp_save_rtx (void) |
66561750 | 4889 | { |
a221313c | 4890 | rtx seq, m = cfun->machine->gp_save_rtx; |
4891 | ||
4892 | if (m == NULL) | |
4893 | { | |
4894 | start_sequence (); | |
4895 | ||
4896 | m = assign_stack_local (DImode, UNITS_PER_WORD, BITS_PER_WORD); | |
4897 | m = validize_mem (m); | |
4898 | emit_move_insn (m, pic_offset_table_rtx); | |
4899 | ||
4900 | seq = get_insns (); | |
4901 | end_sequence (); | |
8a1586ba | 4902 | |
4903 | /* We used to simply emit the sequence after entry_of_function. | |
4904 | However this breaks the CFG if the first instruction in the | |
4905 | first block is not the NOTE_INSN_BASIC_BLOCK, for example a | |
4906 | label. Emit the sequence properly on the edge. We are only | |
4907 | invoked from dw2_build_landing_pads and finish_eh_generation | |
4908 | will call commit_edge_insertions thanks to a kludge. */ | |
4909 | insert_insn_on_edge (seq, single_succ_edge (ENTRY_BLOCK_PTR)); | |
a221313c | 4910 | |
4911 | cfun->machine->gp_save_rtx = m; | |
4912 | } | |
4913 | ||
4914 | return m; | |
66561750 | 4915 | } |
4916 | ||
0c0464e6 | 4917 | static int |
92643d95 | 4918 | alpha_ra_ever_killed (void) |
0c0464e6 | 4919 | { |
5a965225 | 4920 | rtx top; |
4921 | ||
0f37b7a2 | 4922 | if (!has_hard_reg_initial_val (Pmode, REG_RA)) |
3072d30e | 4923 | return (int)df_regs_ever_live_p (REG_RA); |
0c0464e6 | 4924 | |
5a965225 | 4925 | push_topmost_sequence (); |
4926 | top = get_insns (); | |
4927 | pop_topmost_sequence (); | |
4928 | ||
4929 | return reg_set_between_p (gen_rtx_REG (Pmode, REG_RA), top, NULL_RTX); | |
0c0464e6 | 4930 | } |
4931 | ||
bf2a98b3 | 4932 | \f |
6fec94c5 | 4933 | /* Return the trap mode suffix applicable to the current |
65abff06 | 4934 | instruction, or NULL. */ |
bf2a98b3 | 4935 | |
6fec94c5 | 4936 | static const char * |
92643d95 | 4937 | get_trap_mode_suffix (void) |
bf2a98b3 | 4938 | { |
6fec94c5 | 4939 | enum attr_trap_suffix s = get_attr_trap_suffix (current_output_insn); |
bf2a98b3 | 4940 | |
6fec94c5 | 4941 | switch (s) |
bf2a98b3 | 4942 | { |
6fec94c5 | 4943 | case TRAP_SUFFIX_NONE: |
4944 | return NULL; | |
c4622276 | 4945 | |
6fec94c5 | 4946 | case TRAP_SUFFIX_SU: |
bc16f0c1 | 4947 | if (alpha_fptm >= ALPHA_FPTM_SU) |
6fec94c5 | 4948 | return "su"; |
4949 | return NULL; | |
c4622276 | 4950 | |
6fec94c5 | 4951 | case TRAP_SUFFIX_SUI: |
4952 | if (alpha_fptm >= ALPHA_FPTM_SUI) | |
4953 | return "sui"; | |
4954 | return NULL; | |
4955 | ||
4956 | case TRAP_SUFFIX_V_SV: | |
39344852 | 4957 | switch (alpha_fptm) |
4958 | { | |
4959 | case ALPHA_FPTM_N: | |
6fec94c5 | 4960 | return NULL; |
39344852 | 4961 | case ALPHA_FPTM_U: |
6fec94c5 | 4962 | return "v"; |
39344852 | 4963 | case ALPHA_FPTM_SU: |
4964 | case ALPHA_FPTM_SUI: | |
6fec94c5 | 4965 | return "sv"; |
4d10b463 | 4966 | default: |
4967 | gcc_unreachable (); | |
39344852 | 4968 | } |
39344852 | 4969 | |
6fec94c5 | 4970 | case TRAP_SUFFIX_V_SV_SVI: |
b5ea3193 | 4971 | switch (alpha_fptm) |
4972 | { | |
4973 | case ALPHA_FPTM_N: | |
6fec94c5 | 4974 | return NULL; |
b5ea3193 | 4975 | case ALPHA_FPTM_U: |
6fec94c5 | 4976 | return "v"; |
b5ea3193 | 4977 | case ALPHA_FPTM_SU: |
6fec94c5 | 4978 | return "sv"; |
b5ea3193 | 4979 | case ALPHA_FPTM_SUI: |
6fec94c5 | 4980 | return "svi"; |
4d10b463 | 4981 | default: |
4982 | gcc_unreachable (); | |
b5ea3193 | 4983 | } |
4984 | break; | |
4985 | ||
6fec94c5 | 4986 | case TRAP_SUFFIX_U_SU_SUI: |
c4622276 | 4987 | switch (alpha_fptm) |
4988 | { | |
4989 | case ALPHA_FPTM_N: | |
6fec94c5 | 4990 | return NULL; |
c4622276 | 4991 | case ALPHA_FPTM_U: |
6fec94c5 | 4992 | return "u"; |
c4622276 | 4993 | case ALPHA_FPTM_SU: |
6fec94c5 | 4994 | return "su"; |
c4622276 | 4995 | case ALPHA_FPTM_SUI: |
6fec94c5 | 4996 | return "sui"; |
4d10b463 | 4997 | default: |
4998 | gcc_unreachable (); | |
c4622276 | 4999 | } |
5000 | break; | |
4d10b463 | 5001 | |
5002 | default: | |
5003 | gcc_unreachable (); | |
6fec94c5 | 5004 | } |
4d10b463 | 5005 | gcc_unreachable (); |
6fec94c5 | 5006 | } |
c4622276 | 5007 | |
6fec94c5 | 5008 | /* Return the rounding mode suffix applicable to the current |
65abff06 | 5009 | instruction, or NULL. */ |
6fec94c5 | 5010 | |
5011 | static const char * | |
92643d95 | 5012 | get_round_mode_suffix (void) |
6fec94c5 | 5013 | { |
5014 | enum attr_round_suffix s = get_attr_round_suffix (current_output_insn); | |
5015 | ||
5016 | switch (s) | |
5017 | { | |
5018 | case ROUND_SUFFIX_NONE: | |
5019 | return NULL; | |
5020 | case ROUND_SUFFIX_NORMAL: | |
5021 | switch (alpha_fprm) | |
c4622276 | 5022 | { |
6fec94c5 | 5023 | case ALPHA_FPRM_NORM: |
5024 | return NULL; | |
9e7454d0 | 5025 | case ALPHA_FPRM_MINF: |
6fec94c5 | 5026 | return "m"; |
5027 | case ALPHA_FPRM_CHOP: | |
5028 | return "c"; | |
5029 | case ALPHA_FPRM_DYN: | |
5030 | return "d"; | |
4d10b463 | 5031 | default: |
5032 | gcc_unreachable (); | |
c4622276 | 5033 | } |
5034 | break; | |
5035 | ||
6fec94c5 | 5036 | case ROUND_SUFFIX_C: |
5037 | return "c"; | |
4d10b463 | 5038 | |
5039 | default: | |
5040 | gcc_unreachable (); | |
6fec94c5 | 5041 | } |
4d10b463 | 5042 | gcc_unreachable (); |
6fec94c5 | 5043 | } |
5044 | ||
5f7b9df8 | 5045 | /* Locate some local-dynamic symbol still in use by this function |
5046 | so that we can print its name in some movdi_er_tlsldm pattern. */ | |
5047 | ||
92643d95 | 5048 | static int |
5049 | get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED) | |
5050 | { | |
5051 | rtx x = *px; | |
5052 | ||
5053 | if (GET_CODE (x) == SYMBOL_REF | |
5054 | && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC) | |
5055 | { | |
5056 | cfun->machine->some_ld_name = XSTR (x, 0); | |
5057 | return 1; | |
5058 | } | |
5059 | ||
5060 | return 0; | |
5061 | } | |
5062 | ||
5f7b9df8 | 5063 | static const char * |
92643d95 | 5064 | get_some_local_dynamic_name (void) |
5f7b9df8 | 5065 | { |
5066 | rtx insn; | |
5067 | ||
5068 | if (cfun->machine->some_ld_name) | |
5069 | return cfun->machine->some_ld_name; | |
5070 | ||
5071 | for (insn = get_insns (); insn ; insn = NEXT_INSN (insn)) | |
5072 | if (INSN_P (insn) | |
5073 | && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0)) | |
5074 | return cfun->machine->some_ld_name; | |
5075 | ||
4d10b463 | 5076 | gcc_unreachable (); |
5f7b9df8 | 5077 | } |
5078 | ||
6fec94c5 | 5079 | /* Print an operand. Recognize special options, documented below. */ |
5080 | ||
5081 | void | |
92643d95 | 5082 | print_operand (FILE *file, rtx x, int code) |
6fec94c5 | 5083 | { |
5084 | int i; | |
5085 | ||
5086 | switch (code) | |
5087 | { | |
5088 | case '~': | |
5089 | /* Print the assembler name of the current function. */ | |
5090 | assemble_name (file, alpha_fnname); | |
5091 | break; | |
5092 | ||
5f7b9df8 | 5093 | case '&': |
5094 | assemble_name (file, get_some_local_dynamic_name ()); | |
5095 | break; | |
5096 | ||
6fec94c5 | 5097 | case '/': |
5098 | { | |
5099 | const char *trap = get_trap_mode_suffix (); | |
5100 | const char *round = get_round_mode_suffix (); | |
5101 | ||
5102 | if (trap || round) | |
9caef960 | 5103 | fprintf (file, (TARGET_AS_SLASH_BEFORE_SUFFIX ? "/%s%s" : "%s%s"), |
5104 | (trap ? trap : ""), (round ? round : "")); | |
6fec94c5 | 5105 | break; |
5106 | } | |
5107 | ||
8df4a58b | 5108 | case ',': |
5109 | /* Generates single precision instruction suffix. */ | |
6fec94c5 | 5110 | fputc ((TARGET_FLOAT_VAX ? 'f' : 's'), file); |
8df4a58b | 5111 | break; |
5112 | ||
5113 | case '-': | |
5114 | /* Generates double precision instruction suffix. */ | |
6fec94c5 | 5115 | fputc ((TARGET_FLOAT_VAX ? 'g' : 't'), file); |
8df4a58b | 5116 | break; |
5117 | ||
1f0ce6a6 | 5118 | case '#': |
5119 | if (alpha_this_literal_sequence_number == 0) | |
5120 | alpha_this_literal_sequence_number = alpha_next_sequence_number++; | |
5121 | fprintf (file, "%d", alpha_this_literal_sequence_number); | |
5122 | break; | |
5123 | ||
5124 | case '*': | |
5125 | if (alpha_this_gpdisp_sequence_number == 0) | |
5126 | alpha_this_gpdisp_sequence_number = alpha_next_sequence_number++; | |
5127 | fprintf (file, "%d", alpha_this_gpdisp_sequence_number); | |
5128 | break; | |
5129 | ||
5130 | case 'H': | |
5131 | if (GET_CODE (x) == HIGH) | |
5dcb037d | 5132 | output_addr_const (file, XEXP (x, 0)); |
1f0ce6a6 | 5133 | else |
5134 | output_operand_lossage ("invalid %%H value"); | |
5135 | break; | |
5136 | ||
ad2ed779 | 5137 | case 'J': |
5f7b9df8 | 5138 | { |
5139 | const char *lituse; | |
5140 | ||
5141 | if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSGD_CALL) | |
5142 | { | |
5143 | x = XVECEXP (x, 0, 0); | |
5144 | lituse = "lituse_tlsgd"; | |
5145 | } | |
5146 | else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSLDM_CALL) | |
5147 | { | |
5148 | x = XVECEXP (x, 0, 0); | |
5149 | lituse = "lituse_tlsldm"; | |
5150 | } | |
c933fb42 | 5151 | else if (CONST_INT_P (x)) |
5f7b9df8 | 5152 | lituse = "lituse_jsr"; |
5153 | else | |
5154 | { | |
5155 | output_operand_lossage ("invalid %%J value"); | |
5156 | break; | |
5157 | } | |
5158 | ||
5159 | if (x != const0_rtx) | |
5160 | fprintf (file, "\t\t!%s!%d", lituse, (int) INTVAL (x)); | |
5161 | } | |
ad2ed779 | 5162 | break; |
5163 | ||
592222c2 | 5164 | case 'j': |
5165 | { | |
5166 | const char *lituse; | |
5167 | ||
5168 | #ifdef HAVE_AS_JSRDIRECT_RELOCS | |
5169 | lituse = "lituse_jsrdirect"; | |
5170 | #else | |
5171 | lituse = "lituse_jsr"; | |
5172 | #endif | |
5173 | ||
5174 | gcc_assert (INTVAL (x) != 0); | |
5175 | fprintf (file, "\t\t!%s!%d", lituse, (int) INTVAL (x)); | |
5176 | } | |
5177 | break; | |
bf2a98b3 | 5178 | case 'r': |
5179 | /* If this operand is the constant zero, write it as "$31". */ | |
c933fb42 | 5180 | if (REG_P (x)) |
bf2a98b3 | 5181 | fprintf (file, "%s", reg_names[REGNO (x)]); |
5182 | else if (x == CONST0_RTX (GET_MODE (x))) | |
5183 | fprintf (file, "$31"); | |
5184 | else | |
5185 | output_operand_lossage ("invalid %%r value"); | |
bf2a98b3 | 5186 | break; |
5187 | ||
5188 | case 'R': | |
5189 | /* Similar, but for floating-point. */ | |
c933fb42 | 5190 | if (REG_P (x)) |
bf2a98b3 | 5191 | fprintf (file, "%s", reg_names[REGNO (x)]); |
5192 | else if (x == CONST0_RTX (GET_MODE (x))) | |
5193 | fprintf (file, "$f31"); | |
5194 | else | |
5195 | output_operand_lossage ("invalid %%R value"); | |
bf2a98b3 | 5196 | break; |
5197 | ||
5198 | case 'N': | |
5199 | /* Write the 1's complement of a constant. */ | |
c933fb42 | 5200 | if (!CONST_INT_P (x)) |
bf2a98b3 | 5201 | output_operand_lossage ("invalid %%N value"); |
5202 | ||
61a63ca5 | 5203 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INTVAL (x)); |
bf2a98b3 | 5204 | break; |
5205 | ||
5206 | case 'P': | |
5207 | /* Write 1 << C, for a constant C. */ | |
c933fb42 | 5208 | if (!CONST_INT_P (x)) |
bf2a98b3 | 5209 | output_operand_lossage ("invalid %%P value"); |
5210 | ||
61a63ca5 | 5211 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, (HOST_WIDE_INT) 1 << INTVAL (x)); |
bf2a98b3 | 5212 | break; |
5213 | ||
5214 | case 'h': | |
5215 | /* Write the high-order 16 bits of a constant, sign-extended. */ | |
c933fb42 | 5216 | if (!CONST_INT_P (x)) |
bf2a98b3 | 5217 | output_operand_lossage ("invalid %%h value"); |
5218 | ||
61a63ca5 | 5219 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) >> 16); |
bf2a98b3 | 5220 | break; |
5221 | ||
5222 | case 'L': | |
5223 | /* Write the low-order 16 bits of a constant, sign-extended. */ | |
c933fb42 | 5224 | if (!CONST_INT_P (x)) |
bf2a98b3 | 5225 | output_operand_lossage ("invalid %%L value"); |
5226 | ||
61a63ca5 | 5227 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, |
5228 | (INTVAL (x) & 0xffff) - 2 * (INTVAL (x) & 0x8000)); | |
bf2a98b3 | 5229 | break; |
5230 | ||
5231 | case 'm': | |
5232 | /* Write mask for ZAP insn. */ | |
5233 | if (GET_CODE (x) == CONST_DOUBLE) | |
5234 | { | |
5235 | HOST_WIDE_INT mask = 0; | |
5236 | HOST_WIDE_INT value; | |
5237 | ||
5238 | value = CONST_DOUBLE_LOW (x); | |
5239 | for (i = 0; i < HOST_BITS_PER_WIDE_INT / HOST_BITS_PER_CHAR; | |
5240 | i++, value >>= 8) | |
5241 | if (value & 0xff) | |
5242 | mask |= (1 << i); | |
5243 | ||
5244 | value = CONST_DOUBLE_HIGH (x); | |
5245 | for (i = 0; i < HOST_BITS_PER_WIDE_INT / HOST_BITS_PER_CHAR; | |
5246 | i++, value >>= 8) | |
5247 | if (value & 0xff) | |
5248 | mask |= (1 << (i + sizeof (int))); | |
5249 | ||
61a63ca5 | 5250 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, mask & 0xff); |
bf2a98b3 | 5251 | } |
5252 | ||
c933fb42 | 5253 | else if (CONST_INT_P (x)) |
bf2a98b3 | 5254 | { |
5255 | HOST_WIDE_INT mask = 0, value = INTVAL (x); | |
5256 | ||
5257 | for (i = 0; i < 8; i++, value >>= 8) | |
5258 | if (value & 0xff) | |
5259 | mask |= (1 << i); | |
5260 | ||
61a63ca5 | 5261 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, mask); |
bf2a98b3 | 5262 | } |
5263 | else | |
5264 | output_operand_lossage ("invalid %%m value"); | |
5265 | break; | |
5266 | ||
5267 | case 'M': | |
34377880 | 5268 | /* 'b', 'w', 'l', or 'q' as the value of the constant. */ |
c933fb42 | 5269 | if (!CONST_INT_P (x) |
34377880 | 5270 | || (INTVAL (x) != 8 && INTVAL (x) != 16 |
5271 | && INTVAL (x) != 32 && INTVAL (x) != 64)) | |
bf2a98b3 | 5272 | output_operand_lossage ("invalid %%M value"); |
5273 | ||
5274 | fprintf (file, "%s", | |
34377880 | 5275 | (INTVAL (x) == 8 ? "b" |
5276 | : INTVAL (x) == 16 ? "w" | |
5277 | : INTVAL (x) == 32 ? "l" | |
5278 | : "q")); | |
bf2a98b3 | 5279 | break; |
5280 | ||
5281 | case 'U': | |
5282 | /* Similar, except do it from the mask. */ | |
c933fb42 | 5283 | if (CONST_INT_P (x)) |
ae4cd3a5 | 5284 | { |
5285 | HOST_WIDE_INT value = INTVAL (x); | |
5286 | ||
5287 | if (value == 0xff) | |
5288 | { | |
5289 | fputc ('b', file); | |
5290 | break; | |
5291 | } | |
5292 | if (value == 0xffff) | |
5293 | { | |
5294 | fputc ('w', file); | |
5295 | break; | |
5296 | } | |
5297 | if (value == 0xffffffff) | |
5298 | { | |
5299 | fputc ('l', file); | |
5300 | break; | |
5301 | } | |
5302 | if (value == -1) | |
5303 | { | |
5304 | fputc ('q', file); | |
5305 | break; | |
5306 | } | |
5307 | } | |
5308 | else if (HOST_BITS_PER_WIDE_INT == 32 | |
5309 | && GET_CODE (x) == CONST_DOUBLE | |
5310 | && CONST_DOUBLE_LOW (x) == 0xffffffff | |
5311 | && CONST_DOUBLE_HIGH (x) == 0) | |
5312 | { | |
5313 | fputc ('l', file); | |
5314 | break; | |
5315 | } | |
5316 | output_operand_lossage ("invalid %%U value"); | |
bf2a98b3 | 5317 | break; |
5318 | ||
5319 | case 's': | |
9caef960 | 5320 | /* Write the constant value divided by 8 for little-endian mode or |
5321 | (56 - value) / 8 for big-endian mode. */ | |
5322 | ||
c933fb42 | 5323 | if (!CONST_INT_P (x) |
9caef960 | 5324 | || (unsigned HOST_WIDE_INT) INTVAL (x) >= (WORDS_BIG_ENDIAN |
5325 | ? 56 | |
9e7454d0 | 5326 | : 64) |
9caef960 | 5327 | || (INTVAL (x) & 7) != 0) |
bf2a98b3 | 5328 | output_operand_lossage ("invalid %%s value"); |
5329 | ||
9caef960 | 5330 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, |
5331 | WORDS_BIG_ENDIAN | |
5332 | ? (56 - INTVAL (x)) / 8 | |
5333 | : INTVAL (x) / 8); | |
bf2a98b3 | 5334 | break; |
5335 | ||
5336 | case 'S': | |
5337 | /* Same, except compute (64 - c) / 8 */ | |
5338 | ||
c933fb42 | 5339 | if (!CONST_INT_P (x) |
bf2a98b3 | 5340 | && (unsigned HOST_WIDE_INT) INTVAL (x) >= 64 |
5341 | && (INTVAL (x) & 7) != 8) | |
5342 | output_operand_lossage ("invalid %%s value"); | |
5343 | ||
61a63ca5 | 5344 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, (64 - INTVAL (x)) / 8); |
bf2a98b3 | 5345 | break; |
5346 | ||
9caef960 | 5347 | case 't': |
5348 | { | |
5349 | /* On Unicos/Mk systems: use a DEX expression if the symbol | |
5350 | clashes with a register name. */ | |
5351 | int dex = unicosmk_need_dex (x); | |
5352 | if (dex) | |
5353 | fprintf (file, "DEX(%d)", dex); | |
5354 | else | |
5355 | output_addr_const (file, x); | |
5356 | } | |
5357 | break; | |
5358 | ||
62dc3582 | 5359 | case 'C': case 'D': case 'c': case 'd': |
bf2a98b3 | 5360 | /* Write out comparison name. */ |
62dc3582 | 5361 | { |
5362 | enum rtx_code c = GET_CODE (x); | |
5363 | ||
6720e96c | 5364 | if (!COMPARISON_P (x)) |
62dc3582 | 5365 | output_operand_lossage ("invalid %%C value"); |
5366 | ||
f3d263a7 | 5367 | else if (code == 'D') |
62dc3582 | 5368 | c = reverse_condition (c); |
5369 | else if (code == 'c') | |
5370 | c = swap_condition (c); | |
5371 | else if (code == 'd') | |
5372 | c = swap_condition (reverse_condition (c)); | |
5373 | ||
5374 | if (c == LEU) | |
5375 | fprintf (file, "ule"); | |
5376 | else if (c == LTU) | |
5377 | fprintf (file, "ult"); | |
a4110d9a | 5378 | else if (c == UNORDERED) |
5379 | fprintf (file, "un"); | |
62dc3582 | 5380 | else |
5381 | fprintf (file, "%s", GET_RTX_NAME (c)); | |
5382 | } | |
8ad50a44 | 5383 | break; |
5384 | ||
bf2a98b3 | 5385 | case 'E': |
5386 | /* Write the divide or modulus operator. */ | |
5387 | switch (GET_CODE (x)) | |
5388 | { | |
5389 | case DIV: | |
5390 | fprintf (file, "div%s", GET_MODE (x) == SImode ? "l" : "q"); | |
5391 | break; | |
5392 | case UDIV: | |
5393 | fprintf (file, "div%su", GET_MODE (x) == SImode ? "l" : "q"); | |
5394 | break; | |
5395 | case MOD: | |
5396 | fprintf (file, "rem%s", GET_MODE (x) == SImode ? "l" : "q"); | |
5397 | break; | |
5398 | case UMOD: | |
5399 | fprintf (file, "rem%su", GET_MODE (x) == SImode ? "l" : "q"); | |
5400 | break; | |
5401 | default: | |
5402 | output_operand_lossage ("invalid %%E value"); | |
5403 | break; | |
5404 | } | |
5405 | break; | |
5406 | ||
bf2a98b3 | 5407 | case 'A': |
5408 | /* Write "_u" for unaligned access. */ | |
c933fb42 | 5409 | if (MEM_P (x) && GET_CODE (XEXP (x, 0)) == AND) |
bf2a98b3 | 5410 | fprintf (file, "_u"); |
5411 | break; | |
5412 | ||
5413 | case 0: | |
c933fb42 | 5414 | if (REG_P (x)) |
bf2a98b3 | 5415 | fprintf (file, "%s", reg_names[REGNO (x)]); |
c933fb42 | 5416 | else if (MEM_P (x)) |
bf2a98b3 | 5417 | output_address (XEXP (x, 0)); |
5f7b9df8 | 5418 | else if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == UNSPEC) |
5419 | { | |
5420 | switch (XINT (XEXP (x, 0), 1)) | |
5421 | { | |
5422 | case UNSPEC_DTPREL: | |
5423 | case UNSPEC_TPREL: | |
5424 | output_addr_const (file, XVECEXP (XEXP (x, 0), 0, 0)); | |
5425 | break; | |
5426 | default: | |
5427 | output_operand_lossage ("unknown relocation unspec"); | |
5428 | break; | |
5429 | } | |
5430 | } | |
bf2a98b3 | 5431 | else |
5432 | output_addr_const (file, x); | |
5433 | break; | |
5434 | ||
5435 | default: | |
5436 | output_operand_lossage ("invalid %%xn code"); | |
5437 | } | |
5438 | } | |
6e0fe99e | 5439 | |
5440 | void | |
92643d95 | 5441 | print_operand_address (FILE *file, rtx addr) |
6e0fe99e | 5442 | { |
a3e39a24 | 5443 | int basereg = 31; |
6e0fe99e | 5444 | HOST_WIDE_INT offset = 0; |
5445 | ||
5446 | if (GET_CODE (addr) == AND) | |
5447 | addr = XEXP (addr, 0); | |
6e0fe99e | 5448 | |
a3e39a24 | 5449 | if (GET_CODE (addr) == PLUS |
c933fb42 | 5450 | && CONST_INT_P (XEXP (addr, 1))) |
6e0fe99e | 5451 | { |
5452 | offset = INTVAL (XEXP (addr, 1)); | |
a3e39a24 | 5453 | addr = XEXP (addr, 0); |
6e0fe99e | 5454 | } |
1f0ce6a6 | 5455 | |
5456 | if (GET_CODE (addr) == LO_SUM) | |
5457 | { | |
5f7b9df8 | 5458 | const char *reloc16, *reloclo; |
5459 | rtx op1 = XEXP (addr, 1); | |
5460 | ||
5461 | if (GET_CODE (op1) == CONST && GET_CODE (XEXP (op1, 0)) == UNSPEC) | |
5462 | { | |
5463 | op1 = XEXP (op1, 0); | |
5464 | switch (XINT (op1, 1)) | |
5465 | { | |
5466 | case UNSPEC_DTPREL: | |
5467 | reloc16 = NULL; | |
5468 | reloclo = (alpha_tls_size == 16 ? "dtprel" : "dtprello"); | |
5469 | break; | |
5470 | case UNSPEC_TPREL: | |
5471 | reloc16 = NULL; | |
5472 | reloclo = (alpha_tls_size == 16 ? "tprel" : "tprello"); | |
5473 | break; | |
5474 | default: | |
5475 | output_operand_lossage ("unknown relocation unspec"); | |
5476 | return; | |
5477 | } | |
5478 | ||
5479 | output_addr_const (file, XVECEXP (op1, 0, 0)); | |
5480 | } | |
5481 | else | |
5482 | { | |
5483 | reloc16 = "gprel"; | |
5484 | reloclo = "gprellow"; | |
5485 | output_addr_const (file, op1); | |
5486 | } | |
5487 | ||
1f0ce6a6 | 5488 | if (offset) |
4840a03a | 5489 | fprintf (file, "+" HOST_WIDE_INT_PRINT_DEC, offset); |
9e7454d0 | 5490 | |
1f0ce6a6 | 5491 | addr = XEXP (addr, 0); |
4d10b463 | 5492 | switch (GET_CODE (addr)) |
5493 | { | |
5494 | case REG: | |
5495 | basereg = REGNO (addr); | |
5496 | break; | |
5497 | ||
5498 | case SUBREG: | |
5499 | basereg = subreg_regno (addr); | |
5500 | break; | |
5501 | ||
5502 | default: | |
5503 | gcc_unreachable (); | |
5504 | } | |
5dcb037d | 5505 | |
5506 | fprintf (file, "($%d)\t\t!%s", basereg, | |
5f7b9df8 | 5507 | (basereg == 29 ? reloc16 : reloclo)); |
1f0ce6a6 | 5508 | return; |
5509 | } | |
5510 | ||
4d10b463 | 5511 | switch (GET_CODE (addr)) |
5512 | { | |
5513 | case REG: | |
5514 | basereg = REGNO (addr); | |
5515 | break; | |
5516 | ||
5517 | case SUBREG: | |
5518 | basereg = subreg_regno (addr); | |
5519 | break; | |
5520 | ||
5521 | case CONST_INT: | |
5522 | offset = INTVAL (addr); | |
5523 | break; | |
cf73d31f | 5524 | |
5525 | #if TARGET_ABI_OPEN_VMS | |
4d10b463 | 5526 | case SYMBOL_REF: |
cf73d31f | 5527 | fprintf (file, "%s", XSTR (addr, 0)); |
5528 | return; | |
4d10b463 | 5529 | |
5530 | case CONST: | |
5531 | gcc_assert (GET_CODE (XEXP (addr, 0)) == PLUS | |
5532 | && GET_CODE (XEXP (XEXP (addr, 0), 0)) == SYMBOL_REF); | |
6433714e | 5533 | fprintf (file, "%s+" HOST_WIDE_INT_PRINT_DEC, |
cf73d31f | 5534 | XSTR (XEXP (XEXP (addr, 0), 0), 0), |
5535 | INTVAL (XEXP (XEXP (addr, 0), 1))); | |
5536 | return; | |
4d10b463 | 5537 | |
cf73d31f | 5538 | #endif |
4d10b463 | 5539 | default: |
5540 | gcc_unreachable (); | |
5541 | } | |
6e0fe99e | 5542 | |
4840a03a | 5543 | fprintf (file, HOST_WIDE_INT_PRINT_DEC "($%d)", offset, basereg); |
6e0fe99e | 5544 | } |
bf2a98b3 | 5545 | \f |
9e042f31 | 5546 | /* Emit RTL insns to initialize the variable parts of a trampoline at |
7bcbe23a | 5547 | M_TRAMP. FNDECL is target function's decl. CHAIN_VALUE is an rtx |
5548 | for the static chain value for the function. */ | |
96297568 | 5549 | |
7bcbe23a | 5550 | static void |
5551 | alpha_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value) | |
9e042f31 | 5552 | { |
7bcbe23a | 5553 | rtx fnaddr, mem, word1, word2; |
5554 | ||
5555 | fnaddr = XEXP (DECL_RTL (fndecl), 0); | |
9e042f31 | 5556 | |
17683b9f | 5557 | #ifdef POINTERS_EXTEND_UNSIGNED |
7bcbe23a | 5558 | fnaddr = convert_memory_address (Pmode, fnaddr); |
5559 | chain_value = convert_memory_address (Pmode, chain_value); | |
17683b9f | 5560 | #endif |
5561 | ||
d2f33c43 | 5562 | if (TARGET_ABI_OPEN_VMS) |
5563 | { | |
d2f33c43 | 5564 | const char *fnname; |
5565 | char *trname; | |
5566 | ||
5567 | /* Construct the name of the trampoline entry point. */ | |
5568 | fnname = XSTR (fnaddr, 0); | |
5569 | trname = (char *) alloca (strlen (fnname) + 5); | |
5570 | strcpy (trname, fnname); | |
5571 | strcat (trname, "..tr"); | |
7bcbe23a | 5572 | fnname = ggc_alloc_string (trname, strlen (trname) + 1); |
5573 | word2 = gen_rtx_SYMBOL_REF (Pmode, fnname); | |
d2f33c43 | 5574 | |
5575 | /* Trampoline (or "bounded") procedure descriptor is constructed from | |
5576 | the function's procedure descriptor with certain fields zeroed IAW | |
5577 | the VMS calling standard. This is stored in the first quadword. */ | |
7bcbe23a | 5578 | word1 = force_reg (DImode, gen_const_mem (DImode, fnaddr)); |
5579 | word1 = expand_and (DImode, word1, GEN_INT (0xffff0fff0000fff0), NULL); | |
d2f33c43 | 5580 | } |
7bcbe23a | 5581 | else |
5582 | { | |
5583 | /* These 4 instructions are: | |
5584 | ldq $1,24($27) | |
5585 | ldq $27,16($27) | |
5586 | jmp $31,($27),0 | |
5587 | nop | |
5588 | We don't bother setting the HINT field of the jump; the nop | |
5589 | is merely there for padding. */ | |
5590 | word1 = GEN_INT (0xa77b0010a43b0018); | |
5591 | word2 = GEN_INT (0x47ff041f6bfb0000); | |
5592 | } | |
5593 | ||
5594 | /* Store the first two words, as computed above. */ | |
5595 | mem = adjust_address (m_tramp, DImode, 0); | |
5596 | emit_move_insn (mem, word1); | |
5597 | mem = adjust_address (m_tramp, DImode, 8); | |
5598 | emit_move_insn (mem, word2); | |
5599 | ||
5600 | /* Store function address and static chain value. */ | |
5601 | mem = adjust_address (m_tramp, Pmode, 16); | |
5602 | emit_move_insn (mem, fnaddr); | |
5603 | mem = adjust_address (m_tramp, Pmode, 24); | |
5604 | emit_move_insn (mem, chain_value); | |
d2f33c43 | 5605 | |
7bcbe23a | 5606 | if (!TARGET_ABI_OPEN_VMS) |
5607 | { | |
5608 | emit_insn (gen_imb ()); | |
5577e296 | 5609 | #ifdef ENABLE_EXECUTE_STACK |
7bcbe23a | 5610 | emit_library_call (init_one_libfunc ("__enable_execute_stack"), |
5611 | LCT_NORMAL, VOIDmode, 1, XEXP (m_tramp, 0), Pmode); | |
9e042f31 | 5612 | #endif |
7bcbe23a | 5613 | } |
9e042f31 | 5614 | } |
5615 | \f | |
915c336f | 5616 | /* Determine where to put an argument to a function. |
5617 | Value is zero to push the argument on the stack, | |
5618 | or a hard register in which to store the argument. | |
5619 | ||
5620 | MODE is the argument's machine mode. | |
5621 | TYPE is the data type of the argument (as a tree). | |
5622 | This is null for libcalls where that information may | |
5623 | not be available. | |
5624 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
5625 | the preceding args and about the function being called. | |
5626 | NAMED is nonzero if this argument is a named parameter | |
5627 | (otherwise it is an extra parameter matching an ellipsis). | |
5628 | ||
5629 | On Alpha the first 6 words of args are normally in registers | |
5630 | and the rest are pushed. */ | |
5631 | ||
5632 | rtx | |
92643d95 | 5633 | function_arg (CUMULATIVE_ARGS cum, enum machine_mode mode, tree type, |
5634 | int named ATTRIBUTE_UNUSED) | |
915c336f | 5635 | { |
5636 | int basereg; | |
57e47080 | 5637 | int num_args; |
915c336f | 5638 | |
a685f5d8 | 5639 | /* Don't get confused and pass small structures in FP registers. */ |
5640 | if (type && AGGREGATE_TYPE_P (type)) | |
9caef960 | 5641 | basereg = 16; |
a685f5d8 | 5642 | else |
5643 | { | |
5644 | #ifdef ENABLE_CHECKING | |
92d40bc4 | 5645 | /* With alpha_split_complex_arg, we shouldn't see any raw complex |
a685f5d8 | 5646 | values here. */ |
4d10b463 | 5647 | gcc_assert (!COMPLEX_MODE_P (mode)); |
a685f5d8 | 5648 | #endif |
5649 | ||
5650 | /* Set up defaults for FP operands passed in FP registers, and | |
5651 | integral operands passed in integer registers. */ | |
5652 | if (TARGET_FPREGS && GET_MODE_CLASS (mode) == MODE_FLOAT) | |
5653 | basereg = 32 + 16; | |
5654 | else | |
5655 | basereg = 16; | |
5656 | } | |
9caef960 | 5657 | |
5658 | /* ??? Irritatingly, the definition of CUMULATIVE_ARGS is different for | |
5659 | the three platforms, so we can't avoid conditional compilation. */ | |
1467e953 | 5660 | #if TARGET_ABI_OPEN_VMS |
9caef960 | 5661 | { |
5662 | if (mode == VOIDmode) | |
5663 | return alpha_arg_info_reg_val (cum); | |
1467e953 | 5664 | |
9caef960 | 5665 | num_args = cum.num_args; |
0336f0f0 | 5666 | if (num_args >= 6 |
5667 | || targetm.calls.must_pass_in_stack (mode, type)) | |
9caef960 | 5668 | return NULL_RTX; |
5669 | } | |
a685f5d8 | 5670 | #elif TARGET_ABI_UNICOSMK |
9caef960 | 5671 | { |
5672 | int size; | |
915c336f | 5673 | |
9caef960 | 5674 | /* If this is the last argument, generate the call info word (CIW). */ |
5675 | /* ??? We don't include the caller's line number in the CIW because | |
5676 | I don't know how to determine it if debug infos are turned off. */ | |
5677 | if (mode == VOIDmode) | |
5678 | { | |
5679 | int i; | |
5680 | HOST_WIDE_INT lo; | |
5681 | HOST_WIDE_INT hi; | |
5682 | rtx ciw; | |
5683 | ||
5684 | lo = 0; | |
5685 | ||
5686 | for (i = 0; i < cum.num_reg_words && i < 5; i++) | |
5687 | if (cum.reg_args_type[i]) | |
5688 | lo |= (1 << (7 - i)); | |
5689 | ||
5690 | if (cum.num_reg_words == 6 && cum.reg_args_type[5]) | |
5691 | lo |= 7; | |
5692 | else | |
5693 | lo |= cum.num_reg_words; | |
5694 | ||
5695 | #if HOST_BITS_PER_WIDE_INT == 32 | |
5696 | hi = (cum.num_args << 20) | cum.num_arg_words; | |
5697 | #else | |
e162157f | 5698 | lo = lo | ((HOST_WIDE_INT) cum.num_args << 52) |
5699 | | ((HOST_WIDE_INT) cum.num_arg_words << 32); | |
9caef960 | 5700 | hi = 0; |
5701 | #endif | |
5702 | ciw = immed_double_const (lo, hi, DImode); | |
5703 | ||
5704 | return gen_rtx_UNSPEC (DImode, gen_rtvec (1, ciw), | |
5705 | UNSPEC_UMK_LOAD_CIW); | |
5706 | } | |
5707 | ||
5708 | size = ALPHA_ARG_SIZE (mode, type, named); | |
5709 | num_args = cum.num_reg_words; | |
0336f0f0 | 5710 | if (cum.force_stack |
5711 | || cum.num_reg_words + size > 6 | |
5712 | || targetm.calls.must_pass_in_stack (mode, type)) | |
9caef960 | 5713 | return NULL_RTX; |
5714 | else if (type && TYPE_MODE (type) == BLKmode) | |
5715 | { | |
5716 | rtx reg1, reg2; | |
5717 | ||
5718 | reg1 = gen_rtx_REG (DImode, num_args + 16); | |
5719 | reg1 = gen_rtx_EXPR_LIST (DImode, reg1, const0_rtx); | |
5720 | ||
5721 | /* The argument fits in two registers. Note that we still need to | |
5722 | reserve a register for empty structures. */ | |
5723 | if (size == 0) | |
5724 | return NULL_RTX; | |
5725 | else if (size == 1) | |
5726 | return gen_rtx_PARALLEL (mode, gen_rtvec (1, reg1)); | |
5727 | else | |
5728 | { | |
5729 | reg2 = gen_rtx_REG (DImode, num_args + 17); | |
5730 | reg2 = gen_rtx_EXPR_LIST (DImode, reg2, GEN_INT (8)); | |
5731 | return gen_rtx_PARALLEL (mode, gen_rtvec (2, reg1, reg2)); | |
5732 | } | |
5733 | } | |
5734 | } | |
a685f5d8 | 5735 | #elif TARGET_ABI_OSF |
9caef960 | 5736 | { |
5737 | if (cum >= 6) | |
5738 | return NULL_RTX; | |
5739 | num_args = cum; | |
5740 | ||
5741 | /* VOID is passed as a special flag for "last argument". */ | |
5742 | if (type == void_type_node) | |
5743 | basereg = 16; | |
0336f0f0 | 5744 | else if (targetm.calls.must_pass_in_stack (mode, type)) |
9caef960 | 5745 | return NULL_RTX; |
9caef960 | 5746 | } |
a685f5d8 | 5747 | #else |
5748 | #error Unhandled ABI | |
5749 | #endif | |
915c336f | 5750 | |
57e47080 | 5751 | return gen_rtx_REG (mode, num_args + basereg); |
915c336f | 5752 | } |
5753 | ||
f054eb3c | 5754 | static int |
5755 | alpha_arg_partial_bytes (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED, | |
5756 | enum machine_mode mode ATTRIBUTE_UNUSED, | |
5757 | tree type ATTRIBUTE_UNUSED, | |
5758 | bool named ATTRIBUTE_UNUSED) | |
5759 | { | |
5760 | int words = 0; | |
5761 | ||
5762 | #if TARGET_ABI_OPEN_VMS | |
5763 | if (cum->num_args < 6 | |
5764 | && 6 < cum->num_args + ALPHA_ARG_SIZE (mode, type, named)) | |
5c5b637a | 5765 | words = 6 - cum->num_args; |
f054eb3c | 5766 | #elif TARGET_ABI_UNICOSMK |
5767 | /* Never any split arguments. */ | |
5768 | #elif TARGET_ABI_OSF | |
5769 | if (*cum < 6 && 6 < *cum + ALPHA_ARG_SIZE (mode, type, named)) | |
5770 | words = 6 - *cum; | |
5771 | #else | |
5772 | #error Unhandled ABI | |
5773 | #endif | |
5774 | ||
5775 | return words * UNITS_PER_WORD; | |
5776 | } | |
5777 | ||
5778 | ||
a685f5d8 | 5779 | /* Return true if TYPE must be returned in memory, instead of in registers. */ |
5780 | ||
dd9f3024 | 5781 | static bool |
fb80456a | 5782 | alpha_return_in_memory (const_tree type, const_tree fndecl ATTRIBUTE_UNUSED) |
a685f5d8 | 5783 | { |
dd9f3024 | 5784 | enum machine_mode mode = VOIDmode; |
a685f5d8 | 5785 | int size; |
5786 | ||
5787 | if (type) | |
5788 | { | |
5789 | mode = TYPE_MODE (type); | |
5790 | ||
cfdbb1f5 | 5791 | /* All aggregates are returned in memory, except on OpenVMS where |
5792 | records that fit 64 bits should be returned by immediate value | |
5793 | as required by section 3.8.7.1 of the OpenVMS Calling Standard. */ | |
5794 | if (TARGET_ABI_OPEN_VMS | |
5795 | && TREE_CODE (type) != ARRAY_TYPE | |
5796 | && (unsigned HOST_WIDE_INT) int_size_in_bytes(type) <= 8) | |
5797 | return false; | |
5798 | ||
a685f5d8 | 5799 | if (AGGREGATE_TYPE_P (type)) |
5800 | return true; | |
5801 | } | |
5802 | ||
5803 | size = GET_MODE_SIZE (mode); | |
5804 | switch (GET_MODE_CLASS (mode)) | |
5805 | { | |
5806 | case MODE_VECTOR_FLOAT: | |
5807 | /* Pass all float vectors in memory, like an aggregate. */ | |
5808 | return true; | |
5809 | ||
5810 | case MODE_COMPLEX_FLOAT: | |
5811 | /* We judge complex floats on the size of their element, | |
5812 | not the size of the whole type. */ | |
5813 | size = GET_MODE_UNIT_SIZE (mode); | |
5814 | break; | |
5815 | ||
5816 | case MODE_INT: | |
5817 | case MODE_FLOAT: | |
5818 | case MODE_COMPLEX_INT: | |
5819 | case MODE_VECTOR_INT: | |
5820 | break; | |
5821 | ||
5822 | default: | |
9e7454d0 | 5823 | /* ??? We get called on all sorts of random stuff from |
4d10b463 | 5824 | aggregate_value_p. We must return something, but it's not |
5825 | clear what's safe to return. Pretend it's a struct I | |
5826 | guess. */ | |
a685f5d8 | 5827 | return true; |
5828 | } | |
5829 | ||
5830 | /* Otherwise types must fit in one register. */ | |
5831 | return size > UNITS_PER_WORD; | |
5832 | } | |
5833 | ||
b981d932 | 5834 | /* Return true if TYPE should be passed by invisible reference. */ |
5835 | ||
5836 | static bool | |
5837 | alpha_pass_by_reference (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED, | |
5838 | enum machine_mode mode, | |
fb80456a | 5839 | const_tree type ATTRIBUTE_UNUSED, |
b981d932 | 5840 | bool named ATTRIBUTE_UNUSED) |
5841 | { | |
5842 | return mode == TFmode || mode == TCmode; | |
5843 | } | |
5844 | ||
a685f5d8 | 5845 | /* Define how to find the value returned by a function. VALTYPE is the |
5846 | data type of the value (as a tree). If the precise function being | |
5847 | called is known, FUNC is its FUNCTION_DECL; otherwise, FUNC is 0. | |
5848 | MODE is set instead of VALTYPE for libcalls. | |
5849 | ||
5850 | On Alpha the value is found in $0 for integer functions and | |
5851 | $f0 for floating-point functions. */ | |
5852 | ||
5853 | rtx | |
fb80456a | 5854 | function_value (const_tree valtype, const_tree func ATTRIBUTE_UNUSED, |
a685f5d8 | 5855 | enum machine_mode mode) |
5856 | { | |
f5e8a4bc | 5857 | unsigned int regnum, dummy ATTRIBUTE_UNUSED; |
8deb3959 | 5858 | enum mode_class mclass; |
a685f5d8 | 5859 | |
4d10b463 | 5860 | gcc_assert (!valtype || !alpha_return_in_memory (valtype, func)); |
a685f5d8 | 5861 | |
5862 | if (valtype) | |
5863 | mode = TYPE_MODE (valtype); | |
5864 | ||
8deb3959 | 5865 | mclass = GET_MODE_CLASS (mode); |
5866 | switch (mclass) | |
a685f5d8 | 5867 | { |
5868 | case MODE_INT: | |
cfdbb1f5 | 5869 | /* Do the same thing as PROMOTE_MODE except for libcalls on VMS, |
5870 | where we have them returning both SImode and DImode. */ | |
5871 | if (!(TARGET_ABI_OPEN_VMS && valtype && AGGREGATE_TYPE_P (valtype))) | |
5872 | PROMOTE_MODE (mode, dummy, valtype); | |
8e262b5e | 5873 | /* FALLTHRU */ |
a685f5d8 | 5874 | |
5875 | case MODE_COMPLEX_INT: | |
5876 | case MODE_VECTOR_INT: | |
5877 | regnum = 0; | |
5878 | break; | |
5879 | ||
5880 | case MODE_FLOAT: | |
5881 | regnum = 32; | |
5882 | break; | |
5883 | ||
5884 | case MODE_COMPLEX_FLOAT: | |
5885 | { | |
5886 | enum machine_mode cmode = GET_MODE_INNER (mode); | |
5887 | ||
5888 | return gen_rtx_PARALLEL | |
5889 | (VOIDmode, | |
5890 | gen_rtvec (2, | |
5891 | gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_REG (cmode, 32), | |
bcd9bd66 | 5892 | const0_rtx), |
a685f5d8 | 5893 | gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_REG (cmode, 33), |
5894 | GEN_INT (GET_MODE_SIZE (cmode))))); | |
5895 | } | |
5896 | ||
cfdbb1f5 | 5897 | case MODE_RANDOM: |
5898 | /* We should only reach here for BLKmode on VMS. */ | |
5899 | gcc_assert (TARGET_ABI_OPEN_VMS && mode == BLKmode); | |
5900 | regnum = 0; | |
5901 | break; | |
5902 | ||
a685f5d8 | 5903 | default: |
4d10b463 | 5904 | gcc_unreachable (); |
a685f5d8 | 5905 | } |
5906 | ||
5907 | return gen_rtx_REG (mode, regnum); | |
5908 | } | |
5909 | ||
9e7454d0 | 5910 | /* TCmode complex values are passed by invisible reference. We |
92d40bc4 | 5911 | should not split these values. */ |
5912 | ||
5913 | static bool | |
a9f1838b | 5914 | alpha_split_complex_arg (const_tree type) |
92d40bc4 | 5915 | { |
5916 | return TYPE_MODE (type) != TCmode; | |
5917 | } | |
5918 | ||
2e15d750 | 5919 | static tree |
5920 | alpha_build_builtin_va_list (void) | |
bf2a98b3 | 5921 | { |
7ba21c9f | 5922 | tree base, ofs, space, record, type_decl; |
bf2a98b3 | 5923 | |
9caef960 | 5924 | if (TARGET_ABI_OPEN_VMS || TARGET_ABI_UNICOSMK) |
e7aabeab | 5925 | return ptr_type_node; |
5926 | ||
a1f71e15 | 5927 | record = (*lang_hooks.types.make_type) (RECORD_TYPE); |
54e46243 | 5928 | type_decl = build_decl (BUILTINS_LOCATION, |
5929 | TYPE_DECL, get_identifier ("__va_list_tag"), record); | |
0054fd98 | 5930 | TREE_CHAIN (record) = type_decl; |
5931 | TYPE_NAME (record) = type_decl; | |
5932 | ||
e7aabeab | 5933 | /* C++? SET_IS_AGGR_TYPE (record, 1); */ |
bf2a98b3 | 5934 | |
7ba21c9f | 5935 | /* Dummy field to prevent alignment warnings. */ |
54e46243 | 5936 | space = build_decl (BUILTINS_LOCATION, |
5937 | FIELD_DECL, NULL_TREE, integer_type_node); | |
7ba21c9f | 5938 | DECL_FIELD_CONTEXT (space) = record; |
5939 | DECL_ARTIFICIAL (space) = 1; | |
5940 | DECL_IGNORED_P (space) = 1; | |
5941 | ||
54e46243 | 5942 | ofs = build_decl (BUILTINS_LOCATION, |
5943 | FIELD_DECL, get_identifier ("__offset"), | |
e7aabeab | 5944 | integer_type_node); |
5945 | DECL_FIELD_CONTEXT (ofs) = record; | |
7ba21c9f | 5946 | TREE_CHAIN (ofs) = space; |
fc4c89ed | 5947 | |
54e46243 | 5948 | base = build_decl (BUILTINS_LOCATION, |
5949 | FIELD_DECL, get_identifier ("__base"), | |
e7aabeab | 5950 | ptr_type_node); |
5951 | DECL_FIELD_CONTEXT (base) = record; | |
5952 | TREE_CHAIN (base) = ofs; | |
fc4c89ed | 5953 | |
e7aabeab | 5954 | TYPE_FIELDS (record) = base; |
5955 | layout_type (record); | |
5956 | ||
a6c787e5 | 5957 | va_list_gpr_counter_field = ofs; |
e7aabeab | 5958 | return record; |
5959 | } | |
5960 | ||
7955d282 | 5961 | #if TARGET_ABI_OSF |
a6c787e5 | 5962 | /* Helper function for alpha_stdarg_optimize_hook. Skip over casts |
5963 | and constant additions. */ | |
5964 | ||
94c0325b | 5965 | static gimple |
a6c787e5 | 5966 | va_list_skip_additions (tree lhs) |
5967 | { | |
94c0325b | 5968 | gimple stmt; |
a6c787e5 | 5969 | |
5970 | for (;;) | |
5971 | { | |
94c0325b | 5972 | enum tree_code code; |
5973 | ||
a6c787e5 | 5974 | stmt = SSA_NAME_DEF_STMT (lhs); |
5975 | ||
94c0325b | 5976 | if (gimple_code (stmt) == GIMPLE_PHI) |
a6c787e5 | 5977 | return stmt; |
5978 | ||
94c0325b | 5979 | if (!is_gimple_assign (stmt) |
5980 | || gimple_assign_lhs (stmt) != lhs) | |
5981 | return NULL; | |
a6c787e5 | 5982 | |
94c0325b | 5983 | if (TREE_CODE (gimple_assign_rhs1 (stmt)) != SSA_NAME) |
5984 | return stmt; | |
5985 | code = gimple_assign_rhs_code (stmt); | |
5986 | if (!CONVERT_EXPR_CODE_P (code) | |
5987 | && ((code != PLUS_EXPR && code != POINTER_PLUS_EXPR) | |
5988 | || TREE_CODE (gimple_assign_rhs2 (stmt)) != INTEGER_CST | |
5989 | || !host_integerp (gimple_assign_rhs2 (stmt), 1))) | |
5990 | return stmt; | |
a6c787e5 | 5991 | |
94c0325b | 5992 | lhs = gimple_assign_rhs1 (stmt); |
a6c787e5 | 5993 | } |
5994 | } | |
5995 | ||
5996 | /* Check if LHS = RHS statement is | |
5997 | LHS = *(ap.__base + ap.__offset + cst) | |
5998 | or | |
5999 | LHS = *(ap.__base | |
6000 | + ((ap.__offset + cst <= 47) | |
6001 | ? ap.__offset + cst - 48 : ap.__offset + cst) + cst2). | |
6002 | If the former, indicate that GPR registers are needed, | |
6003 | if the latter, indicate that FPR registers are needed. | |
adde8f91 | 6004 | |
6005 | Also look for LHS = (*ptr).field, where ptr is one of the forms | |
6006 | listed above. | |
6007 | ||
a6c787e5 | 6008 | On alpha, cfun->va_list_gpr_size is used as size of the needed |
adde8f91 | 6009 | regs and cfun->va_list_fpr_size is a bitmask, bit 0 set if GPR |
6010 | registers are needed and bit 1 set if FPR registers are needed. | |
6011 | Return true if va_list references should not be scanned for the | |
6012 | current statement. */ | |
a6c787e5 | 6013 | |
6014 | static bool | |
75a70cf9 | 6015 | alpha_stdarg_optimize_hook (struct stdarg_info *si, const_gimple stmt) |
a6c787e5 | 6016 | { |
94c0325b | 6017 | tree base, offset, rhs; |
a6c787e5 | 6018 | int offset_arg = 1; |
94c0325b | 6019 | gimple base_stmt; |
a6c787e5 | 6020 | |
94c0325b | 6021 | if (get_gimple_rhs_class (gimple_assign_rhs_code (stmt)) |
6022 | != GIMPLE_SINGLE_RHS) | |
6023 | return false; | |
6024 | ||
6025 | rhs = gimple_assign_rhs1 (stmt); | |
adde8f91 | 6026 | while (handled_component_p (rhs)) |
6027 | rhs = TREE_OPERAND (rhs, 0); | |
a6c787e5 | 6028 | if (TREE_CODE (rhs) != INDIRECT_REF |
6029 | || TREE_CODE (TREE_OPERAND (rhs, 0)) != SSA_NAME) | |
6030 | return false; | |
6031 | ||
94c0325b | 6032 | stmt = va_list_skip_additions (TREE_OPERAND (rhs, 0)); |
6033 | if (stmt == NULL | |
6034 | || !is_gimple_assign (stmt) | |
6035 | || gimple_assign_rhs_code (stmt) != POINTER_PLUS_EXPR) | |
a6c787e5 | 6036 | return false; |
6037 | ||
94c0325b | 6038 | base = gimple_assign_rhs1 (stmt); |
a6c787e5 | 6039 | if (TREE_CODE (base) == SSA_NAME) |
94c0325b | 6040 | { |
6041 | base_stmt = va_list_skip_additions (base); | |
6042 | if (base_stmt | |
6043 | && is_gimple_assign (base_stmt) | |
6044 | && gimple_assign_rhs_code (base_stmt) == COMPONENT_REF) | |
6045 | base = gimple_assign_rhs1 (base_stmt); | |
6046 | } | |
a6c787e5 | 6047 | |
6048 | if (TREE_CODE (base) != COMPONENT_REF | |
6049 | || TREE_OPERAND (base, 1) != TYPE_FIELDS (va_list_type_node)) | |
6050 | { | |
94c0325b | 6051 | base = gimple_assign_rhs2 (stmt); |
a6c787e5 | 6052 | if (TREE_CODE (base) == SSA_NAME) |
94c0325b | 6053 | { |
6054 | base_stmt = va_list_skip_additions (base); | |
6055 | if (base_stmt | |
6056 | && is_gimple_assign (base_stmt) | |
6057 | && gimple_assign_rhs_code (base_stmt) == COMPONENT_REF) | |
6058 | base = gimple_assign_rhs1 (base_stmt); | |
6059 | } | |
a6c787e5 | 6060 | |
6061 | if (TREE_CODE (base) != COMPONENT_REF | |
6062 | || TREE_OPERAND (base, 1) != TYPE_FIELDS (va_list_type_node)) | |
6063 | return false; | |
6064 | ||
6065 | offset_arg = 0; | |
6066 | } | |
6067 | ||
6068 | base = get_base_address (base); | |
6069 | if (TREE_CODE (base) != VAR_DECL | |
dda53cd5 | 6070 | || !bitmap_bit_p (si->va_list_vars, DECL_UID (base))) |
a6c787e5 | 6071 | return false; |
6072 | ||
94c0325b | 6073 | offset = gimple_op (stmt, 1 + offset_arg); |
a6c787e5 | 6074 | if (TREE_CODE (offset) == SSA_NAME) |
a6c787e5 | 6075 | { |
94c0325b | 6076 | gimple offset_stmt = va_list_skip_additions (offset); |
a6c787e5 | 6077 | |
94c0325b | 6078 | if (offset_stmt |
6079 | && gimple_code (offset_stmt) == GIMPLE_PHI) | |
a6c787e5 | 6080 | { |
94c0325b | 6081 | HOST_WIDE_INT sub; |
6082 | gimple arg1_stmt, arg2_stmt; | |
6083 | tree arg1, arg2; | |
6084 | enum tree_code code1, code2; | |
a6c787e5 | 6085 | |
94c0325b | 6086 | if (gimple_phi_num_args (offset_stmt) != 2) |
7955d282 | 6087 | goto escapes; |
a6c787e5 | 6088 | |
94c0325b | 6089 | arg1_stmt |
6090 | = va_list_skip_additions (gimple_phi_arg_def (offset_stmt, 0)); | |
6091 | arg2_stmt | |
6092 | = va_list_skip_additions (gimple_phi_arg_def (offset_stmt, 1)); | |
6093 | if (arg1_stmt == NULL | |
6094 | || !is_gimple_assign (arg1_stmt) | |
6095 | || arg2_stmt == NULL | |
6096 | || !is_gimple_assign (arg2_stmt)) | |
6097 | goto escapes; | |
a6c787e5 | 6098 | |
94c0325b | 6099 | code1 = gimple_assign_rhs_code (arg1_stmt); |
6100 | code2 = gimple_assign_rhs_code (arg2_stmt); | |
6101 | if (code1 == COMPONENT_REF | |
6102 | && (code2 == MINUS_EXPR || code2 == PLUS_EXPR)) | |
6103 | /* Do nothing. */; | |
6104 | else if (code2 == COMPONENT_REF | |
6105 | && (code1 == MINUS_EXPR || code1 == PLUS_EXPR)) | |
6106 | { | |
6107 | gimple tem = arg1_stmt; | |
6108 | code2 = code1; | |
6109 | arg1_stmt = arg2_stmt; | |
6110 | arg2_stmt = tem; | |
6111 | } | |
6112 | else | |
6113 | goto escapes; | |
7955d282 | 6114 | |
94c0325b | 6115 | if (!host_integerp (gimple_assign_rhs2 (arg2_stmt), 0)) |
6116 | goto escapes; | |
7955d282 | 6117 | |
94c0325b | 6118 | sub = tree_low_cst (gimple_assign_rhs2 (arg2_stmt), 0); |
6119 | if (code2 == MINUS_EXPR) | |
6120 | sub = -sub; | |
6121 | if (sub < -48 || sub > -32) | |
6122 | goto escapes; | |
a6c787e5 | 6123 | |
94c0325b | 6124 | arg1 = gimple_assign_rhs1 (arg1_stmt); |
6125 | arg2 = gimple_assign_rhs1 (arg2_stmt); | |
6126 | if (TREE_CODE (arg2) == SSA_NAME) | |
6127 | { | |
6128 | arg2_stmt = va_list_skip_additions (arg2); | |
6129 | if (arg2_stmt == NULL | |
6130 | || !is_gimple_assign (arg2_stmt) | |
6131 | || gimple_assign_rhs_code (arg2_stmt) != COMPONENT_REF) | |
6132 | goto escapes; | |
6133 | arg2 = gimple_assign_rhs1 (arg2_stmt); | |
6134 | } | |
6135 | if (arg1 != arg2) | |
6136 | goto escapes; | |
6137 | ||
6138 | if (TREE_CODE (arg1) != COMPONENT_REF | |
6139 | || TREE_OPERAND (arg1, 1) != va_list_gpr_counter_field | |
6140 | || get_base_address (arg1) != base) | |
6141 | goto escapes; | |
6142 | ||
6143 | /* Need floating point regs. */ | |
6144 | cfun->va_list_fpr_size |= 2; | |
6145 | return false; | |
6146 | } | |
6147 | if (offset_stmt | |
6148 | && is_gimple_assign (offset_stmt) | |
6149 | && gimple_assign_rhs_code (offset_stmt) == COMPONENT_REF) | |
6150 | offset = gimple_assign_rhs1 (offset_stmt); | |
6151 | } | |
6152 | if (TREE_CODE (offset) != COMPONENT_REF | |
6153 | || TREE_OPERAND (offset, 1) != va_list_gpr_counter_field | |
6154 | || get_base_address (offset) != base) | |
a6c787e5 | 6155 | goto escapes; |
6156 | else | |
6157 | /* Need general regs. */ | |
6158 | cfun->va_list_fpr_size |= 1; | |
6159 | return false; | |
6160 | ||
6161 | escapes: | |
6162 | si->va_list_escapes = true; | |
6163 | return false; | |
6164 | } | |
7955d282 | 6165 | #endif |
a6c787e5 | 6166 | |
4310aa50 | 6167 | /* Perform any needed actions needed for a function that is receiving a |
dd9f3024 | 6168 | variable number of arguments. */ |
4310aa50 | 6169 | |
dd9f3024 | 6170 | static void |
2dc656b7 | 6171 | alpha_setup_incoming_varargs (CUMULATIVE_ARGS *pcum, enum machine_mode mode, |
6172 | tree type, int *pretend_size, int no_rtl) | |
dd9f3024 | 6173 | { |
2dc656b7 | 6174 | CUMULATIVE_ARGS cum = *pcum; |
6175 | ||
6176 | /* Skip the current argument. */ | |
6177 | FUNCTION_ARG_ADVANCE (cum, mode, type, 1); | |
6178 | ||
dd9f3024 | 6179 | #if TARGET_ABI_UNICOSMK |
6180 | /* On Unicos/Mk, the standard subroutine __T3E_MISMATCH stores all register | |
6181 | arguments on the stack. Unfortunately, it doesn't always store the first | |
6182 | one (i.e. the one that arrives in $16 or $f16). This is not a problem | |
6183 | with stdargs as we always have at least one named argument there. */ | |
2dc656b7 | 6184 | if (cum.num_reg_words < 6) |
dd9f3024 | 6185 | { |
6186 | if (!no_rtl) | |
6187 | { | |
2dc656b7 | 6188 | emit_insn (gen_umk_mismatch_args (GEN_INT (cum.num_reg_words))); |
dd9f3024 | 6189 | emit_insn (gen_arg_home_umk ()); |
6190 | } | |
6191 | *pretend_size = 0; | |
6192 | } | |
6193 | #elif TARGET_ABI_OPEN_VMS | |
6194 | /* For VMS, we allocate space for all 6 arg registers plus a count. | |
4310aa50 | 6195 | |
dd9f3024 | 6196 | However, if NO registers need to be saved, don't allocate any space. |
6197 | This is not only because we won't need the space, but because AP | |
6198 | includes the current_pretend_args_size and we don't want to mess up | |
6199 | any ap-relative addresses already made. */ | |
2dc656b7 | 6200 | if (cum.num_args < 6) |
dd9f3024 | 6201 | { |
6202 | if (!no_rtl) | |
6203 | { | |
6204 | emit_move_insn (gen_rtx_REG (DImode, 1), virtual_incoming_args_rtx); | |
6205 | emit_insn (gen_arg_home ()); | |
6206 | } | |
6207 | *pretend_size = 7 * UNITS_PER_WORD; | |
6208 | } | |
6209 | #else | |
6210 | /* On OSF/1 and friends, we allocate space for all 12 arg registers, but | |
6211 | only push those that are remaining. However, if NO registers need to | |
6212 | be saved, don't allocate any space. This is not only because we won't | |
6213 | need the space, but because AP includes the current_pretend_args_size | |
6214 | and we don't want to mess up any ap-relative addresses already made. | |
6215 | ||
6216 | If we are not to use the floating-point registers, save the integer | |
6217 | registers where we would put the floating-point registers. This is | |
6218 | not the most efficient way to implement varargs with just one register | |
6219 | class, but it isn't worth doing anything more efficient in this rare | |
6220 | case. */ | |
4310aa50 | 6221 | if (cum >= 6) |
6222 | return; | |
6223 | ||
6224 | if (!no_rtl) | |
6225 | { | |
32c2fdea | 6226 | int count; |
6227 | alias_set_type set = get_varargs_alias_set (); | |
4310aa50 | 6228 | rtx tmp; |
6229 | ||
7955d282 | 6230 | count = cfun->va_list_gpr_size / UNITS_PER_WORD; |
6231 | if (count > 6 - cum) | |
6232 | count = 6 - cum; | |
4310aa50 | 6233 | |
7955d282 | 6234 | /* Detect whether integer registers or floating-point registers |
6235 | are needed by the detected va_arg statements. See above for | |
6236 | how these values are computed. Note that the "escape" value | |
6237 | is VA_LIST_MAX_FPR_SIZE, which is 255, which has both of | |
6238 | these bits set. */ | |
6239 | gcc_assert ((VA_LIST_MAX_FPR_SIZE & 3) == 3); | |
6240 | ||
6241 | if (cfun->va_list_fpr_size & 1) | |
6242 | { | |
6243 | tmp = gen_rtx_MEM (BLKmode, | |
6244 | plus_constant (virtual_incoming_args_rtx, | |
6245 | (cum + 6) * UNITS_PER_WORD)); | |
ae2dd339 | 6246 | MEM_NOTRAP_P (tmp) = 1; |
7955d282 | 6247 | set_mem_alias_set (tmp, set); |
6248 | move_block_from_reg (16 + cum, tmp, count); | |
6249 | } | |
6250 | ||
6251 | if (cfun->va_list_fpr_size & 2) | |
6252 | { | |
6253 | tmp = gen_rtx_MEM (BLKmode, | |
6254 | plus_constant (virtual_incoming_args_rtx, | |
6255 | cum * UNITS_PER_WORD)); | |
ae2dd339 | 6256 | MEM_NOTRAP_P (tmp) = 1; |
7955d282 | 6257 | set_mem_alias_set (tmp, set); |
6258 | move_block_from_reg (16 + cum + TARGET_FPREGS*32, tmp, count); | |
6259 | } | |
6260 | } | |
4310aa50 | 6261 | *pretend_size = 12 * UNITS_PER_WORD; |
f6940372 | 6262 | #endif |
dd9f3024 | 6263 | } |
4310aa50 | 6264 | |
8a58ed0a | 6265 | static void |
92643d95 | 6266 | alpha_va_start (tree valist, rtx nextarg ATTRIBUTE_UNUSED) |
e7aabeab | 6267 | { |
6268 | HOST_WIDE_INT offset; | |
6269 | tree t, offset_field, base_field; | |
fc4c89ed | 6270 | |
80909c64 | 6271 | if (TREE_CODE (TREE_TYPE (valist)) == ERROR_MARK) |
6272 | return; | |
6273 | ||
fc264da3 | 6274 | if (TARGET_ABI_UNICOSMK) |
7df226a2 | 6275 | std_expand_builtin_va_start (valist, nextarg); |
e7aabeab | 6276 | |
6644435d | 6277 | /* For Unix, TARGET_SETUP_INCOMING_VARARGS moves the starting address base |
e7aabeab | 6278 | up by 48, storing fp arg registers in the first 48 bytes, and the |
6279 | integer arg registers in the next 48 bytes. This is only done, | |
6280 | however, if any integer registers need to be stored. | |
6281 | ||
6282 | If no integer registers need be stored, then we must subtract 48 | |
6283 | in order to account for the integer arg registers which are counted | |
4310aa50 | 6284 | in argsize above, but which are not actually stored on the stack. |
6285 | Must further be careful here about structures straddling the last | |
9e7454d0 | 6286 | integer argument register; that futzes with pretend_args_size, |
4310aa50 | 6287 | which changes the meaning of AP. */ |
e7aabeab | 6288 | |
2dc656b7 | 6289 | if (NUM_ARGS < 6) |
fc264da3 | 6290 | offset = TARGET_ABI_OPEN_VMS ? UNITS_PER_WORD : 6 * UNITS_PER_WORD; |
8df4a58b | 6291 | else |
abe32cce | 6292 | offset = -6 * UNITS_PER_WORD + crtl->args.pretend_args_size; |
e7aabeab | 6293 | |
fc264da3 | 6294 | if (TARGET_ABI_OPEN_VMS) |
6295 | { | |
cfdbb1f5 | 6296 | t = make_tree (ptr_type_node, virtual_incoming_args_rtx); |
6297 | t = build2 (POINTER_PLUS_EXPR, ptr_type_node, t, | |
6298 | size_int (offset + NUM_ARGS * UNITS_PER_WORD)); | |
6299 | t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist, t); | |
fc264da3 | 6300 | TREE_SIDE_EFFECTS (t) = 1; |
fc264da3 | 6301 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); |
6302 | } | |
6303 | else | |
6304 | { | |
6305 | base_field = TYPE_FIELDS (TREE_TYPE (valist)); | |
6306 | offset_field = TREE_CHAIN (base_field); | |
6307 | ||
ed03eadb | 6308 | base_field = build3 (COMPONENT_REF, TREE_TYPE (base_field), |
6309 | valist, base_field, NULL_TREE); | |
6310 | offset_field = build3 (COMPONENT_REF, TREE_TYPE (offset_field), | |
6311 | valist, offset_field, NULL_TREE); | |
fc264da3 | 6312 | |
6313 | t = make_tree (ptr_type_node, virtual_incoming_args_rtx); | |
8920b6b9 | 6314 | t = build2 (POINTER_PLUS_EXPR, ptr_type_node, t, |
6315 | size_int (offset)); | |
75a70cf9 | 6316 | t = build2 (MODIFY_EXPR, TREE_TYPE (base_field), base_field, t); |
fc264da3 | 6317 | TREE_SIDE_EFFECTS (t) = 1; |
6318 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
6319 | ||
7016c612 | 6320 | t = build_int_cst (NULL_TREE, NUM_ARGS * UNITS_PER_WORD); |
75a70cf9 | 6321 | t = build2 (MODIFY_EXPR, TREE_TYPE (offset_field), offset_field, t); |
fc264da3 | 6322 | TREE_SIDE_EFFECTS (t) = 1; |
6323 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
6324 | } | |
e7aabeab | 6325 | } |
6326 | ||
de8f9b94 | 6327 | static tree |
94c0325b | 6328 | alpha_gimplify_va_arg_1 (tree type, tree base, tree offset, |
75a70cf9 | 6329 | gimple_seq *pre_p) |
de8f9b94 | 6330 | { |
94c0325b | 6331 | tree type_size, ptr_type, addend, t, addr; |
6332 | gimple_seq internal_post; | |
de8f9b94 | 6333 | |
de8f9b94 | 6334 | /* If the type could not be passed in registers, skip the block |
6335 | reserved for the registers. */ | |
0336f0f0 | 6336 | if (targetm.calls.must_pass_in_stack (TYPE_MODE (type), type)) |
de8f9b94 | 6337 | { |
7016c612 | 6338 | t = build_int_cst (TREE_TYPE (offset), 6*8); |
75a70cf9 | 6339 | gimplify_assign (offset, |
6340 | build2 (MAX_EXPR, TREE_TYPE (offset), offset, t), | |
6341 | pre_p); | |
de8f9b94 | 6342 | } |
6343 | ||
6344 | addend = offset; | |
bd746187 | 6345 | ptr_type = build_pointer_type_for_mode (type, ptr_mode, true); |
de8f9b94 | 6346 | |
2cd7bb84 | 6347 | if (TREE_CODE (type) == COMPLEX_TYPE) |
de8f9b94 | 6348 | { |
6349 | tree real_part, imag_part, real_temp; | |
6350 | ||
c7b3f103 | 6351 | real_part = alpha_gimplify_va_arg_1 (TREE_TYPE (type), base, |
6352 | offset, pre_p); | |
6353 | ||
6354 | /* Copy the value into a new temporary, lest the formal temporary | |
de8f9b94 | 6355 | be reused out from under us. */ |
c7b3f103 | 6356 | real_temp = get_initialized_tmp_var (real_part, pre_p, NULL); |
de8f9b94 | 6357 | |
c7b3f103 | 6358 | imag_part = alpha_gimplify_va_arg_1 (TREE_TYPE (type), base, |
6359 | offset, pre_p); | |
de8f9b94 | 6360 | |
ed03eadb | 6361 | return build2 (COMPLEX_EXPR, type, real_temp, imag_part); |
de8f9b94 | 6362 | } |
6363 | else if (TREE_CODE (type) == REAL_TYPE) | |
6364 | { | |
6365 | tree fpaddend, cond, fourtyeight; | |
6366 | ||
7016c612 | 6367 | fourtyeight = build_int_cst (TREE_TYPE (addend), 6*8); |
ed03eadb | 6368 | fpaddend = fold_build2 (MINUS_EXPR, TREE_TYPE (addend), |
6369 | addend, fourtyeight); | |
6370 | cond = fold_build2 (LT_EXPR, boolean_type_node, addend, fourtyeight); | |
6371 | addend = fold_build3 (COND_EXPR, TREE_TYPE (addend), cond, | |
6372 | fpaddend, addend); | |
de8f9b94 | 6373 | } |
6374 | ||
6375 | /* Build the final address and force that value into a temporary. */ | |
8920b6b9 | 6376 | addr = build2 (POINTER_PLUS_EXPR, ptr_type, fold_convert (ptr_type, base), |
6377 | fold_convert (sizetype, addend)); | |
c7b3f103 | 6378 | internal_post = NULL; |
6379 | gimplify_expr (&addr, pre_p, &internal_post, is_gimple_val, fb_rvalue); | |
94c0325b | 6380 | gimple_seq_add_seq (pre_p, internal_post); |
de8f9b94 | 6381 | |
6382 | /* Update the offset field. */ | |
c7b3f103 | 6383 | type_size = TYPE_SIZE_UNIT (TYPE_MAIN_VARIANT (type)); |
6384 | if (type_size == NULL || TREE_OVERFLOW (type_size)) | |
6385 | t = size_zero_node; | |
6386 | else | |
6387 | { | |
6388 | t = size_binop (PLUS_EXPR, type_size, size_int (7)); | |
6389 | t = size_binop (TRUNC_DIV_EXPR, t, size_int (8)); | |
6390 | t = size_binop (MULT_EXPR, t, size_int (8)); | |
6391 | } | |
6392 | t = fold_convert (TREE_TYPE (offset), t); | |
75a70cf9 | 6393 | gimplify_assign (offset, build2 (PLUS_EXPR, TREE_TYPE (offset), offset, t), |
6394 | pre_p); | |
de8f9b94 | 6395 | |
063f5fdd | 6396 | return build_va_arg_indirect_ref (addr); |
de8f9b94 | 6397 | } |
6398 | ||
e0eca1fa | 6399 | static tree |
75a70cf9 | 6400 | alpha_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p, |
6401 | gimple_seq *post_p) | |
de8f9b94 | 6402 | { |
e0eca1fa | 6403 | tree offset_field, base_field, offset, base, t, r; |
2cd7bb84 | 6404 | bool indirect; |
de8f9b94 | 6405 | |
6406 | if (TARGET_ABI_OPEN_VMS || TARGET_ABI_UNICOSMK) | |
e0eca1fa | 6407 | return std_gimplify_va_arg_expr (valist, type, pre_p, post_p); |
de8f9b94 | 6408 | |
6409 | base_field = TYPE_FIELDS (va_list_type_node); | |
6410 | offset_field = TREE_CHAIN (base_field); | |
ed03eadb | 6411 | base_field = build3 (COMPONENT_REF, TREE_TYPE (base_field), |
6412 | valist, base_field, NULL_TREE); | |
6413 | offset_field = build3 (COMPONENT_REF, TREE_TYPE (offset_field), | |
6414 | valist, offset_field, NULL_TREE); | |
de8f9b94 | 6415 | |
c7b3f103 | 6416 | /* Pull the fields of the structure out into temporaries. Since we never |
6417 | modify the base field, we can use a formal temporary. Sign-extend the | |
6418 | offset field so that it's the proper width for pointer arithmetic. */ | |
6419 | base = get_formal_tmp_var (base_field, pre_p); | |
de8f9b94 | 6420 | |
c7b3f103 | 6421 | t = fold_convert (lang_hooks.types.type_for_size (64, 0), offset_field); |
6422 | offset = get_initialized_tmp_var (t, pre_p, NULL); | |
de8f9b94 | 6423 | |
2cd7bb84 | 6424 | indirect = pass_by_reference (NULL, TYPE_MODE (type), type, false); |
6425 | if (indirect) | |
bd746187 | 6426 | type = build_pointer_type_for_mode (type, ptr_mode, true); |
2cd7bb84 | 6427 | |
de8f9b94 | 6428 | /* Find the value. Note that this will be a stable indirection, or |
6429 | a composite of stable indirections in the case of complex. */ | |
c7b3f103 | 6430 | r = alpha_gimplify_va_arg_1 (type, base, offset, pre_p); |
de8f9b94 | 6431 | |
6432 | /* Stuff the offset temporary back into its field. */ | |
94c0325b | 6433 | gimplify_assign (unshare_expr (offset_field), |
75a70cf9 | 6434 | fold_convert (TREE_TYPE (offset_field), offset), pre_p); |
e0eca1fa | 6435 | |
2cd7bb84 | 6436 | if (indirect) |
063f5fdd | 6437 | r = build_va_arg_indirect_ref (r); |
2cd7bb84 | 6438 | |
e0eca1fa | 6439 | return r; |
de8f9b94 | 6440 | } |
bf2a98b3 | 6441 | \f |
f2cc13dc | 6442 | /* Builtins. */ |
6443 | ||
6444 | enum alpha_builtin | |
6445 | { | |
6446 | ALPHA_BUILTIN_CMPBGE, | |
ae4cd3a5 | 6447 | ALPHA_BUILTIN_EXTBL, |
6448 | ALPHA_BUILTIN_EXTWL, | |
6449 | ALPHA_BUILTIN_EXTLL, | |
f2cc13dc | 6450 | ALPHA_BUILTIN_EXTQL, |
ae4cd3a5 | 6451 | ALPHA_BUILTIN_EXTWH, |
6452 | ALPHA_BUILTIN_EXTLH, | |
f2cc13dc | 6453 | ALPHA_BUILTIN_EXTQH, |
ae4cd3a5 | 6454 | ALPHA_BUILTIN_INSBL, |
6455 | ALPHA_BUILTIN_INSWL, | |
6456 | ALPHA_BUILTIN_INSLL, | |
6457 | ALPHA_BUILTIN_INSQL, | |
6458 | ALPHA_BUILTIN_INSWH, | |
6459 | ALPHA_BUILTIN_INSLH, | |
6460 | ALPHA_BUILTIN_INSQH, | |
6461 | ALPHA_BUILTIN_MSKBL, | |
6462 | ALPHA_BUILTIN_MSKWL, | |
6463 | ALPHA_BUILTIN_MSKLL, | |
6464 | ALPHA_BUILTIN_MSKQL, | |
6465 | ALPHA_BUILTIN_MSKWH, | |
6466 | ALPHA_BUILTIN_MSKLH, | |
6467 | ALPHA_BUILTIN_MSKQH, | |
6468 | ALPHA_BUILTIN_UMULH, | |
f2cc13dc | 6469 | ALPHA_BUILTIN_ZAP, |
6470 | ALPHA_BUILTIN_ZAPNOT, | |
6471 | ALPHA_BUILTIN_AMASK, | |
6472 | ALPHA_BUILTIN_IMPLVER, | |
6473 | ALPHA_BUILTIN_RPCC, | |
938e069b | 6474 | ALPHA_BUILTIN_THREAD_POINTER, |
6475 | ALPHA_BUILTIN_SET_THREAD_POINTER, | |
50f36bdb | 6476 | ALPHA_BUILTIN_ESTABLISH_VMS_CONDITION_HANDLER, |
6477 | ALPHA_BUILTIN_REVERT_VMS_CONDITION_HANDLER, | |
f2cc13dc | 6478 | |
6479 | /* TARGET_MAX */ | |
6480 | ALPHA_BUILTIN_MINUB8, | |
6481 | ALPHA_BUILTIN_MINSB8, | |
6482 | ALPHA_BUILTIN_MINUW4, | |
6483 | ALPHA_BUILTIN_MINSW4, | |
6484 | ALPHA_BUILTIN_MAXUB8, | |
6485 | ALPHA_BUILTIN_MAXSB8, | |
6486 | ALPHA_BUILTIN_MAXUW4, | |
6487 | ALPHA_BUILTIN_MAXSW4, | |
6488 | ALPHA_BUILTIN_PERR, | |
6489 | ALPHA_BUILTIN_PKLB, | |
6490 | ALPHA_BUILTIN_PKWB, | |
6491 | ALPHA_BUILTIN_UNPKBL, | |
6492 | ALPHA_BUILTIN_UNPKBW, | |
6493 | ||
ae4cd3a5 | 6494 | /* TARGET_CIX */ |
6495 | ALPHA_BUILTIN_CTTZ, | |
6496 | ALPHA_BUILTIN_CTLZ, | |
6497 | ALPHA_BUILTIN_CTPOP, | |
6498 | ||
f2cc13dc | 6499 | ALPHA_BUILTIN_max |
6500 | }; | |
6501 | ||
ff8e23a2 | 6502 | static enum insn_code const code_for_builtin[ALPHA_BUILTIN_max] = { |
ae4cd3a5 | 6503 | CODE_FOR_builtin_cmpbge, |
6504 | CODE_FOR_builtin_extbl, | |
6505 | CODE_FOR_builtin_extwl, | |
6506 | CODE_FOR_builtin_extll, | |
6507 | CODE_FOR_builtin_extql, | |
6508 | CODE_FOR_builtin_extwh, | |
6509 | CODE_FOR_builtin_extlh, | |
6510 | CODE_FOR_builtin_extqh, | |
6511 | CODE_FOR_builtin_insbl, | |
6512 | CODE_FOR_builtin_inswl, | |
6513 | CODE_FOR_builtin_insll, | |
6514 | CODE_FOR_builtin_insql, | |
6515 | CODE_FOR_builtin_inswh, | |
6516 | CODE_FOR_builtin_inslh, | |
6517 | CODE_FOR_builtin_insqh, | |
6518 | CODE_FOR_builtin_mskbl, | |
6519 | CODE_FOR_builtin_mskwl, | |
6520 | CODE_FOR_builtin_mskll, | |
6521 | CODE_FOR_builtin_mskql, | |
6522 | CODE_FOR_builtin_mskwh, | |
6523 | CODE_FOR_builtin_msklh, | |
6524 | CODE_FOR_builtin_mskqh, | |
6525 | CODE_FOR_umuldi3_highpart, | |
6526 | CODE_FOR_builtin_zap, | |
6527 | CODE_FOR_builtin_zapnot, | |
6528 | CODE_FOR_builtin_amask, | |
6529 | CODE_FOR_builtin_implver, | |
6530 | CODE_FOR_builtin_rpcc, | |
938e069b | 6531 | CODE_FOR_load_tp, |
6532 | CODE_FOR_set_tp, | |
50f36bdb | 6533 | CODE_FOR_builtin_establish_vms_condition_handler, |
6534 | CODE_FOR_builtin_revert_vms_condition_handler, | |
ae4cd3a5 | 6535 | |
6536 | /* TARGET_MAX */ | |
6537 | CODE_FOR_builtin_minub8, | |
6538 | CODE_FOR_builtin_minsb8, | |
6539 | CODE_FOR_builtin_minuw4, | |
6540 | CODE_FOR_builtin_minsw4, | |
6541 | CODE_FOR_builtin_maxub8, | |
6542 | CODE_FOR_builtin_maxsb8, | |
6543 | CODE_FOR_builtin_maxuw4, | |
6544 | CODE_FOR_builtin_maxsw4, | |
6545 | CODE_FOR_builtin_perr, | |
6546 | CODE_FOR_builtin_pklb, | |
6547 | CODE_FOR_builtin_pkwb, | |
6548 | CODE_FOR_builtin_unpkbl, | |
6549 | CODE_FOR_builtin_unpkbw, | |
6550 | ||
6551 | /* TARGET_CIX */ | |
849c7bc6 | 6552 | CODE_FOR_ctzdi2, |
6553 | CODE_FOR_clzdi2, | |
6554 | CODE_FOR_popcountdi2 | |
ae4cd3a5 | 6555 | }; |
6556 | ||
f2cc13dc | 6557 | struct alpha_builtin_def |
6558 | { | |
6559 | const char *name; | |
6560 | enum alpha_builtin code; | |
6561 | unsigned int target_mask; | |
849c7bc6 | 6562 | bool is_const; |
f2cc13dc | 6563 | }; |
6564 | ||
6565 | static struct alpha_builtin_def const zero_arg_builtins[] = { | |
849c7bc6 | 6566 | { "__builtin_alpha_implver", ALPHA_BUILTIN_IMPLVER, 0, true }, |
6567 | { "__builtin_alpha_rpcc", ALPHA_BUILTIN_RPCC, 0, false } | |
f2cc13dc | 6568 | }; |
6569 | ||
6570 | static struct alpha_builtin_def const one_arg_builtins[] = { | |
849c7bc6 | 6571 | { "__builtin_alpha_amask", ALPHA_BUILTIN_AMASK, 0, true }, |
6572 | { "__builtin_alpha_pklb", ALPHA_BUILTIN_PKLB, MASK_MAX, true }, | |
6573 | { "__builtin_alpha_pkwb", ALPHA_BUILTIN_PKWB, MASK_MAX, true }, | |
6574 | { "__builtin_alpha_unpkbl", ALPHA_BUILTIN_UNPKBL, MASK_MAX, true }, | |
6575 | { "__builtin_alpha_unpkbw", ALPHA_BUILTIN_UNPKBW, MASK_MAX, true }, | |
6576 | { "__builtin_alpha_cttz", ALPHA_BUILTIN_CTTZ, MASK_CIX, true }, | |
6577 | { "__builtin_alpha_ctlz", ALPHA_BUILTIN_CTLZ, MASK_CIX, true }, | |
6578 | { "__builtin_alpha_ctpop", ALPHA_BUILTIN_CTPOP, MASK_CIX, true } | |
f2cc13dc | 6579 | }; |
6580 | ||
6581 | static struct alpha_builtin_def const two_arg_builtins[] = { | |
849c7bc6 | 6582 | { "__builtin_alpha_cmpbge", ALPHA_BUILTIN_CMPBGE, 0, true }, |
6583 | { "__builtin_alpha_extbl", ALPHA_BUILTIN_EXTBL, 0, true }, | |
6584 | { "__builtin_alpha_extwl", ALPHA_BUILTIN_EXTWL, 0, true }, | |
6585 | { "__builtin_alpha_extll", ALPHA_BUILTIN_EXTLL, 0, true }, | |
6586 | { "__builtin_alpha_extql", ALPHA_BUILTIN_EXTQL, 0, true }, | |
6587 | { "__builtin_alpha_extwh", ALPHA_BUILTIN_EXTWH, 0, true }, | |
6588 | { "__builtin_alpha_extlh", ALPHA_BUILTIN_EXTLH, 0, true }, | |
6589 | { "__builtin_alpha_extqh", ALPHA_BUILTIN_EXTQH, 0, true }, | |
6590 | { "__builtin_alpha_insbl", ALPHA_BUILTIN_INSBL, 0, true }, | |
6591 | { "__builtin_alpha_inswl", ALPHA_BUILTIN_INSWL, 0, true }, | |
6592 | { "__builtin_alpha_insll", ALPHA_BUILTIN_INSLL, 0, true }, | |
6593 | { "__builtin_alpha_insql", ALPHA_BUILTIN_INSQL, 0, true }, | |
6594 | { "__builtin_alpha_inswh", ALPHA_BUILTIN_INSWH, 0, true }, | |
6595 | { "__builtin_alpha_inslh", ALPHA_BUILTIN_INSLH, 0, true }, | |
6596 | { "__builtin_alpha_insqh", ALPHA_BUILTIN_INSQH, 0, true }, | |
6597 | { "__builtin_alpha_mskbl", ALPHA_BUILTIN_MSKBL, 0, true }, | |
6598 | { "__builtin_alpha_mskwl", ALPHA_BUILTIN_MSKWL, 0, true }, | |
6599 | { "__builtin_alpha_mskll", ALPHA_BUILTIN_MSKLL, 0, true }, | |
6600 | { "__builtin_alpha_mskql", ALPHA_BUILTIN_MSKQL, 0, true }, | |
6601 | { "__builtin_alpha_mskwh", ALPHA_BUILTIN_MSKWH, 0, true }, | |
6602 | { "__builtin_alpha_msklh", ALPHA_BUILTIN_MSKLH, 0, true }, | |
6603 | { "__builtin_alpha_mskqh", ALPHA_BUILTIN_MSKQH, 0, true }, | |
6604 | { "__builtin_alpha_umulh", ALPHA_BUILTIN_UMULH, 0, true }, | |
6605 | { "__builtin_alpha_zap", ALPHA_BUILTIN_ZAP, 0, true }, | |
6606 | { "__builtin_alpha_zapnot", ALPHA_BUILTIN_ZAPNOT, 0, true }, | |
6607 | { "__builtin_alpha_minub8", ALPHA_BUILTIN_MINUB8, MASK_MAX, true }, | |
6608 | { "__builtin_alpha_minsb8", ALPHA_BUILTIN_MINSB8, MASK_MAX, true }, | |
6609 | { "__builtin_alpha_minuw4", ALPHA_BUILTIN_MINUW4, MASK_MAX, true }, | |
6610 | { "__builtin_alpha_minsw4", ALPHA_BUILTIN_MINSW4, MASK_MAX, true }, | |
6611 | { "__builtin_alpha_maxub8", ALPHA_BUILTIN_MAXUB8, MASK_MAX, true }, | |
6612 | { "__builtin_alpha_maxsb8", ALPHA_BUILTIN_MAXSB8, MASK_MAX, true }, | |
6613 | { "__builtin_alpha_maxuw4", ALPHA_BUILTIN_MAXUW4, MASK_MAX, true }, | |
6614 | { "__builtin_alpha_maxsw4", ALPHA_BUILTIN_MAXSW4, MASK_MAX, true }, | |
6615 | { "__builtin_alpha_perr", ALPHA_BUILTIN_PERR, MASK_MAX, true } | |
f2cc13dc | 6616 | }; |
6617 | ||
849c7bc6 | 6618 | static GTY(()) tree alpha_v8qi_u; |
6619 | static GTY(()) tree alpha_v8qi_s; | |
6620 | static GTY(()) tree alpha_v4hi_u; | |
6621 | static GTY(()) tree alpha_v4hi_s; | |
6622 | ||
b657e73a | 6623 | /* Helper function of alpha_init_builtins. Add the COUNT built-in |
6624 | functions pointed to by P, with function type FTYPE. */ | |
6625 | ||
6626 | static void | |
6627 | alpha_add_builtins (const struct alpha_builtin_def *p, size_t count, | |
6628 | tree ftype) | |
6629 | { | |
6630 | tree decl; | |
6631 | size_t i; | |
6632 | ||
6633 | for (i = 0; i < count; ++i, ++p) | |
6634 | if ((target_flags & p->target_mask) == p->target_mask) | |
6635 | { | |
6636 | decl = add_builtin_function (p->name, ftype, p->code, BUILT_IN_MD, | |
6637 | NULL, NULL); | |
6638 | if (p->is_const) | |
6639 | TREE_READONLY (decl) = 1; | |
6640 | TREE_NOTHROW (decl) = 1; | |
6641 | } | |
6642 | } | |
6643 | ||
6644 | ||
f2cc13dc | 6645 | static void |
92643d95 | 6646 | alpha_init_builtins (void) |
f2cc13dc | 6647 | { |
e2dc233c | 6648 | tree dimode_integer_type_node; |
b657e73a | 6649 | tree ftype, decl; |
f2cc13dc | 6650 | |
e2dc233c | 6651 | dimode_integer_type_node = lang_hooks.types.type_for_mode (DImode, 0); |
6652 | ||
a5773a09 | 6653 | /* Fwrite on VMS is non-standard. */ |
6654 | #if TARGET_ABI_OPEN_VMS | |
6655 | implicit_built_in_decls[(int) BUILT_IN_FWRITE] = NULL_TREE; | |
6656 | implicit_built_in_decls[(int) BUILT_IN_FWRITE_UNLOCKED] = NULL_TREE; | |
6657 | #endif | |
6658 | ||
e2dc233c | 6659 | ftype = build_function_type (dimode_integer_type_node, void_list_node); |
b657e73a | 6660 | alpha_add_builtins (zero_arg_builtins, ARRAY_SIZE (zero_arg_builtins), |
6661 | ftype); | |
f2cc13dc | 6662 | |
e2dc233c | 6663 | ftype = build_function_type_list (dimode_integer_type_node, |
6664 | dimode_integer_type_node, NULL_TREE); | |
b657e73a | 6665 | alpha_add_builtins (one_arg_builtins, ARRAY_SIZE (one_arg_builtins), |
6666 | ftype); | |
f2cc13dc | 6667 | |
e2dc233c | 6668 | ftype = build_function_type_list (dimode_integer_type_node, |
6669 | dimode_integer_type_node, | |
6670 | dimode_integer_type_node, NULL_TREE); | |
b657e73a | 6671 | alpha_add_builtins (two_arg_builtins, ARRAY_SIZE (two_arg_builtins), |
6672 | ftype); | |
938e069b | 6673 | |
6674 | ftype = build_function_type (ptr_type_node, void_list_node); | |
b657e73a | 6675 | decl = add_builtin_function ("__builtin_thread_pointer", ftype, |
6676 | ALPHA_BUILTIN_THREAD_POINTER, BUILT_IN_MD, | |
6677 | NULL, NULL); | |
6678 | TREE_NOTHROW (decl) = 1; | |
938e069b | 6679 | |
8b55c4ba | 6680 | ftype = build_function_type_list (void_type_node, ptr_type_node, NULL_TREE); |
b657e73a | 6681 | decl = add_builtin_function ("__builtin_set_thread_pointer", ftype, |
6682 | ALPHA_BUILTIN_SET_THREAD_POINTER, BUILT_IN_MD, | |
6683 | NULL, NULL); | |
6684 | TREE_NOTHROW (decl) = 1; | |
849c7bc6 | 6685 | |
50f36bdb | 6686 | if (TARGET_ABI_OPEN_VMS) |
6687 | { | |
6688 | ftype = build_function_type_list (ptr_type_node, ptr_type_node, | |
6689 | NULL_TREE); | |
6690 | add_builtin_function ("__builtin_establish_vms_condition_handler", ftype, | |
6691 | ALPHA_BUILTIN_ESTABLISH_VMS_CONDITION_HANDLER, | |
6692 | BUILT_IN_MD, NULL, NULL_TREE); | |
6693 | ||
6694 | ftype = build_function_type_list (ptr_type_node, void_type_node, | |
6695 | NULL_TREE); | |
6696 | add_builtin_function ("__builtin_revert_vms_condition_handler", ftype, | |
6697 | ALPHA_BUILTIN_REVERT_VMS_CONDITION_HANDLER, | |
6698 | BUILT_IN_MD, NULL, NULL_TREE); | |
6699 | } | |
6700 | ||
849c7bc6 | 6701 | alpha_v8qi_u = build_vector_type (unsigned_intQI_type_node, 8); |
6702 | alpha_v8qi_s = build_vector_type (intQI_type_node, 8); | |
6703 | alpha_v4hi_u = build_vector_type (unsigned_intHI_type_node, 4); | |
6704 | alpha_v4hi_s = build_vector_type (intHI_type_node, 4); | |
f2cc13dc | 6705 | } |
6706 | ||
6707 | /* Expand an expression EXP that calls a built-in function, | |
6708 | with result going to TARGET if that's convenient | |
6709 | (and in mode MODE if that's convenient). | |
6710 | SUBTARGET may be used as the target for computing one of EXP's operands. | |
6711 | IGNORE is nonzero if the value is to be ignored. */ | |
6712 | ||
6713 | static rtx | |
92643d95 | 6714 | alpha_expand_builtin (tree exp, rtx target, |
6715 | rtx subtarget ATTRIBUTE_UNUSED, | |
6716 | enum machine_mode mode ATTRIBUTE_UNUSED, | |
6717 | int ignore ATTRIBUTE_UNUSED) | |
f2cc13dc | 6718 | { |
f2cc13dc | 6719 | #define MAX_ARGS 2 |
6720 | ||
c2f47e15 | 6721 | tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); |
f2cc13dc | 6722 | unsigned int fcode = DECL_FUNCTION_CODE (fndecl); |
c2f47e15 | 6723 | tree arg; |
6724 | call_expr_arg_iterator iter; | |
f2cc13dc | 6725 | enum insn_code icode; |
6726 | rtx op[MAX_ARGS], pat; | |
6727 | int arity; | |
938e069b | 6728 | bool nonvoid; |
f2cc13dc | 6729 | |
6730 | if (fcode >= ALPHA_BUILTIN_max) | |
6731 | internal_error ("bad builtin fcode"); | |
6732 | icode = code_for_builtin[fcode]; | |
6733 | if (icode == 0) | |
6734 | internal_error ("bad builtin fcode"); | |
6735 | ||
938e069b | 6736 | nonvoid = TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node; |
6737 | ||
c2f47e15 | 6738 | arity = 0; |
6739 | FOR_EACH_CALL_EXPR_ARG (arg, iter, exp) | |
f2cc13dc | 6740 | { |
6741 | const struct insn_operand_data *insn_op; | |
6742 | ||
f2cc13dc | 6743 | if (arg == error_mark_node) |
6744 | return NULL_RTX; | |
6745 | if (arity > MAX_ARGS) | |
6746 | return NULL_RTX; | |
6747 | ||
938e069b | 6748 | insn_op = &insn_data[icode].operand[arity + nonvoid]; |
6749 | ||
0a48089c | 6750 | op[arity] = expand_expr (arg, NULL_RTX, insn_op->mode, EXPAND_NORMAL); |
f2cc13dc | 6751 | |
f2cc13dc | 6752 | if (!(*insn_op->predicate) (op[arity], insn_op->mode)) |
6753 | op[arity] = copy_to_mode_reg (insn_op->mode, op[arity]); | |
c2f47e15 | 6754 | arity++; |
f2cc13dc | 6755 | } |
6756 | ||
938e069b | 6757 | if (nonvoid) |
6758 | { | |
6759 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
6760 | if (!target | |
6761 | || GET_MODE (target) != tmode | |
6762 | || !(*insn_data[icode].operand[0].predicate) (target, tmode)) | |
6763 | target = gen_reg_rtx (tmode); | |
6764 | } | |
f2cc13dc | 6765 | |
6766 | switch (arity) | |
6767 | { | |
6768 | case 0: | |
6769 | pat = GEN_FCN (icode) (target); | |
6770 | break; | |
6771 | case 1: | |
938e069b | 6772 | if (nonvoid) |
6773 | pat = GEN_FCN (icode) (target, op[0]); | |
6774 | else | |
6775 | pat = GEN_FCN (icode) (op[0]); | |
f2cc13dc | 6776 | break; |
6777 | case 2: | |
6778 | pat = GEN_FCN (icode) (target, op[0], op[1]); | |
6779 | break; | |
6780 | default: | |
4d10b463 | 6781 | gcc_unreachable (); |
f2cc13dc | 6782 | } |
6783 | if (!pat) | |
6784 | return NULL_RTX; | |
6785 | emit_insn (pat); | |
6786 | ||
938e069b | 6787 | if (nonvoid) |
6788 | return target; | |
6789 | else | |
6790 | return const0_rtx; | |
f2cc13dc | 6791 | } |
849c7bc6 | 6792 | |
6793 | ||
6794 | /* Several bits below assume HWI >= 64 bits. This should be enforced | |
6795 | by config.gcc. */ | |
6796 | #if HOST_BITS_PER_WIDE_INT < 64 | |
6797 | # error "HOST_WIDE_INT too small" | |
6798 | #endif | |
6799 | ||
6800 | /* Fold the builtin for the CMPBGE instruction. This is a vector comparison | |
85c36fd1 | 6801 | with an 8-bit output vector. OPINT contains the integer operands; bit N |
849c7bc6 | 6802 | of OP_CONST is set if OPINT[N] is valid. */ |
6803 | ||
6804 | static tree | |
6805 | alpha_fold_builtin_cmpbge (unsigned HOST_WIDE_INT opint[], long op_const) | |
6806 | { | |
6807 | if (op_const == 3) | |
6808 | { | |
6809 | int i, val; | |
6810 | for (i = 0, val = 0; i < 8; ++i) | |
6811 | { | |
6812 | unsigned HOST_WIDE_INT c0 = (opint[0] >> (i * 8)) & 0xff; | |
6813 | unsigned HOST_WIDE_INT c1 = (opint[1] >> (i * 8)) & 0xff; | |
6814 | if (c0 >= c1) | |
6815 | val |= 1 << i; | |
6816 | } | |
6817 | return build_int_cst (long_integer_type_node, val); | |
6818 | } | |
3def9653 | 6819 | else if (op_const == 2 && opint[1] == 0) |
849c7bc6 | 6820 | return build_int_cst (long_integer_type_node, 0xff); |
6821 | return NULL; | |
6822 | } | |
6823 | ||
6824 | /* Fold the builtin for the ZAPNOT instruction. This is essentially a | |
6825 | specialized form of an AND operation. Other byte manipulation instructions | |
6826 | are defined in terms of this instruction, so this is also used as a | |
6827 | subroutine for other builtins. | |
6828 | ||
6829 | OP contains the tree operands; OPINT contains the extracted integer values. | |
6830 | Bit N of OP_CONST it set if OPINT[N] is valid. OP may be null if only | |
6831 | OPINT may be considered. */ | |
6832 | ||
6833 | static tree | |
6834 | alpha_fold_builtin_zapnot (tree *op, unsigned HOST_WIDE_INT opint[], | |
6835 | long op_const) | |
6836 | { | |
6837 | if (op_const & 2) | |
6838 | { | |
6839 | unsigned HOST_WIDE_INT mask = 0; | |
6840 | int i; | |
6841 | ||
6842 | for (i = 0; i < 8; ++i) | |
6843 | if ((opint[1] >> i) & 1) | |
6844 | mask |= (unsigned HOST_WIDE_INT)0xff << (i * 8); | |
6845 | ||
6846 | if (op_const & 1) | |
6847 | return build_int_cst (long_integer_type_node, opint[0] & mask); | |
6848 | ||
6849 | if (op) | |
b3da1868 | 6850 | return fold_build2 (BIT_AND_EXPR, long_integer_type_node, op[0], |
6851 | build_int_cst (long_integer_type_node, mask)); | |
849c7bc6 | 6852 | } |
6853 | else if ((op_const & 1) && opint[0] == 0) | |
6854 | return build_int_cst (long_integer_type_node, 0); | |
6855 | return NULL; | |
6856 | } | |
6857 | ||
6858 | /* Fold the builtins for the EXT family of instructions. */ | |
6859 | ||
6860 | static tree | |
6861 | alpha_fold_builtin_extxx (tree op[], unsigned HOST_WIDE_INT opint[], | |
6862 | long op_const, unsigned HOST_WIDE_INT bytemask, | |
6863 | bool is_high) | |
6864 | { | |
6865 | long zap_const = 2; | |
6866 | tree *zap_op = NULL; | |
6867 | ||
6868 | if (op_const & 2) | |
6869 | { | |
6870 | unsigned HOST_WIDE_INT loc; | |
6871 | ||
6872 | loc = opint[1] & 7; | |
6873 | if (BYTES_BIG_ENDIAN) | |
6874 | loc ^= 7; | |
6875 | loc *= 8; | |
6876 | ||
6877 | if (loc != 0) | |
6878 | { | |
6879 | if (op_const & 1) | |
6880 | { | |
6881 | unsigned HOST_WIDE_INT temp = opint[0]; | |
6882 | if (is_high) | |
6883 | temp <<= loc; | |
6884 | else | |
6885 | temp >>= loc; | |
6886 | opint[0] = temp; | |
6887 | zap_const = 3; | |
6888 | } | |
6889 | } | |
6890 | else | |
6891 | zap_op = op; | |
6892 | } | |
6893 | ||
6894 | opint[1] = bytemask; | |
6895 | return alpha_fold_builtin_zapnot (zap_op, opint, zap_const); | |
6896 | } | |
6897 | ||
6898 | /* Fold the builtins for the INS family of instructions. */ | |
6899 | ||
6900 | static tree | |
6901 | alpha_fold_builtin_insxx (tree op[], unsigned HOST_WIDE_INT opint[], | |
6902 | long op_const, unsigned HOST_WIDE_INT bytemask, | |
6903 | bool is_high) | |
6904 | { | |
6905 | if ((op_const & 1) && opint[0] == 0) | |
6906 | return build_int_cst (long_integer_type_node, 0); | |
6907 | ||
6908 | if (op_const & 2) | |
6909 | { | |
6910 | unsigned HOST_WIDE_INT temp, loc, byteloc; | |
6911 | tree *zap_op = NULL; | |
6912 | ||
6913 | loc = opint[1] & 7; | |
6914 | if (BYTES_BIG_ENDIAN) | |
6915 | loc ^= 7; | |
6916 | bytemask <<= loc; | |
6917 | ||
6918 | temp = opint[0]; | |
6919 | if (is_high) | |
6920 | { | |
6921 | byteloc = (64 - (loc * 8)) & 0x3f; | |
6922 | if (byteloc == 0) | |
6923 | zap_op = op; | |
6924 | else | |
6925 | temp >>= byteloc; | |
6926 | bytemask >>= 8; | |
6927 | } | |
6928 | else | |
6929 | { | |
6930 | byteloc = loc * 8; | |
6931 | if (byteloc == 0) | |
6932 | zap_op = op; | |
6933 | else | |
6934 | temp <<= byteloc; | |
6935 | } | |
6936 | ||
6937 | opint[0] = temp; | |
6938 | opint[1] = bytemask; | |
6939 | return alpha_fold_builtin_zapnot (zap_op, opint, op_const); | |
6940 | } | |
6941 | ||
6942 | return NULL; | |
6943 | } | |
6944 | ||
6945 | static tree | |
6946 | alpha_fold_builtin_mskxx (tree op[], unsigned HOST_WIDE_INT opint[], | |
6947 | long op_const, unsigned HOST_WIDE_INT bytemask, | |
6948 | bool is_high) | |
6949 | { | |
6950 | if (op_const & 2) | |
6951 | { | |
6952 | unsigned HOST_WIDE_INT loc; | |
6953 | ||
6954 | loc = opint[1] & 7; | |
6955 | if (BYTES_BIG_ENDIAN) | |
6956 | loc ^= 7; | |
6957 | bytemask <<= loc; | |
6958 | ||
6959 | if (is_high) | |
6960 | bytemask >>= 8; | |
6961 | ||
6962 | opint[1] = bytemask ^ 0xff; | |
6963 | } | |
6964 | ||
6965 | return alpha_fold_builtin_zapnot (op, opint, op_const); | |
6966 | } | |
6967 | ||
6968 | static tree | |
6969 | alpha_fold_builtin_umulh (unsigned HOST_WIDE_INT opint[], long op_const) | |
6970 | { | |
6971 | switch (op_const) | |
6972 | { | |
6973 | case 3: | |
6974 | { | |
6975 | unsigned HOST_WIDE_INT l; | |
6976 | HOST_WIDE_INT h; | |
6977 | ||
6978 | mul_double (opint[0], 0, opint[1], 0, &l, &h); | |
6979 | ||
6980 | #if HOST_BITS_PER_WIDE_INT > 64 | |
6981 | # error fixme | |
6982 | #endif | |
6983 | ||
6984 | return build_int_cst (long_integer_type_node, h); | |
6985 | } | |
6986 | ||
6987 | case 1: | |
6988 | opint[1] = opint[0]; | |
6989 | /* FALLTHRU */ | |
6990 | case 2: | |
6991 | /* Note that (X*1) >> 64 == 0. */ | |
6992 | if (opint[1] == 0 || opint[1] == 1) | |
6993 | return build_int_cst (long_integer_type_node, 0); | |
6994 | break; | |
6995 | } | |
6996 | return NULL; | |
6997 | } | |
6998 | ||
6999 | static tree | |
7000 | alpha_fold_vector_minmax (enum tree_code code, tree op[], tree vtype) | |
7001 | { | |
7002 | tree op0 = fold_convert (vtype, op[0]); | |
7003 | tree op1 = fold_convert (vtype, op[1]); | |
b3da1868 | 7004 | tree val = fold_build2 (code, vtype, op0, op1); |
70ce4162 | 7005 | return fold_build1 (VIEW_CONVERT_EXPR, long_integer_type_node, val); |
849c7bc6 | 7006 | } |
7007 | ||
7008 | static tree | |
7009 | alpha_fold_builtin_perr (unsigned HOST_WIDE_INT opint[], long op_const) | |
7010 | { | |
7011 | unsigned HOST_WIDE_INT temp = 0; | |
7012 | int i; | |
7013 | ||
7014 | if (op_const != 3) | |
7015 | return NULL; | |
7016 | ||
7017 | for (i = 0; i < 8; ++i) | |
7018 | { | |
7019 | unsigned HOST_WIDE_INT a = (opint[0] >> (i * 8)) & 0xff; | |
7020 | unsigned HOST_WIDE_INT b = (opint[1] >> (i * 8)) & 0xff; | |
7021 | if (a >= b) | |
7022 | temp += a - b; | |
7023 | else | |
7024 | temp += b - a; | |
7025 | } | |
7026 | ||
7027 | return build_int_cst (long_integer_type_node, temp); | |
7028 | } | |
7029 | ||
7030 | static tree | |
7031 | alpha_fold_builtin_pklb (unsigned HOST_WIDE_INT opint[], long op_const) | |
7032 | { | |
7033 | unsigned HOST_WIDE_INT temp; | |
7034 | ||
7035 | if (op_const == 0) | |
7036 | return NULL; | |
7037 | ||
7038 | temp = opint[0] & 0xff; | |
7039 | temp |= (opint[0] >> 24) & 0xff00; | |
7040 | ||
7041 | return build_int_cst (long_integer_type_node, temp); | |
7042 | } | |
7043 | ||
7044 | static tree | |
7045 | alpha_fold_builtin_pkwb (unsigned HOST_WIDE_INT opint[], long op_const) | |
7046 | { | |
7047 | unsigned HOST_WIDE_INT temp; | |
7048 | ||
7049 | if (op_const == 0) | |
7050 | return NULL; | |
7051 | ||
7052 | temp = opint[0] & 0xff; | |
7053 | temp |= (opint[0] >> 8) & 0xff00; | |
7054 | temp |= (opint[0] >> 16) & 0xff0000; | |
7055 | temp |= (opint[0] >> 24) & 0xff000000; | |
7056 | ||
7057 | return build_int_cst (long_integer_type_node, temp); | |
7058 | } | |
7059 | ||
7060 | static tree | |
7061 | alpha_fold_builtin_unpkbl (unsigned HOST_WIDE_INT opint[], long op_const) | |
7062 | { | |
7063 | unsigned HOST_WIDE_INT temp; | |
7064 | ||
7065 | if (op_const == 0) | |
7066 | return NULL; | |
7067 | ||
7068 | temp = opint[0] & 0xff; | |
7069 | temp |= (opint[0] & 0xff00) << 24; | |
7070 | ||
7071 | return build_int_cst (long_integer_type_node, temp); | |
7072 | } | |
7073 | ||
7074 | static tree | |
7075 | alpha_fold_builtin_unpkbw (unsigned HOST_WIDE_INT opint[], long op_const) | |
7076 | { | |
7077 | unsigned HOST_WIDE_INT temp; | |
7078 | ||
7079 | if (op_const == 0) | |
7080 | return NULL; | |
7081 | ||
7082 | temp = opint[0] & 0xff; | |
7083 | temp |= (opint[0] & 0x0000ff00) << 8; | |
7084 | temp |= (opint[0] & 0x00ff0000) << 16; | |
7085 | temp |= (opint[0] & 0xff000000) << 24; | |
7086 | ||
7087 | return build_int_cst (long_integer_type_node, temp); | |
7088 | } | |
7089 | ||
7090 | static tree | |
7091 | alpha_fold_builtin_cttz (unsigned HOST_WIDE_INT opint[], long op_const) | |
7092 | { | |
7093 | unsigned HOST_WIDE_INT temp; | |
7094 | ||
7095 | if (op_const == 0) | |
7096 | return NULL; | |
7097 | ||
7098 | if (opint[0] == 0) | |
7099 | temp = 64; | |
7100 | else | |
7101 | temp = exact_log2 (opint[0] & -opint[0]); | |
7102 | ||
7103 | return build_int_cst (long_integer_type_node, temp); | |
7104 | } | |
7105 | ||
7106 | static tree | |
7107 | alpha_fold_builtin_ctlz (unsigned HOST_WIDE_INT opint[], long op_const) | |
7108 | { | |
7109 | unsigned HOST_WIDE_INT temp; | |
7110 | ||
7111 | if (op_const == 0) | |
7112 | return NULL; | |
7113 | ||
7114 | if (opint[0] == 0) | |
7115 | temp = 64; | |
7116 | else | |
7117 | temp = 64 - floor_log2 (opint[0]) - 1; | |
7118 | ||
7119 | return build_int_cst (long_integer_type_node, temp); | |
7120 | } | |
7121 | ||
7122 | static tree | |
7123 | alpha_fold_builtin_ctpop (unsigned HOST_WIDE_INT opint[], long op_const) | |
7124 | { | |
7125 | unsigned HOST_WIDE_INT temp, op; | |
7126 | ||
7127 | if (op_const == 0) | |
7128 | return NULL; | |
7129 | ||
7130 | op = opint[0]; | |
7131 | temp = 0; | |
7132 | while (op) | |
7133 | temp++, op &= op - 1; | |
7134 | ||
7135 | return build_int_cst (long_integer_type_node, temp); | |
7136 | } | |
7137 | ||
7138 | /* Fold one of our builtin functions. */ | |
7139 | ||
7140 | static tree | |
432093e5 | 7141 | alpha_fold_builtin (tree fndecl, tree call, bool ignore ATTRIBUTE_UNUSED) |
849c7bc6 | 7142 | { |
432093e5 | 7143 | tree *op = CALL_EXPR_ARGP (call); |
849c7bc6 | 7144 | unsigned HOST_WIDE_INT opint[MAX_ARGS]; |
432093e5 | 7145 | long op_const = 0; |
7146 | int arity; | |
849c7bc6 | 7147 | |
432093e5 | 7148 | for (i = 0; i < call_expr_nargs (call); i++) |
849c7bc6 | 7149 | { |
432093e5 | 7150 | tree arg = CALL_EXPR_ARG (call, i); |
849c7bc6 | 7151 | if (arg == error_mark_node) |
7152 | return NULL; | |
7153 | if (arity >= MAX_ARGS) | |
7154 | return NULL; | |
7155 | ||
849c7bc6 | 7156 | opint[arity] = 0; |
7157 | if (TREE_CODE (arg) == INTEGER_CST) | |
7158 | { | |
7159 | op_const |= 1L << arity; | |
7160 | opint[arity] = int_cst_value (arg); | |
7161 | } | |
7162 | } | |
7163 | ||
7164 | switch (DECL_FUNCTION_CODE (fndecl)) | |
7165 | { | |
7166 | case ALPHA_BUILTIN_CMPBGE: | |
7167 | return alpha_fold_builtin_cmpbge (opint, op_const); | |
7168 | ||
7169 | case ALPHA_BUILTIN_EXTBL: | |
7170 | return alpha_fold_builtin_extxx (op, opint, op_const, 0x01, false); | |
7171 | case ALPHA_BUILTIN_EXTWL: | |
7172 | return alpha_fold_builtin_extxx (op, opint, op_const, 0x03, false); | |
7173 | case ALPHA_BUILTIN_EXTLL: | |
7174 | return alpha_fold_builtin_extxx (op, opint, op_const, 0x0f, false); | |
7175 | case ALPHA_BUILTIN_EXTQL: | |
7176 | return alpha_fold_builtin_extxx (op, opint, op_const, 0xff, false); | |
7177 | case ALPHA_BUILTIN_EXTWH: | |
7178 | return alpha_fold_builtin_extxx (op, opint, op_const, 0x03, true); | |
7179 | case ALPHA_BUILTIN_EXTLH: | |
7180 | return alpha_fold_builtin_extxx (op, opint, op_const, 0x0f, true); | |
7181 | case ALPHA_BUILTIN_EXTQH: | |
7182 | return alpha_fold_builtin_extxx (op, opint, op_const, 0xff, true); | |
7183 | ||
7184 | case ALPHA_BUILTIN_INSBL: | |
7185 | return alpha_fold_builtin_insxx (op, opint, op_const, 0x01, false); | |
7186 | case ALPHA_BUILTIN_INSWL: | |
7187 | return alpha_fold_builtin_insxx (op, opint, op_const, 0x03, false); | |
7188 | case ALPHA_BUILTIN_INSLL: | |
7189 | return alpha_fold_builtin_insxx (op, opint, op_const, 0x0f, false); | |
7190 | case ALPHA_BUILTIN_INSQL: | |
7191 | return alpha_fold_builtin_insxx (op, opint, op_const, 0xff, false); | |
7192 | case ALPHA_BUILTIN_INSWH: | |
7193 | return alpha_fold_builtin_insxx (op, opint, op_const, 0x03, true); | |
7194 | case ALPHA_BUILTIN_INSLH: | |
7195 | return alpha_fold_builtin_insxx (op, opint, op_const, 0x0f, true); | |
7196 | case ALPHA_BUILTIN_INSQH: | |
7197 | return alpha_fold_builtin_insxx (op, opint, op_const, 0xff, true); | |
7198 | ||
7199 | case ALPHA_BUILTIN_MSKBL: | |
7200 | return alpha_fold_builtin_mskxx (op, opint, op_const, 0x01, false); | |
7201 | case ALPHA_BUILTIN_MSKWL: | |
7202 | return alpha_fold_builtin_mskxx (op, opint, op_const, 0x03, false); | |
7203 | case ALPHA_BUILTIN_MSKLL: | |
7204 | return alpha_fold_builtin_mskxx (op, opint, op_const, 0x0f, false); | |
7205 | case ALPHA_BUILTIN_MSKQL: | |
7206 | return alpha_fold_builtin_mskxx (op, opint, op_const, 0xff, false); | |
7207 | case ALPHA_BUILTIN_MSKWH: | |
7208 | return alpha_fold_builtin_mskxx (op, opint, op_const, 0x03, true); | |
7209 | case ALPHA_BUILTIN_MSKLH: | |
7210 | return alpha_fold_builtin_mskxx (op, opint, op_const, 0x0f, true); | |
7211 | case ALPHA_BUILTIN_MSKQH: | |
7212 | return alpha_fold_builtin_mskxx (op, opint, op_const, 0xff, true); | |
7213 | ||
7214 | case ALPHA_BUILTIN_UMULH: | |
7215 | return alpha_fold_builtin_umulh (opint, op_const); | |
7216 | ||
7217 | case ALPHA_BUILTIN_ZAP: | |
7218 | opint[1] ^= 0xff; | |
7219 | /* FALLTHRU */ | |
7220 | case ALPHA_BUILTIN_ZAPNOT: | |
7221 | return alpha_fold_builtin_zapnot (op, opint, op_const); | |
7222 | ||
7223 | case ALPHA_BUILTIN_MINUB8: | |
7224 | return alpha_fold_vector_minmax (MIN_EXPR, op, alpha_v8qi_u); | |
7225 | case ALPHA_BUILTIN_MINSB8: | |
7226 | return alpha_fold_vector_minmax (MIN_EXPR, op, alpha_v8qi_s); | |
7227 | case ALPHA_BUILTIN_MINUW4: | |
7228 | return alpha_fold_vector_minmax (MIN_EXPR, op, alpha_v4hi_u); | |
7229 | case ALPHA_BUILTIN_MINSW4: | |
7230 | return alpha_fold_vector_minmax (MIN_EXPR, op, alpha_v4hi_s); | |
7231 | case ALPHA_BUILTIN_MAXUB8: | |
7232 | return alpha_fold_vector_minmax (MAX_EXPR, op, alpha_v8qi_u); | |
7233 | case ALPHA_BUILTIN_MAXSB8: | |
7234 | return alpha_fold_vector_minmax (MAX_EXPR, op, alpha_v8qi_s); | |
7235 | case ALPHA_BUILTIN_MAXUW4: | |
7236 | return alpha_fold_vector_minmax (MAX_EXPR, op, alpha_v4hi_u); | |
7237 | case ALPHA_BUILTIN_MAXSW4: | |
7238 | return alpha_fold_vector_minmax (MAX_EXPR, op, alpha_v4hi_s); | |
7239 | ||
7240 | case ALPHA_BUILTIN_PERR: | |
7241 | return alpha_fold_builtin_perr (opint, op_const); | |
7242 | case ALPHA_BUILTIN_PKLB: | |
7243 | return alpha_fold_builtin_pklb (opint, op_const); | |
7244 | case ALPHA_BUILTIN_PKWB: | |
7245 | return alpha_fold_builtin_pkwb (opint, op_const); | |
7246 | case ALPHA_BUILTIN_UNPKBL: | |
7247 | return alpha_fold_builtin_unpkbl (opint, op_const); | |
7248 | case ALPHA_BUILTIN_UNPKBW: | |
7249 | return alpha_fold_builtin_unpkbw (opint, op_const); | |
7250 | ||
7251 | case ALPHA_BUILTIN_CTTZ: | |
7252 | return alpha_fold_builtin_cttz (opint, op_const); | |
7253 | case ALPHA_BUILTIN_CTLZ: | |
7254 | return alpha_fold_builtin_ctlz (opint, op_const); | |
7255 | case ALPHA_BUILTIN_CTPOP: | |
7256 | return alpha_fold_builtin_ctpop (opint, op_const); | |
7257 | ||
7258 | case ALPHA_BUILTIN_AMASK: | |
7259 | case ALPHA_BUILTIN_IMPLVER: | |
7260 | case ALPHA_BUILTIN_RPCC: | |
7261 | case ALPHA_BUILTIN_THREAD_POINTER: | |
7262 | case ALPHA_BUILTIN_SET_THREAD_POINTER: | |
7263 | /* None of these are foldable at compile-time. */ | |
7264 | default: | |
7265 | return NULL; | |
7266 | } | |
7267 | } | |
f2cc13dc | 7268 | \f |
bf2a98b3 | 7269 | /* This page contains routines that are used to determine what the function |
7270 | prologue and epilogue code will do and write them out. */ | |
7271 | ||
7272 | /* Compute the size of the save area in the stack. */ | |
7273 | ||
8df4a58b | 7274 | /* These variables are used for communication between the following functions. |
7275 | They indicate various things about the current function being compiled | |
7276 | that are used to tell what kind of prologue, epilogue and procedure | |
efee20da | 7277 | descriptor to generate. */ |
8df4a58b | 7278 | |
7279 | /* Nonzero if we need a stack procedure. */ | |
b19d7ab1 | 7280 | enum alpha_procedure_types {PT_NULL = 0, PT_REGISTER = 1, PT_STACK = 2}; |
7281 | static enum alpha_procedure_types alpha_procedure_type; | |
8df4a58b | 7282 | |
7283 | /* Register number (either FP or SP) that is used to unwind the frame. */ | |
b9a5aa8e | 7284 | static int vms_unwind_regno; |
8df4a58b | 7285 | |
7286 | /* Register number used to save FP. We need not have one for RA since | |
7287 | we don't modify it for register procedures. This is only defined | |
7288 | for register frame procedures. */ | |
b9a5aa8e | 7289 | static int vms_save_fp_regno; |
8df4a58b | 7290 | |
7291 | /* Register number used to reference objects off our PV. */ | |
b9a5aa8e | 7292 | static int vms_base_regno; |
8df4a58b | 7293 | |
2cf1388a | 7294 | /* Compute register masks for saved registers. */ |
8df4a58b | 7295 | |
7296 | static void | |
92643d95 | 7297 | alpha_sa_mask (unsigned long *imaskP, unsigned long *fmaskP) |
8df4a58b | 7298 | { |
7299 | unsigned long imask = 0; | |
7300 | unsigned long fmask = 0; | |
1f0ce6a6 | 7301 | unsigned int i; |
8df4a58b | 7302 | |
eaa112a0 | 7303 | /* When outputting a thunk, we don't have valid register life info, |
7304 | but assemble_start_function wants to output .frame and .mask | |
7305 | directives. */ | |
9247818a | 7306 | if (cfun->is_thunk) |
2cf1388a | 7307 | { |
961d6ddd | 7308 | *imaskP = 0; |
7309 | *fmaskP = 0; | |
7310 | return; | |
7311 | } | |
8df4a58b | 7312 | |
b19d7ab1 | 7313 | if (TARGET_ABI_OPEN_VMS && alpha_procedure_type == PT_STACK) |
df7d0d23 | 7314 | imask |= (1UL << HARD_FRAME_POINTER_REGNUM); |
8df4a58b | 7315 | |
961d6ddd | 7316 | /* One for every register we have to save. */ |
7317 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
7318 | if (! fixed_regs[i] && ! call_used_regs[i] | |
3072d30e | 7319 | && df_regs_ever_live_p (i) && i != REG_RA |
961d6ddd | 7320 | && (!TARGET_ABI_UNICOSMK || i != HARD_FRAME_POINTER_REGNUM)) |
7321 | { | |
7322 | if (i < 32) | |
df7d0d23 | 7323 | imask |= (1UL << i); |
961d6ddd | 7324 | else |
df7d0d23 | 7325 | fmask |= (1UL << (i - 32)); |
961d6ddd | 7326 | } |
7327 | ||
7328 | /* We need to restore these for the handler. */ | |
18d50ae6 | 7329 | if (crtl->calls_eh_return) |
c49ad9ef | 7330 | { |
7331 | for (i = 0; ; ++i) | |
7332 | { | |
7333 | unsigned regno = EH_RETURN_DATA_REGNO (i); | |
7334 | if (regno == INVALID_REGNUM) | |
7335 | break; | |
7336 | imask |= 1UL << regno; | |
7337 | } | |
c49ad9ef | 7338 | } |
9e7454d0 | 7339 | |
961d6ddd | 7340 | /* If any register spilled, then spill the return address also. */ |
7341 | /* ??? This is required by the Digital stack unwind specification | |
7342 | and isn't needed if we're doing Dwarf2 unwinding. */ | |
7343 | if (imask || fmask || alpha_ra_ever_killed ()) | |
df7d0d23 | 7344 | imask |= (1UL << REG_RA); |
b9a5aa8e | 7345 | |
8df4a58b | 7346 | *imaskP = imask; |
7347 | *fmaskP = fmask; | |
8df4a58b | 7348 | } |
7349 | ||
7350 | int | |
92643d95 | 7351 | alpha_sa_size (void) |
8df4a58b | 7352 | { |
5aae9d06 | 7353 | unsigned long mask[2]; |
8df4a58b | 7354 | int sa_size = 0; |
5aae9d06 | 7355 | int i, j; |
8df4a58b | 7356 | |
5aae9d06 | 7357 | alpha_sa_mask (&mask[0], &mask[1]); |
7358 | ||
7359 | if (TARGET_ABI_UNICOSMK) | |
7360 | { | |
7361 | if (mask[0] || mask[1]) | |
7362 | sa_size = 14; | |
7363 | } | |
2cf1388a | 7364 | else |
2cf1388a | 7365 | { |
5aae9d06 | 7366 | for (j = 0; j < 2; ++j) |
7367 | for (i = 0; i < 32; ++i) | |
7368 | if ((mask[j] >> i) & 1) | |
7369 | sa_size++; | |
2cf1388a | 7370 | } |
8df4a58b | 7371 | |
9caef960 | 7372 | if (TARGET_ABI_UNICOSMK) |
7373 | { | |
7374 | /* We might not need to generate a frame if we don't make any calls | |
7375 | (including calls to __T3E_MISMATCH if this is a vararg function), | |
7376 | don't have any local variables which require stack slots, don't | |
7377 | use alloca and have not determined that we need a frame for other | |
7378 | reasons. */ | |
7379 | ||
b19d7ab1 | 7380 | alpha_procedure_type |
7381 | = (sa_size || get_frame_size() != 0 | |
abe32cce | 7382 | || crtl->outgoing_args_size |
18d50ae6 | 7383 | || cfun->stdarg || cfun->calls_alloca |
b19d7ab1 | 7384 | || frame_pointer_needed) |
7385 | ? PT_STACK : PT_REGISTER; | |
9caef960 | 7386 | |
7387 | /* Always reserve space for saving callee-saved registers if we | |
7388 | need a frame as required by the calling convention. */ | |
b19d7ab1 | 7389 | if (alpha_procedure_type == PT_STACK) |
9caef960 | 7390 | sa_size = 14; |
7391 | } | |
7392 | else if (TARGET_ABI_OPEN_VMS) | |
b9a5aa8e | 7393 | { |
d3832055 | 7394 | /* Start with a stack procedure if we make any calls (REG_RA used), or |
7395 | need a frame pointer, with a register procedure if we otherwise need | |
7396 | at least a slot, and with a null procedure in other cases. */ | |
7397 | if ((mask[0] >> REG_RA) & 1 || frame_pointer_needed) | |
b19d7ab1 | 7398 | alpha_procedure_type = PT_STACK; |
7399 | else if (get_frame_size() != 0) | |
7400 | alpha_procedure_type = PT_REGISTER; | |
7401 | else | |
7402 | alpha_procedure_type = PT_NULL; | |
5aae9d06 | 7403 | |
2ab60bb1 | 7404 | /* Don't reserve space for saving FP & RA yet. Do that later after we've |
5aae9d06 | 7405 | made the final decision on stack procedure vs register procedure. */ |
b19d7ab1 | 7406 | if (alpha_procedure_type == PT_STACK) |
2ab60bb1 | 7407 | sa_size -= 2; |
b9a5aa8e | 7408 | |
7409 | /* Decide whether to refer to objects off our PV via FP or PV. | |
7410 | If we need FP for something else or if we receive a nonlocal | |
7411 | goto (which expects PV to contain the value), we must use PV. | |
7412 | Otherwise, start by assuming we can use FP. */ | |
b19d7ab1 | 7413 | |
7414 | vms_base_regno | |
7415 | = (frame_pointer_needed | |
18d50ae6 | 7416 | || cfun->has_nonlocal_label |
b19d7ab1 | 7417 | || alpha_procedure_type == PT_STACK |
abe32cce | 7418 | || crtl->outgoing_args_size) |
b19d7ab1 | 7419 | ? REG_PV : HARD_FRAME_POINTER_REGNUM; |
b9a5aa8e | 7420 | |
7421 | /* If we want to copy PV into FP, we need to find some register | |
7422 | in which to save FP. */ | |
7423 | ||
7424 | vms_save_fp_regno = -1; | |
7425 | if (vms_base_regno == HARD_FRAME_POINTER_REGNUM) | |
7426 | for (i = 0; i < 32; i++) | |
3072d30e | 7427 | if (! fixed_regs[i] && call_used_regs[i] && ! df_regs_ever_live_p (i)) |
b9a5aa8e | 7428 | vms_save_fp_regno = i; |
7429 | ||
50f36bdb | 7430 | /* A VMS condition handler requires a stack procedure in our |
7431 | implementation. (not required by the calling standard). */ | |
7432 | if ((vms_save_fp_regno == -1 && alpha_procedure_type == PT_REGISTER) | |
7433 | || cfun->machine->uses_condition_handler) | |
b19d7ab1 | 7434 | vms_base_regno = REG_PV, alpha_procedure_type = PT_STACK; |
7435 | else if (alpha_procedure_type == PT_NULL) | |
7436 | vms_base_regno = REG_PV; | |
b9a5aa8e | 7437 | |
7438 | /* Stack unwinding should be done via FP unless we use it for PV. */ | |
7439 | vms_unwind_regno = (vms_base_regno == REG_PV | |
7440 | ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM); | |
7441 | ||
50f36bdb | 7442 | /* If this is a stack procedure, allow space for saving FP, RA and |
7443 | a condition handler slot if needed. */ | |
b19d7ab1 | 7444 | if (alpha_procedure_type == PT_STACK) |
50f36bdb | 7445 | sa_size += 2 + cfun->machine->uses_condition_handler; |
b9a5aa8e | 7446 | } |
7447 | else | |
7448 | { | |
b9a5aa8e | 7449 | /* Our size must be even (multiple of 16 bytes). */ |
7450 | if (sa_size & 1) | |
7451 | sa_size++; | |
7452 | } | |
8df4a58b | 7453 | |
7454 | return sa_size * 8; | |
7455 | } | |
7456 | ||
4310aa50 | 7457 | /* Define the offset between two registers, one to be eliminated, |
7458 | and the other its replacement, at the start of a routine. */ | |
7459 | ||
7460 | HOST_WIDE_INT | |
92643d95 | 7461 | alpha_initial_elimination_offset (unsigned int from, |
7462 | unsigned int to ATTRIBUTE_UNUSED) | |
4310aa50 | 7463 | { |
7464 | HOST_WIDE_INT ret; | |
7465 | ||
7466 | ret = alpha_sa_size (); | |
abe32cce | 7467 | ret += ALPHA_ROUND (crtl->outgoing_args_size); |
4310aa50 | 7468 | |
4d10b463 | 7469 | switch (from) |
7470 | { | |
7471 | case FRAME_POINTER_REGNUM: | |
7472 | break; | |
7473 | ||
7474 | case ARG_POINTER_REGNUM: | |
7475 | ret += (ALPHA_ROUND (get_frame_size () | |
abe32cce | 7476 | + crtl->args.pretend_args_size) |
7477 | - crtl->args.pretend_args_size); | |
4d10b463 | 7478 | break; |
7479 | ||
7480 | default: | |
7481 | gcc_unreachable (); | |
7482 | } | |
4310aa50 | 7483 | |
7484 | return ret; | |
7485 | } | |
7486 | ||
d3832055 | 7487 | #if TARGET_ABI_OPEN_VMS |
7488 | ||
cd90919d | 7489 | /* Worker function for TARGET_CAN_ELIMINATE. */ |
7490 | ||
7491 | static bool | |
7492 | alpha_vms_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to) | |
8df4a58b | 7493 | { |
d3832055 | 7494 | /* We need the alpha_procedure_type to decide. Evaluate it now. */ |
8df4a58b | 7495 | alpha_sa_size (); |
d3832055 | 7496 | |
7497 | switch (alpha_procedure_type) | |
7498 | { | |
7499 | case PT_NULL: | |
7500 | /* NULL procedures have no frame of their own and we only | |
7501 | know how to resolve from the current stack pointer. */ | |
7502 | return to == STACK_POINTER_REGNUM; | |
7503 | ||
7504 | case PT_REGISTER: | |
7505 | case PT_STACK: | |
7506 | /* We always eliminate except to the stack pointer if there is no | |
7507 | usable frame pointer at hand. */ | |
7508 | return (to != STACK_POINTER_REGNUM | |
7509 | || vms_unwind_regno != HARD_FRAME_POINTER_REGNUM); | |
7510 | } | |
7511 | ||
7512 | gcc_unreachable (); | |
8df4a58b | 7513 | } |
7514 | ||
d3832055 | 7515 | /* FROM is to be eliminated for TO. Return the offset so that TO+offset |
7516 | designates the same location as FROM. */ | |
7517 | ||
7518 | HOST_WIDE_INT | |
7519 | alpha_vms_initial_elimination_offset (unsigned int from, unsigned int to) | |
7520 | { | |
7521 | /* The only possible attempts we ever expect are ARG or FRAME_PTR to | |
7522 | HARD_FRAME or STACK_PTR. We need the alpha_procedure_type to decide | |
7523 | on the proper computations and will need the register save area size | |
7524 | in most cases. */ | |
7525 | ||
7526 | HOST_WIDE_INT sa_size = alpha_sa_size (); | |
7527 | ||
7528 | /* PT_NULL procedures have no frame of their own and we only allow | |
7529 | elimination to the stack pointer. This is the argument pointer and we | |
7530 | resolve the soft frame pointer to that as well. */ | |
7531 | ||
7532 | if (alpha_procedure_type == PT_NULL) | |
7533 | return 0; | |
7534 | ||
7535 | /* For a PT_STACK procedure the frame layout looks as follows | |
7536 | ||
7537 | -----> decreasing addresses | |
7538 | ||
7539 | < size rounded up to 16 | likewise > | |
7540 | --------------#------------------------------+++--------------+++-------# | |
7541 | incoming args # pretended args | "frame" | regs sa | PV | outgoing args # | |
7542 | --------------#---------------------------------------------------------# | |
7543 | ^ ^ ^ ^ | |
7544 | ARG_PTR FRAME_PTR HARD_FRAME_PTR STACK_PTR | |
7545 | ||
7546 | ||
7547 | PT_REGISTER procedures are similar in that they may have a frame of their | |
7548 | own. They have no regs-sa/pv/outgoing-args area. | |
7549 | ||
7550 | We first compute offset to HARD_FRAME_PTR, then add what we need to get | |
7551 | to STACK_PTR if need be. */ | |
7552 | ||
7553 | { | |
7554 | HOST_WIDE_INT offset; | |
7555 | HOST_WIDE_INT pv_save_size = alpha_procedure_type == PT_STACK ? 8 : 0; | |
7556 | ||
7557 | switch (from) | |
7558 | { | |
7559 | case FRAME_POINTER_REGNUM: | |
7560 | offset = ALPHA_ROUND (sa_size + pv_save_size); | |
7561 | break; | |
7562 | case ARG_POINTER_REGNUM: | |
7563 | offset = (ALPHA_ROUND (sa_size + pv_save_size | |
7564 | + get_frame_size () | |
7565 | + crtl->args.pretend_args_size) | |
7566 | - crtl->args.pretend_args_size); | |
7567 | break; | |
7568 | default: | |
7569 | gcc_unreachable (); | |
7570 | } | |
7571 | ||
7572 | if (to == STACK_POINTER_REGNUM) | |
7573 | offset += ALPHA_ROUND (crtl->outgoing_args_size); | |
7574 | ||
7575 | return offset; | |
7576 | } | |
8df4a58b | 7577 | } |
7578 | ||
00dca3d4 | 7579 | #define COMMON_OBJECT "common_object" |
7580 | ||
7581 | static tree | |
7582 | common_object_handler (tree *node, tree name ATTRIBUTE_UNUSED, | |
7583 | tree args ATTRIBUTE_UNUSED, int flags ATTRIBUTE_UNUSED, | |
7584 | bool *no_add_attrs ATTRIBUTE_UNUSED) | |
7585 | { | |
7586 | tree decl = *node; | |
7587 | gcc_assert (DECL_P (decl)); | |
7588 | ||
7589 | DECL_COMMON (decl) = 1; | |
7590 | return NULL_TREE; | |
7591 | } | |
2d280039 | 7592 | |
cd819d2f | 7593 | static const struct attribute_spec vms_attribute_table[] = |
bf2a98b3 | 7594 | { |
e3c541f0 | 7595 | /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */ |
00dca3d4 | 7596 | { COMMON_OBJECT, 0, 1, true, false, false, common_object_handler }, |
7597 | { NULL, 0, 0, false, false, false, NULL } | |
e3c541f0 | 7598 | }; |
bf2a98b3 | 7599 | |
00dca3d4 | 7600 | void |
7601 | vms_output_aligned_decl_common(FILE *file, tree decl, const char *name, | |
7602 | unsigned HOST_WIDE_INT size, | |
7603 | unsigned int align) | |
7604 | { | |
7605 | tree attr = DECL_ATTRIBUTES (decl); | |
7606 | fprintf (file, "%s", COMMON_ASM_OP); | |
7607 | assemble_name (file, name); | |
7608 | fprintf (file, "," HOST_WIDE_INT_PRINT_UNSIGNED, size); | |
7609 | /* ??? Unlike on OSF/1, the alignment factor is not in log units. */ | |
7610 | fprintf (file, ",%u", align / BITS_PER_UNIT); | |
7611 | if (attr) | |
7612 | { | |
7613 | attr = lookup_attribute (COMMON_OBJECT, attr); | |
7614 | if (attr) | |
7615 | fprintf (file, ",%s", | |
7616 | IDENTIFIER_POINTER (TREE_VALUE (TREE_VALUE (attr)))); | |
7617 | } | |
7618 | fputc ('\n', file); | |
7619 | } | |
7620 | ||
7621 | #undef COMMON_OBJECT | |
7622 | ||
2d280039 | 7623 | #endif |
7624 | ||
1f0ce6a6 | 7625 | static int |
92643d95 | 7626 | find_lo_sum_using_gp (rtx *px, void *data ATTRIBUTE_UNUSED) |
1f0ce6a6 | 7627 | { |
a3859c0f | 7628 | return GET_CODE (*px) == LO_SUM && XEXP (*px, 0) == pic_offset_table_rtx; |
7629 | } | |
7630 | ||
7631 | int | |
92643d95 | 7632 | alpha_find_lo_sum_using_gp (rtx insn) |
a3859c0f | 7633 | { |
7634 | return for_each_rtx (&PATTERN (insn), find_lo_sum_using_gp, NULL) > 0; | |
1f0ce6a6 | 7635 | } |
7636 | ||
b9a5aa8e | 7637 | static int |
92643d95 | 7638 | alpha_does_function_need_gp (void) |
b9a5aa8e | 7639 | { |
7640 | rtx insn; | |
bf2a98b3 | 7641 | |
9caef960 | 7642 | /* The GP being variable is an OSF abi thing. */ |
7643 | if (! TARGET_ABI_OSF) | |
b9a5aa8e | 7644 | return 0; |
bf2a98b3 | 7645 | |
008fdc59 | 7646 | /* We need the gp to load the address of __mcount. */ |
18d50ae6 | 7647 | if (TARGET_PROFILING_NEEDS_GP && crtl->profile) |
b9a5aa8e | 7648 | return 1; |
0e0a0e7a | 7649 | |
008fdc59 | 7650 | /* The code emitted by alpha_output_mi_thunk_osf uses the gp. */ |
9247818a | 7651 | if (cfun->is_thunk) |
2cf1388a | 7652 | return 1; |
2cf1388a | 7653 | |
008fdc59 | 7654 | /* The nonlocal receiver pattern assumes that the gp is valid for |
7655 | the nested function. Reasonable because it's almost always set | |
7656 | correctly already. For the cases where that's wrong, make sure | |
7657 | the nested function loads its gp on entry. */ | |
18d50ae6 | 7658 | if (crtl->has_nonlocal_goto) |
008fdc59 | 7659 | return 1; |
7660 | ||
9e7454d0 | 7661 | /* If we need a GP (we have a LDSYM insn or a CALL_INSN), load it first. |
b9a5aa8e | 7662 | Even if we are a static function, we still need to do this in case |
7663 | our address is taken and passed to something like qsort. */ | |
bf2a98b3 | 7664 | |
b9a5aa8e | 7665 | push_topmost_sequence (); |
7666 | insn = get_insns (); | |
7667 | pop_topmost_sequence (); | |
8df4a58b | 7668 | |
b9a5aa8e | 7669 | for (; insn; insn = NEXT_INSN (insn)) |
30608852 | 7670 | if (NONDEBUG_INSN_P (insn) |
449b6e20 | 7671 | && ! JUMP_TABLE_DATA_P (insn) |
b9a5aa8e | 7672 | && GET_CODE (PATTERN (insn)) != USE |
a3859c0f | 7673 | && GET_CODE (PATTERN (insn)) != CLOBBER |
7674 | && get_attr_usegp (insn)) | |
7675 | return 1; | |
bf2a98b3 | 7676 | |
b9a5aa8e | 7677 | return 0; |
bf2a98b3 | 7678 | } |
7679 | ||
7d73bc2a | 7680 | \f |
5a965225 | 7681 | /* Helper function to set RTX_FRAME_RELATED_P on instructions, including |
7682 | sequences. */ | |
7683 | ||
7684 | static rtx | |
92643d95 | 7685 | set_frame_related_p (void) |
5a965225 | 7686 | { |
31d3e01c | 7687 | rtx seq = get_insns (); |
7688 | rtx insn; | |
7689 | ||
5a965225 | 7690 | end_sequence (); |
7691 | ||
31d3e01c | 7692 | if (!seq) |
7693 | return NULL_RTX; | |
7694 | ||
7695 | if (INSN_P (seq)) | |
5a965225 | 7696 | { |
31d3e01c | 7697 | insn = seq; |
7698 | while (insn != NULL_RTX) | |
7699 | { | |
7700 | RTX_FRAME_RELATED_P (insn) = 1; | |
7701 | insn = NEXT_INSN (insn); | |
7702 | } | |
7703 | seq = emit_insn (seq); | |
5a965225 | 7704 | } |
7705 | else | |
7706 | { | |
7707 | seq = emit_insn (seq); | |
7708 | RTX_FRAME_RELATED_P (seq) = 1; | |
5a965225 | 7709 | } |
31d3e01c | 7710 | return seq; |
5a965225 | 7711 | } |
7712 | ||
7713 | #define FRP(exp) (start_sequence (), exp, set_frame_related_p ()) | |
7714 | ||
fb0de38e | 7715 | /* Generates a store with the proper unwind info attached. VALUE is |
183f1993 | 7716 | stored at BASE_REG+BASE_OFS. If FRAME_BIAS is nonzero, then BASE_REG |
fb0de38e | 7717 | contains SP+FRAME_BIAS, and that is the unwind info that should be |
7718 | generated. If FRAME_REG != VALUE, then VALUE is being stored on | |
7719 | behalf of FRAME_REG, and FRAME_REG should be present in the unwind. */ | |
7720 | ||
7721 | static void | |
7722 | emit_frame_store_1 (rtx value, rtx base_reg, HOST_WIDE_INT frame_bias, | |
7723 | HOST_WIDE_INT base_ofs, rtx frame_reg) | |
7724 | { | |
7725 | rtx addr, mem, insn; | |
7726 | ||
7727 | addr = plus_constant (base_reg, base_ofs); | |
7728 | mem = gen_rtx_MEM (DImode, addr); | |
7729 | set_mem_alias_set (mem, alpha_sr_alias_set); | |
7730 | ||
7731 | insn = emit_move_insn (mem, value); | |
7732 | RTX_FRAME_RELATED_P (insn) = 1; | |
7733 | ||
7734 | if (frame_bias || value != frame_reg) | |
7735 | { | |
7736 | if (frame_bias) | |
7737 | { | |
7738 | addr = plus_constant (stack_pointer_rtx, frame_bias + base_ofs); | |
7739 | mem = gen_rtx_MEM (DImode, addr); | |
7740 | } | |
7741 | ||
0a48089c | 7742 | add_reg_note (insn, REG_FRAME_RELATED_EXPR, |
7743 | gen_rtx_SET (VOIDmode, mem, frame_reg)); | |
fb0de38e | 7744 | } |
7745 | } | |
7746 | ||
7747 | static void | |
7748 | emit_frame_store (unsigned int regno, rtx base_reg, | |
7749 | HOST_WIDE_INT frame_bias, HOST_WIDE_INT base_ofs) | |
7750 | { | |
7751 | rtx reg = gen_rtx_REG (DImode, regno); | |
7752 | emit_frame_store_1 (reg, base_reg, frame_bias, base_ofs, reg); | |
7753 | } | |
7754 | ||
bf2a98b3 | 7755 | /* Write function prologue. */ |
7756 | ||
8df4a58b | 7757 | /* On vms we have two kinds of functions: |
7758 | ||
7759 | - stack frame (PROC_STACK) | |
7760 | these are 'normal' functions with local vars and which are | |
7761 | calling other functions | |
7762 | - register frame (PROC_REGISTER) | |
7763 | keeps all data in registers, needs no stack | |
7764 | ||
7765 | We must pass this to the assembler so it can generate the | |
7766 | proper pdsc (procedure descriptor) | |
7767 | This is done with the '.pdesc' command. | |
7768 | ||
b9a5aa8e | 7769 | On not-vms, we don't really differentiate between the two, as we can |
7770 | simply allocate stack without saving registers. */ | |
8df4a58b | 7771 | |
7772 | void | |
92643d95 | 7773 | alpha_expand_prologue (void) |
8df4a58b | 7774 | { |
b9a5aa8e | 7775 | /* Registers to save. */ |
8df4a58b | 7776 | unsigned long imask = 0; |
7777 | unsigned long fmask = 0; | |
7778 | /* Stack space needed for pushing registers clobbered by us. */ | |
7779 | HOST_WIDE_INT sa_size; | |
7780 | /* Complete stack size needed. */ | |
7781 | HOST_WIDE_INT frame_size; | |
7782 | /* Offset from base reg to register save area. */ | |
b9a5aa8e | 7783 | HOST_WIDE_INT reg_offset; |
fb0de38e | 7784 | rtx sa_reg; |
8df4a58b | 7785 | int i; |
7786 | ||
7787 | sa_size = alpha_sa_size (); | |
8df4a58b | 7788 | |
b9a5aa8e | 7789 | frame_size = get_frame_size (); |
1467e953 | 7790 | if (TARGET_ABI_OPEN_VMS) |
9e7454d0 | 7791 | frame_size = ALPHA_ROUND (sa_size |
b19d7ab1 | 7792 | + (alpha_procedure_type == PT_STACK ? 8 : 0) |
b9a5aa8e | 7793 | + frame_size |
abe32cce | 7794 | + crtl->args.pretend_args_size); |
9caef960 | 7795 | else if (TARGET_ABI_UNICOSMK) |
7796 | /* We have to allocate space for the DSIB if we generate a frame. */ | |
7797 | frame_size = ALPHA_ROUND (sa_size | |
b19d7ab1 | 7798 | + (alpha_procedure_type == PT_STACK ? 48 : 0)) |
9caef960 | 7799 | + ALPHA_ROUND (frame_size |
abe32cce | 7800 | + crtl->outgoing_args_size); |
b9a5aa8e | 7801 | else |
abe32cce | 7802 | frame_size = (ALPHA_ROUND (crtl->outgoing_args_size) |
b9a5aa8e | 7803 | + sa_size |
7804 | + ALPHA_ROUND (frame_size | |
abe32cce | 7805 | + crtl->args.pretend_args_size)); |
8df4a58b | 7806 | |
1467e953 | 7807 | if (TARGET_ABI_OPEN_VMS) |
50f36bdb | 7808 | reg_offset = 8 + 8 * cfun->machine->uses_condition_handler; |
b9a5aa8e | 7809 | else |
abe32cce | 7810 | reg_offset = ALPHA_ROUND (crtl->outgoing_args_size); |
8df4a58b | 7811 | |
b9a5aa8e | 7812 | alpha_sa_mask (&imask, &fmask); |
8df4a58b | 7813 | |
a314eb5e | 7814 | /* Emit an insn to reload GP, if needed. */ |
1467e953 | 7815 | if (TARGET_ABI_OSF) |
a314eb5e | 7816 | { |
7817 | alpha_function_needs_gp = alpha_does_function_need_gp (); | |
7818 | if (alpha_function_needs_gp) | |
7819 | emit_insn (gen_prologue_ldgp ()); | |
7820 | } | |
7821 | ||
30dceb30 | 7822 | /* TARGET_PROFILING_NEEDS_GP actually implies that we need to insert |
7823 | the call to mcount ourselves, rather than having the linker do it | |
7824 | magically in response to -pg. Since _mcount has special linkage, | |
7825 | don't represent the call as a call. */ | |
18d50ae6 | 7826 | if (TARGET_PROFILING_NEEDS_GP && crtl->profile) |
30dceb30 | 7827 | emit_insn (gen_prologue_mcount ()); |
9caef960 | 7828 | |
7829 | if (TARGET_ABI_UNICOSMK) | |
7830 | unicosmk_gen_dsib (&imask); | |
7831 | ||
8df4a58b | 7832 | /* Adjust the stack by the frame size. If the frame size is > 4096 |
7833 | bytes, we need to be sure we probe somewhere in the first and last | |
7834 | 4096 bytes (we can probably get away without the latter test) and | |
7835 | every 8192 bytes in between. If the frame size is > 32768, we | |
7836 | do this in a loop. Otherwise, we generate the explicit probe | |
9e7454d0 | 7837 | instructions. |
8df4a58b | 7838 | |
7839 | Note that we are only allowed to adjust sp once in the prologue. */ | |
7840 | ||
b9a5aa8e | 7841 | if (frame_size <= 32768) |
8df4a58b | 7842 | { |
7843 | if (frame_size > 4096) | |
7844 | { | |
baf8b2cc | 7845 | int probed; |
8df4a58b | 7846 | |
baf8b2cc | 7847 | for (probed = 4096; probed < frame_size; probed += 8192) |
9caef960 | 7848 | emit_insn (gen_probe_stack (GEN_INT (TARGET_ABI_UNICOSMK |
7849 | ? -probed + 64 | |
7850 | : -probed))); | |
8df4a58b | 7851 | |
7852 | /* We only have to do this probe if we aren't saving registers. */ | |
baf8b2cc | 7853 | if (sa_size == 0 && frame_size > probed - 4096) |
b9a5aa8e | 7854 | emit_insn (gen_probe_stack (GEN_INT (-frame_size))); |
8df4a58b | 7855 | } |
7856 | ||
7857 | if (frame_size != 0) | |
205b281f | 7858 | FRP (emit_insn (gen_adddi3 (stack_pointer_rtx, stack_pointer_rtx, |
9caef960 | 7859 | GEN_INT (TARGET_ABI_UNICOSMK |
7860 | ? -frame_size + 64 | |
7861 | : -frame_size)))); | |
8df4a58b | 7862 | } |
7863 | else | |
7864 | { | |
b9a5aa8e | 7865 | /* Here we generate code to set R22 to SP + 4096 and set R23 to the |
8df4a58b | 7866 | number of 8192 byte blocks to probe. We then probe each block |
7867 | in the loop and then set SP to the proper location. If the | |
7868 | amount remaining is > 4096, we have to do one more probe if we | |
7869 | are not saving any registers. */ | |
7870 | ||
7871 | HOST_WIDE_INT blocks = (frame_size + 4096) / 8192; | |
7872 | HOST_WIDE_INT leftover = frame_size + 4096 - blocks * 8192; | |
b9a5aa8e | 7873 | rtx ptr = gen_rtx_REG (DImode, 22); |
7874 | rtx count = gen_rtx_REG (DImode, 23); | |
cd28cb76 | 7875 | rtx seq; |
8df4a58b | 7876 | |
b9a5aa8e | 7877 | emit_move_insn (count, GEN_INT (blocks)); |
9caef960 | 7878 | emit_insn (gen_adddi3 (ptr, stack_pointer_rtx, |
7879 | GEN_INT (TARGET_ABI_UNICOSMK ? 4096 - 64 : 4096))); | |
8df4a58b | 7880 | |
b9a5aa8e | 7881 | /* Because of the difficulty in emitting a new basic block this |
7882 | late in the compilation, generate the loop as a single insn. */ | |
7883 | emit_insn (gen_prologue_stack_probe_loop (count, ptr)); | |
8df4a58b | 7884 | |
7885 | if (leftover > 4096 && sa_size == 0) | |
b9a5aa8e | 7886 | { |
7887 | rtx last = gen_rtx_MEM (DImode, plus_constant (ptr, -leftover)); | |
7888 | MEM_VOLATILE_P (last) = 1; | |
7889 | emit_move_insn (last, const0_rtx); | |
7890 | } | |
8df4a58b | 7891 | |
1467e953 | 7892 | if (TARGET_ABI_WINDOWS_NT) |
f88f2646 | 7893 | { |
7894 | /* For NT stack unwind (done by 'reverse execution'), it's | |
7895 | not OK to take the result of a loop, even though the value | |
7896 | is already in ptr, so we reload it via a single operation | |
9e7454d0 | 7897 | and subtract it to sp. |
cd28cb76 | 7898 | |
7899 | Yes, that's correct -- we have to reload the whole constant | |
df9e12ce | 7900 | into a temporary via ldah+lda then subtract from sp. */ |
f88f2646 | 7901 | |
7902 | HOST_WIDE_INT lo, hi; | |
05bea6dd | 7903 | lo = ((frame_size & 0xffff) ^ 0x8000) - 0x8000; |
7904 | hi = frame_size - lo; | |
5a965225 | 7905 | |
cd28cb76 | 7906 | emit_move_insn (ptr, GEN_INT (hi)); |
df9e12ce | 7907 | emit_insn (gen_adddi3 (ptr, ptr, GEN_INT (lo))); |
cd28cb76 | 7908 | seq = emit_insn (gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx, |
7909 | ptr)); | |
f88f2646 | 7910 | } |
7911 | else | |
7912 | { | |
f88f2646 | 7913 | seq = emit_insn (gen_adddi3 (stack_pointer_rtx, ptr, |
7914 | GEN_INT (-leftover))); | |
f88f2646 | 7915 | } |
cd28cb76 | 7916 | |
7917 | /* This alternative is special, because the DWARF code cannot | |
7918 | possibly intuit through the loop above. So we invent this | |
7919 | note it looks at instead. */ | |
7920 | RTX_FRAME_RELATED_P (seq) = 1; | |
0a48089c | 7921 | add_reg_note (seq, REG_FRAME_RELATED_EXPR, |
7922 | gen_rtx_SET (VOIDmode, stack_pointer_rtx, | |
7923 | gen_rtx_PLUS (Pmode, stack_pointer_rtx, | |
7924 | GEN_INT (TARGET_ABI_UNICOSMK | |
7925 | ? -frame_size + 64 | |
7926 | : -frame_size)))); | |
8df4a58b | 7927 | } |
7928 | ||
9caef960 | 7929 | if (!TARGET_ABI_UNICOSMK) |
8df4a58b | 7930 | { |
fb0de38e | 7931 | HOST_WIDE_INT sa_bias = 0; |
7932 | ||
9caef960 | 7933 | /* Cope with very large offsets to the register save area. */ |
7934 | sa_reg = stack_pointer_rtx; | |
7935 | if (reg_offset + sa_size > 0x8000) | |
7936 | { | |
7937 | int low = ((reg_offset & 0xffff) ^ 0x8000) - 0x8000; | |
fb0de38e | 7938 | rtx sa_bias_rtx; |
8df4a58b | 7939 | |
9caef960 | 7940 | if (low + sa_size <= 0x8000) |
fb0de38e | 7941 | sa_bias = reg_offset - low, reg_offset = low; |
9e7454d0 | 7942 | else |
fb0de38e | 7943 | sa_bias = reg_offset, reg_offset = 0; |
8df4a58b | 7944 | |
9caef960 | 7945 | sa_reg = gen_rtx_REG (DImode, 24); |
fb0de38e | 7946 | sa_bias_rtx = GEN_INT (sa_bias); |
7947 | ||
7948 | if (add_operand (sa_bias_rtx, DImode)) | |
7949 | emit_insn (gen_adddi3 (sa_reg, stack_pointer_rtx, sa_bias_rtx)); | |
7950 | else | |
7951 | { | |
7952 | emit_move_insn (sa_reg, sa_bias_rtx); | |
7953 | emit_insn (gen_adddi3 (sa_reg, stack_pointer_rtx, sa_reg)); | |
7954 | } | |
9caef960 | 7955 | } |
9e7454d0 | 7956 | |
9caef960 | 7957 | /* Save regs in stack order. Beginning with VMS PV. */ |
b19d7ab1 | 7958 | if (TARGET_ABI_OPEN_VMS && alpha_procedure_type == PT_STACK) |
fb0de38e | 7959 | emit_frame_store (REG_PV, stack_pointer_rtx, 0, 0); |
8df4a58b | 7960 | |
9caef960 | 7961 | /* Save register RA next. */ |
df7d0d23 | 7962 | if (imask & (1UL << REG_RA)) |
9caef960 | 7963 | { |
fb0de38e | 7964 | emit_frame_store (REG_RA, sa_reg, sa_bias, reg_offset); |
df7d0d23 | 7965 | imask &= ~(1UL << REG_RA); |
9caef960 | 7966 | reg_offset += 8; |
7967 | } | |
8df4a58b | 7968 | |
9caef960 | 7969 | /* Now save any other registers required to be saved. */ |
c49ad9ef | 7970 | for (i = 0; i < 31; i++) |
df7d0d23 | 7971 | if (imask & (1UL << i)) |
9caef960 | 7972 | { |
fb0de38e | 7973 | emit_frame_store (i, sa_reg, sa_bias, reg_offset); |
9caef960 | 7974 | reg_offset += 8; |
7975 | } | |
8df4a58b | 7976 | |
c49ad9ef | 7977 | for (i = 0; i < 31; i++) |
df7d0d23 | 7978 | if (fmask & (1UL << i)) |
9caef960 | 7979 | { |
fb0de38e | 7980 | emit_frame_store (i+32, sa_reg, sa_bias, reg_offset); |
9caef960 | 7981 | reg_offset += 8; |
7982 | } | |
7983 | } | |
b19d7ab1 | 7984 | else if (TARGET_ABI_UNICOSMK && alpha_procedure_type == PT_STACK) |
9caef960 | 7985 | { |
7986 | /* The standard frame on the T3E includes space for saving registers. | |
7987 | We just have to use it. We don't have to save the return address and | |
7988 | the old frame pointer here - they are saved in the DSIB. */ | |
7989 | ||
7990 | reg_offset = -56; | |
7991 | for (i = 9; i < 15; i++) | |
df7d0d23 | 7992 | if (imask & (1UL << i)) |
9caef960 | 7993 | { |
fb0de38e | 7994 | emit_frame_store (i, hard_frame_pointer_rtx, 0, reg_offset); |
9caef960 | 7995 | reg_offset -= 8; |
7996 | } | |
7997 | for (i = 2; i < 10; i++) | |
df7d0d23 | 7998 | if (fmask & (1UL << i)) |
9caef960 | 7999 | { |
fb0de38e | 8000 | emit_frame_store (i+32, hard_frame_pointer_rtx, 0, reg_offset); |
9caef960 | 8001 | reg_offset -= 8; |
8002 | } | |
8003 | } | |
8df4a58b | 8004 | |
1467e953 | 8005 | if (TARGET_ABI_OPEN_VMS) |
8df4a58b | 8006 | { |
d30e4246 | 8007 | /* Register frame procedures save the fp. */ |
b19d7ab1 | 8008 | if (alpha_procedure_type == PT_REGISTER) |
d30e4246 | 8009 | { |
8010 | rtx insn = emit_move_insn (gen_rtx_REG (DImode, vms_save_fp_regno), | |
8011 | hard_frame_pointer_rtx); | |
8012 | add_reg_note (insn, REG_CFA_REGISTER, NULL); | |
8013 | RTX_FRAME_RELATED_P (insn) = 1; | |
8014 | } | |
8df4a58b | 8015 | |
b19d7ab1 | 8016 | if (alpha_procedure_type != PT_NULL && vms_base_regno != REG_PV) |
6d50e356 | 8017 | emit_insn (gen_force_movdi (gen_rtx_REG (DImode, vms_base_regno), |
8018 | gen_rtx_REG (DImode, REG_PV))); | |
8df4a58b | 8019 | |
b19d7ab1 | 8020 | if (alpha_procedure_type != PT_NULL |
8021 | && vms_unwind_regno == HARD_FRAME_POINTER_REGNUM) | |
205b281f | 8022 | FRP (emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx)); |
8df4a58b | 8023 | |
b9a5aa8e | 8024 | /* If we have to allocate space for outgoing args, do it now. */ |
abe32cce | 8025 | if (crtl->outgoing_args_size != 0) |
81a5b286 | 8026 | { |
8027 | rtx seq | |
9e7454d0 | 8028 | = emit_move_insn (stack_pointer_rtx, |
81a5b286 | 8029 | plus_constant |
8030 | (hard_frame_pointer_rtx, | |
8031 | - (ALPHA_ROUND | |
abe32cce | 8032 | (crtl->outgoing_args_size)))); |
9e7454d0 | 8033 | |
81a5b286 | 8034 | /* Only set FRAME_RELATED_P on the stack adjustment we just emitted |
8035 | if ! frame_pointer_needed. Setting the bit will change the CFA | |
8036 | computation rule to use sp again, which would be wrong if we had | |
8037 | frame_pointer_needed, as this means sp might move unpredictably | |
8038 | later on. | |
8039 | ||
8040 | Also, note that | |
8041 | frame_pointer_needed | |
8042 | => vms_unwind_regno == HARD_FRAME_POINTER_REGNUM | |
8043 | and | |
abe32cce | 8044 | crtl->outgoing_args_size != 0 |
81a5b286 | 8045 | => alpha_procedure_type != PT_NULL, |
8046 | ||
8047 | so when we are not setting the bit here, we are guaranteed to | |
5910bb95 | 8048 | have emitted an FRP frame pointer update just before. */ |
81a5b286 | 8049 | RTX_FRAME_RELATED_P (seq) = ! frame_pointer_needed; |
8050 | } | |
b9a5aa8e | 8051 | } |
9caef960 | 8052 | else if (!TARGET_ABI_UNICOSMK) |
b9a5aa8e | 8053 | { |
8054 | /* If we need a frame pointer, set it from the stack pointer. */ | |
8055 | if (frame_pointer_needed) | |
8056 | { | |
8057 | if (TARGET_CAN_FAULT_IN_PROLOGUE) | |
5a965225 | 8058 | FRP (emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx)); |
8df4a58b | 8059 | else |
205b281f | 8060 | /* This must always be the last instruction in the |
8061 | prologue, thus we emit a special move + clobber. */ | |
5a965225 | 8062 | FRP (emit_insn (gen_init_fp (hard_frame_pointer_rtx, |
8063 | stack_pointer_rtx, sa_reg))); | |
8df4a58b | 8064 | } |
8df4a58b | 8065 | } |
8066 | ||
b9a5aa8e | 8067 | /* The ABIs for VMS and OSF/1 say that while we can schedule insns into |
8068 | the prologue, for exception handling reasons, we cannot do this for | |
8069 | any insn that might fault. We could prevent this for mems with a | |
8070 | (clobber:BLK (scratch)), but this doesn't work for fp insns. So we | |
8071 | have to prevent all such scheduling with a blockage. | |
8df4a58b | 8072 | |
9e7454d0 | 8073 | Linux, on the other hand, never bothered to implement OSF/1's |
b9a5aa8e | 8074 | exception handling, and so doesn't care about such things. Anyone |
8075 | planning to use dwarf2 frame-unwind info can also omit the blockage. */ | |
8df4a58b | 8076 | |
b9a5aa8e | 8077 | if (! TARGET_CAN_FAULT_IN_PROLOGUE) |
8078 | emit_insn (gen_blockage ()); | |
1fce2e8a | 8079 | } |
8080 | ||
e3b8b697 | 8081 | /* Count the number of .file directives, so that .loc is up to date. */ |
d0de818d | 8082 | int num_source_filenames = 0; |
e3b8b697 | 8083 | |
2cf1388a | 8084 | /* Output the textual info surrounding the prologue. */ |
8df4a58b | 8085 | |
b9a5aa8e | 8086 | void |
92643d95 | 8087 | alpha_start_function (FILE *file, const char *fnname, |
8088 | tree decl ATTRIBUTE_UNUSED) | |
0c0464e6 | 8089 | { |
b9a5aa8e | 8090 | unsigned long imask = 0; |
8091 | unsigned long fmask = 0; | |
8092 | /* Stack space needed for pushing registers clobbered by us. */ | |
8093 | HOST_WIDE_INT sa_size; | |
8094 | /* Complete stack size needed. */ | |
f9e9d81d | 8095 | unsigned HOST_WIDE_INT frame_size; |
6dbdfeeb | 8096 | /* The maximum debuggable frame size (512 Kbytes using Tru64 as). */ |
8097 | unsigned HOST_WIDE_INT max_frame_size = TARGET_ABI_OSF && !TARGET_GAS | |
8098 | ? 524288 | |
8099 | : 1UL << 31; | |
b9a5aa8e | 8100 | /* Offset from base reg to register save area. */ |
8101 | HOST_WIDE_INT reg_offset; | |
2cf1388a | 8102 | char *entry_label = (char *) alloca (strlen (fnname) + 6); |
d2f33c43 | 8103 | char *tramp_label = (char *) alloca (strlen (fnname) + 6); |
b9a5aa8e | 8104 | int i; |
0c0464e6 | 8105 | |
9caef960 | 8106 | /* Don't emit an extern directive for functions defined in the same file. */ |
8107 | if (TARGET_ABI_UNICOSMK) | |
8108 | { | |
8109 | tree name_tree; | |
8110 | name_tree = get_identifier (fnname); | |
8111 | TREE_ASM_WRITTEN (name_tree) = 1; | |
8112 | } | |
8113 | ||
1f697db5 | 8114 | #if TARGET_ABI_OPEN_VMS |
8115 | if (vms_debug_main | |
8116 | && strncmp (vms_debug_main, fnname, strlen (vms_debug_main)) == 0) | |
8117 | { | |
8118 | targetm.asm_out.globalize_label (asm_out_file, VMS_DEBUG_MAIN_POINTER); | |
8119 | ASM_OUTPUT_DEF (asm_out_file, VMS_DEBUG_MAIN_POINTER, fnname); | |
8120 | switch_to_section (text_section); | |
8121 | vms_debug_main = NULL; | |
8122 | } | |
8123 | #endif | |
8124 | ||
a314eb5e | 8125 | alpha_fnname = fnname; |
b9a5aa8e | 8126 | sa_size = alpha_sa_size (); |
0c0464e6 | 8127 | |
b9a5aa8e | 8128 | frame_size = get_frame_size (); |
1467e953 | 8129 | if (TARGET_ABI_OPEN_VMS) |
9e7454d0 | 8130 | frame_size = ALPHA_ROUND (sa_size |
b19d7ab1 | 8131 | + (alpha_procedure_type == PT_STACK ? 8 : 0) |
b9a5aa8e | 8132 | + frame_size |
abe32cce | 8133 | + crtl->args.pretend_args_size); |
9caef960 | 8134 | else if (TARGET_ABI_UNICOSMK) |
8135 | frame_size = ALPHA_ROUND (sa_size | |
b19d7ab1 | 8136 | + (alpha_procedure_type == PT_STACK ? 48 : 0)) |
9caef960 | 8137 | + ALPHA_ROUND (frame_size |
abe32cce | 8138 | + crtl->outgoing_args_size); |
b9a5aa8e | 8139 | else |
abe32cce | 8140 | frame_size = (ALPHA_ROUND (crtl->outgoing_args_size) |
b9a5aa8e | 8141 | + sa_size |
8142 | + ALPHA_ROUND (frame_size | |
abe32cce | 8143 | + crtl->args.pretend_args_size)); |
0c0464e6 | 8144 | |
1467e953 | 8145 | if (TARGET_ABI_OPEN_VMS) |
50f36bdb | 8146 | reg_offset = 8 + 8 * cfun->machine->uses_condition_handler; |
b9a5aa8e | 8147 | else |
abe32cce | 8148 | reg_offset = ALPHA_ROUND (crtl->outgoing_args_size); |
0c0464e6 | 8149 | |
b9a5aa8e | 8150 | alpha_sa_mask (&imask, &fmask); |
bf2a98b3 | 8151 | |
0e0a0e7a | 8152 | /* Ecoff can handle multiple .file directives, so put out file and lineno. |
449b7f2d | 8153 | We have to do that before the .ent directive as we cannot switch |
8154 | files within procedures with native ecoff because line numbers are | |
8155 | linked to procedure descriptors. | |
8156 | Outputting the lineno helps debugging of one line functions as they | |
8157 | would otherwise get no line number at all. Please note that we would | |
01cc3b75 | 8158 | like to put out last_linenum from final.c, but it is not accessible. */ |
449b7f2d | 8159 | |
8160 | if (write_symbols == SDB_DEBUG) | |
8161 | { | |
9caef960 | 8162 | #ifdef ASM_OUTPUT_SOURCE_FILENAME |
346064d9 | 8163 | ASM_OUTPUT_SOURCE_FILENAME (file, |
8164 | DECL_SOURCE_FILE (current_function_decl)); | |
9caef960 | 8165 | #endif |
e3b8b697 | 8166 | #ifdef SDB_OUTPUT_SOURCE_LINE |
449b7f2d | 8167 | if (debug_info_level != DINFO_LEVEL_TERSE) |
e3b8b697 | 8168 | SDB_OUTPUT_SOURCE_LINE (file, |
8169 | DECL_SOURCE_LINE (current_function_decl)); | |
9caef960 | 8170 | #endif |
449b7f2d | 8171 | } |
8172 | ||
b9a5aa8e | 8173 | /* Issue function start and label. */ |
9caef960 | 8174 | if (TARGET_ABI_OPEN_VMS |
8175 | || (!TARGET_ABI_UNICOSMK && !flag_inhibit_size_directive)) | |
f1fe649e | 8176 | { |
b9a5aa8e | 8177 | fputs ("\t.ent ", file); |
2cf1388a | 8178 | assemble_name (file, fnname); |
b9a5aa8e | 8179 | putc ('\n', file); |
a314eb5e | 8180 | |
8181 | /* If the function needs GP, we'll write the "..ng" label there. | |
8182 | Otherwise, do it here. */ | |
961d6ddd | 8183 | if (TARGET_ABI_OSF |
8184 | && ! alpha_function_needs_gp | |
9247818a | 8185 | && ! cfun->is_thunk) |
a314eb5e | 8186 | { |
8187 | putc ('$', file); | |
8188 | assemble_name (file, fnname); | |
8189 | fputs ("..ng:\n", file); | |
8190 | } | |
f1fe649e | 8191 | } |
d2f33c43 | 8192 | /* Nested functions on VMS that are potentially called via trampoline |
8193 | get a special transfer entry point that loads the called functions | |
8194 | procedure descriptor and static chain. */ | |
8195 | if (TARGET_ABI_OPEN_VMS | |
8196 | && !TREE_PUBLIC (decl) | |
8197 | && DECL_CONTEXT (decl) | |
8198 | && !TYPE_P (DECL_CONTEXT (decl))) | |
8199 | { | |
8200 | strcpy (tramp_label, fnname); | |
8201 | strcat (tramp_label, "..tr"); | |
8202 | ASM_OUTPUT_LABEL (file, tramp_label); | |
8203 | fprintf (file, "\tldq $1,24($27)\n"); | |
8204 | fprintf (file, "\tldq $27,16($27)\n"); | |
8205 | } | |
449b7f2d | 8206 | |
2cf1388a | 8207 | strcpy (entry_label, fnname); |
1467e953 | 8208 | if (TARGET_ABI_OPEN_VMS) |
b9a5aa8e | 8209 | strcat (entry_label, "..en"); |
9caef960 | 8210 | |
8211 | /* For public functions, the label must be globalized by appending an | |
8212 | additional colon. */ | |
8213 | if (TARGET_ABI_UNICOSMK && TREE_PUBLIC (decl)) | |
8214 | strcat (entry_label, ":"); | |
8215 | ||
b9a5aa8e | 8216 | ASM_OUTPUT_LABEL (file, entry_label); |
8217 | inside_function = TRUE; | |
449b7f2d | 8218 | |
1467e953 | 8219 | if (TARGET_ABI_OPEN_VMS) |
b9a5aa8e | 8220 | fprintf (file, "\t.base $%d\n", vms_base_regno); |
bf2a98b3 | 8221 | |
9caef960 | 8222 | if (!TARGET_ABI_OPEN_VMS && !TARGET_ABI_UNICOSMK && TARGET_IEEE_CONFORMANT |
b9a5aa8e | 8223 | && !flag_inhibit_size_directive) |
9c0e5703 | 8224 | { |
b9a5aa8e | 8225 | /* Set flags in procedure descriptor to request IEEE-conformant |
8226 | math-library routines. The value we set it to is PDSC_EXC_IEEE | |
65abff06 | 8227 | (/usr/include/pdsc.h). */ |
b9a5aa8e | 8228 | fputs ("\t.eflag 48\n", file); |
9c0e5703 | 8229 | } |
bf2a98b3 | 8230 | |
b9a5aa8e | 8231 | /* Set up offsets to alpha virtual arg/local debugging pointer. */ |
abe32cce | 8232 | alpha_auto_offset = -frame_size + crtl->args.pretend_args_size; |
b9a5aa8e | 8233 | alpha_arg_offset = -frame_size + 48; |
cb015df5 | 8234 | |
b9a5aa8e | 8235 | /* Describe our frame. If the frame size is larger than an integer, |
8236 | print it as zero to avoid an assembler error. We won't be | |
8237 | properly describing such a frame, but that's the best we can do. */ | |
9caef960 | 8238 | if (TARGET_ABI_UNICOSMK) |
8239 | ; | |
8240 | else if (TARGET_ABI_OPEN_VMS) | |
4840a03a | 8241 | fprintf (file, "\t.frame $%d," HOST_WIDE_INT_PRINT_DEC ",$26," |
8242 | HOST_WIDE_INT_PRINT_DEC "\n", | |
8243 | vms_unwind_regno, | |
8244 | frame_size >= (1UL << 31) ? 0 : frame_size, | |
8245 | reg_offset); | |
b9a5aa8e | 8246 | else if (!flag_inhibit_size_directive) |
4840a03a | 8247 | fprintf (file, "\t.frame $%d," HOST_WIDE_INT_PRINT_DEC ",$26,%d\n", |
8248 | (frame_pointer_needed | |
8249 | ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM), | |
6dbdfeeb | 8250 | frame_size >= max_frame_size ? 0 : frame_size, |
abe32cce | 8251 | crtl->args.pretend_args_size); |
15d5236f | 8252 | |
b9a5aa8e | 8253 | /* Describe which registers were spilled. */ |
9caef960 | 8254 | if (TARGET_ABI_UNICOSMK) |
8255 | ; | |
8256 | else if (TARGET_ABI_OPEN_VMS) | |
15d5236f | 8257 | { |
b9a5aa8e | 8258 | if (imask) |
9caef960 | 8259 | /* ??? Does VMS care if mask contains ra? The old code didn't |
b9a5aa8e | 8260 | set it, so I don't here. */ |
df7d0d23 | 8261 | fprintf (file, "\t.mask 0x%lx,0\n", imask & ~(1UL << REG_RA)); |
b9a5aa8e | 8262 | if (fmask) |
769ea120 | 8263 | fprintf (file, "\t.fmask 0x%lx,0\n", fmask); |
b19d7ab1 | 8264 | if (alpha_procedure_type == PT_REGISTER) |
b9a5aa8e | 8265 | fprintf (file, "\t.fp_save $%d\n", vms_save_fp_regno); |
8266 | } | |
8267 | else if (!flag_inhibit_size_directive) | |
8268 | { | |
8269 | if (imask) | |
15d5236f | 8270 | { |
4840a03a | 8271 | fprintf (file, "\t.mask 0x%lx," HOST_WIDE_INT_PRINT_DEC "\n", imask, |
6dbdfeeb | 8272 | frame_size >= max_frame_size ? 0 : reg_offset - frame_size); |
b9a5aa8e | 8273 | |
8274 | for (i = 0; i < 32; ++i) | |
df7d0d23 | 8275 | if (imask & (1UL << i)) |
b9a5aa8e | 8276 | reg_offset += 8; |
15d5236f | 8277 | } |
b9a5aa8e | 8278 | |
8279 | if (fmask) | |
4840a03a | 8280 | fprintf (file, "\t.fmask 0x%lx," HOST_WIDE_INT_PRINT_DEC "\n", fmask, |
6dbdfeeb | 8281 | frame_size >= max_frame_size ? 0 : reg_offset - frame_size); |
bf2a98b3 | 8282 | } |
8283 | ||
1467e953 | 8284 | #if TARGET_ABI_OPEN_VMS |
50f36bdb | 8285 | /* If a user condition handler has been installed at some point, emit |
8286 | the procedure descriptor bits to point the Condition Handling Facility | |
8287 | at the indirection wrapper, and state the fp offset at which the user | |
8288 | handler may be found. */ | |
8289 | if (cfun->machine->uses_condition_handler) | |
8290 | { | |
8291 | fprintf (file, "\t.handler __gcc_shell_handler\n"); | |
8292 | fprintf (file, "\t.handler_data %d\n", VMS_COND_HANDLER_FP_OFFSET); | |
8293 | } | |
8294 | ||
6cde52a2 | 8295 | /* Ifdef'ed cause link_section are only available then. */ |
2f14b1f9 | 8296 | switch_to_section (readonly_data_section); |
b9a5aa8e | 8297 | fprintf (file, "\t.align 3\n"); |
2cf1388a | 8298 | assemble_name (file, fnname); fputs ("..na:\n", file); |
b9a5aa8e | 8299 | fputs ("\t.ascii \"", file); |
2cf1388a | 8300 | assemble_name (file, fnname); |
b9a5aa8e | 8301 | fputs ("\\0\"\n", file); |
2cf1388a | 8302 | alpha_need_linkage (fnname, 1); |
2f14b1f9 | 8303 | switch_to_section (text_section); |
b9a5aa8e | 8304 | #endif |
8305 | } | |
bf2a98b3 | 8306 | |
b9a5aa8e | 8307 | /* Emit the .prologue note at the scheduled end of the prologue. */ |
16b3392b | 8308 | |
85ae73e8 | 8309 | static void |
92643d95 | 8310 | alpha_output_function_end_prologue (FILE *file) |
b9a5aa8e | 8311 | { |
9caef960 | 8312 | if (TARGET_ABI_UNICOSMK) |
8313 | ; | |
8314 | else if (TARGET_ABI_OPEN_VMS) | |
b9a5aa8e | 8315 | fputs ("\t.prologue\n", file); |
1467e953 | 8316 | else if (TARGET_ABI_WINDOWS_NT) |
b9a5aa8e | 8317 | fputs ("\t.prologue 0\n", file); |
8318 | else if (!flag_inhibit_size_directive) | |
961d6ddd | 8319 | fprintf (file, "\t.prologue %d\n", |
9247818a | 8320 | alpha_function_needs_gp || cfun->is_thunk); |
bf2a98b3 | 8321 | } |
8322 | ||
8323 | /* Write function epilogue. */ | |
8324 | ||
8325 | void | |
92643d95 | 8326 | alpha_expand_epilogue (void) |
bf2a98b3 | 8327 | { |
b9a5aa8e | 8328 | /* Registers to save. */ |
8329 | unsigned long imask = 0; | |
8330 | unsigned long fmask = 0; | |
8331 | /* Stack space needed for pushing registers clobbered by us. */ | |
8332 | HOST_WIDE_INT sa_size; | |
8333 | /* Complete stack size needed. */ | |
8334 | HOST_WIDE_INT frame_size; | |
8335 | /* Offset from base reg to register save area. */ | |
8336 | HOST_WIDE_INT reg_offset; | |
8337 | int fp_is_frame_pointer, fp_offset; | |
8338 | rtx sa_reg, sa_reg_exp = NULL; | |
d30e4246 | 8339 | rtx sp_adj1, sp_adj2, mem, reg, insn; |
11016d99 | 8340 | rtx eh_ofs; |
d30e4246 | 8341 | rtx cfa_restores = NULL_RTX; |
bf2a98b3 | 8342 | int i; |
8343 | ||
b9a5aa8e | 8344 | sa_size = alpha_sa_size (); |
bf2a98b3 | 8345 | |
b9a5aa8e | 8346 | frame_size = get_frame_size (); |
1467e953 | 8347 | if (TARGET_ABI_OPEN_VMS) |
9e7454d0 | 8348 | frame_size = ALPHA_ROUND (sa_size |
b19d7ab1 | 8349 | + (alpha_procedure_type == PT_STACK ? 8 : 0) |
b9a5aa8e | 8350 | + frame_size |
abe32cce | 8351 | + crtl->args.pretend_args_size); |
9caef960 | 8352 | else if (TARGET_ABI_UNICOSMK) |
8353 | frame_size = ALPHA_ROUND (sa_size | |
b19d7ab1 | 8354 | + (alpha_procedure_type == PT_STACK ? 48 : 0)) |
9caef960 | 8355 | + ALPHA_ROUND (frame_size |
abe32cce | 8356 | + crtl->outgoing_args_size); |
b9a5aa8e | 8357 | else |
abe32cce | 8358 | frame_size = (ALPHA_ROUND (crtl->outgoing_args_size) |
b9a5aa8e | 8359 | + sa_size |
8360 | + ALPHA_ROUND (frame_size | |
abe32cce | 8361 | + crtl->args.pretend_args_size)); |
bf2a98b3 | 8362 | |
1467e953 | 8363 | if (TARGET_ABI_OPEN_VMS) |
b19d7ab1 | 8364 | { |
8365 | if (alpha_procedure_type == PT_STACK) | |
50f36bdb | 8366 | reg_offset = 8 + 8 * cfun->machine->uses_condition_handler; |
b19d7ab1 | 8367 | else |
8368 | reg_offset = 0; | |
8369 | } | |
b9a5aa8e | 8370 | else |
abe32cce | 8371 | reg_offset = ALPHA_ROUND (crtl->outgoing_args_size); |
b9a5aa8e | 8372 | |
8373 | alpha_sa_mask (&imask, &fmask); | |
8374 | ||
b19d7ab1 | 8375 | fp_is_frame_pointer |
8376 | = ((TARGET_ABI_OPEN_VMS && alpha_procedure_type == PT_STACK) | |
8377 | || (!TARGET_ABI_OPEN_VMS && frame_pointer_needed)); | |
29768226 | 8378 | fp_offset = 0; |
8379 | sa_reg = stack_pointer_rtx; | |
b9a5aa8e | 8380 | |
18d50ae6 | 8381 | if (crtl->calls_eh_return) |
c92c328f | 8382 | eh_ofs = EH_RETURN_STACKADJ_RTX; |
8383 | else | |
8384 | eh_ofs = NULL_RTX; | |
8385 | ||
9caef960 | 8386 | if (!TARGET_ABI_UNICOSMK && sa_size) |
b9a5aa8e | 8387 | { |
8388 | /* If we have a frame pointer, restore SP from it. */ | |
1467e953 | 8389 | if ((TARGET_ABI_OPEN_VMS |
b9a5aa8e | 8390 | && vms_unwind_regno == HARD_FRAME_POINTER_REGNUM) |
1467e953 | 8391 | || (!TARGET_ABI_OPEN_VMS && frame_pointer_needed)) |
d30e4246 | 8392 | emit_move_insn (stack_pointer_rtx, hard_frame_pointer_rtx); |
15d5236f | 8393 | |
b9a5aa8e | 8394 | /* Cope with very large offsets to the register save area. */ |
b9a5aa8e | 8395 | if (reg_offset + sa_size > 0x8000) |
bf2a98b3 | 8396 | { |
b9a5aa8e | 8397 | int low = ((reg_offset & 0xffff) ^ 0x8000) - 0x8000; |
8398 | HOST_WIDE_INT bias; | |
8399 | ||
8400 | if (low + sa_size <= 0x8000) | |
8401 | bias = reg_offset - low, reg_offset = low; | |
9e7454d0 | 8402 | else |
b9a5aa8e | 8403 | bias = reg_offset, reg_offset = 0; |
8404 | ||
8405 | sa_reg = gen_rtx_REG (DImode, 22); | |
8406 | sa_reg_exp = plus_constant (stack_pointer_rtx, bias); | |
8407 | ||
d30e4246 | 8408 | emit_move_insn (sa_reg, sa_reg_exp); |
bf2a98b3 | 8409 | } |
9e7454d0 | 8410 | |
65abff06 | 8411 | /* Restore registers in order, excepting a true frame pointer. */ |
bf2a98b3 | 8412 | |
c92c328f | 8413 | mem = gen_rtx_MEM (DImode, plus_constant (sa_reg, reg_offset)); |
11016d99 | 8414 | if (! eh_ofs) |
ab6ab77e | 8415 | set_mem_alias_set (mem, alpha_sr_alias_set); |
d30e4246 | 8416 | reg = gen_rtx_REG (DImode, REG_RA); |
8417 | emit_move_insn (reg, mem); | |
8418 | cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores); | |
c92c328f | 8419 | |
b9a5aa8e | 8420 | reg_offset += 8; |
df7d0d23 | 8421 | imask &= ~(1UL << REG_RA); |
16b3392b | 8422 | |
c49ad9ef | 8423 | for (i = 0; i < 31; ++i) |
df7d0d23 | 8424 | if (imask & (1UL << i)) |
bf2a98b3 | 8425 | { |
b9a5aa8e | 8426 | if (i == HARD_FRAME_POINTER_REGNUM && fp_is_frame_pointer) |
16b3392b | 8427 | fp_offset = reg_offset; |
8428 | else | |
b9a5aa8e | 8429 | { |
849674a3 | 8430 | mem = gen_rtx_MEM (DImode, plus_constant(sa_reg, reg_offset)); |
ab6ab77e | 8431 | set_mem_alias_set (mem, alpha_sr_alias_set); |
d30e4246 | 8432 | reg = gen_rtx_REG (DImode, i); |
8433 | emit_move_insn (reg, mem); | |
8434 | cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, | |
8435 | cfa_restores); | |
b9a5aa8e | 8436 | } |
bf2a98b3 | 8437 | reg_offset += 8; |
8438 | } | |
8439 | ||
c49ad9ef | 8440 | for (i = 0; i < 31; ++i) |
df7d0d23 | 8441 | if (fmask & (1UL << i)) |
bf2a98b3 | 8442 | { |
849674a3 | 8443 | mem = gen_rtx_MEM (DFmode, plus_constant(sa_reg, reg_offset)); |
ab6ab77e | 8444 | set_mem_alias_set (mem, alpha_sr_alias_set); |
d30e4246 | 8445 | reg = gen_rtx_REG (DFmode, i+32); |
8446 | emit_move_insn (reg, mem); | |
8447 | cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores); | |
bf2a98b3 | 8448 | reg_offset += 8; |
8449 | } | |
b9a5aa8e | 8450 | } |
b19d7ab1 | 8451 | else if (TARGET_ABI_UNICOSMK && alpha_procedure_type == PT_STACK) |
9caef960 | 8452 | { |
8453 | /* Restore callee-saved general-purpose registers. */ | |
8454 | ||
8455 | reg_offset = -56; | |
8456 | ||
8457 | for (i = 9; i < 15; i++) | |
df7d0d23 | 8458 | if (imask & (1UL << i)) |
9caef960 | 8459 | { |
8460 | mem = gen_rtx_MEM (DImode, plus_constant(hard_frame_pointer_rtx, | |
8461 | reg_offset)); | |
8462 | set_mem_alias_set (mem, alpha_sr_alias_set); | |
d30e4246 | 8463 | reg = gen_rtx_REG (DImode, i); |
8464 | emit_move_insn (reg, mem); | |
8465 | cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores); | |
9caef960 | 8466 | reg_offset -= 8; |
8467 | } | |
8468 | ||
8469 | for (i = 2; i < 10; i++) | |
df7d0d23 | 8470 | if (fmask & (1UL << i)) |
9caef960 | 8471 | { |
8472 | mem = gen_rtx_MEM (DFmode, plus_constant(hard_frame_pointer_rtx, | |
8473 | reg_offset)); | |
8474 | set_mem_alias_set (mem, alpha_sr_alias_set); | |
d30e4246 | 8475 | reg = gen_rtx_REG (DFmode, i+32); |
8476 | emit_move_insn (reg, mem); | |
8477 | cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores); | |
9caef960 | 8478 | reg_offset -= 8; |
8479 | } | |
8480 | ||
8481 | /* Restore the return address from the DSIB. */ | |
d30e4246 | 8482 | mem = gen_rtx_MEM (DImode, plus_constant (hard_frame_pointer_rtx, -8)); |
9caef960 | 8483 | set_mem_alias_set (mem, alpha_sr_alias_set); |
d30e4246 | 8484 | reg = gen_rtx_REG (DImode, REG_RA); |
8485 | emit_move_insn (reg, mem); | |
8486 | cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores); | |
9caef960 | 8487 | } |
bf2a98b3 | 8488 | |
11016d99 | 8489 | if (frame_size || eh_ofs) |
b9a5aa8e | 8490 | { |
ec37ccb4 | 8491 | sp_adj1 = stack_pointer_rtx; |
8492 | ||
11016d99 | 8493 | if (eh_ofs) |
ec37ccb4 | 8494 | { |
8495 | sp_adj1 = gen_rtx_REG (DImode, 23); | |
8496 | emit_move_insn (sp_adj1, | |
11016d99 | 8497 | gen_rtx_PLUS (Pmode, stack_pointer_rtx, eh_ofs)); |
ec37ccb4 | 8498 | } |
8499 | ||
b9a5aa8e | 8500 | /* If the stack size is large, begin computation into a temporary |
8501 | register so as not to interfere with a potential fp restore, | |
8502 | which must be consecutive with an SP restore. */ | |
9caef960 | 8503 | if (frame_size < 32768 |
18d50ae6 | 8504 | && ! (TARGET_ABI_UNICOSMK && cfun->calls_alloca)) |
ec37ccb4 | 8505 | sp_adj2 = GEN_INT (frame_size); |
9caef960 | 8506 | else if (TARGET_ABI_UNICOSMK) |
8507 | { | |
8508 | sp_adj1 = gen_rtx_REG (DImode, 23); | |
d30e4246 | 8509 | emit_move_insn (sp_adj1, hard_frame_pointer_rtx); |
9caef960 | 8510 | sp_adj2 = const0_rtx; |
8511 | } | |
b9a5aa8e | 8512 | else if (frame_size < 0x40007fffL) |
8513 | { | |
8514 | int low = ((frame_size & 0xffff) ^ 0x8000) - 0x8000; | |
8515 | ||
ec37ccb4 | 8516 | sp_adj2 = plus_constant (sp_adj1, frame_size - low); |
b9a5aa8e | 8517 | if (sa_reg_exp && rtx_equal_p (sa_reg_exp, sp_adj2)) |
8518 | sp_adj1 = sa_reg; | |
8519 | else | |
8520 | { | |
8521 | sp_adj1 = gen_rtx_REG (DImode, 23); | |
d30e4246 | 8522 | emit_move_insn (sp_adj1, sp_adj2); |
b9a5aa8e | 8523 | } |
8524 | sp_adj2 = GEN_INT (low); | |
8525 | } | |
0e0a0e7a | 8526 | else |
b9a5aa8e | 8527 | { |
ec37ccb4 | 8528 | rtx tmp = gen_rtx_REG (DImode, 23); |
d30e4246 | 8529 | sp_adj2 = alpha_emit_set_const (tmp, DImode, frame_size, 3, false); |
ec37ccb4 | 8530 | if (!sp_adj2) |
b9a5aa8e | 8531 | { |
8532 | /* We can't drop new things to memory this late, afaik, | |
8533 | so build it up by pieces. */ | |
d30e4246 | 8534 | sp_adj2 = alpha_emit_set_long_const (tmp, frame_size, |
8535 | -(frame_size < 0)); | |
4d10b463 | 8536 | gcc_assert (sp_adj2); |
b9a5aa8e | 8537 | } |
b9a5aa8e | 8538 | } |
bf2a98b3 | 8539 | |
b9a5aa8e | 8540 | /* From now on, things must be in order. So emit blockages. */ |
8541 | ||
8542 | /* Restore the frame pointer. */ | |
9caef960 | 8543 | if (TARGET_ABI_UNICOSMK) |
8544 | { | |
8545 | emit_insn (gen_blockage ()); | |
8546 | mem = gen_rtx_MEM (DImode, | |
8547 | plus_constant (hard_frame_pointer_rtx, -16)); | |
8548 | set_mem_alias_set (mem, alpha_sr_alias_set); | |
d30e4246 | 8549 | emit_move_insn (hard_frame_pointer_rtx, mem); |
8550 | cfa_restores = alloc_reg_note (REG_CFA_RESTORE, | |
8551 | hard_frame_pointer_rtx, cfa_restores); | |
9caef960 | 8552 | } |
8553 | else if (fp_is_frame_pointer) | |
b9a5aa8e | 8554 | { |
8555 | emit_insn (gen_blockage ()); | |
205b281f | 8556 | mem = gen_rtx_MEM (DImode, plus_constant (sa_reg, fp_offset)); |
ab6ab77e | 8557 | set_mem_alias_set (mem, alpha_sr_alias_set); |
d30e4246 | 8558 | emit_move_insn (hard_frame_pointer_rtx, mem); |
8559 | cfa_restores = alloc_reg_note (REG_CFA_RESTORE, | |
8560 | hard_frame_pointer_rtx, cfa_restores); | |
b9a5aa8e | 8561 | } |
1467e953 | 8562 | else if (TARGET_ABI_OPEN_VMS) |
b9a5aa8e | 8563 | { |
8564 | emit_insn (gen_blockage ()); | |
d30e4246 | 8565 | emit_move_insn (hard_frame_pointer_rtx, |
8566 | gen_rtx_REG (DImode, vms_save_fp_regno)); | |
8567 | cfa_restores = alloc_reg_note (REG_CFA_RESTORE, | |
8568 | hard_frame_pointer_rtx, cfa_restores); | |
b9a5aa8e | 8569 | } |
8570 | ||
8571 | /* Restore the stack pointer. */ | |
8572 | emit_insn (gen_blockage ()); | |
9caef960 | 8573 | if (sp_adj2 == const0_rtx) |
d30e4246 | 8574 | insn = emit_move_insn (stack_pointer_rtx, sp_adj1); |
9caef960 | 8575 | else |
d30e4246 | 8576 | insn = emit_move_insn (stack_pointer_rtx, |
8577 | gen_rtx_PLUS (DImode, sp_adj1, sp_adj2)); | |
8578 | REG_NOTES (insn) = cfa_restores; | |
8579 | add_reg_note (insn, REG_CFA_DEF_CFA, stack_pointer_rtx); | |
8580 | RTX_FRAME_RELATED_P (insn) = 1; | |
b9a5aa8e | 8581 | } |
9e7454d0 | 8582 | else |
b9a5aa8e | 8583 | { |
d30e4246 | 8584 | gcc_assert (cfa_restores == NULL); |
8585 | ||
b19d7ab1 | 8586 | if (TARGET_ABI_OPEN_VMS && alpha_procedure_type == PT_REGISTER) |
b9a5aa8e | 8587 | { |
8588 | emit_insn (gen_blockage ()); | |
d30e4246 | 8589 | insn = emit_move_insn (hard_frame_pointer_rtx, |
8590 | gen_rtx_REG (DImode, vms_save_fp_regno)); | |
8591 | add_reg_note (insn, REG_CFA_RESTORE, hard_frame_pointer_rtx); | |
8592 | RTX_FRAME_RELATED_P (insn) = 1; | |
b9a5aa8e | 8593 | } |
b19d7ab1 | 8594 | else if (TARGET_ABI_UNICOSMK && alpha_procedure_type != PT_STACK) |
9caef960 | 8595 | { |
8596 | /* Decrement the frame pointer if the function does not have a | |
8597 | frame. */ | |
9caef960 | 8598 | emit_insn (gen_blockage ()); |
d30e4246 | 8599 | emit_insn (gen_adddi3 (hard_frame_pointer_rtx, |
8600 | hard_frame_pointer_rtx, constm1_rtx)); | |
9caef960 | 8601 | } |
bf2a98b3 | 8602 | } |
b9a5aa8e | 8603 | } |
cf73d31f | 8604 | \f |
b9a5aa8e | 8605 | /* Output the rest of the textual info surrounding the epilogue. */ |
8606 | ||
8607 | void | |
92643d95 | 8608 | alpha_end_function (FILE *file, const char *fnname, tree decl ATTRIBUTE_UNUSED) |
b9a5aa8e | 8609 | { |
32a8f747 | 8610 | rtx insn; |
8611 | ||
8612 | /* We output a nop after noreturn calls at the very end of the function to | |
8613 | ensure that the return address always remains in the caller's code range, | |
8614 | as not doing so might confuse unwinding engines. */ | |
8615 | insn = get_last_insn (); | |
8616 | if (!INSN_P (insn)) | |
8617 | insn = prev_active_insn (insn); | |
937fc2f7 | 8618 | if (insn && CALL_P (insn)) |
32a8f747 | 8619 | output_asm_insn (get_insn_template (CODE_FOR_nop, NULL), NULL); |
8620 | ||
04b0d94a | 8621 | #if TARGET_ABI_OPEN_VMS |
8622 | alpha_write_linkage (file, fnname, decl); | |
8623 | #endif | |
8624 | ||
bf2a98b3 | 8625 | /* End the function. */ |
9caef960 | 8626 | if (!TARGET_ABI_UNICOSMK && !flag_inhibit_size_directive) |
f1fe649e | 8627 | { |
b9a5aa8e | 8628 | fputs ("\t.end ", file); |
2cf1388a | 8629 | assemble_name (file, fnname); |
b9a5aa8e | 8630 | putc ('\n', file); |
f1fe649e | 8631 | } |
449b7f2d | 8632 | inside_function = FALSE; |
9c0e5703 | 8633 | |
9caef960 | 8634 | /* Output jump tables and the static subroutine information block. */ |
8635 | if (TARGET_ABI_UNICOSMK) | |
8636 | { | |
8637 | unicosmk_output_ssib (file, fnname); | |
8638 | unicosmk_output_deferred_case_vectors (file); | |
8639 | } | |
bf2a98b3 | 8640 | } |
961d6ddd | 8641 | |
2db66e7c | 8642 | #if TARGET_ABI_OPEN_VMS |
8643 | void avms_asm_output_external (FILE *file, tree decl ATTRIBUTE_UNUSED, const char *name) | |
8644 | { | |
8645 | #ifdef DO_CRTL_NAMES | |
8646 | DO_CRTL_NAMES; | |
8647 | #endif | |
8648 | } | |
8649 | #endif | |
8650 | ||
6988553d | 8651 | #if TARGET_ABI_OSF |
8652 | /* Emit a tail call to FUNCTION after adjusting THIS by DELTA. | |
961d6ddd | 8653 | |
8654 | In order to avoid the hordes of differences between generated code | |
8655 | with and without TARGET_EXPLICIT_RELOCS, and to avoid duplicating | |
8656 | lots of code loading up large constants, generate rtl and emit it | |
8657 | instead of going straight to text. | |
8658 | ||
8659 | Not sure why this idea hasn't been explored before... */ | |
8660 | ||
6988553d | 8661 | static void |
92643d95 | 8662 | alpha_output_mi_thunk_osf (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED, |
8663 | HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset, | |
8664 | tree function) | |
961d6ddd | 8665 | { |
8666 | HOST_WIDE_INT hi, lo; | |
8deb3959 | 8667 | rtx this_rtx, insn, funexp; |
961d6ddd | 8668 | |
8669 | /* We always require a valid GP. */ | |
8670 | emit_insn (gen_prologue_ldgp ()); | |
31b97e8f | 8671 | emit_note (NOTE_INSN_PROLOGUE_END); |
961d6ddd | 8672 | |
8673 | /* Find the "this" pointer. If the function returns a structure, | |
8674 | the structure return pointer is in $16. */ | |
45550790 | 8675 | if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function)) |
8deb3959 | 8676 | this_rtx = gen_rtx_REG (Pmode, 17); |
961d6ddd | 8677 | else |
8deb3959 | 8678 | this_rtx = gen_rtx_REG (Pmode, 16); |
961d6ddd | 8679 | |
8680 | /* Add DELTA. When possible we use ldah+lda. Otherwise load the | |
8681 | entire constant for the add. */ | |
8682 | lo = ((delta & 0xffff) ^ 0x8000) - 0x8000; | |
8683 | hi = (((delta - lo) & 0xffffffff) ^ 0x80000000) - 0x80000000; | |
8684 | if (hi + lo == delta) | |
8685 | { | |
8686 | if (hi) | |
8deb3959 | 8687 | emit_insn (gen_adddi3 (this_rtx, this_rtx, GEN_INT (hi))); |
961d6ddd | 8688 | if (lo) |
8deb3959 | 8689 | emit_insn (gen_adddi3 (this_rtx, this_rtx, GEN_INT (lo))); |
961d6ddd | 8690 | } |
8691 | else | |
8692 | { | |
8693 | rtx tmp = alpha_emit_set_long_const (gen_rtx_REG (Pmode, 0), | |
8694 | delta, -(delta < 0)); | |
8deb3959 | 8695 | emit_insn (gen_adddi3 (this_rtx, this_rtx, tmp)); |
961d6ddd | 8696 | } |
8697 | ||
a19ec9da | 8698 | /* Add a delta stored in the vtable at VCALL_OFFSET. */ |
8699 | if (vcall_offset) | |
8700 | { | |
8701 | rtx tmp, tmp2; | |
8702 | ||
8703 | tmp = gen_rtx_REG (Pmode, 0); | |
8deb3959 | 8704 | emit_move_insn (tmp, gen_rtx_MEM (Pmode, this_rtx)); |
a19ec9da | 8705 | |
8706 | lo = ((vcall_offset & 0xffff) ^ 0x8000) - 0x8000; | |
8707 | hi = (((vcall_offset - lo) & 0xffffffff) ^ 0x80000000) - 0x80000000; | |
8708 | if (hi + lo == vcall_offset) | |
8709 | { | |
8710 | if (hi) | |
8711 | emit_insn (gen_adddi3 (tmp, tmp, GEN_INT (hi))); | |
8712 | } | |
8713 | else | |
8714 | { | |
8715 | tmp2 = alpha_emit_set_long_const (gen_rtx_REG (Pmode, 1), | |
8716 | vcall_offset, -(vcall_offset < 0)); | |
8717 | emit_insn (gen_adddi3 (tmp, tmp, tmp2)); | |
8718 | lo = 0; | |
8719 | } | |
8720 | if (lo) | |
8721 | tmp2 = gen_rtx_PLUS (Pmode, tmp, GEN_INT (lo)); | |
8722 | else | |
8723 | tmp2 = tmp; | |
8724 | emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp2)); | |
8725 | ||
8deb3959 | 8726 | emit_insn (gen_adddi3 (this_rtx, this_rtx, tmp)); |
a19ec9da | 8727 | } |
8728 | ||
961d6ddd | 8729 | /* Generate a tail call to the target function. */ |
8730 | if (! TREE_USED (function)) | |
8731 | { | |
8732 | assemble_external (function); | |
8733 | TREE_USED (function) = 1; | |
8734 | } | |
8735 | funexp = XEXP (DECL_RTL (function), 0); | |
8736 | funexp = gen_rtx_MEM (FUNCTION_MODE, funexp); | |
8737 | insn = emit_call_insn (gen_sibcall (funexp, const0_rtx)); | |
8738 | SIBLING_CALL_P (insn) = 1; | |
8739 | ||
8740 | /* Run just enough of rest_of_compilation to get the insns emitted. | |
8741 | There's not really enough bulk here to make other passes such as | |
8742 | instruction scheduling worth while. Note that use_thunk calls | |
8743 | assemble_start_function and assemble_end_function. */ | |
8744 | insn = get_insns (); | |
221a03b9 | 8745 | insn_locators_alloc (); |
961d6ddd | 8746 | shorten_branches (insn); |
8747 | final_start_function (insn, file, 1); | |
4bf029b0 | 8748 | final (insn, file, 1); |
961d6ddd | 8749 | final_end_function (); |
8750 | } | |
6988553d | 8751 | #endif /* TARGET_ABI_OSF */ |
449b7f2d | 8752 | \f |
8753 | /* Debugging support. */ | |
8754 | ||
8755 | #include "gstab.h" | |
8756 | ||
8757 | /* Count the number of sdb related labels are generated (to find block | |
8758 | start and end boundaries). */ | |
8759 | ||
8760 | int sdb_label_count = 0; | |
8761 | ||
449b7f2d | 8762 | /* Name of the file containing the current function. */ |
8763 | ||
ace75b22 | 8764 | static const char *current_function_file = ""; |
449b7f2d | 8765 | |
8766 | /* Offsets to alpha virtual arg/local debugging pointers. */ | |
8767 | ||
8768 | long alpha_arg_offset; | |
8769 | long alpha_auto_offset; | |
8770 | \f | |
8771 | /* Emit a new filename to a stream. */ | |
8772 | ||
8773 | void | |
92643d95 | 8774 | alpha_output_filename (FILE *stream, const char *name) |
449b7f2d | 8775 | { |
8776 | static int first_time = TRUE; | |
449b7f2d | 8777 | |
8778 | if (first_time) | |
8779 | { | |
8780 | first_time = FALSE; | |
8781 | ++num_source_filenames; | |
8782 | current_function_file = name; | |
8783 | fprintf (stream, "\t.file\t%d ", num_source_filenames); | |
8784 | output_quoted_string (stream, name); | |
8785 | fprintf (stream, "\n"); | |
8786 | if (!TARGET_GAS && write_symbols == DBX_DEBUG) | |
8787 | fprintf (stream, "\t#@stabs\n"); | |
8788 | } | |
8789 | ||
8763f243 | 8790 | else if (write_symbols == DBX_DEBUG) |
e3b8b697 | 8791 | /* dbxout.c will emit an appropriate .stabs directive. */ |
8792 | return; | |
449b7f2d | 8793 | |
8794 | else if (name != current_function_file | |
be3797c1 | 8795 | && strcmp (name, current_function_file) != 0) |
449b7f2d | 8796 | { |
8797 | if (inside_function && ! TARGET_GAS) | |
8798 | fprintf (stream, "\t#.file\t%d ", num_source_filenames); | |
8799 | else | |
8800 | { | |
8801 | ++num_source_filenames; | |
8802 | current_function_file = name; | |
8803 | fprintf (stream, "\t.file\t%d ", num_source_filenames); | |
8804 | } | |
8805 | ||
8806 | output_quoted_string (stream, name); | |
8807 | fprintf (stream, "\n"); | |
8808 | } | |
8809 | } | |
c4622276 | 8810 | \f |
8811 | /* Structure to show the current status of registers and memory. */ | |
8812 | ||
8813 | struct shadow_summary | |
8814 | { | |
8815 | struct { | |
495c4a78 | 8816 | unsigned int i : 31; /* Mask of int regs */ |
8817 | unsigned int fp : 31; /* Mask of fp regs */ | |
8818 | unsigned int mem : 1; /* mem == imem | fpmem */ | |
c4622276 | 8819 | } used, defd; |
8820 | }; | |
8821 | ||
8822 | /* Summary the effects of expression X on the machine. Update SUM, a pointer | |
8823 | to the summary structure. SET is nonzero if the insn is setting the | |
8824 | object, otherwise zero. */ | |
8825 | ||
8826 | static void | |
92643d95 | 8827 | summarize_insn (rtx x, struct shadow_summary *sum, int set) |
c4622276 | 8828 | { |
d2ca078f | 8829 | const char *format_ptr; |
c4622276 | 8830 | int i, j; |
8831 | ||
8832 | if (x == 0) | |
8833 | return; | |
8834 | ||
8835 | switch (GET_CODE (x)) | |
8836 | { | |
8837 | /* ??? Note that this case would be incorrect if the Alpha had a | |
8838 | ZERO_EXTRACT in SET_DEST. */ | |
8839 | case SET: | |
8840 | summarize_insn (SET_SRC (x), sum, 0); | |
8841 | summarize_insn (SET_DEST (x), sum, 1); | |
8842 | break; | |
8843 | ||
8844 | case CLOBBER: | |
8845 | summarize_insn (XEXP (x, 0), sum, 1); | |
8846 | break; | |
8847 | ||
8848 | case USE: | |
8849 | summarize_insn (XEXP (x, 0), sum, 0); | |
8850 | break; | |
8851 | ||
a886cc41 | 8852 | case ASM_OPERANDS: |
8853 | for (i = ASM_OPERANDS_INPUT_LENGTH (x) - 1; i >= 0; i--) | |
8854 | summarize_insn (ASM_OPERANDS_INPUT (x, i), sum, 0); | |
8855 | break; | |
8856 | ||
c4622276 | 8857 | case PARALLEL: |
3a5dbb5e | 8858 | for (i = XVECLEN (x, 0) - 1; i >= 0; i--) |
c4622276 | 8859 | summarize_insn (XVECEXP (x, 0, i), sum, 0); |
8860 | break; | |
8861 | ||
a886cc41 | 8862 | case SUBREG: |
b9a5aa8e | 8863 | summarize_insn (SUBREG_REG (x), sum, 0); |
8864 | break; | |
a886cc41 | 8865 | |
c4622276 | 8866 | case REG: |
8867 | { | |
8868 | int regno = REGNO (x); | |
f3d263a7 | 8869 | unsigned long mask = ((unsigned long) 1) << (regno % 32); |
c4622276 | 8870 | |
8871 | if (regno == 31 || regno == 63) | |
8872 | break; | |
8873 | ||
8874 | if (set) | |
8875 | { | |
8876 | if (regno < 32) | |
8877 | sum->defd.i |= mask; | |
8878 | else | |
8879 | sum->defd.fp |= mask; | |
8880 | } | |
8881 | else | |
8882 | { | |
8883 | if (regno < 32) | |
8884 | sum->used.i |= mask; | |
8885 | else | |
8886 | sum->used.fp |= mask; | |
8887 | } | |
8888 | } | |
8889 | break; | |
8890 | ||
8891 | case MEM: | |
8892 | if (set) | |
8893 | sum->defd.mem = 1; | |
8894 | else | |
8895 | sum->used.mem = 1; | |
8896 | ||
8897 | /* Find the regs used in memory address computation: */ | |
8898 | summarize_insn (XEXP (x, 0), sum, 0); | |
8899 | break; | |
8900 | ||
2d710b28 | 8901 | case CONST_INT: case CONST_DOUBLE: |
8902 | case SYMBOL_REF: case LABEL_REF: case CONST: | |
5bdbf614 | 8903 | case SCRATCH: case ASM_INPUT: |
2d710b28 | 8904 | break; |
8905 | ||
c4622276 | 8906 | /* Handle common unary and binary ops for efficiency. */ |
8907 | case COMPARE: case PLUS: case MINUS: case MULT: case DIV: | |
8908 | case MOD: case UDIV: case UMOD: case AND: case IOR: | |
8909 | case XOR: case ASHIFT: case ROTATE: case ASHIFTRT: case LSHIFTRT: | |
8910 | case ROTATERT: case SMIN: case SMAX: case UMIN: case UMAX: | |
8911 | case NE: case EQ: case GE: case GT: case LE: | |
8912 | case LT: case GEU: case GTU: case LEU: case LTU: | |
8913 | summarize_insn (XEXP (x, 0), sum, 0); | |
8914 | summarize_insn (XEXP (x, 1), sum, 0); | |
8915 | break; | |
8916 | ||
8917 | case NEG: case NOT: case SIGN_EXTEND: case ZERO_EXTEND: | |
8918 | case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE: case FLOAT: | |
8919 | case FIX: case UNSIGNED_FLOAT: case UNSIGNED_FIX: case ABS: | |
9e7454d0 | 8920 | case SQRT: case FFS: |
c4622276 | 8921 | summarize_insn (XEXP (x, 0), sum, 0); |
8922 | break; | |
8923 | ||
8924 | default: | |
8925 | format_ptr = GET_RTX_FORMAT (GET_CODE (x)); | |
3a5dbb5e | 8926 | for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--) |
cada32d3 | 8927 | switch (format_ptr[i]) |
c4622276 | 8928 | { |
8929 | case 'e': | |
8930 | summarize_insn (XEXP (x, i), sum, 0); | |
8931 | break; | |
8932 | ||
8933 | case 'E': | |
3a5dbb5e | 8934 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) |
c4622276 | 8935 | summarize_insn (XVECEXP (x, i, j), sum, 0); |
8936 | break; | |
8937 | ||
1dc5f36f | 8938 | case 'i': |
8939 | break; | |
8940 | ||
c4622276 | 8941 | default: |
4d10b463 | 8942 | gcc_unreachable (); |
c4622276 | 8943 | } |
8944 | } | |
8945 | } | |
c4622276 | 8946 | |
b9a5aa8e | 8947 | /* Ensure a sufficient number of `trapb' insns are in the code when |
8948 | the user requests code with a trap precision of functions or | |
8949 | instructions. | |
8950 | ||
8951 | In naive mode, when the user requests a trap-precision of | |
8952 | "instruction", a trapb is needed after every instruction that may | |
8953 | generate a trap. This ensures that the code is resumption safe but | |
8954 | it is also slow. | |
8955 | ||
8956 | When optimizations are turned on, we delay issuing a trapb as long | |
8957 | as possible. In this context, a trap shadow is the sequence of | |
8958 | instructions that starts with a (potentially) trap generating | |
8959 | instruction and extends to the next trapb or call_pal instruction | |
8960 | (but GCC never generates call_pal by itself). We can delay (and | |
8961 | therefore sometimes omit) a trapb subject to the following | |
8962 | conditions: | |
8963 | ||
8964 | (a) On entry to the trap shadow, if any Alpha register or memory | |
8965 | location contains a value that is used as an operand value by some | |
8966 | instruction in the trap shadow (live on entry), then no instruction | |
8967 | in the trap shadow may modify the register or memory location. | |
8968 | ||
8969 | (b) Within the trap shadow, the computation of the base register | |
8970 | for a memory load or store instruction may not involve using the | |
8971 | result of an instruction that might generate an UNPREDICTABLE | |
8972 | result. | |
8973 | ||
8974 | (c) Within the trap shadow, no register may be used more than once | |
8975 | as a destination register. (This is to make life easier for the | |
8976 | trap-handler.) | |
c4622276 | 8977 | |
18adf4f6 | 8978 | (d) The trap shadow may not include any branch instructions. */ |
c4622276 | 8979 | |
18adf4f6 | 8980 | static void |
92643d95 | 8981 | alpha_handle_trap_shadows (void) |
c4622276 | 8982 | { |
18adf4f6 | 8983 | struct shadow_summary shadow; |
8984 | int trap_pending, exception_nesting; | |
b9b4428b | 8985 | rtx i, n; |
c4622276 | 8986 | |
18adf4f6 | 8987 | trap_pending = 0; |
8988 | exception_nesting = 0; | |
8989 | shadow.used.i = 0; | |
8990 | shadow.used.fp = 0; | |
8991 | shadow.used.mem = 0; | |
8992 | shadow.defd = shadow.used; | |
9e7454d0 | 8993 | |
2efea8c0 | 8994 | for (i = get_insns (); i ; i = NEXT_INSN (i)) |
18adf4f6 | 8995 | { |
c933fb42 | 8996 | if (NOTE_P (i)) |
18adf4f6 | 8997 | { |
ad4583d9 | 8998 | switch (NOTE_KIND (i)) |
18adf4f6 | 8999 | { |
9000 | case NOTE_INSN_EH_REGION_BEG: | |
9001 | exception_nesting++; | |
9002 | if (trap_pending) | |
9003 | goto close_shadow; | |
9004 | break; | |
9005 | ||
9006 | case NOTE_INSN_EH_REGION_END: | |
9007 | exception_nesting--; | |
9008 | if (trap_pending) | |
9009 | goto close_shadow; | |
9010 | break; | |
9011 | ||
9012 | case NOTE_INSN_EPILOGUE_BEG: | |
9013 | if (trap_pending && alpha_tp >= ALPHA_TP_FUNC) | |
9014 | goto close_shadow; | |
9015 | break; | |
9016 | } | |
9017 | } | |
9018 | else if (trap_pending) | |
9019 | { | |
9020 | if (alpha_tp == ALPHA_TP_FUNC) | |
9021 | { | |
c933fb42 | 9022 | if (JUMP_P (i) |
18adf4f6 | 9023 | && GET_CODE (PATTERN (i)) == RETURN) |
9024 | goto close_shadow; | |
9025 | } | |
9026 | else if (alpha_tp == ALPHA_TP_INSN) | |
9027 | { | |
9028 | if (optimize > 0) | |
9029 | { | |
9030 | struct shadow_summary sum; | |
9031 | ||
9032 | sum.used.i = 0; | |
9033 | sum.used.fp = 0; | |
9034 | sum.used.mem = 0; | |
a886cc41 | 9035 | sum.defd = sum.used; |
18adf4f6 | 9036 | |
9037 | switch (GET_CODE (i)) | |
9038 | { | |
9039 | case INSN: | |
4d10b463 | 9040 | /* Annoyingly, get_attr_trap will die on these. */ |
fad0a39b | 9041 | if (GET_CODE (PATTERN (i)) == USE |
9042 | || GET_CODE (PATTERN (i)) == CLOBBER) | |
18adf4f6 | 9043 | break; |
9044 | ||
9045 | summarize_insn (PATTERN (i), &sum, 0); | |
9046 | ||
9047 | if ((sum.defd.i & shadow.defd.i) | |
9048 | || (sum.defd.fp & shadow.defd.fp)) | |
9049 | { | |
9050 | /* (c) would be violated */ | |
9051 | goto close_shadow; | |
9052 | } | |
9053 | ||
9054 | /* Combine shadow with summary of current insn: */ | |
9055 | shadow.used.i |= sum.used.i; | |
9056 | shadow.used.fp |= sum.used.fp; | |
9057 | shadow.used.mem |= sum.used.mem; | |
9058 | shadow.defd.i |= sum.defd.i; | |
9059 | shadow.defd.fp |= sum.defd.fp; | |
9060 | shadow.defd.mem |= sum.defd.mem; | |
9061 | ||
9062 | if ((sum.defd.i & shadow.used.i) | |
9063 | || (sum.defd.fp & shadow.used.fp) | |
9064 | || (sum.defd.mem & shadow.used.mem)) | |
9065 | { | |
9066 | /* (a) would be violated (also takes care of (b)) */ | |
4d10b463 | 9067 | gcc_assert (get_attr_trap (i) != TRAP_YES |
9068 | || (!(sum.defd.i & sum.used.i) | |
9069 | && !(sum.defd.fp & sum.used.fp))); | |
18adf4f6 | 9070 | |
9071 | goto close_shadow; | |
9072 | } | |
9073 | break; | |
9074 | ||
9075 | case JUMP_INSN: | |
9076 | case CALL_INSN: | |
9077 | case CODE_LABEL: | |
9078 | goto close_shadow; | |
9079 | ||
9080 | default: | |
4d10b463 | 9081 | gcc_unreachable (); |
18adf4f6 | 9082 | } |
9083 | } | |
9084 | else | |
9085 | { | |
9086 | close_shadow: | |
b9b4428b | 9087 | n = emit_insn_before (gen_trapb (), i); |
9088 | PUT_MODE (n, TImode); | |
9089 | PUT_MODE (i, TImode); | |
18adf4f6 | 9090 | trap_pending = 0; |
9091 | shadow.used.i = 0; | |
9092 | shadow.used.fp = 0; | |
9093 | shadow.used.mem = 0; | |
9094 | shadow.defd = shadow.used; | |
9095 | } | |
9096 | } | |
9097 | } | |
c4622276 | 9098 | |
609d4083 | 9099 | if ((exception_nesting > 0 || alpha_tp >= ALPHA_TP_FUNC) |
c933fb42 | 9100 | && NONJUMP_INSN_P (i) |
609d4083 | 9101 | && GET_CODE (PATTERN (i)) != USE |
9102 | && GET_CODE (PATTERN (i)) != CLOBBER | |
9103 | && get_attr_trap (i) == TRAP_YES) | |
9104 | { | |
9105 | if (optimize && !trap_pending) | |
9106 | summarize_insn (PATTERN (i), &shadow, 0); | |
9107 | trap_pending = 1; | |
9108 | } | |
c4622276 | 9109 | } |
9110 | } | |
b9b4428b | 9111 | \f |
b9b4428b | 9112 | /* Alpha can only issue instruction groups simultaneously if they are |
5910bb95 | 9113 | suitably aligned. This is very processor-specific. */ |
07770f18 | 9114 | /* There are a number of entries in alphaev4_insn_pipe and alphaev5_insn_pipe |
9115 | that are marked "fake". These instructions do not exist on that target, | |
9116 | but it is possible to see these insns with deranged combinations of | |
9117 | command-line options, such as "-mtune=ev4 -mmax". Instead of aborting, | |
9118 | choose a result at random. */ | |
b9b4428b | 9119 | |
849674a3 | 9120 | enum alphaev4_pipe { |
9121 | EV4_STOP = 0, | |
9122 | EV4_IB0 = 1, | |
9123 | EV4_IB1 = 2, | |
9124 | EV4_IBX = 4 | |
9125 | }; | |
9126 | ||
b9b4428b | 9127 | enum alphaev5_pipe { |
9128 | EV5_STOP = 0, | |
9129 | EV5_NONE = 1, | |
9130 | EV5_E01 = 2, | |
9131 | EV5_E0 = 4, | |
9132 | EV5_E1 = 8, | |
9133 | EV5_FAM = 16, | |
9134 | EV5_FA = 32, | |
9135 | EV5_FM = 64 | |
9136 | }; | |
9137 | ||
849674a3 | 9138 | static enum alphaev4_pipe |
92643d95 | 9139 | alphaev4_insn_pipe (rtx insn) |
849674a3 | 9140 | { |
9141 | if (recog_memoized (insn) < 0) | |
9142 | return EV4_STOP; | |
9143 | if (get_attr_length (insn) != 4) | |
9144 | return EV4_STOP; | |
9145 | ||
9146 | switch (get_attr_type (insn)) | |
9147 | { | |
9148 | case TYPE_ILD: | |
f155876e | 9149 | case TYPE_LDSYM: |
849674a3 | 9150 | case TYPE_FLD: |
f155876e | 9151 | case TYPE_LD_L: |
849674a3 | 9152 | return EV4_IBX; |
9153 | ||
849674a3 | 9154 | case TYPE_IADD: |
9155 | case TYPE_ILOG: | |
9156 | case TYPE_ICMOV: | |
9157 | case TYPE_ICMP: | |
849674a3 | 9158 | case TYPE_FST: |
9159 | case TYPE_SHIFT: | |
9160 | case TYPE_IMUL: | |
9161 | case TYPE_FBR: | |
07770f18 | 9162 | case TYPE_MVI: /* fake */ |
849674a3 | 9163 | return EV4_IB0; |
9164 | ||
f155876e | 9165 | case TYPE_IST: |
849674a3 | 9166 | case TYPE_MISC: |
9167 | case TYPE_IBR: | |
9168 | case TYPE_JSR: | |
1050b77e | 9169 | case TYPE_CALLPAL: |
849674a3 | 9170 | case TYPE_FCPYS: |
9171 | case TYPE_FCMOV: | |
9172 | case TYPE_FADD: | |
9173 | case TYPE_FDIV: | |
9174 | case TYPE_FMUL: | |
f155876e | 9175 | case TYPE_ST_C: |
9176 | case TYPE_MB: | |
07770f18 | 9177 | case TYPE_FSQRT: /* fake */ |
9178 | case TYPE_FTOI: /* fake */ | |
9179 | case TYPE_ITOF: /* fake */ | |
849674a3 | 9180 | return EV4_IB1; |
9181 | ||
9182 | default: | |
4d10b463 | 9183 | gcc_unreachable (); |
849674a3 | 9184 | } |
9185 | } | |
9186 | ||
b9b4428b | 9187 | static enum alphaev5_pipe |
92643d95 | 9188 | alphaev5_insn_pipe (rtx insn) |
b9b4428b | 9189 | { |
9190 | if (recog_memoized (insn) < 0) | |
9191 | return EV5_STOP; | |
9192 | if (get_attr_length (insn) != 4) | |
9193 | return EV5_STOP; | |
9194 | ||
9195 | switch (get_attr_type (insn)) | |
9196 | { | |
9197 | case TYPE_ILD: | |
9198 | case TYPE_FLD: | |
9199 | case TYPE_LDSYM: | |
9200 | case TYPE_IADD: | |
9201 | case TYPE_ILOG: | |
9202 | case TYPE_ICMOV: | |
9203 | case TYPE_ICMP: | |
9204 | return EV5_E01; | |
9205 | ||
9206 | case TYPE_IST: | |
9207 | case TYPE_FST: | |
9208 | case TYPE_SHIFT: | |
9209 | case TYPE_IMUL: | |
9210 | case TYPE_MISC: | |
9211 | case TYPE_MVI: | |
f155876e | 9212 | case TYPE_LD_L: |
9213 | case TYPE_ST_C: | |
9214 | case TYPE_MB: | |
07770f18 | 9215 | case TYPE_FTOI: /* fake */ |
9216 | case TYPE_ITOF: /* fake */ | |
b9b4428b | 9217 | return EV5_E0; |
9218 | ||
9219 | case TYPE_IBR: | |
9220 | case TYPE_JSR: | |
1050b77e | 9221 | case TYPE_CALLPAL: |
b9b4428b | 9222 | return EV5_E1; |
9223 | ||
9224 | case TYPE_FCPYS: | |
9225 | return EV5_FAM; | |
9226 | ||
9227 | case TYPE_FBR: | |
9228 | case TYPE_FCMOV: | |
9229 | case TYPE_FADD: | |
9230 | case TYPE_FDIV: | |
07770f18 | 9231 | case TYPE_FSQRT: /* fake */ |
b9b4428b | 9232 | return EV5_FA; |
9233 | ||
9234 | case TYPE_FMUL: | |
9235 | return EV5_FM; | |
ddca68f8 | 9236 | |
9237 | default: | |
4d10b463 | 9238 | gcc_unreachable (); |
b9b4428b | 9239 | } |
b9b4428b | 9240 | } |
9241 | ||
9e7454d0 | 9242 | /* IN_USE is a mask of the slots currently filled within the insn group. |
849674a3 | 9243 | The mask bits come from alphaev4_pipe above. If EV4_IBX is set, then |
9e7454d0 | 9244 | the insn in EV4_IB0 can be swapped by the hardware into EV4_IB1. |
849674a3 | 9245 | |
9246 | LEN is, of course, the length of the group in bytes. */ | |
9247 | ||
9248 | static rtx | |
92643d95 | 9249 | alphaev4_next_group (rtx insn, int *pin_use, int *plen) |
849674a3 | 9250 | { |
9251 | int len, in_use; | |
9252 | ||
9253 | len = in_use = 0; | |
9254 | ||
9204e736 | 9255 | if (! INSN_P (insn) |
849674a3 | 9256 | || GET_CODE (PATTERN (insn)) == CLOBBER |
9257 | || GET_CODE (PATTERN (insn)) == USE) | |
9258 | goto next_and_done; | |
9259 | ||
9260 | while (1) | |
9261 | { | |
9262 | enum alphaev4_pipe pipe; | |
9263 | ||
9264 | pipe = alphaev4_insn_pipe (insn); | |
9265 | switch (pipe) | |
9266 | { | |
9267 | case EV4_STOP: | |
9268 | /* Force complex instructions to start new groups. */ | |
9269 | if (in_use) | |
9270 | goto done; | |
9271 | ||
20833d12 | 9272 | /* If this is a completely unrecognized insn, it's an asm. |
849674a3 | 9273 | We don't know how long it is, so record length as -1 to |
9274 | signal a needed realignment. */ | |
9275 | if (recog_memoized (insn) < 0) | |
9276 | len = -1; | |
9277 | else | |
9278 | len = get_attr_length (insn); | |
9279 | goto next_and_done; | |
9280 | ||
9281 | case EV4_IBX: | |
9282 | if (in_use & EV4_IB0) | |
9283 | { | |
9284 | if (in_use & EV4_IB1) | |
9285 | goto done; | |
9286 | in_use |= EV4_IB1; | |
9287 | } | |
9288 | else | |
9289 | in_use |= EV4_IB0 | EV4_IBX; | |
9290 | break; | |
9291 | ||
9292 | case EV4_IB0: | |
9293 | if (in_use & EV4_IB0) | |
9294 | { | |
9295 | if (!(in_use & EV4_IBX) || (in_use & EV4_IB1)) | |
9296 | goto done; | |
9297 | in_use |= EV4_IB1; | |
9298 | } | |
9299 | in_use |= EV4_IB0; | |
9300 | break; | |
9301 | ||
9302 | case EV4_IB1: | |
9303 | if (in_use & EV4_IB1) | |
9304 | goto done; | |
9305 | in_use |= EV4_IB1; | |
9306 | break; | |
9307 | ||
9308 | default: | |
4d10b463 | 9309 | gcc_unreachable (); |
849674a3 | 9310 | } |
9311 | len += 4; | |
9e7454d0 | 9312 | |
849674a3 | 9313 | /* Haifa doesn't do well scheduling branches. */ |
c933fb42 | 9314 | if (JUMP_P (insn)) |
849674a3 | 9315 | goto next_and_done; |
9316 | ||
9317 | next: | |
9318 | insn = next_nonnote_insn (insn); | |
9319 | ||
9204e736 | 9320 | if (!insn || ! INSN_P (insn)) |
849674a3 | 9321 | goto done; |
9322 | ||
9323 | /* Let Haifa tell us where it thinks insn group boundaries are. */ | |
9324 | if (GET_MODE (insn) == TImode) | |
9325 | goto done; | |
9326 | ||
9327 | if (GET_CODE (insn) == CLOBBER || GET_CODE (insn) == USE) | |
9328 | goto next; | |
9329 | } | |
9330 | ||
9331 | next_and_done: | |
9332 | insn = next_nonnote_insn (insn); | |
9333 | ||
9334 | done: | |
9335 | *plen = len; | |
9336 | *pin_use = in_use; | |
9337 | return insn; | |
9338 | } | |
9339 | ||
9e7454d0 | 9340 | /* IN_USE is a mask of the slots currently filled within the insn group. |
849674a3 | 9341 | The mask bits come from alphaev5_pipe above. If EV5_E01 is set, then |
9e7454d0 | 9342 | the insn in EV5_E0 can be swapped by the hardware into EV5_E1. |
b9b4428b | 9343 | |
9344 | LEN is, of course, the length of the group in bytes. */ | |
9345 | ||
9346 | static rtx | |
92643d95 | 9347 | alphaev5_next_group (rtx insn, int *pin_use, int *plen) |
b9b4428b | 9348 | { |
9349 | int len, in_use; | |
9350 | ||
9351 | len = in_use = 0; | |
9352 | ||
9204e736 | 9353 | if (! INSN_P (insn) |
ddca68f8 | 9354 | || GET_CODE (PATTERN (insn)) == CLOBBER |
9355 | || GET_CODE (PATTERN (insn)) == USE) | |
9356 | goto next_and_done; | |
b9b4428b | 9357 | |
ddca68f8 | 9358 | while (1) |
b9b4428b | 9359 | { |
9360 | enum alphaev5_pipe pipe; | |
b9b4428b | 9361 | |
9362 | pipe = alphaev5_insn_pipe (insn); | |
9363 | switch (pipe) | |
9364 | { | |
9365 | case EV5_STOP: | |
9366 | /* Force complex instructions to start new groups. */ | |
9367 | if (in_use) | |
9368 | goto done; | |
9369 | ||
20833d12 | 9370 | /* If this is a completely unrecognized insn, it's an asm. |
b9b4428b | 9371 | We don't know how long it is, so record length as -1 to |
9372 | signal a needed realignment. */ | |
9373 | if (recog_memoized (insn) < 0) | |
9374 | len = -1; | |
9375 | else | |
9376 | len = get_attr_length (insn); | |
ddca68f8 | 9377 | goto next_and_done; |
b9b4428b | 9378 | |
4d10b463 | 9379 | /* ??? Most of the places below, we would like to assert never |
9380 | happen, as it would indicate an error either in Haifa, or | |
9381 | in the scheduling description. Unfortunately, Haifa never | |
9382 | schedules the last instruction of the BB, so we don't have | |
9383 | an accurate TI bit to go off. */ | |
b9b4428b | 9384 | case EV5_E01: |
9385 | if (in_use & EV5_E0) | |
9386 | { | |
9387 | if (in_use & EV5_E1) | |
9388 | goto done; | |
9389 | in_use |= EV5_E1; | |
9390 | } | |
9391 | else | |
9392 | in_use |= EV5_E0 | EV5_E01; | |
9393 | break; | |
9394 | ||
9395 | case EV5_E0: | |
9396 | if (in_use & EV5_E0) | |
9397 | { | |
849674a3 | 9398 | if (!(in_use & EV5_E01) || (in_use & EV5_E1)) |
b9b4428b | 9399 | goto done; |
9400 | in_use |= EV5_E1; | |
9401 | } | |
9402 | in_use |= EV5_E0; | |
9403 | break; | |
9404 | ||
9405 | case EV5_E1: | |
9406 | if (in_use & EV5_E1) | |
9407 | goto done; | |
9408 | in_use |= EV5_E1; | |
9409 | break; | |
9410 | ||
9411 | case EV5_FAM: | |
9412 | if (in_use & EV5_FA) | |
9413 | { | |
9414 | if (in_use & EV5_FM) | |
9415 | goto done; | |
9416 | in_use |= EV5_FM; | |
9417 | } | |
9418 | else | |
9419 | in_use |= EV5_FA | EV5_FAM; | |
9420 | break; | |
9421 | ||
9422 | case EV5_FA: | |
9423 | if (in_use & EV5_FA) | |
9424 | goto done; | |
9425 | in_use |= EV5_FA; | |
9426 | break; | |
9427 | ||
9428 | case EV5_FM: | |
9429 | if (in_use & EV5_FM) | |
9430 | goto done; | |
9431 | in_use |= EV5_FM; | |
9432 | break; | |
9433 | ||
9434 | case EV5_NONE: | |
9435 | break; | |
9436 | ||
9437 | default: | |
4d10b463 | 9438 | gcc_unreachable (); |
b9b4428b | 9439 | } |
9440 | len += 4; | |
9e7454d0 | 9441 | |
b9b4428b | 9442 | /* Haifa doesn't do well scheduling branches. */ |
9443 | /* ??? If this is predicted not-taken, slotting continues, except | |
9444 | that no more IBR, FBR, or JSR insns may be slotted. */ | |
c933fb42 | 9445 | if (JUMP_P (insn)) |
ddca68f8 | 9446 | goto next_and_done; |
b9b4428b | 9447 | |
ddca68f8 | 9448 | next: |
b9b4428b | 9449 | insn = next_nonnote_insn (insn); |
9450 | ||
9204e736 | 9451 | if (!insn || ! INSN_P (insn)) |
b9b4428b | 9452 | goto done; |
f9137da0 | 9453 | |
b9b4428b | 9454 | /* Let Haifa tell us where it thinks insn group boundaries are. */ |
9455 | if (GET_MODE (insn) == TImode) | |
9456 | goto done; | |
9457 | ||
ddca68f8 | 9458 | if (GET_CODE (insn) == CLOBBER || GET_CODE (insn) == USE) |
9459 | goto next; | |
b9b4428b | 9460 | } |
ddca68f8 | 9461 | |
9462 | next_and_done: | |
9463 | insn = next_nonnote_insn (insn); | |
b9b4428b | 9464 | |
9465 | done: | |
9466 | *plen = len; | |
9467 | *pin_use = in_use; | |
9468 | return insn; | |
b9b4428b | 9469 | } |
9470 | ||
849674a3 | 9471 | static rtx |
92643d95 | 9472 | alphaev4_next_nop (int *pin_use) |
849674a3 | 9473 | { |
9474 | int in_use = *pin_use; | |
9475 | rtx nop; | |
9476 | ||
9477 | if (!(in_use & EV4_IB0)) | |
9478 | { | |
9479 | in_use |= EV4_IB0; | |
9480 | nop = gen_nop (); | |
9481 | } | |
9482 | else if ((in_use & (EV4_IBX|EV4_IB1)) == EV4_IBX) | |
9483 | { | |
9484 | in_use |= EV4_IB1; | |
9485 | nop = gen_nop (); | |
9486 | } | |
9487 | else if (TARGET_FP && !(in_use & EV4_IB1)) | |
9488 | { | |
9489 | in_use |= EV4_IB1; | |
9490 | nop = gen_fnop (); | |
9491 | } | |
9492 | else | |
9493 | nop = gen_unop (); | |
9494 | ||
9495 | *pin_use = in_use; | |
9496 | return nop; | |
9497 | } | |
9498 | ||
9499 | static rtx | |
92643d95 | 9500 | alphaev5_next_nop (int *pin_use) |
849674a3 | 9501 | { |
9502 | int in_use = *pin_use; | |
9503 | rtx nop; | |
9504 | ||
9505 | if (!(in_use & EV5_E1)) | |
9506 | { | |
9507 | in_use |= EV5_E1; | |
9508 | nop = gen_nop (); | |
9509 | } | |
9510 | else if (TARGET_FP && !(in_use & EV5_FA)) | |
9511 | { | |
9512 | in_use |= EV5_FA; | |
9513 | nop = gen_fnop (); | |
9514 | } | |
9515 | else if (TARGET_FP && !(in_use & EV5_FM)) | |
9516 | { | |
9517 | in_use |= EV5_FM; | |
9518 | nop = gen_fnop (); | |
9519 | } | |
9520 | else | |
9521 | nop = gen_unop (); | |
9522 | ||
9523 | *pin_use = in_use; | |
9524 | return nop; | |
9525 | } | |
9526 | ||
9527 | /* The instruction group alignment main loop. */ | |
9528 | ||
b9b4428b | 9529 | static void |
92643d95 | 9530 | alpha_align_insns (unsigned int max_align, |
9531 | rtx (*next_group) (rtx, int *, int *), | |
9532 | rtx (*next_nop) (int *)) | |
b9b4428b | 9533 | { |
9534 | /* ALIGN is the known alignment for the insn group. */ | |
b53f315c | 9535 | unsigned int align; |
b9b4428b | 9536 | /* OFS is the offset of the current insn in the insn group. */ |
9537 | int ofs; | |
fd1ace94 | 9538 | int prev_in_use, in_use, len, ldgp; |
b9b4428b | 9539 | rtx i, next; |
9540 | ||
9541 | /* Let shorten branches care for assigning alignments to code labels. */ | |
2efea8c0 | 9542 | shorten_branches (get_insns ()); |
b9b4428b | 9543 | |
d815ce59 | 9544 | if (align_functions < 4) |
9545 | align = 4; | |
eeca3ba1 | 9546 | else if ((unsigned int) align_functions < max_align) |
d815ce59 | 9547 | align = align_functions; |
9548 | else | |
9549 | align = max_align; | |
e2c8a34a | 9550 | |
b9b4428b | 9551 | ofs = prev_in_use = 0; |
2efea8c0 | 9552 | i = get_insns (); |
c933fb42 | 9553 | if (NOTE_P (i)) |
b9b4428b | 9554 | i = next_nonnote_insn (i); |
9555 | ||
fd1ace94 | 9556 | ldgp = alpha_function_needs_gp ? 8 : 0; |
9557 | ||
b9b4428b | 9558 | while (i) |
9559 | { | |
b53f315c | 9560 | next = (*next_group) (i, &in_use, &len); |
b9b4428b | 9561 | |
9562 | /* When we see a label, resync alignment etc. */ | |
c933fb42 | 9563 | if (LABEL_P (i)) |
b9b4428b | 9564 | { |
b53f315c | 9565 | unsigned int new_align = 1 << label_to_alignment (i); |
9566 | ||
b9b4428b | 9567 | if (new_align >= align) |
9568 | { | |
849674a3 | 9569 | align = new_align < max_align ? new_align : max_align; |
b9b4428b | 9570 | ofs = 0; |
9571 | } | |
b53f315c | 9572 | |
b9b4428b | 9573 | else if (ofs & (new_align-1)) |
9574 | ofs = (ofs | (new_align-1)) + 1; | |
4d10b463 | 9575 | gcc_assert (!len); |
b9b4428b | 9576 | } |
9577 | ||
9578 | /* Handle complex instructions special. */ | |
9579 | else if (in_use == 0) | |
9580 | { | |
9581 | /* Asms will have length < 0. This is a signal that we have | |
9582 | lost alignment knowledge. Assume, however, that the asm | |
9583 | will not mis-align instructions. */ | |
9584 | if (len < 0) | |
9585 | { | |
9586 | ofs = 0; | |
9587 | align = 4; | |
9588 | len = 0; | |
9589 | } | |
9590 | } | |
9591 | ||
9592 | /* If the known alignment is smaller than the recognized insn group, | |
9593 | realign the output. */ | |
1f0ce6a6 | 9594 | else if ((int) align < len) |
b9b4428b | 9595 | { |
b53f315c | 9596 | unsigned int new_log_align = len > 8 ? 4 : 3; |
943a1b57 | 9597 | rtx prev, where; |
b9b4428b | 9598 | |
943a1b57 | 9599 | where = prev = prev_nonnote_insn (i); |
c933fb42 | 9600 | if (!where || !LABEL_P (where)) |
b9b4428b | 9601 | where = i; |
9602 | ||
943a1b57 | 9603 | /* Can't realign between a call and its gp reload. */ |
9604 | if (! (TARGET_EXPLICIT_RELOCS | |
c933fb42 | 9605 | && prev && CALL_P (prev))) |
943a1b57 | 9606 | { |
9607 | emit_insn_before (gen_realign (GEN_INT (new_log_align)), where); | |
9608 | align = 1 << new_log_align; | |
9609 | ofs = 0; | |
9610 | } | |
b9b4428b | 9611 | } |
9612 | ||
fd1ace94 | 9613 | /* We may not insert padding inside the initial ldgp sequence. */ |
9614 | else if (ldgp > 0) | |
9615 | ldgp -= len; | |
9616 | ||
b9b4428b | 9617 | /* If the group won't fit in the same INT16 as the previous, |
9618 | we need to add padding to keep the group together. Rather | |
9619 | than simply leaving the insn filling to the assembler, we | |
9620 | can make use of the knowledge of what sorts of instructions | |
9621 | were issued in the previous group to make sure that all of | |
9622 | the added nops are really free. */ | |
1f0ce6a6 | 9623 | else if (ofs + len > (int) align) |
b9b4428b | 9624 | { |
9625 | int nop_count = (align - ofs) / 4; | |
9626 | rtx where; | |
9627 | ||
efee20da | 9628 | /* Insert nops before labels, branches, and calls to truly merge |
943a1b57 | 9629 | the execution of the nops with the previous instruction group. */ |
b9b4428b | 9630 | where = prev_nonnote_insn (i); |
849674a3 | 9631 | if (where) |
b9b4428b | 9632 | { |
c933fb42 | 9633 | if (LABEL_P (where)) |
b9b4428b | 9634 | { |
849674a3 | 9635 | rtx where2 = prev_nonnote_insn (where); |
c933fb42 | 9636 | if (where2 && JUMP_P (where2)) |
849674a3 | 9637 | where = where2; |
b9b4428b | 9638 | } |
c933fb42 | 9639 | else if (NONJUMP_INSN_P (where)) |
849674a3 | 9640 | where = i; |
b9b4428b | 9641 | } |
849674a3 | 9642 | else |
9643 | where = i; | |
9644 | ||
9e7454d0 | 9645 | do |
849674a3 | 9646 | emit_insn_before ((*next_nop)(&prev_in_use), where); |
b9b4428b | 9647 | while (--nop_count); |
9648 | ofs = 0; | |
9649 | } | |
9650 | ||
9651 | ofs = (ofs + len) & (align - 1); | |
9652 | prev_in_use = in_use; | |
9653 | i = next; | |
9654 | } | |
9655 | } | |
a27deefc | 9656 | |
9657 | /* Insert an unop between a noreturn function call and GP load. */ | |
9658 | ||
9659 | static void | |
9660 | alpha_pad_noreturn (void) | |
9661 | { | |
9662 | rtx insn, next; | |
9663 | ||
9664 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) | |
9665 | { | |
9666 | if (!CALL_P (insn) | |
9667 | || !find_reg_note (insn, REG_NORETURN, NULL_RTX)) | |
9668 | continue; | |
9669 | ||
9670 | next = next_active_insn (insn); | |
9671 | ||
9672 | if (next) | |
9673 | { | |
9674 | rtx pat = PATTERN (next); | |
9675 | ||
9676 | if (GET_CODE (pat) == SET | |
9677 | && GET_CODE (SET_SRC (pat)) == UNSPEC_VOLATILE | |
9678 | && XINT (SET_SRC (pat), 1) == UNSPECV_LDGP1) | |
9679 | emit_insn_after (gen_unop (), insn); | |
9680 | } | |
9681 | } | |
9682 | } | |
b9b4428b | 9683 | \f |
35a3065a | 9684 | /* Machine dependent reorg pass. */ |
18adf4f6 | 9685 | |
2efea8c0 | 9686 | static void |
92643d95 | 9687 | alpha_reorg (void) |
18adf4f6 | 9688 | { |
a27deefc | 9689 | /* Workaround for a linker error that triggers when an |
9690 | exception handler immediatelly follows a noreturn function. | |
9691 | ||
9692 | The instruction stream from an object file: | |
9693 | ||
9694 | 54: 00 40 5b 6b jsr ra,(t12),58 <__func+0x58> | |
9695 | 58: 00 00 ba 27 ldah gp,0(ra) | |
9696 | 5c: 00 00 bd 23 lda gp,0(gp) | |
9697 | 60: 00 00 7d a7 ldq t12,0(gp) | |
9698 | 64: 00 40 5b 6b jsr ra,(t12),68 <__func+0x68> | |
9699 | ||
9700 | was converted in the final link pass to: | |
9701 | ||
9702 | fdb24: a0 03 40 d3 bsr ra,fe9a8 <_called_func+0x8> | |
9703 | fdb28: 00 00 fe 2f unop | |
9704 | fdb2c: 00 00 fe 2f unop | |
9705 | fdb30: 30 82 7d a7 ldq t12,-32208(gp) | |
9706 | fdb34: 00 40 5b 6b jsr ra,(t12),fdb38 <__func+0x68> | |
9707 | ||
9708 | GP load instructions were wrongly cleared by the linker relaxation | |
9709 | pass. This workaround prevents removal of GP loads by inserting | |
9710 | an unop instruction between a noreturn function call and | |
9711 | exception handler prologue. */ | |
9712 | ||
9713 | if (current_function_has_exception_handlers ()) | |
9714 | alpha_pad_noreturn (); | |
9715 | ||
b9b4428b | 9716 | if (alpha_tp != ALPHA_TP_PROG || flag_exceptions) |
2efea8c0 | 9717 | alpha_handle_trap_shadows (); |
b9b4428b | 9718 | |
b9b4428b | 9719 | /* Due to the number of extra trapb insns, don't bother fixing up |
9720 | alignment when trap precision is instruction. Moreover, we can | |
b53f315c | 9721 | only do our job when sched2 is run. */ |
b9b4428b | 9722 | if (optimize && !optimize_size |
9723 | && alpha_tp != ALPHA_TP_INSN | |
9724 | && flag_schedule_insns_after_reload) | |
9725 | { | |
fb64edde | 9726 | if (alpha_tune == PROCESSOR_EV4) |
2efea8c0 | 9727 | alpha_align_insns (8, alphaev4_next_group, alphaev4_next_nop); |
fb64edde | 9728 | else if (alpha_tune == PROCESSOR_EV5) |
2efea8c0 | 9729 | alpha_align_insns (16, alphaev5_next_group, alphaev5_next_nop); |
b9b4428b | 9730 | } |
18adf4f6 | 9731 | } |
18adf4f6 | 9732 | \f |
92c473b8 | 9733 | #if !TARGET_ABI_UNICOSMK |
9734 | ||
9735 | #ifdef HAVE_STAMP_H | |
9736 | #include <stamp.h> | |
9737 | #endif | |
9738 | ||
9739 | static void | |
9740 | alpha_file_start (void) | |
9741 | { | |
0fdc84d7 | 9742 | #ifdef OBJECT_FORMAT_ELF |
9743 | /* If emitting dwarf2 debug information, we cannot generate a .file | |
9744 | directive to start the file, as it will conflict with dwarf2out | |
9745 | file numbers. So it's only useful when emitting mdebug output. */ | |
9746 | targetm.file_start_file_directive = (write_symbols == DBX_DEBUG); | |
9747 | #endif | |
9748 | ||
92c473b8 | 9749 | default_file_start (); |
9750 | #ifdef MS_STAMP | |
bc964653 | 9751 | fprintf (asm_out_file, "\t.verstamp %d %d\n", MS_STAMP, LS_STAMP); |
92c473b8 | 9752 | #endif |
9753 | ||
9754 | fputs ("\t.set noreorder\n", asm_out_file); | |
9755 | fputs ("\t.set volatile\n", asm_out_file); | |
9756 | if (!TARGET_ABI_OPEN_VMS) | |
9757 | fputs ("\t.set noat\n", asm_out_file); | |
9758 | if (TARGET_EXPLICIT_RELOCS) | |
9759 | fputs ("\t.set nomacro\n", asm_out_file); | |
9760 | if (TARGET_SUPPORT_ARCH | TARGET_BWX | TARGET_MAX | TARGET_FIX | TARGET_CIX) | |
fb64edde | 9761 | { |
9762 | const char *arch; | |
9763 | ||
9764 | if (alpha_cpu == PROCESSOR_EV6 || TARGET_FIX || TARGET_CIX) | |
9765 | arch = "ev6"; | |
9766 | else if (TARGET_MAX) | |
9767 | arch = "pca56"; | |
9768 | else if (TARGET_BWX) | |
9769 | arch = "ev56"; | |
9770 | else if (alpha_cpu == PROCESSOR_EV5) | |
9771 | arch = "ev5"; | |
9772 | else | |
9773 | arch = "ev4"; | |
9774 | ||
9775 | fprintf (asm_out_file, "\t.arch %s\n", arch); | |
9776 | } | |
92c473b8 | 9777 | } |
9778 | #endif | |
9779 | ||
bbfbe351 | 9780 | #ifdef OBJECT_FORMAT_ELF |
4e151b05 | 9781 | /* Since we don't have a .dynbss section, we should not allow global |
9782 | relocations in the .rodata section. */ | |
9783 | ||
9784 | static int | |
9785 | alpha_elf_reloc_rw_mask (void) | |
9786 | { | |
9787 | return flag_pic ? 3 : 2; | |
9788 | } | |
bbfbe351 | 9789 | |
2f14b1f9 | 9790 | /* Return a section for X. The only special thing we do here is to |
9791 | honor small data. */ | |
bbfbe351 | 9792 | |
2f14b1f9 | 9793 | static section * |
92643d95 | 9794 | alpha_elf_select_rtx_section (enum machine_mode mode, rtx x, |
9795 | unsigned HOST_WIDE_INT align) | |
bbfbe351 | 9796 | { |
9797 | if (TARGET_SMALL_DATA && GET_MODE_SIZE (mode) <= g_switch_value) | |
5910bb95 | 9798 | /* ??? Consider using mergeable sdata sections. */ |
2f14b1f9 | 9799 | return sdata_section; |
bbfbe351 | 9800 | else |
2f14b1f9 | 9801 | return default_elf_select_rtx_section (mode, x, align); |
bbfbe351 | 9802 | } |
9803 | ||
cc2af183 | 9804 | static unsigned int |
9805 | alpha_elf_section_type_flags (tree decl, const char *name, int reloc) | |
9806 | { | |
9807 | unsigned int flags = 0; | |
9808 | ||
9809 | if (strcmp (name, ".sdata") == 0 | |
9810 | || strncmp (name, ".sdata.", 7) == 0 | |
9811 | || strncmp (name, ".gnu.linkonce.s.", 16) == 0 | |
9812 | || strcmp (name, ".sbss") == 0 | |
9813 | || strncmp (name, ".sbss.", 6) == 0 | |
9814 | || strncmp (name, ".gnu.linkonce.sb.", 17) == 0) | |
9815 | flags = SECTION_SMALL; | |
9816 | ||
9817 | flags |= default_section_type_flags (decl, name, reloc); | |
9818 | return flags; | |
9819 | } | |
bbfbe351 | 9820 | #endif /* OBJECT_FORMAT_ELF */ |
9821 | \f | |
9de382d9 | 9822 | /* Structure to collect function names for final output in link section. */ |
9823 | /* Note that items marked with GTY can't be ifdef'ed out. */ | |
573aba85 | 9824 | |
9825 | enum links_kind {KIND_UNUSED, KIND_LOCAL, KIND_EXTERN}; | |
9de382d9 | 9826 | enum reloc_kind {KIND_LINKAGE, KIND_CODEADDR}; |
573aba85 | 9827 | |
fb1e4f4a | 9828 | struct GTY(()) alpha_links |
573aba85 | 9829 | { |
9de382d9 | 9830 | int num; |
c45d3ddf | 9831 | const char *target; |
573aba85 | 9832 | rtx linkage; |
9de382d9 | 9833 | enum links_kind lkind; |
9834 | enum reloc_kind rkind; | |
9835 | }; | |
9836 | ||
fb1e4f4a | 9837 | struct GTY(()) alpha_funcs |
9de382d9 | 9838 | { |
9839 | int num; | |
9840 | splay_tree GTY ((param1_is (char *), param2_is (struct alpha_links *))) | |
9841 | links; | |
573aba85 | 9842 | }; |
9843 | ||
9844 | static GTY ((param1_is (char *), param2_is (struct alpha_links *))) | |
9de382d9 | 9845 | splay_tree alpha_links_tree; |
9846 | static GTY ((param1_is (tree), param2_is (struct alpha_funcs *))) | |
9847 | splay_tree alpha_funcs_tree; | |
9848 | ||
9849 | static GTY(()) int alpha_funcs_num; | |
573aba85 | 9850 | |
1467e953 | 9851 | #if TARGET_ABI_OPEN_VMS |
8df4a58b | 9852 | |
0dbd1c74 | 9853 | /* Return the VMS argument type corresponding to MODE. */ |
8df4a58b | 9854 | |
0dbd1c74 | 9855 | enum avms_arg_type |
92643d95 | 9856 | alpha_arg_type (enum machine_mode mode) |
0dbd1c74 | 9857 | { |
9858 | switch (mode) | |
8df4a58b | 9859 | { |
0dbd1c74 | 9860 | case SFmode: |
9861 | return TARGET_FLOAT_VAX ? FF : FS; | |
9862 | case DFmode: | |
9863 | return TARGET_FLOAT_VAX ? FD : FT; | |
9864 | default: | |
9865 | return I64; | |
8df4a58b | 9866 | } |
0dbd1c74 | 9867 | } |
8df4a58b | 9868 | |
0dbd1c74 | 9869 | /* Return an rtx for an integer representing the VMS Argument Information |
9870 | register value. */ | |
8df4a58b | 9871 | |
1dd6c958 | 9872 | rtx |
92643d95 | 9873 | alpha_arg_info_reg_val (CUMULATIVE_ARGS cum) |
0dbd1c74 | 9874 | { |
9875 | unsigned HOST_WIDE_INT regval = cum.num_args; | |
9876 | int i; | |
8df4a58b | 9877 | |
0dbd1c74 | 9878 | for (i = 0; i < 6; i++) |
9879 | regval |= ((int) cum.atypes[i]) << (i * 3 + 8); | |
8df4a58b | 9880 | |
0dbd1c74 | 9881 | return GEN_INT (regval); |
9882 | } | |
9883 | \f | |
c45d3ddf | 9884 | /* Register the need for a (fake) .linkage entry for calls to function NAME. |
9885 | IS_LOCAL is 1 if this is for a definition, 0 if this is for a real call. | |
9886 | Return a SYMBOL_REF suited to the call instruction. */ | |
57e47080 | 9887 | |
9888 | rtx | |
92643d95 | 9889 | alpha_need_linkage (const char *name, int is_local) |
8df4a58b | 9890 | { |
57e47080 | 9891 | splay_tree_node node; |
9892 | struct alpha_links *al; | |
c45d3ddf | 9893 | const char *target; |
9894 | tree id; | |
8df4a58b | 9895 | |
9896 | if (name[0] == '*') | |
9897 | name++; | |
9898 | ||
cf73d31f | 9899 | if (is_local) |
9900 | { | |
9de382d9 | 9901 | struct alpha_funcs *cfaf; |
9902 | ||
9903 | if (!alpha_funcs_tree) | |
9904 | alpha_funcs_tree = splay_tree_new_ggc ((splay_tree_compare_fn) | |
9905 | splay_tree_compare_pointers); | |
9e7454d0 | 9906 | |
9de382d9 | 9907 | cfaf = (struct alpha_funcs *) ggc_alloc (sizeof (struct alpha_funcs)); |
cf73d31f | 9908 | |
9909 | cfaf->links = 0; | |
9910 | cfaf->num = ++alpha_funcs_num; | |
9911 | ||
9912 | splay_tree_insert (alpha_funcs_tree, | |
9913 | (splay_tree_key) current_function_decl, | |
9914 | (splay_tree_value) cfaf); | |
cf73d31f | 9915 | } |
9916 | ||
9917 | if (alpha_links_tree) | |
57e47080 | 9918 | { |
9919 | /* Is this name already defined? */ | |
8df4a58b | 9920 | |
cf73d31f | 9921 | node = splay_tree_lookup (alpha_links_tree, (splay_tree_key) name); |
57e47080 | 9922 | if (node) |
9923 | { | |
9924 | al = (struct alpha_links *) node->value; | |
9925 | if (is_local) | |
9926 | { | |
9927 | /* Defined here but external assumed. */ | |
cf73d31f | 9928 | if (al->lkind == KIND_EXTERN) |
9929 | al->lkind = KIND_LOCAL; | |
57e47080 | 9930 | } |
9931 | else | |
9932 | { | |
9933 | /* Used here but unused assumed. */ | |
cf73d31f | 9934 | if (al->lkind == KIND_UNUSED) |
9935 | al->lkind = KIND_LOCAL; | |
57e47080 | 9936 | } |
9937 | return al->linkage; | |
9938 | } | |
9939 | } | |
9940 | else | |
8482c296 | 9941 | alpha_links_tree = splay_tree_new_ggc ((splay_tree_compare_fn) strcmp); |
8df4a58b | 9942 | |
573aba85 | 9943 | al = (struct alpha_links *) ggc_alloc (sizeof (struct alpha_links)); |
9944 | name = ggc_strdup (name); | |
8df4a58b | 9945 | |
9946 | /* Assume external if no definition. */ | |
cf73d31f | 9947 | al->lkind = (is_local ? KIND_UNUSED : KIND_EXTERN); |
8df4a58b | 9948 | |
c45d3ddf | 9949 | /* Ensure we have an IDENTIFIER so assemble_name can mark it used |
9950 | and find the ultimate alias target like assemble_name. */ | |
9951 | id = get_identifier (name); | |
9952 | target = NULL; | |
9953 | while (IDENTIFIER_TRANSPARENT_ALIAS (id)) | |
9954 | { | |
9955 | id = TREE_CHAIN (id); | |
9956 | target = IDENTIFIER_POINTER (id); | |
9957 | } | |
d2899e26 | 9958 | |
c45d3ddf | 9959 | al->target = target ? target : name; |
9960 | al->linkage = gen_rtx_SYMBOL_REF (Pmode, name); | |
57e47080 | 9961 | |
cf73d31f | 9962 | splay_tree_insert (alpha_links_tree, (splay_tree_key) name, |
57e47080 | 9963 | (splay_tree_value) al); |
8df4a58b | 9964 | |
57e47080 | 9965 | return al->linkage; |
8df4a58b | 9966 | } |
9967 | ||
c45d3ddf | 9968 | /* Return a SYMBOL_REF representing the reference to the .linkage entry |
9969 | of function FUNC built for calls made from CFUNDECL. LFLAG is 1 if | |
9970 | this is the reference to the linkage pointer value, 0 if this is the | |
9971 | reference to the function entry value. RFLAG is 1 if this a reduced | |
9972 | reference (code address only), 0 if this is a full reference. */ | |
9973 | ||
cf73d31f | 9974 | rtx |
c45d3ddf | 9975 | alpha_use_linkage (rtx func, tree cfundecl, int lflag, int rflag) |
cf73d31f | 9976 | { |
9977 | splay_tree_node cfunnode; | |
9978 | struct alpha_funcs *cfaf; | |
9979 | struct alpha_links *al; | |
c45d3ddf | 9980 | const char *name = XSTR (func, 0); |
cf73d31f | 9981 | |
9982 | cfaf = (struct alpha_funcs *) 0; | |
9983 | al = (struct alpha_links *) 0; | |
9984 | ||
9985 | cfunnode = splay_tree_lookup (alpha_funcs_tree, (splay_tree_key) cfundecl); | |
9986 | cfaf = (struct alpha_funcs *) cfunnode->value; | |
9987 | ||
9988 | if (cfaf->links) | |
9989 | { | |
9990 | splay_tree_node lnode; | |
9991 | ||
9992 | /* Is this name already defined? */ | |
9993 | ||
9994 | lnode = splay_tree_lookup (cfaf->links, (splay_tree_key) name); | |
9995 | if (lnode) | |
9996 | al = (struct alpha_links *) lnode->value; | |
9997 | } | |
9998 | else | |
9de382d9 | 9999 | cfaf->links = splay_tree_new_ggc ((splay_tree_compare_fn) strcmp); |
cf73d31f | 10000 | |
10001 | if (!al) | |
10002 | { | |
10003 | size_t name_len; | |
10004 | size_t buflen; | |
cf73d31f | 10005 | char *linksym; |
10006 | splay_tree_node node = 0; | |
10007 | struct alpha_links *anl; | |
10008 | ||
10009 | if (name[0] == '*') | |
10010 | name++; | |
10011 | ||
10012 | name_len = strlen (name); | |
c45d3ddf | 10013 | linksym = (char *) alloca (name_len + 50); |
cf73d31f | 10014 | |
9de382d9 | 10015 | al = (struct alpha_links *) ggc_alloc (sizeof (struct alpha_links)); |
cf73d31f | 10016 | al->num = cfaf->num; |
10017 | ||
10018 | node = splay_tree_lookup (alpha_links_tree, (splay_tree_key) name); | |
10019 | if (node) | |
10020 | { | |
10021 | anl = (struct alpha_links *) node->value; | |
10022 | al->lkind = anl->lkind; | |
c45d3ddf | 10023 | name = anl->target; |
cf73d31f | 10024 | } |
10025 | ||
c45d3ddf | 10026 | sprintf (linksym, "$%d..%s..lk", cfaf->num, name); |
10027 | buflen = strlen (linksym); | |
cf73d31f | 10028 | |
10029 | al->linkage = gen_rtx_SYMBOL_REF | |
10030 | (Pmode, ggc_alloc_string (linksym, buflen + 1)); | |
10031 | ||
10032 | splay_tree_insert (cfaf->links, (splay_tree_key) name, | |
10033 | (splay_tree_value) al); | |
10034 | } | |
10035 | ||
10036 | if (rflag) | |
10037 | al->rkind = KIND_CODEADDR; | |
10038 | else | |
10039 | al->rkind = KIND_LINKAGE; | |
9e7454d0 | 10040 | |
cf73d31f | 10041 | if (lflag) |
10042 | return gen_rtx_MEM (Pmode, plus_constant (al->linkage, 8)); | |
10043 | else | |
10044 | return al->linkage; | |
10045 | } | |
10046 | ||
57e47080 | 10047 | static int |
92643d95 | 10048 | alpha_write_one_linkage (splay_tree_node node, void *data) |
57e47080 | 10049 | { |
0d95286f | 10050 | const char *const name = (const char *) node->key; |
cf73d31f | 10051 | struct alpha_links *link = (struct alpha_links *) node->value; |
57e47080 | 10052 | FILE *stream = (FILE *) data; |
10053 | ||
cf73d31f | 10054 | fprintf (stream, "$%d..%s..lk:\n", link->num, name); |
10055 | if (link->rkind == KIND_CODEADDR) | |
57e47080 | 10056 | { |
cf73d31f | 10057 | if (link->lkind == KIND_LOCAL) |
10058 | { | |
10059 | /* Local and used */ | |
10060 | fprintf (stream, "\t.quad %s..en\n", name); | |
10061 | } | |
10062 | else | |
10063 | { | |
10064 | /* External and used, request code address. */ | |
10065 | fprintf (stream, "\t.code_address %s\n", name); | |
10066 | } | |
57e47080 | 10067 | } |
10068 | else | |
10069 | { | |
cf73d31f | 10070 | if (link->lkind == KIND_LOCAL) |
10071 | { | |
10072 | /* Local and used, build linkage pair. */ | |
10073 | fprintf (stream, "\t.quad %s..en\n", name); | |
10074 | fprintf (stream, "\t.quad %s\n", name); | |
10075 | } | |
10076 | else | |
10077 | { | |
10078 | /* External and used, request linkage pair. */ | |
10079 | fprintf (stream, "\t.linkage %s\n", name); | |
10080 | } | |
57e47080 | 10081 | } |
10082 | ||
10083 | return 0; | |
10084 | } | |
8df4a58b | 10085 | |
cf73d31f | 10086 | static void |
92643d95 | 10087 | alpha_write_linkage (FILE *stream, const char *funname, tree fundecl) |
8df4a58b | 10088 | { |
cf73d31f | 10089 | splay_tree_node node; |
10090 | struct alpha_funcs *func; | |
10091 | ||
2f14b1f9 | 10092 | fprintf (stream, "\t.link\n"); |
cf73d31f | 10093 | fprintf (stream, "\t.align 3\n"); |
2f14b1f9 | 10094 | in_section = NULL; |
10095 | ||
cf73d31f | 10096 | node = splay_tree_lookup (alpha_funcs_tree, (splay_tree_key) fundecl); |
10097 | func = (struct alpha_funcs *) node->value; | |
10098 | ||
10099 | fputs ("\t.name ", stream); | |
10100 | assemble_name (stream, funname); | |
10101 | fputs ("..na\n", stream); | |
10102 | ASM_OUTPUT_LABEL (stream, funname); | |
10103 | fprintf (stream, "\t.pdesc "); | |
10104 | assemble_name (stream, funname); | |
10105 | fprintf (stream, "..en,%s\n", | |
10106 | alpha_procedure_type == PT_STACK ? "stack" | |
10107 | : alpha_procedure_type == PT_REGISTER ? "reg" : "null"); | |
10108 | ||
10109 | if (func->links) | |
c64a8830 | 10110 | { |
cf73d31f | 10111 | splay_tree_foreach (func->links, alpha_write_one_linkage, stream); |
10112 | /* splay_tree_delete (func->links); */ | |
c64a8830 | 10113 | } |
8df4a58b | 10114 | } |
10115 | ||
2cb4ac60 | 10116 | /* Switch to an arbitrary section NAME with attributes as specified |
10117 | by FLAGS. ALIGN specifies any known alignment requirements for | |
10118 | the section; 0 if the default should be used. */ | |
10119 | ||
10120 | static void | |
537cd941 | 10121 | vms_asm_named_section (const char *name, unsigned int flags, |
10122 | tree decl ATTRIBUTE_UNUSED) | |
2cb4ac60 | 10123 | { |
c64a8830 | 10124 | fputc ('\n', asm_out_file); |
10125 | fprintf (asm_out_file, ".section\t%s", name); | |
2cb4ac60 | 10126 | |
c64a8830 | 10127 | if (flags & SECTION_DEBUG) |
10128 | fprintf (asm_out_file, ",NOWRT"); | |
10129 | ||
10130 | fputc ('\n', asm_out_file); | |
2cb4ac60 | 10131 | } |
10132 | ||
01d15dc5 | 10133 | /* Record an element in the table of global constructors. SYMBOL is |
10134 | a SYMBOL_REF of the function to be called; PRIORITY is a number | |
9e7454d0 | 10135 | between 0 and MAX_INIT_PRIORITY. |
01d15dc5 | 10136 | |
10137 | Differs from default_ctors_section_asm_out_constructor in that the | |
10138 | width of the .ctors entry is always 64 bits, rather than the 32 bits | |
10139 | used by a normal pointer. */ | |
10140 | ||
10141 | static void | |
92643d95 | 10142 | vms_asm_out_constructor (rtx symbol, int priority ATTRIBUTE_UNUSED) |
01d15dc5 | 10143 | { |
2f14b1f9 | 10144 | switch_to_section (ctors_section); |
09d688ff | 10145 | assemble_align (BITS_PER_WORD); |
10146 | assemble_integer (symbol, UNITS_PER_WORD, BITS_PER_WORD, 1); | |
01d15dc5 | 10147 | } |
10148 | ||
10149 | static void | |
92643d95 | 10150 | vms_asm_out_destructor (rtx symbol, int priority ATTRIBUTE_UNUSED) |
01d15dc5 | 10151 | { |
2f14b1f9 | 10152 | switch_to_section (dtors_section); |
09d688ff | 10153 | assemble_align (BITS_PER_WORD); |
10154 | assemble_integer (symbol, UNITS_PER_WORD, BITS_PER_WORD, 1); | |
01d15dc5 | 10155 | } |
8df4a58b | 10156 | #else |
10157 | ||
57e47080 | 10158 | rtx |
92643d95 | 10159 | alpha_need_linkage (const char *name ATTRIBUTE_UNUSED, |
10160 | int is_local ATTRIBUTE_UNUSED) | |
8df4a58b | 10161 | { |
57e47080 | 10162 | return NULL_RTX; |
8df4a58b | 10163 | } |
10164 | ||
cf73d31f | 10165 | rtx |
c45d3ddf | 10166 | alpha_use_linkage (rtx func ATTRIBUTE_UNUSED, |
92643d95 | 10167 | tree cfundecl ATTRIBUTE_UNUSED, |
10168 | int lflag ATTRIBUTE_UNUSED, | |
10169 | int rflag ATTRIBUTE_UNUSED) | |
cf73d31f | 10170 | { |
10171 | return NULL_RTX; | |
10172 | } | |
10173 | ||
1467e953 | 10174 | #endif /* TARGET_ABI_OPEN_VMS */ |
9caef960 | 10175 | \f |
10176 | #if TARGET_ABI_UNICOSMK | |
10177 | ||
0336f0f0 | 10178 | /* This evaluates to true if we do not know how to pass TYPE solely in |
10179 | registers. This is the case for all arguments that do not fit in two | |
10180 | registers. */ | |
10181 | ||
10182 | static bool | |
fb80456a | 10183 | unicosmk_must_pass_in_stack (enum machine_mode mode, const_tree type) |
0336f0f0 | 10184 | { |
10185 | if (type == NULL) | |
10186 | return false; | |
10187 | ||
10188 | if (TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST) | |
10189 | return true; | |
10190 | if (TREE_ADDRESSABLE (type)) | |
10191 | return true; | |
10192 | ||
10193 | return ALPHA_ARG_SIZE (mode, type, 0) > 2; | |
10194 | } | |
10195 | ||
9caef960 | 10196 | /* Define the offset between two registers, one to be eliminated, and the |
10197 | other its replacement, at the start of a routine. */ | |
10198 | ||
10199 | int | |
92643d95 | 10200 | unicosmk_initial_elimination_offset (int from, int to) |
9caef960 | 10201 | { |
10202 | int fixed_size; | |
9e7454d0 | 10203 | |
9caef960 | 10204 | fixed_size = alpha_sa_size(); |
10205 | if (fixed_size != 0) | |
10206 | fixed_size += 48; | |
10207 | ||
10208 | if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM) | |
9e7454d0 | 10209 | return -fixed_size; |
9caef960 | 10210 | else if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM) |
10211 | return 0; | |
10212 | else if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM) | |
abe32cce | 10213 | return (ALPHA_ROUND (crtl->outgoing_args_size) |
9caef960 | 10214 | + ALPHA_ROUND (get_frame_size())); |
10215 | else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM) | |
10216 | return (ALPHA_ROUND (fixed_size) | |
9e7454d0 | 10217 | + ALPHA_ROUND (get_frame_size() |
abe32cce | 10218 | + crtl->outgoing_args_size)); |
9caef960 | 10219 | else |
4d10b463 | 10220 | gcc_unreachable (); |
9caef960 | 10221 | } |
10222 | ||
10223 | /* Output the module name for .ident and .end directives. We have to strip | |
10224 | directories and add make sure that the module name starts with a letter | |
10225 | or '$'. */ | |
10226 | ||
10227 | static void | |
92643d95 | 10228 | unicosmk_output_module_name (FILE *file) |
9caef960 | 10229 | { |
8789d51c | 10230 | const char *name = lbasename (main_input_filename); |
10231 | unsigned len = strlen (name); | |
10232 | char *clean_name = alloca (len + 2); | |
10233 | char *ptr = clean_name; | |
9e7454d0 | 10234 | |
9caef960 | 10235 | /* CAM only accepts module names that start with a letter or '$'. We |
10236 | prefix the module name with a '$' if necessary. */ | |
10237 | ||
10238 | if (!ISALPHA (*name)) | |
8789d51c | 10239 | *ptr++ = '$'; |
10240 | memcpy (ptr, name, len + 1); | |
10241 | clean_symbol_name (clean_name); | |
10242 | fputs (clean_name, file); | |
9caef960 | 10243 | } |
10244 | ||
92643d95 | 10245 | /* Output the definition of a common variable. */ |
9caef960 | 10246 | |
92643d95 | 10247 | void |
10248 | unicosmk_output_common (FILE *file, const char *name, int size, int align) | |
9caef960 | 10249 | { |
92643d95 | 10250 | tree name_tree; |
10251 | printf ("T3E__: common %s\n", name); | |
9caef960 | 10252 | |
2f14b1f9 | 10253 | in_section = NULL; |
9caef960 | 10254 | fputs("\t.endp\n\n\t.psect ", file); |
10255 | assemble_name(file, name); | |
10256 | fprintf(file, ",%d,common\n", floor_log2 (align / BITS_PER_UNIT)); | |
10257 | fprintf(file, "\t.byte\t0:%d\n", size); | |
10258 | ||
10259 | /* Mark the symbol as defined in this module. */ | |
10260 | name_tree = get_identifier (name); | |
10261 | TREE_ASM_WRITTEN (name_tree) = 1; | |
10262 | } | |
10263 | ||
10264 | #define SECTION_PUBLIC SECTION_MACH_DEP | |
10265 | #define SECTION_MAIN (SECTION_PUBLIC << 1) | |
10266 | static int current_section_align; | |
10267 | ||
2f14b1f9 | 10268 | /* A get_unnamed_section callback for switching to the text section. */ |
10269 | ||
10270 | static void | |
10271 | unicosmk_output_text_section_asm_op (const void *data ATTRIBUTE_UNUSED) | |
10272 | { | |
10273 | static int count = 0; | |
10274 | fprintf (asm_out_file, "\t.endp\n\n\t.psect\tgcc@text___%d,code\n", count++); | |
10275 | } | |
10276 | ||
10277 | /* A get_unnamed_section callback for switching to the data section. */ | |
10278 | ||
10279 | static void | |
10280 | unicosmk_output_data_section_asm_op (const void *data ATTRIBUTE_UNUSED) | |
10281 | { | |
10282 | static int count = 1; | |
10283 | fprintf (asm_out_file, "\t.endp\n\n\t.psect\tgcc@data___%d,data\n", count++); | |
10284 | } | |
10285 | ||
10286 | /* Implement TARGET_ASM_INIT_SECTIONS. | |
10287 | ||
10288 | The Cray assembler is really weird with respect to sections. It has only | |
10289 | named sections and you can't reopen a section once it has been closed. | |
10290 | This means that we have to generate unique names whenever we want to | |
10291 | reenter the text or the data section. */ | |
10292 | ||
10293 | static void | |
10294 | unicosmk_init_sections (void) | |
10295 | { | |
10296 | text_section = get_unnamed_section (SECTION_CODE, | |
10297 | unicosmk_output_text_section_asm_op, | |
10298 | NULL); | |
10299 | data_section = get_unnamed_section (SECTION_WRITE, | |
10300 | unicosmk_output_data_section_asm_op, | |
10301 | NULL); | |
10302 | readonly_data_section = data_section; | |
10303 | } | |
10304 | ||
9caef960 | 10305 | static unsigned int |
92643d95 | 10306 | unicosmk_section_type_flags (tree decl, const char *name, |
10307 | int reloc ATTRIBUTE_UNUSED) | |
9caef960 | 10308 | { |
10309 | unsigned int flags = default_section_type_flags (decl, name, reloc); | |
10310 | ||
10311 | if (!decl) | |
10312 | return flags; | |
10313 | ||
10314 | if (TREE_CODE (decl) == FUNCTION_DECL) | |
10315 | { | |
10316 | current_section_align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT); | |
10317 | if (align_functions_log > current_section_align) | |
10318 | current_section_align = align_functions_log; | |
10319 | ||
10320 | if (! strcmp (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl)), "main")) | |
10321 | flags |= SECTION_MAIN; | |
10322 | } | |
10323 | else | |
10324 | current_section_align = floor_log2 (DECL_ALIGN (decl) / BITS_PER_UNIT); | |
10325 | ||
10326 | if (TREE_PUBLIC (decl)) | |
10327 | flags |= SECTION_PUBLIC; | |
10328 | ||
10329 | return flags; | |
10330 | } | |
10331 | ||
10332 | /* Generate a section name for decl and associate it with the | |
10333 | declaration. */ | |
10334 | ||
52470889 | 10335 | static void |
92643d95 | 10336 | unicosmk_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED) |
9caef960 | 10337 | { |
10338 | const char *name; | |
10339 | int len; | |
10340 | ||
4d10b463 | 10341 | gcc_assert (decl); |
9caef960 | 10342 | |
10343 | name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl)); | |
09a1f342 | 10344 | name = default_strip_name_encoding (name); |
9caef960 | 10345 | len = strlen (name); |
10346 | ||
10347 | if (TREE_CODE (decl) == FUNCTION_DECL) | |
10348 | { | |
10349 | char *string; | |
10350 | ||
9e7454d0 | 10351 | /* It is essential that we prefix the section name here because |
10352 | otherwise the section names generated for constructors and | |
9caef960 | 10353 | destructors confuse collect2. */ |
10354 | ||
10355 | string = alloca (len + 6); | |
10356 | sprintf (string, "code@%s", name); | |
10357 | DECL_SECTION_NAME (decl) = build_string (len + 5, string); | |
10358 | } | |
10359 | else if (TREE_PUBLIC (decl)) | |
10360 | DECL_SECTION_NAME (decl) = build_string (len, name); | |
10361 | else | |
10362 | { | |
10363 | char *string; | |
10364 | ||
10365 | string = alloca (len + 6); | |
10366 | sprintf (string, "data@%s", name); | |
10367 | DECL_SECTION_NAME (decl) = build_string (len + 5, string); | |
10368 | } | |
10369 | } | |
10370 | ||
10371 | /* Switch to an arbitrary section NAME with attributes as specified | |
10372 | by FLAGS. ALIGN specifies any known alignment requirements for | |
10373 | the section; 0 if the default should be used. */ | |
10374 | ||
10375 | static void | |
537cd941 | 10376 | unicosmk_asm_named_section (const char *name, unsigned int flags, |
10377 | tree decl ATTRIBUTE_UNUSED) | |
9caef960 | 10378 | { |
10379 | const char *kind; | |
10380 | ||
10381 | /* Close the previous section. */ | |
10382 | ||
10383 | fputs ("\t.endp\n\n", asm_out_file); | |
10384 | ||
10385 | /* Find out what kind of section we are opening. */ | |
10386 | ||
10387 | if (flags & SECTION_MAIN) | |
10388 | fputs ("\t.start\tmain\n", asm_out_file); | |
10389 | ||
10390 | if (flags & SECTION_CODE) | |
10391 | kind = "code"; | |
10392 | else if (flags & SECTION_PUBLIC) | |
10393 | kind = "common"; | |
10394 | else | |
10395 | kind = "data"; | |
10396 | ||
10397 | if (current_section_align != 0) | |
10398 | fprintf (asm_out_file, "\t.psect\t%s,%d,%s\n", name, | |
10399 | current_section_align, kind); | |
10400 | else | |
10401 | fprintf (asm_out_file, "\t.psect\t%s,%s\n", name, kind); | |
10402 | } | |
10403 | ||
10404 | static void | |
92643d95 | 10405 | unicosmk_insert_attributes (tree decl, tree *attr_ptr ATTRIBUTE_UNUSED) |
9caef960 | 10406 | { |
10407 | if (DECL_P (decl) | |
10408 | && (TREE_PUBLIC (decl) || TREE_CODE (decl) == FUNCTION_DECL)) | |
52470889 | 10409 | unicosmk_unique_section (decl, 0); |
9caef960 | 10410 | } |
10411 | ||
10412 | /* Output an alignment directive. We have to use the macro 'gcc@code@align' | |
10413 | in code sections because .align fill unused space with zeroes. */ | |
9e7454d0 | 10414 | |
9caef960 | 10415 | void |
92643d95 | 10416 | unicosmk_output_align (FILE *file, int align) |
9caef960 | 10417 | { |
10418 | if (inside_function) | |
10419 | fprintf (file, "\tgcc@code@align\t%d\n", align); | |
10420 | else | |
10421 | fprintf (file, "\t.align\t%d\n", align); | |
10422 | } | |
10423 | ||
10424 | /* Add a case vector to the current function's list of deferred case | |
10425 | vectors. Case vectors have to be put into a separate section because CAM | |
10426 | does not allow data definitions in code sections. */ | |
10427 | ||
10428 | void | |
92643d95 | 10429 | unicosmk_defer_case_vector (rtx lab, rtx vec) |
9caef960 | 10430 | { |
10431 | struct machine_function *machine = cfun->machine; | |
9e7454d0 | 10432 | |
9caef960 | 10433 | vec = gen_rtx_EXPR_LIST (VOIDmode, lab, vec); |
10434 | machine->addr_list = gen_rtx_EXPR_LIST (VOIDmode, vec, | |
9e7454d0 | 10435 | machine->addr_list); |
9caef960 | 10436 | } |
10437 | ||
10438 | /* Output a case vector. */ | |
10439 | ||
10440 | static void | |
92643d95 | 10441 | unicosmk_output_addr_vec (FILE *file, rtx vec) |
9caef960 | 10442 | { |
10443 | rtx lab = XEXP (vec, 0); | |
10444 | rtx body = XEXP (vec, 1); | |
10445 | int vlen = XVECLEN (body, 0); | |
10446 | int idx; | |
10447 | ||
805e22b2 | 10448 | (*targetm.asm_out.internal_label) (file, "L", CODE_LABEL_NUMBER (lab)); |
9caef960 | 10449 | |
10450 | for (idx = 0; idx < vlen; idx++) | |
10451 | { | |
10452 | ASM_OUTPUT_ADDR_VEC_ELT | |
10453 | (file, CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 0, idx), 0))); | |
10454 | } | |
10455 | } | |
10456 | ||
10457 | /* Output current function's deferred case vectors. */ | |
10458 | ||
10459 | static void | |
92643d95 | 10460 | unicosmk_output_deferred_case_vectors (FILE *file) |
9caef960 | 10461 | { |
10462 | struct machine_function *machine = cfun->machine; | |
10463 | rtx t; | |
10464 | ||
10465 | if (machine->addr_list == NULL_RTX) | |
10466 | return; | |
10467 | ||
2f14b1f9 | 10468 | switch_to_section (data_section); |
9caef960 | 10469 | for (t = machine->addr_list; t; t = XEXP (t, 1)) |
10470 | unicosmk_output_addr_vec (file, XEXP (t, 0)); | |
10471 | } | |
10472 | ||
92643d95 | 10473 | /* Generate the name of the SSIB section for the current function. */ |
10474 | ||
10475 | #define SSIB_PREFIX "__SSIB_" | |
10476 | #define SSIB_PREFIX_LEN 7 | |
10477 | ||
10478 | static const char * | |
10479 | unicosmk_ssib_name (void) | |
10480 | { | |
9e7454d0 | 10481 | /* This is ok since CAM won't be able to deal with names longer than that |
92643d95 | 10482 | anyway. */ |
10483 | ||
10484 | static char name[256]; | |
10485 | ||
10486 | rtx x; | |
10487 | const char *fnname; | |
10488 | int len; | |
10489 | ||
10490 | x = DECL_RTL (cfun->decl); | |
c933fb42 | 10491 | gcc_assert (MEM_P (x)); |
92643d95 | 10492 | x = XEXP (x, 0); |
4d10b463 | 10493 | gcc_assert (GET_CODE (x) == SYMBOL_REF); |
92643d95 | 10494 | fnname = XSTR (x, 0); |
10495 | ||
10496 | len = strlen (fnname); | |
10497 | if (len + SSIB_PREFIX_LEN > 255) | |
10498 | len = 255 - SSIB_PREFIX_LEN; | |
10499 | ||
10500 | strcpy (name, SSIB_PREFIX); | |
10501 | strncpy (name + SSIB_PREFIX_LEN, fnname, len); | |
10502 | name[len + SSIB_PREFIX_LEN] = 0; | |
10503 | ||
10504 | return name; | |
10505 | } | |
10506 | ||
9e7454d0 | 10507 | /* Set up the dynamic subprogram information block (DSIB) and update the |
10508 | frame pointer register ($15) for subroutines which have a frame. If the | |
9caef960 | 10509 | subroutine doesn't have a frame, simply increment $15. */ |
10510 | ||
10511 | static void | |
92643d95 | 10512 | unicosmk_gen_dsib (unsigned long *imaskP) |
9caef960 | 10513 | { |
b19d7ab1 | 10514 | if (alpha_procedure_type == PT_STACK) |
9caef960 | 10515 | { |
10516 | const char *ssib_name; | |
10517 | rtx mem; | |
10518 | ||
10519 | /* Allocate 64 bytes for the DSIB. */ | |
10520 | ||
10521 | FRP (emit_insn (gen_adddi3 (stack_pointer_rtx, stack_pointer_rtx, | |
10522 | GEN_INT (-64)))); | |
10523 | emit_insn (gen_blockage ()); | |
10524 | ||
10525 | /* Save the return address. */ | |
10526 | ||
10527 | mem = gen_rtx_MEM (DImode, plus_constant (stack_pointer_rtx, 56)); | |
10528 | set_mem_alias_set (mem, alpha_sr_alias_set); | |
10529 | FRP (emit_move_insn (mem, gen_rtx_REG (DImode, REG_RA))); | |
df7d0d23 | 10530 | (*imaskP) &= ~(1UL << REG_RA); |
9caef960 | 10531 | |
10532 | /* Save the old frame pointer. */ | |
10533 | ||
10534 | mem = gen_rtx_MEM (DImode, plus_constant (stack_pointer_rtx, 48)); | |
10535 | set_mem_alias_set (mem, alpha_sr_alias_set); | |
10536 | FRP (emit_move_insn (mem, hard_frame_pointer_rtx)); | |
df7d0d23 | 10537 | (*imaskP) &= ~(1UL << HARD_FRAME_POINTER_REGNUM); |
9caef960 | 10538 | |
10539 | emit_insn (gen_blockage ()); | |
10540 | ||
10541 | /* Store the SSIB pointer. */ | |
10542 | ||
10543 | ssib_name = ggc_strdup (unicosmk_ssib_name ()); | |
10544 | mem = gen_rtx_MEM (DImode, plus_constant (stack_pointer_rtx, 32)); | |
10545 | set_mem_alias_set (mem, alpha_sr_alias_set); | |
10546 | ||
10547 | FRP (emit_move_insn (gen_rtx_REG (DImode, 5), | |
10548 | gen_rtx_SYMBOL_REF (Pmode, ssib_name))); | |
10549 | FRP (emit_move_insn (mem, gen_rtx_REG (DImode, 5))); | |
10550 | ||
10551 | /* Save the CIW index. */ | |
10552 | ||
10553 | mem = gen_rtx_MEM (DImode, plus_constant (stack_pointer_rtx, 24)); | |
10554 | set_mem_alias_set (mem, alpha_sr_alias_set); | |
10555 | FRP (emit_move_insn (mem, gen_rtx_REG (DImode, 25))); | |
10556 | ||
10557 | emit_insn (gen_blockage ()); | |
10558 | ||
10559 | /* Set the new frame pointer. */ | |
9caef960 | 10560 | FRP (emit_insn (gen_adddi3 (hard_frame_pointer_rtx, |
10561 | stack_pointer_rtx, GEN_INT (64)))); | |
9caef960 | 10562 | } |
10563 | else | |
10564 | { | |
10565 | /* Increment the frame pointer register to indicate that we do not | |
10566 | have a frame. */ | |
d30e4246 | 10567 | emit_insn (gen_adddi3 (hard_frame_pointer_rtx, |
10568 | hard_frame_pointer_rtx, const1_rtx)); | |
9caef960 | 10569 | } |
10570 | } | |
10571 | ||
9caef960 | 10572 | /* Output the static subroutine information block for the current |
10573 | function. */ | |
10574 | ||
10575 | static void | |
92643d95 | 10576 | unicosmk_output_ssib (FILE *file, const char *fnname) |
9caef960 | 10577 | { |
10578 | int len; | |
10579 | int i; | |
10580 | rtx x; | |
10581 | rtx ciw; | |
10582 | struct machine_function *machine = cfun->machine; | |
10583 | ||
2f14b1f9 | 10584 | in_section = NULL; |
9caef960 | 10585 | fprintf (file, "\t.endp\n\n\t.psect\t%s%s,data\n", user_label_prefix, |
10586 | unicosmk_ssib_name ()); | |
10587 | ||
10588 | /* Some required stuff and the function name length. */ | |
10589 | ||
10590 | len = strlen (fnname); | |
10591 | fprintf (file, "\t.quad\t^X20008%2.2X28\n", len); | |
10592 | ||
10593 | /* Saved registers | |
10594 | ??? We don't do that yet. */ | |
10595 | ||
10596 | fputs ("\t.quad\t0\n", file); | |
10597 | ||
10598 | /* Function address. */ | |
10599 | ||
10600 | fputs ("\t.quad\t", file); | |
10601 | assemble_name (file, fnname); | |
10602 | putc ('\n', file); | |
10603 | ||
10604 | fputs ("\t.quad\t0\n", file); | |
10605 | fputs ("\t.quad\t0\n", file); | |
10606 | ||
10607 | /* Function name. | |
10608 | ??? We do it the same way Cray CC does it but this could be | |
10609 | simplified. */ | |
10610 | ||
10611 | for( i = 0; i < len; i++ ) | |
10612 | fprintf (file, "\t.byte\t%d\n", (int)(fnname[i])); | |
10613 | if( (len % 8) == 0 ) | |
10614 | fputs ("\t.quad\t0\n", file); | |
10615 | else | |
10616 | fprintf (file, "\t.bits\t%d : 0\n", (8 - (len % 8))*8); | |
10617 | ||
10618 | /* All call information words used in the function. */ | |
10619 | ||
10620 | for (x = machine->first_ciw; x; x = XEXP (x, 1)) | |
10621 | { | |
10622 | ciw = XEXP (x, 0); | |
9caef960 | 10623 | #if HOST_BITS_PER_WIDE_INT == 32 |
4840a03a | 10624 | fprintf (file, "\t.quad\t" HOST_WIDE_INT_PRINT_DOUBLE_HEX "\n", |
9caef960 | 10625 | CONST_DOUBLE_HIGH (ciw), CONST_DOUBLE_LOW (ciw)); |
10626 | #else | |
4840a03a | 10627 | fprintf (file, "\t.quad\t" HOST_WIDE_INT_PRINT_HEX "\n", INTVAL (ciw)); |
9caef960 | 10628 | #endif |
9caef960 | 10629 | } |
10630 | } | |
10631 | ||
10632 | /* Add a call information word (CIW) to the list of the current function's | |
10633 | CIWs and return its index. | |
10634 | ||
10635 | X is a CONST_INT or CONST_DOUBLE representing the CIW. */ | |
10636 | ||
10637 | rtx | |
92643d95 | 10638 | unicosmk_add_call_info_word (rtx x) |
9caef960 | 10639 | { |
10640 | rtx node; | |
10641 | struct machine_function *machine = cfun->machine; | |
10642 | ||
10643 | node = gen_rtx_EXPR_LIST (VOIDmode, x, NULL_RTX); | |
10644 | if (machine->first_ciw == NULL_RTX) | |
10645 | machine->first_ciw = node; | |
10646 | else | |
10647 | XEXP (machine->last_ciw, 1) = node; | |
10648 | ||
10649 | machine->last_ciw = node; | |
10650 | ++machine->ciw_count; | |
10651 | ||
10652 | return GEN_INT (machine->ciw_count | |
35901471 | 10653 | + strlen (current_function_name ())/8 + 5); |
9caef960 | 10654 | } |
10655 | ||
9caef960 | 10656 | /* The Cray assembler doesn't accept extern declarations for symbols which |
10657 | are defined in the same file. We have to keep track of all global | |
10658 | symbols which are referenced and/or defined in a source file and output | |
10659 | extern declarations for those which are referenced but not defined at | |
10660 | the end of file. */ | |
10661 | ||
10662 | /* List of identifiers for which an extern declaration might have to be | |
10663 | emitted. */ | |
9de382d9 | 10664 | /* FIXME: needs to use GC, so it can be saved and restored for PCH. */ |
9caef960 | 10665 | |
10666 | struct unicosmk_extern_list | |
10667 | { | |
10668 | struct unicosmk_extern_list *next; | |
10669 | const char *name; | |
10670 | }; | |
10671 | ||
10672 | static struct unicosmk_extern_list *unicosmk_extern_head = 0; | |
10673 | ||
10674 | /* Output extern declarations which are required for every asm file. */ | |
10675 | ||
10676 | static void | |
92643d95 | 10677 | unicosmk_output_default_externs (FILE *file) |
9caef960 | 10678 | { |
0d95286f | 10679 | static const char *const externs[] = |
9caef960 | 10680 | { "__T3E_MISMATCH" }; |
10681 | ||
10682 | int i; | |
10683 | int n; | |
10684 | ||
10685 | n = ARRAY_SIZE (externs); | |
10686 | ||
10687 | for (i = 0; i < n; i++) | |
10688 | fprintf (file, "\t.extern\t%s\n", externs[i]); | |
10689 | } | |
10690 | ||
10691 | /* Output extern declarations for global symbols which are have been | |
10692 | referenced but not defined. */ | |
10693 | ||
10694 | static void | |
92643d95 | 10695 | unicosmk_output_externs (FILE *file) |
9caef960 | 10696 | { |
10697 | struct unicosmk_extern_list *p; | |
10698 | const char *real_name; | |
10699 | int len; | |
10700 | tree name_tree; | |
10701 | ||
10702 | len = strlen (user_label_prefix); | |
10703 | for (p = unicosmk_extern_head; p != 0; p = p->next) | |
10704 | { | |
9e7454d0 | 10705 | /* We have to strip the encoding and possibly remove user_label_prefix |
9caef960 | 10706 | from the identifier in order to handle -fleading-underscore and |
10707 | explicit asm names correctly (cf. gcc.dg/asm-names-1.c). */ | |
09a1f342 | 10708 | real_name = default_strip_name_encoding (p->name); |
9caef960 | 10709 | if (len && p->name[0] == '*' |
10710 | && !memcmp (real_name, user_label_prefix, len)) | |
10711 | real_name += len; | |
9e7454d0 | 10712 | |
9caef960 | 10713 | name_tree = get_identifier (real_name); |
10714 | if (! TREE_ASM_WRITTEN (name_tree)) | |
10715 | { | |
10716 | TREE_ASM_WRITTEN (name_tree) = 1; | |
10717 | fputs ("\t.extern\t", file); | |
10718 | assemble_name (file, p->name); | |
10719 | putc ('\n', file); | |
10720 | } | |
10721 | } | |
10722 | } | |
9e7454d0 | 10723 | |
9caef960 | 10724 | /* Record an extern. */ |
10725 | ||
10726 | void | |
92643d95 | 10727 | unicosmk_add_extern (const char *name) |
9caef960 | 10728 | { |
10729 | struct unicosmk_extern_list *p; | |
10730 | ||
10731 | p = (struct unicosmk_extern_list *) | |
92192583 | 10732 | xmalloc (sizeof (struct unicosmk_extern_list)); |
9caef960 | 10733 | p->next = unicosmk_extern_head; |
10734 | p->name = name; | |
10735 | unicosmk_extern_head = p; | |
10736 | } | |
10737 | ||
10738 | /* The Cray assembler generates incorrect code if identifiers which | |
10739 | conflict with register names are used as instruction operands. We have | |
10740 | to replace such identifiers with DEX expressions. */ | |
10741 | ||
10742 | /* Structure to collect identifiers which have been replaced by DEX | |
10743 | expressions. */ | |
9de382d9 | 10744 | /* FIXME: needs to use GC, so it can be saved and restored for PCH. */ |
9caef960 | 10745 | |
10746 | struct unicosmk_dex { | |
10747 | struct unicosmk_dex *next; | |
10748 | const char *name; | |
10749 | }; | |
10750 | ||
9e7454d0 | 10751 | /* List of identifiers which have been replaced by DEX expressions. The DEX |
9caef960 | 10752 | number is determined by the position in the list. */ |
10753 | ||
9e7454d0 | 10754 | static struct unicosmk_dex *unicosmk_dex_list = NULL; |
9caef960 | 10755 | |
10756 | /* The number of elements in the DEX list. */ | |
10757 | ||
10758 | static int unicosmk_dex_count = 0; | |
10759 | ||
10760 | /* Check if NAME must be replaced by a DEX expression. */ | |
10761 | ||
10762 | static int | |
92643d95 | 10763 | unicosmk_special_name (const char *name) |
9caef960 | 10764 | { |
10765 | if (name[0] == '*') | |
10766 | ++name; | |
10767 | ||
10768 | if (name[0] == '$') | |
10769 | ++name; | |
10770 | ||
10771 | if (name[0] != 'r' && name[0] != 'f' && name[0] != 'R' && name[0] != 'F') | |
10772 | return 0; | |
10773 | ||
10774 | switch (name[1]) | |
10775 | { | |
10776 | case '1': case '2': | |
10777 | return (name[2] == '\0' || (ISDIGIT (name[2]) && name[3] == '\0')); | |
10778 | ||
10779 | case '3': | |
10780 | return (name[2] == '\0' | |
10781 | || ((name[2] == '0' || name[2] == '1') && name[3] == '\0')); | |
10782 | ||
10783 | default: | |
10784 | return (ISDIGIT (name[1]) && name[2] == '\0'); | |
10785 | } | |
10786 | } | |
10787 | ||
10788 | /* Return the DEX number if X must be replaced by a DEX expression and 0 | |
10789 | otherwise. */ | |
10790 | ||
10791 | static int | |
92643d95 | 10792 | unicosmk_need_dex (rtx x) |
9caef960 | 10793 | { |
10794 | struct unicosmk_dex *dex; | |
10795 | const char *name; | |
10796 | int i; | |
9e7454d0 | 10797 | |
9caef960 | 10798 | if (GET_CODE (x) != SYMBOL_REF) |
10799 | return 0; | |
10800 | ||
10801 | name = XSTR (x,0); | |
10802 | if (! unicosmk_special_name (name)) | |
10803 | return 0; | |
10804 | ||
10805 | i = unicosmk_dex_count; | |
10806 | for (dex = unicosmk_dex_list; dex; dex = dex->next) | |
10807 | { | |
10808 | if (! strcmp (name, dex->name)) | |
10809 | return i; | |
10810 | --i; | |
10811 | } | |
9e7454d0 | 10812 | |
92192583 | 10813 | dex = (struct unicosmk_dex *) xmalloc (sizeof (struct unicosmk_dex)); |
9caef960 | 10814 | dex->name = name; |
10815 | dex->next = unicosmk_dex_list; | |
10816 | unicosmk_dex_list = dex; | |
10817 | ||
10818 | ++unicosmk_dex_count; | |
10819 | return unicosmk_dex_count; | |
10820 | } | |
10821 | ||
10822 | /* Output the DEX definitions for this file. */ | |
10823 | ||
10824 | static void | |
92643d95 | 10825 | unicosmk_output_dex (FILE *file) |
9caef960 | 10826 | { |
10827 | struct unicosmk_dex *dex; | |
10828 | int i; | |
10829 | ||
10830 | if (unicosmk_dex_list == NULL) | |
10831 | return; | |
10832 | ||
10833 | fprintf (file, "\t.dexstart\n"); | |
10834 | ||
10835 | i = unicosmk_dex_count; | |
10836 | for (dex = unicosmk_dex_list; dex; dex = dex->next) | |
10837 | { | |
10838 | fprintf (file, "\tDEX (%d) = ", i); | |
10839 | assemble_name (file, dex->name); | |
10840 | putc ('\n', file); | |
10841 | --i; | |
10842 | } | |
9e7454d0 | 10843 | |
9caef960 | 10844 | fprintf (file, "\t.dexend\n"); |
10845 | } | |
10846 | ||
92643d95 | 10847 | /* Output text that to appear at the beginning of an assembler file. */ |
10848 | ||
9e7454d0 | 10849 | static void |
92c473b8 | 10850 | unicosmk_file_start (void) |
92643d95 | 10851 | { |
10852 | int i; | |
10853 | ||
92c473b8 | 10854 | fputs ("\t.ident\t", asm_out_file); |
10855 | unicosmk_output_module_name (asm_out_file); | |
10856 | fputs ("\n\n", asm_out_file); | |
92643d95 | 10857 | |
10858 | /* The Unicos/Mk assembler uses different register names. Instead of trying | |
10859 | to support them, we simply use micro definitions. */ | |
10860 | ||
10861 | /* CAM has different register names: rN for the integer register N and fN | |
10862 | for the floating-point register N. Instead of trying to use these in | |
10863 | alpha.md, we define the symbols $N and $fN to refer to the appropriate | |
10864 | register. */ | |
10865 | ||
10866 | for (i = 0; i < 32; ++i) | |
92c473b8 | 10867 | fprintf (asm_out_file, "$%d <- r%d\n", i, i); |
92643d95 | 10868 | |
10869 | for (i = 0; i < 32; ++i) | |
92c473b8 | 10870 | fprintf (asm_out_file, "$f%d <- f%d\n", i, i); |
92643d95 | 10871 | |
92c473b8 | 10872 | putc ('\n', asm_out_file); |
92643d95 | 10873 | |
10874 | /* The .align directive fill unused space with zeroes which does not work | |
10875 | in code sections. We define the macro 'gcc@code@align' which uses nops | |
10876 | instead. Note that it assumes that code sections always have the | |
10877 | biggest possible alignment since . refers to the current offset from | |
10878 | the beginning of the section. */ | |
10879 | ||
92c473b8 | 10880 | fputs ("\t.macro gcc@code@align n\n", asm_out_file); |
10881 | fputs ("gcc@n@bytes = 1 << n\n", asm_out_file); | |
10882 | fputs ("gcc@here = . % gcc@n@bytes\n", asm_out_file); | |
10883 | fputs ("\t.if ne, gcc@here, 0\n", asm_out_file); | |
10884 | fputs ("\t.repeat (gcc@n@bytes - gcc@here) / 4\n", asm_out_file); | |
10885 | fputs ("\tbis r31,r31,r31\n", asm_out_file); | |
10886 | fputs ("\t.endr\n", asm_out_file); | |
10887 | fputs ("\t.endif\n", asm_out_file); | |
10888 | fputs ("\t.endm gcc@code@align\n\n", asm_out_file); | |
92643d95 | 10889 | |
10890 | /* Output extern declarations which should always be visible. */ | |
92c473b8 | 10891 | unicosmk_output_default_externs (asm_out_file); |
92643d95 | 10892 | |
10893 | /* Open a dummy section. We always need to be inside a section for the | |
10894 | section-switching code to work correctly. | |
10895 | ??? This should be a module id or something like that. I still have to | |
10896 | figure out what the rules for those are. */ | |
92c473b8 | 10897 | fputs ("\n\t.psect\t$SG00000,data\n", asm_out_file); |
92643d95 | 10898 | } |
10899 | ||
10900 | /* Output text to appear at the end of an assembler file. This includes all | |
10901 | pending extern declarations and DEX expressions. */ | |
10902 | ||
10903 | static void | |
10904 | unicosmk_file_end (void) | |
10905 | { | |
10906 | fputs ("\t.endp\n\n", asm_out_file); | |
10907 | ||
10908 | /* Output all pending externs. */ | |
10909 | ||
10910 | unicosmk_output_externs (asm_out_file); | |
10911 | ||
9e7454d0 | 10912 | /* Output dex definitions used for functions whose names conflict with |
92643d95 | 10913 | register names. */ |
10914 | ||
10915 | unicosmk_output_dex (asm_out_file); | |
10916 | ||
10917 | fputs ("\t.end\t", asm_out_file); | |
10918 | unicosmk_output_module_name (asm_out_file); | |
10919 | putc ('\n', asm_out_file); | |
10920 | } | |
10921 | ||
9caef960 | 10922 | #else |
10923 | ||
10924 | static void | |
92643d95 | 10925 | unicosmk_output_deferred_case_vectors (FILE *file ATTRIBUTE_UNUSED) |
9caef960 | 10926 | {} |
10927 | ||
10928 | static void | |
92643d95 | 10929 | unicosmk_gen_dsib (unsigned long *imaskP ATTRIBUTE_UNUSED) |
9caef960 | 10930 | {} |
10931 | ||
10932 | static void | |
92643d95 | 10933 | unicosmk_output_ssib (FILE * file ATTRIBUTE_UNUSED, |
10934 | const char * fnname ATTRIBUTE_UNUSED) | |
9caef960 | 10935 | {} |
10936 | ||
10937 | rtx | |
92643d95 | 10938 | unicosmk_add_call_info_word (rtx x ATTRIBUTE_UNUSED) |
9caef960 | 10939 | { |
10940 | return NULL_RTX; | |
10941 | } | |
10942 | ||
10943 | static int | |
92643d95 | 10944 | unicosmk_need_dex (rtx x ATTRIBUTE_UNUSED) |
9caef960 | 10945 | { |
10946 | return 0; | |
10947 | } | |
10948 | ||
10949 | #endif /* TARGET_ABI_UNICOSMK */ | |
1f3233d1 | 10950 | |
f2f543a3 | 10951 | static void |
10952 | alpha_init_libfuncs (void) | |
10953 | { | |
10954 | if (TARGET_ABI_UNICOSMK) | |
10955 | { | |
10956 | /* Prevent gcc from generating calls to __divsi3. */ | |
10957 | set_optab_libfunc (sdiv_optab, SImode, 0); | |
10958 | set_optab_libfunc (udiv_optab, SImode, 0); | |
10959 | ||
10960 | /* Use the functions provided by the system library | |
10961 | for DImode integer division. */ | |
10962 | set_optab_libfunc (sdiv_optab, DImode, "$sldiv"); | |
10963 | set_optab_libfunc (udiv_optab, DImode, "$uldiv"); | |
10964 | } | |
10965 | else if (TARGET_ABI_OPEN_VMS) | |
10966 | { | |
10967 | /* Use the VMS runtime library functions for division and | |
10968 | remainder. */ | |
10969 | set_optab_libfunc (sdiv_optab, SImode, "OTS$DIV_I"); | |
10970 | set_optab_libfunc (sdiv_optab, DImode, "OTS$DIV_L"); | |
10971 | set_optab_libfunc (udiv_optab, SImode, "OTS$DIV_UI"); | |
10972 | set_optab_libfunc (udiv_optab, DImode, "OTS$DIV_UL"); | |
10973 | set_optab_libfunc (smod_optab, SImode, "OTS$REM_I"); | |
10974 | set_optab_libfunc (smod_optab, DImode, "OTS$REM_L"); | |
10975 | set_optab_libfunc (umod_optab, SImode, "OTS$REM_UI"); | |
10976 | set_optab_libfunc (umod_optab, DImode, "OTS$REM_UL"); | |
2db66e7c | 10977 | abort_libfunc = init_one_libfunc ("decc$abort"); |
10978 | memcmp_libfunc = init_one_libfunc ("decc$memcmp"); | |
10979 | #ifdef MEM_LIBFUNCS_INIT | |
10980 | MEM_LIBFUNCS_INIT; | |
10981 | #endif | |
f2f543a3 | 10982 | } |
10983 | } | |
10984 | ||
92643d95 | 10985 | \f |
10986 | /* Initialize the GCC target structure. */ | |
10987 | #if TARGET_ABI_OPEN_VMS | |
10988 | # undef TARGET_ATTRIBUTE_TABLE | |
10989 | # define TARGET_ATTRIBUTE_TABLE vms_attribute_table | |
cd90919d | 10990 | # undef TARGET_CAN_ELIMINATE |
10991 | # define TARGET_CAN_ELIMINATE alpha_vms_can_eliminate | |
92643d95 | 10992 | #endif |
10993 | ||
10994 | #undef TARGET_IN_SMALL_DATA_P | |
10995 | #define TARGET_IN_SMALL_DATA_P alpha_in_small_data_p | |
10996 | ||
10997 | #if TARGET_ABI_UNICOSMK | |
10998 | # undef TARGET_INSERT_ATTRIBUTES | |
10999 | # define TARGET_INSERT_ATTRIBUTES unicosmk_insert_attributes | |
11000 | # undef TARGET_SECTION_TYPE_FLAGS | |
11001 | # define TARGET_SECTION_TYPE_FLAGS unicosmk_section_type_flags | |
11002 | # undef TARGET_ASM_UNIQUE_SECTION | |
11003 | # define TARGET_ASM_UNIQUE_SECTION unicosmk_unique_section | |
76aec42f | 11004 | #undef TARGET_ASM_FUNCTION_RODATA_SECTION |
11005 | #define TARGET_ASM_FUNCTION_RODATA_SECTION default_no_function_rodata_section | |
92643d95 | 11006 | # undef TARGET_ASM_GLOBALIZE_LABEL |
11007 | # define TARGET_ASM_GLOBALIZE_LABEL hook_void_FILEptr_constcharptr | |
0336f0f0 | 11008 | # undef TARGET_MUST_PASS_IN_STACK |
11009 | # define TARGET_MUST_PASS_IN_STACK unicosmk_must_pass_in_stack | |
92643d95 | 11010 | #endif |
11011 | ||
11012 | #undef TARGET_ASM_ALIGNED_HI_OP | |
11013 | #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t" | |
11014 | #undef TARGET_ASM_ALIGNED_DI_OP | |
11015 | #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t" | |
11016 | ||
11017 | /* Default unaligned ops are provided for ELF systems. To get unaligned | |
11018 | data for non-ELF systems, we have to turn off auto alignment. */ | |
0dbcfe49 | 11019 | #if !defined (OBJECT_FORMAT_ELF) || TARGET_ABI_OPEN_VMS |
92643d95 | 11020 | #undef TARGET_ASM_UNALIGNED_HI_OP |
11021 | #define TARGET_ASM_UNALIGNED_HI_OP "\t.align 0\n\t.word\t" | |
11022 | #undef TARGET_ASM_UNALIGNED_SI_OP | |
11023 | #define TARGET_ASM_UNALIGNED_SI_OP "\t.align 0\n\t.long\t" | |
11024 | #undef TARGET_ASM_UNALIGNED_DI_OP | |
11025 | #define TARGET_ASM_UNALIGNED_DI_OP "\t.align 0\n\t.quad\t" | |
11026 | #endif | |
11027 | ||
11028 | #ifdef OBJECT_FORMAT_ELF | |
4e151b05 | 11029 | #undef TARGET_ASM_RELOC_RW_MASK |
11030 | #define TARGET_ASM_RELOC_RW_MASK alpha_elf_reloc_rw_mask | |
92643d95 | 11031 | #undef TARGET_ASM_SELECT_RTX_SECTION |
11032 | #define TARGET_ASM_SELECT_RTX_SECTION alpha_elf_select_rtx_section | |
cc2af183 | 11033 | #undef TARGET_SECTION_TYPE_FLAGS |
11034 | #define TARGET_SECTION_TYPE_FLAGS alpha_elf_section_type_flags | |
92643d95 | 11035 | #endif |
11036 | ||
11037 | #undef TARGET_ASM_FUNCTION_END_PROLOGUE | |
11038 | #define TARGET_ASM_FUNCTION_END_PROLOGUE alpha_output_function_end_prologue | |
11039 | ||
f2f543a3 | 11040 | #undef TARGET_INIT_LIBFUNCS |
11041 | #define TARGET_INIT_LIBFUNCS alpha_init_libfuncs | |
11042 | ||
41e3a0c7 | 11043 | #undef TARGET_LEGITIMIZE_ADDRESS |
11044 | #define TARGET_LEGITIMIZE_ADDRESS alpha_legitimize_address | |
11045 | ||
92c473b8 | 11046 | #if TARGET_ABI_UNICOSMK |
11047 | #undef TARGET_ASM_FILE_START | |
11048 | #define TARGET_ASM_FILE_START unicosmk_file_start | |
11049 | #undef TARGET_ASM_FILE_END | |
11050 | #define TARGET_ASM_FILE_END unicosmk_file_end | |
11051 | #else | |
11052 | #undef TARGET_ASM_FILE_START | |
11053 | #define TARGET_ASM_FILE_START alpha_file_start | |
11054 | #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE | |
11055 | #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true | |
11056 | #endif | |
11057 | ||
92643d95 | 11058 | #undef TARGET_SCHED_ADJUST_COST |
11059 | #define TARGET_SCHED_ADJUST_COST alpha_adjust_cost | |
11060 | #undef TARGET_SCHED_ISSUE_RATE | |
11061 | #define TARGET_SCHED_ISSUE_RATE alpha_issue_rate | |
92643d95 | 11062 | #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD |
11063 | #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \ | |
11064 | alpha_multipass_dfa_lookahead | |
11065 | ||
11066 | #undef TARGET_HAVE_TLS | |
11067 | #define TARGET_HAVE_TLS HAVE_AS_TLS | |
11068 | ||
11069 | #undef TARGET_INIT_BUILTINS | |
11070 | #define TARGET_INIT_BUILTINS alpha_init_builtins | |
11071 | #undef TARGET_EXPAND_BUILTIN | |
11072 | #define TARGET_EXPAND_BUILTIN alpha_expand_builtin | |
849c7bc6 | 11073 | #undef TARGET_FOLD_BUILTIN |
11074 | #define TARGET_FOLD_BUILTIN alpha_fold_builtin | |
92643d95 | 11075 | |
11076 | #undef TARGET_FUNCTION_OK_FOR_SIBCALL | |
11077 | #define TARGET_FUNCTION_OK_FOR_SIBCALL alpha_function_ok_for_sibcall | |
11078 | #undef TARGET_CANNOT_COPY_INSN_P | |
11079 | #define TARGET_CANNOT_COPY_INSN_P alpha_cannot_copy_insn_p | |
c0da4391 | 11080 | #undef TARGET_CANNOT_FORCE_CONST_MEM |
11081 | #define TARGET_CANNOT_FORCE_CONST_MEM alpha_cannot_force_const_mem | |
92643d95 | 11082 | |
11083 | #if TARGET_ABI_OSF | |
11084 | #undef TARGET_ASM_OUTPUT_MI_THUNK | |
11085 | #define TARGET_ASM_OUTPUT_MI_THUNK alpha_output_mi_thunk_osf | |
11086 | #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK | |
a9f1838b | 11087 | #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true |
7955d282 | 11088 | #undef TARGET_STDARG_OPTIMIZE_HOOK |
11089 | #define TARGET_STDARG_OPTIMIZE_HOOK alpha_stdarg_optimize_hook | |
92643d95 | 11090 | #endif |
11091 | ||
11092 | #undef TARGET_RTX_COSTS | |
11093 | #define TARGET_RTX_COSTS alpha_rtx_costs | |
11094 | #undef TARGET_ADDRESS_COST | |
f529eb25 | 11095 | #define TARGET_ADDRESS_COST hook_int_rtx_bool_0 |
92643d95 | 11096 | |
11097 | #undef TARGET_MACHINE_DEPENDENT_REORG | |
11098 | #define TARGET_MACHINE_DEPENDENT_REORG alpha_reorg | |
11099 | ||
3b2411a8 | 11100 | #undef TARGET_PROMOTE_FUNCTION_MODE |
11101 | #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote | |
dd9f3024 | 11102 | #undef TARGET_PROMOTE_PROTOTYPES |
fb80456a | 11103 | #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_false |
dd9f3024 | 11104 | #undef TARGET_RETURN_IN_MEMORY |
11105 | #define TARGET_RETURN_IN_MEMORY alpha_return_in_memory | |
b981d932 | 11106 | #undef TARGET_PASS_BY_REFERENCE |
11107 | #define TARGET_PASS_BY_REFERENCE alpha_pass_by_reference | |
dd9f3024 | 11108 | #undef TARGET_SETUP_INCOMING_VARARGS |
11109 | #define TARGET_SETUP_INCOMING_VARARGS alpha_setup_incoming_varargs | |
11110 | #undef TARGET_STRICT_ARGUMENT_NAMING | |
11111 | #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true | |
11112 | #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED | |
11113 | #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true | |
92d40bc4 | 11114 | #undef TARGET_SPLIT_COMPLEX_ARG |
11115 | #define TARGET_SPLIT_COMPLEX_ARG alpha_split_complex_arg | |
de8f9b94 | 11116 | #undef TARGET_GIMPLIFY_VA_ARG_EXPR |
11117 | #define TARGET_GIMPLIFY_VA_ARG_EXPR alpha_gimplify_va_arg | |
f054eb3c | 11118 | #undef TARGET_ARG_PARTIAL_BYTES |
11119 | #define TARGET_ARG_PARTIAL_BYTES alpha_arg_partial_bytes | |
7bcbe23a | 11120 | #undef TARGET_TRAMPOLINE_INIT |
11121 | #define TARGET_TRAMPOLINE_INIT alpha_trampoline_init | |
b2aef146 | 11122 | |
0d96cd2b | 11123 | #undef TARGET_SECONDARY_RELOAD |
11124 | #define TARGET_SECONDARY_RELOAD alpha_secondary_reload | |
11125 | ||
b2aef146 | 11126 | #undef TARGET_SCALAR_MODE_SUPPORTED_P |
11127 | #define TARGET_SCALAR_MODE_SUPPORTED_P alpha_scalar_mode_supported_p | |
9e7454d0 | 11128 | #undef TARGET_VECTOR_MODE_SUPPORTED_P |
11129 | #define TARGET_VECTOR_MODE_SUPPORTED_P alpha_vector_mode_supported_p | |
dd9f3024 | 11130 | |
2e15d750 | 11131 | #undef TARGET_BUILD_BUILTIN_VA_LIST |
11132 | #define TARGET_BUILD_BUILTIN_VA_LIST alpha_build_builtin_va_list | |
11133 | ||
8a58ed0a | 11134 | #undef TARGET_EXPAND_BUILTIN_VA_START |
11135 | #define TARGET_EXPAND_BUILTIN_VA_START alpha_va_start | |
11136 | ||
2ca3d426 | 11137 | /* The Alpha architecture does not require sequential consistency. See |
11138 | http://www.cs.umd.edu/~pugh/java/memoryModel/AlphaReordering.html | |
11139 | for an example of how it can be violated in practice. */ | |
11140 | #undef TARGET_RELAXED_ORDERING | |
11141 | #define TARGET_RELAXED_ORDERING true | |
11142 | ||
fb64edde | 11143 | #undef TARGET_DEFAULT_TARGET_FLAGS |
11144 | #define TARGET_DEFAULT_TARGET_FLAGS \ | |
11145 | (TARGET_DEFAULT | TARGET_CPU_DEFAULT | TARGET_DEFAULT_EXPLICIT_RELOCS) | |
11146 | #undef TARGET_HANDLE_OPTION | |
11147 | #define TARGET_HANDLE_OPTION alpha_handle_option | |
11148 | ||
4257b08a | 11149 | #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING |
eddcdde1 | 11150 | #undef TARGET_MANGLE_TYPE |
11151 | #define TARGET_MANGLE_TYPE alpha_mangle_type | |
4257b08a | 11152 | #endif |
11153 | ||
fd50b071 | 11154 | #undef TARGET_LEGITIMATE_ADDRESS_P |
11155 | #define TARGET_LEGITIMATE_ADDRESS_P alpha_legitimate_address_p | |
11156 | ||
92643d95 | 11157 | struct gcc_target targetm = TARGET_INITIALIZER; |
11158 | ||
11159 | \f | |
1f3233d1 | 11160 | #include "gt-alpha.h" |