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bf2a98b3 | 1 | /* Subroutines used for code generation on the DEC Alpha. |
6d2bbb9f | 2 | Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, |
9e7454d0 | 3 | 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc. |
0e0a0e7a | 4 | Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) |
bf2a98b3 | 5 | |
187b36cf | 6 | This file is part of GCC. |
bf2a98b3 | 7 | |
187b36cf | 8 | GCC is free software; you can redistribute it and/or modify |
bf2a98b3 | 9 | it under the terms of the GNU General Public License as published by |
10 | the Free Software Foundation; either version 2, or (at your option) | |
11 | any later version. | |
12 | ||
187b36cf | 13 | GCC is distributed in the hope that it will be useful, |
bf2a98b3 | 14 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
187b36cf | 19 | along with GCC; see the file COPYING. If not, write to |
77b72456 | 20 | the Free Software Foundation, 59 Temple Place - Suite 330, |
21 | Boston, MA 02111-1307, USA. */ | |
bf2a98b3 | 22 | |
23 | ||
bf2a98b3 | 24 | #include "config.h" |
769ea120 | 25 | #include "system.h" |
805e22b2 | 26 | #include "coretypes.h" |
27 | #include "tm.h" | |
bf2a98b3 | 28 | #include "rtl.h" |
d8fc4d0b | 29 | #include "tree.h" |
bf2a98b3 | 30 | #include "regs.h" |
31 | #include "hard-reg-set.h" | |
32 | #include "real.h" | |
33 | #include "insn-config.h" | |
34 | #include "conditions.h" | |
bf2a98b3 | 35 | #include "output.h" |
36 | #include "insn-attr.h" | |
37 | #include "flags.h" | |
38 | #include "recog.h" | |
bf2a98b3 | 39 | #include "expr.h" |
d8fc4d0b | 40 | #include "optabs.h" |
41 | #include "reload.h" | |
bf2a98b3 | 42 | #include "obstack.h" |
0c0464e6 | 43 | #include "except.h" |
44 | #include "function.h" | |
769ea120 | 45 | #include "toplev.h" |
11016d99 | 46 | #include "ggc.h" |
0f37b7a2 | 47 | #include "integrate.h" |
0d50f0b7 | 48 | #include "tm_p.h" |
a767736d | 49 | #include "target.h" |
50 | #include "target-def.h" | |
961d6ddd | 51 | #include "debug.h" |
a1f71e15 | 52 | #include "langhooks.h" |
573aba85 | 53 | #include <splay-tree.h> |
356907d3 | 54 | #include "cfglayout.h" |
de8f9b94 | 55 | #include "tree-gimple.h" |
0c0464e6 | 56 | |
65abff06 | 57 | /* Specify which cpu to schedule for. */ |
0c0464e6 | 58 | |
f141a8b4 | 59 | enum processor_type alpha_cpu; |
9e7454d0 | 60 | static const char * const alpha_cpu_name[] = |
07c1a295 | 61 | { |
62 | "ev4", "ev5", "ev6" | |
63 | }; | |
0c5845b3 | 64 | |
c4622276 | 65 | /* Specify how accurate floating-point traps need to be. */ |
66 | ||
67 | enum alpha_trap_precision alpha_tp; | |
68 | ||
69 | /* Specify the floating-point rounding mode. */ | |
70 | ||
71 | enum alpha_fp_rounding_mode alpha_fprm; | |
72 | ||
73 | /* Specify which things cause traps. */ | |
74 | ||
75 | enum alpha_fp_trap_mode alpha_fptm; | |
76 | ||
5f7b9df8 | 77 | /* Specify bit size of immediate TLS offsets. */ |
78 | ||
79 | int alpha_tls_size = 32; | |
80 | ||
c4622276 | 81 | /* Strings decoded into the above options. */ |
0c0464e6 | 82 | |
ace75b22 | 83 | const char *alpha_cpu_string; /* -mcpu= */ |
27de1488 | 84 | const char *alpha_tune_string; /* -mtune= */ |
ace75b22 | 85 | const char *alpha_tp_string; /* -mtrap-precision=[p|s|i] */ |
86 | const char *alpha_fprm_string; /* -mfp-rounding-mode=[n|m|c|d] */ | |
87 | const char *alpha_fptm_string; /* -mfp-trap-mode=[n|u|su|sui] */ | |
88 | const char *alpha_mlat_string; /* -mmemory-latency= */ | |
5f7b9df8 | 89 | const char *alpha_tls_size_string; /* -mtls-size=[16|32|64] */ |
c4622276 | 90 | |
bf2a98b3 | 91 | /* Save information from a "cmpxx" operation until the branch or scc is |
92 | emitted. */ | |
93 | ||
b18b881f | 94 | struct alpha_compare alpha_compare; |
bf2a98b3 | 95 | |
e3e08e7f | 96 | /* Nonzero if inside of a function, because the Alpha asm can't |
449b7f2d | 97 | handle .files inside of functions. */ |
98 | ||
99 | static int inside_function = FALSE; | |
100 | ||
07c1a295 | 101 | /* The number of cycles of latency we should assume on memory reads. */ |
102 | ||
103 | int alpha_memory_latency = 3; | |
104 | ||
b9a5aa8e | 105 | /* Whether the function needs the GP. */ |
106 | ||
107 | static int alpha_function_needs_gp; | |
108 | ||
849674a3 | 109 | /* The alias set for prologue/epilogue register save/restore. */ |
110 | ||
9de382d9 | 111 | static GTY(()) int alpha_sr_alias_set; |
849674a3 | 112 | |
a314eb5e | 113 | /* The assembler name of the current function. */ |
114 | ||
115 | static const char *alpha_fnname; | |
116 | ||
1f0ce6a6 | 117 | /* The next explicit relocation sequence number. */ |
9de382d9 | 118 | extern GTY(()) int alpha_next_sequence_number; |
1f0ce6a6 | 119 | int alpha_next_sequence_number = 1; |
120 | ||
121 | /* The literal and gpdisp sequence numbers for this insn, as printed | |
122 | by %# and %* respectively. */ | |
9de382d9 | 123 | extern GTY(()) int alpha_this_literal_sequence_number; |
124 | extern GTY(()) int alpha_this_gpdisp_sequence_number; | |
1f0ce6a6 | 125 | int alpha_this_literal_sequence_number; |
126 | int alpha_this_gpdisp_sequence_number; | |
127 | ||
fab7adbf | 128 | /* Costs of various operations on the different architectures. */ |
129 | ||
130 | struct alpha_rtx_cost_data | |
131 | { | |
132 | unsigned char fp_add; | |
133 | unsigned char fp_mult; | |
134 | unsigned char fp_div_sf; | |
135 | unsigned char fp_div_df; | |
136 | unsigned char int_mult_si; | |
137 | unsigned char int_mult_di; | |
138 | unsigned char int_shift; | |
139 | unsigned char int_cmov; | |
d7cf2331 | 140 | unsigned short int_div; |
fab7adbf | 141 | }; |
142 | ||
143 | static struct alpha_rtx_cost_data const alpha_rtx_cost_data[PROCESSOR_MAX] = | |
144 | { | |
145 | { /* EV4 */ | |
146 | COSTS_N_INSNS (6), /* fp_add */ | |
147 | COSTS_N_INSNS (6), /* fp_mult */ | |
148 | COSTS_N_INSNS (34), /* fp_div_sf */ | |
149 | COSTS_N_INSNS (63), /* fp_div_df */ | |
150 | COSTS_N_INSNS (23), /* int_mult_si */ | |
151 | COSTS_N_INSNS (23), /* int_mult_di */ | |
152 | COSTS_N_INSNS (2), /* int_shift */ | |
153 | COSTS_N_INSNS (2), /* int_cmov */ | |
f6777b0a | 154 | COSTS_N_INSNS (97), /* int_div */ |
fab7adbf | 155 | }, |
156 | { /* EV5 */ | |
157 | COSTS_N_INSNS (4), /* fp_add */ | |
158 | COSTS_N_INSNS (4), /* fp_mult */ | |
159 | COSTS_N_INSNS (15), /* fp_div_sf */ | |
160 | COSTS_N_INSNS (22), /* fp_div_df */ | |
161 | COSTS_N_INSNS (8), /* int_mult_si */ | |
162 | COSTS_N_INSNS (12), /* int_mult_di */ | |
163 | COSTS_N_INSNS (1) + 1, /* int_shift */ | |
164 | COSTS_N_INSNS (1), /* int_cmov */ | |
f6777b0a | 165 | COSTS_N_INSNS (83), /* int_div */ |
fab7adbf | 166 | }, |
167 | { /* EV6 */ | |
168 | COSTS_N_INSNS (4), /* fp_add */ | |
169 | COSTS_N_INSNS (4), /* fp_mult */ | |
170 | COSTS_N_INSNS (12), /* fp_div_sf */ | |
171 | COSTS_N_INSNS (15), /* fp_div_df */ | |
172 | COSTS_N_INSNS (7), /* int_mult_si */ | |
173 | COSTS_N_INSNS (7), /* int_mult_di */ | |
174 | COSTS_N_INSNS (1), /* int_shift */ | |
175 | COSTS_N_INSNS (2), /* int_cmov */ | |
f6777b0a | 176 | COSTS_N_INSNS (86), /* int_div */ |
fab7adbf | 177 | }, |
178 | }; | |
179 | ||
d7cf2331 | 180 | /* Similar but tuned for code size instead of execution latency. The |
181 | extra +N is fractional cost tuning based on latency. It's used to | |
182 | encourage use of cheaper insns like shift, but only if there's just | |
183 | one of them. */ | |
184 | ||
185 | static struct alpha_rtx_cost_data const alpha_rtx_cost_size = | |
186 | { | |
187 | COSTS_N_INSNS (1), /* fp_add */ | |
188 | COSTS_N_INSNS (1), /* fp_mult */ | |
189 | COSTS_N_INSNS (1), /* fp_div_sf */ | |
190 | COSTS_N_INSNS (1) + 1, /* fp_div_df */ | |
191 | COSTS_N_INSNS (1) + 1, /* int_mult_si */ | |
192 | COSTS_N_INSNS (1) + 2, /* int_mult_di */ | |
193 | COSTS_N_INSNS (1), /* int_shift */ | |
194 | COSTS_N_INSNS (1), /* int_cmov */ | |
195 | COSTS_N_INSNS (6), /* int_div */ | |
196 | }; | |
197 | ||
0dbd1c74 | 198 | /* Get the number of args of a function in one of two ways. */ |
9caef960 | 199 | #if TARGET_ABI_OPEN_VMS || TARGET_ABI_UNICOSMK |
0dbd1c74 | 200 | #define NUM_ARGS current_function_args_info.num_args |
201 | #else | |
202 | #define NUM_ARGS current_function_args_info | |
203 | #endif | |
d2832bd8 | 204 | |
d2832bd8 | 205 | #define REG_PV 27 |
206 | #define REG_RA 26 | |
f2cc13dc | 207 | |
92643d95 | 208 | /* Declarations of static functions. */ |
209 | static struct machine_function *alpha_init_machine_status (void); | |
210 | static rtx alpha_emit_xfloating_compare (enum rtx_code, rtx, rtx); | |
805e22b2 | 211 | |
92643d95 | 212 | #if TARGET_ABI_OPEN_VMS |
213 | static void alpha_write_linkage (FILE *, const char *, tree); | |
6988553d | 214 | #endif |
215 | ||
92643d95 | 216 | static void unicosmk_output_deferred_case_vectors (FILE *); |
217 | static void unicosmk_gen_dsib (unsigned long *); | |
218 | static void unicosmk_output_ssib (FILE *, const char *); | |
219 | static int unicosmk_need_dex (rtx); | |
a767736d | 220 | \f |
65abff06 | 221 | /* Parse target option strings. */ |
c4622276 | 222 | |
223 | void | |
92643d95 | 224 | override_options (void) |
c4622276 | 225 | { |
27de1488 | 226 | int i; |
e99c3a1d | 227 | static const struct cpu_table { |
228 | const char *const name; | |
229 | const enum processor_type processor; | |
230 | const int flags; | |
27de1488 | 231 | } cpu_table[] = { |
232 | #define EV5_MASK (MASK_CPU_EV5) | |
233 | #define EV6_MASK (MASK_CPU_EV6|MASK_BWX|MASK_MAX|MASK_FIX) | |
234 | { "ev4", PROCESSOR_EV4, 0 }, | |
235 | { "ev45", PROCESSOR_EV4, 0 }, | |
236 | { "21064", PROCESSOR_EV4, 0 }, | |
237 | { "ev5", PROCESSOR_EV5, EV5_MASK }, | |
238 | { "21164", PROCESSOR_EV5, EV5_MASK }, | |
239 | { "ev56", PROCESSOR_EV5, EV5_MASK|MASK_BWX }, | |
240 | { "21164a", PROCESSOR_EV5, EV5_MASK|MASK_BWX }, | |
241 | { "pca56", PROCESSOR_EV5, EV5_MASK|MASK_BWX|MASK_MAX }, | |
242 | { "21164PC",PROCESSOR_EV5, EV5_MASK|MASK_BWX|MASK_MAX }, | |
243 | { "21164pc",PROCESSOR_EV5, EV5_MASK|MASK_BWX|MASK_MAX }, | |
244 | { "ev6", PROCESSOR_EV6, EV6_MASK }, | |
245 | { "21264", PROCESSOR_EV6, EV6_MASK }, | |
246 | { "ev67", PROCESSOR_EV6, EV6_MASK|MASK_CIX }, | |
247 | { "21264a", PROCESSOR_EV6, EV6_MASK|MASK_CIX }, | |
248 | { 0, 0, 0 } | |
249 | }; | |
9e7454d0 | 250 | |
9caef960 | 251 | /* Unicos/Mk doesn't have shared libraries. */ |
252 | if (TARGET_ABI_UNICOSMK && flag_pic) | |
253 | { | |
254 | warning ("-f%s ignored for Unicos/Mk (not supported)", | |
255 | (flag_pic > 1) ? "PIC" : "pic"); | |
256 | flag_pic = 0; | |
257 | } | |
258 | ||
9e7454d0 | 259 | /* On Unicos/Mk, the native compiler consistently generates /d suffices for |
9caef960 | 260 | floating-point instructions. Make that the default for this target. */ |
261 | if (TARGET_ABI_UNICOSMK) | |
262 | alpha_fprm = ALPHA_FPRM_DYN; | |
263 | else | |
264 | alpha_fprm = ALPHA_FPRM_NORM; | |
265 | ||
c4622276 | 266 | alpha_tp = ALPHA_TP_PROG; |
c4622276 | 267 | alpha_fptm = ALPHA_FPTM_N; |
268 | ||
9e7454d0 | 269 | /* We cannot use su and sui qualifiers for conversion instructions on |
9caef960 | 270 | Unicos/Mk. I'm not sure if this is due to assembler or hardware |
271 | limitations. Right now, we issue a warning if -mieee is specified | |
272 | and then ignore it; eventually, we should either get it right or | |
273 | disable the option altogether. */ | |
274 | ||
c4622276 | 275 | if (TARGET_IEEE) |
276 | { | |
9caef960 | 277 | if (TARGET_ABI_UNICOSMK) |
278 | warning ("-mieee not supported on Unicos/Mk"); | |
279 | else | |
280 | { | |
281 | alpha_tp = ALPHA_TP_INSN; | |
282 | alpha_fptm = ALPHA_FPTM_SU; | |
283 | } | |
c4622276 | 284 | } |
285 | ||
286 | if (TARGET_IEEE_WITH_INEXACT) | |
287 | { | |
9caef960 | 288 | if (TARGET_ABI_UNICOSMK) |
289 | warning ("-mieee-with-inexact not supported on Unicos/Mk"); | |
290 | else | |
291 | { | |
292 | alpha_tp = ALPHA_TP_INSN; | |
293 | alpha_fptm = ALPHA_FPTM_SUI; | |
294 | } | |
c4622276 | 295 | } |
296 | ||
297 | if (alpha_tp_string) | |
264f7d8c | 298 | { |
299 | if (! strcmp (alpha_tp_string, "p")) | |
c4622276 | 300 | alpha_tp = ALPHA_TP_PROG; |
264f7d8c | 301 | else if (! strcmp (alpha_tp_string, "f")) |
c4622276 | 302 | alpha_tp = ALPHA_TP_FUNC; |
264f7d8c | 303 | else if (! strcmp (alpha_tp_string, "i")) |
c4622276 | 304 | alpha_tp = ALPHA_TP_INSN; |
264f7d8c | 305 | else |
306 | error ("bad value `%s' for -mtrap-precision switch", alpha_tp_string); | |
307 | } | |
c4622276 | 308 | |
309 | if (alpha_fprm_string) | |
264f7d8c | 310 | { |
311 | if (! strcmp (alpha_fprm_string, "n")) | |
c4622276 | 312 | alpha_fprm = ALPHA_FPRM_NORM; |
264f7d8c | 313 | else if (! strcmp (alpha_fprm_string, "m")) |
c4622276 | 314 | alpha_fprm = ALPHA_FPRM_MINF; |
264f7d8c | 315 | else if (! strcmp (alpha_fprm_string, "c")) |
c4622276 | 316 | alpha_fprm = ALPHA_FPRM_CHOP; |
264f7d8c | 317 | else if (! strcmp (alpha_fprm_string,"d")) |
c4622276 | 318 | alpha_fprm = ALPHA_FPRM_DYN; |
264f7d8c | 319 | else |
320 | error ("bad value `%s' for -mfp-rounding-mode switch", | |
c4622276 | 321 | alpha_fprm_string); |
264f7d8c | 322 | } |
c4622276 | 323 | |
324 | if (alpha_fptm_string) | |
264f7d8c | 325 | { |
326 | if (strcmp (alpha_fptm_string, "n") == 0) | |
327 | alpha_fptm = ALPHA_FPTM_N; | |
328 | else if (strcmp (alpha_fptm_string, "u") == 0) | |
329 | alpha_fptm = ALPHA_FPTM_U; | |
330 | else if (strcmp (alpha_fptm_string, "su") == 0) | |
331 | alpha_fptm = ALPHA_FPTM_SU; | |
332 | else if (strcmp (alpha_fptm_string, "sui") == 0) | |
333 | alpha_fptm = ALPHA_FPTM_SUI; | |
334 | else | |
335 | error ("bad value `%s' for -mfp-trap-mode switch", alpha_fptm_string); | |
336 | } | |
c4622276 | 337 | |
5f7b9df8 | 338 | if (alpha_tls_size_string) |
339 | { | |
340 | if (strcmp (alpha_tls_size_string, "16") == 0) | |
341 | alpha_tls_size = 16; | |
342 | else if (strcmp (alpha_tls_size_string, "32") == 0) | |
343 | alpha_tls_size = 32; | |
344 | else if (strcmp (alpha_tls_size_string, "64") == 0) | |
345 | alpha_tls_size = 64; | |
346 | else | |
347 | error ("bad value `%s' for -mtls-size switch", alpha_tls_size_string); | |
348 | } | |
349 | ||
cbd8ec27 | 350 | alpha_cpu |
351 | = TARGET_CPU_DEFAULT & MASK_CPU_EV6 ? PROCESSOR_EV6 | |
352 | : (TARGET_CPU_DEFAULT & MASK_CPU_EV5 ? PROCESSOR_EV5 : PROCESSOR_EV4); | |
353 | ||
354 | if (alpha_cpu_string) | |
355 | { | |
27de1488 | 356 | for (i = 0; cpu_table [i].name; i++) |
357 | if (! strcmp (alpha_cpu_string, cpu_table [i].name)) | |
358 | { | |
359 | alpha_cpu = cpu_table [i].processor; | |
360 | target_flags &= ~ (MASK_BWX | MASK_MAX | MASK_FIX | MASK_CIX | |
361 | | MASK_CPU_EV5 | MASK_CPU_EV6); | |
362 | target_flags |= cpu_table [i].flags; | |
363 | break; | |
364 | } | |
365 | if (! cpu_table [i].name) | |
cbd8ec27 | 366 | error ("bad value `%s' for -mcpu switch", alpha_cpu_string); |
367 | } | |
368 | ||
27de1488 | 369 | if (alpha_tune_string) |
370 | { | |
371 | for (i = 0; cpu_table [i].name; i++) | |
372 | if (! strcmp (alpha_tune_string, cpu_table [i].name)) | |
373 | { | |
374 | alpha_cpu = cpu_table [i].processor; | |
375 | break; | |
376 | } | |
377 | if (! cpu_table [i].name) | |
378 | error ("bad value `%s' for -mcpu switch", alpha_tune_string); | |
379 | } | |
380 | ||
65abff06 | 381 | /* Do some sanity checks on the above options. */ |
c4622276 | 382 | |
9caef960 | 383 | if (TARGET_ABI_UNICOSMK && alpha_fptm != ALPHA_FPTM_N) |
384 | { | |
385 | warning ("trap mode not supported on Unicos/Mk"); | |
386 | alpha_fptm = ALPHA_FPTM_N; | |
387 | } | |
388 | ||
264f7d8c | 389 | if ((alpha_fptm == ALPHA_FPTM_SU || alpha_fptm == ALPHA_FPTM_SUI) |
27de1488 | 390 | && alpha_tp != ALPHA_TP_INSN && ! TARGET_CPU_EV6) |
c4622276 | 391 | { |
264f7d8c | 392 | warning ("fp software completion requires -mtrap-precision=i"); |
c4622276 | 393 | alpha_tp = ALPHA_TP_INSN; |
394 | } | |
8df4a58b | 395 | |
27de1488 | 396 | if (TARGET_CPU_EV6) |
bc16f0c1 | 397 | { |
398 | /* Except for EV6 pass 1 (not released), we always have precise | |
399 | arithmetic traps. Which means we can do software completion | |
400 | without minding trap shadows. */ | |
401 | alpha_tp = ALPHA_TP_PROG; | |
402 | } | |
403 | ||
8df4a58b | 404 | if (TARGET_FLOAT_VAX) |
405 | { | |
406 | if (alpha_fprm == ALPHA_FPRM_MINF || alpha_fprm == ALPHA_FPRM_DYN) | |
407 | { | |
408 | warning ("rounding mode not supported for VAX floats"); | |
409 | alpha_fprm = ALPHA_FPRM_NORM; | |
410 | } | |
411 | if (alpha_fptm == ALPHA_FPTM_SUI) | |
412 | { | |
413 | warning ("trap mode not supported for VAX floats"); | |
414 | alpha_fptm = ALPHA_FPTM_SU; | |
415 | } | |
ef76af46 | 416 | if (target_flags_explicit & MASK_LONG_DOUBLE_128) |
417 | warning ("128-bit long double not supported for VAX floats"); | |
418 | target_flags &= ~MASK_LONG_DOUBLE_128; | |
8df4a58b | 419 | } |
07c1a295 | 420 | |
421 | { | |
422 | char *end; | |
423 | int lat; | |
424 | ||
425 | if (!alpha_mlat_string) | |
426 | alpha_mlat_string = "L1"; | |
427 | ||
14184418 | 428 | if (ISDIGIT ((unsigned char)alpha_mlat_string[0]) |
07c1a295 | 429 | && (lat = strtol (alpha_mlat_string, &end, 10), *end == '\0')) |
430 | ; | |
431 | else if ((alpha_mlat_string[0] == 'L' || alpha_mlat_string[0] == 'l') | |
14184418 | 432 | && ISDIGIT ((unsigned char)alpha_mlat_string[1]) |
07c1a295 | 433 | && alpha_mlat_string[2] == '\0') |
434 | { | |
9e7454d0 | 435 | static int const cache_latency[][4] = |
07c1a295 | 436 | { |
437 | { 3, 30, -1 }, /* ev4 -- Bcache is a guess */ | |
438 | { 2, 12, 38 }, /* ev5 -- Bcache from PC164 LMbench numbers */ | |
65abff06 | 439 | { 3, 12, 30 }, /* ev6 -- Bcache from DS20 LMbench. */ |
07c1a295 | 440 | }; |
441 | ||
442 | lat = alpha_mlat_string[1] - '0'; | |
88b64d67 | 443 | if (lat <= 0 || lat > 3 || cache_latency[alpha_cpu][lat-1] == -1) |
07c1a295 | 444 | { |
445 | warning ("L%d cache latency unknown for %s", | |
446 | lat, alpha_cpu_name[alpha_cpu]); | |
447 | lat = 3; | |
448 | } | |
449 | else | |
450 | lat = cache_latency[alpha_cpu][lat-1]; | |
451 | } | |
452 | else if (! strcmp (alpha_mlat_string, "main")) | |
453 | { | |
454 | /* Most current memories have about 370ns latency. This is | |
455 | a reasonable guess for a fast cpu. */ | |
456 | lat = 150; | |
457 | } | |
458 | else | |
459 | { | |
460 | warning ("bad value `%s' for -mmemory-latency", alpha_mlat_string); | |
461 | lat = 3; | |
462 | } | |
463 | ||
464 | alpha_memory_latency = lat; | |
465 | } | |
a9fa9190 | 466 | |
467 | /* Default the definition of "small data" to 8 bytes. */ | |
468 | if (!g_switch_set) | |
469 | g_switch_value = 8; | |
849674a3 | 470 | |
5dcb037d | 471 | /* Infer TARGET_SMALL_DATA from -fpic/-fPIC. */ |
472 | if (flag_pic == 1) | |
473 | target_flags |= MASK_SMALL_DATA; | |
474 | else if (flag_pic == 2) | |
475 | target_flags &= ~MASK_SMALL_DATA; | |
476 | ||
0ea5169b | 477 | /* Align labels and loops for optimal branching. */ |
478 | /* ??? Kludge these by not doing anything if we don't optimize and also if | |
65abff06 | 479 | we are writing ECOFF symbols to work around a bug in DEC's assembler. */ |
0ea5169b | 480 | if (optimize > 0 && write_symbols != SDB_DEBUG) |
481 | { | |
482 | if (align_loops <= 0) | |
483 | align_loops = 16; | |
484 | if (align_jumps <= 0) | |
485 | align_jumps = 16; | |
486 | } | |
487 | if (align_functions <= 0) | |
488 | align_functions = 16; | |
489 | ||
849674a3 | 490 | /* Acquire a unique set number for our register saves and restores. */ |
491 | alpha_sr_alias_set = new_alias_set (); | |
9caef960 | 492 | |
493 | /* Register variables and functions with the garbage collector. */ | |
494 | ||
9caef960 | 495 | /* Set up function hooks. */ |
496 | init_machine_status = alpha_init_machine_status; | |
1268285a | 497 | |
498 | /* Tell the compiler when we're using VAX floating point. */ | |
499 | if (TARGET_FLOAT_VAX) | |
500 | { | |
0021bea9 | 501 | REAL_MODE_FORMAT (SFmode) = &vax_f_format; |
502 | REAL_MODE_FORMAT (DFmode) = &vax_g_format; | |
503 | REAL_MODE_FORMAT (TFmode) = NULL; | |
1268285a | 504 | } |
c4622276 | 505 | } |
506 | \f | |
bf2a98b3 | 507 | /* Returns 1 if VALUE is a mask that contains full bytes of zero or ones. */ |
508 | ||
509 | int | |
92643d95 | 510 | zap_mask (HOST_WIDE_INT value) |
bf2a98b3 | 511 | { |
512 | int i; | |
513 | ||
514 | for (i = 0; i < HOST_BITS_PER_WIDE_INT / HOST_BITS_PER_CHAR; | |
515 | i++, value >>= 8) | |
516 | if ((value & 0xff) != 0 && (value & 0xff) != 0xff) | |
517 | return 0; | |
518 | ||
519 | return 1; | |
520 | } | |
521 | ||
9e7454d0 | 522 | /* Return true if OP is valid for a particular TLS relocation. |
41421c64 | 523 | We are already guaranteed that OP is a CONST. */ |
bf2a98b3 | 524 | |
525 | int | |
41421c64 | 526 | tls_symbolic_operand_1 (rtx op, int size, int unspec) |
bf2a98b3 | 527 | { |
5f7b9df8 | 528 | op = XEXP (op, 0); |
529 | ||
530 | if (GET_CODE (op) != UNSPEC || XINT (op, 1) != unspec) | |
531 | return 0; | |
532 | op = XVECEXP (op, 0, 0); | |
533 | ||
534 | if (GET_CODE (op) != SYMBOL_REF) | |
535 | return 0; | |
5f7b9df8 | 536 | |
09a1f342 | 537 | if (SYMBOL_REF_LOCAL_P (op)) |
5f7b9df8 | 538 | { |
09a1f342 | 539 | if (alpha_tls_size > size) |
5f7b9df8 | 540 | return 0; |
541 | } | |
09a1f342 | 542 | else |
5f7b9df8 | 543 | { |
09a1f342 | 544 | if (size != 64) |
5f7b9df8 | 545 | return 0; |
546 | } | |
5f7b9df8 | 547 | |
09a1f342 | 548 | switch (SYMBOL_REF_TLS_MODEL (op)) |
9bdcc1e5 | 549 | { |
09a1f342 | 550 | case TLS_MODEL_LOCAL_DYNAMIC: |
9bdcc1e5 | 551 | return unspec == UNSPEC_DTPREL; |
09a1f342 | 552 | case TLS_MODEL_INITIAL_EXEC: |
9bdcc1e5 | 553 | return unspec == UNSPEC_TPREL && size == 64; |
09a1f342 | 554 | case TLS_MODEL_LOCAL_EXEC: |
555 | return unspec == UNSPEC_TPREL; | |
9bdcc1e5 | 556 | default: |
557 | abort (); | |
558 | } | |
5f7b9df8 | 559 | } |
560 | ||
41421c64 | 561 | /* Used by aligned_memory_operand and unaligned_memory_operand to |
562 | resolve what reload is going to do with OP if it's a register. */ | |
bbf31a61 | 563 | |
41421c64 | 564 | rtx |
565 | resolve_reload_operand (rtx op) | |
bf2a98b3 | 566 | { |
cc215844 | 567 | if (reload_in_progress) |
bf2a98b3 | 568 | { |
cc215844 | 569 | rtx tmp = op; |
570 | if (GET_CODE (tmp) == SUBREG) | |
571 | tmp = SUBREG_REG (tmp); | |
572 | if (GET_CODE (tmp) == REG | |
573 | && REGNO (tmp) >= FIRST_PSEUDO_REGISTER) | |
574 | { | |
575 | op = reg_equiv_memory_loc[REGNO (tmp)]; | |
576 | if (op == 0) | |
577 | return 0; | |
578 | } | |
bf2a98b3 | 579 | } |
41421c64 | 580 | return op; |
14f7bc98 | 581 | } |
582 | ||
f5a60074 | 583 | /* Implements CONST_OK_FOR_LETTER_P. Return true if the value matches |
584 | the range defined for C in [I-P]. */ | |
585 | ||
586 | bool | |
92643d95 | 587 | alpha_const_ok_for_letter_p (HOST_WIDE_INT value, int c) |
f5a60074 | 588 | { |
589 | switch (c) | |
590 | { | |
591 | case 'I': | |
592 | /* An unsigned 8 bit constant. */ | |
593 | return (unsigned HOST_WIDE_INT) value < 0x100; | |
594 | case 'J': | |
595 | /* The constant zero. */ | |
596 | return value == 0; | |
597 | case 'K': | |
598 | /* A signed 16 bit constant. */ | |
599 | return (unsigned HOST_WIDE_INT) (value + 0x8000) < 0x10000; | |
600 | case 'L': | |
601 | /* A shifted signed 16 bit constant appropriate for LDAH. */ | |
602 | return ((value & 0xffff) == 0 | |
603 | && ((value) >> 31 == -1 || value >> 31 == 0)); | |
604 | case 'M': | |
605 | /* A constant that can be AND'ed with using a ZAP insn. */ | |
606 | return zap_mask (value); | |
607 | case 'N': | |
608 | /* A complemented unsigned 8 bit constant. */ | |
609 | return (unsigned HOST_WIDE_INT) (~ value) < 0x100; | |
610 | case 'O': | |
611 | /* A negated unsigned 8 bit constant. */ | |
612 | return (unsigned HOST_WIDE_INT) (- value) < 0x100; | |
613 | case 'P': | |
614 | /* The constant 1, 2 or 3. */ | |
615 | return value == 1 || value == 2 || value == 3; | |
616 | ||
617 | default: | |
618 | return false; | |
619 | } | |
620 | } | |
621 | ||
622 | /* Implements CONST_DOUBLE_OK_FOR_LETTER_P. Return true if VALUE | |
623 | matches for C in [GH]. */ | |
624 | ||
625 | bool | |
92643d95 | 626 | alpha_const_double_ok_for_letter_p (rtx value, int c) |
f5a60074 | 627 | { |
628 | switch (c) | |
629 | { | |
630 | case 'G': | |
631 | /* The floating point zero constant. */ | |
632 | return (GET_MODE_CLASS (GET_MODE (value)) == MODE_FLOAT | |
633 | && value == CONST0_RTX (GET_MODE (value))); | |
634 | ||
635 | case 'H': | |
636 | /* A valid operand of a ZAP insn. */ | |
637 | return (GET_MODE (value) == VOIDmode | |
638 | && zap_mask (CONST_DOUBLE_LOW (value)) | |
639 | && zap_mask (CONST_DOUBLE_HIGH (value))); | |
640 | ||
641 | default: | |
642 | return false; | |
643 | } | |
644 | } | |
645 | ||
646 | /* Implements CONST_DOUBLE_OK_FOR_LETTER_P. Return true if VALUE | |
647 | matches for C. */ | |
648 | ||
649 | bool | |
92643d95 | 650 | alpha_extra_constraint (rtx value, int c) |
f5a60074 | 651 | { |
652 | switch (c) | |
653 | { | |
654 | case 'Q': | |
655 | return normal_memory_operand (value, VOIDmode); | |
656 | case 'R': | |
657 | return direct_call_operand (value, Pmode); | |
658 | case 'S': | |
659 | return (GET_CODE (value) == CONST_INT | |
660 | && (unsigned HOST_WIDE_INT) INTVAL (value) < 64); | |
661 | case 'T': | |
662 | return GET_CODE (value) == HIGH; | |
663 | case 'U': | |
664 | return TARGET_ABI_UNICOSMK && symbolic_operand (value, VOIDmode); | |
f2cc13dc | 665 | case 'W': |
666 | return (GET_CODE (value) == CONST_VECTOR | |
667 | && value == CONST0_RTX (GET_MODE (value))); | |
f5a60074 | 668 | default: |
669 | return false; | |
670 | } | |
671 | } | |
672 | ||
b2aef146 | 673 | /* The scalar modes supported differs from the default check-what-c-supports |
674 | version in that sometimes TFmode is available even when long double | |
675 | indicates only DFmode. On unicosmk, we have the situation that HImode | |
676 | doesn't map to any C type, but of course we still support that. */ | |
677 | ||
678 | static bool | |
679 | alpha_scalar_mode_supported_p (enum machine_mode mode) | |
680 | { | |
681 | switch (mode) | |
682 | { | |
683 | case QImode: | |
684 | case HImode: | |
685 | case SImode: | |
686 | case DImode: | |
687 | case TImode: /* via optabs.c */ | |
688 | return true; | |
689 | ||
690 | case SFmode: | |
691 | case DFmode: | |
692 | return true; | |
693 | ||
694 | case TFmode: | |
695 | return TARGET_HAS_XFLOATING_LIBS; | |
696 | ||
697 | default: | |
698 | return false; | |
699 | } | |
700 | } | |
701 | ||
702 | /* Alpha implements a couple of integer vector mode operations when | |
703 | TARGET_MAX is enabled. */ | |
704 | ||
9e7454d0 | 705 | static bool |
706 | alpha_vector_mode_supported_p (enum machine_mode mode) | |
707 | { | |
708 | if (TARGET_MAX | |
b2aef146 | 709 | && (mode == V8QImode |
710 | || mode == V4HImode | |
711 | || mode == V2SImode)) | |
9e7454d0 | 712 | return true; |
713 | ||
714 | return false; | |
715 | } | |
716 | ||
550e415f | 717 | /* Return 1 if this function can directly return via $26. */ |
718 | ||
719 | int | |
92643d95 | 720 | direct_return (void) |
550e415f | 721 | { |
9caef960 | 722 | return (! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK |
1467e953 | 723 | && reload_completed |
724 | && alpha_sa_size () == 0 | |
550e415f | 725 | && get_frame_size () == 0 |
726 | && current_function_outgoing_args_size == 0 | |
727 | && current_function_pretend_args_size == 0); | |
728 | } | |
ecb98d40 | 729 | |
730 | /* Return the ADDR_VEC associated with a tablejump insn. */ | |
731 | ||
732 | rtx | |
92643d95 | 733 | alpha_tablejump_addr_vec (rtx insn) |
ecb98d40 | 734 | { |
735 | rtx tmp; | |
736 | ||
737 | tmp = JUMP_LABEL (insn); | |
738 | if (!tmp) | |
739 | return NULL_RTX; | |
740 | tmp = NEXT_INSN (tmp); | |
741 | if (!tmp) | |
742 | return NULL_RTX; | |
743 | if (GET_CODE (tmp) == JUMP_INSN | |
744 | && GET_CODE (PATTERN (tmp)) == ADDR_DIFF_VEC) | |
745 | return PATTERN (tmp); | |
746 | return NULL_RTX; | |
747 | } | |
748 | ||
749 | /* Return the label of the predicted edge, or CONST0_RTX if we don't know. */ | |
750 | ||
751 | rtx | |
92643d95 | 752 | alpha_tablejump_best_label (rtx insn) |
ecb98d40 | 753 | { |
754 | rtx jump_table = alpha_tablejump_addr_vec (insn); | |
755 | rtx best_label = NULL_RTX; | |
756 | ||
757 | /* ??? Once the CFG doesn't keep getting completely rebuilt, look | |
758 | there for edge frequency counts from profile data. */ | |
759 | ||
760 | if (jump_table) | |
761 | { | |
762 | int n_labels = XVECLEN (jump_table, 1); | |
763 | int best_count = -1; | |
764 | int i, j; | |
765 | ||
766 | for (i = 0; i < n_labels; i++) | |
767 | { | |
768 | int count = 1; | |
769 | ||
770 | for (j = i + 1; j < n_labels; j++) | |
771 | if (XEXP (XVECEXP (jump_table, 1, i), 0) | |
772 | == XEXP (XVECEXP (jump_table, 1, j), 0)) | |
773 | count++; | |
774 | ||
775 | if (count > best_count) | |
776 | best_count = count, best_label = XVECEXP (jump_table, 1, i); | |
777 | } | |
778 | } | |
779 | ||
780 | return best_label ? best_label : const0_rtx; | |
781 | } | |
5f7b9df8 | 782 | |
783 | /* Return the TLS model to use for SYMBOL. */ | |
784 | ||
785 | static enum tls_model | |
92643d95 | 786 | tls_symbolic_operand_type (rtx symbol) |
5f7b9df8 | 787 | { |
09a1f342 | 788 | enum tls_model model; |
5f7b9df8 | 789 | |
790 | if (GET_CODE (symbol) != SYMBOL_REF) | |
791 | return 0; | |
09a1f342 | 792 | model = SYMBOL_REF_TLS_MODEL (symbol); |
5f7b9df8 | 793 | |
09a1f342 | 794 | /* Local-exec with a 64-bit size is the same code as initial-exec. */ |
795 | if (model == TLS_MODEL_LOCAL_EXEC && alpha_tls_size == 64) | |
796 | model = TLS_MODEL_INITIAL_EXEC; | |
5f7b9df8 | 797 | |
09a1f342 | 798 | return model; |
5f7b9df8 | 799 | } |
14f7bc98 | 800 | \f |
9bdcc1e5 | 801 | /* Return true if the function DECL will share the same GP as any |
802 | function in the current unit of translation. */ | |
803 | ||
804 | static bool | |
92643d95 | 805 | decl_has_samegp (tree decl) |
9bdcc1e5 | 806 | { |
807 | /* Functions that are not local can be overridden, and thus may | |
808 | not share the same gp. */ | |
809 | if (!(*targetm.binds_local_p) (decl)) | |
810 | return false; | |
811 | ||
812 | /* If -msmall-data is in effect, assume that there is only one GP | |
813 | for the module, and so any local symbol has this property. We | |
814 | need explicit relocations to be able to enforce this for symbols | |
815 | not defined in this unit of translation, however. */ | |
816 | if (TARGET_EXPLICIT_RELOCS && TARGET_SMALL_DATA) | |
817 | return true; | |
818 | ||
819 | /* Functions that are not external are defined in this UoT. */ | |
cf1d67e3 | 820 | /* ??? Irritatingly, static functions not yet emitted are still |
821 | marked "external". Apply this to non-static functions only. */ | |
822 | return !TREE_PUBLIC (decl) || !DECL_EXTERNAL (decl); | |
9bdcc1e5 | 823 | } |
824 | ||
52470889 | 825 | /* Return true if EXP should be placed in the small data section. */ |
826 | ||
827 | static bool | |
92643d95 | 828 | alpha_in_small_data_p (tree exp) |
52470889 | 829 | { |
0aad4cd2 | 830 | /* We want to merge strings, so we never consider them small data. */ |
831 | if (TREE_CODE (exp) == STRING_CST) | |
832 | return false; | |
833 | ||
6ac09a46 | 834 | /* Functions are never in the small data area. Duh. */ |
835 | if (TREE_CODE (exp) == FUNCTION_DECL) | |
836 | return false; | |
837 | ||
52470889 | 838 | if (TREE_CODE (exp) == VAR_DECL && DECL_SECTION_NAME (exp)) |
839 | { | |
840 | const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (exp)); | |
841 | if (strcmp (section, ".sdata") == 0 | |
842 | || strcmp (section, ".sbss") == 0) | |
843 | return true; | |
844 | } | |
845 | else | |
846 | { | |
847 | HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (exp)); | |
848 | ||
849 | /* If this is an incomplete type with size 0, then we can't put it | |
850 | in sdata because it might be too big when completed. */ | |
3be2f219 | 851 | if (size > 0 && (unsigned HOST_WIDE_INT) size <= g_switch_value) |
52470889 | 852 | return true; |
853 | } | |
854 | ||
855 | return false; | |
856 | } | |
857 | ||
cf73d31f | 858 | #if TARGET_ABI_OPEN_VMS |
859 | static bool | |
92643d95 | 860 | alpha_linkage_symbol_p (const char *symname) |
cf73d31f | 861 | { |
862 | int symlen = strlen (symname); | |
863 | ||
864 | if (symlen > 4) | |
865 | return strcmp (&symname [symlen - 4], "..lk") == 0; | |
866 | ||
867 | return false; | |
868 | } | |
869 | ||
870 | #define LINKAGE_SYMBOL_REF_P(X) \ | |
871 | ((GET_CODE (X) == SYMBOL_REF \ | |
872 | && alpha_linkage_symbol_p (XSTR (X, 0))) \ | |
873 | || (GET_CODE (X) == CONST \ | |
874 | && GET_CODE (XEXP (X, 0)) == PLUS \ | |
875 | && GET_CODE (XEXP (XEXP (X, 0), 0)) == SYMBOL_REF \ | |
876 | && alpha_linkage_symbol_p (XSTR (XEXP (XEXP (X, 0), 0), 0)))) | |
877 | #endif | |
878 | ||
24b3c0ed | 879 | /* legitimate_address_p recognizes an RTL expression that is a valid |
880 | memory address for an instruction. The MODE argument is the | |
881 | machine mode for the MEM expression that wants to use this address. | |
882 | ||
883 | For Alpha, we have either a constant address or the sum of a | |
884 | register and a constant address, or just a register. For DImode, | |
885 | any of those forms can be surrounded with an AND that clear the | |
886 | low-order three bits; this is an "unaligned" access. */ | |
887 | ||
888 | bool | |
92643d95 | 889 | alpha_legitimate_address_p (enum machine_mode mode, rtx x, int strict) |
24b3c0ed | 890 | { |
891 | /* If this is an ldq_u type address, discard the outer AND. */ | |
892 | if (mode == DImode | |
893 | && GET_CODE (x) == AND | |
894 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
895 | && INTVAL (XEXP (x, 1)) == -8) | |
896 | x = XEXP (x, 0); | |
897 | ||
898 | /* Discard non-paradoxical subregs. */ | |
899 | if (GET_CODE (x) == SUBREG | |
900 | && (GET_MODE_SIZE (GET_MODE (x)) | |
901 | < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))) | |
902 | x = SUBREG_REG (x); | |
903 | ||
904 | /* Unadorned general registers are valid. */ | |
905 | if (REG_P (x) | |
906 | && (strict | |
907 | ? STRICT_REG_OK_FOR_BASE_P (x) | |
908 | : NONSTRICT_REG_OK_FOR_BASE_P (x))) | |
909 | return true; | |
910 | ||
911 | /* Constant addresses (i.e. +/- 32k) are valid. */ | |
912 | if (CONSTANT_ADDRESS_P (x)) | |
913 | return true; | |
914 | ||
cf73d31f | 915 | #if TARGET_ABI_OPEN_VMS |
916 | if (LINKAGE_SYMBOL_REF_P (x)) | |
917 | return true; | |
918 | #endif | |
919 | ||
24b3c0ed | 920 | /* Register plus a small constant offset is valid. */ |
921 | if (GET_CODE (x) == PLUS) | |
922 | { | |
923 | rtx ofs = XEXP (x, 1); | |
924 | x = XEXP (x, 0); | |
925 | ||
926 | /* Discard non-paradoxical subregs. */ | |
927 | if (GET_CODE (x) == SUBREG | |
928 | && (GET_MODE_SIZE (GET_MODE (x)) | |
929 | < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))) | |
930 | x = SUBREG_REG (x); | |
931 | ||
932 | if (REG_P (x)) | |
933 | { | |
934 | if (! strict | |
935 | && NONSTRICT_REG_OK_FP_BASE_P (x) | |
936 | && GET_CODE (ofs) == CONST_INT) | |
937 | return true; | |
938 | if ((strict | |
939 | ? STRICT_REG_OK_FOR_BASE_P (x) | |
940 | : NONSTRICT_REG_OK_FOR_BASE_P (x)) | |
941 | && CONSTANT_ADDRESS_P (ofs)) | |
942 | return true; | |
943 | } | |
24b3c0ed | 944 | } |
945 | ||
f5a60074 | 946 | /* If we're managing explicit relocations, LO_SUM is valid, as |
947 | are small data symbols. */ | |
948 | else if (TARGET_EXPLICIT_RELOCS) | |
1f0ce6a6 | 949 | { |
f5a60074 | 950 | if (small_symbolic_operand (x, Pmode)) |
1f0ce6a6 | 951 | return true; |
f5a60074 | 952 | |
953 | if (GET_CODE (x) == LO_SUM) | |
954 | { | |
955 | rtx ofs = XEXP (x, 1); | |
956 | x = XEXP (x, 0); | |
957 | ||
958 | /* Discard non-paradoxical subregs. */ | |
959 | if (GET_CODE (x) == SUBREG | |
960 | && (GET_MODE_SIZE (GET_MODE (x)) | |
961 | < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))) | |
962 | x = SUBREG_REG (x); | |
963 | ||
964 | /* Must have a valid base register. */ | |
965 | if (! (REG_P (x) | |
966 | && (strict | |
967 | ? STRICT_REG_OK_FOR_BASE_P (x) | |
968 | : NONSTRICT_REG_OK_FOR_BASE_P (x)))) | |
969 | return false; | |
970 | ||
971 | /* The symbol must be local. */ | |
5f7b9df8 | 972 | if (local_symbolic_operand (ofs, Pmode) |
973 | || dtp32_symbolic_operand (ofs, Pmode) | |
974 | || tp32_symbolic_operand (ofs, Pmode)) | |
f5a60074 | 975 | return true; |
976 | } | |
1f0ce6a6 | 977 | } |
978 | ||
24b3c0ed | 979 | return false; |
980 | } | |
981 | ||
09a1f342 | 982 | /* Build the SYMBOL_REF for __tls_get_addr. */ |
983 | ||
984 | static GTY(()) rtx tls_get_addr_libfunc; | |
985 | ||
986 | static rtx | |
92643d95 | 987 | get_tls_get_addr (void) |
09a1f342 | 988 | { |
989 | if (!tls_get_addr_libfunc) | |
990 | tls_get_addr_libfunc = init_one_libfunc ("__tls_get_addr"); | |
991 | return tls_get_addr_libfunc; | |
992 | } | |
993 | ||
0d50f0b7 | 994 | /* Try machine-dependent ways of modifying an illegitimate address |
995 | to be legitimate. If we find one, return the new, valid address. */ | |
996 | ||
997 | rtx | |
92643d95 | 998 | alpha_legitimize_address (rtx x, rtx scratch, |
999 | enum machine_mode mode ATTRIBUTE_UNUSED) | |
0d50f0b7 | 1000 | { |
1001 | HOST_WIDE_INT addend; | |
1002 | ||
1003 | /* If the address is (plus reg const_int) and the CONST_INT is not a | |
1004 | valid offset, compute the high part of the constant and add it to | |
1005 | the register. Then our address is (plus temp low-part-const). */ | |
1006 | if (GET_CODE (x) == PLUS | |
1007 | && GET_CODE (XEXP (x, 0)) == REG | |
1008 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
1009 | && ! CONSTANT_ADDRESS_P (XEXP (x, 1))) | |
1010 | { | |
1011 | addend = INTVAL (XEXP (x, 1)); | |
1012 | x = XEXP (x, 0); | |
1013 | goto split_addend; | |
1014 | } | |
1015 | ||
1016 | /* If the address is (const (plus FOO const_int)), find the low-order | |
1017 | part of the CONST_INT. Then load FOO plus any high-order part of the | |
1018 | CONST_INT into a register. Our address is (plus reg low-part-const). | |
1019 | This is done to reduce the number of GOT entries. */ | |
f5a60074 | 1020 | if (!no_new_pseudos |
1021 | && GET_CODE (x) == CONST | |
0d50f0b7 | 1022 | && GET_CODE (XEXP (x, 0)) == PLUS |
1023 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT) | |
1024 | { | |
1025 | addend = INTVAL (XEXP (XEXP (x, 0), 1)); | |
1026 | x = force_reg (Pmode, XEXP (XEXP (x, 0), 0)); | |
1027 | goto split_addend; | |
1028 | } | |
1029 | ||
1030 | /* If we have a (plus reg const), emit the load as in (2), then add | |
1031 | the two registers, and finally generate (plus reg low-part-const) as | |
1032 | our address. */ | |
f5a60074 | 1033 | if (!no_new_pseudos |
1034 | && GET_CODE (x) == PLUS | |
0d50f0b7 | 1035 | && GET_CODE (XEXP (x, 0)) == REG |
1036 | && GET_CODE (XEXP (x, 1)) == CONST | |
1037 | && GET_CODE (XEXP (XEXP (x, 1), 0)) == PLUS | |
1038 | && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 1)) == CONST_INT) | |
1039 | { | |
1040 | addend = INTVAL (XEXP (XEXP (XEXP (x, 1), 0), 1)); | |
1041 | x = expand_simple_binop (Pmode, PLUS, XEXP (x, 0), | |
1042 | XEXP (XEXP (XEXP (x, 1), 0), 0), | |
1043 | NULL_RTX, 1, OPTAB_LIB_WIDEN); | |
1044 | goto split_addend; | |
1045 | } | |
1046 | ||
1f0ce6a6 | 1047 | /* If this is a local symbol, split the address into HIGH/LO_SUM parts. */ |
8afb6db4 | 1048 | if (TARGET_EXPLICIT_RELOCS && symbolic_operand (x, Pmode)) |
1f0ce6a6 | 1049 | { |
5f7b9df8 | 1050 | rtx r0, r16, eqv, tga, tp, insn, dest, seq; |
1051 | ||
1052 | switch (tls_symbolic_operand_type (x)) | |
1053 | { | |
1054 | case TLS_MODEL_GLOBAL_DYNAMIC: | |
1055 | start_sequence (); | |
1056 | ||
1057 | r0 = gen_rtx_REG (Pmode, 0); | |
1058 | r16 = gen_rtx_REG (Pmode, 16); | |
09a1f342 | 1059 | tga = get_tls_get_addr (); |
5f7b9df8 | 1060 | dest = gen_reg_rtx (Pmode); |
1061 | seq = GEN_INT (alpha_next_sequence_number++); | |
9e7454d0 | 1062 | |
5f7b9df8 | 1063 | emit_insn (gen_movdi_er_tlsgd (r16, pic_offset_table_rtx, x, seq)); |
1064 | insn = gen_call_value_osf_tlsgd (r0, tga, seq); | |
1065 | insn = emit_call_insn (insn); | |
1066 | CONST_OR_PURE_CALL_P (insn) = 1; | |
1067 | use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r16); | |
1068 | ||
1069 | insn = get_insns (); | |
1070 | end_sequence (); | |
1071 | ||
1072 | emit_libcall_block (insn, dest, r0, x); | |
1073 | return dest; | |
1074 | ||
1075 | case TLS_MODEL_LOCAL_DYNAMIC: | |
1076 | start_sequence (); | |
1077 | ||
1078 | r0 = gen_rtx_REG (Pmode, 0); | |
1079 | r16 = gen_rtx_REG (Pmode, 16); | |
09a1f342 | 1080 | tga = get_tls_get_addr (); |
5f7b9df8 | 1081 | scratch = gen_reg_rtx (Pmode); |
1082 | seq = GEN_INT (alpha_next_sequence_number++); | |
1083 | ||
1084 | emit_insn (gen_movdi_er_tlsldm (r16, pic_offset_table_rtx, seq)); | |
1085 | insn = gen_call_value_osf_tlsldm (r0, tga, seq); | |
1086 | insn = emit_call_insn (insn); | |
1087 | CONST_OR_PURE_CALL_P (insn) = 1; | |
1088 | use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r16); | |
1089 | ||
1090 | insn = get_insns (); | |
1091 | end_sequence (); | |
1092 | ||
1093 | eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), | |
1094 | UNSPEC_TLSLDM_CALL); | |
1095 | emit_libcall_block (insn, scratch, r0, eqv); | |
1096 | ||
1097 | eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), UNSPEC_DTPREL); | |
1098 | eqv = gen_rtx_CONST (Pmode, eqv); | |
1099 | ||
1100 | if (alpha_tls_size == 64) | |
1101 | { | |
1102 | dest = gen_reg_rtx (Pmode); | |
1103 | emit_insn (gen_rtx_SET (VOIDmode, dest, eqv)); | |
1104 | emit_insn (gen_adddi3 (dest, dest, scratch)); | |
1105 | return dest; | |
1106 | } | |
1107 | if (alpha_tls_size == 32) | |
1108 | { | |
1109 | insn = gen_rtx_HIGH (Pmode, eqv); | |
1110 | insn = gen_rtx_PLUS (Pmode, scratch, insn); | |
1111 | scratch = gen_reg_rtx (Pmode); | |
1112 | emit_insn (gen_rtx_SET (VOIDmode, scratch, insn)); | |
1113 | } | |
1114 | return gen_rtx_LO_SUM (Pmode, scratch, eqv); | |
1115 | ||
1116 | case TLS_MODEL_INITIAL_EXEC: | |
1117 | eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), UNSPEC_TPREL); | |
1118 | eqv = gen_rtx_CONST (Pmode, eqv); | |
1119 | tp = gen_reg_rtx (Pmode); | |
1120 | scratch = gen_reg_rtx (Pmode); | |
1121 | dest = gen_reg_rtx (Pmode); | |
1122 | ||
1123 | emit_insn (gen_load_tp (tp)); | |
1124 | emit_insn (gen_rtx_SET (VOIDmode, scratch, eqv)); | |
1125 | emit_insn (gen_adddi3 (dest, tp, scratch)); | |
1126 | return dest; | |
1127 | ||
1128 | case TLS_MODEL_LOCAL_EXEC: | |
1129 | eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), UNSPEC_TPREL); | |
1130 | eqv = gen_rtx_CONST (Pmode, eqv); | |
1131 | tp = gen_reg_rtx (Pmode); | |
1132 | ||
1133 | emit_insn (gen_load_tp (tp)); | |
1134 | if (alpha_tls_size == 32) | |
1135 | { | |
1136 | insn = gen_rtx_HIGH (Pmode, eqv); | |
1137 | insn = gen_rtx_PLUS (Pmode, tp, insn); | |
1138 | tp = gen_reg_rtx (Pmode); | |
1139 | emit_insn (gen_rtx_SET (VOIDmode, tp, insn)); | |
1140 | } | |
1141 | return gen_rtx_LO_SUM (Pmode, tp, eqv); | |
1142 | } | |
1143 | ||
8afb6db4 | 1144 | if (local_symbolic_operand (x, Pmode)) |
1145 | { | |
1146 | if (small_symbolic_operand (x, Pmode)) | |
f5a60074 | 1147 | return x; |
8afb6db4 | 1148 | else |
1149 | { | |
f5a60074 | 1150 | if (!no_new_pseudos) |
1151 | scratch = gen_reg_rtx (Pmode); | |
1152 | emit_insn (gen_rtx_SET (VOIDmode, scratch, | |
1153 | gen_rtx_HIGH (Pmode, x))); | |
1154 | return gen_rtx_LO_SUM (Pmode, scratch, x); | |
8afb6db4 | 1155 | } |
5dcb037d | 1156 | } |
1f0ce6a6 | 1157 | } |
1158 | ||
0d50f0b7 | 1159 | return NULL; |
1160 | ||
1161 | split_addend: | |
1162 | { | |
f5a60074 | 1163 | HOST_WIDE_INT low, high; |
1164 | ||
1165 | low = ((addend & 0xffff) ^ 0x8000) - 0x8000; | |
1166 | addend -= low; | |
1167 | high = ((addend & 0xffffffff) ^ 0x80000000) - 0x80000000; | |
1168 | addend -= high; | |
1169 | ||
1170 | if (addend) | |
1171 | x = expand_simple_binop (Pmode, PLUS, x, GEN_INT (addend), | |
1172 | (no_new_pseudos ? scratch : NULL_RTX), | |
1173 | 1, OPTAB_LIB_WIDEN); | |
1174 | if (high) | |
1175 | x = expand_simple_binop (Pmode, PLUS, x, GEN_INT (high), | |
1176 | (no_new_pseudos ? scratch : NULL_RTX), | |
1177 | 1, OPTAB_LIB_WIDEN); | |
1178 | ||
1179 | return plus_constant (x, low); | |
0d50f0b7 | 1180 | } |
1181 | } | |
1182 | ||
c0da4391 | 1183 | /* Primarily this is required for TLS symbols, but given that our move |
1184 | patterns *ought* to be able to handle any symbol at any time, we | |
1185 | should never be spilling symbolic operands to the constant pool, ever. */ | |
1186 | ||
1187 | static bool | |
1188 | alpha_cannot_force_const_mem (rtx x) | |
1189 | { | |
1190 | enum rtx_code code = GET_CODE (x); | |
1191 | return code == SYMBOL_REF || code == LABEL_REF || code == CONST; | |
1192 | } | |
1193 | ||
805e22b2 | 1194 | /* We do not allow indirect calls to be optimized into sibling calls, nor |
9bdcc1e5 | 1195 | can we allow a call to a function with a different GP to be optimized |
1196 | into a sibcall. */ | |
1197 | ||
805e22b2 | 1198 | static bool |
92643d95 | 1199 | alpha_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED) |
805e22b2 | 1200 | { |
9bdcc1e5 | 1201 | /* Can't do indirect tail calls, since we don't know if the target |
1202 | uses the same GP. */ | |
1203 | if (!decl) | |
1204 | return false; | |
1205 | ||
1206 | /* Otherwise, we can make a tail call if the target function shares | |
1207 | the same GP. */ | |
1208 | return decl_has_samegp (decl); | |
805e22b2 | 1209 | } |
1210 | ||
f5a60074 | 1211 | /* For TARGET_EXPLICIT_RELOCS, we don't obfuscate a SYMBOL_REF to a |
1212 | small symbolic operand until after reload. At which point we need | |
1213 | to replace (mem (symbol_ref)) with (mem (lo_sum $29 symbol_ref)) | |
1214 | so that sched2 has the proper dependency information. */ | |
9e7454d0 | 1215 | /* |
41421c64 | 1216 | {"some_small_symbolic_operand", {SET, PARALLEL, PREFETCH, UNSPEC, \ |
1217 | UNSPEC_VOLATILE}}, | |
1218 | */ | |
f5a60074 | 1219 | |
367e2ab3 | 1220 | static int |
92643d95 | 1221 | some_small_symbolic_operand_1 (rtx *px, void *data ATTRIBUTE_UNUSED) |
367e2ab3 | 1222 | { |
1223 | rtx x = *px; | |
f5a60074 | 1224 | |
792433e3 | 1225 | /* Don't re-split. */ |
1226 | if (GET_CODE (x) == LO_SUM) | |
1227 | return -1; | |
367e2ab3 | 1228 | |
792433e3 | 1229 | return small_symbolic_operand (x, Pmode) != 0; |
f5a60074 | 1230 | } |
1231 | ||
92643d95 | 1232 | int |
1233 | some_small_symbolic_operand (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED) | |
f5a60074 | 1234 | { |
92643d95 | 1235 | return for_each_rtx (&x, some_small_symbolic_operand_1, NULL); |
367e2ab3 | 1236 | } |
f5a60074 | 1237 | |
367e2ab3 | 1238 | static int |
92643d95 | 1239 | split_small_symbolic_operand_1 (rtx *px, void *data ATTRIBUTE_UNUSED) |
367e2ab3 | 1240 | { |
1241 | rtx x = *px; | |
443bb1a6 | 1242 | |
792433e3 | 1243 | /* Don't re-split. */ |
1244 | if (GET_CODE (x) == LO_SUM) | |
1245 | return -1; | |
f5a60074 | 1246 | |
367e2ab3 | 1247 | if (small_symbolic_operand (x, Pmode)) |
1248 | { | |
1249 | x = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, x); | |
1250 | *px = x; | |
792433e3 | 1251 | return -1; |
367e2ab3 | 1252 | } |
1253 | ||
792433e3 | 1254 | return 0; |
f5a60074 | 1255 | } |
1256 | ||
92643d95 | 1257 | rtx |
1258 | split_small_symbolic_operand (rtx x) | |
1259 | { | |
1260 | x = copy_insn (x); | |
1261 | for_each_rtx (&x, split_small_symbolic_operand_1, NULL); | |
1262 | return x; | |
1263 | } | |
1264 | ||
2f58af60 | 1265 | /* Indicate that INSN cannot be duplicated. This is true for any insn |
1266 | that we've marked with gpdisp relocs, since those have to stay in | |
1267 | 1-1 correspondence with one another. | |
1268 | ||
5910bb95 | 1269 | Technically we could copy them if we could set up a mapping from one |
2f58af60 | 1270 | sequence number to another, across the set of insns to be duplicated. |
1271 | This seems overly complicated and error-prone since interblock motion | |
b55f2ed8 | 1272 | from sched-ebb could move one of the pair of insns to a different block. |
1273 | ||
1274 | Also cannot allow jsr insns to be duplicated. If they throw exceptions, | |
1275 | then they'll be in a different block from their ldgp. Which could lead | |
1276 | the bb reorder code to think that it would be ok to copy just the block | |
1277 | containing the call and branch to the block containing the ldgp. */ | |
2f58af60 | 1278 | |
1279 | static bool | |
92643d95 | 1280 | alpha_cannot_copy_insn_p (rtx insn) |
2f58af60 | 1281 | { |
2f58af60 | 1282 | if (!reload_completed || !TARGET_EXPLICIT_RELOCS) |
1283 | return false; | |
b55f2ed8 | 1284 | if (recog_memoized (insn) >= 0) |
1285 | return get_attr_cannot_copy (insn); | |
1286 | else | |
2f58af60 | 1287 | return false; |
2f58af60 | 1288 | } |
1289 | ||
9e7454d0 | 1290 | |
0d50f0b7 | 1291 | /* Try a machine-dependent way of reloading an illegitimate address |
1292 | operand. If we find one, push the reload and return the new rtx. */ | |
9e7454d0 | 1293 | |
0d50f0b7 | 1294 | rtx |
92643d95 | 1295 | alpha_legitimize_reload_address (rtx x, |
1296 | enum machine_mode mode ATTRIBUTE_UNUSED, | |
1297 | int opnum, int type, | |
1298 | int ind_levels ATTRIBUTE_UNUSED) | |
0d50f0b7 | 1299 | { |
1300 | /* We must recognize output that we have already generated ourselves. */ | |
1301 | if (GET_CODE (x) == PLUS | |
1302 | && GET_CODE (XEXP (x, 0)) == PLUS | |
1303 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG | |
1304 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
1305 | && GET_CODE (XEXP (x, 1)) == CONST_INT) | |
1306 | { | |
1307 | push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL, | |
1308 | BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0, | |
1309 | opnum, type); | |
1310 | return x; | |
1311 | } | |
1312 | ||
1313 | /* We wish to handle large displacements off a base register by | |
1314 | splitting the addend across an ldah and the mem insn. This | |
1315 | cuts number of extra insns needed from 3 to 1. */ | |
1316 | if (GET_CODE (x) == PLUS | |
1317 | && GET_CODE (XEXP (x, 0)) == REG | |
1318 | && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER | |
1319 | && REGNO_OK_FOR_BASE_P (REGNO (XEXP (x, 0))) | |
1320 | && GET_CODE (XEXP (x, 1)) == CONST_INT) | |
1321 | { | |
1322 | HOST_WIDE_INT val = INTVAL (XEXP (x, 1)); | |
1323 | HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; | |
1324 | HOST_WIDE_INT high | |
1325 | = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000; | |
1326 | ||
1327 | /* Check for 32-bit overflow. */ | |
1328 | if (high + low != val) | |
1329 | return NULL_RTX; | |
1330 | ||
1331 | /* Reload the high part into a base reg; leave the low part | |
1332 | in the mem directly. */ | |
1333 | x = gen_rtx_PLUS (GET_MODE (x), | |
1334 | gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0), | |
1335 | GEN_INT (high)), | |
1336 | GEN_INT (low)); | |
1337 | ||
1338 | push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL, | |
1339 | BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0, | |
1340 | opnum, type); | |
1341 | return x; | |
1342 | } | |
1343 | ||
1344 | return NULL_RTX; | |
1345 | } | |
1346 | \f | |
fab7adbf | 1347 | /* Compute a (partial) cost for rtx X. Return true if the complete |
1348 | cost has been computed, and false if subexpressions should be | |
1349 | scanned. In either case, *TOTAL contains the cost result. */ | |
1350 | ||
1351 | static bool | |
92643d95 | 1352 | alpha_rtx_costs (rtx x, int code, int outer_code, int *total) |
fab7adbf | 1353 | { |
1354 | enum machine_mode mode = GET_MODE (x); | |
1355 | bool float_mode_p = FLOAT_MODE_P (mode); | |
d7cf2331 | 1356 | const struct alpha_rtx_cost_data *cost_data; |
1357 | ||
1358 | if (optimize_size) | |
1359 | cost_data = &alpha_rtx_cost_size; | |
1360 | else | |
1361 | cost_data = &alpha_rtx_cost_data[alpha_cpu]; | |
fab7adbf | 1362 | |
1363 | switch (code) | |
1364 | { | |
d7cf2331 | 1365 | case CONST_INT: |
fab7adbf | 1366 | /* If this is an 8-bit constant, return zero since it can be used |
1367 | nearly anywhere with no cost. If it is a valid operand for an | |
1368 | ADD or AND, likewise return 0 if we know it will be used in that | |
1369 | context. Otherwise, return 2 since it might be used there later. | |
1370 | All other constants take at least two insns. */ | |
fab7adbf | 1371 | if (INTVAL (x) >= 0 && INTVAL (x) < 256) |
1372 | { | |
1373 | *total = 0; | |
1374 | return true; | |
1375 | } | |
8e262b5e | 1376 | /* FALLTHRU */ |
fab7adbf | 1377 | |
1378 | case CONST_DOUBLE: | |
1379 | if (x == CONST0_RTX (mode)) | |
1380 | *total = 0; | |
1381 | else if ((outer_code == PLUS && add_operand (x, VOIDmode)) | |
1382 | || (outer_code == AND && and_operand (x, VOIDmode))) | |
1383 | *total = 0; | |
1384 | else if (add_operand (x, VOIDmode) || and_operand (x, VOIDmode)) | |
1385 | *total = 2; | |
1386 | else | |
1387 | *total = COSTS_N_INSNS (2); | |
1388 | return true; | |
9e7454d0 | 1389 | |
fab7adbf | 1390 | case CONST: |
1391 | case SYMBOL_REF: | |
1392 | case LABEL_REF: | |
1393 | if (TARGET_EXPLICIT_RELOCS && small_symbolic_operand (x, VOIDmode)) | |
1394 | *total = COSTS_N_INSNS (outer_code != MEM); | |
1395 | else if (TARGET_EXPLICIT_RELOCS && local_symbolic_operand (x, VOIDmode)) | |
1396 | *total = COSTS_N_INSNS (1 + (outer_code != MEM)); | |
1397 | else if (tls_symbolic_operand_type (x)) | |
1398 | /* Estimate of cost for call_pal rduniq. */ | |
d7cf2331 | 1399 | /* ??? How many insns do we emit here? More than one... */ |
fab7adbf | 1400 | *total = COSTS_N_INSNS (15); |
1401 | else | |
1402 | /* Otherwise we do a load from the GOT. */ | |
d7cf2331 | 1403 | *total = COSTS_N_INSNS (optimize_size ? 1 : alpha_memory_latency); |
fab7adbf | 1404 | return true; |
9e7454d0 | 1405 | |
fab7adbf | 1406 | case PLUS: |
1407 | case MINUS: | |
1408 | if (float_mode_p) | |
d7cf2331 | 1409 | *total = cost_data->fp_add; |
fab7adbf | 1410 | else if (GET_CODE (XEXP (x, 0)) == MULT |
1411 | && const48_operand (XEXP (XEXP (x, 0), 1), VOIDmode)) | |
1412 | { | |
1413 | *total = (rtx_cost (XEXP (XEXP (x, 0), 0), outer_code) | |
be8c6d9c | 1414 | + rtx_cost (XEXP (x, 1), outer_code) + COSTS_N_INSNS (1)); |
fab7adbf | 1415 | return true; |
1416 | } | |
1417 | return false; | |
1418 | ||
1419 | case MULT: | |
1420 | if (float_mode_p) | |
d7cf2331 | 1421 | *total = cost_data->fp_mult; |
fab7adbf | 1422 | else if (mode == DImode) |
d7cf2331 | 1423 | *total = cost_data->int_mult_di; |
fab7adbf | 1424 | else |
d7cf2331 | 1425 | *total = cost_data->int_mult_si; |
fab7adbf | 1426 | return false; |
1427 | ||
1428 | case ASHIFT: | |
1429 | if (GET_CODE (XEXP (x, 1)) == CONST_INT | |
1430 | && INTVAL (XEXP (x, 1)) <= 3) | |
1431 | { | |
1432 | *total = COSTS_N_INSNS (1); | |
1433 | return false; | |
1434 | } | |
8e262b5e | 1435 | /* FALLTHRU */ |
fab7adbf | 1436 | |
1437 | case ASHIFTRT: | |
1438 | case LSHIFTRT: | |
d7cf2331 | 1439 | *total = cost_data->int_shift; |
fab7adbf | 1440 | return false; |
1441 | ||
1442 | case IF_THEN_ELSE: | |
1443 | if (float_mode_p) | |
d7cf2331 | 1444 | *total = cost_data->fp_add; |
fab7adbf | 1445 | else |
d7cf2331 | 1446 | *total = cost_data->int_cmov; |
fab7adbf | 1447 | return false; |
1448 | ||
1449 | case DIV: | |
1450 | case UDIV: | |
1451 | case MOD: | |
1452 | case UMOD: | |
1453 | if (!float_mode_p) | |
d7cf2331 | 1454 | *total = cost_data->int_div; |
fab7adbf | 1455 | else if (mode == SFmode) |
d7cf2331 | 1456 | *total = cost_data->fp_div_sf; |
fab7adbf | 1457 | else |
d7cf2331 | 1458 | *total = cost_data->fp_div_df; |
fab7adbf | 1459 | return false; |
1460 | ||
1461 | case MEM: | |
d7cf2331 | 1462 | *total = COSTS_N_INSNS (optimize_size ? 1 : alpha_memory_latency); |
fab7adbf | 1463 | return true; |
1464 | ||
1465 | case NEG: | |
1466 | if (! float_mode_p) | |
1467 | { | |
1468 | *total = COSTS_N_INSNS (1); | |
1469 | return false; | |
1470 | } | |
8e262b5e | 1471 | /* FALLTHRU */ |
fab7adbf | 1472 | |
1473 | case ABS: | |
1474 | if (! float_mode_p) | |
1475 | { | |
d7cf2331 | 1476 | *total = COSTS_N_INSNS (1) + cost_data->int_cmov; |
fab7adbf | 1477 | return false; |
1478 | } | |
8e262b5e | 1479 | /* FALLTHRU */ |
fab7adbf | 1480 | |
1481 | case FLOAT: | |
1482 | case UNSIGNED_FLOAT: | |
1483 | case FIX: | |
1484 | case UNSIGNED_FIX: | |
1485 | case FLOAT_EXTEND: | |
1486 | case FLOAT_TRUNCATE: | |
d7cf2331 | 1487 | *total = cost_data->fp_add; |
fab7adbf | 1488 | return false; |
1489 | ||
1490 | default: | |
1491 | return false; | |
1492 | } | |
1493 | } | |
1494 | \f | |
bf2a98b3 | 1495 | /* REF is an alignable memory location. Place an aligned SImode |
1496 | reference into *PALIGNED_MEM and the number of bits to shift into | |
a99a652b | 1497 | *PBITNUM. SCRATCH is a free register for use in reloading out |
1498 | of range stack slots. */ | |
bf2a98b3 | 1499 | |
1500 | void | |
92643d95 | 1501 | get_aligned_mem (rtx ref, rtx *paligned_mem, rtx *pbitnum) |
bf2a98b3 | 1502 | { |
1503 | rtx base; | |
1504 | HOST_WIDE_INT offset = 0; | |
1505 | ||
cc215844 | 1506 | if (GET_CODE (ref) != MEM) |
1507 | abort (); | |
bf2a98b3 | 1508 | |
cc215844 | 1509 | if (reload_in_progress |
1510 | && ! memory_address_p (GET_MODE (ref), XEXP (ref, 0))) | |
a99a652b | 1511 | { |
cc215844 | 1512 | base = find_replacement (&XEXP (ref, 0)); |
1513 | ||
1514 | if (! memory_address_p (GET_MODE (ref), base)) | |
1515 | abort (); | |
a99a652b | 1516 | } |
bf2a98b3 | 1517 | else |
a99a652b | 1518 | { |
a99a652b | 1519 | base = XEXP (ref, 0); |
1520 | } | |
bf2a98b3 | 1521 | |
1522 | if (GET_CODE (base) == PLUS) | |
1523 | offset += INTVAL (XEXP (base, 1)), base = XEXP (base, 0); | |
1524 | ||
8259ab07 | 1525 | *paligned_mem |
1526 | = widen_memory_access (ref, SImode, (offset & ~3) - offset); | |
bf2a98b3 | 1527 | |
9caef960 | 1528 | if (WORDS_BIG_ENDIAN) |
1529 | *pbitnum = GEN_INT (32 - (GET_MODE_BITSIZE (GET_MODE (ref)) | |
1530 | + (offset & 3) * 8)); | |
1531 | else | |
1532 | *pbitnum = GEN_INT ((offset & 3) * 8); | |
bf2a98b3 | 1533 | } |
1534 | ||
9e7454d0 | 1535 | /* Similar, but just get the address. Handle the two reload cases. |
b044f41c | 1536 | Add EXTRA_OFFSET to the address we return. */ |
bf2a98b3 | 1537 | |
1538 | rtx | |
92643d95 | 1539 | get_unaligned_address (rtx ref, int extra_offset) |
bf2a98b3 | 1540 | { |
1541 | rtx base; | |
1542 | HOST_WIDE_INT offset = 0; | |
1543 | ||
cc215844 | 1544 | if (GET_CODE (ref) != MEM) |
1545 | abort (); | |
bf2a98b3 | 1546 | |
cc215844 | 1547 | if (reload_in_progress |
1548 | && ! memory_address_p (GET_MODE (ref), XEXP (ref, 0))) | |
a99a652b | 1549 | { |
a99a652b | 1550 | base = find_replacement (&XEXP (ref, 0)); |
cc215844 | 1551 | |
1552 | if (! memory_address_p (GET_MODE (ref), base)) | |
1553 | abort (); | |
a99a652b | 1554 | } |
bf2a98b3 | 1555 | else |
a99a652b | 1556 | { |
a99a652b | 1557 | base = XEXP (ref, 0); |
1558 | } | |
bf2a98b3 | 1559 | |
1560 | if (GET_CODE (base) == PLUS) | |
1561 | offset += INTVAL (XEXP (base, 1)), base = XEXP (base, 0); | |
1562 | ||
b044f41c | 1563 | return plus_constant (base, offset + extra_offset); |
bf2a98b3 | 1564 | } |
14f7bc98 | 1565 | |
f5a60074 | 1566 | /* On the Alpha, all (non-symbolic) constants except zero go into |
9e7454d0 | 1567 | a floating-point register via memory. Note that we cannot |
f5a60074 | 1568 | return anything that is not a subset of CLASS, and that some |
1569 | symbolic constants cannot be dropped to memory. */ | |
1570 | ||
1571 | enum reg_class | |
92643d95 | 1572 | alpha_preferred_reload_class(rtx x, enum reg_class class) |
f5a60074 | 1573 | { |
1574 | /* Zero is present in any register class. */ | |
1575 | if (x == CONST0_RTX (GET_MODE (x))) | |
1576 | return class; | |
1577 | ||
1578 | /* These sorts of constants we can easily drop to memory. */ | |
1579 | if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE) | |
1580 | { | |
1581 | if (class == FLOAT_REGS) | |
1582 | return NO_REGS; | |
1583 | if (class == ALL_REGS) | |
1584 | return GENERAL_REGS; | |
1585 | return class; | |
1586 | } | |
1587 | ||
1588 | /* All other kinds of constants should not (and in the case of HIGH | |
1589 | cannot) be dropped to memory -- instead we use a GENERAL_REGS | |
1590 | secondary reload. */ | |
1591 | if (CONSTANT_P (x)) | |
1592 | return (class == ALL_REGS ? GENERAL_REGS : class); | |
1593 | ||
1594 | return class; | |
1595 | } | |
1596 | ||
14f7bc98 | 1597 | /* Loading and storing HImode or QImode values to and from memory |
1598 | usually requires a scratch register. The exceptions are loading | |
1599 | QImode and HImode from an aligned address to a general register | |
9e7454d0 | 1600 | unless byte instructions are permitted. |
14f7bc98 | 1601 | |
1602 | We also cannot load an unaligned address or a paradoxical SUBREG | |
9e7454d0 | 1603 | into an FP register. |
14f7bc98 | 1604 | |
1605 | We also cannot do integral arithmetic into FP regs, as might result | |
1606 | from register elimination into a DImode fp register. */ | |
1607 | ||
1608 | enum reg_class | |
92643d95 | 1609 | secondary_reload_class (enum reg_class class, enum machine_mode mode, |
1610 | rtx x, int in) | |
14f7bc98 | 1611 | { |
d60e9bbd | 1612 | if ((mode == QImode || mode == HImode) && ! TARGET_BWX) |
d2494d49 | 1613 | { |
d60e9bbd | 1614 | if (GET_CODE (x) == MEM |
1615 | || (GET_CODE (x) == REG && REGNO (x) >= FIRST_PSEUDO_REGISTER) | |
1616 | || (GET_CODE (x) == SUBREG | |
1617 | && (GET_CODE (SUBREG_REG (x)) == MEM | |
1618 | || (GET_CODE (SUBREG_REG (x)) == REG | |
1619 | && REGNO (SUBREG_REG (x)) >= FIRST_PSEUDO_REGISTER)))) | |
d2494d49 | 1620 | { |
1621 | if (!in || !aligned_memory_operand(x, mode)) | |
1622 | return GENERAL_REGS; | |
1623 | } | |
1624 | } | |
14f7bc98 | 1625 | |
1626 | if (class == FLOAT_REGS) | |
1627 | { | |
1628 | if (GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) == AND) | |
1629 | return GENERAL_REGS; | |
1630 | ||
1631 | if (GET_CODE (x) == SUBREG | |
1632 | && (GET_MODE_SIZE (GET_MODE (x)) | |
1633 | > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))) | |
1634 | return GENERAL_REGS; | |
1635 | ||
1f0ce6a6 | 1636 | if (in && INTEGRAL_MODE_P (mode) |
1637 | && ! (memory_operand (x, mode) || x == const0_rtx)) | |
14f7bc98 | 1638 | return GENERAL_REGS; |
1639 | } | |
1640 | ||
1641 | return NO_REGS; | |
1642 | } | |
bf2a98b3 | 1643 | \f |
1644 | /* Subfunction of the following function. Update the flags of any MEM | |
1645 | found in part of X. */ | |
1646 | ||
b04fab2a | 1647 | static int |
1648 | alpha_set_memflags_1 (rtx *xp, void *data) | |
bf2a98b3 | 1649 | { |
b04fab2a | 1650 | rtx x = *xp, orig = (rtx) data; |
bf2a98b3 | 1651 | |
b04fab2a | 1652 | if (GET_CODE (x) != MEM) |
1653 | return 0; | |
bf2a98b3 | 1654 | |
b04fab2a | 1655 | MEM_VOLATILE_P (x) = MEM_VOLATILE_P (orig); |
1656 | MEM_IN_STRUCT_P (x) = MEM_IN_STRUCT_P (orig); | |
1657 | MEM_SCALAR_P (x) = MEM_SCALAR_P (orig); | |
1658 | MEM_NOTRAP_P (x) = MEM_NOTRAP_P (orig); | |
1659 | MEM_READONLY_P (x) = MEM_READONLY_P (orig); | |
bf2a98b3 | 1660 | |
b04fab2a | 1661 | /* Sadly, we cannot use alias sets because the extra aliasing |
1662 | produced by the AND interferes. Given that two-byte quantities | |
1663 | are the only thing we would be able to differentiate anyway, | |
1664 | there does not seem to be any point in convoluting the early | |
1665 | out of the alias check. */ | |
99c14947 | 1666 | |
b04fab2a | 1667 | return -1; |
bf2a98b3 | 1668 | } |
1669 | ||
31d3e01c | 1670 | /* Given INSN, which is an INSN list or the PATTERN of a single insn |
1671 | generated to perform a memory operation, look for any MEMs in either | |
1672 | a SET_DEST or a SET_SRC and copy the in-struct, unchanging, and | |
1673 | volatile flags from REF into each of the MEMs found. If REF is not | |
1674 | a MEM, don't do anything. */ | |
bf2a98b3 | 1675 | |
1676 | void | |
92643d95 | 1677 | alpha_set_memflags (rtx insn, rtx ref) |
bf2a98b3 | 1678 | { |
b04fab2a | 1679 | rtx *base_ptr; |
849674a3 | 1680 | |
1681 | if (GET_CODE (ref) != MEM) | |
bf2a98b3 | 1682 | return; |
1683 | ||
9e7454d0 | 1684 | /* This is only called from alpha.md, after having had something |
849674a3 | 1685 | generated from one of the insn patterns. So if everything is |
1686 | zero, the pattern is already up-to-date. */ | |
b04fab2a | 1687 | if (!MEM_VOLATILE_P (ref) |
1688 | && !MEM_IN_STRUCT_P (ref) | |
1689 | && !MEM_SCALAR_P (ref) | |
1690 | && !MEM_NOTRAP_P (ref) | |
1691 | && !MEM_READONLY_P (ref)) | |
849674a3 | 1692 | return; |
1693 | ||
b04fab2a | 1694 | if (INSN_P (insn)) |
1695 | base_ptr = &PATTERN (insn); | |
1696 | else | |
1697 | base_ptr = &insn; | |
1698 | for_each_rtx (base_ptr, alpha_set_memflags_1, (void *) ref); | |
bf2a98b3 | 1699 | } |
1700 | \f | |
92643d95 | 1701 | /* Internal routine for alpha_emit_set_const to check for N or below insns. */ |
6f86cb15 | 1702 | |
1703 | static rtx | |
92643d95 | 1704 | alpha_emit_set_const_1 (rtx target, enum machine_mode mode, |
1705 | HOST_WIDE_INT c, int n) | |
bf2a98b3 | 1706 | { |
bdb19034 | 1707 | HOST_WIDE_INT new; |
bf2a98b3 | 1708 | int i, bits; |
ea5db00c | 1709 | /* Use a pseudo if highly optimizing and still generating RTL. */ |
1710 | rtx subtarget | |
d2422fc2 | 1711 | = (flag_expensive_optimizations && !no_new_pseudos ? 0 : target); |
301416af | 1712 | rtx temp, insn; |
bf2a98b3 | 1713 | |
bf2a98b3 | 1714 | /* If this is a sign-extended 32-bit constant, we can do this in at most |
1715 | three insns, so do it if we have enough insns left. We always have | |
65abff06 | 1716 | a sign-extended 32-bit constant when compiling on a narrow machine. */ |
bf2a98b3 | 1717 | |
3bc2043a | 1718 | if (HOST_BITS_PER_WIDE_INT != 64 |
1719 | || c >> 31 == -1 || c >> 31 == 0) | |
bf2a98b3 | 1720 | { |
bdb19034 | 1721 | HOST_WIDE_INT low = ((c & 0xffff) ^ 0x8000) - 0x8000; |
bf2a98b3 | 1722 | HOST_WIDE_INT tmp1 = c - low; |
bdb19034 | 1723 | HOST_WIDE_INT high = (((tmp1 >> 16) & 0xffff) ^ 0x8000) - 0x8000; |
bf2a98b3 | 1724 | HOST_WIDE_INT extra = 0; |
1725 | ||
81d03ebd | 1726 | /* If HIGH will be interpreted as negative but the constant is |
1727 | positive, we must adjust it to do two ldha insns. */ | |
1728 | ||
1729 | if ((high & 0x8000) != 0 && c >= 0) | |
bf2a98b3 | 1730 | { |
1731 | extra = 0x4000; | |
1732 | tmp1 -= 0x40000000; | |
1733 | high = ((tmp1 >> 16) & 0xffff) - 2 * ((tmp1 >> 16) & 0x8000); | |
1734 | } | |
1735 | ||
1736 | if (c == low || (low == 0 && extra == 0)) | |
3bc2043a | 1737 | { |
1738 | /* We used to use copy_to_suggested_reg (GEN_INT (c), target, mode) | |
1739 | but that meant that we can't handle INT_MIN on 32-bit machines | |
9e7454d0 | 1740 | (like NT/Alpha), because we recurse indefinitely through |
3bc2043a | 1741 | emit_move_insn to gen_movdi. So instead, since we know exactly |
1742 | what we want, create it explicitly. */ | |
1743 | ||
1744 | if (target == NULL) | |
1745 | target = gen_reg_rtx (mode); | |
941522d6 | 1746 | emit_insn (gen_rtx_SET (VOIDmode, target, GEN_INT (c))); |
3bc2043a | 1747 | return target; |
1748 | } | |
6f86cb15 | 1749 | else if (n >= 2 + (extra != 0)) |
bf2a98b3 | 1750 | { |
5b952578 | 1751 | if (no_new_pseudos) |
1752 | { | |
1753 | emit_insn (gen_rtx_SET (VOIDmode, target, GEN_INT (high << 16))); | |
1754 | temp = target; | |
1755 | } | |
1756 | else | |
1757 | temp = copy_to_suggested_reg (GEN_INT (high << 16), | |
1758 | subtarget, mode); | |
ea5db00c | 1759 | |
301416af | 1760 | /* As of 2002-02-23, addsi3 is only available when not optimizing. |
1761 | This means that if we go through expand_binop, we'll try to | |
1762 | generate extensions, etc, which will require new pseudos, which | |
1763 | will fail during some split phases. The SImode add patterns | |
1764 | still exist, but are not named. So build the insns by hand. */ | |
1765 | ||
bf2a98b3 | 1766 | if (extra != 0) |
301416af | 1767 | { |
1768 | if (! subtarget) | |
1769 | subtarget = gen_reg_rtx (mode); | |
1770 | insn = gen_rtx_PLUS (mode, temp, GEN_INT (extra << 16)); | |
1771 | insn = gen_rtx_SET (VOIDmode, subtarget, insn); | |
1772 | emit_insn (insn); | |
b8585446 | 1773 | temp = subtarget; |
301416af | 1774 | } |
bf2a98b3 | 1775 | |
301416af | 1776 | if (target == NULL) |
1777 | target = gen_reg_rtx (mode); | |
1778 | insn = gen_rtx_PLUS (mode, temp, GEN_INT (low)); | |
1779 | insn = gen_rtx_SET (VOIDmode, target, insn); | |
1780 | emit_insn (insn); | |
1781 | return target; | |
bf2a98b3 | 1782 | } |
1783 | } | |
1784 | ||
dacd345b | 1785 | /* If we couldn't do it that way, try some other methods. But if we have |
07014ed9 | 1786 | no instructions left, don't bother. Likewise, if this is SImode and |
1787 | we can't make pseudos, we can't do anything since the expand_binop | |
1788 | and expand_unop calls will widen and try to make pseudos. */ | |
bf2a98b3 | 1789 | |
d2422fc2 | 1790 | if (n == 1 || (mode == SImode && no_new_pseudos)) |
bf2a98b3 | 1791 | return 0; |
1792 | ||
dacd345b | 1793 | /* Next, see if we can load a related constant and then shift and possibly |
bf2a98b3 | 1794 | negate it to get the constant we want. Try this once each increasing |
1795 | numbers of insns. */ | |
1796 | ||
1797 | for (i = 1; i < n; i++) | |
1798 | { | |
bdb19034 | 1799 | /* First, see if minus some low bits, we've an easy load of |
1800 | high bits. */ | |
1801 | ||
1802 | new = ((c & 0xffff) ^ 0x8000) - 0x8000; | |
1803 | if (new != 0 | |
1804 | && (temp = alpha_emit_set_const (subtarget, mode, c - new, i)) != 0) | |
1805 | return expand_binop (mode, add_optab, temp, GEN_INT (new), | |
1806 | target, 0, OPTAB_WIDEN); | |
1807 | ||
1808 | /* Next try complementing. */ | |
ea5db00c | 1809 | if ((temp = alpha_emit_set_const (subtarget, mode, ~ c, i)) != 0) |
1810 | return expand_unop (mode, one_cmpl_optab, temp, target, 0); | |
bf2a98b3 | 1811 | |
ea5db00c | 1812 | /* Next try to form a constant and do a left shift. We can do this |
bf2a98b3 | 1813 | if some low-order bits are zero; the exact_log2 call below tells |
1814 | us that information. The bits we are shifting out could be any | |
1815 | value, but here we'll just try the 0- and sign-extended forms of | |
1816 | the constant. To try to increase the chance of having the same | |
1817 | constant in more than one insn, start at the highest number of | |
1818 | bits to shift, but try all possibilities in case a ZAPNOT will | |
1819 | be useful. */ | |
1820 | ||
1821 | if ((bits = exact_log2 (c & - c)) > 0) | |
1822 | for (; bits > 0; bits--) | |
dacd345b | 1823 | if ((temp = (alpha_emit_set_const |
bdb19034 | 1824 | (subtarget, mode, c >> bits, i))) != 0 |
ea5db00c | 1825 | || ((temp = (alpha_emit_set_const |
1826 | (subtarget, mode, | |
1827 | ((unsigned HOST_WIDE_INT) c) >> bits, i))) | |
1828 | != 0)) | |
1829 | return expand_binop (mode, ashl_optab, temp, GEN_INT (bits), | |
1830 | target, 0, OPTAB_WIDEN); | |
bf2a98b3 | 1831 | |
1832 | /* Now try high-order zero bits. Here we try the shifted-in bits as | |
066efb8d | 1833 | all zero and all ones. Be careful to avoid shifting outside the |
1834 | mode and to avoid shifting outside the host wide int size. */ | |
3bc2043a | 1835 | /* On narrow hosts, don't shift a 1 into the high bit, since we'll |
1836 | confuse the recursive call and set all of the high 32 bits. */ | |
bf2a98b3 | 1837 | |
066efb8d | 1838 | if ((bits = (MIN (HOST_BITS_PER_WIDE_INT, GET_MODE_SIZE (mode) * 8) |
3bc2043a | 1839 | - floor_log2 (c) - 1 - (HOST_BITS_PER_WIDE_INT < 64))) > 0) |
bf2a98b3 | 1840 | for (; bits > 0; bits--) |
ea5db00c | 1841 | if ((temp = alpha_emit_set_const (subtarget, mode, |
1842 | c << bits, i)) != 0 | |
1843 | || ((temp = (alpha_emit_set_const | |
1844 | (subtarget, mode, | |
1845 | ((c << bits) | (((HOST_WIDE_INT) 1 << bits) - 1)), | |
1846 | i))) | |
1847 | != 0)) | |
1848 | return expand_binop (mode, lshr_optab, temp, GEN_INT (bits), | |
066efb8d | 1849 | target, 1, OPTAB_WIDEN); |
bf2a98b3 | 1850 | |
1851 | /* Now try high-order 1 bits. We get that with a sign-extension. | |
066efb8d | 1852 | But one bit isn't enough here. Be careful to avoid shifting outside |
65abff06 | 1853 | the mode and to avoid shifting outside the host wide int size. */ |
9caef960 | 1854 | |
066efb8d | 1855 | if ((bits = (MIN (HOST_BITS_PER_WIDE_INT, GET_MODE_SIZE (mode) * 8) |
1856 | - floor_log2 (~ c) - 2)) > 0) | |
bf2a98b3 | 1857 | for (; bits > 0; bits--) |
ea5db00c | 1858 | if ((temp = alpha_emit_set_const (subtarget, mode, |
1859 | c << bits, i)) != 0 | |
1860 | || ((temp = (alpha_emit_set_const | |
1861 | (subtarget, mode, | |
1862 | ((c << bits) | (((HOST_WIDE_INT) 1 << bits) - 1)), | |
1863 | i))) | |
1864 | != 0)) | |
1865 | return expand_binop (mode, ashr_optab, temp, GEN_INT (bits), | |
1866 | target, 0, OPTAB_WIDEN); | |
bf2a98b3 | 1867 | } |
1868 | ||
bdb19034 | 1869 | #if HOST_BITS_PER_WIDE_INT == 64 |
1870 | /* Finally, see if can load a value into the target that is the same as the | |
1871 | constant except that all bytes that are 0 are changed to be 0xff. If we | |
1872 | can, then we can do a ZAPNOT to obtain the desired constant. */ | |
1873 | ||
1874 | new = c; | |
1875 | for (i = 0; i < 64; i += 8) | |
1876 | if ((new & ((HOST_WIDE_INT) 0xff << i)) == 0) | |
1877 | new |= (HOST_WIDE_INT) 0xff << i; | |
e52799e9 | 1878 | |
bdb19034 | 1879 | /* We are only called for SImode and DImode. If this is SImode, ensure that |
1880 | we are sign extended to a full word. */ | |
1881 | ||
1882 | if (mode == SImode) | |
1883 | new = ((new & 0xffffffff) ^ 0x80000000) - 0x80000000; | |
1884 | ||
1885 | if (new != c && new != -1 | |
1886 | && (temp = alpha_emit_set_const (subtarget, mode, new, n - 1)) != 0) | |
1887 | return expand_binop (mode, and_optab, temp, GEN_INT (c | ~ new), | |
e52799e9 | 1888 | target, 0, OPTAB_WIDEN); |
bdb19034 | 1889 | #endif |
e52799e9 | 1890 | |
bf2a98b3 | 1891 | return 0; |
1892 | } | |
996a379d | 1893 | |
92643d95 | 1894 | /* Try to output insns to set TARGET equal to the constant C if it can be |
1895 | done in less than N insns. Do all computations in MODE. Returns the place | |
1896 | where the output has been placed if it can be done and the insns have been | |
1897 | emitted. If it would take more than N insns, zero is returned and no | |
1898 | insns and emitted. */ | |
1899 | ||
1900 | rtx | |
1901 | alpha_emit_set_const (rtx target, enum machine_mode mode, | |
1902 | HOST_WIDE_INT c, int n) | |
1903 | { | |
1904 | rtx result = 0; | |
1905 | rtx orig_target = target; | |
1906 | int i; | |
1907 | ||
1908 | /* If we can't make any pseudos, TARGET is an SImode hard register, we | |
1909 | can't load this constant in one insn, do this in DImode. */ | |
1910 | if (no_new_pseudos && mode == SImode | |
1911 | && GET_CODE (target) == REG && REGNO (target) < FIRST_PSEUDO_REGISTER | |
1912 | && (result = alpha_emit_set_const_1 (target, mode, c, 1)) == 0) | |
1913 | { | |
1914 | target = gen_lowpart (DImode, target); | |
1915 | mode = DImode; | |
1916 | } | |
1917 | ||
1918 | /* Try 1 insn, then 2, then up to N. */ | |
1919 | for (i = 1; i <= n; i++) | |
1920 | { | |
1921 | result = alpha_emit_set_const_1 (target, mode, c, i); | |
1922 | if (result) | |
1923 | { | |
1924 | rtx insn = get_last_insn (); | |
1925 | rtx set = single_set (insn); | |
1926 | if (! CONSTANT_P (SET_SRC (set))) | |
1927 | set_unique_reg_note (get_last_insn (), REG_EQUAL, GEN_INT (c)); | |
1928 | break; | |
1929 | } | |
1930 | } | |
1931 | ||
1932 | /* Allow for the case where we changed the mode of TARGET. */ | |
1933 | if (result == target) | |
1934 | result = orig_target; | |
1935 | ||
1936 | return result; | |
1937 | } | |
1938 | ||
2612f626 | 1939 | /* Having failed to find a 3 insn sequence in alpha_emit_set_const, |
1940 | fall back to a straight forward decomposition. We do this to avoid | |
1941 | exponential run times encountered when looking for longer sequences | |
1942 | with alpha_emit_set_const. */ | |
1943 | ||
1944 | rtx | |
92643d95 | 1945 | alpha_emit_set_long_const (rtx target, HOST_WIDE_INT c1, HOST_WIDE_INT c2) |
2612f626 | 1946 | { |
2612f626 | 1947 | HOST_WIDE_INT d1, d2, d3, d4; |
2612f626 | 1948 | |
1949 | /* Decompose the entire word */ | |
af792316 | 1950 | #if HOST_BITS_PER_WIDE_INT >= 64 |
1951 | if (c2 != -(c1 < 0)) | |
1952 | abort (); | |
1953 | d1 = ((c1 & 0xffff) ^ 0x8000) - 0x8000; | |
1954 | c1 -= d1; | |
1955 | d2 = ((c1 & 0xffffffff) ^ 0x80000000) - 0x80000000; | |
1956 | c1 = (c1 - d2) >> 32; | |
1957 | d3 = ((c1 & 0xffff) ^ 0x8000) - 0x8000; | |
1958 | c1 -= d3; | |
1959 | d4 = ((c1 & 0xffffffff) ^ 0x80000000) - 0x80000000; | |
1960 | if (c1 != d4) | |
1961 | abort (); | |
1962 | #else | |
1963 | d1 = ((c1 & 0xffff) ^ 0x8000) - 0x8000; | |
1964 | c1 -= d1; | |
1965 | d2 = ((c1 & 0xffffffff) ^ 0x80000000) - 0x80000000; | |
1966 | if (c1 != d2) | |
1967 | abort (); | |
1968 | c2 += (d2 < 0); | |
1969 | d3 = ((c2 & 0xffff) ^ 0x8000) - 0x8000; | |
1970 | c2 -= d3; | |
1971 | d4 = ((c2 & 0xffffffff) ^ 0x80000000) - 0x80000000; | |
1972 | if (c2 != d4) | |
1973 | abort (); | |
1974 | #endif | |
2612f626 | 1975 | |
1976 | /* Construct the high word */ | |
af792316 | 1977 | if (d4) |
1978 | { | |
1979 | emit_move_insn (target, GEN_INT (d4)); | |
1980 | if (d3) | |
1981 | emit_move_insn (target, gen_rtx_PLUS (DImode, target, GEN_INT (d3))); | |
1982 | } | |
2612f626 | 1983 | else |
af792316 | 1984 | emit_move_insn (target, GEN_INT (d3)); |
2612f626 | 1985 | |
1986 | /* Shift it into place */ | |
af792316 | 1987 | emit_move_insn (target, gen_rtx_ASHIFT (DImode, target, GEN_INT (32))); |
2612f626 | 1988 | |
af792316 | 1989 | /* Add in the low bits. */ |
1990 | if (d2) | |
1991 | emit_move_insn (target, gen_rtx_PLUS (DImode, target, GEN_INT (d2))); | |
1992 | if (d1) | |
1993 | emit_move_insn (target, gen_rtx_PLUS (DImode, target, GEN_INT (d1))); | |
2612f626 | 1994 | |
af792316 | 1995 | return target; |
2612f626 | 1996 | } |
2612f626 | 1997 | |
cb6e3ae1 | 1998 | /* Expand a move instruction; return true if all work is done. |
1999 | We don't handle non-bwx subword loads here. */ | |
2000 | ||
2001 | bool | |
92643d95 | 2002 | alpha_expand_mov (enum machine_mode mode, rtx *operands) |
cb6e3ae1 | 2003 | { |
2004 | /* If the output is not a register, the input must be. */ | |
2005 | if (GET_CODE (operands[0]) == MEM | |
2006 | && ! reg_or_0_operand (operands[1], mode)) | |
2007 | operands[1] = force_reg (mode, operands[1]); | |
2008 | ||
f5a60074 | 2009 | /* Allow legitimize_address to perform some simplifications. */ |
62e050c6 | 2010 | if (mode == Pmode && symbolic_operand (operands[1], mode)) |
1f0ce6a6 | 2011 | { |
05b07808 | 2012 | rtx tmp; |
2013 | ||
05b07808 | 2014 | tmp = alpha_legitimize_address (operands[1], operands[0], mode); |
f5a60074 | 2015 | if (tmp) |
5dcb037d | 2016 | { |
5f7b9df8 | 2017 | if (tmp == operands[0]) |
2018 | return true; | |
f5a60074 | 2019 | operands[1] = tmp; |
8afb6db4 | 2020 | return false; |
2021 | } | |
1f0ce6a6 | 2022 | } |
2023 | ||
cb6e3ae1 | 2024 | /* Early out for non-constants and valid constants. */ |
2025 | if (! CONSTANT_P (operands[1]) || input_operand (operands[1], mode)) | |
2026 | return false; | |
2027 | ||
2028 | /* Split large integers. */ | |
2029 | if (GET_CODE (operands[1]) == CONST_INT | |
2030 | || GET_CODE (operands[1]) == CONST_DOUBLE) | |
2031 | { | |
2032 | HOST_WIDE_INT i0, i1; | |
d1bf99d0 | 2033 | rtx temp = NULL_RTX; |
cb6e3ae1 | 2034 | |
2035 | if (GET_CODE (operands[1]) == CONST_INT) | |
2036 | { | |
2037 | i0 = INTVAL (operands[1]); | |
2038 | i1 = -(i0 < 0); | |
2039 | } | |
2040 | else if (HOST_BITS_PER_WIDE_INT >= 64) | |
2041 | { | |
2042 | i0 = CONST_DOUBLE_LOW (operands[1]); | |
2043 | i1 = -(i0 < 0); | |
2044 | } | |
2045 | else | |
2046 | { | |
2047 | i0 = CONST_DOUBLE_LOW (operands[1]); | |
2048 | i1 = CONST_DOUBLE_HIGH (operands[1]); | |
2049 | } | |
2050 | ||
2051 | if (HOST_BITS_PER_WIDE_INT >= 64 || i1 == -(i0 < 0)) | |
2052 | temp = alpha_emit_set_const (operands[0], mode, i0, 3); | |
2053 | ||
2054 | if (!temp && TARGET_BUILD_CONSTANTS) | |
2055 | temp = alpha_emit_set_long_const (operands[0], i0, i1); | |
2056 | ||
2057 | if (temp) | |
2058 | { | |
2059 | if (rtx_equal_p (operands[0], temp)) | |
2060 | return true; | |
2061 | operands[1] = temp; | |
2062 | return false; | |
2063 | } | |
2064 | } | |
2065 | ||
2066 | /* Otherwise we've nothing left but to drop the thing to memory. */ | |
d18a1a2b | 2067 | operands[1] = force_const_mem (mode, operands[1]); |
cb6e3ae1 | 2068 | if (reload_in_progress) |
2069 | { | |
2070 | emit_move_insn (operands[0], XEXP (operands[1], 0)); | |
2071 | operands[1] = copy_rtx (operands[1]); | |
2072 | XEXP (operands[1], 0) = operands[0]; | |
2073 | } | |
2074 | else | |
2075 | operands[1] = validize_mem (operands[1]); | |
2076 | return false; | |
2077 | } | |
2078 | ||
2079 | /* Expand a non-bwx QImode or HImode move instruction; | |
2080 | return true if all work is done. */ | |
2081 | ||
2082 | bool | |
92643d95 | 2083 | alpha_expand_mov_nobwx (enum machine_mode mode, rtx *operands) |
cb6e3ae1 | 2084 | { |
2085 | /* If the output is not a register, the input must be. */ | |
2086 | if (GET_CODE (operands[0]) == MEM) | |
2087 | operands[1] = force_reg (mode, operands[1]); | |
2088 | ||
2089 | /* Handle four memory cases, unaligned and aligned for either the input | |
2090 | or the output. The only case where we can be called during reload is | |
2091 | for aligned loads; all other cases require temporaries. */ | |
2092 | ||
2093 | if (GET_CODE (operands[1]) == MEM | |
2094 | || (GET_CODE (operands[1]) == SUBREG | |
2095 | && GET_CODE (SUBREG_REG (operands[1])) == MEM) | |
2096 | || (reload_in_progress && GET_CODE (operands[1]) == REG | |
2097 | && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER) | |
2098 | || (reload_in_progress && GET_CODE (operands[1]) == SUBREG | |
2099 | && GET_CODE (SUBREG_REG (operands[1])) == REG | |
2100 | && REGNO (SUBREG_REG (operands[1])) >= FIRST_PSEUDO_REGISTER)) | |
2101 | { | |
2102 | if (aligned_memory_operand (operands[1], mode)) | |
2103 | { | |
2104 | if (reload_in_progress) | |
2105 | { | |
2106 | emit_insn ((mode == QImode | |
2107 | ? gen_reload_inqi_help | |
2108 | : gen_reload_inhi_help) | |
2109 | (operands[0], operands[1], | |
2110 | gen_rtx_REG (SImode, REGNO (operands[0])))); | |
2111 | } | |
2112 | else | |
2113 | { | |
2114 | rtx aligned_mem, bitnum; | |
2115 | rtx scratch = gen_reg_rtx (SImode); | |
d67e1866 | 2116 | rtx subtarget; |
2117 | bool copyout; | |
cb6e3ae1 | 2118 | |
2119 | get_aligned_mem (operands[1], &aligned_mem, &bitnum); | |
2120 | ||
d67e1866 | 2121 | subtarget = operands[0]; |
2122 | if (GET_CODE (subtarget) == REG) | |
2123 | subtarget = gen_lowpart (DImode, subtarget), copyout = false; | |
2124 | else | |
2125 | subtarget = gen_reg_rtx (DImode), copyout = true; | |
2126 | ||
cb6e3ae1 | 2127 | emit_insn ((mode == QImode |
2128 | ? gen_aligned_loadqi | |
2129 | : gen_aligned_loadhi) | |
d67e1866 | 2130 | (subtarget, aligned_mem, bitnum, scratch)); |
2131 | ||
2132 | if (copyout) | |
2133 | emit_move_insn (operands[0], gen_lowpart (mode, subtarget)); | |
cb6e3ae1 | 2134 | } |
2135 | } | |
2136 | else | |
2137 | { | |
2138 | /* Don't pass these as parameters since that makes the generated | |
2139 | code depend on parameter evaluation order which will cause | |
2140 | bootstrap failures. */ | |
2141 | ||
d67e1866 | 2142 | rtx temp1, temp2, seq, subtarget; |
2143 | bool copyout; | |
2144 | ||
2145 | temp1 = gen_reg_rtx (DImode); | |
2146 | temp2 = gen_reg_rtx (DImode); | |
cb6e3ae1 | 2147 | |
d67e1866 | 2148 | subtarget = operands[0]; |
2149 | if (GET_CODE (subtarget) == REG) | |
2150 | subtarget = gen_lowpart (DImode, subtarget), copyout = false; | |
2151 | else | |
2152 | subtarget = gen_reg_rtx (DImode), copyout = true; | |
2153 | ||
2154 | seq = ((mode == QImode | |
2155 | ? gen_unaligned_loadqi | |
2156 | : gen_unaligned_loadhi) | |
2157 | (subtarget, get_unaligned_address (operands[1], 0), | |
2158 | temp1, temp2)); | |
cb6e3ae1 | 2159 | alpha_set_memflags (seq, operands[1]); |
2160 | emit_insn (seq); | |
d67e1866 | 2161 | |
2162 | if (copyout) | |
2163 | emit_move_insn (operands[0], gen_lowpart (mode, subtarget)); | |
cb6e3ae1 | 2164 | } |
2165 | return true; | |
2166 | } | |
2167 | ||
2168 | if (GET_CODE (operands[0]) == MEM | |
2169 | || (GET_CODE (operands[0]) == SUBREG | |
2170 | && GET_CODE (SUBREG_REG (operands[0])) == MEM) | |
2171 | || (reload_in_progress && GET_CODE (operands[0]) == REG | |
2172 | && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER) | |
2173 | || (reload_in_progress && GET_CODE (operands[0]) == SUBREG | |
2174 | && GET_CODE (SUBREG_REG (operands[0])) == REG | |
2175 | && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER)) | |
2176 | { | |
2177 | if (aligned_memory_operand (operands[0], mode)) | |
2178 | { | |
2179 | rtx aligned_mem, bitnum; | |
2180 | rtx temp1 = gen_reg_rtx (SImode); | |
2181 | rtx temp2 = gen_reg_rtx (SImode); | |
2182 | ||
2183 | get_aligned_mem (operands[0], &aligned_mem, &bitnum); | |
2184 | ||
2185 | emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum, | |
2186 | temp1, temp2)); | |
2187 | } | |
2188 | else | |
2189 | { | |
2190 | rtx temp1 = gen_reg_rtx (DImode); | |
2191 | rtx temp2 = gen_reg_rtx (DImode); | |
2192 | rtx temp3 = gen_reg_rtx (DImode); | |
2193 | rtx seq = ((mode == QImode | |
2194 | ? gen_unaligned_storeqi | |
2195 | : gen_unaligned_storehi) | |
2196 | (get_unaligned_address (operands[0], 0), | |
2197 | operands[1], temp1, temp2, temp3)); | |
2198 | ||
2199 | alpha_set_memflags (seq, operands[0]); | |
2200 | emit_insn (seq); | |
2201 | } | |
2202 | return true; | |
2203 | } | |
2204 | ||
2205 | return false; | |
2206 | } | |
2207 | ||
2a42ba09 | 2208 | /* Generate an unsigned DImode to FP conversion. This is the same code |
2209 | optabs would emit if we didn't have TFmode patterns. | |
2210 | ||
2211 | For SFmode, this is the only construction I've found that can pass | |
2212 | gcc.c-torture/execute/ieee/rbug.c. No scenario that uses DFmode | |
2213 | intermediates will work, because you'll get intermediate rounding | |
2214 | that ruins the end result. Some of this could be fixed by turning | |
2215 | on round-to-positive-infinity, but that requires diddling the fpsr, | |
2216 | which kills performance. I tried turning this around and converting | |
2217 | to a negative number, so that I could turn on /m, but either I did | |
2218 | it wrong or there's something else cause I wound up with the exact | |
2219 | same single-bit error. There is a branch-less form of this same code: | |
2220 | ||
2221 | srl $16,1,$1 | |
2222 | and $16,1,$2 | |
2223 | cmplt $16,0,$3 | |
2224 | or $1,$2,$2 | |
2225 | cmovge $16,$16,$2 | |
2226 | itoft $3,$f10 | |
2227 | itoft $2,$f11 | |
2228 | cvtqs $f11,$f11 | |
2229 | adds $f11,$f11,$f0 | |
2230 | fcmoveq $f10,$f11,$f0 | |
2231 | ||
2232 | I'm not using it because it's the same number of instructions as | |
2233 | this branch-full form, and it has more serialized long latency | |
2234 | instructions on the critical path. | |
2235 | ||
2236 | For DFmode, we can avoid rounding errors by breaking up the word | |
2237 | into two pieces, converting them separately, and adding them back: | |
2238 | ||
2239 | LC0: .long 0,0x5f800000 | |
2240 | ||
2241 | itoft $16,$f11 | |
2242 | lda $2,LC0 | |
093c0196 | 2243 | cmplt $16,0,$1 |
2a42ba09 | 2244 | cpyse $f11,$f31,$f10 |
2245 | cpyse $f31,$f11,$f11 | |
2246 | s4addq $1,$2,$1 | |
2247 | lds $f12,0($1) | |
2248 | cvtqt $f10,$f10 | |
2249 | cvtqt $f11,$f11 | |
2250 | addt $f12,$f10,$f0 | |
2251 | addt $f0,$f11,$f0 | |
2252 | ||
2253 | This doesn't seem to be a clear-cut win over the optabs form. | |
2254 | It probably all depends on the distribution of numbers being | |
2255 | converted -- in the optabs form, all but high-bit-set has a | |
2256 | much lower minimum execution time. */ | |
2257 | ||
2258 | void | |
92643d95 | 2259 | alpha_emit_floatuns (rtx operands[2]) |
2a42ba09 | 2260 | { |
2261 | rtx neglab, donelab, i0, i1, f0, in, out; | |
2262 | enum machine_mode mode; | |
2263 | ||
2264 | out = operands[0]; | |
8e2025b4 | 2265 | in = force_reg (DImode, operands[1]); |
2a42ba09 | 2266 | mode = GET_MODE (out); |
2267 | neglab = gen_label_rtx (); | |
2268 | donelab = gen_label_rtx (); | |
2269 | i0 = gen_reg_rtx (DImode); | |
2270 | i1 = gen_reg_rtx (DImode); | |
2271 | f0 = gen_reg_rtx (mode); | |
2272 | ||
7e69f45b | 2273 | emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, DImode, 0, neglab); |
2a42ba09 | 2274 | |
2275 | emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_FLOAT (mode, in))); | |
2276 | emit_jump_insn (gen_jump (donelab)); | |
093c0196 | 2277 | emit_barrier (); |
2a42ba09 | 2278 | |
2279 | emit_label (neglab); | |
2280 | ||
2281 | emit_insn (gen_lshrdi3 (i0, in, const1_rtx)); | |
2282 | emit_insn (gen_anddi3 (i1, in, const1_rtx)); | |
2283 | emit_insn (gen_iordi3 (i0, i0, i1)); | |
2284 | emit_insn (gen_rtx_SET (VOIDmode, f0, gen_rtx_FLOAT (mode, i0))); | |
2285 | emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_PLUS (mode, f0, f0))); | |
2286 | ||
2287 | emit_label (donelab); | |
2288 | } | |
2289 | ||
3a2a3a7f | 2290 | /* Generate the comparison for a conditional branch. */ |
2291 | ||
2292 | rtx | |
92643d95 | 2293 | alpha_emit_conditional_branch (enum rtx_code code) |
3a2a3a7f | 2294 | { |
2295 | enum rtx_code cmp_code, branch_code; | |
2296 | enum machine_mode cmp_mode, branch_mode = VOIDmode; | |
b18b881f | 2297 | rtx op0 = alpha_compare.op0, op1 = alpha_compare.op1; |
3a2a3a7f | 2298 | rtx tem; |
2299 | ||
915c336f | 2300 | if (alpha_compare.fp_p && GET_MODE (op0) == TFmode) |
2301 | { | |
2302 | if (! TARGET_HAS_XFLOATING_LIBS) | |
2303 | abort (); | |
2304 | ||
2305 | /* X_floating library comparison functions return | |
2306 | -1 unordered | |
2307 | 0 false | |
2308 | 1 true | |
2309 | Convert the compare against the raw return value. */ | |
2310 | ||
a92123e9 | 2311 | switch (code) |
2312 | { | |
2313 | case UNORDERED: | |
2314 | cmp_code = EQ; | |
2315 | code = LT; | |
2316 | break; | |
2317 | case ORDERED: | |
2318 | cmp_code = EQ; | |
2319 | code = GE; | |
2320 | break; | |
2321 | case NE: | |
2322 | cmp_code = NE; | |
2323 | code = NE; | |
2324 | break; | |
2325 | default: | |
2326 | cmp_code = code; | |
f4a6c960 | 2327 | code = GT; |
a92123e9 | 2328 | break; |
2329 | } | |
d74ce6fa | 2330 | |
2331 | op0 = alpha_emit_xfloating_compare (cmp_code, op0, op1); | |
915c336f | 2332 | op1 = const0_rtx; |
2333 | alpha_compare.fp_p = 0; | |
915c336f | 2334 | } |
2335 | ||
3a2a3a7f | 2336 | /* The general case: fold the comparison code to the types of compares |
2337 | that we have, choosing the branch as necessary. */ | |
2338 | switch (code) | |
2339 | { | |
2340 | case EQ: case LE: case LT: case LEU: case LTU: | |
a4110d9a | 2341 | case UNORDERED: |
3a2a3a7f | 2342 | /* We have these compares: */ |
2343 | cmp_code = code, branch_code = NE; | |
2344 | break; | |
2345 | ||
2346 | case NE: | |
a4110d9a | 2347 | case ORDERED: |
65abff06 | 2348 | /* These must be reversed. */ |
a4110d9a | 2349 | cmp_code = reverse_condition (code), branch_code = EQ; |
3a2a3a7f | 2350 | break; |
2351 | ||
2352 | case GE: case GT: case GEU: case GTU: | |
2353 | /* For FP, we swap them, for INT, we reverse them. */ | |
b18b881f | 2354 | if (alpha_compare.fp_p) |
3a2a3a7f | 2355 | { |
2356 | cmp_code = swap_condition (code); | |
2357 | branch_code = NE; | |
2358 | tem = op0, op0 = op1, op1 = tem; | |
2359 | } | |
2360 | else | |
2361 | { | |
2362 | cmp_code = reverse_condition (code); | |
2363 | branch_code = EQ; | |
2364 | } | |
2365 | break; | |
2366 | ||
2367 | default: | |
2368 | abort (); | |
2369 | } | |
2370 | ||
b18b881f | 2371 | if (alpha_compare.fp_p) |
3a2a3a7f | 2372 | { |
2373 | cmp_mode = DFmode; | |
7f3be425 | 2374 | if (flag_unsafe_math_optimizations) |
3a2a3a7f | 2375 | { |
2376 | /* When we are not as concerned about non-finite values, and we | |
2377 | are comparing against zero, we can branch directly. */ | |
2378 | if (op1 == CONST0_RTX (DFmode)) | |
21f1e711 | 2379 | cmp_code = UNKNOWN, branch_code = code; |
3a2a3a7f | 2380 | else if (op0 == CONST0_RTX (DFmode)) |
2381 | { | |
2382 | /* Undo the swap we probably did just above. */ | |
2383 | tem = op0, op0 = op1, op1 = tem; | |
4899654e | 2384 | branch_code = swap_condition (cmp_code); |
21f1e711 | 2385 | cmp_code = UNKNOWN; |
3a2a3a7f | 2386 | } |
2387 | } | |
2388 | else | |
2389 | { | |
d30e015b | 2390 | /* ??? We mark the branch mode to be CCmode to prevent the |
9e7454d0 | 2391 | compare and branch from being combined, since the compare |
3a2a3a7f | 2392 | insn follows IEEE rules that the branch does not. */ |
2393 | branch_mode = CCmode; | |
2394 | } | |
2395 | } | |
2396 | else | |
2397 | { | |
2398 | cmp_mode = DImode; | |
2399 | ||
2400 | /* The following optimizations are only for signed compares. */ | |
2401 | if (code != LEU && code != LTU && code != GEU && code != GTU) | |
2402 | { | |
2403 | /* Whee. Compare and branch against 0 directly. */ | |
2404 | if (op1 == const0_rtx) | |
21f1e711 | 2405 | cmp_code = UNKNOWN, branch_code = code; |
3a2a3a7f | 2406 | |
3a2f3420 | 2407 | /* If the constants doesn't fit into an immediate, but can |
2408 | be generated by lda/ldah, we adjust the argument and | |
2409 | compare against zero, so we can use beq/bne directly. */ | |
62350d6c | 2410 | /* ??? Don't do this when comparing against symbols, otherwise |
2411 | we'll reduce (&x == 0x1234) to (&x-0x1234 == 0), which will | |
2412 | be declared false out of hand (at least for non-weak). */ | |
2413 | else if (GET_CODE (op1) == CONST_INT | |
2414 | && (code == EQ || code == NE) | |
2415 | && !(symbolic_operand (op0, VOIDmode) | |
2416 | || (GET_CODE (op0) == REG && REG_POINTER (op0)))) | |
3a2a3a7f | 2417 | { |
2418 | HOST_WIDE_INT v = INTVAL (op1), n = -v; | |
2419 | ||
2420 | if (! CONST_OK_FOR_LETTER_P (v, 'I') | |
2421 | && (CONST_OK_FOR_LETTER_P (n, 'K') | |
2422 | || CONST_OK_FOR_LETTER_P (n, 'L'))) | |
2423 | { | |
2424 | cmp_code = PLUS, branch_code = code; | |
2425 | op1 = GEN_INT (n); | |
2426 | } | |
2427 | } | |
2428 | } | |
3a2a3a7f | 2429 | |
d74ce6fa | 2430 | if (!reg_or_0_operand (op0, DImode)) |
2431 | op0 = force_reg (DImode, op0); | |
2432 | if (cmp_code != PLUS && !reg_or_8bit_operand (op1, DImode)) | |
2433 | op1 = force_reg (DImode, op1); | |
2434 | } | |
3a2a3a7f | 2435 | |
2436 | /* Emit an initial compare instruction, if necessary. */ | |
2437 | tem = op0; | |
21f1e711 | 2438 | if (cmp_code != UNKNOWN) |
3a2a3a7f | 2439 | { |
2440 | tem = gen_reg_rtx (cmp_mode); | |
2441 | emit_move_insn (tem, gen_rtx_fmt_ee (cmp_code, cmp_mode, op0, op1)); | |
2442 | } | |
2443 | ||
b18b881f | 2444 | /* Zero the operands. */ |
2445 | memset (&alpha_compare, 0, sizeof (alpha_compare)); | |
2446 | ||
3a2a3a7f | 2447 | /* Return the branch comparison. */ |
2448 | return gen_rtx_fmt_ee (branch_code, branch_mode, tem, CONST0_RTX (cmp_mode)); | |
2449 | } | |
2450 | ||
d74ce6fa | 2451 | /* Certain simplifications can be done to make invalid setcc operations |
2452 | valid. Return the final comparison, or NULL if we can't work. */ | |
2453 | ||
2454 | rtx | |
92643d95 | 2455 | alpha_emit_setcc (enum rtx_code code) |
d74ce6fa | 2456 | { |
2457 | enum rtx_code cmp_code; | |
2458 | rtx op0 = alpha_compare.op0, op1 = alpha_compare.op1; | |
2459 | int fp_p = alpha_compare.fp_p; | |
2460 | rtx tmp; | |
2461 | ||
2462 | /* Zero the operands. */ | |
2463 | memset (&alpha_compare, 0, sizeof (alpha_compare)); | |
2464 | ||
2465 | if (fp_p && GET_MODE (op0) == TFmode) | |
2466 | { | |
2467 | if (! TARGET_HAS_XFLOATING_LIBS) | |
2468 | abort (); | |
2469 | ||
2470 | /* X_floating library comparison functions return | |
2471 | -1 unordered | |
2472 | 0 false | |
2473 | 1 true | |
2474 | Convert the compare against the raw return value. */ | |
2475 | ||
2476 | if (code == UNORDERED || code == ORDERED) | |
2477 | cmp_code = EQ; | |
2478 | else | |
2479 | cmp_code = code; | |
2480 | ||
2481 | op0 = alpha_emit_xfloating_compare (cmp_code, op0, op1); | |
2482 | op1 = const0_rtx; | |
2483 | fp_p = 0; | |
2484 | ||
2485 | if (code == UNORDERED) | |
2486 | code = LT; | |
2487 | else if (code == ORDERED) | |
2488 | code = GE; | |
2489 | else | |
2490 | code = GT; | |
2491 | } | |
2492 | ||
2493 | if (fp_p && !TARGET_FIX) | |
2494 | return NULL_RTX; | |
2495 | ||
2496 | /* The general case: fold the comparison code to the types of compares | |
2497 | that we have, choosing the branch as necessary. */ | |
2498 | ||
21f1e711 | 2499 | cmp_code = UNKNOWN; |
d74ce6fa | 2500 | switch (code) |
2501 | { | |
2502 | case EQ: case LE: case LT: case LEU: case LTU: | |
2503 | case UNORDERED: | |
2504 | /* We have these compares. */ | |
2505 | if (fp_p) | |
2506 | cmp_code = code, code = NE; | |
2507 | break; | |
2508 | ||
2509 | case NE: | |
2510 | if (!fp_p && op1 == const0_rtx) | |
2511 | break; | |
8e262b5e | 2512 | /* FALLTHRU */ |
d74ce6fa | 2513 | |
2514 | case ORDERED: | |
2515 | cmp_code = reverse_condition (code); | |
2516 | code = EQ; | |
2517 | break; | |
2518 | ||
2519 | case GE: case GT: case GEU: case GTU: | |
75b3314a | 2520 | /* These normally need swapping, but for integer zero we have |
bc882521 | 2521 | special patterns that recognize swapped operands. */ |
2522 | if (!fp_p && op1 == const0_rtx) | |
2523 | break; | |
d74ce6fa | 2524 | code = swap_condition (code); |
2525 | if (fp_p) | |
2526 | cmp_code = code, code = NE; | |
2527 | tmp = op0, op0 = op1, op1 = tmp; | |
2528 | break; | |
2529 | ||
2530 | default: | |
2531 | abort (); | |
2532 | } | |
2533 | ||
2534 | if (!fp_p) | |
2535 | { | |
bc882521 | 2536 | if (!register_operand (op0, DImode)) |
d74ce6fa | 2537 | op0 = force_reg (DImode, op0); |
2538 | if (!reg_or_8bit_operand (op1, DImode)) | |
2539 | op1 = force_reg (DImode, op1); | |
2540 | } | |
2541 | ||
2542 | /* Emit an initial compare instruction, if necessary. */ | |
21f1e711 | 2543 | if (cmp_code != UNKNOWN) |
d74ce6fa | 2544 | { |
2545 | enum machine_mode mode = fp_p ? DFmode : DImode; | |
2546 | ||
2547 | tmp = gen_reg_rtx (mode); | |
2548 | emit_insn (gen_rtx_SET (VOIDmode, tmp, | |
2549 | gen_rtx_fmt_ee (cmp_code, mode, op0, op1))); | |
2550 | ||
2551 | op0 = fp_p ? gen_lowpart (DImode, tmp) : tmp; | |
2552 | op1 = const0_rtx; | |
2553 | } | |
2554 | ||
2555 | /* Return the setcc comparison. */ | |
2556 | return gen_rtx_fmt_ee (code, DImode, op0, op1); | |
2557 | } | |
2558 | ||
3a2a3a7f | 2559 | |
996a379d | 2560 | /* Rewrite a comparison against zero CMP of the form |
2561 | (CODE (cc0) (const_int 0)) so it can be written validly in | |
2562 | a conditional move (if_then_else CMP ...). | |
e3e08e7f | 2563 | If both of the operands that set cc0 are nonzero we must emit |
996a379d | 2564 | an insn to perform the compare (it can't be done within |
65abff06 | 2565 | the conditional move). */ |
92643d95 | 2566 | |
996a379d | 2567 | rtx |
92643d95 | 2568 | alpha_emit_conditional_move (rtx cmp, enum machine_mode mode) |
996a379d | 2569 | { |
23be97c5 | 2570 | enum rtx_code code = GET_CODE (cmp); |
c60bc286 | 2571 | enum rtx_code cmov_code = NE; |
b18b881f | 2572 | rtx op0 = alpha_compare.op0; |
2573 | rtx op1 = alpha_compare.op1; | |
2574 | int fp_p = alpha_compare.fp_p; | |
23be97c5 | 2575 | enum machine_mode cmp_mode |
2576 | = (GET_MODE (op0) == VOIDmode ? DImode : GET_MODE (op0)); | |
b18b881f | 2577 | enum machine_mode cmp_op_mode = fp_p ? DFmode : DImode; |
3a2a3a7f | 2578 | enum machine_mode cmov_mode = VOIDmode; |
7f3be425 | 2579 | int local_fast_math = flag_unsafe_math_optimizations; |
23be97c5 | 2580 | rtx tem; |
996a379d | 2581 | |
b18b881f | 2582 | /* Zero the operands. */ |
2583 | memset (&alpha_compare, 0, sizeof (alpha_compare)); | |
2584 | ||
2585 | if (fp_p != FLOAT_MODE_P (mode)) | |
d6cc9868 | 2586 | { |
2587 | enum rtx_code cmp_code; | |
2588 | ||
2589 | if (! TARGET_FIX) | |
2590 | return 0; | |
2591 | ||
2592 | /* If we have fp<->int register move instructions, do a cmov by | |
2593 | performing the comparison in fp registers, and move the | |
e3e08e7f | 2594 | zero/nonzero value to integer registers, where we can then |
d6cc9868 | 2595 | use a normal cmov, or vice-versa. */ |
2596 | ||
2597 | switch (code) | |
2598 | { | |
2599 | case EQ: case LE: case LT: case LEU: case LTU: | |
2600 | /* We have these compares. */ | |
2601 | cmp_code = code, code = NE; | |
2602 | break; | |
2603 | ||
2604 | case NE: | |
2605 | /* This must be reversed. */ | |
2606 | cmp_code = EQ, code = EQ; | |
2607 | break; | |
2608 | ||
2609 | case GE: case GT: case GEU: case GTU: | |
75b3314a | 2610 | /* These normally need swapping, but for integer zero we have |
2611 | special patterns that recognize swapped operands. */ | |
2612 | if (!fp_p && op1 == const0_rtx) | |
88f8f2a2 | 2613 | cmp_code = code, code = NE; |
2614 | else | |
2615 | { | |
2616 | cmp_code = swap_condition (code); | |
2617 | code = NE; | |
2618 | tem = op0, op0 = op1, op1 = tem; | |
2619 | } | |
d6cc9868 | 2620 | break; |
2621 | ||
2622 | default: | |
2623 | abort (); | |
2624 | } | |
2625 | ||
2626 | tem = gen_reg_rtx (cmp_op_mode); | |
2627 | emit_insn (gen_rtx_SET (VOIDmode, tem, | |
2628 | gen_rtx_fmt_ee (cmp_code, cmp_op_mode, | |
2629 | op0, op1))); | |
2630 | ||
2631 | cmp_mode = cmp_op_mode = fp_p ? DImode : DFmode; | |
2632 | op0 = gen_lowpart (cmp_op_mode, tem); | |
2633 | op1 = CONST0_RTX (cmp_op_mode); | |
2634 | fp_p = !fp_p; | |
2635 | local_fast_math = 1; | |
2636 | } | |
996a379d | 2637 | |
2638 | /* We may be able to use a conditional move directly. | |
65abff06 | 2639 | This avoids emitting spurious compares. */ |
2a42ba09 | 2640 | if (signed_comparison_operator (cmp, VOIDmode) |
d6cc9868 | 2641 | && (!fp_p || local_fast_math) |
23be97c5 | 2642 | && (op0 == CONST0_RTX (cmp_mode) || op1 == CONST0_RTX (cmp_mode))) |
941522d6 | 2643 | return gen_rtx_fmt_ee (code, VOIDmode, op0, op1); |
996a379d | 2644 | |
3029ee00 | 2645 | /* We can't put the comparison inside the conditional move; |
996a379d | 2646 | emit a compare instruction and put that inside the |
23be97c5 | 2647 | conditional move. Make sure we emit only comparisons we have; |
2648 | swap or reverse as necessary. */ | |
996a379d | 2649 | |
3029ee00 | 2650 | if (no_new_pseudos) |
2651 | return NULL_RTX; | |
2652 | ||
996a379d | 2653 | switch (code) |
2654 | { | |
23be97c5 | 2655 | case EQ: case LE: case LT: case LEU: case LTU: |
2656 | /* We have these compares: */ | |
996a379d | 2657 | break; |
23be97c5 | 2658 | |
996a379d | 2659 | case NE: |
65abff06 | 2660 | /* This must be reversed. */ |
23be97c5 | 2661 | code = reverse_condition (code); |
c60bc286 | 2662 | cmov_code = EQ; |
996a379d | 2663 | break; |
23be97c5 | 2664 | |
2665 | case GE: case GT: case GEU: case GTU: | |
d74ce6fa | 2666 | /* These must be swapped. */ |
88f8f2a2 | 2667 | if (op1 != CONST0_RTX (cmp_mode)) |
2668 | { | |
2669 | code = swap_condition (code); | |
2670 | tem = op0, op0 = op1, op1 = tem; | |
2671 | } | |
996a379d | 2672 | break; |
23be97c5 | 2673 | |
996a379d | 2674 | default: |
23be97c5 | 2675 | abort (); |
996a379d | 2676 | } |
2677 | ||
d74ce6fa | 2678 | if (!fp_p) |
2679 | { | |
2680 | if (!reg_or_0_operand (op0, DImode)) | |
2681 | op0 = force_reg (DImode, op0); | |
2682 | if (!reg_or_8bit_operand (op1, DImode)) | |
2683 | op1 = force_reg (DImode, op1); | |
2684 | } | |
2685 | ||
b9b4428b | 2686 | /* ??? We mark the branch mode to be CCmode to prevent the compare |
3a2a3a7f | 2687 | and cmov from being combined, since the compare insn follows IEEE |
2688 | rules that the cmov does not. */ | |
d6cc9868 | 2689 | if (fp_p && !local_fast_math) |
3a2a3a7f | 2690 | cmov_mode = CCmode; |
2691 | ||
23be97c5 | 2692 | tem = gen_reg_rtx (cmp_op_mode); |
941522d6 | 2693 | emit_move_insn (tem, gen_rtx_fmt_ee (code, cmp_op_mode, op0, op1)); |
3a2a3a7f | 2694 | return gen_rtx_fmt_ee (cmov_code, cmov_mode, tem, CONST0_RTX (cmp_op_mode)); |
996a379d | 2695 | } |
bbf31a61 | 2696 | |
2697 | /* Simplify a conditional move of two constants into a setcc with | |
2698 | arithmetic. This is done with a splitter since combine would | |
2699 | just undo the work if done during code generation. It also catches | |
2700 | cases we wouldn't have before cse. */ | |
2701 | ||
2702 | int | |
92643d95 | 2703 | alpha_split_conditional_move (enum rtx_code code, rtx dest, rtx cond, |
2704 | rtx t_rtx, rtx f_rtx) | |
bbf31a61 | 2705 | { |
2706 | HOST_WIDE_INT t, f, diff; | |
2707 | enum machine_mode mode; | |
2708 | rtx target, subtarget, tmp; | |
2709 | ||
2710 | mode = GET_MODE (dest); | |
2711 | t = INTVAL (t_rtx); | |
2712 | f = INTVAL (f_rtx); | |
2713 | diff = t - f; | |
2714 | ||
2715 | if (((code == NE || code == EQ) && diff < 0) | |
2716 | || (code == GE || code == GT)) | |
2717 | { | |
2718 | code = reverse_condition (code); | |
2719 | diff = t, t = f, f = diff; | |
2720 | diff = t - f; | |
2721 | } | |
2722 | ||
2723 | subtarget = target = dest; | |
2724 | if (mode != DImode) | |
2725 | { | |
2726 | target = gen_lowpart (DImode, dest); | |
2727 | if (! no_new_pseudos) | |
2728 | subtarget = gen_reg_rtx (DImode); | |
2729 | else | |
2730 | subtarget = target; | |
2731 | } | |
64656695 | 2732 | /* Below, we must be careful to use copy_rtx on target and subtarget |
2733 | in intermediate insns, as they may be a subreg rtx, which may not | |
2734 | be shared. */ | |
bbf31a61 | 2735 | |
2736 | if (f == 0 && exact_log2 (diff) > 0 | |
8d232dc7 | 2737 | /* On EV6, we've got enough shifters to make non-arithmetic shifts |
bbf31a61 | 2738 | viable over a longer latency cmove. On EV5, the E0 slot is a |
65abff06 | 2739 | scarce resource, and on EV4 shift has the same latency as a cmove. */ |
bbf31a61 | 2740 | && (diff <= 8 || alpha_cpu == PROCESSOR_EV6)) |
2741 | { | |
2742 | tmp = gen_rtx_fmt_ee (code, DImode, cond, const0_rtx); | |
64656695 | 2743 | emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (subtarget), tmp)); |
bbf31a61 | 2744 | |
64656695 | 2745 | tmp = gen_rtx_ASHIFT (DImode, copy_rtx (subtarget), |
2746 | GEN_INT (exact_log2 (t))); | |
bbf31a61 | 2747 | emit_insn (gen_rtx_SET (VOIDmode, target, tmp)); |
2748 | } | |
2749 | else if (f == 0 && t == -1) | |
2750 | { | |
2751 | tmp = gen_rtx_fmt_ee (code, DImode, cond, const0_rtx); | |
64656695 | 2752 | emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (subtarget), tmp)); |
bbf31a61 | 2753 | |
64656695 | 2754 | emit_insn (gen_negdi2 (target, copy_rtx (subtarget))); |
bbf31a61 | 2755 | } |
2756 | else if (diff == 1 || diff == 4 || diff == 8) | |
2757 | { | |
2758 | rtx add_op; | |
2759 | ||
2760 | tmp = gen_rtx_fmt_ee (code, DImode, cond, const0_rtx); | |
64656695 | 2761 | emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (subtarget), tmp)); |
bbf31a61 | 2762 | |
2763 | if (diff == 1) | |
64656695 | 2764 | emit_insn (gen_adddi3 (target, copy_rtx (subtarget), GEN_INT (f))); |
bbf31a61 | 2765 | else |
2766 | { | |
2767 | add_op = GEN_INT (f); | |
2768 | if (sext_add_operand (add_op, mode)) | |
2769 | { | |
64656695 | 2770 | tmp = gen_rtx_MULT (DImode, copy_rtx (subtarget), |
2771 | GEN_INT (diff)); | |
bbf31a61 | 2772 | tmp = gen_rtx_PLUS (DImode, tmp, add_op); |
2773 | emit_insn (gen_rtx_SET (VOIDmode, target, tmp)); | |
2774 | } | |
2775 | else | |
2776 | return 0; | |
2777 | } | |
2778 | } | |
2779 | else | |
2780 | return 0; | |
2781 | ||
2782 | return 1; | |
2783 | } | |
34377880 | 2784 | \f |
915c336f | 2785 | /* Look up the function X_floating library function name for the |
2786 | given operation. */ | |
2787 | ||
2d7c492e | 2788 | struct xfloating_op GTY(()) |
2789 | { | |
2790 | const enum rtx_code code; | |
7035b2ab | 2791 | const char *const GTY((skip)) osf_func; |
2792 | const char *const GTY((skip)) vms_func; | |
2d7c492e | 2793 | rtx libcall; |
2794 | }; | |
2795 | ||
9e7454d0 | 2796 | static GTY(()) struct xfloating_op xfloating_ops[] = |
2d7c492e | 2797 | { |
2798 | { PLUS, "_OtsAddX", "OTS$ADD_X", 0 }, | |
2799 | { MINUS, "_OtsSubX", "OTS$SUB_X", 0 }, | |
2800 | { MULT, "_OtsMulX", "OTS$MUL_X", 0 }, | |
2801 | { DIV, "_OtsDivX", "OTS$DIV_X", 0 }, | |
2802 | { EQ, "_OtsEqlX", "OTS$EQL_X", 0 }, | |
2803 | { NE, "_OtsNeqX", "OTS$NEQ_X", 0 }, | |
2804 | { LT, "_OtsLssX", "OTS$LSS_X", 0 }, | |
2805 | { LE, "_OtsLeqX", "OTS$LEQ_X", 0 }, | |
2806 | { GT, "_OtsGtrX", "OTS$GTR_X", 0 }, | |
2807 | { GE, "_OtsGeqX", "OTS$GEQ_X", 0 }, | |
2808 | { FIX, "_OtsCvtXQ", "OTS$CVTXQ", 0 }, | |
2809 | { FLOAT, "_OtsCvtQX", "OTS$CVTQX", 0 }, | |
2810 | { UNSIGNED_FLOAT, "_OtsCvtQUX", "OTS$CVTQUX", 0 }, | |
2811 | { FLOAT_EXTEND, "_OtsConvertFloatTX", "OTS$CVT_FLOAT_T_X", 0 }, | |
2812 | { FLOAT_TRUNCATE, "_OtsConvertFloatXT", "OTS$CVT_FLOAT_X_T", 0 } | |
2813 | }; | |
2814 | ||
2815 | static GTY(()) struct xfloating_op vax_cvt_ops[] = | |
2816 | { | |
2817 | { FLOAT_EXTEND, "_OtsConvertFloatGX", "OTS$CVT_FLOAT_G_X", 0 }, | |
2818 | { FLOAT_TRUNCATE, "_OtsConvertFloatXG", "OTS$CVT_FLOAT_X_G", 0 } | |
2819 | }; | |
2820 | ||
2821 | static rtx | |
92643d95 | 2822 | alpha_lookup_xfloating_lib_func (enum rtx_code code) |
915c336f | 2823 | { |
2d7c492e | 2824 | struct xfloating_op *ops = xfloating_ops; |
2825 | long n = ARRAY_SIZE (xfloating_ops); | |
915c336f | 2826 | long i; |
2827 | ||
2d7c492e | 2828 | /* How irritating. Nothing to key off for the main table. */ |
2829 | if (TARGET_FLOAT_VAX && (code == FLOAT_EXTEND || code == FLOAT_TRUNCATE)) | |
915c336f | 2830 | { |
2d7c492e | 2831 | ops = vax_cvt_ops; |
2832 | n = ARRAY_SIZE (vax_cvt_ops); | |
915c336f | 2833 | } |
2834 | ||
2d7c492e | 2835 | for (i = 0; i < n; ++i, ++ops) |
2836 | if (ops->code == code) | |
2837 | { | |
2838 | rtx func = ops->libcall; | |
2839 | if (!func) | |
2840 | { | |
2841 | func = init_one_libfunc (TARGET_ABI_OPEN_VMS | |
2842 | ? ops->vms_func : ops->osf_func); | |
2843 | ops->libcall = func; | |
2844 | } | |
2845 | return func; | |
2846 | } | |
915c336f | 2847 | |
2848 | abort(); | |
2849 | } | |
2850 | ||
2851 | /* Most X_floating operations take the rounding mode as an argument. | |
2852 | Compute that here. */ | |
2853 | ||
2854 | static int | |
92643d95 | 2855 | alpha_compute_xfloating_mode_arg (enum rtx_code code, |
2856 | enum alpha_fp_rounding_mode round) | |
915c336f | 2857 | { |
2858 | int mode; | |
2859 | ||
2860 | switch (round) | |
2861 | { | |
2862 | case ALPHA_FPRM_NORM: | |
2863 | mode = 2; | |
2864 | break; | |
2865 | case ALPHA_FPRM_MINF: | |
2866 | mode = 1; | |
2867 | break; | |
2868 | case ALPHA_FPRM_CHOP: | |
2869 | mode = 0; | |
2870 | break; | |
2871 | case ALPHA_FPRM_DYN: | |
2872 | mode = 4; | |
2873 | break; | |
2874 | default: | |
2875 | abort (); | |
2876 | ||
2877 | /* XXX For reference, round to +inf is mode = 3. */ | |
2878 | } | |
2879 | ||
2880 | if (code == FLOAT_TRUNCATE && alpha_fptm == ALPHA_FPTM_N) | |
2881 | mode |= 0x10000; | |
2882 | ||
2883 | return mode; | |
2884 | } | |
2885 | ||
2886 | /* Emit an X_floating library function call. | |
2887 | ||
2888 | Note that these functions do not follow normal calling conventions: | |
2889 | TFmode arguments are passed in two integer registers (as opposed to | |
9e7454d0 | 2890 | indirect); TFmode return values appear in R16+R17. |
915c336f | 2891 | |
2d7c492e | 2892 | FUNC is the function to call. |
915c336f | 2893 | TARGET is where the output belongs. |
2894 | OPERANDS are the inputs. | |
2895 | NOPERANDS is the count of inputs. | |
2896 | EQUIV is the expression equivalent for the function. | |
2897 | */ | |
2898 | ||
2899 | static void | |
2d7c492e | 2900 | alpha_emit_xfloating_libcall (rtx func, rtx target, rtx operands[], |
92643d95 | 2901 | int noperands, rtx equiv) |
915c336f | 2902 | { |
2903 | rtx usage = NULL_RTX, tmp, reg; | |
2904 | int regno = 16, i; | |
2905 | ||
2906 | start_sequence (); | |
2907 | ||
2908 | for (i = 0; i < noperands; ++i) | |
2909 | { | |
2910 | switch (GET_MODE (operands[i])) | |
2911 | { | |
2912 | case TFmode: | |
2913 | reg = gen_rtx_REG (TFmode, regno); | |
2914 | regno += 2; | |
2915 | break; | |
2916 | ||
2917 | case DFmode: | |
2918 | reg = gen_rtx_REG (DFmode, regno + 32); | |
2919 | regno += 1; | |
2920 | break; | |
2921 | ||
2922 | case VOIDmode: | |
2923 | if (GET_CODE (operands[i]) != CONST_INT) | |
2924 | abort (); | |
8e262b5e | 2925 | /* FALLTHRU */ |
915c336f | 2926 | case DImode: |
2927 | reg = gen_rtx_REG (DImode, regno); | |
2928 | regno += 1; | |
2929 | break; | |
2930 | ||
2931 | default: | |
2932 | abort (); | |
2933 | } | |
2934 | ||
2935 | emit_move_insn (reg, operands[i]); | |
2936 | usage = alloc_EXPR_LIST (0, gen_rtx_USE (VOIDmode, reg), usage); | |
2937 | } | |
2938 | ||
2939 | switch (GET_MODE (target)) | |
2940 | { | |
2941 | case TFmode: | |
2942 | reg = gen_rtx_REG (TFmode, 16); | |
2943 | break; | |
2944 | case DFmode: | |
2945 | reg = gen_rtx_REG (DFmode, 32); | |
2946 | break; | |
2947 | case DImode: | |
2948 | reg = gen_rtx_REG (DImode, 0); | |
2949 | break; | |
2950 | default: | |
2951 | abort (); | |
2952 | } | |
2953 | ||
2d7c492e | 2954 | tmp = gen_rtx_MEM (QImode, func); |
2c6f8e4d | 2955 | tmp = emit_call_insn (GEN_CALL_VALUE (reg, tmp, const0_rtx, |
915c336f | 2956 | const0_rtx, const0_rtx)); |
2957 | CALL_INSN_FUNCTION_USAGE (tmp) = usage; | |
2d7c492e | 2958 | CONST_OR_PURE_CALL_P (tmp) = 1; |
915c336f | 2959 | |
2960 | tmp = get_insns (); | |
2961 | end_sequence (); | |
2962 | ||
2963 | emit_libcall_block (tmp, target, reg, equiv); | |
2964 | } | |
2965 | ||
2966 | /* Emit an X_floating library function call for arithmetic (+,-,*,/). */ | |
2967 | ||
2968 | void | |
92643d95 | 2969 | alpha_emit_xfloating_arith (enum rtx_code code, rtx operands[]) |
915c336f | 2970 | { |
2d7c492e | 2971 | rtx func; |
915c336f | 2972 | int mode; |
b90b6519 | 2973 | rtx out_operands[3]; |
915c336f | 2974 | |
2975 | func = alpha_lookup_xfloating_lib_func (code); | |
2976 | mode = alpha_compute_xfloating_mode_arg (code, alpha_fprm); | |
2977 | ||
b90b6519 | 2978 | out_operands[0] = operands[1]; |
2979 | out_operands[1] = operands[2]; | |
2980 | out_operands[2] = GEN_INT (mode); | |
9e7454d0 | 2981 | alpha_emit_xfloating_libcall (func, operands[0], out_operands, 3, |
915c336f | 2982 | gen_rtx_fmt_ee (code, TFmode, operands[1], |
2983 | operands[2])); | |
2984 | } | |
2985 | ||
2986 | /* Emit an X_floating library function call for a comparison. */ | |
2987 | ||
2988 | static rtx | |
92643d95 | 2989 | alpha_emit_xfloating_compare (enum rtx_code code, rtx op0, rtx op1) |
915c336f | 2990 | { |
2d7c492e | 2991 | rtx func; |
915c336f | 2992 | rtx out, operands[2]; |
2993 | ||
2994 | func = alpha_lookup_xfloating_lib_func (code); | |
2995 | ||
2996 | operands[0] = op0; | |
2997 | operands[1] = op1; | |
2998 | out = gen_reg_rtx (DImode); | |
2999 | ||
d1324b4b | 3000 | /* ??? Strange mode for equiv because what's actually returned |
3001 | is -1,0,1, not a proper boolean value. */ | |
3002 | alpha_emit_xfloating_libcall (func, out, operands, 2, | |
3003 | gen_rtx_fmt_ee (code, CCmode, op0, op1)); | |
915c336f | 3004 | |
3005 | return out; | |
3006 | } | |
3007 | ||
3008 | /* Emit an X_floating library function call for a conversion. */ | |
3009 | ||
3010 | void | |
caf6f044 | 3011 | alpha_emit_xfloating_cvt (enum rtx_code orig_code, rtx operands[]) |
915c336f | 3012 | { |
3013 | int noperands = 1, mode; | |
b90b6519 | 3014 | rtx out_operands[2]; |
2d7c492e | 3015 | rtx func; |
caf6f044 | 3016 | enum rtx_code code = orig_code; |
3017 | ||
3018 | if (code == UNSIGNED_FIX) | |
3019 | code = FIX; | |
915c336f | 3020 | |
3021 | func = alpha_lookup_xfloating_lib_func (code); | |
3022 | ||
b90b6519 | 3023 | out_operands[0] = operands[1]; |
3024 | ||
915c336f | 3025 | switch (code) |
3026 | { | |
3027 | case FIX: | |
3028 | mode = alpha_compute_xfloating_mode_arg (code, ALPHA_FPRM_CHOP); | |
b90b6519 | 3029 | out_operands[1] = GEN_INT (mode); |
8581412d | 3030 | noperands = 2; |
915c336f | 3031 | break; |
3032 | case FLOAT_TRUNCATE: | |
3033 | mode = alpha_compute_xfloating_mode_arg (code, alpha_fprm); | |
b90b6519 | 3034 | out_operands[1] = GEN_INT (mode); |
8581412d | 3035 | noperands = 2; |
915c336f | 3036 | break; |
3037 | default: | |
3038 | break; | |
3039 | } | |
3040 | ||
b90b6519 | 3041 | alpha_emit_xfloating_libcall (func, operands[0], out_operands, noperands, |
caf6f044 | 3042 | gen_rtx_fmt_e (orig_code, |
3043 | GET_MODE (operands[0]), | |
915c336f | 3044 | operands[1])); |
3045 | } | |
3420680b | 3046 | |
2267ca84 | 3047 | /* Split a TFmode OP[1] into DImode OP[2,3] and likewise for |
3048 | OP[0] into OP[0,1]. Naturally, output operand ordering is | |
3049 | little-endian. */ | |
3050 | ||
3420680b | 3051 | void |
92643d95 | 3052 | alpha_split_tfmode_pair (rtx operands[4]) |
3420680b | 3053 | { |
3054 | if (GET_CODE (operands[1]) == REG) | |
3055 | { | |
3056 | operands[3] = gen_rtx_REG (DImode, REGNO (operands[1]) + 1); | |
3057 | operands[2] = gen_rtx_REG (DImode, REGNO (operands[1])); | |
3058 | } | |
3059 | else if (GET_CODE (operands[1]) == MEM) | |
3060 | { | |
e513d163 | 3061 | operands[3] = adjust_address (operands[1], DImode, 8); |
3062 | operands[2] = adjust_address (operands[1], DImode, 0); | |
3420680b | 3063 | } |
3064 | else if (operands[1] == CONST0_RTX (TFmode)) | |
3065 | operands[2] = operands[3] = const0_rtx; | |
3066 | else | |
3067 | abort (); | |
3068 | ||
3069 | if (GET_CODE (operands[0]) == REG) | |
3070 | { | |
3071 | operands[1] = gen_rtx_REG (DImode, REGNO (operands[0]) + 1); | |
3072 | operands[0] = gen_rtx_REG (DImode, REGNO (operands[0])); | |
3073 | } | |
3074 | else if (GET_CODE (operands[0]) == MEM) | |
3075 | { | |
e513d163 | 3076 | operands[1] = adjust_address (operands[0], DImode, 8); |
3077 | operands[0] = adjust_address (operands[0], DImode, 0); | |
3420680b | 3078 | } |
3079 | else | |
3080 | abort (); | |
3081 | } | |
2267ca84 | 3082 | |
9e7454d0 | 3083 | /* Implement negtf2 or abstf2. Op0 is destination, op1 is source, |
3084 | op2 is a register containing the sign bit, operation is the | |
2267ca84 | 3085 | logical operation to be performed. */ |
3086 | ||
3087 | void | |
92643d95 | 3088 | alpha_split_tfmode_frobsign (rtx operands[3], rtx (*operation) (rtx, rtx, rtx)) |
2267ca84 | 3089 | { |
3090 | rtx high_bit = operands[2]; | |
3091 | rtx scratch; | |
3092 | int move; | |
3093 | ||
3094 | alpha_split_tfmode_pair (operands); | |
3095 | ||
e3e08e7f | 3096 | /* Detect three flavors of operand overlap. */ |
2267ca84 | 3097 | move = 1; |
3098 | if (rtx_equal_p (operands[0], operands[2])) | |
3099 | move = 0; | |
3100 | else if (rtx_equal_p (operands[1], operands[2])) | |
3101 | { | |
3102 | if (rtx_equal_p (operands[0], high_bit)) | |
3103 | move = 2; | |
3104 | else | |
3105 | move = -1; | |
3106 | } | |
3107 | ||
3108 | if (move < 0) | |
3109 | emit_move_insn (operands[0], operands[2]); | |
3110 | ||
3111 | /* ??? If the destination overlaps both source tf and high_bit, then | |
3112 | assume source tf is dead in its entirety and use the other half | |
3113 | for a scratch register. Otherwise "scratch" is just the proper | |
3114 | destination register. */ | |
3115 | scratch = operands[move < 2 ? 1 : 3]; | |
3116 | ||
3117 | emit_insn ((*operation) (scratch, high_bit, operands[3])); | |
3118 | ||
3119 | if (move > 0) | |
3120 | { | |
3121 | emit_move_insn (operands[0], operands[2]); | |
3122 | if (move > 1) | |
3123 | emit_move_insn (operands[1], scratch); | |
3124 | } | |
3125 | } | |
915c336f | 3126 | \f |
34377880 | 3127 | /* Use ext[wlq][lh] as the Architecture Handbook describes for extracting |
3128 | unaligned data: | |
3129 | ||
3130 | unsigned: signed: | |
3131 | word: ldq_u r1,X(r11) ldq_u r1,X(r11) | |
3132 | ldq_u r2,X+1(r11) ldq_u r2,X+1(r11) | |
3133 | lda r3,X(r11) lda r3,X+2(r11) | |
3134 | extwl r1,r3,r1 extql r1,r3,r1 | |
3135 | extwh r2,r3,r2 extqh r2,r3,r2 | |
3136 | or r1.r2.r1 or r1,r2,r1 | |
3137 | sra r1,48,r1 | |
3138 | ||
3139 | long: ldq_u r1,X(r11) ldq_u r1,X(r11) | |
3140 | ldq_u r2,X+3(r11) ldq_u r2,X+3(r11) | |
3141 | lda r3,X(r11) lda r3,X(r11) | |
3142 | extll r1,r3,r1 extll r1,r3,r1 | |
3143 | extlh r2,r3,r2 extlh r2,r3,r2 | |
3144 | or r1.r2.r1 addl r1,r2,r1 | |
3145 | ||
3146 | quad: ldq_u r1,X(r11) | |
3147 | ldq_u r2,X+7(r11) | |
3148 | lda r3,X(r11) | |
3149 | extql r1,r3,r1 | |
3150 | extqh r2,r3,r2 | |
3151 | or r1.r2.r1 | |
3152 | */ | |
3153 | ||
3154 | void | |
92643d95 | 3155 | alpha_expand_unaligned_load (rtx tgt, rtx mem, HOST_WIDE_INT size, |
3156 | HOST_WIDE_INT ofs, int sign) | |
34377880 | 3157 | { |
1f0ce6a6 | 3158 | rtx meml, memh, addr, extl, exth, tmp, mema; |
2cc46ade | 3159 | enum machine_mode mode; |
34377880 | 3160 | |
3161 | meml = gen_reg_rtx (DImode); | |
3162 | memh = gen_reg_rtx (DImode); | |
3163 | addr = gen_reg_rtx (DImode); | |
3164 | extl = gen_reg_rtx (DImode); | |
3165 | exth = gen_reg_rtx (DImode); | |
3166 | ||
1f0ce6a6 | 3167 | mema = XEXP (mem, 0); |
3168 | if (GET_CODE (mema) == LO_SUM) | |
3169 | mema = force_reg (Pmode, mema); | |
3170 | ||
3024e9f8 | 3171 | /* AND addresses cannot be in any alias set, since they may implicitly |
9e7454d0 | 3172 | alias surrounding code. Ideally we'd have some alias set that |
3024e9f8 | 3173 | covered all types except those with alignment 8 or higher. */ |
3174 | ||
3175 | tmp = change_address (mem, DImode, | |
9e7454d0 | 3176 | gen_rtx_AND (DImode, |
1f0ce6a6 | 3177 | plus_constant (mema, ofs), |
3024e9f8 | 3178 | GEN_INT (-8))); |
ab6ab77e | 3179 | set_mem_alias_set (tmp, 0); |
3024e9f8 | 3180 | emit_move_insn (meml, tmp); |
3181 | ||
3182 | tmp = change_address (mem, DImode, | |
9e7454d0 | 3183 | gen_rtx_AND (DImode, |
1f0ce6a6 | 3184 | plus_constant (mema, ofs + size - 1), |
3024e9f8 | 3185 | GEN_INT (-8))); |
ab6ab77e | 3186 | set_mem_alias_set (tmp, 0); |
3024e9f8 | 3187 | emit_move_insn (memh, tmp); |
34377880 | 3188 | |
9caef960 | 3189 | if (WORDS_BIG_ENDIAN && sign && (size == 2 || size == 4)) |
3190 | { | |
3191 | emit_move_insn (addr, plus_constant (mema, -1)); | |
3192 | ||
3193 | emit_insn (gen_extqh_be (extl, meml, addr)); | |
3194 | emit_insn (gen_extxl_be (exth, memh, GEN_INT (64), addr)); | |
3195 | ||
3196 | addr = expand_binop (DImode, ior_optab, extl, exth, tgt, 1, OPTAB_WIDEN); | |
3197 | addr = expand_binop (DImode, ashr_optab, addr, GEN_INT (64 - size*8), | |
3198 | addr, 1, OPTAB_WIDEN); | |
3199 | } | |
3200 | else if (sign && size == 2) | |
34377880 | 3201 | { |
1f0ce6a6 | 3202 | emit_move_insn (addr, plus_constant (mema, ofs+2)); |
34377880 | 3203 | |
9caef960 | 3204 | emit_insn (gen_extxl_le (extl, meml, GEN_INT (64), addr)); |
3205 | emit_insn (gen_extqh_le (exth, memh, addr)); | |
34377880 | 3206 | |
ba4a7733 | 3207 | /* We must use tgt here for the target. Alpha-vms port fails if we use |
3208 | addr for the target, because addr is marked as a pointer and combine | |
3209 | knows that pointers are always sign-extended 32 bit values. */ | |
3210 | addr = expand_binop (DImode, ior_optab, extl, exth, tgt, 1, OPTAB_WIDEN); | |
9e7454d0 | 3211 | addr = expand_binop (DImode, ashr_optab, addr, GEN_INT (48), |
2cc46ade | 3212 | addr, 1, OPTAB_WIDEN); |
34377880 | 3213 | } |
2cc46ade | 3214 | else |
34377880 | 3215 | { |
9caef960 | 3216 | if (WORDS_BIG_ENDIAN) |
2cc46ade | 3217 | { |
9caef960 | 3218 | emit_move_insn (addr, plus_constant (mema, ofs+size-1)); |
3219 | switch ((int) size) | |
3220 | { | |
3221 | case 2: | |
3222 | emit_insn (gen_extwh_be (extl, meml, addr)); | |
3223 | mode = HImode; | |
3224 | break; | |
34377880 | 3225 | |
9caef960 | 3226 | case 4: |
3227 | emit_insn (gen_extlh_be (extl, meml, addr)); | |
3228 | mode = SImode; | |
3229 | break; | |
34377880 | 3230 | |
9caef960 | 3231 | case 8: |
3232 | emit_insn (gen_extqh_be (extl, meml, addr)); | |
3233 | mode = DImode; | |
3234 | break; | |
915c336f | 3235 | |
9caef960 | 3236 | default: |
3237 | abort (); | |
3238 | } | |
3239 | emit_insn (gen_extxl_be (exth, memh, GEN_INT (size*8), addr)); | |
3240 | } | |
3241 | else | |
3242 | { | |
3243 | emit_move_insn (addr, plus_constant (mema, ofs)); | |
3244 | emit_insn (gen_extxl_le (extl, meml, GEN_INT (size*8), addr)); | |
3245 | switch ((int) size) | |
3246 | { | |
3247 | case 2: | |
3248 | emit_insn (gen_extwh_le (exth, memh, addr)); | |
3249 | mode = HImode; | |
3250 | break; | |
3251 | ||
3252 | case 4: | |
3253 | emit_insn (gen_extlh_le (exth, memh, addr)); | |
3254 | mode = SImode; | |
3255 | break; | |
3256 | ||
3257 | case 8: | |
3258 | emit_insn (gen_extqh_le (exth, memh, addr)); | |
3259 | mode = DImode; | |
3260 | break; | |
3261 | ||
3262 | default: | |
3263 | abort(); | |
3264 | } | |
2cc46ade | 3265 | } |
3266 | ||
3267 | addr = expand_binop (mode, ior_optab, gen_lowpart (mode, extl), | |
3268 | gen_lowpart (mode, exth), gen_lowpart (mode, tgt), | |
3269 | sign, OPTAB_WIDEN); | |
34377880 | 3270 | } |
3271 | ||
2cc46ade | 3272 | if (addr != tgt) |
3273 | emit_move_insn (tgt, gen_lowpart(GET_MODE (tgt), addr)); | |
34377880 | 3274 | } |
3275 | ||
3276 | /* Similarly, use ins and msk instructions to perform unaligned stores. */ | |
3277 | ||
3278 | void | |
92643d95 | 3279 | alpha_expand_unaligned_store (rtx dst, rtx src, |
3280 | HOST_WIDE_INT size, HOST_WIDE_INT ofs) | |
34377880 | 3281 | { |
1f0ce6a6 | 3282 | rtx dstl, dsth, addr, insl, insh, meml, memh, dsta; |
9e7454d0 | 3283 | |
34377880 | 3284 | dstl = gen_reg_rtx (DImode); |
3285 | dsth = gen_reg_rtx (DImode); | |
3286 | insl = gen_reg_rtx (DImode); | |
3287 | insh = gen_reg_rtx (DImode); | |
3288 | ||
1f0ce6a6 | 3289 | dsta = XEXP (dst, 0); |
3290 | if (GET_CODE (dsta) == LO_SUM) | |
3291 | dsta = force_reg (Pmode, dsta); | |
3292 | ||
3024e9f8 | 3293 | /* AND addresses cannot be in any alias set, since they may implicitly |
9e7454d0 | 3294 | alias surrounding code. Ideally we'd have some alias set that |
3024e9f8 | 3295 | covered all types except those with alignment 8 or higher. */ |
3296 | ||
34377880 | 3297 | meml = change_address (dst, DImode, |
9e7454d0 | 3298 | gen_rtx_AND (DImode, |
1f0ce6a6 | 3299 | plus_constant (dsta, ofs), |
941522d6 | 3300 | GEN_INT (-8))); |
ab6ab77e | 3301 | set_mem_alias_set (meml, 0); |
3024e9f8 | 3302 | |
34377880 | 3303 | memh = change_address (dst, DImode, |
9e7454d0 | 3304 | gen_rtx_AND (DImode, |
1f0ce6a6 | 3305 | plus_constant (dsta, ofs + size - 1), |
941522d6 | 3306 | GEN_INT (-8))); |
ab6ab77e | 3307 | set_mem_alias_set (memh, 0); |
34377880 | 3308 | |
3309 | emit_move_insn (dsth, memh); | |
3310 | emit_move_insn (dstl, meml); | |
9caef960 | 3311 | if (WORDS_BIG_ENDIAN) |
34377880 | 3312 | { |
9caef960 | 3313 | addr = copy_addr_to_reg (plus_constant (dsta, ofs+size-1)); |
3314 | ||
3315 | if (src != const0_rtx) | |
3316 | { | |
3317 | switch ((int) size) | |
3318 | { | |
3319 | case 2: | |
3320 | emit_insn (gen_inswl_be (insh, gen_lowpart (HImode,src), addr)); | |
3321 | break; | |
3322 | case 4: | |
3323 | emit_insn (gen_insll_be (insh, gen_lowpart (SImode,src), addr)); | |
3324 | break; | |
3325 | case 8: | |
3326 | emit_insn (gen_insql_be (insh, gen_lowpart (DImode,src), addr)); | |
3327 | break; | |
3328 | } | |
3329 | emit_insn (gen_insxh (insl, gen_lowpart (DImode, src), | |
3330 | GEN_INT (size*8), addr)); | |
3331 | } | |
34377880 | 3332 | |
29768226 | 3333 | switch ((int) size) |
34377880 | 3334 | { |
3335 | case 2: | |
9caef960 | 3336 | emit_insn (gen_mskxl_be (dsth, dsth, GEN_INT (0xffff), addr)); |
34377880 | 3337 | break; |
3338 | case 4: | |
9caef960 | 3339 | { |
ae4cd3a5 | 3340 | rtx msk = immed_double_const (0xffffffff, 0, DImode); |
9caef960 | 3341 | emit_insn (gen_mskxl_be (dsth, dsth, msk, addr)); |
ae4cd3a5 | 3342 | break; |
9caef960 | 3343 | } |
ae4cd3a5 | 3344 | case 8: |
3345 | emit_insn (gen_mskxl_be (dsth, dsth, constm1_rtx, addr)); | |
34377880 | 3346 | break; |
3347 | } | |
9caef960 | 3348 | |
3349 | emit_insn (gen_mskxh (dstl, dstl, GEN_INT (size*8), addr)); | |
34377880 | 3350 | } |
9caef960 | 3351 | else |
3352 | { | |
3353 | addr = copy_addr_to_reg (plus_constant (dsta, ofs)); | |
34377880 | 3354 | |
9caef960 | 3355 | if (src != const0_rtx) |
3356 | { | |
3357 | emit_insn (gen_insxh (insh, gen_lowpart (DImode, src), | |
3358 | GEN_INT (size*8), addr)); | |
34377880 | 3359 | |
9caef960 | 3360 | switch ((int) size) |
3361 | { | |
3362 | case 2: | |
3363 | emit_insn (gen_inswl_le (insl, gen_lowpart (HImode, src), addr)); | |
3364 | break; | |
3365 | case 4: | |
3366 | emit_insn (gen_insll_le (insl, gen_lowpart (SImode, src), addr)); | |
3367 | break; | |
3368 | case 8: | |
3369 | emit_insn (gen_insql_le (insl, src, addr)); | |
3370 | break; | |
3371 | } | |
3372 | } | |
3373 | ||
3374 | emit_insn (gen_mskxh (dsth, dsth, GEN_INT (size*8), addr)); | |
3375 | ||
3376 | switch ((int) size) | |
3377 | { | |
3378 | case 2: | |
3379 | emit_insn (gen_mskxl_le (dstl, dstl, GEN_INT (0xffff), addr)); | |
3380 | break; | |
3381 | case 4: | |
9caef960 | 3382 | { |
ae4cd3a5 | 3383 | rtx msk = immed_double_const (0xffffffff, 0, DImode); |
9caef960 | 3384 | emit_insn (gen_mskxl_le (dstl, dstl, msk, addr)); |
ae4cd3a5 | 3385 | break; |
9caef960 | 3386 | } |
ae4cd3a5 | 3387 | case 8: |
3388 | emit_insn (gen_mskxl_le (dstl, dstl, constm1_rtx, addr)); | |
9caef960 | 3389 | break; |
3390 | } | |
34377880 | 3391 | } |
3392 | ||
3393 | if (src != const0_rtx) | |
3394 | { | |
2cc46ade | 3395 | dsth = expand_binop (DImode, ior_optab, insh, dsth, dsth, 0, OPTAB_WIDEN); |
3396 | dstl = expand_binop (DImode, ior_optab, insl, dstl, dstl, 0, OPTAB_WIDEN); | |
34377880 | 3397 | } |
9e7454d0 | 3398 | |
9caef960 | 3399 | if (WORDS_BIG_ENDIAN) |
3400 | { | |
3401 | emit_move_insn (meml, dstl); | |
3402 | emit_move_insn (memh, dsth); | |
3403 | } | |
3404 | else | |
3405 | { | |
3406 | /* Must store high before low for degenerate case of aligned. */ | |
3407 | emit_move_insn (memh, dsth); | |
3408 | emit_move_insn (meml, dstl); | |
3409 | } | |
34377880 | 3410 | } |
3411 | ||
2cc46ade | 3412 | /* The block move code tries to maximize speed by separating loads and |
3413 | stores at the expense of register pressure: we load all of the data | |
3414 | before we store it back out. There are two secondary effects worth | |
3415 | mentioning, that this speeds copying to/from aligned and unaligned | |
3416 | buffers, and that it makes the code significantly easier to write. */ | |
34377880 | 3417 | |
2cc46ade | 3418 | #define MAX_MOVE_WORDS 8 |
3419 | ||
3420 | /* Load an integral number of consecutive unaligned quadwords. */ | |
34377880 | 3421 | |
3422 | static void | |
92643d95 | 3423 | alpha_expand_unaligned_load_words (rtx *out_regs, rtx smem, |
3424 | HOST_WIDE_INT words, HOST_WIDE_INT ofs) | |
34377880 | 3425 | { |
3426 | rtx const im8 = GEN_INT (-8); | |
3427 | rtx const i64 = GEN_INT (64); | |
2cc46ade | 3428 | rtx ext_tmps[MAX_MOVE_WORDS], data_regs[MAX_MOVE_WORDS+1]; |
1f0ce6a6 | 3429 | rtx sreg, areg, tmp, smema; |
34377880 | 3430 | HOST_WIDE_INT i; |
3431 | ||
1f0ce6a6 | 3432 | smema = XEXP (smem, 0); |
3433 | if (GET_CODE (smema) == LO_SUM) | |
3434 | smema = force_reg (Pmode, smema); | |
3435 | ||
34377880 | 3436 | /* Generate all the tmp registers we need. */ |
3437 | for (i = 0; i < words; ++i) | |
2cc46ade | 3438 | { |
3439 | data_regs[i] = out_regs[i]; | |
3440 | ext_tmps[i] = gen_reg_rtx (DImode); | |
3441 | } | |
3442 | data_regs[words] = gen_reg_rtx (DImode); | |
3443 | ||
3444 | if (ofs != 0) | |
e513d163 | 3445 | smem = adjust_address (smem, GET_MODE (smem), ofs); |
9e7454d0 | 3446 | |
34377880 | 3447 | /* Load up all of the source data. */ |
3448 | for (i = 0; i < words; ++i) | |
3449 | { | |
3024e9f8 | 3450 | tmp = change_address (smem, DImode, |
3451 | gen_rtx_AND (DImode, | |
1f0ce6a6 | 3452 | plus_constant (smema, 8*i), |
3024e9f8 | 3453 | im8)); |
ab6ab77e | 3454 | set_mem_alias_set (tmp, 0); |
3024e9f8 | 3455 | emit_move_insn (data_regs[i], tmp); |
34377880 | 3456 | } |
3024e9f8 | 3457 | |
3458 | tmp = change_address (smem, DImode, | |
3459 | gen_rtx_AND (DImode, | |
1f0ce6a6 | 3460 | plus_constant (smema, 8*words - 1), |
3024e9f8 | 3461 | im8)); |
ab6ab77e | 3462 | set_mem_alias_set (tmp, 0); |
3024e9f8 | 3463 | emit_move_insn (data_regs[words], tmp); |
34377880 | 3464 | |
3465 | /* Extract the half-word fragments. Unfortunately DEC decided to make | |
9e7454d0 | 3466 | extxh with offset zero a noop instead of zeroing the register, so |
34377880 | 3467 | we must take care of that edge condition ourselves with cmov. */ |
3468 | ||
1f0ce6a6 | 3469 | sreg = copy_addr_to_reg (smema); |
9e7454d0 | 3470 | areg = expand_binop (DImode, and_optab, sreg, GEN_INT (7), NULL, |
2cc46ade | 3471 | 1, OPTAB_WIDEN); |
9caef960 | 3472 | if (WORDS_BIG_ENDIAN) |
3473 | emit_move_insn (sreg, plus_constant (sreg, 7)); | |
34377880 | 3474 | for (i = 0; i < words; ++i) |
3475 | { | |
9caef960 | 3476 | if (WORDS_BIG_ENDIAN) |
3477 | { | |
3478 | emit_insn (gen_extqh_be (data_regs[i], data_regs[i], sreg)); | |
3479 | emit_insn (gen_extxl_be (ext_tmps[i], data_regs[i+1], i64, sreg)); | |
3480 | } | |
3481 | else | |
3482 | { | |
3483 | emit_insn (gen_extxl_le (data_regs[i], data_regs[i], i64, sreg)); | |
3484 | emit_insn (gen_extqh_le (ext_tmps[i], data_regs[i+1], sreg)); | |
3485 | } | |
941522d6 | 3486 | emit_insn (gen_rtx_SET (VOIDmode, ext_tmps[i], |
3487 | gen_rtx_IF_THEN_ELSE (DImode, | |
2cc46ade | 3488 | gen_rtx_EQ (DImode, areg, |
3489 | const0_rtx), | |
941522d6 | 3490 | const0_rtx, ext_tmps[i]))); |
34377880 | 3491 | } |
3492 | ||
3493 | /* Merge the half-words into whole words. */ | |
3494 | for (i = 0; i < words; ++i) | |
3495 | { | |
2cc46ade | 3496 | out_regs[i] = expand_binop (DImode, ior_optab, data_regs[i], |
3497 | ext_tmps[i], data_regs[i], 1, OPTAB_WIDEN); | |
34377880 | 3498 | } |
3499 | } | |
3500 | ||
3501 | /* Store an integral number of consecutive unaligned quadwords. DATA_REGS | |
3502 | may be NULL to store zeros. */ | |
3503 | ||
3504 | static void | |
92643d95 | 3505 | alpha_expand_unaligned_store_words (rtx *data_regs, rtx dmem, |
3506 | HOST_WIDE_INT words, HOST_WIDE_INT ofs) | |
34377880 | 3507 | { |
3508 | rtx const im8 = GEN_INT (-8); | |
3509 | rtx const i64 = GEN_INT (64); | |
34377880 | 3510 | rtx ins_tmps[MAX_MOVE_WORDS]; |
2cc46ade | 3511 | rtx st_tmp_1, st_tmp_2, dreg; |
1f0ce6a6 | 3512 | rtx st_addr_1, st_addr_2, dmema; |
34377880 | 3513 | HOST_WIDE_INT i; |
3514 | ||
1f0ce6a6 | 3515 | dmema = XEXP (dmem, 0); |
3516 | if (GET_CODE (dmema) == LO_SUM) | |
3517 | dmema = force_reg (Pmode, dmema); | |
3518 | ||
34377880 | 3519 | /* Generate all the tmp registers we need. */ |
3520 | if (data_regs != NULL) | |
3521 | for (i = 0; i < words; ++i) | |
3522 | ins_tmps[i] = gen_reg_rtx(DImode); | |
3523 | st_tmp_1 = gen_reg_rtx(DImode); | |
3524 | st_tmp_2 = gen_reg_rtx(DImode); | |
9e7454d0 | 3525 | |
2cc46ade | 3526 | if (ofs != 0) |
e513d163 | 3527 | dmem = adjust_address (dmem, GET_MODE (dmem), ofs); |
2cc46ade | 3528 | |
3529 | st_addr_2 = change_address (dmem, DImode, | |
941522d6 | 3530 | gen_rtx_AND (DImode, |
1f0ce6a6 | 3531 | plus_constant (dmema, words*8 - 1), |
34377880 | 3532 | im8)); |
ab6ab77e | 3533 | set_mem_alias_set (st_addr_2, 0); |
3024e9f8 | 3534 | |
2cc46ade | 3535 | st_addr_1 = change_address (dmem, DImode, |
1f0ce6a6 | 3536 | gen_rtx_AND (DImode, dmema, im8)); |
ab6ab77e | 3537 | set_mem_alias_set (st_addr_1, 0); |
34377880 | 3538 | |
3539 | /* Load up the destination end bits. */ | |
3540 | emit_move_insn (st_tmp_2, st_addr_2); | |
3541 | emit_move_insn (st_tmp_1, st_addr_1); | |
3542 | ||
3543 | /* Shift the input data into place. */ | |
1f0ce6a6 | 3544 | dreg = copy_addr_to_reg (dmema); |
9caef960 | 3545 | if (WORDS_BIG_ENDIAN) |
3546 | emit_move_insn (dreg, plus_constant (dreg, 7)); | |
34377880 | 3547 | if (data_regs != NULL) |
3548 | { | |
3549 | for (i = words-1; i >= 0; --i) | |
3550 | { | |
9caef960 | 3551 | if (WORDS_BIG_ENDIAN) |
3552 | { | |
3553 | emit_insn (gen_insql_be (ins_tmps[i], data_regs[i], dreg)); | |
3554 | emit_insn (gen_insxh (data_regs[i], data_regs[i], i64, dreg)); | |
3555 | } | |
3556 | else | |
3557 | { | |
3558 | emit_insn (gen_insxh (ins_tmps[i], data_regs[i], i64, dreg)); | |
3559 | emit_insn (gen_insql_le (data_regs[i], data_regs[i], dreg)); | |
3560 | } | |
34377880 | 3561 | } |
34377880 | 3562 | for (i = words-1; i > 0; --i) |
3563 | { | |
2cc46ade | 3564 | ins_tmps[i-1] = expand_binop (DImode, ior_optab, data_regs[i], |
3565 | ins_tmps[i-1], ins_tmps[i-1], 1, | |
3566 | OPTAB_WIDEN); | |
34377880 | 3567 | } |
3568 | } | |
3569 | ||
3570 | /* Split and merge the ends with the destination data. */ | |
9caef960 | 3571 | if (WORDS_BIG_ENDIAN) |
3572 | { | |
ae4cd3a5 | 3573 | emit_insn (gen_mskxl_be (st_tmp_2, st_tmp_2, constm1_rtx, dreg)); |
9caef960 | 3574 | emit_insn (gen_mskxh (st_tmp_1, st_tmp_1, i64, dreg)); |
3575 | } | |
3576 | else | |
3577 | { | |
3578 | emit_insn (gen_mskxh (st_tmp_2, st_tmp_2, i64, dreg)); | |
ae4cd3a5 | 3579 | emit_insn (gen_mskxl_le (st_tmp_1, st_tmp_1, constm1_rtx, dreg)); |
9caef960 | 3580 | } |
34377880 | 3581 | |
3582 | if (data_regs != NULL) | |
3583 | { | |
2cc46ade | 3584 | st_tmp_2 = expand_binop (DImode, ior_optab, st_tmp_2, ins_tmps[words-1], |
3585 | st_tmp_2, 1, OPTAB_WIDEN); | |
3586 | st_tmp_1 = expand_binop (DImode, ior_optab, st_tmp_1, data_regs[0], | |
3587 | st_tmp_1, 1, OPTAB_WIDEN); | |
34377880 | 3588 | } |
3589 | ||
3590 | /* Store it all. */ | |
9caef960 | 3591 | if (WORDS_BIG_ENDIAN) |
3592 | emit_move_insn (st_addr_1, st_tmp_1); | |
3593 | else | |
3594 | emit_move_insn (st_addr_2, st_tmp_2); | |
34377880 | 3595 | for (i = words-1; i > 0; --i) |
3596 | { | |
3024e9f8 | 3597 | rtx tmp = change_address (dmem, DImode, |
3598 | gen_rtx_AND (DImode, | |
9caef960 | 3599 | plus_constant(dmema, |
3600 | WORDS_BIG_ENDIAN ? i*8-1 : i*8), | |
3024e9f8 | 3601 | im8)); |
ab6ab77e | 3602 | set_mem_alias_set (tmp, 0); |
3024e9f8 | 3603 | emit_move_insn (tmp, data_regs ? ins_tmps[i-1] : const0_rtx); |
34377880 | 3604 | } |
9caef960 | 3605 | if (WORDS_BIG_ENDIAN) |
3606 | emit_move_insn (st_addr_2, st_tmp_2); | |
3607 | else | |
3608 | emit_move_insn (st_addr_1, st_tmp_1); | |
34377880 | 3609 | } |
3610 | ||
3611 | ||
3612 | /* Expand string/block move operations. | |
3613 | ||
3614 | operands[0] is the pointer to the destination. | |
3615 | operands[1] is the pointer to the source. | |
3616 | operands[2] is the number of bytes to move. | |
3617 | operands[3] is the alignment. */ | |
3618 | ||
3619 | int | |
92643d95 | 3620 | alpha_expand_block_move (rtx operands[]) |
34377880 | 3621 | { |
3622 | rtx bytes_rtx = operands[2]; | |
3623 | rtx align_rtx = operands[3]; | |
d94b545b | 3624 | HOST_WIDE_INT orig_bytes = INTVAL (bytes_rtx); |
a9aaae37 | 3625 | HOST_WIDE_INT bytes = orig_bytes; |
3626 | HOST_WIDE_INT src_align = INTVAL (align_rtx) * BITS_PER_UNIT; | |
3627 | HOST_WIDE_INT dst_align = src_align; | |
80909c64 | 3628 | rtx orig_src = operands[1]; |
3629 | rtx orig_dst = operands[0]; | |
3630 | rtx data_regs[2 * MAX_MOVE_WORDS + 16]; | |
2cc46ade | 3631 | rtx tmp; |
1f0ce6a6 | 3632 | unsigned int i, words, ofs, nregs = 0; |
9e7454d0 | 3633 | |
80909c64 | 3634 | if (orig_bytes <= 0) |
34377880 | 3635 | return 1; |
a9aaae37 | 3636 | else if (orig_bytes > MAX_MOVE_WORDS * UNITS_PER_WORD) |
34377880 | 3637 | return 0; |
3638 | ||
2cc46ade | 3639 | /* Look for additional alignment information from recorded register info. */ |
3640 | ||
3641 | tmp = XEXP (orig_src, 0); | |
3642 | if (GET_CODE (tmp) == REG) | |
80909c64 | 3643 | src_align = MAX (src_align, REGNO_POINTER_ALIGN (REGNO (tmp))); |
2cc46ade | 3644 | else if (GET_CODE (tmp) == PLUS |
3645 | && GET_CODE (XEXP (tmp, 0)) == REG | |
3646 | && GET_CODE (XEXP (tmp, 1)) == CONST_INT) | |
3647 | { | |
80909c64 | 3648 | unsigned HOST_WIDE_INT c = INTVAL (XEXP (tmp, 1)); |
3649 | unsigned int a = REGNO_POINTER_ALIGN (REGNO (XEXP (tmp, 0))); | |
2cc46ade | 3650 | |
3651 | if (a > src_align) | |
3652 | { | |
80909c64 | 3653 | if (a >= 64 && c % 8 == 0) |
3654 | src_align = 64; | |
3655 | else if (a >= 32 && c % 4 == 0) | |
3656 | src_align = 32; | |
3657 | else if (a >= 16 && c % 2 == 0) | |
3658 | src_align = 16; | |
2cc46ade | 3659 | } |
3660 | } | |
9e7454d0 | 3661 | |
2cc46ade | 3662 | tmp = XEXP (orig_dst, 0); |
3663 | if (GET_CODE (tmp) == REG) | |
80909c64 | 3664 | dst_align = MAX (dst_align, REGNO_POINTER_ALIGN (REGNO (tmp))); |
2cc46ade | 3665 | else if (GET_CODE (tmp) == PLUS |
3666 | && GET_CODE (XEXP (tmp, 0)) == REG | |
3667 | && GET_CODE (XEXP (tmp, 1)) == CONST_INT) | |
3668 | { | |
80909c64 | 3669 | unsigned HOST_WIDE_INT c = INTVAL (XEXP (tmp, 1)); |
3670 | unsigned int a = REGNO_POINTER_ALIGN (REGNO (XEXP (tmp, 0))); | |
2cc46ade | 3671 | |
3672 | if (a > dst_align) | |
3673 | { | |
80909c64 | 3674 | if (a >= 64 && c % 8 == 0) |
3675 | dst_align = 64; | |
3676 | else if (a >= 32 && c % 4 == 0) | |
3677 | dst_align = 32; | |
3678 | else if (a >= 16 && c % 2 == 0) | |
3679 | dst_align = 16; | |
2cc46ade | 3680 | } |
3681 | } | |
3682 | ||
2cc46ade | 3683 | ofs = 0; |
80909c64 | 3684 | if (src_align >= 64 && bytes >= 8) |
34377880 | 3685 | { |
3686 | words = bytes / 8; | |
3687 | ||
34377880 | 3688 | for (i = 0; i < words; ++i) |
27d0c333 | 3689 | data_regs[nregs + i] = gen_reg_rtx (DImode); |
34377880 | 3690 | |
34377880 | 3691 | for (i = 0; i < words; ++i) |
80909c64 | 3692 | emit_move_insn (data_regs[nregs + i], |
e513d163 | 3693 | adjust_address (orig_src, DImode, ofs + i * 8)); |
34377880 | 3694 | |
2cc46ade | 3695 | nregs += words; |
34377880 | 3696 | bytes -= words * 8; |
7597afe9 | 3697 | ofs += words * 8; |
34377880 | 3698 | } |
80909c64 | 3699 | |
3700 | if (src_align >= 32 && bytes >= 4) | |
34377880 | 3701 | { |
3702 | words = bytes / 4; | |
3703 | ||
34377880 | 3704 | for (i = 0; i < words; ++i) |
27d0c333 | 3705 | data_regs[nregs + i] = gen_reg_rtx (SImode); |
34377880 | 3706 | |
34377880 | 3707 | for (i = 0; i < words; ++i) |
80909c64 | 3708 | emit_move_insn (data_regs[nregs + i], |
537ffcfc | 3709 | adjust_address (orig_src, SImode, ofs + i * 4)); |
34377880 | 3710 | |
2cc46ade | 3711 | nregs += words; |
34377880 | 3712 | bytes -= words * 4; |
7597afe9 | 3713 | ofs += words * 4; |
34377880 | 3714 | } |
80909c64 | 3715 | |
a9aaae37 | 3716 | if (bytes >= 8) |
34377880 | 3717 | { |
3718 | words = bytes / 8; | |
3719 | ||
34377880 | 3720 | for (i = 0; i < words+1; ++i) |
27d0c333 | 3721 | data_regs[nregs + i] = gen_reg_rtx (DImode); |
34377880 | 3722 | |
b47268cf | 3723 | alpha_expand_unaligned_load_words (data_regs + nregs, orig_src, |
3724 | words, ofs); | |
34377880 | 3725 | |
2cc46ade | 3726 | nregs += words; |
34377880 | 3727 | bytes -= words * 8; |
7597afe9 | 3728 | ofs += words * 8; |
34377880 | 3729 | } |
80909c64 | 3730 | |
80909c64 | 3731 | if (! TARGET_BWX && bytes >= 4) |
34377880 | 3732 | { |
2cc46ade | 3733 | data_regs[nregs++] = tmp = gen_reg_rtx (SImode); |
34377880 | 3734 | alpha_expand_unaligned_load (tmp, orig_src, 4, ofs, 0); |
34377880 | 3735 | bytes -= 4; |
3736 | ofs += 4; | |
3737 | } | |
80909c64 | 3738 | |
34377880 | 3739 | if (bytes >= 2) |
3740 | { | |
80909c64 | 3741 | if (src_align >= 16) |
34377880 | 3742 | { |
3743 | do { | |
2cc46ade | 3744 | data_regs[nregs++] = tmp = gen_reg_rtx (HImode); |
e513d163 | 3745 | emit_move_insn (tmp, adjust_address (orig_src, HImode, ofs)); |
34377880 | 3746 | bytes -= 2; |
3747 | ofs += 2; | |
3748 | } while (bytes >= 2); | |
3749 | } | |
80909c64 | 3750 | else if (! TARGET_BWX) |
34377880 | 3751 | { |
2cc46ade | 3752 | data_regs[nregs++] = tmp = gen_reg_rtx (HImode); |
34377880 | 3753 | alpha_expand_unaligned_load (tmp, orig_src, 2, ofs, 0); |
34377880 | 3754 | bytes -= 2; |
3755 | ofs += 2; | |
3756 | } | |
3757 | } | |
80909c64 | 3758 | |
34377880 | 3759 | while (bytes > 0) |
3760 | { | |
2cc46ade | 3761 | data_regs[nregs++] = tmp = gen_reg_rtx (QImode); |
e513d163 | 3762 | emit_move_insn (tmp, adjust_address (orig_src, QImode, ofs)); |
34377880 | 3763 | bytes -= 1; |
3764 | ofs += 1; | |
3765 | } | |
80909c64 | 3766 | |
d6a88f01 | 3767 | if (nregs > ARRAY_SIZE (data_regs)) |
80909c64 | 3768 | abort (); |
2cc46ade | 3769 | |
80909c64 | 3770 | /* Now save it back out again. */ |
2cc46ade | 3771 | |
3772 | i = 0, ofs = 0; | |
3773 | ||
2cc46ade | 3774 | /* Write out the data in whatever chunks reading the source allowed. */ |
80909c64 | 3775 | if (dst_align >= 64) |
2cc46ade | 3776 | { |
3777 | while (i < nregs && GET_MODE (data_regs[i]) == DImode) | |
3778 | { | |
e513d163 | 3779 | emit_move_insn (adjust_address (orig_dst, DImode, ofs), |
2cc46ade | 3780 | data_regs[i]); |
3781 | ofs += 8; | |
3782 | i++; | |
3783 | } | |
3784 | } | |
80909c64 | 3785 | |
3786 | if (dst_align >= 32) | |
2cc46ade | 3787 | { |
3788 | /* If the source has remaining DImode regs, write them out in | |
3789 | two pieces. */ | |
3790 | while (i < nregs && GET_MODE (data_regs[i]) == DImode) | |
3791 | { | |
3792 | tmp = expand_binop (DImode, lshr_optab, data_regs[i], GEN_INT (32), | |
3793 | NULL_RTX, 1, OPTAB_WIDEN); | |
3794 | ||
e513d163 | 3795 | emit_move_insn (adjust_address (orig_dst, SImode, ofs), |
2cc46ade | 3796 | gen_lowpart (SImode, data_regs[i])); |
e513d163 | 3797 | emit_move_insn (adjust_address (orig_dst, SImode, ofs + 4), |
2cc46ade | 3798 | gen_lowpart (SImode, tmp)); |
3799 | ofs += 8; | |
3800 | i++; | |
3801 | } | |
3802 | ||
3803 | while (i < nregs && GET_MODE (data_regs[i]) == SImode) | |
3804 | { | |
e513d163 | 3805 | emit_move_insn (adjust_address (orig_dst, SImode, ofs), |
2cc46ade | 3806 | data_regs[i]); |
3807 | ofs += 4; | |
3808 | i++; | |
3809 | } | |
3810 | } | |
80909c64 | 3811 | |
2cc46ade | 3812 | if (i < nregs && GET_MODE (data_regs[i]) == DImode) |
3813 | { | |
3814 | /* Write out a remaining block of words using unaligned methods. */ | |
3815 | ||
80909c64 | 3816 | for (words = 1; i + words < nregs; words++) |
3817 | if (GET_MODE (data_regs[i + words]) != DImode) | |
2cc46ade | 3818 | break; |
3819 | ||
3820 | if (words == 1) | |
3821 | alpha_expand_unaligned_store (orig_dst, data_regs[i], 8, ofs); | |
3822 | else | |
80909c64 | 3823 | alpha_expand_unaligned_store_words (data_regs + i, orig_dst, |
3824 | words, ofs); | |
9e7454d0 | 3825 | |
2cc46ade | 3826 | i += words; |
3827 | ofs += words * 8; | |
3828 | } | |
3829 | ||
3830 | /* Due to the above, this won't be aligned. */ | |
3831 | /* ??? If we have more than one of these, consider constructing full | |
3832 | words in registers and using alpha_expand_unaligned_store_words. */ | |
3833 | while (i < nregs && GET_MODE (data_regs[i]) == SImode) | |
3834 | { | |
3835 | alpha_expand_unaligned_store (orig_dst, data_regs[i], 4, ofs); | |
3836 | ofs += 4; | |
3837 | i++; | |
3838 | } | |
3839 | ||
80909c64 | 3840 | if (dst_align >= 16) |
2cc46ade | 3841 | while (i < nregs && GET_MODE (data_regs[i]) == HImode) |
3842 | { | |
e513d163 | 3843 | emit_move_insn (adjust_address (orig_dst, HImode, ofs), data_regs[i]); |
2cc46ade | 3844 | i++; |
3845 | ofs += 2; | |
3846 | } | |
3847 | else | |
3848 | while (i < nregs && GET_MODE (data_regs[i]) == HImode) | |
3849 | { | |
3850 | alpha_expand_unaligned_store (orig_dst, data_regs[i], 2, ofs); | |
3851 | i++; | |
3852 | ofs += 2; | |
3853 | } | |
80909c64 | 3854 | |
2cc46ade | 3855 | while (i < nregs && GET_MODE (data_regs[i]) == QImode) |
3856 | { | |
e513d163 | 3857 | emit_move_insn (adjust_address (orig_dst, QImode, ofs), data_regs[i]); |
2cc46ade | 3858 | i++; |
3859 | ofs += 1; | |
3860 | } | |
80909c64 | 3861 | |
2cc46ade | 3862 | if (i != nregs) |
80909c64 | 3863 | abort (); |
34377880 | 3864 | |
3865 | return 1; | |
3866 | } | |
3867 | ||
3868 | int | |
92643d95 | 3869 | alpha_expand_block_clear (rtx operands[]) |
34377880 | 3870 | { |
3871 | rtx bytes_rtx = operands[1]; | |
3872 | rtx align_rtx = operands[2]; | |
80909c64 | 3873 | HOST_WIDE_INT orig_bytes = INTVAL (bytes_rtx); |
a9aaae37 | 3874 | HOST_WIDE_INT bytes = orig_bytes; |
3875 | HOST_WIDE_INT align = INTVAL (align_rtx) * BITS_PER_UNIT; | |
3876 | HOST_WIDE_INT alignofs = 0; | |
80909c64 | 3877 | rtx orig_dst = operands[0]; |
2cc46ade | 3878 | rtx tmp; |
a9aaae37 | 3879 | int i, words, ofs = 0; |
9e7454d0 | 3880 | |
80909c64 | 3881 | if (orig_bytes <= 0) |
34377880 | 3882 | return 1; |
a9aaae37 | 3883 | if (orig_bytes > MAX_MOVE_WORDS * UNITS_PER_WORD) |
34377880 | 3884 | return 0; |
3885 | ||
2cc46ade | 3886 | /* Look for stricter alignment. */ |
2cc46ade | 3887 | tmp = XEXP (orig_dst, 0); |
3888 | if (GET_CODE (tmp) == REG) | |
80909c64 | 3889 | align = MAX (align, REGNO_POINTER_ALIGN (REGNO (tmp))); |
2cc46ade | 3890 | else if (GET_CODE (tmp) == PLUS |
3891 | && GET_CODE (XEXP (tmp, 0)) == REG | |
3892 | && GET_CODE (XEXP (tmp, 1)) == CONST_INT) | |
3893 | { | |
a9aaae37 | 3894 | HOST_WIDE_INT c = INTVAL (XEXP (tmp, 1)); |
3895 | int a = REGNO_POINTER_ALIGN (REGNO (XEXP (tmp, 0))); | |
2cc46ade | 3896 | |
3897 | if (a > align) | |
3898 | { | |
a9aaae37 | 3899 | if (a >= 64) |
3900 | align = a, alignofs = 8 - c % 8; | |
3901 | else if (a >= 32) | |
3902 | align = a, alignofs = 4 - c % 4; | |
3903 | else if (a >= 16) | |
3904 | align = a, alignofs = 2 - c % 2; | |
2cc46ade | 3905 | } |
3906 | } | |
3907 | ||
a9aaae37 | 3908 | /* Handle an unaligned prefix first. */ |
3909 | ||
3910 | if (alignofs > 0) | |
3911 | { | |
3912 | #if HOST_BITS_PER_WIDE_INT >= 64 | |
3913 | /* Given that alignofs is bounded by align, the only time BWX could | |
3914 | generate three stores is for a 7 byte fill. Prefer two individual | |
3915 | stores over a load/mask/store sequence. */ | |
3916 | if ((!TARGET_BWX || alignofs == 7) | |
3917 | && align >= 32 | |
3918 | && !(alignofs == 4 && bytes >= 4)) | |
3919 | { | |
3920 | enum machine_mode mode = (align >= 64 ? DImode : SImode); | |
3921 | int inv_alignofs = (align >= 64 ? 8 : 4) - alignofs; | |
3922 | rtx mem, tmp; | |
3923 | HOST_WIDE_INT mask; | |
3924 | ||
e513d163 | 3925 | mem = adjust_address (orig_dst, mode, ofs - inv_alignofs); |
ab6ab77e | 3926 | set_mem_alias_set (mem, 0); |
a9aaae37 | 3927 | |
3928 | mask = ~(~(HOST_WIDE_INT)0 << (inv_alignofs * 8)); | |
3929 | if (bytes < alignofs) | |
3930 | { | |
3931 | mask |= ~(HOST_WIDE_INT)0 << ((inv_alignofs + bytes) * 8); | |
3932 | ofs += bytes; | |
3933 | bytes = 0; | |
3934 | } | |
3935 | else | |
3936 | { | |
3937 | bytes -= alignofs; | |
3938 | ofs += alignofs; | |
3939 | } | |
3940 | alignofs = 0; | |
3941 | ||
3942 | tmp = expand_binop (mode, and_optab, mem, GEN_INT (mask), | |
3943 | NULL_RTX, 1, OPTAB_WIDEN); | |
3944 | ||
3945 | emit_move_insn (mem, tmp); | |
3946 | } | |
3947 | #endif | |
3948 | ||
3949 | if (TARGET_BWX && (alignofs & 1) && bytes >= 1) | |
3950 | { | |
e513d163 | 3951 | emit_move_insn (adjust_address (orig_dst, QImode, ofs), const0_rtx); |
a9aaae37 | 3952 | bytes -= 1; |
3953 | ofs += 1; | |
3954 | alignofs -= 1; | |
3955 | } | |
3956 | if (TARGET_BWX && align >= 16 && (alignofs & 3) == 2 && bytes >= 2) | |
3957 | { | |
e513d163 | 3958 | emit_move_insn (adjust_address (orig_dst, HImode, ofs), const0_rtx); |
a9aaae37 | 3959 | bytes -= 2; |
3960 | ofs += 2; | |
3961 | alignofs -= 2; | |
3962 | } | |
3963 | if (alignofs == 4 && bytes >= 4) | |
3964 | { | |
e513d163 | 3965 | emit_move_insn (adjust_address (orig_dst, SImode, ofs), const0_rtx); |
a9aaae37 | 3966 | bytes -= 4; |
3967 | ofs += 4; | |
3968 | alignofs = 0; | |
3969 | } | |
3970 | ||
3971 | /* If we've not used the extra lead alignment information by now, | |
3972 | we won't be able to. Downgrade align to match what's left over. */ | |
3973 | if (alignofs > 0) | |
3974 | { | |
3975 | alignofs = alignofs & -alignofs; | |
3976 | align = MIN (align, alignofs * BITS_PER_UNIT); | |
3977 | } | |
3978 | } | |
3979 | ||
3980 | /* Handle a block of contiguous long-words. */ | |
34377880 | 3981 | |
80909c64 | 3982 | if (align >= 64 && bytes >= 8) |
34377880 | 3983 | { |
3984 | words = bytes / 8; | |
3985 | ||
3986 | for (i = 0; i < words; ++i) | |
1f0ce6a6 | 3987 | emit_move_insn (adjust_address (orig_dst, DImode, ofs + i * 8), |
e513d163 | 3988 | const0_rtx); |
34377880 | 3989 | |
3990 | bytes -= words * 8; | |
7597afe9 | 3991 | ofs += words * 8; |
34377880 | 3992 | } |
80909c64 | 3993 | |
a9aaae37 | 3994 | /* If the block is large and appropriately aligned, emit a single |
3995 | store followed by a sequence of stq_u insns. */ | |
3996 | ||
3997 | if (align >= 32 && bytes > 16) | |
3998 | { | |
1f0ce6a6 | 3999 | rtx orig_dsta; |
4000 | ||
e513d163 | 4001 | emit_move_insn (adjust_address (orig_dst, SImode, ofs), const0_rtx); |
a9aaae37 | 4002 | bytes -= 4; |
4003 | ofs += 4; | |
4004 | ||
1f0ce6a6 | 4005 | orig_dsta = XEXP (orig_dst, 0); |
4006 | if (GET_CODE (orig_dsta) == LO_SUM) | |
4007 | orig_dsta = force_reg (Pmode, orig_dsta); | |
4008 | ||
a9aaae37 | 4009 | words = bytes / 8; |
4010 | for (i = 0; i < words; ++i) | |
4011 | { | |
ab6ab77e | 4012 | rtx mem |
4013 | = change_address (orig_dst, DImode, | |
4014 | gen_rtx_AND (DImode, | |
1f0ce6a6 | 4015 | plus_constant (orig_dsta, ofs + i*8), |
ab6ab77e | 4016 | GEN_INT (-8))); |
4017 | set_mem_alias_set (mem, 0); | |
a9aaae37 | 4018 | emit_move_insn (mem, const0_rtx); |
4019 | } | |
4020 | ||
4021 | /* Depending on the alignment, the first stq_u may have overlapped | |
4022 | with the initial stl, which means that the last stq_u didn't | |
4023 | write as much as it would appear. Leave those questionable bytes | |
4024 | unaccounted for. */ | |
4025 | bytes -= words * 8 - 4; | |
4026 | ofs += words * 8 - 4; | |
4027 | } | |
4028 | ||
4029 | /* Handle a smaller block of aligned words. */ | |
4030 | ||
4031 | if ((align >= 64 && bytes == 4) | |
4032 | || (align == 32 && bytes >= 4)) | |
34377880 | 4033 | { |
4034 | words = bytes / 4; | |
4035 | ||
4036 | for (i = 0; i < words; ++i) | |
e513d163 | 4037 | emit_move_insn (adjust_address (orig_dst, SImode, ofs + i * 4), |
80909c64 | 4038 | const0_rtx); |
34377880 | 4039 | |
4040 | bytes -= words * 4; | |
7597afe9 | 4041 | ofs += words * 4; |
34377880 | 4042 | } |
80909c64 | 4043 | |
a9aaae37 | 4044 | /* An unaligned block uses stq_u stores for as many as possible. */ |
4045 | ||
4046 | if (bytes >= 8) | |
34377880 | 4047 | { |
4048 | words = bytes / 8; | |
4049 | ||
7597afe9 | 4050 | alpha_expand_unaligned_store_words (NULL, orig_dst, words, ofs); |
34377880 | 4051 | |
4052 | bytes -= words * 8; | |
7597afe9 | 4053 | ofs += words * 8; |
34377880 | 4054 | } |
4055 | ||
a9aaae37 | 4056 | /* Next clean up any trailing pieces. */ |
34377880 | 4057 | |
a9aaae37 | 4058 | #if HOST_BITS_PER_WIDE_INT >= 64 |
4059 | /* Count the number of bits in BYTES for which aligned stores could | |
4060 | be emitted. */ | |
4061 | words = 0; | |
4062 | for (i = (TARGET_BWX ? 1 : 4); i * BITS_PER_UNIT <= align ; i <<= 1) | |
4063 | if (bytes & i) | |
4064 | words += 1; | |
4065 | ||
4066 | /* If we have appropriate alignment (and it wouldn't take too many | |
4067 | instructions otherwise), mask out the bytes we need. */ | |
4068 | if (TARGET_BWX ? words > 2 : bytes > 0) | |
4069 | { | |
4070 | if (align >= 64) | |
4071 | { | |
4072 | rtx mem, tmp; | |
4073 | HOST_WIDE_INT mask; | |
4074 | ||
e513d163 | 4075 | mem = adjust_address (orig_dst, DImode, ofs); |
ab6ab77e | 4076 | set_mem_alias_set (mem, 0); |
a9aaae37 | 4077 | |
4078 | mask = ~(HOST_WIDE_INT)0 << (bytes * 8); | |
4079 | ||
4080 | tmp = expand_binop (DImode, and_optab, mem, GEN_INT (mask), | |
4081 | NULL_RTX, 1, OPTAB_WIDEN); | |
4082 | ||
4083 | emit_move_insn (mem, tmp); | |
4084 | return 1; | |
4085 | } | |
4086 | else if (align >= 32 && bytes < 4) | |
4087 | { | |
4088 | rtx mem, tmp; | |
4089 | HOST_WIDE_INT mask; | |
4090 | ||
e513d163 | 4091 | mem = adjust_address (orig_dst, SImode, ofs); |
ab6ab77e | 4092 | set_mem_alias_set (mem, 0); |
a9aaae37 | 4093 | |
4094 | mask = ~(HOST_WIDE_INT)0 << (bytes * 8); | |
4095 | ||
4096 | tmp = expand_binop (SImode, and_optab, mem, GEN_INT (mask), | |
4097 | NULL_RTX, 1, OPTAB_WIDEN); | |
4098 | ||
4099 | emit_move_insn (mem, tmp); | |
4100 | return 1; | |
4101 | } | |
34377880 | 4102 | } |
a9aaae37 | 4103 | #endif |
80909c64 | 4104 | |
34377880 | 4105 | if (!TARGET_BWX && bytes >= 4) |
4106 | { | |
4107 | alpha_expand_unaligned_store (orig_dst, const0_rtx, 4, ofs); | |
4108 | bytes -= 4; | |
4109 | ofs += 4; | |
4110 | } | |
80909c64 | 4111 | |
34377880 | 4112 | if (bytes >= 2) |
4113 | { | |
80909c64 | 4114 | if (align >= 16) |
34377880 | 4115 | { |
4116 | do { | |
e513d163 | 4117 | emit_move_insn (adjust_address (orig_dst, HImode, ofs), |
34377880 | 4118 | const0_rtx); |
4119 | bytes -= 2; | |
4120 | ofs += 2; | |
4121 | } while (bytes >= 2); | |
4122 | } | |
80909c64 | 4123 | else if (! TARGET_BWX) |
34377880 | 4124 | { |
4125 | alpha_expand_unaligned_store (orig_dst, const0_rtx, 2, ofs); | |
4126 | bytes -= 2; | |
4127 | ofs += 2; | |
4128 | } | |
4129 | } | |
80909c64 | 4130 | |
34377880 | 4131 | while (bytes > 0) |
4132 | { | |
e513d163 | 4133 | emit_move_insn (adjust_address (orig_dst, QImode, ofs), const0_rtx); |
34377880 | 4134 | bytes -= 1; |
4135 | ofs += 1; | |
4136 | } | |
4137 | ||
4138 | return 1; | |
4139 | } | |
f2cc13dc | 4140 | |
4141 | /* Returns a mask so that zap(x, value) == x & mask. */ | |
4142 | ||
4143 | rtx | |
92643d95 | 4144 | alpha_expand_zap_mask (HOST_WIDE_INT value) |
f2cc13dc | 4145 | { |
4146 | rtx result; | |
4147 | int i; | |
4148 | ||
4149 | if (HOST_BITS_PER_WIDE_INT >= 64) | |
4150 | { | |
4151 | HOST_WIDE_INT mask = 0; | |
4152 | ||
4153 | for (i = 7; i >= 0; --i) | |
4154 | { | |
4155 | mask <<= 8; | |
4156 | if (!((value >> i) & 1)) | |
4157 | mask |= 0xff; | |
4158 | } | |
4159 | ||
4160 | result = gen_int_mode (mask, DImode); | |
4161 | } | |
4162 | else if (HOST_BITS_PER_WIDE_INT == 32) | |
4163 | { | |
4164 | HOST_WIDE_INT mask_lo = 0, mask_hi = 0; | |
4165 | ||
4166 | for (i = 7; i >= 4; --i) | |
4167 | { | |
4168 | mask_hi <<= 8; | |
4169 | if (!((value >> i) & 1)) | |
4170 | mask_hi |= 0xff; | |
4171 | } | |
4172 | ||
4173 | for (i = 3; i >= 0; --i) | |
4174 | { | |
4175 | mask_lo <<= 8; | |
4176 | if (!((value >> i) & 1)) | |
4177 | mask_lo |= 0xff; | |
4178 | } | |
4179 | ||
4180 | result = immed_double_const (mask_lo, mask_hi, DImode); | |
4181 | } | |
4182 | else | |
4183 | abort (); | |
4184 | ||
4185 | return result; | |
4186 | } | |
4187 | ||
4188 | void | |
92643d95 | 4189 | alpha_expand_builtin_vector_binop (rtx (*gen) (rtx, rtx, rtx), |
4190 | enum machine_mode mode, | |
4191 | rtx op0, rtx op1, rtx op2) | |
f2cc13dc | 4192 | { |
4193 | op0 = gen_lowpart (mode, op0); | |
4194 | ||
4195 | if (op1 == const0_rtx) | |
4196 | op1 = CONST0_RTX (mode); | |
4197 | else | |
4198 | op1 = gen_lowpart (mode, op1); | |
ae4cd3a5 | 4199 | |
4200 | if (op2 == const0_rtx) | |
f2cc13dc | 4201 | op2 = CONST0_RTX (mode); |
4202 | else | |
4203 | op2 = gen_lowpart (mode, op2); | |
4204 | ||
4205 | emit_insn ((*gen) (op0, op1, op2)); | |
4206 | } | |
bf2a98b3 | 4207 | \f |
4208 | /* Adjust the cost of a scheduling dependency. Return the new cost of | |
4209 | a dependency LINK or INSN on DEP_INSN. COST is the current cost. */ | |
4210 | ||
747af5e7 | 4211 | static int |
92643d95 | 4212 | alpha_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost) |
bf2a98b3 | 4213 | { |
d2832bd8 | 4214 | enum attr_type insn_type, dep_insn_type; |
bf2a98b3 | 4215 | |
4216 | /* If the dependence is an anti-dependence, there is no cost. For an | |
4217 | output dependence, there is sometimes a cost, but it doesn't seem | |
4218 | worth handling those few cases. */ | |
bf2a98b3 | 4219 | if (REG_NOTE_KIND (link) != 0) |
7eb0c947 | 4220 | return cost; |
bf2a98b3 | 4221 | |
d2832bd8 | 4222 | /* If we can't recognize the insns, we can't really do anything. */ |
4223 | if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0) | |
4224 | return cost; | |
4225 | ||
4226 | insn_type = get_attr_type (insn); | |
4227 | dep_insn_type = get_attr_type (dep_insn); | |
4228 | ||
07c1a295 | 4229 | /* Bring in the user-defined memory latency. */ |
e7a69d05 | 4230 | if (dep_insn_type == TYPE_ILD |
4231 | || dep_insn_type == TYPE_FLD | |
4232 | || dep_insn_type == TYPE_LDSYM) | |
07c1a295 | 4233 | cost += alpha_memory_latency-1; |
4234 | ||
7eb0c947 | 4235 | /* Everything else handled in DFA bypasses now. */ |
3680ac41 | 4236 | |
bf2a98b3 | 4237 | return cost; |
4238 | } | |
747af5e7 | 4239 | |
7eb0c947 | 4240 | /* The number of instructions that can be issued per cycle. */ |
4241 | ||
747af5e7 | 4242 | static int |
92643d95 | 4243 | alpha_issue_rate (void) |
747af5e7 | 4244 | { |
4245 | return (alpha_cpu == PROCESSOR_EV4 ? 2 : 4); | |
4246 | } | |
4247 | ||
7eb0c947 | 4248 | /* How many alternative schedules to try. This should be as wide as the |
4249 | scheduling freedom in the DFA, but no wider. Making this value too | |
4250 | large results extra work for the scheduler. | |
4251 | ||
4252 | For EV4, loads can be issued to either IB0 or IB1, thus we have 2 | |
4253 | alternative schedules. For EV5, we can choose between E0/E1 and | |
8d232dc7 | 4254 | FA/FM. For EV6, an arithmetic insn can be issued to U0/U1/L0/L1. */ |
7eb0c947 | 4255 | |
4256 | static int | |
92643d95 | 4257 | alpha_multipass_dfa_lookahead (void) |
7eb0c947 | 4258 | { |
4259 | return (alpha_cpu == PROCESSOR_EV6 ? 4 : 2); | |
4260 | } | |
0c0464e6 | 4261 | \f |
5f7b9df8 | 4262 | /* Machine-specific function data. */ |
4263 | ||
1f3233d1 | 4264 | struct machine_function GTY(()) |
5f7b9df8 | 4265 | { |
674a8f0b | 4266 | /* For unicosmk. */ |
5f7b9df8 | 4267 | /* List of call information words for calls from this function. */ |
4268 | struct rtx_def *first_ciw; | |
4269 | struct rtx_def *last_ciw; | |
4270 | int ciw_count; | |
4271 | ||
4272 | /* List of deferred case vectors. */ | |
4273 | struct rtx_def *addr_list; | |
1f3233d1 | 4274 | |
674a8f0b | 4275 | /* For OSF. */ |
5f7b9df8 | 4276 | const char *some_ld_name; |
a221313c | 4277 | |
4278 | /* For TARGET_LD_BUGGY_LDGP. */ | |
4279 | struct rtx_def *gp_save_rtx; | |
5f7b9df8 | 4280 | }; |
4281 | ||
1f3233d1 | 4282 | /* How to allocate a 'struct machine_function'. */ |
9caef960 | 4283 | |
1f3233d1 | 4284 | static struct machine_function * |
92643d95 | 4285 | alpha_init_machine_status (void) |
9caef960 | 4286 | { |
9e7454d0 | 4287 | return ((struct machine_function *) |
1f3233d1 | 4288 | ggc_alloc_cleared (sizeof (struct machine_function))); |
9caef960 | 4289 | } |
9caef960 | 4290 | |
0c0464e6 | 4291 | /* Functions to save and restore alpha_return_addr_rtx. */ |
4292 | ||
0c0464e6 | 4293 | /* Start the ball rolling with RETURN_ADDR_RTX. */ |
4294 | ||
4295 | rtx | |
92643d95 | 4296 | alpha_return_addr (int count, rtx frame ATTRIBUTE_UNUSED) |
0c0464e6 | 4297 | { |
0c0464e6 | 4298 | if (count != 0) |
4299 | return const0_rtx; | |
4300 | ||
0f37b7a2 | 4301 | return get_hard_reg_initial_val (Pmode, REG_RA); |
0c0464e6 | 4302 | } |
4303 | ||
a221313c | 4304 | /* Return or create a memory slot containing the gp value for the current |
66561750 | 4305 | function. Needed only if TARGET_LD_BUGGY_LDGP. */ |
4306 | ||
4307 | rtx | |
92643d95 | 4308 | alpha_gp_save_rtx (void) |
66561750 | 4309 | { |
a221313c | 4310 | rtx seq, m = cfun->machine->gp_save_rtx; |
4311 | ||
4312 | if (m == NULL) | |
4313 | { | |
4314 | start_sequence (); | |
4315 | ||
4316 | m = assign_stack_local (DImode, UNITS_PER_WORD, BITS_PER_WORD); | |
4317 | m = validize_mem (m); | |
4318 | emit_move_insn (m, pic_offset_table_rtx); | |
4319 | ||
4320 | seq = get_insns (); | |
4321 | end_sequence (); | |
4322 | emit_insn_after (seq, entry_of_function ()); | |
4323 | ||
4324 | cfun->machine->gp_save_rtx = m; | |
4325 | } | |
4326 | ||
4327 | return m; | |
66561750 | 4328 | } |
4329 | ||
0c0464e6 | 4330 | static int |
92643d95 | 4331 | alpha_ra_ever_killed (void) |
0c0464e6 | 4332 | { |
5a965225 | 4333 | rtx top; |
4334 | ||
0f37b7a2 | 4335 | if (!has_hard_reg_initial_val (Pmode, REG_RA)) |
0c0464e6 | 4336 | return regs_ever_live[REG_RA]; |
4337 | ||
5a965225 | 4338 | push_topmost_sequence (); |
4339 | top = get_insns (); | |
4340 | pop_topmost_sequence (); | |
4341 | ||
4342 | return reg_set_between_p (gen_rtx_REG (Pmode, REG_RA), top, NULL_RTX); | |
0c0464e6 | 4343 | } |
4344 | ||
bf2a98b3 | 4345 | \f |
6fec94c5 | 4346 | /* Return the trap mode suffix applicable to the current |
65abff06 | 4347 | instruction, or NULL. */ |
bf2a98b3 | 4348 | |
6fec94c5 | 4349 | static const char * |
92643d95 | 4350 | get_trap_mode_suffix (void) |
bf2a98b3 | 4351 | { |
6fec94c5 | 4352 | enum attr_trap_suffix s = get_attr_trap_suffix (current_output_insn); |
bf2a98b3 | 4353 | |
6fec94c5 | 4354 | switch (s) |
bf2a98b3 | 4355 | { |
6fec94c5 | 4356 | case TRAP_SUFFIX_NONE: |
4357 | return NULL; | |
c4622276 | 4358 | |
6fec94c5 | 4359 | case TRAP_SUFFIX_SU: |
bc16f0c1 | 4360 | if (alpha_fptm >= ALPHA_FPTM_SU) |
6fec94c5 | 4361 | return "su"; |
4362 | return NULL; | |
c4622276 | 4363 | |
6fec94c5 | 4364 | case TRAP_SUFFIX_SUI: |
4365 | if (alpha_fptm >= ALPHA_FPTM_SUI) | |
4366 | return "sui"; | |
4367 | return NULL; | |
4368 | ||
4369 | case TRAP_SUFFIX_V_SV: | |
39344852 | 4370 | switch (alpha_fptm) |
4371 | { | |
4372 | case ALPHA_FPTM_N: | |
6fec94c5 | 4373 | return NULL; |
39344852 | 4374 | case ALPHA_FPTM_U: |
6fec94c5 | 4375 | return "v"; |
39344852 | 4376 | case ALPHA_FPTM_SU: |
4377 | case ALPHA_FPTM_SUI: | |
6fec94c5 | 4378 | return "sv"; |
39344852 | 4379 | } |
4380 | break; | |
4381 | ||
6fec94c5 | 4382 | case TRAP_SUFFIX_V_SV_SVI: |
b5ea3193 | 4383 | switch (alpha_fptm) |
4384 | { | |
4385 | case ALPHA_FPTM_N: | |
6fec94c5 | 4386 | return NULL; |
b5ea3193 | 4387 | case ALPHA_FPTM_U: |
6fec94c5 | 4388 | return "v"; |
b5ea3193 | 4389 | case ALPHA_FPTM_SU: |
6fec94c5 | 4390 | return "sv"; |
b5ea3193 | 4391 | case ALPHA_FPTM_SUI: |
6fec94c5 | 4392 | return "svi"; |
b5ea3193 | 4393 | } |
4394 | break; | |
4395 | ||
6fec94c5 | 4396 | case TRAP_SUFFIX_U_SU_SUI: |
c4622276 | 4397 | switch (alpha_fptm) |
4398 | { | |
4399 | case ALPHA_FPTM_N: | |
6fec94c5 | 4400 | return NULL; |
c4622276 | 4401 | case ALPHA_FPTM_U: |
6fec94c5 | 4402 | return "u"; |
c4622276 | 4403 | case ALPHA_FPTM_SU: |
6fec94c5 | 4404 | return "su"; |
c4622276 | 4405 | case ALPHA_FPTM_SUI: |
6fec94c5 | 4406 | return "sui"; |
c4622276 | 4407 | } |
4408 | break; | |
6fec94c5 | 4409 | } |
4410 | abort (); | |
4411 | } | |
c4622276 | 4412 | |
6fec94c5 | 4413 | /* Return the rounding mode suffix applicable to the current |
65abff06 | 4414 | instruction, or NULL. */ |
6fec94c5 | 4415 | |
4416 | static const char * | |
92643d95 | 4417 | get_round_mode_suffix (void) |
6fec94c5 | 4418 | { |
4419 | enum attr_round_suffix s = get_attr_round_suffix (current_output_insn); | |
4420 | ||
4421 | switch (s) | |
4422 | { | |
4423 | case ROUND_SUFFIX_NONE: | |
4424 | return NULL; | |
4425 | case ROUND_SUFFIX_NORMAL: | |
4426 | switch (alpha_fprm) | |
c4622276 | 4427 | { |
6fec94c5 | 4428 | case ALPHA_FPRM_NORM: |
4429 | return NULL; | |
9e7454d0 | 4430 | case ALPHA_FPRM_MINF: |
6fec94c5 | 4431 | return "m"; |
4432 | case ALPHA_FPRM_CHOP: | |
4433 | return "c"; | |
4434 | case ALPHA_FPRM_DYN: | |
4435 | return "d"; | |
c4622276 | 4436 | } |
4437 | break; | |
4438 | ||
6fec94c5 | 4439 | case ROUND_SUFFIX_C: |
4440 | return "c"; | |
4441 | } | |
4442 | abort (); | |
4443 | } | |
4444 | ||
5f7b9df8 | 4445 | /* Locate some local-dynamic symbol still in use by this function |
4446 | so that we can print its name in some movdi_er_tlsldm pattern. */ | |
4447 | ||
92643d95 | 4448 | static int |
4449 | get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED) | |
4450 | { | |
4451 | rtx x = *px; | |
4452 | ||
4453 | if (GET_CODE (x) == SYMBOL_REF | |
4454 | && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC) | |
4455 | { | |
4456 | cfun->machine->some_ld_name = XSTR (x, 0); | |
4457 | return 1; | |
4458 | } | |
4459 | ||
4460 | return 0; | |
4461 | } | |
4462 | ||
5f7b9df8 | 4463 | static const char * |
92643d95 | 4464 | get_some_local_dynamic_name (void) |
5f7b9df8 | 4465 | { |
4466 | rtx insn; | |
4467 | ||
4468 | if (cfun->machine->some_ld_name) | |
4469 | return cfun->machine->some_ld_name; | |
4470 | ||
4471 | for (insn = get_insns (); insn ; insn = NEXT_INSN (insn)) | |
4472 | if (INSN_P (insn) | |
4473 | && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0)) | |
4474 | return cfun->machine->some_ld_name; | |
4475 | ||
4476 | abort (); | |
4477 | } | |
4478 | ||
6fec94c5 | 4479 | /* Print an operand. Recognize special options, documented below. */ |
4480 | ||
4481 | void | |
92643d95 | 4482 | print_operand (FILE *file, rtx x, int code) |
6fec94c5 | 4483 | { |
4484 | int i; | |
4485 | ||
4486 | switch (code) | |
4487 | { | |
4488 | case '~': | |
4489 | /* Print the assembler name of the current function. */ | |
4490 | assemble_name (file, alpha_fnname); | |
4491 | break; | |
4492 | ||
5f7b9df8 | 4493 | case '&': |
4494 | assemble_name (file, get_some_local_dynamic_name ()); | |
4495 | break; | |
4496 | ||
6fec94c5 | 4497 | case '/': |
4498 | { | |
4499 | const char *trap = get_trap_mode_suffix (); | |
4500 | const char *round = get_round_mode_suffix (); | |
4501 | ||
4502 | if (trap || round) | |
9caef960 | 4503 | fprintf (file, (TARGET_AS_SLASH_BEFORE_SUFFIX ? "/%s%s" : "%s%s"), |
4504 | (trap ? trap : ""), (round ? round : "")); | |
6fec94c5 | 4505 | break; |
4506 | } | |
4507 | ||
8df4a58b | 4508 | case ',': |
4509 | /* Generates single precision instruction suffix. */ | |
6fec94c5 | 4510 | fputc ((TARGET_FLOAT_VAX ? 'f' : 's'), file); |
8df4a58b | 4511 | break; |
4512 | ||
4513 | case '-': | |
4514 | /* Generates double precision instruction suffix. */ | |
6fec94c5 | 4515 | fputc ((TARGET_FLOAT_VAX ? 'g' : 't'), file); |
8df4a58b | 4516 | break; |
4517 | ||
822c7fc8 | 4518 | case '+': |
4519 | /* Generates a nop after a noreturn call at the very end of the | |
4520 | function. */ | |
4521 | if (next_real_insn (current_output_insn) == 0) | |
4522 | fprintf (file, "\n\tnop"); | |
4523 | break; | |
4524 | ||
1f0ce6a6 | 4525 | case '#': |
4526 | if (alpha_this_literal_sequence_number == 0) | |
4527 | alpha_this_literal_sequence_number = alpha_next_sequence_number++; | |
4528 | fprintf (file, "%d", alpha_this_literal_sequence_number); | |
4529 | break; | |
4530 | ||
4531 | case '*': | |
4532 | if (alpha_this_gpdisp_sequence_number == 0) | |
4533 | alpha_this_gpdisp_sequence_number = alpha_next_sequence_number++; | |
4534 | fprintf (file, "%d", alpha_this_gpdisp_sequence_number); | |
4535 | break; | |
4536 | ||
4537 | case 'H': | |
4538 | if (GET_CODE (x) == HIGH) | |
5dcb037d | 4539 | output_addr_const (file, XEXP (x, 0)); |
1f0ce6a6 | 4540 | else |
4541 | output_operand_lossage ("invalid %%H value"); | |
4542 | break; | |
4543 | ||
ad2ed779 | 4544 | case 'J': |
5f7b9df8 | 4545 | { |
4546 | const char *lituse; | |
4547 | ||
4548 | if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSGD_CALL) | |
4549 | { | |
4550 | x = XVECEXP (x, 0, 0); | |
4551 | lituse = "lituse_tlsgd"; | |
4552 | } | |
4553 | else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSLDM_CALL) | |
4554 | { | |
4555 | x = XVECEXP (x, 0, 0); | |
4556 | lituse = "lituse_tlsldm"; | |
4557 | } | |
4558 | else if (GET_CODE (x) == CONST_INT) | |
4559 | lituse = "lituse_jsr"; | |
4560 | else | |
4561 | { | |
4562 | output_operand_lossage ("invalid %%J value"); | |
4563 | break; | |
4564 | } | |
4565 | ||
4566 | if (x != const0_rtx) | |
4567 | fprintf (file, "\t\t!%s!%d", lituse, (int) INTVAL (x)); | |
4568 | } | |
ad2ed779 | 4569 | break; |
4570 | ||
bf2a98b3 | 4571 | case 'r': |
4572 | /* If this operand is the constant zero, write it as "$31". */ | |
4573 | if (GET_CODE (x) == REG) | |
4574 | fprintf (file, "%s", reg_names[REGNO (x)]); | |
4575 | else if (x == CONST0_RTX (GET_MODE (x))) | |
4576 | fprintf (file, "$31"); | |
4577 | else | |
4578 | output_operand_lossage ("invalid %%r value"); | |
bf2a98b3 | 4579 | break; |
4580 | ||
4581 | case 'R': | |
4582 | /* Similar, but for floating-point. */ | |
4583 | if (GET_CODE (x) == REG) | |
4584 | fprintf (file, "%s", reg_names[REGNO (x)]); | |
4585 | else if (x == CONST0_RTX (GET_MODE (x))) | |
4586 | fprintf (file, "$f31"); | |
4587 | else | |
4588 | output_operand_lossage ("invalid %%R value"); | |
bf2a98b3 | 4589 | break; |
4590 | ||
4591 | case 'N': | |
4592 | /* Write the 1's complement of a constant. */ | |
4593 | if (GET_CODE (x) != CONST_INT) | |
4594 | output_operand_lossage ("invalid %%N value"); | |
4595 | ||
61a63ca5 | 4596 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INTVAL (x)); |
bf2a98b3 | 4597 | break; |
4598 | ||
4599 | case 'P': | |
4600 | /* Write 1 << C, for a constant C. */ | |
4601 | if (GET_CODE (x) != CONST_INT) | |
4602 | output_operand_lossage ("invalid %%P value"); | |
4603 | ||
61a63ca5 | 4604 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, (HOST_WIDE_INT) 1 << INTVAL (x)); |
bf2a98b3 | 4605 | break; |
4606 | ||
4607 | case 'h': | |
4608 | /* Write the high-order 16 bits of a constant, sign-extended. */ | |
4609 | if (GET_CODE (x) != CONST_INT) | |
4610 | output_operand_lossage ("invalid %%h value"); | |
4611 | ||
61a63ca5 | 4612 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) >> 16); |
bf2a98b3 | 4613 | break; |
4614 | ||
4615 | case 'L': | |
4616 | /* Write the low-order 16 bits of a constant, sign-extended. */ | |
4617 | if (GET_CODE (x) != CONST_INT) | |
4618 | output_operand_lossage ("invalid %%L value"); | |
4619 | ||
61a63ca5 | 4620 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, |
4621 | (INTVAL (x) & 0xffff) - 2 * (INTVAL (x) & 0x8000)); | |
bf2a98b3 | 4622 | break; |
4623 | ||
4624 | case 'm': | |
4625 | /* Write mask for ZAP insn. */ | |
4626 | if (GET_CODE (x) == CONST_DOUBLE) | |
4627 | { | |
4628 | HOST_WIDE_INT mask = 0; | |
4629 | HOST_WIDE_INT value; | |
4630 | ||
4631 | value = CONST_DOUBLE_LOW (x); | |
4632 | for (i = 0; i < HOST_BITS_PER_WIDE_INT / HOST_BITS_PER_CHAR; | |
4633 | i++, value >>= 8) | |
4634 | if (value & 0xff) | |
4635 | mask |= (1 << i); | |
4636 | ||
4637 | value = CONST_DOUBLE_HIGH (x); | |
4638 | for (i = 0; i < HOST_BITS_PER_WIDE_INT / HOST_BITS_PER_CHAR; | |
4639 | i++, value >>= 8) | |
4640 | if (value & 0xff) | |
4641 | mask |= (1 << (i + sizeof (int))); | |
4642 | ||
61a63ca5 | 4643 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, mask & 0xff); |
bf2a98b3 | 4644 | } |
4645 | ||
4646 | else if (GET_CODE (x) == CONST_INT) | |
4647 | { | |
4648 | HOST_WIDE_INT mask = 0, value = INTVAL (x); | |
4649 | ||
4650 | for (i = 0; i < 8; i++, value >>= 8) | |
4651 | if (value & 0xff) | |
4652 | mask |= (1 << i); | |
4653 | ||
61a63ca5 | 4654 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, mask); |
bf2a98b3 | 4655 | } |
4656 | else | |
4657 | output_operand_lossage ("invalid %%m value"); | |
4658 | break; | |
4659 | ||
4660 | case 'M': | |
34377880 | 4661 | /* 'b', 'w', 'l', or 'q' as the value of the constant. */ |
bf2a98b3 | 4662 | if (GET_CODE (x) != CONST_INT |
34377880 | 4663 | || (INTVAL (x) != 8 && INTVAL (x) != 16 |
4664 | && INTVAL (x) != 32 && INTVAL (x) != 64)) | |
bf2a98b3 | 4665 | output_operand_lossage ("invalid %%M value"); |
4666 | ||
4667 | fprintf (file, "%s", | |
34377880 | 4668 | (INTVAL (x) == 8 ? "b" |
4669 | : INTVAL (x) == 16 ? "w" | |
4670 | : INTVAL (x) == 32 ? "l" | |
4671 | : "q")); | |
bf2a98b3 | 4672 | break; |
4673 | ||
4674 | case 'U': | |
4675 | /* Similar, except do it from the mask. */ | |
ae4cd3a5 | 4676 | if (GET_CODE (x) == CONST_INT) |
4677 | { | |
4678 | HOST_WIDE_INT value = INTVAL (x); | |
4679 | ||
4680 | if (value == 0xff) | |
4681 | { | |
4682 | fputc ('b', file); | |
4683 | break; | |
4684 | } | |
4685 | if (value == 0xffff) | |
4686 | { | |
4687 | fputc ('w', file); | |
4688 | break; | |
4689 | } | |
4690 | if (value == 0xffffffff) | |
4691 | { | |
4692 | fputc ('l', file); | |
4693 | break; | |
4694 | } | |
4695 | if (value == -1) | |
4696 | { | |
4697 | fputc ('q', file); | |
4698 | break; | |
4699 | } | |
4700 | } | |
4701 | else if (HOST_BITS_PER_WIDE_INT == 32 | |
4702 | && GET_CODE (x) == CONST_DOUBLE | |
4703 | && CONST_DOUBLE_LOW (x) == 0xffffffff | |
4704 | && CONST_DOUBLE_HIGH (x) == 0) | |
4705 | { | |
4706 | fputc ('l', file); | |
4707 | break; | |
4708 | } | |
4709 | output_operand_lossage ("invalid %%U value"); | |
bf2a98b3 | 4710 | break; |
4711 | ||
4712 | case 's': | |
9caef960 | 4713 | /* Write the constant value divided by 8 for little-endian mode or |
4714 | (56 - value) / 8 for big-endian mode. */ | |
4715 | ||
bf2a98b3 | 4716 | if (GET_CODE (x) != CONST_INT |
9caef960 | 4717 | || (unsigned HOST_WIDE_INT) INTVAL (x) >= (WORDS_BIG_ENDIAN |
4718 | ? 56 | |
9e7454d0 | 4719 | : 64) |
9caef960 | 4720 | || (INTVAL (x) & 7) != 0) |
bf2a98b3 | 4721 | output_operand_lossage ("invalid %%s value"); |
4722 | ||
9caef960 | 4723 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, |
4724 | WORDS_BIG_ENDIAN | |
4725 | ? (56 - INTVAL (x)) / 8 | |
4726 | : INTVAL (x) / 8); | |
bf2a98b3 | 4727 | break; |
4728 | ||
4729 | case 'S': | |
4730 | /* Same, except compute (64 - c) / 8 */ | |
4731 | ||
4732 | if (GET_CODE (x) != CONST_INT | |
4733 | && (unsigned HOST_WIDE_INT) INTVAL (x) >= 64 | |
4734 | && (INTVAL (x) & 7) != 8) | |
4735 | output_operand_lossage ("invalid %%s value"); | |
4736 | ||
61a63ca5 | 4737 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, (64 - INTVAL (x)) / 8); |
bf2a98b3 | 4738 | break; |
4739 | ||
9caef960 | 4740 | case 't': |
4741 | { | |
4742 | /* On Unicos/Mk systems: use a DEX expression if the symbol | |
4743 | clashes with a register name. */ | |
4744 | int dex = unicosmk_need_dex (x); | |
4745 | if (dex) | |
4746 | fprintf (file, "DEX(%d)", dex); | |
4747 | else | |
4748 | output_addr_const (file, x); | |
4749 | } | |
4750 | break; | |
4751 | ||
62dc3582 | 4752 | case 'C': case 'D': case 'c': case 'd': |
bf2a98b3 | 4753 | /* Write out comparison name. */ |
62dc3582 | 4754 | { |
4755 | enum rtx_code c = GET_CODE (x); | |
4756 | ||
6720e96c | 4757 | if (!COMPARISON_P (x)) |
62dc3582 | 4758 | output_operand_lossage ("invalid %%C value"); |
4759 | ||
f3d263a7 | 4760 | else if (code == 'D') |
62dc3582 | 4761 | c = reverse_condition (c); |
4762 | else if (code == 'c') | |
4763 | c = swap_condition (c); | |
4764 | else if (code == 'd') | |
4765 | c = swap_condition (reverse_condition (c)); | |
4766 | ||
4767 | if (c == LEU) | |
4768 | fprintf (file, "ule"); | |
4769 | else if (c == LTU) | |
4770 | fprintf (file, "ult"); | |
a4110d9a | 4771 | else if (c == UNORDERED) |
4772 | fprintf (file, "un"); | |
62dc3582 | 4773 | else |
4774 | fprintf (file, "%s", GET_RTX_NAME (c)); | |
4775 | } | |
8ad50a44 | 4776 | break; |
4777 | ||
bf2a98b3 | 4778 | case 'E': |
4779 | /* Write the divide or modulus operator. */ | |
4780 | switch (GET_CODE (x)) | |
4781 | { | |
4782 | case DIV: | |
4783 | fprintf (file, "div%s", GET_MODE (x) == SImode ? "l" : "q"); | |
4784 | break; | |
4785 | case UDIV: | |
4786 | fprintf (file, "div%su", GET_MODE (x) == SImode ? "l" : "q"); | |
4787 | break; | |
4788 | case MOD: | |
4789 | fprintf (file, "rem%s", GET_MODE (x) == SImode ? "l" : "q"); | |
4790 | break; | |
4791 | case UMOD: | |
4792 | fprintf (file, "rem%su", GET_MODE (x) == SImode ? "l" : "q"); | |
4793 | break; | |
4794 | default: | |
4795 | output_operand_lossage ("invalid %%E value"); | |
4796 | break; | |
4797 | } | |
4798 | break; | |
4799 | ||
bf2a98b3 | 4800 | case 'A': |
4801 | /* Write "_u" for unaligned access. */ | |
4802 | if (GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) == AND) | |
4803 | fprintf (file, "_u"); | |
4804 | break; | |
4805 | ||
4806 | case 0: | |
4807 | if (GET_CODE (x) == REG) | |
4808 | fprintf (file, "%s", reg_names[REGNO (x)]); | |
4809 | else if (GET_CODE (x) == MEM) | |
4810 | output_address (XEXP (x, 0)); | |
5f7b9df8 | 4811 | else if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == UNSPEC) |
4812 | { | |
4813 | switch (XINT (XEXP (x, 0), 1)) | |
4814 | { | |
4815 | case UNSPEC_DTPREL: | |
4816 | case UNSPEC_TPREL: | |
4817 | output_addr_const (file, XVECEXP (XEXP (x, 0), 0, 0)); | |
4818 | break; | |
4819 | default: | |
4820 | output_operand_lossage ("unknown relocation unspec"); | |
4821 | break; | |
4822 | } | |
4823 | } | |
bf2a98b3 | 4824 | else |
4825 | output_addr_const (file, x); | |
4826 | break; | |
4827 | ||
4828 | default: | |
4829 | output_operand_lossage ("invalid %%xn code"); | |
4830 | } | |
4831 | } | |
6e0fe99e | 4832 | |
4833 | void | |
92643d95 | 4834 | print_operand_address (FILE *file, rtx addr) |
6e0fe99e | 4835 | { |
a3e39a24 | 4836 | int basereg = 31; |
6e0fe99e | 4837 | HOST_WIDE_INT offset = 0; |
4838 | ||
4839 | if (GET_CODE (addr) == AND) | |
4840 | addr = XEXP (addr, 0); | |
6e0fe99e | 4841 | |
a3e39a24 | 4842 | if (GET_CODE (addr) == PLUS |
4843 | && GET_CODE (XEXP (addr, 1)) == CONST_INT) | |
6e0fe99e | 4844 | { |
4845 | offset = INTVAL (XEXP (addr, 1)); | |
a3e39a24 | 4846 | addr = XEXP (addr, 0); |
6e0fe99e | 4847 | } |
1f0ce6a6 | 4848 | |
4849 | if (GET_CODE (addr) == LO_SUM) | |
4850 | { | |
5f7b9df8 | 4851 | const char *reloc16, *reloclo; |
4852 | rtx op1 = XEXP (addr, 1); | |
4853 | ||
4854 | if (GET_CODE (op1) == CONST && GET_CODE (XEXP (op1, 0)) == UNSPEC) | |
4855 | { | |
4856 | op1 = XEXP (op1, 0); | |
4857 | switch (XINT (op1, 1)) | |
4858 | { | |
4859 | case UNSPEC_DTPREL: | |
4860 | reloc16 = NULL; | |
4861 | reloclo = (alpha_tls_size == 16 ? "dtprel" : "dtprello"); | |
4862 | break; | |
4863 | case UNSPEC_TPREL: | |
4864 | reloc16 = NULL; | |
4865 | reloclo = (alpha_tls_size == 16 ? "tprel" : "tprello"); | |
4866 | break; | |
4867 | default: | |
4868 | output_operand_lossage ("unknown relocation unspec"); | |
4869 | return; | |
4870 | } | |
4871 | ||
4872 | output_addr_const (file, XVECEXP (op1, 0, 0)); | |
4873 | } | |
4874 | else | |
4875 | { | |
4876 | reloc16 = "gprel"; | |
4877 | reloclo = "gprellow"; | |
4878 | output_addr_const (file, op1); | |
4879 | } | |
4880 | ||
1f0ce6a6 | 4881 | if (offset) |
4840a03a | 4882 | fprintf (file, "+" HOST_WIDE_INT_PRINT_DEC, offset); |
9e7454d0 | 4883 | |
1f0ce6a6 | 4884 | addr = XEXP (addr, 0); |
4885 | if (GET_CODE (addr) == REG) | |
4886 | basereg = REGNO (addr); | |
4887 | else if (GET_CODE (addr) == SUBREG | |
4888 | && GET_CODE (SUBREG_REG (addr)) == REG) | |
4889 | basereg = subreg_regno (addr); | |
4890 | else | |
4891 | abort (); | |
5dcb037d | 4892 | |
4893 | fprintf (file, "($%d)\t\t!%s", basereg, | |
5f7b9df8 | 4894 | (basereg == 29 ? reloc16 : reloclo)); |
1f0ce6a6 | 4895 | return; |
4896 | } | |
4897 | ||
a3e39a24 | 4898 | if (GET_CODE (addr) == REG) |
4899 | basereg = REGNO (addr); | |
4900 | else if (GET_CODE (addr) == SUBREG | |
4901 | && GET_CODE (SUBREG_REG (addr)) == REG) | |
1f0ce6a6 | 4902 | basereg = subreg_regno (addr); |
a3e39a24 | 4903 | else if (GET_CODE (addr) == CONST_INT) |
4904 | offset = INTVAL (addr); | |
cf73d31f | 4905 | |
4906 | #if TARGET_ABI_OPEN_VMS | |
4907 | else if (GET_CODE (addr) == SYMBOL_REF) | |
4908 | { | |
4909 | fprintf (file, "%s", XSTR (addr, 0)); | |
4910 | return; | |
4911 | } | |
4912 | else if (GET_CODE (addr) == CONST | |
4913 | && GET_CODE (XEXP (addr, 0)) == PLUS | |
4914 | && GET_CODE (XEXP (XEXP (addr, 0), 0)) == SYMBOL_REF) | |
4915 | { | |
6433714e | 4916 | fprintf (file, "%s+" HOST_WIDE_INT_PRINT_DEC, |
cf73d31f | 4917 | XSTR (XEXP (XEXP (addr, 0), 0), 0), |
4918 | INTVAL (XEXP (XEXP (addr, 0), 1))); | |
4919 | return; | |
4920 | } | |
4921 | #endif | |
4922 | ||
6e0fe99e | 4923 | else |
4924 | abort (); | |
4925 | ||
4840a03a | 4926 | fprintf (file, HOST_WIDE_INT_PRINT_DEC "($%d)", offset, basereg); |
6e0fe99e | 4927 | } |
bf2a98b3 | 4928 | \f |
9e042f31 | 4929 | /* Emit RTL insns to initialize the variable parts of a trampoline at |
4930 | TRAMP. FNADDR is an RTX for the address of the function's pure | |
4931 | code. CXT is an RTX for the static chain value for the function. | |
96297568 | 4932 | |
4933 | The three offset parameters are for the individual template's | |
9e7454d0 | 4934 | layout. A JMPOFS < 0 indicates that the trampoline does not |
96297568 | 4935 | contain instructions at all. |
4936 | ||
9e042f31 | 4937 | We assume here that a function will be called many more times than |
4938 | its address is taken (e.g., it might be passed to qsort), so we | |
4939 | take the trouble to initialize the "hint" field in the JMP insn. | |
4940 | Note that the hint field is PC (new) + 4 * bits 13:0. */ | |
4941 | ||
4942 | void | |
92643d95 | 4943 | alpha_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt, |
4944 | int fnofs, int cxtofs, int jmpofs) | |
9e042f31 | 4945 | { |
4946 | rtx temp, temp1, addr; | |
17683b9f | 4947 | /* VMS really uses DImode pointers in memory at this point. */ |
1467e953 | 4948 | enum machine_mode mode = TARGET_ABI_OPEN_VMS ? Pmode : ptr_mode; |
9e042f31 | 4949 | |
17683b9f | 4950 | #ifdef POINTERS_EXTEND_UNSIGNED |
4951 | fnaddr = convert_memory_address (mode, fnaddr); | |
4952 | cxt = convert_memory_address (mode, cxt); | |
4953 | #endif | |
4954 | ||
9e042f31 | 4955 | /* Store function address and CXT. */ |
46ba8e1c | 4956 | addr = memory_address (mode, plus_constant (tramp, fnofs)); |
7014838c | 4957 | emit_move_insn (gen_rtx_MEM (mode, addr), fnaddr); |
46ba8e1c | 4958 | addr = memory_address (mode, plus_constant (tramp, cxtofs)); |
7014838c | 4959 | emit_move_insn (gen_rtx_MEM (mode, addr), cxt); |
96297568 | 4960 | |
4961 | /* This has been disabled since the hint only has a 32k range, and in | |
65abff06 | 4962 | no existing OS is the stack within 32k of the text segment. */ |
96297568 | 4963 | if (0 && jmpofs >= 0) |
4964 | { | |
4965 | /* Compute hint value. */ | |
4966 | temp = force_operand (plus_constant (tramp, jmpofs+4), NULL_RTX); | |
4967 | temp = expand_binop (DImode, sub_optab, fnaddr, temp, temp, 1, | |
4968 | OPTAB_WIDEN); | |
4969 | temp = expand_shift (RSHIFT_EXPR, Pmode, temp, | |
7016c612 | 4970 | build_int_cst (NULL_TREE, 2), NULL_RTX, 1); |
6de9716c | 4971 | temp = expand_and (SImode, gen_lowpart (SImode, temp), |
4972 | GEN_INT (0x3fff), 0); | |
96297568 | 4973 | |
4974 | /* Merge in the hint. */ | |
4975 | addr = memory_address (SImode, plus_constant (tramp, jmpofs)); | |
7014838c | 4976 | temp1 = force_reg (SImode, gen_rtx_MEM (SImode, addr)); |
6de9716c | 4977 | temp1 = expand_and (SImode, temp1, GEN_INT (0xffffc000), NULL_RTX); |
96297568 | 4978 | temp1 = expand_binop (SImode, ior_optab, temp1, temp, temp1, 1, |
4979 | OPTAB_WIDEN); | |
7014838c | 4980 | emit_move_insn (gen_rtx_MEM (SImode, addr), temp1); |
96297568 | 4981 | } |
9e042f31 | 4982 | |
5577e296 | 4983 | #ifdef ENABLE_EXECUTE_STACK |
09a1f342 | 4984 | emit_library_call (init_one_libfunc ("__enable_execute_stack"), |
f0bdd254 | 4985 | 0, VOIDmode, 1, tramp, Pmode); |
9e042f31 | 4986 | #endif |
4987 | ||
96297568 | 4988 | if (jmpofs >= 0) |
4989 | emit_insn (gen_imb ()); | |
9e042f31 | 4990 | } |
4991 | \f | |
915c336f | 4992 | /* Determine where to put an argument to a function. |
4993 | Value is zero to push the argument on the stack, | |
4994 | or a hard register in which to store the argument. | |
4995 | ||
4996 | MODE is the argument's machine mode. | |
4997 | TYPE is the data type of the argument (as a tree). | |
4998 | This is null for libcalls where that information may | |
4999 | not be available. | |
5000 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
5001 | the preceding args and about the function being called. | |
5002 | NAMED is nonzero if this argument is a named parameter | |
5003 | (otherwise it is an extra parameter matching an ellipsis). | |
5004 | ||
5005 | On Alpha the first 6 words of args are normally in registers | |
5006 | and the rest are pushed. */ | |
5007 | ||
5008 | rtx | |
92643d95 | 5009 | function_arg (CUMULATIVE_ARGS cum, enum machine_mode mode, tree type, |
5010 | int named ATTRIBUTE_UNUSED) | |
915c336f | 5011 | { |
5012 | int basereg; | |
57e47080 | 5013 | int num_args; |
915c336f | 5014 | |
a685f5d8 | 5015 | /* Don't get confused and pass small structures in FP registers. */ |
5016 | if (type && AGGREGATE_TYPE_P (type)) | |
9caef960 | 5017 | basereg = 16; |
a685f5d8 | 5018 | else |
5019 | { | |
5020 | #ifdef ENABLE_CHECKING | |
92d40bc4 | 5021 | /* With alpha_split_complex_arg, we shouldn't see any raw complex |
a685f5d8 | 5022 | values here. */ |
5023 | if (COMPLEX_MODE_P (mode)) | |
5024 | abort (); | |
5025 | #endif | |
5026 | ||
5027 | /* Set up defaults for FP operands passed in FP registers, and | |
5028 | integral operands passed in integer registers. */ | |
5029 | if (TARGET_FPREGS && GET_MODE_CLASS (mode) == MODE_FLOAT) | |
5030 | basereg = 32 + 16; | |
5031 | else | |
5032 | basereg = 16; | |
5033 | } | |
9caef960 | 5034 | |
5035 | /* ??? Irritatingly, the definition of CUMULATIVE_ARGS is different for | |
5036 | the three platforms, so we can't avoid conditional compilation. */ | |
1467e953 | 5037 | #if TARGET_ABI_OPEN_VMS |
9caef960 | 5038 | { |
5039 | if (mode == VOIDmode) | |
5040 | return alpha_arg_info_reg_val (cum); | |
1467e953 | 5041 | |
9caef960 | 5042 | num_args = cum.num_args; |
0336f0f0 | 5043 | if (num_args >= 6 |
5044 | || targetm.calls.must_pass_in_stack (mode, type)) | |
9caef960 | 5045 | return NULL_RTX; |
5046 | } | |
a685f5d8 | 5047 | #elif TARGET_ABI_UNICOSMK |
9caef960 | 5048 | { |
5049 | int size; | |
915c336f | 5050 | |
9caef960 | 5051 | /* If this is the last argument, generate the call info word (CIW). */ |
5052 | /* ??? We don't include the caller's line number in the CIW because | |
5053 | I don't know how to determine it if debug infos are turned off. */ | |
5054 | if (mode == VOIDmode) | |
5055 | { | |
5056 | int i; | |
5057 | HOST_WIDE_INT lo; | |
5058 | HOST_WIDE_INT hi; | |
5059 | rtx ciw; | |
5060 | ||
5061 | lo = 0; | |
5062 | ||
5063 | for (i = 0; i < cum.num_reg_words && i < 5; i++) | |
5064 | if (cum.reg_args_type[i]) | |
5065 | lo |= (1 << (7 - i)); | |
5066 | ||
5067 | if (cum.num_reg_words == 6 && cum.reg_args_type[5]) | |
5068 | lo |= 7; | |
5069 | else | |
5070 | lo |= cum.num_reg_words; | |
5071 | ||
5072 | #if HOST_BITS_PER_WIDE_INT == 32 | |
5073 | hi = (cum.num_args << 20) | cum.num_arg_words; | |
5074 | #else | |
e162157f | 5075 | lo = lo | ((HOST_WIDE_INT) cum.num_args << 52) |
5076 | | ((HOST_WIDE_INT) cum.num_arg_words << 32); | |
9caef960 | 5077 | hi = 0; |
5078 | #endif | |
5079 | ciw = immed_double_const (lo, hi, DImode); | |
5080 | ||
5081 | return gen_rtx_UNSPEC (DImode, gen_rtvec (1, ciw), | |
5082 | UNSPEC_UMK_LOAD_CIW); | |
5083 | } | |
5084 | ||
5085 | size = ALPHA_ARG_SIZE (mode, type, named); | |
5086 | num_args = cum.num_reg_words; | |
0336f0f0 | 5087 | if (cum.force_stack |
5088 | || cum.num_reg_words + size > 6 | |
5089 | || targetm.calls.must_pass_in_stack (mode, type)) | |
9caef960 | 5090 | return NULL_RTX; |
5091 | else if (type && TYPE_MODE (type) == BLKmode) | |
5092 | { | |
5093 | rtx reg1, reg2; | |
5094 | ||
5095 | reg1 = gen_rtx_REG (DImode, num_args + 16); | |
5096 | reg1 = gen_rtx_EXPR_LIST (DImode, reg1, const0_rtx); | |
5097 | ||
5098 | /* The argument fits in two registers. Note that we still need to | |
5099 | reserve a register for empty structures. */ | |
5100 | if (size == 0) | |
5101 | return NULL_RTX; | |
5102 | else if (size == 1) | |
5103 | return gen_rtx_PARALLEL (mode, gen_rtvec (1, reg1)); | |
5104 | else | |
5105 | { | |
5106 | reg2 = gen_rtx_REG (DImode, num_args + 17); | |
5107 | reg2 = gen_rtx_EXPR_LIST (DImode, reg2, GEN_INT (8)); | |
5108 | return gen_rtx_PARALLEL (mode, gen_rtvec (2, reg1, reg2)); | |
5109 | } | |
5110 | } | |
5111 | } | |
a685f5d8 | 5112 | #elif TARGET_ABI_OSF |
9caef960 | 5113 | { |
5114 | if (cum >= 6) | |
5115 | return NULL_RTX; | |
5116 | num_args = cum; | |
5117 | ||
5118 | /* VOID is passed as a special flag for "last argument". */ | |
5119 | if (type == void_type_node) | |
5120 | basereg = 16; | |
0336f0f0 | 5121 | else if (targetm.calls.must_pass_in_stack (mode, type)) |
9caef960 | 5122 | return NULL_RTX; |
9caef960 | 5123 | } |
a685f5d8 | 5124 | #else |
5125 | #error Unhandled ABI | |
5126 | #endif | |
915c336f | 5127 | |
57e47080 | 5128 | return gen_rtx_REG (mode, num_args + basereg); |
915c336f | 5129 | } |
5130 | ||
a685f5d8 | 5131 | /* Return true if TYPE must be returned in memory, instead of in registers. */ |
5132 | ||
dd9f3024 | 5133 | static bool |
5134 | alpha_return_in_memory (tree type, tree fndecl ATTRIBUTE_UNUSED) | |
a685f5d8 | 5135 | { |
dd9f3024 | 5136 | enum machine_mode mode = VOIDmode; |
a685f5d8 | 5137 | int size; |
5138 | ||
5139 | if (type) | |
5140 | { | |
5141 | mode = TYPE_MODE (type); | |
5142 | ||
5143 | /* All aggregates are returned in memory. */ | |
5144 | if (AGGREGATE_TYPE_P (type)) | |
5145 | return true; | |
5146 | } | |
5147 | ||
5148 | size = GET_MODE_SIZE (mode); | |
5149 | switch (GET_MODE_CLASS (mode)) | |
5150 | { | |
5151 | case MODE_VECTOR_FLOAT: | |
5152 | /* Pass all float vectors in memory, like an aggregate. */ | |
5153 | return true; | |
5154 | ||
5155 | case MODE_COMPLEX_FLOAT: | |
5156 | /* We judge complex floats on the size of their element, | |
5157 | not the size of the whole type. */ | |
5158 | size = GET_MODE_UNIT_SIZE (mode); | |
5159 | break; | |
5160 | ||
5161 | case MODE_INT: | |
5162 | case MODE_FLOAT: | |
5163 | case MODE_COMPLEX_INT: | |
5164 | case MODE_VECTOR_INT: | |
5165 | break; | |
5166 | ||
5167 | default: | |
9e7454d0 | 5168 | /* ??? We get called on all sorts of random stuff from |
a685f5d8 | 5169 | aggregate_value_p. We can't abort, but it's not clear |
5170 | what's safe to return. Pretend it's a struct I guess. */ | |
5171 | return true; | |
5172 | } | |
5173 | ||
5174 | /* Otherwise types must fit in one register. */ | |
5175 | return size > UNITS_PER_WORD; | |
5176 | } | |
5177 | ||
b981d932 | 5178 | /* Return true if TYPE should be passed by invisible reference. */ |
5179 | ||
5180 | static bool | |
5181 | alpha_pass_by_reference (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED, | |
5182 | enum machine_mode mode, | |
5183 | tree type ATTRIBUTE_UNUSED, | |
5184 | bool named ATTRIBUTE_UNUSED) | |
5185 | { | |
5186 | return mode == TFmode || mode == TCmode; | |
5187 | } | |
5188 | ||
a685f5d8 | 5189 | /* Define how to find the value returned by a function. VALTYPE is the |
5190 | data type of the value (as a tree). If the precise function being | |
5191 | called is known, FUNC is its FUNCTION_DECL; otherwise, FUNC is 0. | |
5192 | MODE is set instead of VALTYPE for libcalls. | |
5193 | ||
5194 | On Alpha the value is found in $0 for integer functions and | |
5195 | $f0 for floating-point functions. */ | |
5196 | ||
5197 | rtx | |
5198 | function_value (tree valtype, tree func ATTRIBUTE_UNUSED, | |
5199 | enum machine_mode mode) | |
5200 | { | |
79db42ad | 5201 | unsigned int regnum, dummy; |
a685f5d8 | 5202 | enum mode_class class; |
5203 | ||
5204 | #ifdef ENABLE_CHECKING | |
aaca40a8 | 5205 | if (valtype && alpha_return_in_memory (valtype, func)) |
a685f5d8 | 5206 | abort (); |
5207 | #endif | |
5208 | ||
5209 | if (valtype) | |
5210 | mode = TYPE_MODE (valtype); | |
5211 | ||
5212 | class = GET_MODE_CLASS (mode); | |
5213 | switch (class) | |
5214 | { | |
5215 | case MODE_INT: | |
79db42ad | 5216 | PROMOTE_MODE (mode, dummy, valtype); |
8e262b5e | 5217 | /* FALLTHRU */ |
a685f5d8 | 5218 | |
5219 | case MODE_COMPLEX_INT: | |
5220 | case MODE_VECTOR_INT: | |
5221 | regnum = 0; | |
5222 | break; | |
5223 | ||
5224 | case MODE_FLOAT: | |
5225 | regnum = 32; | |
5226 | break; | |
5227 | ||
5228 | case MODE_COMPLEX_FLOAT: | |
5229 | { | |
5230 | enum machine_mode cmode = GET_MODE_INNER (mode); | |
5231 | ||
5232 | return gen_rtx_PARALLEL | |
5233 | (VOIDmode, | |
5234 | gen_rtvec (2, | |
5235 | gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_REG (cmode, 32), | |
bcd9bd66 | 5236 | const0_rtx), |
a685f5d8 | 5237 | gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_REG (cmode, 33), |
5238 | GEN_INT (GET_MODE_SIZE (cmode))))); | |
5239 | } | |
5240 | ||
5241 | default: | |
5242 | abort (); | |
5243 | } | |
5244 | ||
5245 | return gen_rtx_REG (mode, regnum); | |
5246 | } | |
5247 | ||
9e7454d0 | 5248 | /* TCmode complex values are passed by invisible reference. We |
92d40bc4 | 5249 | should not split these values. */ |
5250 | ||
5251 | static bool | |
5252 | alpha_split_complex_arg (tree type) | |
5253 | { | |
5254 | return TYPE_MODE (type) != TCmode; | |
5255 | } | |
5256 | ||
2e15d750 | 5257 | static tree |
5258 | alpha_build_builtin_va_list (void) | |
bf2a98b3 | 5259 | { |
7ba21c9f | 5260 | tree base, ofs, space, record, type_decl; |
bf2a98b3 | 5261 | |
9caef960 | 5262 | if (TARGET_ABI_OPEN_VMS || TARGET_ABI_UNICOSMK) |
e7aabeab | 5263 | return ptr_type_node; |
5264 | ||
a1f71e15 | 5265 | record = (*lang_hooks.types.make_type) (RECORD_TYPE); |
0054fd98 | 5266 | type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record); |
5267 | TREE_CHAIN (record) = type_decl; | |
5268 | TYPE_NAME (record) = type_decl; | |
5269 | ||
e7aabeab | 5270 | /* C++? SET_IS_AGGR_TYPE (record, 1); */ |
bf2a98b3 | 5271 | |
7ba21c9f | 5272 | /* Dummy field to prevent alignment warnings. */ |
5273 | space = build_decl (FIELD_DECL, NULL_TREE, integer_type_node); | |
5274 | DECL_FIELD_CONTEXT (space) = record; | |
5275 | DECL_ARTIFICIAL (space) = 1; | |
5276 | DECL_IGNORED_P (space) = 1; | |
5277 | ||
e7aabeab | 5278 | ofs = build_decl (FIELD_DECL, get_identifier ("__offset"), |
5279 | integer_type_node); | |
5280 | DECL_FIELD_CONTEXT (ofs) = record; | |
7ba21c9f | 5281 | TREE_CHAIN (ofs) = space; |
fc4c89ed | 5282 | |
e7aabeab | 5283 | base = build_decl (FIELD_DECL, get_identifier ("__base"), |
5284 | ptr_type_node); | |
5285 | DECL_FIELD_CONTEXT (base) = record; | |
5286 | TREE_CHAIN (base) = ofs; | |
fc4c89ed | 5287 | |
e7aabeab | 5288 | TYPE_FIELDS (record) = base; |
5289 | layout_type (record); | |
5290 | ||
5291 | return record; | |
5292 | } | |
5293 | ||
4310aa50 | 5294 | /* Perform any needed actions needed for a function that is receiving a |
dd9f3024 | 5295 | variable number of arguments. */ |
4310aa50 | 5296 | |
dd9f3024 | 5297 | static void |
5298 | alpha_setup_incoming_varargs (CUMULATIVE_ARGS *pcum, | |
5299 | enum machine_mode mode ATTRIBUTE_UNUSED, | |
5300 | tree type ATTRIBUTE_UNUSED, | |
5301 | int *pretend_size, int no_rtl) | |
5302 | { | |
5303 | #if TARGET_ABI_UNICOSMK | |
5304 | /* On Unicos/Mk, the standard subroutine __T3E_MISMATCH stores all register | |
5305 | arguments on the stack. Unfortunately, it doesn't always store the first | |
5306 | one (i.e. the one that arrives in $16 or $f16). This is not a problem | |
5307 | with stdargs as we always have at least one named argument there. */ | |
5308 | int num_reg_words = pcum->num_reg_words; | |
5309 | if (num_reg_words < 6) | |
5310 | { | |
5311 | if (!no_rtl) | |
5312 | { | |
5313 | emit_insn (gen_umk_mismatch_args (GEN_INT (num_reg_words + 1))); | |
5314 | emit_insn (gen_arg_home_umk ()); | |
5315 | } | |
5316 | *pretend_size = 0; | |
5317 | } | |
5318 | #elif TARGET_ABI_OPEN_VMS | |
5319 | /* For VMS, we allocate space for all 6 arg registers plus a count. | |
4310aa50 | 5320 | |
dd9f3024 | 5321 | However, if NO registers need to be saved, don't allocate any space. |
5322 | This is not only because we won't need the space, but because AP | |
5323 | includes the current_pretend_args_size and we don't want to mess up | |
5324 | any ap-relative addresses already made. */ | |
5325 | if (pcum->num_args < 6) | |
5326 | { | |
5327 | if (!no_rtl) | |
5328 | { | |
5329 | emit_move_insn (gen_rtx_REG (DImode, 1), virtual_incoming_args_rtx); | |
5330 | emit_insn (gen_arg_home ()); | |
5331 | } | |
5332 | *pretend_size = 7 * UNITS_PER_WORD; | |
5333 | } | |
5334 | #else | |
5335 | /* On OSF/1 and friends, we allocate space for all 12 arg registers, but | |
5336 | only push those that are remaining. However, if NO registers need to | |
5337 | be saved, don't allocate any space. This is not only because we won't | |
5338 | need the space, but because AP includes the current_pretend_args_size | |
5339 | and we don't want to mess up any ap-relative addresses already made. | |
5340 | ||
5341 | If we are not to use the floating-point registers, save the integer | |
5342 | registers where we would put the floating-point registers. This is | |
5343 | not the most efficient way to implement varargs with just one register | |
5344 | class, but it isn't worth doing anything more efficient in this rare | |
5345 | case. */ | |
5346 | CUMULATIVE_ARGS cum = *pcum; | |
96f8cdd2 | 5347 | |
4310aa50 | 5348 | if (cum >= 6) |
5349 | return; | |
5350 | ||
5351 | if (!no_rtl) | |
5352 | { | |
5353 | int set = get_varargs_alias_set (); | |
5354 | rtx tmp; | |
5355 | ||
5356 | tmp = gen_rtx_MEM (BLKmode, | |
5357 | plus_constant (virtual_incoming_args_rtx, | |
5358 | (cum + 6) * UNITS_PER_WORD)); | |
5359 | set_mem_alias_set (tmp, set); | |
530178a9 | 5360 | move_block_from_reg (16 + cum, tmp, 6 - cum); |
4310aa50 | 5361 | |
5362 | tmp = gen_rtx_MEM (BLKmode, | |
5363 | plus_constant (virtual_incoming_args_rtx, | |
5364 | cum * UNITS_PER_WORD)); | |
5365 | set_mem_alias_set (tmp, set); | |
5366 | move_block_from_reg (16 + (TARGET_FPREGS ? 32 : 0) + cum, tmp, | |
530178a9 | 5367 | 6 - cum); |
4310aa50 | 5368 | } |
5369 | *pretend_size = 12 * UNITS_PER_WORD; | |
f6940372 | 5370 | #endif |
dd9f3024 | 5371 | } |
4310aa50 | 5372 | |
e7aabeab | 5373 | void |
92643d95 | 5374 | alpha_va_start (tree valist, rtx nextarg ATTRIBUTE_UNUSED) |
e7aabeab | 5375 | { |
5376 | HOST_WIDE_INT offset; | |
5377 | tree t, offset_field, base_field; | |
fc4c89ed | 5378 | |
80909c64 | 5379 | if (TREE_CODE (TREE_TYPE (valist)) == ERROR_MARK) |
5380 | return; | |
5381 | ||
fc264da3 | 5382 | if (TARGET_ABI_UNICOSMK) |
7df226a2 | 5383 | std_expand_builtin_va_start (valist, nextarg); |
e7aabeab | 5384 | |
6644435d | 5385 | /* For Unix, TARGET_SETUP_INCOMING_VARARGS moves the starting address base |
e7aabeab | 5386 | up by 48, storing fp arg registers in the first 48 bytes, and the |
5387 | integer arg registers in the next 48 bytes. This is only done, | |
5388 | however, if any integer registers need to be stored. | |
5389 | ||
5390 | If no integer registers need be stored, then we must subtract 48 | |
5391 | in order to account for the integer arg registers which are counted | |
4310aa50 | 5392 | in argsize above, but which are not actually stored on the stack. |
5393 | Must further be careful here about structures straddling the last | |
9e7454d0 | 5394 | integer argument register; that futzes with pretend_args_size, |
4310aa50 | 5395 | which changes the meaning of AP. */ |
e7aabeab | 5396 | |
7ccc713a | 5397 | if (NUM_ARGS <= 6) |
fc264da3 | 5398 | offset = TARGET_ABI_OPEN_VMS ? UNITS_PER_WORD : 6 * UNITS_PER_WORD; |
8df4a58b | 5399 | else |
4310aa50 | 5400 | offset = -6 * UNITS_PER_WORD + current_function_pretend_args_size; |
e7aabeab | 5401 | |
fc264da3 | 5402 | if (TARGET_ABI_OPEN_VMS) |
5403 | { | |
5404 | nextarg = plus_constant (nextarg, offset); | |
5405 | nextarg = plus_constant (nextarg, NUM_ARGS * UNITS_PER_WORD); | |
5406 | t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, | |
5407 | make_tree (ptr_type_node, nextarg)); | |
5408 | TREE_SIDE_EFFECTS (t) = 1; | |
e7aabeab | 5409 | |
fc264da3 | 5410 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); |
5411 | } | |
5412 | else | |
5413 | { | |
5414 | base_field = TYPE_FIELDS (TREE_TYPE (valist)); | |
5415 | offset_field = TREE_CHAIN (base_field); | |
5416 | ||
5417 | base_field = build (COMPONENT_REF, TREE_TYPE (base_field), | |
6374121b | 5418 | valist, base_field, NULL_TREE); |
fc264da3 | 5419 | offset_field = build (COMPONENT_REF, TREE_TYPE (offset_field), |
6374121b | 5420 | valist, offset_field, NULL_TREE); |
fc264da3 | 5421 | |
5422 | t = make_tree (ptr_type_node, virtual_incoming_args_rtx); | |
7c446c95 | 5423 | t = build (PLUS_EXPR, ptr_type_node, t, |
7016c612 | 5424 | build_int_cst (NULL_TREE, offset)); |
fc264da3 | 5425 | t = build (MODIFY_EXPR, TREE_TYPE (base_field), base_field, t); |
5426 | TREE_SIDE_EFFECTS (t) = 1; | |
5427 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
5428 | ||
7016c612 | 5429 | t = build_int_cst (NULL_TREE, NUM_ARGS * UNITS_PER_WORD); |
fc264da3 | 5430 | t = build (MODIFY_EXPR, TREE_TYPE (offset_field), offset_field, t); |
5431 | TREE_SIDE_EFFECTS (t) = 1; | |
5432 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
5433 | } | |
e7aabeab | 5434 | } |
5435 | ||
de8f9b94 | 5436 | static tree |
c7b3f103 | 5437 | alpha_gimplify_va_arg_1 (tree type, tree base, tree offset, tree *pre_p) |
de8f9b94 | 5438 | { |
c7b3f103 | 5439 | tree type_size, ptr_type, addend, t, addr, internal_post; |
de8f9b94 | 5440 | |
de8f9b94 | 5441 | /* If the type could not be passed in registers, skip the block |
5442 | reserved for the registers. */ | |
0336f0f0 | 5443 | if (targetm.calls.must_pass_in_stack (TYPE_MODE (type), type)) |
de8f9b94 | 5444 | { |
7016c612 | 5445 | t = build_int_cst (TREE_TYPE (offset), 6*8); |
de8f9b94 | 5446 | t = build (MODIFY_EXPR, TREE_TYPE (offset), offset, |
5447 | build (MAX_EXPR, TREE_TYPE (offset), offset, t)); | |
5448 | gimplify_and_add (t, pre_p); | |
5449 | } | |
5450 | ||
5451 | addend = offset; | |
5452 | ptr_type = build_pointer_type (type); | |
de8f9b94 | 5453 | |
2cd7bb84 | 5454 | if (TREE_CODE (type) == COMPLEX_TYPE) |
de8f9b94 | 5455 | { |
5456 | tree real_part, imag_part, real_temp; | |
5457 | ||
c7b3f103 | 5458 | real_part = alpha_gimplify_va_arg_1 (TREE_TYPE (type), base, |
5459 | offset, pre_p); | |
5460 | ||
5461 | /* Copy the value into a new temporary, lest the formal temporary | |
de8f9b94 | 5462 | be reused out from under us. */ |
c7b3f103 | 5463 | real_temp = get_initialized_tmp_var (real_part, pre_p, NULL); |
de8f9b94 | 5464 | |
c7b3f103 | 5465 | imag_part = alpha_gimplify_va_arg_1 (TREE_TYPE (type), base, |
5466 | offset, pre_p); | |
de8f9b94 | 5467 | |
5468 | return build (COMPLEX_EXPR, type, real_temp, imag_part); | |
5469 | } | |
5470 | else if (TREE_CODE (type) == REAL_TYPE) | |
5471 | { | |
5472 | tree fpaddend, cond, fourtyeight; | |
5473 | ||
7016c612 | 5474 | fourtyeight = build_int_cst (TREE_TYPE (addend), 6*8); |
de8f9b94 | 5475 | fpaddend = fold (build (MINUS_EXPR, TREE_TYPE (addend), |
5476 | addend, fourtyeight)); | |
5477 | cond = fold (build (LT_EXPR, boolean_type_node, addend, fourtyeight)); | |
5478 | addend = fold (build (COND_EXPR, TREE_TYPE (addend), cond, | |
5479 | fpaddend, addend)); | |
5480 | } | |
5481 | ||
5482 | /* Build the final address and force that value into a temporary. */ | |
5483 | addr = build (PLUS_EXPR, ptr_type, fold_convert (ptr_type, base), | |
5484 | fold_convert (ptr_type, addend)); | |
c7b3f103 | 5485 | internal_post = NULL; |
5486 | gimplify_expr (&addr, pre_p, &internal_post, is_gimple_val, fb_rvalue); | |
5487 | append_to_statement_list (internal_post, pre_p); | |
de8f9b94 | 5488 | |
5489 | /* Update the offset field. */ | |
c7b3f103 | 5490 | type_size = TYPE_SIZE_UNIT (TYPE_MAIN_VARIANT (type)); |
5491 | if (type_size == NULL || TREE_OVERFLOW (type_size)) | |
5492 | t = size_zero_node; | |
5493 | else | |
5494 | { | |
5495 | t = size_binop (PLUS_EXPR, type_size, size_int (7)); | |
5496 | t = size_binop (TRUNC_DIV_EXPR, t, size_int (8)); | |
5497 | t = size_binop (MULT_EXPR, t, size_int (8)); | |
5498 | } | |
5499 | t = fold_convert (TREE_TYPE (offset), t); | |
de8f9b94 | 5500 | t = build (MODIFY_EXPR, void_type_node, offset, |
5501 | build (PLUS_EXPR, TREE_TYPE (offset), offset, t)); | |
5502 | gimplify_and_add (t, pre_p); | |
5503 | ||
5504 | return build_fold_indirect_ref (addr); | |
5505 | } | |
5506 | ||
e0eca1fa | 5507 | static tree |
5508 | alpha_gimplify_va_arg (tree valist, tree type, tree *pre_p, tree *post_p) | |
de8f9b94 | 5509 | { |
e0eca1fa | 5510 | tree offset_field, base_field, offset, base, t, r; |
2cd7bb84 | 5511 | bool indirect; |
de8f9b94 | 5512 | |
5513 | if (TARGET_ABI_OPEN_VMS || TARGET_ABI_UNICOSMK) | |
e0eca1fa | 5514 | return std_gimplify_va_arg_expr (valist, type, pre_p, post_p); |
de8f9b94 | 5515 | |
5516 | base_field = TYPE_FIELDS (va_list_type_node); | |
5517 | offset_field = TREE_CHAIN (base_field); | |
5518 | base_field = build (COMPONENT_REF, TREE_TYPE (base_field), | |
6374121b | 5519 | valist, base_field, NULL_TREE); |
de8f9b94 | 5520 | offset_field = build (COMPONENT_REF, TREE_TYPE (offset_field), |
6374121b | 5521 | valist, offset_field, NULL_TREE); |
de8f9b94 | 5522 | |
c7b3f103 | 5523 | /* Pull the fields of the structure out into temporaries. Since we never |
5524 | modify the base field, we can use a formal temporary. Sign-extend the | |
5525 | offset field so that it's the proper width for pointer arithmetic. */ | |
5526 | base = get_formal_tmp_var (base_field, pre_p); | |
de8f9b94 | 5527 | |
c7b3f103 | 5528 | t = fold_convert (lang_hooks.types.type_for_size (64, 0), offset_field); |
5529 | offset = get_initialized_tmp_var (t, pre_p, NULL); | |
de8f9b94 | 5530 | |
2cd7bb84 | 5531 | indirect = pass_by_reference (NULL, TYPE_MODE (type), type, false); |
5532 | if (indirect) | |
5533 | type = build_pointer_type (type); | |
5534 | ||
de8f9b94 | 5535 | /* Find the value. Note that this will be a stable indirection, or |
5536 | a composite of stable indirections in the case of complex. */ | |
c7b3f103 | 5537 | r = alpha_gimplify_va_arg_1 (type, base, offset, pre_p); |
de8f9b94 | 5538 | |
5539 | /* Stuff the offset temporary back into its field. */ | |
5540 | t = build (MODIFY_EXPR, void_type_node, offset_field, | |
5541 | fold_convert (TREE_TYPE (offset_field), offset)); | |
5542 | gimplify_and_add (t, pre_p); | |
e0eca1fa | 5543 | |
2cd7bb84 | 5544 | if (indirect) |
5545 | r = build_fold_indirect_ref (r); | |
5546 | ||
e0eca1fa | 5547 | return r; |
de8f9b94 | 5548 | } |
bf2a98b3 | 5549 | \f |
f2cc13dc | 5550 | /* Builtins. */ |
5551 | ||
5552 | enum alpha_builtin | |
5553 | { | |
5554 | ALPHA_BUILTIN_CMPBGE, | |
ae4cd3a5 | 5555 | ALPHA_BUILTIN_EXTBL, |
5556 | ALPHA_BUILTIN_EXTWL, | |
5557 | ALPHA_BUILTIN_EXTLL, | |
f2cc13dc | 5558 | ALPHA_BUILTIN_EXTQL, |
ae4cd3a5 | 5559 | ALPHA_BUILTIN_EXTWH, |
5560 | ALPHA_BUILTIN_EXTLH, | |
f2cc13dc | 5561 | ALPHA_BUILTIN_EXTQH, |
ae4cd3a5 | 5562 | ALPHA_BUILTIN_INSBL, |
5563 | ALPHA_BUILTIN_INSWL, | |
5564 | ALPHA_BUILTIN_INSLL, | |
5565 | ALPHA_BUILTIN_INSQL, | |
5566 | ALPHA_BUILTIN_INSWH, | |
5567 | ALPHA_BUILTIN_INSLH, | |
5568 | ALPHA_BUILTIN_INSQH, | |
5569 | ALPHA_BUILTIN_MSKBL, | |
5570 | ALPHA_BUILTIN_MSKWL, | |
5571 | ALPHA_BUILTIN_MSKLL, | |
5572 | ALPHA_BUILTIN_MSKQL, | |
5573 | ALPHA_BUILTIN_MSKWH, | |
5574 | ALPHA_BUILTIN_MSKLH, | |
5575 | ALPHA_BUILTIN_MSKQH, | |
5576 | ALPHA_BUILTIN_UMULH, | |
f2cc13dc | 5577 | ALPHA_BUILTIN_ZAP, |
5578 | ALPHA_BUILTIN_ZAPNOT, | |
5579 | ALPHA_BUILTIN_AMASK, | |
5580 | ALPHA_BUILTIN_IMPLVER, | |
5581 | ALPHA_BUILTIN_RPCC, | |
938e069b | 5582 | ALPHA_BUILTIN_THREAD_POINTER, |
5583 | ALPHA_BUILTIN_SET_THREAD_POINTER, | |
f2cc13dc | 5584 | |
5585 | /* TARGET_MAX */ | |
5586 | ALPHA_BUILTIN_MINUB8, | |
5587 | ALPHA_BUILTIN_MINSB8, | |
5588 | ALPHA_BUILTIN_MINUW4, | |
5589 | ALPHA_BUILTIN_MINSW4, | |
5590 | ALPHA_BUILTIN_MAXUB8, | |
5591 | ALPHA_BUILTIN_MAXSB8, | |
5592 | ALPHA_BUILTIN_MAXUW4, | |
5593 | ALPHA_BUILTIN_MAXSW4, | |
5594 | ALPHA_BUILTIN_PERR, | |
5595 | ALPHA_BUILTIN_PKLB, | |
5596 | ALPHA_BUILTIN_PKWB, | |
5597 | ALPHA_BUILTIN_UNPKBL, | |
5598 | ALPHA_BUILTIN_UNPKBW, | |
5599 | ||
ae4cd3a5 | 5600 | /* TARGET_CIX */ |
5601 | ALPHA_BUILTIN_CTTZ, | |
5602 | ALPHA_BUILTIN_CTLZ, | |
5603 | ALPHA_BUILTIN_CTPOP, | |
5604 | ||
f2cc13dc | 5605 | ALPHA_BUILTIN_max |
5606 | }; | |
5607 | ||
ae4cd3a5 | 5608 | static unsigned int const code_for_builtin[ALPHA_BUILTIN_max] = { |
5609 | CODE_FOR_builtin_cmpbge, | |
5610 | CODE_FOR_builtin_extbl, | |
5611 | CODE_FOR_builtin_extwl, | |
5612 | CODE_FOR_builtin_extll, | |
5613 | CODE_FOR_builtin_extql, | |
5614 | CODE_FOR_builtin_extwh, | |
5615 | CODE_FOR_builtin_extlh, | |
5616 | CODE_FOR_builtin_extqh, | |
5617 | CODE_FOR_builtin_insbl, | |
5618 | CODE_FOR_builtin_inswl, | |
5619 | CODE_FOR_builtin_insll, | |
5620 | CODE_FOR_builtin_insql, | |
5621 | CODE_FOR_builtin_inswh, | |
5622 | CODE_FOR_builtin_inslh, | |
5623 | CODE_FOR_builtin_insqh, | |
5624 | CODE_FOR_builtin_mskbl, | |
5625 | CODE_FOR_builtin_mskwl, | |
5626 | CODE_FOR_builtin_mskll, | |
5627 | CODE_FOR_builtin_mskql, | |
5628 | CODE_FOR_builtin_mskwh, | |
5629 | CODE_FOR_builtin_msklh, | |
5630 | CODE_FOR_builtin_mskqh, | |
5631 | CODE_FOR_umuldi3_highpart, | |
5632 | CODE_FOR_builtin_zap, | |
5633 | CODE_FOR_builtin_zapnot, | |
5634 | CODE_FOR_builtin_amask, | |
5635 | CODE_FOR_builtin_implver, | |
5636 | CODE_FOR_builtin_rpcc, | |
938e069b | 5637 | CODE_FOR_load_tp, |
5638 | CODE_FOR_set_tp, | |
ae4cd3a5 | 5639 | |
5640 | /* TARGET_MAX */ | |
5641 | CODE_FOR_builtin_minub8, | |
5642 | CODE_FOR_builtin_minsb8, | |
5643 | CODE_FOR_builtin_minuw4, | |
5644 | CODE_FOR_builtin_minsw4, | |
5645 | CODE_FOR_builtin_maxub8, | |
5646 | CODE_FOR_builtin_maxsb8, | |
5647 | CODE_FOR_builtin_maxuw4, | |
5648 | CODE_FOR_builtin_maxsw4, | |
5649 | CODE_FOR_builtin_perr, | |
5650 | CODE_FOR_builtin_pklb, | |
5651 | CODE_FOR_builtin_pkwb, | |
5652 | CODE_FOR_builtin_unpkbl, | |
5653 | CODE_FOR_builtin_unpkbw, | |
5654 | ||
5655 | /* TARGET_CIX */ | |
5656 | CODE_FOR_builtin_cttz, | |
5657 | CODE_FOR_builtin_ctlz, | |
5658 | CODE_FOR_builtin_ctpop | |
5659 | }; | |
5660 | ||
f2cc13dc | 5661 | struct alpha_builtin_def |
5662 | { | |
5663 | const char *name; | |
5664 | enum alpha_builtin code; | |
5665 | unsigned int target_mask; | |
5666 | }; | |
5667 | ||
5668 | static struct alpha_builtin_def const zero_arg_builtins[] = { | |
5669 | { "__builtin_alpha_implver", ALPHA_BUILTIN_IMPLVER, 0 }, | |
5670 | { "__builtin_alpha_rpcc", ALPHA_BUILTIN_RPCC, 0 } | |
5671 | }; | |
5672 | ||
5673 | static struct alpha_builtin_def const one_arg_builtins[] = { | |
5674 | { "__builtin_alpha_amask", ALPHA_BUILTIN_AMASK, 0 }, | |
5675 | { "__builtin_alpha_pklb", ALPHA_BUILTIN_PKLB, MASK_MAX }, | |
5676 | { "__builtin_alpha_pkwb", ALPHA_BUILTIN_PKWB, MASK_MAX }, | |
5677 | { "__builtin_alpha_unpkbl", ALPHA_BUILTIN_UNPKBL, MASK_MAX }, | |
ae4cd3a5 | 5678 | { "__builtin_alpha_unpkbw", ALPHA_BUILTIN_UNPKBW, MASK_MAX }, |
5679 | { "__builtin_alpha_cttz", ALPHA_BUILTIN_CTTZ, MASK_CIX }, | |
5680 | { "__builtin_alpha_ctlz", ALPHA_BUILTIN_CTLZ, MASK_CIX }, | |
5681 | { "__builtin_alpha_ctpop", ALPHA_BUILTIN_CTPOP, MASK_CIX } | |
f2cc13dc | 5682 | }; |
5683 | ||
5684 | static struct alpha_builtin_def const two_arg_builtins[] = { | |
5685 | { "__builtin_alpha_cmpbge", ALPHA_BUILTIN_CMPBGE, 0 }, | |
ae4cd3a5 | 5686 | { "__builtin_alpha_extbl", ALPHA_BUILTIN_EXTBL, 0 }, |
5687 | { "__builtin_alpha_extwl", ALPHA_BUILTIN_EXTWL, 0 }, | |
5688 | { "__builtin_alpha_extll", ALPHA_BUILTIN_EXTLL, 0 }, | |
f2cc13dc | 5689 | { "__builtin_alpha_extql", ALPHA_BUILTIN_EXTQL, 0 }, |
ae4cd3a5 | 5690 | { "__builtin_alpha_extwh", ALPHA_BUILTIN_EXTWH, 0 }, |
5691 | { "__builtin_alpha_extlh", ALPHA_BUILTIN_EXTLH, 0 }, | |
f2cc13dc | 5692 | { "__builtin_alpha_extqh", ALPHA_BUILTIN_EXTQH, 0 }, |
ae4cd3a5 | 5693 | { "__builtin_alpha_insbl", ALPHA_BUILTIN_INSBL, 0 }, |
5694 | { "__builtin_alpha_inswl", ALPHA_BUILTIN_INSWL, 0 }, | |
5695 | { "__builtin_alpha_insll", ALPHA_BUILTIN_INSLL, 0 }, | |
5696 | { "__builtin_alpha_insql", ALPHA_BUILTIN_INSQL, 0 }, | |
5697 | { "__builtin_alpha_inswh", ALPHA_BUILTIN_INSWH, 0 }, | |
5698 | { "__builtin_alpha_inslh", ALPHA_BUILTIN_INSLH, 0 }, | |
5699 | { "__builtin_alpha_insqh", ALPHA_BUILTIN_INSQH, 0 }, | |
5700 | { "__builtin_alpha_mskbl", ALPHA_BUILTIN_MSKBL, 0 }, | |
5701 | { "__builtin_alpha_mskwl", ALPHA_BUILTIN_MSKWL, 0 }, | |
5702 | { "__builtin_alpha_mskll", ALPHA_BUILTIN_MSKLL, 0 }, | |
5703 | { "__builtin_alpha_mskql", ALPHA_BUILTIN_MSKQL, 0 }, | |
5704 | { "__builtin_alpha_mskwh", ALPHA_BUILTIN_MSKWH, 0 }, | |
5705 | { "__builtin_alpha_msklh", ALPHA_BUILTIN_MSKLH, 0 }, | |
5706 | { "__builtin_alpha_mskqh", ALPHA_BUILTIN_MSKQH, 0 }, | |
5707 | { "__builtin_alpha_umulh", ALPHA_BUILTIN_UMULH, 0 }, | |
f2cc13dc | 5708 | { "__builtin_alpha_zap", ALPHA_BUILTIN_ZAP, 0 }, |
5709 | { "__builtin_alpha_zapnot", ALPHA_BUILTIN_ZAPNOT, 0 }, | |
5710 | { "__builtin_alpha_minub8", ALPHA_BUILTIN_MINUB8, MASK_MAX }, | |
5711 | { "__builtin_alpha_minsb8", ALPHA_BUILTIN_MINSB8, MASK_MAX }, | |
5712 | { "__builtin_alpha_minuw4", ALPHA_BUILTIN_MINUW4, MASK_MAX }, | |
5713 | { "__builtin_alpha_minsw4", ALPHA_BUILTIN_MINSW4, MASK_MAX }, | |
5714 | { "__builtin_alpha_maxub8", ALPHA_BUILTIN_MAXUB8, MASK_MAX }, | |
5715 | { "__builtin_alpha_maxsb8", ALPHA_BUILTIN_MAXSB8, MASK_MAX }, | |
5716 | { "__builtin_alpha_maxuw4", ALPHA_BUILTIN_MAXUW4, MASK_MAX }, | |
5717 | { "__builtin_alpha_maxsw4", ALPHA_BUILTIN_MAXSW4, MASK_MAX }, | |
5718 | { "__builtin_alpha_perr", ALPHA_BUILTIN_PERR, MASK_MAX } | |
5719 | }; | |
5720 | ||
5721 | static void | |
92643d95 | 5722 | alpha_init_builtins (void) |
f2cc13dc | 5723 | { |
5724 | const struct alpha_builtin_def *p; | |
5725 | tree ftype; | |
5726 | size_t i; | |
5727 | ||
5728 | ftype = build_function_type (long_integer_type_node, void_list_node); | |
5729 | ||
5730 | p = zero_arg_builtins; | |
5731 | for (i = 0; i < ARRAY_SIZE (zero_arg_builtins); ++i, ++p) | |
5732 | if ((target_flags & p->target_mask) == p->target_mask) | |
e60d3615 | 5733 | lang_hooks.builtin_function (p->name, ftype, p->code, BUILT_IN_MD, |
5734 | NULL, NULL_TREE); | |
f2cc13dc | 5735 | |
8b55c4ba | 5736 | ftype = build_function_type_list (long_integer_type_node, |
5737 | long_integer_type_node, NULL_TREE); | |
f2cc13dc | 5738 | |
5739 | p = one_arg_builtins; | |
5740 | for (i = 0; i < ARRAY_SIZE (one_arg_builtins); ++i, ++p) | |
5741 | if ((target_flags & p->target_mask) == p->target_mask) | |
e60d3615 | 5742 | lang_hooks.builtin_function (p->name, ftype, p->code, BUILT_IN_MD, |
5743 | NULL, NULL_TREE); | |
f2cc13dc | 5744 | |
8b55c4ba | 5745 | ftype = build_function_type_list (long_integer_type_node, |
5746 | long_integer_type_node, | |
5747 | long_integer_type_node, NULL_TREE); | |
f2cc13dc | 5748 | |
5749 | p = two_arg_builtins; | |
5750 | for (i = 0; i < ARRAY_SIZE (two_arg_builtins); ++i, ++p) | |
5751 | if ((target_flags & p->target_mask) == p->target_mask) | |
e60d3615 | 5752 | lang_hooks.builtin_function (p->name, ftype, p->code, BUILT_IN_MD, |
5753 | NULL, NULL_TREE); | |
938e069b | 5754 | |
5755 | ftype = build_function_type (ptr_type_node, void_list_node); | |
e60d3615 | 5756 | lang_hooks.builtin_function ("__builtin_thread_pointer", ftype, |
5757 | ALPHA_BUILTIN_THREAD_POINTER, BUILT_IN_MD, | |
5758 | NULL, NULL_TREE); | |
938e069b | 5759 | |
8b55c4ba | 5760 | ftype = build_function_type_list (void_type_node, ptr_type_node, NULL_TREE); |
e60d3615 | 5761 | lang_hooks.builtin_function ("__builtin_set_thread_pointer", ftype, |
5762 | ALPHA_BUILTIN_SET_THREAD_POINTER, BUILT_IN_MD, | |
5763 | NULL, NULL_TREE); | |
f2cc13dc | 5764 | } |
5765 | ||
5766 | /* Expand an expression EXP that calls a built-in function, | |
5767 | with result going to TARGET if that's convenient | |
5768 | (and in mode MODE if that's convenient). | |
5769 | SUBTARGET may be used as the target for computing one of EXP's operands. | |
5770 | IGNORE is nonzero if the value is to be ignored. */ | |
5771 | ||
5772 | static rtx | |
92643d95 | 5773 | alpha_expand_builtin (tree exp, rtx target, |
5774 | rtx subtarget ATTRIBUTE_UNUSED, | |
5775 | enum machine_mode mode ATTRIBUTE_UNUSED, | |
5776 | int ignore ATTRIBUTE_UNUSED) | |
f2cc13dc | 5777 | { |
f2cc13dc | 5778 | #define MAX_ARGS 2 |
5779 | ||
5780 | tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); | |
5781 | unsigned int fcode = DECL_FUNCTION_CODE (fndecl); | |
5782 | tree arglist = TREE_OPERAND (exp, 1); | |
5783 | enum insn_code icode; | |
5784 | rtx op[MAX_ARGS], pat; | |
5785 | int arity; | |
938e069b | 5786 | bool nonvoid; |
f2cc13dc | 5787 | |
5788 | if (fcode >= ALPHA_BUILTIN_max) | |
5789 | internal_error ("bad builtin fcode"); | |
5790 | icode = code_for_builtin[fcode]; | |
5791 | if (icode == 0) | |
5792 | internal_error ("bad builtin fcode"); | |
5793 | ||
938e069b | 5794 | nonvoid = TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node; |
5795 | ||
f2cc13dc | 5796 | for (arglist = TREE_OPERAND (exp, 1), arity = 0; |
5797 | arglist; | |
5798 | arglist = TREE_CHAIN (arglist), arity++) | |
5799 | { | |
5800 | const struct insn_operand_data *insn_op; | |
5801 | ||
5802 | tree arg = TREE_VALUE (arglist); | |
5803 | if (arg == error_mark_node) | |
5804 | return NULL_RTX; | |
5805 | if (arity > MAX_ARGS) | |
5806 | return NULL_RTX; | |
5807 | ||
938e069b | 5808 | insn_op = &insn_data[icode].operand[arity + nonvoid]; |
5809 | ||
5810 | op[arity] = expand_expr (arg, NULL_RTX, insn_op->mode, 0); | |
f2cc13dc | 5811 | |
f2cc13dc | 5812 | if (!(*insn_op->predicate) (op[arity], insn_op->mode)) |
5813 | op[arity] = copy_to_mode_reg (insn_op->mode, op[arity]); | |
5814 | } | |
5815 | ||
938e069b | 5816 | if (nonvoid) |
5817 | { | |
5818 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
5819 | if (!target | |
5820 | || GET_MODE (target) != tmode | |
5821 | || !(*insn_data[icode].operand[0].predicate) (target, tmode)) | |
5822 | target = gen_reg_rtx (tmode); | |
5823 | } | |
f2cc13dc | 5824 | |
5825 | switch (arity) | |
5826 | { | |
5827 | case 0: | |
5828 | pat = GEN_FCN (icode) (target); | |
5829 | break; | |
5830 | case 1: | |
938e069b | 5831 | if (nonvoid) |
5832 | pat = GEN_FCN (icode) (target, op[0]); | |
5833 | else | |
5834 | pat = GEN_FCN (icode) (op[0]); | |
f2cc13dc | 5835 | break; |
5836 | case 2: | |
5837 | pat = GEN_FCN (icode) (target, op[0], op[1]); | |
5838 | break; | |
5839 | default: | |
5840 | abort (); | |
5841 | } | |
5842 | if (!pat) | |
5843 | return NULL_RTX; | |
5844 | emit_insn (pat); | |
5845 | ||
938e069b | 5846 | if (nonvoid) |
5847 | return target; | |
5848 | else | |
5849 | return const0_rtx; | |
f2cc13dc | 5850 | } |
5851 | \f | |
bf2a98b3 | 5852 | /* This page contains routines that are used to determine what the function |
5853 | prologue and epilogue code will do and write them out. */ | |
5854 | ||
5855 | /* Compute the size of the save area in the stack. */ | |
5856 | ||
8df4a58b | 5857 | /* These variables are used for communication between the following functions. |
5858 | They indicate various things about the current function being compiled | |
5859 | that are used to tell what kind of prologue, epilogue and procedure | |
efee20da | 5860 | descriptor to generate. */ |
8df4a58b | 5861 | |
5862 | /* Nonzero if we need a stack procedure. */ | |
b19d7ab1 | 5863 | enum alpha_procedure_types {PT_NULL = 0, PT_REGISTER = 1, PT_STACK = 2}; |
5864 | static enum alpha_procedure_types alpha_procedure_type; | |
8df4a58b | 5865 | |
5866 | /* Register number (either FP or SP) that is used to unwind the frame. */ | |
b9a5aa8e | 5867 | static int vms_unwind_regno; |
8df4a58b | 5868 | |
5869 | /* Register number used to save FP. We need not have one for RA since | |
5870 | we don't modify it for register procedures. This is only defined | |
5871 | for register frame procedures. */ | |
b9a5aa8e | 5872 | static int vms_save_fp_regno; |
8df4a58b | 5873 | |
5874 | /* Register number used to reference objects off our PV. */ | |
b9a5aa8e | 5875 | static int vms_base_regno; |
8df4a58b | 5876 | |
2cf1388a | 5877 | /* Compute register masks for saved registers. */ |
8df4a58b | 5878 | |
5879 | static void | |
92643d95 | 5880 | alpha_sa_mask (unsigned long *imaskP, unsigned long *fmaskP) |
8df4a58b | 5881 | { |
5882 | unsigned long imask = 0; | |
5883 | unsigned long fmask = 0; | |
1f0ce6a6 | 5884 | unsigned int i; |
8df4a58b | 5885 | |
eaa112a0 | 5886 | /* When outputting a thunk, we don't have valid register life info, |
5887 | but assemble_start_function wants to output .frame and .mask | |
5888 | directives. */ | |
5889 | if (current_function_is_thunk) | |
2cf1388a | 5890 | { |
961d6ddd | 5891 | *imaskP = 0; |
5892 | *fmaskP = 0; | |
5893 | return; | |
5894 | } | |
8df4a58b | 5895 | |
b19d7ab1 | 5896 | if (TARGET_ABI_OPEN_VMS && alpha_procedure_type == PT_STACK) |
df7d0d23 | 5897 | imask |= (1UL << HARD_FRAME_POINTER_REGNUM); |
8df4a58b | 5898 | |
961d6ddd | 5899 | /* One for every register we have to save. */ |
5900 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
5901 | if (! fixed_regs[i] && ! call_used_regs[i] | |
5902 | && regs_ever_live[i] && i != REG_RA | |
5903 | && (!TARGET_ABI_UNICOSMK || i != HARD_FRAME_POINTER_REGNUM)) | |
5904 | { | |
5905 | if (i < 32) | |
df7d0d23 | 5906 | imask |= (1UL << i); |
961d6ddd | 5907 | else |
df7d0d23 | 5908 | fmask |= (1UL << (i - 32)); |
961d6ddd | 5909 | } |
5910 | ||
5911 | /* We need to restore these for the handler. */ | |
5912 | if (current_function_calls_eh_return) | |
c49ad9ef | 5913 | { |
5914 | for (i = 0; ; ++i) | |
5915 | { | |
5916 | unsigned regno = EH_RETURN_DATA_REGNO (i); | |
5917 | if (regno == INVALID_REGNUM) | |
5918 | break; | |
5919 | imask |= 1UL << regno; | |
5920 | } | |
5921 | ||
5922 | /* Glibc likes to use $31 as an unwind stopper for crt0. To | |
5923 | avoid hackery in unwind-dw2.c, we need to actively store a | |
5924 | zero in the prologue of _Unwind_RaiseException et al. */ | |
5925 | imask |= 1UL << 31; | |
5926 | } | |
9e7454d0 | 5927 | |
961d6ddd | 5928 | /* If any register spilled, then spill the return address also. */ |
5929 | /* ??? This is required by the Digital stack unwind specification | |
5930 | and isn't needed if we're doing Dwarf2 unwinding. */ | |
5931 | if (imask || fmask || alpha_ra_ever_killed ()) | |
df7d0d23 | 5932 | imask |= (1UL << REG_RA); |
b9a5aa8e | 5933 | |
8df4a58b | 5934 | *imaskP = imask; |
5935 | *fmaskP = fmask; | |
8df4a58b | 5936 | } |
5937 | ||
5938 | int | |
92643d95 | 5939 | alpha_sa_size (void) |
8df4a58b | 5940 | { |
5aae9d06 | 5941 | unsigned long mask[2]; |
8df4a58b | 5942 | int sa_size = 0; |
5aae9d06 | 5943 | int i, j; |
8df4a58b | 5944 | |
5aae9d06 | 5945 | alpha_sa_mask (&mask[0], &mask[1]); |
5946 | ||
5947 | if (TARGET_ABI_UNICOSMK) | |
5948 | { | |
5949 | if (mask[0] || mask[1]) | |
5950 | sa_size = 14; | |
5951 | } | |
2cf1388a | 5952 | else |
2cf1388a | 5953 | { |
5aae9d06 | 5954 | for (j = 0; j < 2; ++j) |
5955 | for (i = 0; i < 32; ++i) | |
5956 | if ((mask[j] >> i) & 1) | |
5957 | sa_size++; | |
2cf1388a | 5958 | } |
8df4a58b | 5959 | |
9caef960 | 5960 | if (TARGET_ABI_UNICOSMK) |
5961 | { | |
5962 | /* We might not need to generate a frame if we don't make any calls | |
5963 | (including calls to __T3E_MISMATCH if this is a vararg function), | |
5964 | don't have any local variables which require stack slots, don't | |
5965 | use alloca and have not determined that we need a frame for other | |
5966 | reasons. */ | |
5967 | ||
b19d7ab1 | 5968 | alpha_procedure_type |
5969 | = (sa_size || get_frame_size() != 0 | |
7ccc713a | 5970 | || current_function_outgoing_args_size |
b19d7ab1 | 5971 | || current_function_stdarg || current_function_calls_alloca |
5972 | || frame_pointer_needed) | |
5973 | ? PT_STACK : PT_REGISTER; | |
9caef960 | 5974 | |
5975 | /* Always reserve space for saving callee-saved registers if we | |
5976 | need a frame as required by the calling convention. */ | |
b19d7ab1 | 5977 | if (alpha_procedure_type == PT_STACK) |
9caef960 | 5978 | sa_size = 14; |
5979 | } | |
5980 | else if (TARGET_ABI_OPEN_VMS) | |
b9a5aa8e | 5981 | { |
5982 | /* Start by assuming we can use a register procedure if we don't | |
5983 | make any calls (REG_RA not used) or need to save any | |
5984 | registers and a stack procedure if we do. */ | |
b19d7ab1 | 5985 | if ((mask[0] >> REG_RA) & 1) |
5986 | alpha_procedure_type = PT_STACK; | |
5987 | else if (get_frame_size() != 0) | |
5988 | alpha_procedure_type = PT_REGISTER; | |
5989 | else | |
5990 | alpha_procedure_type = PT_NULL; | |
5aae9d06 | 5991 | |
2ab60bb1 | 5992 | /* Don't reserve space for saving FP & RA yet. Do that later after we've |
5aae9d06 | 5993 | made the final decision on stack procedure vs register procedure. */ |
b19d7ab1 | 5994 | if (alpha_procedure_type == PT_STACK) |
2ab60bb1 | 5995 | sa_size -= 2; |
b9a5aa8e | 5996 | |
5997 | /* Decide whether to refer to objects off our PV via FP or PV. | |
5998 | If we need FP for something else or if we receive a nonlocal | |
5999 | goto (which expects PV to contain the value), we must use PV. | |
6000 | Otherwise, start by assuming we can use FP. */ | |
b19d7ab1 | 6001 | |
6002 | vms_base_regno | |
6003 | = (frame_pointer_needed | |
6004 | || current_function_has_nonlocal_label | |
6005 | || alpha_procedure_type == PT_STACK | |
6006 | || current_function_outgoing_args_size) | |
6007 | ? REG_PV : HARD_FRAME_POINTER_REGNUM; | |
b9a5aa8e | 6008 | |
6009 | /* If we want to copy PV into FP, we need to find some register | |
6010 | in which to save FP. */ | |
6011 | ||
6012 | vms_save_fp_regno = -1; | |
6013 | if (vms_base_regno == HARD_FRAME_POINTER_REGNUM) | |
6014 | for (i = 0; i < 32; i++) | |
6015 | if (! fixed_regs[i] && call_used_regs[i] && ! regs_ever_live[i]) | |
6016 | vms_save_fp_regno = i; | |
6017 | ||
b19d7ab1 | 6018 | if (vms_save_fp_regno == -1 && alpha_procedure_type == PT_REGISTER) |
6019 | vms_base_regno = REG_PV, alpha_procedure_type = PT_STACK; | |
6020 | else if (alpha_procedure_type == PT_NULL) | |
6021 | vms_base_regno = REG_PV; | |
b9a5aa8e | 6022 | |
6023 | /* Stack unwinding should be done via FP unless we use it for PV. */ | |
6024 | vms_unwind_regno = (vms_base_regno == REG_PV | |
6025 | ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM); | |
6026 | ||
6027 | /* If this is a stack procedure, allow space for saving FP and RA. */ | |
b19d7ab1 | 6028 | if (alpha_procedure_type == PT_STACK) |
b9a5aa8e | 6029 | sa_size += 2; |
6030 | } | |
6031 | else | |
6032 | { | |
b9a5aa8e | 6033 | /* Our size must be even (multiple of 16 bytes). */ |
6034 | if (sa_size & 1) | |
6035 | sa_size++; | |
6036 | } | |
8df4a58b | 6037 | |
6038 | return sa_size * 8; | |
6039 | } | |
6040 | ||
4310aa50 | 6041 | /* Define the offset between two registers, one to be eliminated, |
6042 | and the other its replacement, at the start of a routine. */ | |
6043 | ||
6044 | HOST_WIDE_INT | |
92643d95 | 6045 | alpha_initial_elimination_offset (unsigned int from, |
6046 | unsigned int to ATTRIBUTE_UNUSED) | |
4310aa50 | 6047 | { |
6048 | HOST_WIDE_INT ret; | |
6049 | ||
6050 | ret = alpha_sa_size (); | |
6051 | ret += ALPHA_ROUND (current_function_outgoing_args_size); | |
6052 | ||
6053 | if (from == FRAME_POINTER_REGNUM) | |
6054 | ; | |
6055 | else if (from == ARG_POINTER_REGNUM) | |
6056 | ret += (ALPHA_ROUND (get_frame_size () | |
6057 | + current_function_pretend_args_size) | |
6058 | - current_function_pretend_args_size); | |
6059 | else | |
6060 | abort (); | |
6061 | ||
6062 | return ret; | |
6063 | } | |
6064 | ||
8df4a58b | 6065 | int |
92643d95 | 6066 | alpha_pv_save_size (void) |
8df4a58b | 6067 | { |
6068 | alpha_sa_size (); | |
b19d7ab1 | 6069 | return alpha_procedure_type == PT_STACK ? 8 : 0; |
8df4a58b | 6070 | } |
6071 | ||
6072 | int | |
92643d95 | 6073 | alpha_using_fp (void) |
8df4a58b | 6074 | { |
6075 | alpha_sa_size (); | |
b9a5aa8e | 6076 | return vms_unwind_regno == HARD_FRAME_POINTER_REGNUM; |
8df4a58b | 6077 | } |
6078 | ||
1467e953 | 6079 | #if TARGET_ABI_OPEN_VMS |
2d280039 | 6080 | |
e3c541f0 | 6081 | const struct attribute_spec vms_attribute_table[] = |
bf2a98b3 | 6082 | { |
e3c541f0 | 6083 | /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */ |
c64a8830 | 6084 | { "overlaid", 0, 0, true, false, false, NULL }, |
6085 | { "global", 0, 0, true, false, false, NULL }, | |
6086 | { "initialize", 0, 0, true, false, false, NULL }, | |
6087 | { NULL, 0, 0, false, false, false, NULL } | |
e3c541f0 | 6088 | }; |
bf2a98b3 | 6089 | |
2d280039 | 6090 | #endif |
6091 | ||
1f0ce6a6 | 6092 | static int |
92643d95 | 6093 | find_lo_sum_using_gp (rtx *px, void *data ATTRIBUTE_UNUSED) |
1f0ce6a6 | 6094 | { |
a3859c0f | 6095 | return GET_CODE (*px) == LO_SUM && XEXP (*px, 0) == pic_offset_table_rtx; |
6096 | } | |
6097 | ||
6098 | int | |
92643d95 | 6099 | alpha_find_lo_sum_using_gp (rtx insn) |
a3859c0f | 6100 | { |
6101 | return for_each_rtx (&PATTERN (insn), find_lo_sum_using_gp, NULL) > 0; | |
1f0ce6a6 | 6102 | } |
6103 | ||
b9a5aa8e | 6104 | static int |
92643d95 | 6105 | alpha_does_function_need_gp (void) |
b9a5aa8e | 6106 | { |
6107 | rtx insn; | |
bf2a98b3 | 6108 | |
9caef960 | 6109 | /* The GP being variable is an OSF abi thing. */ |
6110 | if (! TARGET_ABI_OSF) | |
b9a5aa8e | 6111 | return 0; |
bf2a98b3 | 6112 | |
008fdc59 | 6113 | /* We need the gp to load the address of __mcount. */ |
7811c823 | 6114 | if (TARGET_PROFILING_NEEDS_GP && current_function_profile) |
b9a5aa8e | 6115 | return 1; |
0e0a0e7a | 6116 | |
008fdc59 | 6117 | /* The code emitted by alpha_output_mi_thunk_osf uses the gp. */ |
2cf1388a | 6118 | if (current_function_is_thunk) |
6119 | return 1; | |
2cf1388a | 6120 | |
008fdc59 | 6121 | /* The nonlocal receiver pattern assumes that the gp is valid for |
6122 | the nested function. Reasonable because it's almost always set | |
6123 | correctly already. For the cases where that's wrong, make sure | |
6124 | the nested function loads its gp on entry. */ | |
6125 | if (current_function_has_nonlocal_goto) | |
6126 | return 1; | |
6127 | ||
9e7454d0 | 6128 | /* If we need a GP (we have a LDSYM insn or a CALL_INSN), load it first. |
b9a5aa8e | 6129 | Even if we are a static function, we still need to do this in case |
6130 | our address is taken and passed to something like qsort. */ | |
bf2a98b3 | 6131 | |
b9a5aa8e | 6132 | push_topmost_sequence (); |
6133 | insn = get_insns (); | |
6134 | pop_topmost_sequence (); | |
8df4a58b | 6135 | |
b9a5aa8e | 6136 | for (; insn; insn = NEXT_INSN (insn)) |
9204e736 | 6137 | if (INSN_P (insn) |
b9a5aa8e | 6138 | && GET_CODE (PATTERN (insn)) != USE |
a3859c0f | 6139 | && GET_CODE (PATTERN (insn)) != CLOBBER |
6140 | && get_attr_usegp (insn)) | |
6141 | return 1; | |
bf2a98b3 | 6142 | |
b9a5aa8e | 6143 | return 0; |
bf2a98b3 | 6144 | } |
6145 | ||
7d73bc2a | 6146 | \f |
5a965225 | 6147 | /* Helper function to set RTX_FRAME_RELATED_P on instructions, including |
6148 | sequences. */ | |
6149 | ||
6150 | static rtx | |
92643d95 | 6151 | set_frame_related_p (void) |
5a965225 | 6152 | { |
31d3e01c | 6153 | rtx seq = get_insns (); |
6154 | rtx insn; | |
6155 | ||
5a965225 | 6156 | end_sequence (); |
6157 | ||
31d3e01c | 6158 | if (!seq) |
6159 | return NULL_RTX; | |
6160 | ||
6161 | if (INSN_P (seq)) | |
5a965225 | 6162 | { |
31d3e01c | 6163 | insn = seq; |
6164 | while (insn != NULL_RTX) | |
6165 | { | |
6166 | RTX_FRAME_RELATED_P (insn) = 1; | |
6167 | insn = NEXT_INSN (insn); | |
6168 | } | |
6169 | seq = emit_insn (seq); | |
5a965225 | 6170 | } |
6171 | else | |
6172 | { | |
6173 | seq = emit_insn (seq); | |
6174 | RTX_FRAME_RELATED_P (seq) = 1; | |
5a965225 | 6175 | } |
31d3e01c | 6176 | return seq; |
5a965225 | 6177 | } |
6178 | ||
6179 | #define FRP(exp) (start_sequence (), exp, set_frame_related_p ()) | |
6180 | ||
fb0de38e | 6181 | /* Generates a store with the proper unwind info attached. VALUE is |
183f1993 | 6182 | stored at BASE_REG+BASE_OFS. If FRAME_BIAS is nonzero, then BASE_REG |
fb0de38e | 6183 | contains SP+FRAME_BIAS, and that is the unwind info that should be |
6184 | generated. If FRAME_REG != VALUE, then VALUE is being stored on | |
6185 | behalf of FRAME_REG, and FRAME_REG should be present in the unwind. */ | |
6186 | ||
6187 | static void | |
6188 | emit_frame_store_1 (rtx value, rtx base_reg, HOST_WIDE_INT frame_bias, | |
6189 | HOST_WIDE_INT base_ofs, rtx frame_reg) | |
6190 | { | |
6191 | rtx addr, mem, insn; | |
6192 | ||
6193 | addr = plus_constant (base_reg, base_ofs); | |
6194 | mem = gen_rtx_MEM (DImode, addr); | |
6195 | set_mem_alias_set (mem, alpha_sr_alias_set); | |
6196 | ||
6197 | insn = emit_move_insn (mem, value); | |
6198 | RTX_FRAME_RELATED_P (insn) = 1; | |
6199 | ||
6200 | if (frame_bias || value != frame_reg) | |
6201 | { | |
6202 | if (frame_bias) | |
6203 | { | |
6204 | addr = plus_constant (stack_pointer_rtx, frame_bias + base_ofs); | |
6205 | mem = gen_rtx_MEM (DImode, addr); | |
6206 | } | |
6207 | ||
6208 | REG_NOTES (insn) | |
6209 | = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
6210 | gen_rtx_SET (VOIDmode, mem, frame_reg), | |
6211 | REG_NOTES (insn)); | |
6212 | } | |
6213 | } | |
6214 | ||
6215 | static void | |
6216 | emit_frame_store (unsigned int regno, rtx base_reg, | |
6217 | HOST_WIDE_INT frame_bias, HOST_WIDE_INT base_ofs) | |
6218 | { | |
6219 | rtx reg = gen_rtx_REG (DImode, regno); | |
6220 | emit_frame_store_1 (reg, base_reg, frame_bias, base_ofs, reg); | |
6221 | } | |
6222 | ||
bf2a98b3 | 6223 | /* Write function prologue. */ |
6224 | ||
8df4a58b | 6225 | /* On vms we have two kinds of functions: |
6226 | ||
6227 | - stack frame (PROC_STACK) | |
6228 | these are 'normal' functions with local vars and which are | |
6229 | calling other functions | |
6230 | - register frame (PROC_REGISTER) | |
6231 | keeps all data in registers, needs no stack | |
6232 | ||
6233 | We must pass this to the assembler so it can generate the | |
6234 | proper pdsc (procedure descriptor) | |
6235 | This is done with the '.pdesc' command. | |
6236 | ||
b9a5aa8e | 6237 | On not-vms, we don't really differentiate between the two, as we can |
6238 | simply allocate stack without saving registers. */ | |
8df4a58b | 6239 | |
6240 | void | |
92643d95 | 6241 | alpha_expand_prologue (void) |
8df4a58b | 6242 | { |
b9a5aa8e | 6243 | /* Registers to save. */ |
8df4a58b | 6244 | unsigned long imask = 0; |
6245 | unsigned long fmask = 0; | |
6246 | /* Stack space needed for pushing registers clobbered by us. */ | |
6247 | HOST_WIDE_INT sa_size; | |
6248 | /* Complete stack size needed. */ | |
6249 | HOST_WIDE_INT frame_size; | |
6250 | /* Offset from base reg to register save area. */ | |
b9a5aa8e | 6251 | HOST_WIDE_INT reg_offset; |
fb0de38e | 6252 | rtx sa_reg; |
8df4a58b | 6253 | int i; |
6254 | ||
6255 | sa_size = alpha_sa_size (); | |
8df4a58b | 6256 | |
b9a5aa8e | 6257 | frame_size = get_frame_size (); |
1467e953 | 6258 | if (TARGET_ABI_OPEN_VMS) |
9e7454d0 | 6259 | frame_size = ALPHA_ROUND (sa_size |
b19d7ab1 | 6260 | + (alpha_procedure_type == PT_STACK ? 8 : 0) |
b9a5aa8e | 6261 | + frame_size |
6262 | + current_function_pretend_args_size); | |
9caef960 | 6263 | else if (TARGET_ABI_UNICOSMK) |
6264 | /* We have to allocate space for the DSIB if we generate a frame. */ | |
6265 | frame_size = ALPHA_ROUND (sa_size | |
b19d7ab1 | 6266 | + (alpha_procedure_type == PT_STACK ? 48 : 0)) |
9caef960 | 6267 | + ALPHA_ROUND (frame_size |
6268 | + current_function_outgoing_args_size); | |
b9a5aa8e | 6269 | else |
6270 | frame_size = (ALPHA_ROUND (current_function_outgoing_args_size) | |
6271 | + sa_size | |
6272 | + ALPHA_ROUND (frame_size | |
6273 | + current_function_pretend_args_size)); | |
8df4a58b | 6274 | |
1467e953 | 6275 | if (TARGET_ABI_OPEN_VMS) |
b9a5aa8e | 6276 | reg_offset = 8; |
6277 | else | |
6278 | reg_offset = ALPHA_ROUND (current_function_outgoing_args_size); | |
8df4a58b | 6279 | |
b9a5aa8e | 6280 | alpha_sa_mask (&imask, &fmask); |
8df4a58b | 6281 | |
a314eb5e | 6282 | /* Emit an insn to reload GP, if needed. */ |
1467e953 | 6283 | if (TARGET_ABI_OSF) |
a314eb5e | 6284 | { |
6285 | alpha_function_needs_gp = alpha_does_function_need_gp (); | |
6286 | if (alpha_function_needs_gp) | |
6287 | emit_insn (gen_prologue_ldgp ()); | |
6288 | } | |
6289 | ||
30dceb30 | 6290 | /* TARGET_PROFILING_NEEDS_GP actually implies that we need to insert |
6291 | the call to mcount ourselves, rather than having the linker do it | |
6292 | magically in response to -pg. Since _mcount has special linkage, | |
6293 | don't represent the call as a call. */ | |
7811c823 | 6294 | if (TARGET_PROFILING_NEEDS_GP && current_function_profile) |
30dceb30 | 6295 | emit_insn (gen_prologue_mcount ()); |
9caef960 | 6296 | |
6297 | if (TARGET_ABI_UNICOSMK) | |
6298 | unicosmk_gen_dsib (&imask); | |
6299 | ||
8df4a58b | 6300 | /* Adjust the stack by the frame size. If the frame size is > 4096 |
6301 | bytes, we need to be sure we probe somewhere in the first and last | |
6302 | 4096 bytes (we can probably get away without the latter test) and | |
6303 | every 8192 bytes in between. If the frame size is > 32768, we | |
6304 | do this in a loop. Otherwise, we generate the explicit probe | |
9e7454d0 | 6305 | instructions. |
8df4a58b | 6306 | |
6307 | Note that we are only allowed to adjust sp once in the prologue. */ | |
6308 | ||
b9a5aa8e | 6309 | if (frame_size <= 32768) |
8df4a58b | 6310 | { |
6311 | if (frame_size > 4096) | |
6312 | { | |
6313 | int probed = 4096; | |
6314 | ||
b9a5aa8e | 6315 | do |
9caef960 | 6316 | emit_insn (gen_probe_stack (GEN_INT (TARGET_ABI_UNICOSMK |
6317 | ? -probed + 64 | |
6318 | : -probed))); | |
b9a5aa8e | 6319 | while ((probed += 8192) < frame_size); |
8df4a58b | 6320 | |
6321 | /* We only have to do this probe if we aren't saving registers. */ | |
6322 | if (sa_size == 0 && probed + 4096 < frame_size) | |
b9a5aa8e | 6323 | emit_insn (gen_probe_stack (GEN_INT (-frame_size))); |
8df4a58b | 6324 | } |
6325 | ||
6326 | if (frame_size != 0) | |
205b281f | 6327 | FRP (emit_insn (gen_adddi3 (stack_pointer_rtx, stack_pointer_rtx, |
9caef960 | 6328 | GEN_INT (TARGET_ABI_UNICOSMK |
6329 | ? -frame_size + 64 | |
6330 | : -frame_size)))); | |
8df4a58b | 6331 | } |
6332 | else | |
6333 | { | |
b9a5aa8e | 6334 | /* Here we generate code to set R22 to SP + 4096 and set R23 to the |
8df4a58b | 6335 | number of 8192 byte blocks to probe. We then probe each block |
6336 | in the loop and then set SP to the proper location. If the | |
6337 | amount remaining is > 4096, we have to do one more probe if we | |
6338 | are not saving any registers. */ | |
6339 | ||
6340 | HOST_WIDE_INT blocks = (frame_size + 4096) / 8192; | |
6341 | HOST_WIDE_INT leftover = frame_size + 4096 - blocks * 8192; | |
b9a5aa8e | 6342 | rtx ptr = gen_rtx_REG (DImode, 22); |
6343 | rtx count = gen_rtx_REG (DImode, 23); | |
cd28cb76 | 6344 | rtx seq; |
8df4a58b | 6345 | |
b9a5aa8e | 6346 | emit_move_insn (count, GEN_INT (blocks)); |
9caef960 | 6347 | emit_insn (gen_adddi3 (ptr, stack_pointer_rtx, |
6348 | GEN_INT (TARGET_ABI_UNICOSMK ? 4096 - 64 : 4096))); | |
8df4a58b | 6349 | |
b9a5aa8e | 6350 | /* Because of the difficulty in emitting a new basic block this |
6351 | late in the compilation, generate the loop as a single insn. */ | |
6352 | emit_insn (gen_prologue_stack_probe_loop (count, ptr)); | |
8df4a58b | 6353 | |
6354 | if (leftover > 4096 && sa_size == 0) | |
b9a5aa8e | 6355 | { |
6356 | rtx last = gen_rtx_MEM (DImode, plus_constant (ptr, -leftover)); | |
6357 | MEM_VOLATILE_P (last) = 1; | |
6358 | emit_move_insn (last, const0_rtx); | |
6359 | } | |
8df4a58b | 6360 | |
1467e953 | 6361 | if (TARGET_ABI_WINDOWS_NT) |
f88f2646 | 6362 | { |
6363 | /* For NT stack unwind (done by 'reverse execution'), it's | |
6364 | not OK to take the result of a loop, even though the value | |
6365 | is already in ptr, so we reload it via a single operation | |
9e7454d0 | 6366 | and subtract it to sp. |
cd28cb76 | 6367 | |
6368 | Yes, that's correct -- we have to reload the whole constant | |
df9e12ce | 6369 | into a temporary via ldah+lda then subtract from sp. */ |
f88f2646 | 6370 | |
6371 | HOST_WIDE_INT lo, hi; | |
05bea6dd | 6372 | lo = ((frame_size & 0xffff) ^ 0x8000) - 0x8000; |
6373 | hi = frame_size - lo; | |
5a965225 | 6374 | |
cd28cb76 | 6375 | emit_move_insn (ptr, GEN_INT (hi)); |
df9e12ce | 6376 | emit_insn (gen_adddi3 (ptr, ptr, GEN_INT (lo))); |
cd28cb76 | 6377 | seq = emit_insn (gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx, |
6378 | ptr)); | |
f88f2646 | 6379 | } |
6380 | else | |
6381 | { | |
f88f2646 | 6382 | seq = emit_insn (gen_adddi3 (stack_pointer_rtx, ptr, |
6383 | GEN_INT (-leftover))); | |
f88f2646 | 6384 | } |
cd28cb76 | 6385 | |
6386 | /* This alternative is special, because the DWARF code cannot | |
6387 | possibly intuit through the loop above. So we invent this | |
6388 | note it looks at instead. */ | |
6389 | RTX_FRAME_RELATED_P (seq) = 1; | |
6390 | REG_NOTES (seq) | |
6391 | = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
6392 | gen_rtx_SET (VOIDmode, stack_pointer_rtx, | |
6393 | gen_rtx_PLUS (Pmode, stack_pointer_rtx, | |
9caef960 | 6394 | GEN_INT (TARGET_ABI_UNICOSMK |
6395 | ? -frame_size + 64 | |
6396 | : -frame_size))), | |
cd28cb76 | 6397 | REG_NOTES (seq)); |
8df4a58b | 6398 | } |
6399 | ||
9caef960 | 6400 | if (!TARGET_ABI_UNICOSMK) |
8df4a58b | 6401 | { |
fb0de38e | 6402 | HOST_WIDE_INT sa_bias = 0; |
6403 | ||
9caef960 | 6404 | /* Cope with very large offsets to the register save area. */ |
6405 | sa_reg = stack_pointer_rtx; | |
6406 | if (reg_offset + sa_size > 0x8000) | |
6407 | { | |
6408 | int low = ((reg_offset & 0xffff) ^ 0x8000) - 0x8000; | |
fb0de38e | 6409 | rtx sa_bias_rtx; |
8df4a58b | 6410 | |
9caef960 | 6411 | if (low + sa_size <= 0x8000) |
fb0de38e | 6412 | sa_bias = reg_offset - low, reg_offset = low; |
9e7454d0 | 6413 | else |
fb0de38e | 6414 | sa_bias = reg_offset, reg_offset = 0; |
8df4a58b | 6415 | |
9caef960 | 6416 | sa_reg = gen_rtx_REG (DImode, 24); |
fb0de38e | 6417 | sa_bias_rtx = GEN_INT (sa_bias); |
6418 | ||
6419 | if (add_operand (sa_bias_rtx, DImode)) | |
6420 | emit_insn (gen_adddi3 (sa_reg, stack_pointer_rtx, sa_bias_rtx)); | |
6421 | else | |
6422 | { | |
6423 | emit_move_insn (sa_reg, sa_bias_rtx); | |
6424 | emit_insn (gen_adddi3 (sa_reg, stack_pointer_rtx, sa_reg)); | |
6425 | } | |
9caef960 | 6426 | } |
9e7454d0 | 6427 | |
9caef960 | 6428 | /* Save regs in stack order. Beginning with VMS PV. */ |
b19d7ab1 | 6429 | if (TARGET_ABI_OPEN_VMS && alpha_procedure_type == PT_STACK) |
fb0de38e | 6430 | emit_frame_store (REG_PV, stack_pointer_rtx, 0, 0); |
8df4a58b | 6431 | |
9caef960 | 6432 | /* Save register RA next. */ |
df7d0d23 | 6433 | if (imask & (1UL << REG_RA)) |
9caef960 | 6434 | { |
fb0de38e | 6435 | emit_frame_store (REG_RA, sa_reg, sa_bias, reg_offset); |
df7d0d23 | 6436 | imask &= ~(1UL << REG_RA); |
9caef960 | 6437 | reg_offset += 8; |
6438 | } | |
8df4a58b | 6439 | |
9caef960 | 6440 | /* Now save any other registers required to be saved. */ |
c49ad9ef | 6441 | for (i = 0; i < 31; i++) |
df7d0d23 | 6442 | if (imask & (1UL << i)) |
9caef960 | 6443 | { |
fb0de38e | 6444 | emit_frame_store (i, sa_reg, sa_bias, reg_offset); |
9caef960 | 6445 | reg_offset += 8; |
6446 | } | |
8df4a58b | 6447 | |
c49ad9ef | 6448 | /* Store a zero if requested for unwinding. */ |
6449 | if (imask & (1UL << 31)) | |
6450 | { | |
fb0de38e | 6451 | emit_frame_store_1 (const0_rtx, sa_reg, sa_bias, reg_offset, |
6452 | gen_rtx_REG (Pmode, 31)); | |
c49ad9ef | 6453 | reg_offset += 8; |
6454 | } | |
6455 | ||
6456 | for (i = 0; i < 31; i++) | |
df7d0d23 | 6457 | if (fmask & (1UL << i)) |
9caef960 | 6458 | { |
fb0de38e | 6459 | emit_frame_store (i+32, sa_reg, sa_bias, reg_offset); |
9caef960 | 6460 | reg_offset += 8; |
6461 | } | |
6462 | } | |
b19d7ab1 | 6463 | else if (TARGET_ABI_UNICOSMK && alpha_procedure_type == PT_STACK) |
9caef960 | 6464 | { |
6465 | /* The standard frame on the T3E includes space for saving registers. | |
6466 | We just have to use it. We don't have to save the return address and | |
6467 | the old frame pointer here - they are saved in the DSIB. */ | |
6468 | ||
6469 | reg_offset = -56; | |
6470 | for (i = 9; i < 15; i++) | |
df7d0d23 | 6471 | if (imask & (1UL << i)) |
9caef960 | 6472 | { |
fb0de38e | 6473 | emit_frame_store (i, hard_frame_pointer_rtx, 0, reg_offset); |
9caef960 | 6474 | reg_offset -= 8; |
6475 | } | |
6476 | for (i = 2; i < 10; i++) | |
df7d0d23 | 6477 | if (fmask & (1UL << i)) |
9caef960 | 6478 | { |
fb0de38e | 6479 | emit_frame_store (i+32, hard_frame_pointer_rtx, 0, reg_offset); |
9caef960 | 6480 | reg_offset -= 8; |
6481 | } | |
6482 | } | |
8df4a58b | 6483 | |
1467e953 | 6484 | if (TARGET_ABI_OPEN_VMS) |
8df4a58b | 6485 | { |
b19d7ab1 | 6486 | if (alpha_procedure_type == PT_REGISTER) |
6487 | /* Register frame procedures save the fp. | |
6488 | ?? Ought to have a dwarf2 save for this. */ | |
6d50e356 | 6489 | emit_move_insn (gen_rtx_REG (DImode, vms_save_fp_regno), |
6490 | hard_frame_pointer_rtx); | |
8df4a58b | 6491 | |
b19d7ab1 | 6492 | if (alpha_procedure_type != PT_NULL && vms_base_regno != REG_PV) |
6d50e356 | 6493 | emit_insn (gen_force_movdi (gen_rtx_REG (DImode, vms_base_regno), |
6494 | gen_rtx_REG (DImode, REG_PV))); | |
8df4a58b | 6495 | |
b19d7ab1 | 6496 | if (alpha_procedure_type != PT_NULL |
6497 | && vms_unwind_regno == HARD_FRAME_POINTER_REGNUM) | |
205b281f | 6498 | FRP (emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx)); |
8df4a58b | 6499 | |
b9a5aa8e | 6500 | /* If we have to allocate space for outgoing args, do it now. */ |
6501 | if (current_function_outgoing_args_size != 0) | |
81a5b286 | 6502 | { |
6503 | rtx seq | |
9e7454d0 | 6504 | = emit_move_insn (stack_pointer_rtx, |
81a5b286 | 6505 | plus_constant |
6506 | (hard_frame_pointer_rtx, | |
6507 | - (ALPHA_ROUND | |
6508 | (current_function_outgoing_args_size)))); | |
9e7454d0 | 6509 | |
81a5b286 | 6510 | /* Only set FRAME_RELATED_P on the stack adjustment we just emitted |
6511 | if ! frame_pointer_needed. Setting the bit will change the CFA | |
6512 | computation rule to use sp again, which would be wrong if we had | |
6513 | frame_pointer_needed, as this means sp might move unpredictably | |
6514 | later on. | |
6515 | ||
6516 | Also, note that | |
6517 | frame_pointer_needed | |
6518 | => vms_unwind_regno == HARD_FRAME_POINTER_REGNUM | |
6519 | and | |
6520 | current_function_outgoing_args_size != 0 | |
6521 | => alpha_procedure_type != PT_NULL, | |
6522 | ||
6523 | so when we are not setting the bit here, we are guaranteed to | |
5910bb95 | 6524 | have emitted an FRP frame pointer update just before. */ |
81a5b286 | 6525 | RTX_FRAME_RELATED_P (seq) = ! frame_pointer_needed; |
6526 | } | |
b9a5aa8e | 6527 | } |
9caef960 | 6528 | else if (!TARGET_ABI_UNICOSMK) |
b9a5aa8e | 6529 | { |
6530 | /* If we need a frame pointer, set it from the stack pointer. */ | |
6531 | if (frame_pointer_needed) | |
6532 | { | |
6533 | if (TARGET_CAN_FAULT_IN_PROLOGUE) | |
5a965225 | 6534 | FRP (emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx)); |
8df4a58b | 6535 | else |
205b281f | 6536 | /* This must always be the last instruction in the |
6537 | prologue, thus we emit a special move + clobber. */ | |
5a965225 | 6538 | FRP (emit_insn (gen_init_fp (hard_frame_pointer_rtx, |
6539 | stack_pointer_rtx, sa_reg))); | |
8df4a58b | 6540 | } |
8df4a58b | 6541 | } |
6542 | ||
b9a5aa8e | 6543 | /* The ABIs for VMS and OSF/1 say that while we can schedule insns into |
6544 | the prologue, for exception handling reasons, we cannot do this for | |
6545 | any insn that might fault. We could prevent this for mems with a | |
6546 | (clobber:BLK (scratch)), but this doesn't work for fp insns. So we | |
6547 | have to prevent all such scheduling with a blockage. | |
8df4a58b | 6548 | |
9e7454d0 | 6549 | Linux, on the other hand, never bothered to implement OSF/1's |
b9a5aa8e | 6550 | exception handling, and so doesn't care about such things. Anyone |
6551 | planning to use dwarf2 frame-unwind info can also omit the blockage. */ | |
8df4a58b | 6552 | |
b9a5aa8e | 6553 | if (! TARGET_CAN_FAULT_IN_PROLOGUE) |
6554 | emit_insn (gen_blockage ()); | |
1fce2e8a | 6555 | } |
6556 | ||
2cf1388a | 6557 | /* Output the textual info surrounding the prologue. */ |
8df4a58b | 6558 | |
b9a5aa8e | 6559 | void |
92643d95 | 6560 | alpha_start_function (FILE *file, const char *fnname, |
6561 | tree decl ATTRIBUTE_UNUSED) | |
0c0464e6 | 6562 | { |
b9a5aa8e | 6563 | unsigned long imask = 0; |
6564 | unsigned long fmask = 0; | |
6565 | /* Stack space needed for pushing registers clobbered by us. */ | |
6566 | HOST_WIDE_INT sa_size; | |
6567 | /* Complete stack size needed. */ | |
f9e9d81d | 6568 | unsigned HOST_WIDE_INT frame_size; |
b9a5aa8e | 6569 | /* Offset from base reg to register save area. */ |
6570 | HOST_WIDE_INT reg_offset; | |
2cf1388a | 6571 | char *entry_label = (char *) alloca (strlen (fnname) + 6); |
b9a5aa8e | 6572 | int i; |
0c0464e6 | 6573 | |
9caef960 | 6574 | /* Don't emit an extern directive for functions defined in the same file. */ |
6575 | if (TARGET_ABI_UNICOSMK) | |
6576 | { | |
6577 | tree name_tree; | |
6578 | name_tree = get_identifier (fnname); | |
6579 | TREE_ASM_WRITTEN (name_tree) = 1; | |
6580 | } | |
6581 | ||
a314eb5e | 6582 | alpha_fnname = fnname; |
b9a5aa8e | 6583 | sa_size = alpha_sa_size (); |
0c0464e6 | 6584 | |
b9a5aa8e | 6585 | frame_size = get_frame_size (); |
1467e953 | 6586 | if (TARGET_ABI_OPEN_VMS) |
9e7454d0 | 6587 | frame_size = ALPHA_ROUND (sa_size |
b19d7ab1 | 6588 | + (alpha_procedure_type == PT_STACK ? 8 : 0) |
b9a5aa8e | 6589 | + frame_size |
6590 | + current_function_pretend_args_size); | |
9caef960 | 6591 | else if (TARGET_ABI_UNICOSMK) |
6592 | frame_size = ALPHA_ROUND (sa_size | |
b19d7ab1 | 6593 | + (alpha_procedure_type == PT_STACK ? 48 : 0)) |
9caef960 | 6594 | + ALPHA_ROUND (frame_size |
6595 | + current_function_outgoing_args_size); | |
b9a5aa8e | 6596 | else |
6597 | frame_size = (ALPHA_ROUND (current_function_outgoing_args_size) | |
6598 | + sa_size | |
6599 | + ALPHA_ROUND (frame_size | |
6600 | + current_function_pretend_args_size)); | |
0c0464e6 | 6601 | |
1467e953 | 6602 | if (TARGET_ABI_OPEN_VMS) |
b9a5aa8e | 6603 | reg_offset = 8; |
6604 | else | |
6605 | reg_offset = ALPHA_ROUND (current_function_outgoing_args_size); | |
0c0464e6 | 6606 | |
b9a5aa8e | 6607 | alpha_sa_mask (&imask, &fmask); |
bf2a98b3 | 6608 | |
0e0a0e7a | 6609 | /* Ecoff can handle multiple .file directives, so put out file and lineno. |
449b7f2d | 6610 | We have to do that before the .ent directive as we cannot switch |
6611 | files within procedures with native ecoff because line numbers are | |
6612 | linked to procedure descriptors. | |
6613 | Outputting the lineno helps debugging of one line functions as they | |
6614 | would otherwise get no line number at all. Please note that we would | |
01cc3b75 | 6615 | like to put out last_linenum from final.c, but it is not accessible. */ |
449b7f2d | 6616 | |
6617 | if (write_symbols == SDB_DEBUG) | |
6618 | { | |
9caef960 | 6619 | #ifdef ASM_OUTPUT_SOURCE_FILENAME |
346064d9 | 6620 | ASM_OUTPUT_SOURCE_FILENAME (file, |
6621 | DECL_SOURCE_FILE (current_function_decl)); | |
9caef960 | 6622 | #endif |
6623 | #ifdef ASM_OUTPUT_SOURCE_LINE | |
449b7f2d | 6624 | if (debug_info_level != DINFO_LEVEL_TERSE) |
346064d9 | 6625 | ASM_OUTPUT_SOURCE_LINE (file, |
6626 | DECL_SOURCE_LINE (current_function_decl), 0); | |
9caef960 | 6627 | #endif |
449b7f2d | 6628 | } |
6629 | ||
b9a5aa8e | 6630 | /* Issue function start and label. */ |
9caef960 | 6631 | if (TARGET_ABI_OPEN_VMS |
6632 | || (!TARGET_ABI_UNICOSMK && !flag_inhibit_size_directive)) | |
f1fe649e | 6633 | { |
b9a5aa8e | 6634 | fputs ("\t.ent ", file); |
2cf1388a | 6635 | assemble_name (file, fnname); |
b9a5aa8e | 6636 | putc ('\n', file); |
a314eb5e | 6637 | |
6638 | /* If the function needs GP, we'll write the "..ng" label there. | |
6639 | Otherwise, do it here. */ | |
961d6ddd | 6640 | if (TARGET_ABI_OSF |
6641 | && ! alpha_function_needs_gp | |
6642 | && ! current_function_is_thunk) | |
a314eb5e | 6643 | { |
6644 | putc ('$', file); | |
6645 | assemble_name (file, fnname); | |
6646 | fputs ("..ng:\n", file); | |
6647 | } | |
f1fe649e | 6648 | } |
449b7f2d | 6649 | |
2cf1388a | 6650 | strcpy (entry_label, fnname); |
1467e953 | 6651 | if (TARGET_ABI_OPEN_VMS) |
b9a5aa8e | 6652 | strcat (entry_label, "..en"); |
9caef960 | 6653 | |
6654 | /* For public functions, the label must be globalized by appending an | |
6655 | additional colon. */ | |
6656 | if (TARGET_ABI_UNICOSMK && TREE_PUBLIC (decl)) | |
6657 | strcat (entry_label, ":"); | |
6658 | ||
b9a5aa8e | 6659 | ASM_OUTPUT_LABEL (file, entry_label); |
6660 | inside_function = TRUE; | |
449b7f2d | 6661 | |
1467e953 | 6662 | if (TARGET_ABI_OPEN_VMS) |
b9a5aa8e | 6663 | fprintf (file, "\t.base $%d\n", vms_base_regno); |
bf2a98b3 | 6664 | |
9caef960 | 6665 | if (!TARGET_ABI_OPEN_VMS && !TARGET_ABI_UNICOSMK && TARGET_IEEE_CONFORMANT |
b9a5aa8e | 6666 | && !flag_inhibit_size_directive) |
9c0e5703 | 6667 | { |
b9a5aa8e | 6668 | /* Set flags in procedure descriptor to request IEEE-conformant |
6669 | math-library routines. The value we set it to is PDSC_EXC_IEEE | |
65abff06 | 6670 | (/usr/include/pdsc.h). */ |
b9a5aa8e | 6671 | fputs ("\t.eflag 48\n", file); |
9c0e5703 | 6672 | } |
bf2a98b3 | 6673 | |
b9a5aa8e | 6674 | /* Set up offsets to alpha virtual arg/local debugging pointer. */ |
6675 | alpha_auto_offset = -frame_size + current_function_pretend_args_size; | |
6676 | alpha_arg_offset = -frame_size + 48; | |
cb015df5 | 6677 | |
b9a5aa8e | 6678 | /* Describe our frame. If the frame size is larger than an integer, |
6679 | print it as zero to avoid an assembler error. We won't be | |
6680 | properly describing such a frame, but that's the best we can do. */ | |
9caef960 | 6681 | if (TARGET_ABI_UNICOSMK) |
6682 | ; | |
6683 | else if (TARGET_ABI_OPEN_VMS) | |
4840a03a | 6684 | fprintf (file, "\t.frame $%d," HOST_WIDE_INT_PRINT_DEC ",$26," |
6685 | HOST_WIDE_INT_PRINT_DEC "\n", | |
6686 | vms_unwind_regno, | |
6687 | frame_size >= (1UL << 31) ? 0 : frame_size, | |
6688 | reg_offset); | |
b9a5aa8e | 6689 | else if (!flag_inhibit_size_directive) |
4840a03a | 6690 | fprintf (file, "\t.frame $%d," HOST_WIDE_INT_PRINT_DEC ",$26,%d\n", |
6691 | (frame_pointer_needed | |
6692 | ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM), | |
6693 | frame_size >= (1UL << 31) ? 0 : frame_size, | |
6694 | current_function_pretend_args_size); | |
15d5236f | 6695 | |
b9a5aa8e | 6696 | /* Describe which registers were spilled. */ |
9caef960 | 6697 | if (TARGET_ABI_UNICOSMK) |
6698 | ; | |
6699 | else if (TARGET_ABI_OPEN_VMS) | |
15d5236f | 6700 | { |
b9a5aa8e | 6701 | if (imask) |
9caef960 | 6702 | /* ??? Does VMS care if mask contains ra? The old code didn't |
b9a5aa8e | 6703 | set it, so I don't here. */ |
df7d0d23 | 6704 | fprintf (file, "\t.mask 0x%lx,0\n", imask & ~(1UL << REG_RA)); |
b9a5aa8e | 6705 | if (fmask) |
769ea120 | 6706 | fprintf (file, "\t.fmask 0x%lx,0\n", fmask); |
b19d7ab1 | 6707 | if (alpha_procedure_type == PT_REGISTER) |
b9a5aa8e | 6708 | fprintf (file, "\t.fp_save $%d\n", vms_save_fp_regno); |
6709 | } | |
6710 | else if (!flag_inhibit_size_directive) | |
6711 | { | |
6712 | if (imask) | |
15d5236f | 6713 | { |
4840a03a | 6714 | fprintf (file, "\t.mask 0x%lx," HOST_WIDE_INT_PRINT_DEC "\n", imask, |
df7d0d23 | 6715 | frame_size >= (1UL << 31) ? 0 : reg_offset - frame_size); |
b9a5aa8e | 6716 | |
6717 | for (i = 0; i < 32; ++i) | |
df7d0d23 | 6718 | if (imask & (1UL << i)) |
b9a5aa8e | 6719 | reg_offset += 8; |
15d5236f | 6720 | } |
b9a5aa8e | 6721 | |
6722 | if (fmask) | |
4840a03a | 6723 | fprintf (file, "\t.fmask 0x%lx," HOST_WIDE_INT_PRINT_DEC "\n", fmask, |
6724 | frame_size >= (1UL << 31) ? 0 : reg_offset - frame_size); | |
bf2a98b3 | 6725 | } |
6726 | ||
1467e953 | 6727 | #if TARGET_ABI_OPEN_VMS |
6cde52a2 | 6728 | /* Ifdef'ed cause link_section are only available then. */ |
6729 | readonly_data_section (); | |
b9a5aa8e | 6730 | fprintf (file, "\t.align 3\n"); |
2cf1388a | 6731 | assemble_name (file, fnname); fputs ("..na:\n", file); |
b9a5aa8e | 6732 | fputs ("\t.ascii \"", file); |
2cf1388a | 6733 | assemble_name (file, fnname); |
b9a5aa8e | 6734 | fputs ("\\0\"\n", file); |
2cf1388a | 6735 | alpha_need_linkage (fnname, 1); |
b9a5aa8e | 6736 | text_section (); |
6737 | #endif | |
6738 | } | |
bf2a98b3 | 6739 | |
b9a5aa8e | 6740 | /* Emit the .prologue note at the scheduled end of the prologue. */ |
16b3392b | 6741 | |
85ae73e8 | 6742 | static void |
92643d95 | 6743 | alpha_output_function_end_prologue (FILE *file) |
b9a5aa8e | 6744 | { |
9caef960 | 6745 | if (TARGET_ABI_UNICOSMK) |
6746 | ; | |
6747 | else if (TARGET_ABI_OPEN_VMS) | |
b9a5aa8e | 6748 | fputs ("\t.prologue\n", file); |
1467e953 | 6749 | else if (TARGET_ABI_WINDOWS_NT) |
b9a5aa8e | 6750 | fputs ("\t.prologue 0\n", file); |
6751 | else if (!flag_inhibit_size_directive) | |
961d6ddd | 6752 | fprintf (file, "\t.prologue %d\n", |
6753 | alpha_function_needs_gp || current_function_is_thunk); | |
bf2a98b3 | 6754 | } |
6755 | ||
6756 | /* Write function epilogue. */ | |
6757 | ||
9e7454d0 | 6758 | /* ??? At some point we will want to support full unwind, and so will |
5a965225 | 6759 | need to mark the epilogue as well. At the moment, we just confuse |
6760 | dwarf2out. */ | |
6761 | #undef FRP | |
6762 | #define FRP(exp) exp | |
6763 | ||
bf2a98b3 | 6764 | void |
92643d95 | 6765 | alpha_expand_epilogue (void) |
bf2a98b3 | 6766 | { |
b9a5aa8e | 6767 | /* Registers to save. */ |
6768 | unsigned long imask = 0; | |
6769 | unsigned long fmask = 0; | |
6770 | /* Stack space needed for pushing registers clobbered by us. */ | |
6771 | HOST_WIDE_INT sa_size; | |
6772 | /* Complete stack size needed. */ | |
6773 | HOST_WIDE_INT frame_size; | |
6774 | /* Offset from base reg to register save area. */ | |
6775 | HOST_WIDE_INT reg_offset; | |
6776 | int fp_is_frame_pointer, fp_offset; | |
6777 | rtx sa_reg, sa_reg_exp = NULL; | |
849674a3 | 6778 | rtx sp_adj1, sp_adj2, mem; |
11016d99 | 6779 | rtx eh_ofs; |
bf2a98b3 | 6780 | int i; |
6781 | ||
b9a5aa8e | 6782 | sa_size = alpha_sa_size (); |
bf2a98b3 | 6783 | |
b9a5aa8e | 6784 | frame_size = get_frame_size (); |
1467e953 | 6785 | if (TARGET_ABI_OPEN_VMS) |
9e7454d0 | 6786 | frame_size = ALPHA_ROUND (sa_size |
b19d7ab1 | 6787 | + (alpha_procedure_type == PT_STACK ? 8 : 0) |
b9a5aa8e | 6788 | + frame_size |
6789 | + current_function_pretend_args_size); | |
9caef960 | 6790 | else if (TARGET_ABI_UNICOSMK) |
6791 | frame_size = ALPHA_ROUND (sa_size | |
b19d7ab1 | 6792 | + (alpha_procedure_type == PT_STACK ? 48 : 0)) |
9caef960 | 6793 | + ALPHA_ROUND (frame_size |
6794 | + current_function_outgoing_args_size); | |
b9a5aa8e | 6795 | else |
6796 | frame_size = (ALPHA_ROUND (current_function_outgoing_args_size) | |
6797 | + sa_size | |
6798 | + ALPHA_ROUND (frame_size | |
6799 | + current_function_pretend_args_size)); | |
bf2a98b3 | 6800 | |
1467e953 | 6801 | if (TARGET_ABI_OPEN_VMS) |
b19d7ab1 | 6802 | { |
6803 | if (alpha_procedure_type == PT_STACK) | |
6804 | reg_offset = 8; | |
6805 | else | |
6806 | reg_offset = 0; | |
6807 | } | |
b9a5aa8e | 6808 | else |
6809 | reg_offset = ALPHA_ROUND (current_function_outgoing_args_size); | |
6810 | ||
6811 | alpha_sa_mask (&imask, &fmask); | |
6812 | ||
b19d7ab1 | 6813 | fp_is_frame_pointer |
6814 | = ((TARGET_ABI_OPEN_VMS && alpha_procedure_type == PT_STACK) | |
6815 | || (!TARGET_ABI_OPEN_VMS && frame_pointer_needed)); | |
29768226 | 6816 | fp_offset = 0; |
6817 | sa_reg = stack_pointer_rtx; | |
b9a5aa8e | 6818 | |
c92c328f | 6819 | if (current_function_calls_eh_return) |
6820 | eh_ofs = EH_RETURN_STACKADJ_RTX; | |
6821 | else | |
6822 | eh_ofs = NULL_RTX; | |
6823 | ||
9caef960 | 6824 | if (!TARGET_ABI_UNICOSMK && sa_size) |
b9a5aa8e | 6825 | { |
6826 | /* If we have a frame pointer, restore SP from it. */ | |
1467e953 | 6827 | if ((TARGET_ABI_OPEN_VMS |
b9a5aa8e | 6828 | && vms_unwind_regno == HARD_FRAME_POINTER_REGNUM) |
1467e953 | 6829 | || (!TARGET_ABI_OPEN_VMS && frame_pointer_needed)) |
205b281f | 6830 | FRP (emit_move_insn (stack_pointer_rtx, hard_frame_pointer_rtx)); |
15d5236f | 6831 | |
b9a5aa8e | 6832 | /* Cope with very large offsets to the register save area. */ |
b9a5aa8e | 6833 | if (reg_offset + sa_size > 0x8000) |
bf2a98b3 | 6834 | { |
b9a5aa8e | 6835 | int low = ((reg_offset & 0xffff) ^ 0x8000) - 0x8000; |
6836 | HOST_WIDE_INT bias; | |
6837 | ||
6838 | if (low + sa_size <= 0x8000) | |
6839 | bias = reg_offset - low, reg_offset = low; | |
9e7454d0 | 6840 | else |
b9a5aa8e | 6841 | bias = reg_offset, reg_offset = 0; |
6842 | ||
6843 | sa_reg = gen_rtx_REG (DImode, 22); | |
6844 | sa_reg_exp = plus_constant (stack_pointer_rtx, bias); | |
6845 | ||
5a965225 | 6846 | FRP (emit_move_insn (sa_reg, sa_reg_exp)); |
bf2a98b3 | 6847 | } |
9e7454d0 | 6848 | |
65abff06 | 6849 | /* Restore registers in order, excepting a true frame pointer. */ |
bf2a98b3 | 6850 | |
c92c328f | 6851 | mem = gen_rtx_MEM (DImode, plus_constant (sa_reg, reg_offset)); |
11016d99 | 6852 | if (! eh_ofs) |
ab6ab77e | 6853 | set_mem_alias_set (mem, alpha_sr_alias_set); |
c92c328f | 6854 | FRP (emit_move_insn (gen_rtx_REG (DImode, REG_RA), mem)); |
6855 | ||
b9a5aa8e | 6856 | reg_offset += 8; |
df7d0d23 | 6857 | imask &= ~(1UL << REG_RA); |
16b3392b | 6858 | |
c49ad9ef | 6859 | for (i = 0; i < 31; ++i) |
df7d0d23 | 6860 | if (imask & (1UL << i)) |
bf2a98b3 | 6861 | { |
b9a5aa8e | 6862 | if (i == HARD_FRAME_POINTER_REGNUM && fp_is_frame_pointer) |
16b3392b | 6863 | fp_offset = reg_offset; |
6864 | else | |
b9a5aa8e | 6865 | { |
849674a3 | 6866 | mem = gen_rtx_MEM (DImode, plus_constant(sa_reg, reg_offset)); |
ab6ab77e | 6867 | set_mem_alias_set (mem, alpha_sr_alias_set); |
849674a3 | 6868 | FRP (emit_move_insn (gen_rtx_REG (DImode, i), mem)); |
b9a5aa8e | 6869 | } |
bf2a98b3 | 6870 | reg_offset += 8; |
6871 | } | |
6872 | ||
c49ad9ef | 6873 | if (imask & (1UL << 31)) |
6874 | reg_offset += 8; | |
6875 | ||
6876 | for (i = 0; i < 31; ++i) | |
df7d0d23 | 6877 | if (fmask & (1UL << i)) |
bf2a98b3 | 6878 | { |
849674a3 | 6879 | mem = gen_rtx_MEM (DFmode, plus_constant(sa_reg, reg_offset)); |
ab6ab77e | 6880 | set_mem_alias_set (mem, alpha_sr_alias_set); |
849674a3 | 6881 | FRP (emit_move_insn (gen_rtx_REG (DFmode, i+32), mem)); |
bf2a98b3 | 6882 | reg_offset += 8; |
6883 | } | |
b9a5aa8e | 6884 | } |
b19d7ab1 | 6885 | else if (TARGET_ABI_UNICOSMK && alpha_procedure_type == PT_STACK) |
9caef960 | 6886 | { |
6887 | /* Restore callee-saved general-purpose registers. */ | |
6888 | ||
6889 | reg_offset = -56; | |
6890 | ||
6891 | for (i = 9; i < 15; i++) | |
df7d0d23 | 6892 | if (imask & (1UL << i)) |
9caef960 | 6893 | { |
6894 | mem = gen_rtx_MEM (DImode, plus_constant(hard_frame_pointer_rtx, | |
6895 | reg_offset)); | |
6896 | set_mem_alias_set (mem, alpha_sr_alias_set); | |
6897 | FRP (emit_move_insn (gen_rtx_REG (DImode, i), mem)); | |
6898 | reg_offset -= 8; | |
6899 | } | |
6900 | ||
6901 | for (i = 2; i < 10; i++) | |
df7d0d23 | 6902 | if (fmask & (1UL << i)) |
9caef960 | 6903 | { |
6904 | mem = gen_rtx_MEM (DFmode, plus_constant(hard_frame_pointer_rtx, | |
6905 | reg_offset)); | |
6906 | set_mem_alias_set (mem, alpha_sr_alias_set); | |
6907 | FRP (emit_move_insn (gen_rtx_REG (DFmode, i+32), mem)); | |
6908 | reg_offset -= 8; | |
6909 | } | |
6910 | ||
6911 | /* Restore the return address from the DSIB. */ | |
6912 | ||
6913 | mem = gen_rtx_MEM (DImode, plus_constant(hard_frame_pointer_rtx, -8)); | |
6914 | set_mem_alias_set (mem, alpha_sr_alias_set); | |
6915 | FRP (emit_move_insn (gen_rtx_REG (DImode, REG_RA), mem)); | |
6916 | } | |
bf2a98b3 | 6917 | |
11016d99 | 6918 | if (frame_size || eh_ofs) |
b9a5aa8e | 6919 | { |
ec37ccb4 | 6920 | sp_adj1 = stack_pointer_rtx; |
6921 | ||
11016d99 | 6922 | if (eh_ofs) |
ec37ccb4 | 6923 | { |
6924 | sp_adj1 = gen_rtx_REG (DImode, 23); | |
6925 | emit_move_insn (sp_adj1, | |
11016d99 | 6926 | gen_rtx_PLUS (Pmode, stack_pointer_rtx, eh_ofs)); |
ec37ccb4 | 6927 | } |
6928 | ||
b9a5aa8e | 6929 | /* If the stack size is large, begin computation into a temporary |
6930 | register so as not to interfere with a potential fp restore, | |
6931 | which must be consecutive with an SP restore. */ | |
9caef960 | 6932 | if (frame_size < 32768 |
6933 | && ! (TARGET_ABI_UNICOSMK && current_function_calls_alloca)) | |
ec37ccb4 | 6934 | sp_adj2 = GEN_INT (frame_size); |
9caef960 | 6935 | else if (TARGET_ABI_UNICOSMK) |
6936 | { | |
6937 | sp_adj1 = gen_rtx_REG (DImode, 23); | |
6938 | FRP (emit_move_insn (sp_adj1, hard_frame_pointer_rtx)); | |
6939 | sp_adj2 = const0_rtx; | |
6940 | } | |
b9a5aa8e | 6941 | else if (frame_size < 0x40007fffL) |
6942 | { | |
6943 | int low = ((frame_size & 0xffff) ^ 0x8000) - 0x8000; | |
6944 | ||
ec37ccb4 | 6945 | sp_adj2 = plus_constant (sp_adj1, frame_size - low); |
b9a5aa8e | 6946 | if (sa_reg_exp && rtx_equal_p (sa_reg_exp, sp_adj2)) |
6947 | sp_adj1 = sa_reg; | |
6948 | else | |
6949 | { | |
6950 | sp_adj1 = gen_rtx_REG (DImode, 23); | |
5a965225 | 6951 | FRP (emit_move_insn (sp_adj1, sp_adj2)); |
b9a5aa8e | 6952 | } |
6953 | sp_adj2 = GEN_INT (low); | |
6954 | } | |
0e0a0e7a | 6955 | else |
b9a5aa8e | 6956 | { |
ec37ccb4 | 6957 | rtx tmp = gen_rtx_REG (DImode, 23); |
6958 | FRP (sp_adj2 = alpha_emit_set_const (tmp, DImode, frame_size, 3)); | |
6959 | if (!sp_adj2) | |
b9a5aa8e | 6960 | { |
6961 | /* We can't drop new things to memory this late, afaik, | |
6962 | so build it up by pieces. */ | |
af792316 | 6963 | FRP (sp_adj2 = alpha_emit_set_long_const (tmp, frame_size, |
6964 | -(frame_size < 0))); | |
ec37ccb4 | 6965 | if (!sp_adj2) |
b9a5aa8e | 6966 | abort (); |
b9a5aa8e | 6967 | } |
b9a5aa8e | 6968 | } |
bf2a98b3 | 6969 | |
b9a5aa8e | 6970 | /* From now on, things must be in order. So emit blockages. */ |
6971 | ||
6972 | /* Restore the frame pointer. */ | |
9caef960 | 6973 | if (TARGET_ABI_UNICOSMK) |
6974 | { | |
6975 | emit_insn (gen_blockage ()); | |
6976 | mem = gen_rtx_MEM (DImode, | |
6977 | plus_constant (hard_frame_pointer_rtx, -16)); | |
6978 | set_mem_alias_set (mem, alpha_sr_alias_set); | |
6979 | FRP (emit_move_insn (hard_frame_pointer_rtx, mem)); | |
6980 | } | |
6981 | else if (fp_is_frame_pointer) | |
b9a5aa8e | 6982 | { |
6983 | emit_insn (gen_blockage ()); | |
205b281f | 6984 | mem = gen_rtx_MEM (DImode, plus_constant (sa_reg, fp_offset)); |
ab6ab77e | 6985 | set_mem_alias_set (mem, alpha_sr_alias_set); |
849674a3 | 6986 | FRP (emit_move_insn (hard_frame_pointer_rtx, mem)); |
b9a5aa8e | 6987 | } |
1467e953 | 6988 | else if (TARGET_ABI_OPEN_VMS) |
b9a5aa8e | 6989 | { |
6990 | emit_insn (gen_blockage ()); | |
5a965225 | 6991 | FRP (emit_move_insn (hard_frame_pointer_rtx, |
6992 | gen_rtx_REG (DImode, vms_save_fp_regno))); | |
b9a5aa8e | 6993 | } |
6994 | ||
6995 | /* Restore the stack pointer. */ | |
6996 | emit_insn (gen_blockage ()); | |
9caef960 | 6997 | if (sp_adj2 == const0_rtx) |
6998 | FRP (emit_move_insn (stack_pointer_rtx, sp_adj1)); | |
6999 | else | |
7000 | FRP (emit_move_insn (stack_pointer_rtx, | |
7001 | gen_rtx_PLUS (DImode, sp_adj1, sp_adj2))); | |
b9a5aa8e | 7002 | } |
9e7454d0 | 7003 | else |
b9a5aa8e | 7004 | { |
b19d7ab1 | 7005 | if (TARGET_ABI_OPEN_VMS && alpha_procedure_type == PT_REGISTER) |
b9a5aa8e | 7006 | { |
7007 | emit_insn (gen_blockage ()); | |
5a965225 | 7008 | FRP (emit_move_insn (hard_frame_pointer_rtx, |
7009 | gen_rtx_REG (DImode, vms_save_fp_regno))); | |
b9a5aa8e | 7010 | } |
b19d7ab1 | 7011 | else if (TARGET_ABI_UNICOSMK && alpha_procedure_type != PT_STACK) |
9caef960 | 7012 | { |
7013 | /* Decrement the frame pointer if the function does not have a | |
7014 | frame. */ | |
7015 | ||
7016 | emit_insn (gen_blockage ()); | |
7017 | FRP (emit_insn (gen_adddi3 (hard_frame_pointer_rtx, | |
bcd9bd66 | 7018 | hard_frame_pointer_rtx, constm1_rtx))); |
9caef960 | 7019 | } |
bf2a98b3 | 7020 | } |
b9a5aa8e | 7021 | } |
cf73d31f | 7022 | \f |
b9a5aa8e | 7023 | /* Output the rest of the textual info surrounding the epilogue. */ |
7024 | ||
7025 | void | |
92643d95 | 7026 | alpha_end_function (FILE *file, const char *fnname, tree decl ATTRIBUTE_UNUSED) |
b9a5aa8e | 7027 | { |
04b0d94a | 7028 | #if TARGET_ABI_OPEN_VMS |
7029 | alpha_write_linkage (file, fnname, decl); | |
7030 | #endif | |
7031 | ||
bf2a98b3 | 7032 | /* End the function. */ |
9caef960 | 7033 | if (!TARGET_ABI_UNICOSMK && !flag_inhibit_size_directive) |
f1fe649e | 7034 | { |
b9a5aa8e | 7035 | fputs ("\t.end ", file); |
2cf1388a | 7036 | assemble_name (file, fnname); |
b9a5aa8e | 7037 | putc ('\n', file); |
f1fe649e | 7038 | } |
449b7f2d | 7039 | inside_function = FALSE; |
9c0e5703 | 7040 | |
9caef960 | 7041 | /* Output jump tables and the static subroutine information block. */ |
7042 | if (TARGET_ABI_UNICOSMK) | |
7043 | { | |
7044 | unicosmk_output_ssib (file, fnname); | |
7045 | unicosmk_output_deferred_case_vectors (file); | |
7046 | } | |
bf2a98b3 | 7047 | } |
961d6ddd | 7048 | |
6988553d | 7049 | #if TARGET_ABI_OSF |
7050 | /* Emit a tail call to FUNCTION after adjusting THIS by DELTA. | |
961d6ddd | 7051 | |
7052 | In order to avoid the hordes of differences between generated code | |
7053 | with and without TARGET_EXPLICIT_RELOCS, and to avoid duplicating | |
7054 | lots of code loading up large constants, generate rtl and emit it | |
7055 | instead of going straight to text. | |
7056 | ||
7057 | Not sure why this idea hasn't been explored before... */ | |
7058 | ||
6988553d | 7059 | static void |
92643d95 | 7060 | alpha_output_mi_thunk_osf (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED, |
7061 | HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset, | |
7062 | tree function) | |
961d6ddd | 7063 | { |
7064 | HOST_WIDE_INT hi, lo; | |
7065 | rtx this, insn, funexp; | |
7066 | ||
656047bf | 7067 | reset_block_changes (); |
7068 | ||
961d6ddd | 7069 | /* We always require a valid GP. */ |
7070 | emit_insn (gen_prologue_ldgp ()); | |
31b97e8f | 7071 | emit_note (NOTE_INSN_PROLOGUE_END); |
961d6ddd | 7072 | |
7073 | /* Find the "this" pointer. If the function returns a structure, | |
7074 | the structure return pointer is in $16. */ | |
45550790 | 7075 | if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function)) |
961d6ddd | 7076 | this = gen_rtx_REG (Pmode, 17); |
7077 | else | |
7078 | this = gen_rtx_REG (Pmode, 16); | |
7079 | ||
7080 | /* Add DELTA. When possible we use ldah+lda. Otherwise load the | |
7081 | entire constant for the add. */ | |
7082 | lo = ((delta & 0xffff) ^ 0x8000) - 0x8000; | |
7083 | hi = (((delta - lo) & 0xffffffff) ^ 0x80000000) - 0x80000000; | |
7084 | if (hi + lo == delta) | |
7085 | { | |
7086 | if (hi) | |
7087 | emit_insn (gen_adddi3 (this, this, GEN_INT (hi))); | |
7088 | if (lo) | |
7089 | emit_insn (gen_adddi3 (this, this, GEN_INT (lo))); | |
7090 | } | |
7091 | else | |
7092 | { | |
7093 | rtx tmp = alpha_emit_set_long_const (gen_rtx_REG (Pmode, 0), | |
7094 | delta, -(delta < 0)); | |
7095 | emit_insn (gen_adddi3 (this, this, tmp)); | |
7096 | } | |
7097 | ||
a19ec9da | 7098 | /* Add a delta stored in the vtable at VCALL_OFFSET. */ |
7099 | if (vcall_offset) | |
7100 | { | |
7101 | rtx tmp, tmp2; | |
7102 | ||
7103 | tmp = gen_rtx_REG (Pmode, 0); | |
7104 | emit_move_insn (tmp, gen_rtx_MEM (Pmode, this)); | |
7105 | ||
7106 | lo = ((vcall_offset & 0xffff) ^ 0x8000) - 0x8000; | |
7107 | hi = (((vcall_offset - lo) & 0xffffffff) ^ 0x80000000) - 0x80000000; | |
7108 | if (hi + lo == vcall_offset) | |
7109 | { | |
7110 | if (hi) | |
7111 | emit_insn (gen_adddi3 (tmp, tmp, GEN_INT (hi))); | |
7112 | } | |
7113 | else | |
7114 | { | |
7115 | tmp2 = alpha_emit_set_long_const (gen_rtx_REG (Pmode, 1), | |
7116 | vcall_offset, -(vcall_offset < 0)); | |
7117 | emit_insn (gen_adddi3 (tmp, tmp, tmp2)); | |
7118 | lo = 0; | |
7119 | } | |
7120 | if (lo) | |
7121 | tmp2 = gen_rtx_PLUS (Pmode, tmp, GEN_INT (lo)); | |
7122 | else | |
7123 | tmp2 = tmp; | |
7124 | emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp2)); | |
7125 | ||
7126 | emit_insn (gen_adddi3 (this, this, tmp)); | |
7127 | } | |
7128 | ||
961d6ddd | 7129 | /* Generate a tail call to the target function. */ |
7130 | if (! TREE_USED (function)) | |
7131 | { | |
7132 | assemble_external (function); | |
7133 | TREE_USED (function) = 1; | |
7134 | } | |
7135 | funexp = XEXP (DECL_RTL (function), 0); | |
7136 | funexp = gen_rtx_MEM (FUNCTION_MODE, funexp); | |
7137 | insn = emit_call_insn (gen_sibcall (funexp, const0_rtx)); | |
7138 | SIBLING_CALL_P (insn) = 1; | |
7139 | ||
7140 | /* Run just enough of rest_of_compilation to get the insns emitted. | |
7141 | There's not really enough bulk here to make other passes such as | |
7142 | instruction scheduling worth while. Note that use_thunk calls | |
7143 | assemble_start_function and assemble_end_function. */ | |
7144 | insn = get_insns (); | |
50494502 | 7145 | insn_locators_initialize (); |
961d6ddd | 7146 | shorten_branches (insn); |
7147 | final_start_function (insn, file, 1); | |
7148 | final (insn, file, 1, 0); | |
7149 | final_end_function (); | |
7150 | } | |
6988553d | 7151 | #endif /* TARGET_ABI_OSF */ |
449b7f2d | 7152 | \f |
7153 | /* Debugging support. */ | |
7154 | ||
7155 | #include "gstab.h" | |
7156 | ||
7157 | /* Count the number of sdb related labels are generated (to find block | |
7158 | start and end boundaries). */ | |
7159 | ||
7160 | int sdb_label_count = 0; | |
7161 | ||
7162 | /* Next label # for each statement. */ | |
7163 | ||
7164 | static int sym_lineno = 0; | |
7165 | ||
7166 | /* Count the number of .file directives, so that .loc is up to date. */ | |
7167 | ||
7168 | static int num_source_filenames = 0; | |
7169 | ||
7170 | /* Name of the file containing the current function. */ | |
7171 | ||
ace75b22 | 7172 | static const char *current_function_file = ""; |
449b7f2d | 7173 | |
7174 | /* Offsets to alpha virtual arg/local debugging pointers. */ | |
7175 | ||
7176 | long alpha_arg_offset; | |
7177 | long alpha_auto_offset; | |
7178 | \f | |
7179 | /* Emit a new filename to a stream. */ | |
7180 | ||
7181 | void | |
92643d95 | 7182 | alpha_output_filename (FILE *stream, const char *name) |
449b7f2d | 7183 | { |
7184 | static int first_time = TRUE; | |
7185 | char ltext_label_name[100]; | |
7186 | ||
7187 | if (first_time) | |
7188 | { | |
7189 | first_time = FALSE; | |
7190 | ++num_source_filenames; | |
7191 | current_function_file = name; | |
7192 | fprintf (stream, "\t.file\t%d ", num_source_filenames); | |
7193 | output_quoted_string (stream, name); | |
7194 | fprintf (stream, "\n"); | |
7195 | if (!TARGET_GAS && write_symbols == DBX_DEBUG) | |
7196 | fprintf (stream, "\t#@stabs\n"); | |
7197 | } | |
7198 | ||
8763f243 | 7199 | else if (write_symbols == DBX_DEBUG) |
449b7f2d | 7200 | { |
7201 | ASM_GENERATE_INTERNAL_LABEL (ltext_label_name, "Ltext", 0); | |
95d655c3 | 7202 | fprintf (stream, "%s", ASM_STABS_OP); |
449b7f2d | 7203 | output_quoted_string (stream, name); |
7204 | fprintf (stream, ",%d,0,0,%s\n", N_SOL, <ext_label_name[1]); | |
7205 | } | |
7206 | ||
7207 | else if (name != current_function_file | |
be3797c1 | 7208 | && strcmp (name, current_function_file) != 0) |
449b7f2d | 7209 | { |
7210 | if (inside_function && ! TARGET_GAS) | |
7211 | fprintf (stream, "\t#.file\t%d ", num_source_filenames); | |
7212 | else | |
7213 | { | |
7214 | ++num_source_filenames; | |
7215 | current_function_file = name; | |
7216 | fprintf (stream, "\t.file\t%d ", num_source_filenames); | |
7217 | } | |
7218 | ||
7219 | output_quoted_string (stream, name); | |
7220 | fprintf (stream, "\n"); | |
7221 | } | |
7222 | } | |
92643d95 | 7223 | |
449b7f2d | 7224 | /* Emit a linenumber to a stream. */ |
7225 | ||
7226 | void | |
92643d95 | 7227 | alpha_output_lineno (FILE *stream, int line) |
449b7f2d | 7228 | { |
8763f243 | 7229 | if (write_symbols == DBX_DEBUG) |
449b7f2d | 7230 | { |
7231 | /* mips-tfile doesn't understand .stabd directives. */ | |
7232 | ++sym_lineno; | |
95d655c3 | 7233 | fprintf (stream, "$LM%d:\n%s%d,0,%d,$LM%d\n", |
449b7f2d | 7234 | sym_lineno, ASM_STABN_OP, N_SLINE, line, sym_lineno); |
7235 | } | |
7236 | else | |
cffb5069 | 7237 | fprintf (stream, "\n\t.loc\t%d %d\n", num_source_filenames, line); |
449b7f2d | 7238 | } |
c4622276 | 7239 | \f |
7240 | /* Structure to show the current status of registers and memory. */ | |
7241 | ||
7242 | struct shadow_summary | |
7243 | { | |
7244 | struct { | |
495c4a78 | 7245 | unsigned int i : 31; /* Mask of int regs */ |
7246 | unsigned int fp : 31; /* Mask of fp regs */ | |
7247 | unsigned int mem : 1; /* mem == imem | fpmem */ | |
c4622276 | 7248 | } used, defd; |
7249 | }; | |
7250 | ||
7251 | /* Summary the effects of expression X on the machine. Update SUM, a pointer | |
7252 | to the summary structure. SET is nonzero if the insn is setting the | |
7253 | object, otherwise zero. */ | |
7254 | ||
7255 | static void | |
92643d95 | 7256 | summarize_insn (rtx x, struct shadow_summary *sum, int set) |
c4622276 | 7257 | { |
d2ca078f | 7258 | const char *format_ptr; |
c4622276 | 7259 | int i, j; |
7260 | ||
7261 | if (x == 0) | |
7262 | return; | |
7263 | ||
7264 | switch (GET_CODE (x)) | |
7265 | { | |
7266 | /* ??? Note that this case would be incorrect if the Alpha had a | |
7267 | ZERO_EXTRACT in SET_DEST. */ | |
7268 | case SET: | |
7269 | summarize_insn (SET_SRC (x), sum, 0); | |
7270 | summarize_insn (SET_DEST (x), sum, 1); | |
7271 | break; | |
7272 | ||
7273 | case CLOBBER: | |
7274 | summarize_insn (XEXP (x, 0), sum, 1); | |
7275 | break; | |
7276 | ||
7277 | case USE: | |
7278 | summarize_insn (XEXP (x, 0), sum, 0); | |
7279 | break; | |
7280 | ||
a886cc41 | 7281 | case ASM_OPERANDS: |
7282 | for (i = ASM_OPERANDS_INPUT_LENGTH (x) - 1; i >= 0; i--) | |
7283 | summarize_insn (ASM_OPERANDS_INPUT (x, i), sum, 0); | |
7284 | break; | |
7285 | ||
c4622276 | 7286 | case PARALLEL: |
3a5dbb5e | 7287 | for (i = XVECLEN (x, 0) - 1; i >= 0; i--) |
c4622276 | 7288 | summarize_insn (XVECEXP (x, 0, i), sum, 0); |
7289 | break; | |
7290 | ||
a886cc41 | 7291 | case SUBREG: |
b9a5aa8e | 7292 | summarize_insn (SUBREG_REG (x), sum, 0); |
7293 | break; | |
a886cc41 | 7294 | |
c4622276 | 7295 | case REG: |
7296 | { | |
7297 | int regno = REGNO (x); | |
f3d263a7 | 7298 | unsigned long mask = ((unsigned long) 1) << (regno % 32); |
c4622276 | 7299 | |
7300 | if (regno == 31 || regno == 63) | |
7301 | break; | |
7302 | ||
7303 | if (set) | |
7304 | { | |
7305 | if (regno < 32) | |
7306 | sum->defd.i |= mask; | |
7307 | else | |
7308 | sum->defd.fp |= mask; | |
7309 | } | |
7310 | else | |
7311 | { | |
7312 | if (regno < 32) | |
7313 | sum->used.i |= mask; | |
7314 | else | |
7315 | sum->used.fp |= mask; | |
7316 | } | |
7317 | } | |
7318 | break; | |
7319 | ||
7320 | case MEM: | |
7321 | if (set) | |
7322 | sum->defd.mem = 1; | |
7323 | else | |
7324 | sum->used.mem = 1; | |
7325 | ||
7326 | /* Find the regs used in memory address computation: */ | |
7327 | summarize_insn (XEXP (x, 0), sum, 0); | |
7328 | break; | |
7329 | ||
2d710b28 | 7330 | case CONST_INT: case CONST_DOUBLE: |
7331 | case SYMBOL_REF: case LABEL_REF: case CONST: | |
5bdbf614 | 7332 | case SCRATCH: case ASM_INPUT: |
2d710b28 | 7333 | break; |
7334 | ||
c4622276 | 7335 | /* Handle common unary and binary ops for efficiency. */ |
7336 | case COMPARE: case PLUS: case MINUS: case MULT: case DIV: | |
7337 | case MOD: case UDIV: case UMOD: case AND: case IOR: | |
7338 | case XOR: case ASHIFT: case ROTATE: case ASHIFTRT: case LSHIFTRT: | |
7339 | case ROTATERT: case SMIN: case SMAX: case UMIN: case UMAX: | |
7340 | case NE: case EQ: case GE: case GT: case LE: | |
7341 | case LT: case GEU: case GTU: case LEU: case LTU: | |
7342 | summarize_insn (XEXP (x, 0), sum, 0); | |
7343 | summarize_insn (XEXP (x, 1), sum, 0); | |
7344 | break; | |
7345 | ||
7346 | case NEG: case NOT: case SIGN_EXTEND: case ZERO_EXTEND: | |
7347 | case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE: case FLOAT: | |
7348 | case FIX: case UNSIGNED_FLOAT: case UNSIGNED_FIX: case ABS: | |
9e7454d0 | 7349 | case SQRT: case FFS: |
c4622276 | 7350 | summarize_insn (XEXP (x, 0), sum, 0); |
7351 | break; | |
7352 | ||
7353 | default: | |
7354 | format_ptr = GET_RTX_FORMAT (GET_CODE (x)); | |
3a5dbb5e | 7355 | for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--) |
cada32d3 | 7356 | switch (format_ptr[i]) |
c4622276 | 7357 | { |
7358 | case 'e': | |
7359 | summarize_insn (XEXP (x, i), sum, 0); | |
7360 | break; | |
7361 | ||
7362 | case 'E': | |
3a5dbb5e | 7363 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) |
c4622276 | 7364 | summarize_insn (XVECEXP (x, i, j), sum, 0); |
7365 | break; | |
7366 | ||
1dc5f36f | 7367 | case 'i': |
7368 | break; | |
7369 | ||
c4622276 | 7370 | default: |
7371 | abort (); | |
7372 | } | |
7373 | } | |
7374 | } | |
c4622276 | 7375 | |
b9a5aa8e | 7376 | /* Ensure a sufficient number of `trapb' insns are in the code when |
7377 | the user requests code with a trap precision of functions or | |
7378 | instructions. | |
7379 | ||
7380 | In naive mode, when the user requests a trap-precision of | |
7381 | "instruction", a trapb is needed after every instruction that may | |
7382 | generate a trap. This ensures that the code is resumption safe but | |
7383 | it is also slow. | |
7384 | ||
7385 | When optimizations are turned on, we delay issuing a trapb as long | |
7386 | as possible. In this context, a trap shadow is the sequence of | |
7387 | instructions that starts with a (potentially) trap generating | |
7388 | instruction and extends to the next trapb or call_pal instruction | |
7389 | (but GCC never generates call_pal by itself). We can delay (and | |
7390 | therefore sometimes omit) a trapb subject to the following | |
7391 | conditions: | |
7392 | ||
7393 | (a) On entry to the trap shadow, if any Alpha register or memory | |
7394 | location contains a value that is used as an operand value by some | |
7395 | instruction in the trap shadow (live on entry), then no instruction | |
7396 | in the trap shadow may modify the register or memory location. | |
7397 | ||
7398 | (b) Within the trap shadow, the computation of the base register | |
7399 | for a memory load or store instruction may not involve using the | |
7400 | result of an instruction that might generate an UNPREDICTABLE | |
7401 | result. | |
7402 | ||
7403 | (c) Within the trap shadow, no register may be used more than once | |
7404 | as a destination register. (This is to make life easier for the | |
7405 | trap-handler.) | |
c4622276 | 7406 | |
18adf4f6 | 7407 | (d) The trap shadow may not include any branch instructions. */ |
c4622276 | 7408 | |
18adf4f6 | 7409 | static void |
92643d95 | 7410 | alpha_handle_trap_shadows (void) |
c4622276 | 7411 | { |
18adf4f6 | 7412 | struct shadow_summary shadow; |
7413 | int trap_pending, exception_nesting; | |
b9b4428b | 7414 | rtx i, n; |
c4622276 | 7415 | |
18adf4f6 | 7416 | trap_pending = 0; |
7417 | exception_nesting = 0; | |
7418 | shadow.used.i = 0; | |
7419 | shadow.used.fp = 0; | |
7420 | shadow.used.mem = 0; | |
7421 | shadow.defd = shadow.used; | |
9e7454d0 | 7422 | |
2efea8c0 | 7423 | for (i = get_insns (); i ; i = NEXT_INSN (i)) |
18adf4f6 | 7424 | { |
7425 | if (GET_CODE (i) == NOTE) | |
7426 | { | |
7427 | switch (NOTE_LINE_NUMBER (i)) | |
7428 | { | |
7429 | case NOTE_INSN_EH_REGION_BEG: | |
7430 | exception_nesting++; | |
7431 | if (trap_pending) | |
7432 | goto close_shadow; | |
7433 | break; | |
7434 | ||
7435 | case NOTE_INSN_EH_REGION_END: | |
7436 | exception_nesting--; | |
7437 | if (trap_pending) | |
7438 | goto close_shadow; | |
7439 | break; | |
7440 | ||
7441 | case NOTE_INSN_EPILOGUE_BEG: | |
7442 | if (trap_pending && alpha_tp >= ALPHA_TP_FUNC) | |
7443 | goto close_shadow; | |
7444 | break; | |
7445 | } | |
7446 | } | |
7447 | else if (trap_pending) | |
7448 | { | |
7449 | if (alpha_tp == ALPHA_TP_FUNC) | |
7450 | { | |
7451 | if (GET_CODE (i) == JUMP_INSN | |
7452 | && GET_CODE (PATTERN (i)) == RETURN) | |
7453 | goto close_shadow; | |
7454 | } | |
7455 | else if (alpha_tp == ALPHA_TP_INSN) | |
7456 | { | |
7457 | if (optimize > 0) | |
7458 | { | |
7459 | struct shadow_summary sum; | |
7460 | ||
7461 | sum.used.i = 0; | |
7462 | sum.used.fp = 0; | |
7463 | sum.used.mem = 0; | |
a886cc41 | 7464 | sum.defd = sum.used; |
18adf4f6 | 7465 | |
7466 | switch (GET_CODE (i)) | |
7467 | { | |
7468 | case INSN: | |
fad0a39b | 7469 | /* Annoyingly, get_attr_trap will abort on these. */ |
7470 | if (GET_CODE (PATTERN (i)) == USE | |
7471 | || GET_CODE (PATTERN (i)) == CLOBBER) | |
18adf4f6 | 7472 | break; |
7473 | ||
7474 | summarize_insn (PATTERN (i), &sum, 0); | |
7475 | ||
7476 | if ((sum.defd.i & shadow.defd.i) | |
7477 | || (sum.defd.fp & shadow.defd.fp)) | |
7478 | { | |
7479 | /* (c) would be violated */ | |
7480 | goto close_shadow; | |
7481 | } | |
7482 | ||
7483 | /* Combine shadow with summary of current insn: */ | |
7484 | shadow.used.i |= sum.used.i; | |
7485 | shadow.used.fp |= sum.used.fp; | |
7486 | shadow.used.mem |= sum.used.mem; | |
7487 | shadow.defd.i |= sum.defd.i; | |
7488 | shadow.defd.fp |= sum.defd.fp; | |
7489 | shadow.defd.mem |= sum.defd.mem; | |
7490 | ||
7491 | if ((sum.defd.i & shadow.used.i) | |
7492 | || (sum.defd.fp & shadow.used.fp) | |
7493 | || (sum.defd.mem & shadow.used.mem)) | |
7494 | { | |
7495 | /* (a) would be violated (also takes care of (b)) */ | |
7496 | if (get_attr_trap (i) == TRAP_YES | |
7497 | && ((sum.defd.i & sum.used.i) | |
7498 | || (sum.defd.fp & sum.used.fp))) | |
7499 | abort (); | |
7500 | ||
7501 | goto close_shadow; | |
7502 | } | |
7503 | break; | |
7504 | ||
7505 | case JUMP_INSN: | |
7506 | case CALL_INSN: | |
7507 | case CODE_LABEL: | |
7508 | goto close_shadow; | |
7509 | ||
7510 | default: | |
c4622276 | 7511 | abort (); |
18adf4f6 | 7512 | } |
7513 | } | |
7514 | else | |
7515 | { | |
7516 | close_shadow: | |
b9b4428b | 7517 | n = emit_insn_before (gen_trapb (), i); |
7518 | PUT_MODE (n, TImode); | |
7519 | PUT_MODE (i, TImode); | |
18adf4f6 | 7520 | trap_pending = 0; |
7521 | shadow.used.i = 0; | |
7522 | shadow.used.fp = 0; | |
7523 | shadow.used.mem = 0; | |
7524 | shadow.defd = shadow.used; | |
7525 | } | |
7526 | } | |
7527 | } | |
c4622276 | 7528 | |
609d4083 | 7529 | if ((exception_nesting > 0 || alpha_tp >= ALPHA_TP_FUNC) |
7530 | && GET_CODE (i) == INSN | |
7531 | && GET_CODE (PATTERN (i)) != USE | |
7532 | && GET_CODE (PATTERN (i)) != CLOBBER | |
7533 | && get_attr_trap (i) == TRAP_YES) | |
7534 | { | |
7535 | if (optimize && !trap_pending) | |
7536 | summarize_insn (PATTERN (i), &shadow, 0); | |
7537 | trap_pending = 1; | |
7538 | } | |
c4622276 | 7539 | } |
7540 | } | |
b9b4428b | 7541 | \f |
b9b4428b | 7542 | /* Alpha can only issue instruction groups simultaneously if they are |
5910bb95 | 7543 | suitably aligned. This is very processor-specific. */ |
b9b4428b | 7544 | |
849674a3 | 7545 | enum alphaev4_pipe { |
7546 | EV4_STOP = 0, | |
7547 | EV4_IB0 = 1, | |
7548 | EV4_IB1 = 2, | |
7549 | EV4_IBX = 4 | |
7550 | }; | |
7551 | ||
b9b4428b | 7552 | enum alphaev5_pipe { |
7553 | EV5_STOP = 0, | |
7554 | EV5_NONE = 1, | |
7555 | EV5_E01 = 2, | |
7556 | EV5_E0 = 4, | |
7557 | EV5_E1 = 8, | |
7558 | EV5_FAM = 16, | |
7559 | EV5_FA = 32, | |
7560 | EV5_FM = 64 | |
7561 | }; | |
7562 | ||
849674a3 | 7563 | static enum alphaev4_pipe |
92643d95 | 7564 | alphaev4_insn_pipe (rtx insn) |
849674a3 | 7565 | { |
7566 | if (recog_memoized (insn) < 0) | |
7567 | return EV4_STOP; | |
7568 | if (get_attr_length (insn) != 4) | |
7569 | return EV4_STOP; | |
7570 | ||
7571 | switch (get_attr_type (insn)) | |
7572 | { | |
7573 | case TYPE_ILD: | |
7574 | case TYPE_FLD: | |
7575 | return EV4_IBX; | |
7576 | ||
7577 | case TYPE_LDSYM: | |
7578 | case TYPE_IADD: | |
7579 | case TYPE_ILOG: | |
7580 | case TYPE_ICMOV: | |
7581 | case TYPE_ICMP: | |
7582 | case TYPE_IST: | |
7583 | case TYPE_FST: | |
7584 | case TYPE_SHIFT: | |
7585 | case TYPE_IMUL: | |
7586 | case TYPE_FBR: | |
7587 | return EV4_IB0; | |
7588 | ||
7589 | case TYPE_MISC: | |
7590 | case TYPE_IBR: | |
7591 | case TYPE_JSR: | |
1050b77e | 7592 | case TYPE_CALLPAL: |
849674a3 | 7593 | case TYPE_FCPYS: |
7594 | case TYPE_FCMOV: | |
7595 | case TYPE_FADD: | |
7596 | case TYPE_FDIV: | |
7597 | case TYPE_FMUL: | |
7598 | return EV4_IB1; | |
7599 | ||
7600 | default: | |
b53f315c | 7601 | abort (); |
849674a3 | 7602 | } |
7603 | } | |
7604 | ||
b9b4428b | 7605 | static enum alphaev5_pipe |
92643d95 | 7606 | alphaev5_insn_pipe (rtx insn) |
b9b4428b | 7607 | { |
7608 | if (recog_memoized (insn) < 0) | |
7609 | return EV5_STOP; | |
7610 | if (get_attr_length (insn) != 4) | |
7611 | return EV5_STOP; | |
7612 | ||
7613 | switch (get_attr_type (insn)) | |
7614 | { | |
7615 | case TYPE_ILD: | |
7616 | case TYPE_FLD: | |
7617 | case TYPE_LDSYM: | |
7618 | case TYPE_IADD: | |
7619 | case TYPE_ILOG: | |
7620 | case TYPE_ICMOV: | |
7621 | case TYPE_ICMP: | |
7622 | return EV5_E01; | |
7623 | ||
7624 | case TYPE_IST: | |
7625 | case TYPE_FST: | |
7626 | case TYPE_SHIFT: | |
7627 | case TYPE_IMUL: | |
7628 | case TYPE_MISC: | |
7629 | case TYPE_MVI: | |
7630 | return EV5_E0; | |
7631 | ||
7632 | case TYPE_IBR: | |
7633 | case TYPE_JSR: | |
1050b77e | 7634 | case TYPE_CALLPAL: |
b9b4428b | 7635 | return EV5_E1; |
7636 | ||
7637 | case TYPE_FCPYS: | |
7638 | return EV5_FAM; | |
7639 | ||
7640 | case TYPE_FBR: | |
7641 | case TYPE_FCMOV: | |
7642 | case TYPE_FADD: | |
7643 | case TYPE_FDIV: | |
7644 | return EV5_FA; | |
7645 | ||
7646 | case TYPE_FMUL: | |
7647 | return EV5_FM; | |
ddca68f8 | 7648 | |
7649 | default: | |
7650 | abort(); | |
b9b4428b | 7651 | } |
b9b4428b | 7652 | } |
7653 | ||
9e7454d0 | 7654 | /* IN_USE is a mask of the slots currently filled within the insn group. |
849674a3 | 7655 | The mask bits come from alphaev4_pipe above. If EV4_IBX is set, then |
9e7454d0 | 7656 | the insn in EV4_IB0 can be swapped by the hardware into EV4_IB1. |
849674a3 | 7657 | |
7658 | LEN is, of course, the length of the group in bytes. */ | |
7659 | ||
7660 | static rtx | |
92643d95 | 7661 | alphaev4_next_group (rtx insn, int *pin_use, int *plen) |
849674a3 | 7662 | { |
7663 | int len, in_use; | |
7664 | ||
7665 | len = in_use = 0; | |
7666 | ||
9204e736 | 7667 | if (! INSN_P (insn) |
849674a3 | 7668 | || GET_CODE (PATTERN (insn)) == CLOBBER |
7669 | || GET_CODE (PATTERN (insn)) == USE) | |
7670 | goto next_and_done; | |
7671 | ||
7672 | while (1) | |
7673 | { | |
7674 | enum alphaev4_pipe pipe; | |
7675 | ||
7676 | pipe = alphaev4_insn_pipe (insn); | |
7677 | switch (pipe) | |
7678 | { | |
7679 | case EV4_STOP: | |
7680 | /* Force complex instructions to start new groups. */ | |
7681 | if (in_use) | |
7682 | goto done; | |
7683 | ||
7684 | /* If this is a completely unrecognized insn, its an asm. | |
7685 | We don't know how long it is, so record length as -1 to | |
7686 | signal a needed realignment. */ | |
7687 | if (recog_memoized (insn) < 0) | |
7688 | len = -1; | |
7689 | else | |
7690 | len = get_attr_length (insn); | |
7691 | goto next_and_done; | |
7692 | ||
7693 | case EV4_IBX: | |
7694 | if (in_use & EV4_IB0) | |
7695 | { | |
7696 | if (in_use & EV4_IB1) | |
7697 | goto done; | |
7698 | in_use |= EV4_IB1; | |
7699 | } | |
7700 | else | |
7701 | in_use |= EV4_IB0 | EV4_IBX; | |
7702 | break; | |
7703 | ||
7704 | case EV4_IB0: | |
7705 | if (in_use & EV4_IB0) | |
7706 | { | |
7707 | if (!(in_use & EV4_IBX) || (in_use & EV4_IB1)) | |
7708 | goto done; | |
7709 | in_use |= EV4_IB1; | |
7710 | } | |
7711 | in_use |= EV4_IB0; | |
7712 | break; | |
7713 | ||
7714 | case EV4_IB1: | |
7715 | if (in_use & EV4_IB1) | |
7716 | goto done; | |
7717 | in_use |= EV4_IB1; | |
7718 | break; | |
7719 | ||
7720 | default: | |
7721 | abort(); | |
7722 | } | |
7723 | len += 4; | |
9e7454d0 | 7724 | |
849674a3 | 7725 | /* Haifa doesn't do well scheduling branches. */ |
7726 | if (GET_CODE (insn) == JUMP_INSN) | |
7727 | goto next_and_done; | |
7728 | ||
7729 | next: | |
7730 | insn = next_nonnote_insn (insn); | |
7731 | ||
9204e736 | 7732 | if (!insn || ! INSN_P (insn)) |
849674a3 | 7733 | goto done; |
7734 | ||
7735 | /* Let Haifa tell us where it thinks insn group boundaries are. */ | |
7736 | if (GET_MODE (insn) == TImode) | |
7737 | goto done; | |
7738 | ||
7739 | if (GET_CODE (insn) == CLOBBER || GET_CODE (insn) == USE) | |
7740 | goto next; | |
7741 | } | |
7742 | ||
7743 | next_and_done: | |
7744 | insn = next_nonnote_insn (insn); | |
7745 | ||
7746 | done: | |
7747 | *plen = len; | |
7748 | *pin_use = in_use; | |
7749 | return insn; | |
7750 | } | |
7751 | ||
9e7454d0 | 7752 | /* IN_USE is a mask of the slots currently filled within the insn group. |
849674a3 | 7753 | The mask bits come from alphaev5_pipe above. If EV5_E01 is set, then |
9e7454d0 | 7754 | the insn in EV5_E0 can be swapped by the hardware into EV5_E1. |
b9b4428b | 7755 | |
7756 | LEN is, of course, the length of the group in bytes. */ | |
7757 | ||
7758 | static rtx | |
92643d95 | 7759 | alphaev5_next_group (rtx insn, int *pin_use, int *plen) |
b9b4428b | 7760 | { |
7761 | int len, in_use; | |
7762 | ||
7763 | len = in_use = 0; | |
7764 | ||
9204e736 | 7765 | if (! INSN_P (insn) |
ddca68f8 | 7766 | || GET_CODE (PATTERN (insn)) == CLOBBER |
7767 | || GET_CODE (PATTERN (insn)) == USE) | |
7768 | goto next_and_done; | |
b9b4428b | 7769 | |
ddca68f8 | 7770 | while (1) |
b9b4428b | 7771 | { |
7772 | enum alphaev5_pipe pipe; | |
b9b4428b | 7773 | |
7774 | pipe = alphaev5_insn_pipe (insn); | |
7775 | switch (pipe) | |
7776 | { | |
7777 | case EV5_STOP: | |
7778 | /* Force complex instructions to start new groups. */ | |
7779 | if (in_use) | |
7780 | goto done; | |
7781 | ||
7782 | /* If this is a completely unrecognized insn, its an asm. | |
7783 | We don't know how long it is, so record length as -1 to | |
7784 | signal a needed realignment. */ | |
7785 | if (recog_memoized (insn) < 0) | |
7786 | len = -1; | |
7787 | else | |
7788 | len = get_attr_length (insn); | |
ddca68f8 | 7789 | goto next_and_done; |
b9b4428b | 7790 | |
9e7454d0 | 7791 | /* ??? Most of the places below, we would like to abort, as |
7792 | it would indicate an error either in Haifa, or in the | |
7793 | scheduling description. Unfortunately, Haifa never | |
b9b4428b | 7794 | schedules the last instruction of the BB, so we don't |
7795 | have an accurate TI bit to go off. */ | |
7796 | case EV5_E01: | |
7797 | if (in_use & EV5_E0) | |
7798 | { | |
7799 | if (in_use & EV5_E1) | |
7800 | goto done; | |
7801 | in_use |= EV5_E1; | |
7802 | } | |
7803 | else | |
7804 | in_use |= EV5_E0 | EV5_E01; | |
7805 | break; | |
7806 | ||
7807 | case EV5_E0: | |
7808 | if (in_use & EV5_E0) | |
7809 | { | |
849674a3 | 7810 | if (!(in_use & EV5_E01) || (in_use & EV5_E1)) |
b9b4428b | 7811 | goto done; |
7812 | in_use |= EV5_E1; | |
7813 | } | |
7814 | in_use |= EV5_E0; | |
7815 | break; | |
7816 | ||
7817 | case EV5_E1: | |
7818 | if (in_use & EV5_E1) | |
7819 | goto done; | |
7820 | in_use |= EV5_E1; | |
7821 | break; | |
7822 | ||
7823 | case EV5_FAM: | |
7824 | if (in_use & EV5_FA) | |
7825 | { | |
7826 | if (in_use & EV5_FM) | |
7827 | goto done; | |
7828 | in_use |= EV5_FM; | |
7829 | } | |
7830 | else | |
7831 | in_use |= EV5_FA | EV5_FAM; | |
7832 | break; | |
7833 | ||
7834 | case EV5_FA: | |
7835 | if (in_use & EV5_FA) | |
7836 | goto done; | |
7837 | in_use |= EV5_FA; | |
7838 | break; | |
7839 | ||
7840 | case EV5_FM: | |
7841 | if (in_use & EV5_FM) | |
7842 | goto done; | |
7843 | in_use |= EV5_FM; | |
7844 | break; | |
7845 | ||
7846 | case EV5_NONE: | |
7847 | break; | |
7848 | ||
7849 | default: | |
7850 | abort(); | |
7851 | } | |
7852 | len += 4; | |
9e7454d0 | 7853 | |
b9b4428b | 7854 | /* Haifa doesn't do well scheduling branches. */ |
7855 | /* ??? If this is predicted not-taken, slotting continues, except | |
7856 | that no more IBR, FBR, or JSR insns may be slotted. */ | |
7857 | if (GET_CODE (insn) == JUMP_INSN) | |
ddca68f8 | 7858 | goto next_and_done; |
b9b4428b | 7859 | |
ddca68f8 | 7860 | next: |
b9b4428b | 7861 | insn = next_nonnote_insn (insn); |
7862 | ||
9204e736 | 7863 | if (!insn || ! INSN_P (insn)) |
b9b4428b | 7864 | goto done; |
f9137da0 | 7865 | |
b9b4428b | 7866 | /* Let Haifa tell us where it thinks insn group boundaries are. */ |
7867 | if (GET_MODE (insn) == TImode) | |
7868 | goto done; | |
7869 | ||
ddca68f8 | 7870 | if (GET_CODE (insn) == CLOBBER || GET_CODE (insn) == USE) |
7871 | goto next; | |
b9b4428b | 7872 | } |
ddca68f8 | 7873 | |
7874 | next_and_done: | |
7875 | insn = next_nonnote_insn (insn); | |
b9b4428b | 7876 | |
7877 | done: | |
7878 | *plen = len; | |
7879 | *pin_use = in_use; | |
7880 | return insn; | |
b9b4428b | 7881 | } |
7882 | ||
849674a3 | 7883 | static rtx |
92643d95 | 7884 | alphaev4_next_nop (int *pin_use) |
849674a3 | 7885 | { |
7886 | int in_use = *pin_use; | |
7887 | rtx nop; | |
7888 | ||
7889 | if (!(in_use & EV4_IB0)) | |
7890 | { | |
7891 | in_use |= EV4_IB0; | |
7892 | nop = gen_nop (); | |
7893 | } | |
7894 | else if ((in_use & (EV4_IBX|EV4_IB1)) == EV4_IBX) | |
7895 | { | |
7896 | in_use |= EV4_IB1; | |
7897 | nop = gen_nop (); | |
7898 | } | |
7899 | else if (TARGET_FP && !(in_use & EV4_IB1)) | |
7900 | { | |
7901 | in_use |= EV4_IB1; | |
7902 | nop = gen_fnop (); | |
7903 | } | |
7904 | else | |
7905 | nop = gen_unop (); | |
7906 | ||
7907 | *pin_use = in_use; | |
7908 | return nop; | |
7909 | } | |
7910 | ||
7911 | static rtx | |
92643d95 | 7912 | alphaev5_next_nop (int *pin_use) |
849674a3 | 7913 | { |
7914 | int in_use = *pin_use; | |
7915 | rtx nop; | |
7916 | ||
7917 | if (!(in_use & EV5_E1)) | |
7918 | { | |
7919 | in_use |= EV5_E1; | |
7920 | nop = gen_nop (); | |
7921 | } | |
7922 | else if (TARGET_FP && !(in_use & EV5_FA)) | |
7923 | { | |
7924 | in_use |= EV5_FA; | |
7925 | nop = gen_fnop (); | |
7926 | } | |
7927 | else if (TARGET_FP && !(in_use & EV5_FM)) | |
7928 | { | |
7929 | in_use |= EV5_FM; | |
7930 | nop = gen_fnop (); | |
7931 | } | |
7932 | else | |
7933 | nop = gen_unop (); | |
7934 | ||
7935 | *pin_use = in_use; | |
7936 | return nop; | |
7937 | } | |
7938 | ||
7939 | /* The instruction group alignment main loop. */ | |
7940 | ||
b9b4428b | 7941 | static void |
92643d95 | 7942 | alpha_align_insns (unsigned int max_align, |
7943 | rtx (*next_group) (rtx, int *, int *), | |
7944 | rtx (*next_nop) (int *)) | |
b9b4428b | 7945 | { |
7946 | /* ALIGN is the known alignment for the insn group. */ | |
b53f315c | 7947 | unsigned int align; |
b9b4428b | 7948 | /* OFS is the offset of the current insn in the insn group. */ |
7949 | int ofs; | |
7950 | int prev_in_use, in_use, len; | |
7951 | rtx i, next; | |
7952 | ||
7953 | /* Let shorten branches care for assigning alignments to code labels. */ | |
2efea8c0 | 7954 | shorten_branches (get_insns ()); |
b9b4428b | 7955 | |
d815ce59 | 7956 | if (align_functions < 4) |
7957 | align = 4; | |
eeca3ba1 | 7958 | else if ((unsigned int) align_functions < max_align) |
d815ce59 | 7959 | align = align_functions; |
7960 | else | |
7961 | align = max_align; | |
e2c8a34a | 7962 | |
b9b4428b | 7963 | ofs = prev_in_use = 0; |
2efea8c0 | 7964 | i = get_insns (); |
b9b4428b | 7965 | if (GET_CODE (i) == NOTE) |
7966 | i = next_nonnote_insn (i); | |
7967 | ||
7968 | while (i) | |
7969 | { | |
b53f315c | 7970 | next = (*next_group) (i, &in_use, &len); |
b9b4428b | 7971 | |
7972 | /* When we see a label, resync alignment etc. */ | |
7973 | if (GET_CODE (i) == CODE_LABEL) | |
7974 | { | |
b53f315c | 7975 | unsigned int new_align = 1 << label_to_alignment (i); |
7976 | ||
b9b4428b | 7977 | if (new_align >= align) |
7978 | { | |
849674a3 | 7979 | align = new_align < max_align ? new_align : max_align; |
b9b4428b | 7980 | ofs = 0; |
7981 | } | |
b53f315c | 7982 | |
b9b4428b | 7983 | else if (ofs & (new_align-1)) |
7984 | ofs = (ofs | (new_align-1)) + 1; | |
7985 | if (len != 0) | |
7986 | abort(); | |
7987 | } | |
7988 | ||
7989 | /* Handle complex instructions special. */ | |
7990 | else if (in_use == 0) | |
7991 | { | |
7992 | /* Asms will have length < 0. This is a signal that we have | |
7993 | lost alignment knowledge. Assume, however, that the asm | |
7994 | will not mis-align instructions. */ | |
7995 | if (len < 0) | |
7996 | { | |
7997 | ofs = 0; | |
7998 | align = 4; | |
7999 | len = 0; | |
8000 | } | |
8001 | } | |
8002 | ||
8003 | /* If the known alignment is smaller than the recognized insn group, | |
8004 | realign the output. */ | |
1f0ce6a6 | 8005 | else if ((int) align < len) |
b9b4428b | 8006 | { |
b53f315c | 8007 | unsigned int new_log_align = len > 8 ? 4 : 3; |
943a1b57 | 8008 | rtx prev, where; |
b9b4428b | 8009 | |
943a1b57 | 8010 | where = prev = prev_nonnote_insn (i); |
b9b4428b | 8011 | if (!where || GET_CODE (where) != CODE_LABEL) |
8012 | where = i; | |
8013 | ||
943a1b57 | 8014 | /* Can't realign between a call and its gp reload. */ |
8015 | if (! (TARGET_EXPLICIT_RELOCS | |
8016 | && prev && GET_CODE (prev) == CALL_INSN)) | |
8017 | { | |
8018 | emit_insn_before (gen_realign (GEN_INT (new_log_align)), where); | |
8019 | align = 1 << new_log_align; | |
8020 | ofs = 0; | |
8021 | } | |
b9b4428b | 8022 | } |
8023 | ||
8024 | /* If the group won't fit in the same INT16 as the previous, | |
8025 | we need to add padding to keep the group together. Rather | |
8026 | than simply leaving the insn filling to the assembler, we | |
8027 | can make use of the knowledge of what sorts of instructions | |
8028 | were issued in the previous group to make sure that all of | |
8029 | the added nops are really free. */ | |
1f0ce6a6 | 8030 | else if (ofs + len > (int) align) |
b9b4428b | 8031 | { |
8032 | int nop_count = (align - ofs) / 4; | |
8033 | rtx where; | |
8034 | ||
efee20da | 8035 | /* Insert nops before labels, branches, and calls to truly merge |
943a1b57 | 8036 | the execution of the nops with the previous instruction group. */ |
b9b4428b | 8037 | where = prev_nonnote_insn (i); |
849674a3 | 8038 | if (where) |
b9b4428b | 8039 | { |
849674a3 | 8040 | if (GET_CODE (where) == CODE_LABEL) |
b9b4428b | 8041 | { |
849674a3 | 8042 | rtx where2 = prev_nonnote_insn (where); |
8043 | if (where2 && GET_CODE (where2) == JUMP_INSN) | |
8044 | where = where2; | |
b9b4428b | 8045 | } |
943a1b57 | 8046 | else if (GET_CODE (where) == INSN) |
849674a3 | 8047 | where = i; |
b9b4428b | 8048 | } |
849674a3 | 8049 | else |
8050 | where = i; | |
8051 | ||
9e7454d0 | 8052 | do |
849674a3 | 8053 | emit_insn_before ((*next_nop)(&prev_in_use), where); |
b9b4428b | 8054 | while (--nop_count); |
8055 | ofs = 0; | |
8056 | } | |
8057 | ||
8058 | ofs = (ofs + len) & (align - 1); | |
8059 | prev_in_use = in_use; | |
8060 | i = next; | |
8061 | } | |
8062 | } | |
b9b4428b | 8063 | \f |
35a3065a | 8064 | /* Machine dependent reorg pass. */ |
18adf4f6 | 8065 | |
2efea8c0 | 8066 | static void |
92643d95 | 8067 | alpha_reorg (void) |
18adf4f6 | 8068 | { |
b9b4428b | 8069 | if (alpha_tp != ALPHA_TP_PROG || flag_exceptions) |
2efea8c0 | 8070 | alpha_handle_trap_shadows (); |
b9b4428b | 8071 | |
b9b4428b | 8072 | /* Due to the number of extra trapb insns, don't bother fixing up |
8073 | alignment when trap precision is instruction. Moreover, we can | |
b53f315c | 8074 | only do our job when sched2 is run. */ |
b9b4428b | 8075 | if (optimize && !optimize_size |
8076 | && alpha_tp != ALPHA_TP_INSN | |
8077 | && flag_schedule_insns_after_reload) | |
8078 | { | |
849674a3 | 8079 | if (alpha_cpu == PROCESSOR_EV4) |
2efea8c0 | 8080 | alpha_align_insns (8, alphaev4_next_group, alphaev4_next_nop); |
849674a3 | 8081 | else if (alpha_cpu == PROCESSOR_EV5) |
2efea8c0 | 8082 | alpha_align_insns (16, alphaev5_next_group, alphaev5_next_nop); |
b9b4428b | 8083 | } |
18adf4f6 | 8084 | } |
18adf4f6 | 8085 | \f |
92c473b8 | 8086 | #if !TARGET_ABI_UNICOSMK |
8087 | ||
8088 | #ifdef HAVE_STAMP_H | |
8089 | #include <stamp.h> | |
8090 | #endif | |
8091 | ||
8092 | static void | |
8093 | alpha_file_start (void) | |
8094 | { | |
0fdc84d7 | 8095 | #ifdef OBJECT_FORMAT_ELF |
8096 | /* If emitting dwarf2 debug information, we cannot generate a .file | |
8097 | directive to start the file, as it will conflict with dwarf2out | |
8098 | file numbers. So it's only useful when emitting mdebug output. */ | |
8099 | targetm.file_start_file_directive = (write_symbols == DBX_DEBUG); | |
8100 | #endif | |
8101 | ||
92c473b8 | 8102 | default_file_start (); |
8103 | #ifdef MS_STAMP | |
bc964653 | 8104 | fprintf (asm_out_file, "\t.verstamp %d %d\n", MS_STAMP, LS_STAMP); |
92c473b8 | 8105 | #endif |
8106 | ||
8107 | fputs ("\t.set noreorder\n", asm_out_file); | |
8108 | fputs ("\t.set volatile\n", asm_out_file); | |
8109 | if (!TARGET_ABI_OPEN_VMS) | |
8110 | fputs ("\t.set noat\n", asm_out_file); | |
8111 | if (TARGET_EXPLICIT_RELOCS) | |
8112 | fputs ("\t.set nomacro\n", asm_out_file); | |
8113 | if (TARGET_SUPPORT_ARCH | TARGET_BWX | TARGET_MAX | TARGET_FIX | TARGET_CIX) | |
8114 | fprintf (asm_out_file, | |
8115 | "\t.arch %s\n", | |
9e7454d0 | 8116 | TARGET_CPU_EV6 ? "ev6" |
92c473b8 | 8117 | : (TARGET_CPU_EV5 |
8118 | ? (TARGET_MAX ? "pca56" : TARGET_BWX ? "ev56" : "ev5") | |
8119 | : "ev4")); | |
8120 | } | |
8121 | #endif | |
8122 | ||
bbfbe351 | 8123 | #ifdef OBJECT_FORMAT_ELF |
8124 | ||
8125 | /* Switch to the section to which we should output X. The only thing | |
8126 | special we do here is to honor small data. */ | |
8127 | ||
8128 | static void | |
92643d95 | 8129 | alpha_elf_select_rtx_section (enum machine_mode mode, rtx x, |
8130 | unsigned HOST_WIDE_INT align) | |
bbfbe351 | 8131 | { |
8132 | if (TARGET_SMALL_DATA && GET_MODE_SIZE (mode) <= g_switch_value) | |
5910bb95 | 8133 | /* ??? Consider using mergeable sdata sections. */ |
bbfbe351 | 8134 | sdata_section (); |
8135 | else | |
8136 | default_elf_select_rtx_section (mode, x, align); | |
8137 | } | |
8138 | ||
8139 | #endif /* OBJECT_FORMAT_ELF */ | |
8140 | \f | |
9de382d9 | 8141 | /* Structure to collect function names for final output in link section. */ |
8142 | /* Note that items marked with GTY can't be ifdef'ed out. */ | |
573aba85 | 8143 | |
8144 | enum links_kind {KIND_UNUSED, KIND_LOCAL, KIND_EXTERN}; | |
9de382d9 | 8145 | enum reloc_kind {KIND_LINKAGE, KIND_CODEADDR}; |
573aba85 | 8146 | |
8147 | struct alpha_links GTY(()) | |
8148 | { | |
9de382d9 | 8149 | int num; |
573aba85 | 8150 | rtx linkage; |
9de382d9 | 8151 | enum links_kind lkind; |
8152 | enum reloc_kind rkind; | |
8153 | }; | |
8154 | ||
8155 | struct alpha_funcs GTY(()) | |
8156 | { | |
8157 | int num; | |
8158 | splay_tree GTY ((param1_is (char *), param2_is (struct alpha_links *))) | |
8159 | links; | |
573aba85 | 8160 | }; |
8161 | ||
8162 | static GTY ((param1_is (char *), param2_is (struct alpha_links *))) | |
9de382d9 | 8163 | splay_tree alpha_links_tree; |
8164 | static GTY ((param1_is (tree), param2_is (struct alpha_funcs *))) | |
8165 | splay_tree alpha_funcs_tree; | |
8166 | ||
8167 | static GTY(()) int alpha_funcs_num; | |
573aba85 | 8168 | |
1467e953 | 8169 | #if TARGET_ABI_OPEN_VMS |
8df4a58b | 8170 | |
0dbd1c74 | 8171 | /* Return the VMS argument type corresponding to MODE. */ |
8df4a58b | 8172 | |
0dbd1c74 | 8173 | enum avms_arg_type |
92643d95 | 8174 | alpha_arg_type (enum machine_mode mode) |
0dbd1c74 | 8175 | { |
8176 | switch (mode) | |
8df4a58b | 8177 | { |
0dbd1c74 | 8178 | case SFmode: |
8179 | return TARGET_FLOAT_VAX ? FF : FS; | |
8180 | case DFmode: | |
8181 | return TARGET_FLOAT_VAX ? FD : FT; | |
8182 | default: | |
8183 | return I64; | |
8df4a58b | 8184 | } |
0dbd1c74 | 8185 | } |
8df4a58b | 8186 | |
0dbd1c74 | 8187 | /* Return an rtx for an integer representing the VMS Argument Information |
8188 | register value. */ | |
8df4a58b | 8189 | |
1dd6c958 | 8190 | rtx |
92643d95 | 8191 | alpha_arg_info_reg_val (CUMULATIVE_ARGS cum) |
0dbd1c74 | 8192 | { |
8193 | unsigned HOST_WIDE_INT regval = cum.num_args; | |
8194 | int i; | |
8df4a58b | 8195 | |
0dbd1c74 | 8196 | for (i = 0; i < 6; i++) |
8197 | regval |= ((int) cum.atypes[i]) << (i * 3 + 8); | |
8df4a58b | 8198 | |
0dbd1c74 | 8199 | return GEN_INT (regval); |
8200 | } | |
8201 | \f | |
8df4a58b | 8202 | /* Make (or fake) .linkage entry for function call. |
8203 | ||
57e47080 | 8204 | IS_LOCAL is 0 if name is used in call, 1 if name is used in definition. |
8df4a58b | 8205 | |
57e47080 | 8206 | Return an SYMBOL_REF rtx for the linkage. */ |
8207 | ||
8208 | rtx | |
92643d95 | 8209 | alpha_need_linkage (const char *name, int is_local) |
8df4a58b | 8210 | { |
57e47080 | 8211 | splay_tree_node node; |
8212 | struct alpha_links *al; | |
8df4a58b | 8213 | |
8214 | if (name[0] == '*') | |
8215 | name++; | |
8216 | ||
cf73d31f | 8217 | if (is_local) |
8218 | { | |
9de382d9 | 8219 | struct alpha_funcs *cfaf; |
8220 | ||
8221 | if (!alpha_funcs_tree) | |
8222 | alpha_funcs_tree = splay_tree_new_ggc ((splay_tree_compare_fn) | |
8223 | splay_tree_compare_pointers); | |
9e7454d0 | 8224 | |
9de382d9 | 8225 | cfaf = (struct alpha_funcs *) ggc_alloc (sizeof (struct alpha_funcs)); |
cf73d31f | 8226 | |
8227 | cfaf->links = 0; | |
8228 | cfaf->num = ++alpha_funcs_num; | |
8229 | ||
8230 | splay_tree_insert (alpha_funcs_tree, | |
8231 | (splay_tree_key) current_function_decl, | |
8232 | (splay_tree_value) cfaf); | |
cf73d31f | 8233 | } |
8234 | ||
8235 | if (alpha_links_tree) | |
57e47080 | 8236 | { |
8237 | /* Is this name already defined? */ | |
8df4a58b | 8238 | |
cf73d31f | 8239 | node = splay_tree_lookup (alpha_links_tree, (splay_tree_key) name); |
57e47080 | 8240 | if (node) |
8241 | { | |
8242 | al = (struct alpha_links *) node->value; | |
8243 | if (is_local) | |
8244 | { | |
8245 | /* Defined here but external assumed. */ | |
cf73d31f | 8246 | if (al->lkind == KIND_EXTERN) |
8247 | al->lkind = KIND_LOCAL; | |
57e47080 | 8248 | } |
8249 | else | |
8250 | { | |
8251 | /* Used here but unused assumed. */ | |
cf73d31f | 8252 | if (al->lkind == KIND_UNUSED) |
8253 | al->lkind = KIND_LOCAL; | |
57e47080 | 8254 | } |
8255 | return al->linkage; | |
8256 | } | |
8257 | } | |
8258 | else | |
8482c296 | 8259 | alpha_links_tree = splay_tree_new_ggc ((splay_tree_compare_fn) strcmp); |
8df4a58b | 8260 | |
573aba85 | 8261 | al = (struct alpha_links *) ggc_alloc (sizeof (struct alpha_links)); |
8262 | name = ggc_strdup (name); | |
8df4a58b | 8263 | |
8264 | /* Assume external if no definition. */ | |
cf73d31f | 8265 | al->lkind = (is_local ? KIND_UNUSED : KIND_EXTERN); |
8df4a58b | 8266 | |
57e47080 | 8267 | /* Ensure we have an IDENTIFIER so assemble_name can mark it used. */ |
d2899e26 | 8268 | get_identifier (name); |
8269 | ||
57e47080 | 8270 | /* Construct a SYMBOL_REF for us to call. */ |
8271 | { | |
8272 | size_t name_len = strlen (name); | |
44acf429 | 8273 | char *linksym = alloca (name_len + 6); |
57e47080 | 8274 | linksym[0] = '$'; |
8275 | memcpy (linksym + 1, name, name_len); | |
8276 | memcpy (linksym + 1 + name_len, "..lk", 5); | |
44acf429 | 8277 | al->linkage = gen_rtx_SYMBOL_REF (Pmode, |
8278 | ggc_alloc_string (linksym, name_len + 5)); | |
57e47080 | 8279 | } |
8280 | ||
cf73d31f | 8281 | splay_tree_insert (alpha_links_tree, (splay_tree_key) name, |
57e47080 | 8282 | (splay_tree_value) al); |
8df4a58b | 8283 | |
57e47080 | 8284 | return al->linkage; |
8df4a58b | 8285 | } |
8286 | ||
cf73d31f | 8287 | rtx |
92643d95 | 8288 | alpha_use_linkage (rtx linkage, tree cfundecl, int lflag, int rflag) |
cf73d31f | 8289 | { |
8290 | splay_tree_node cfunnode; | |
8291 | struct alpha_funcs *cfaf; | |
8292 | struct alpha_links *al; | |
8293 | const char *name = XSTR (linkage, 0); | |
8294 | ||
8295 | cfaf = (struct alpha_funcs *) 0; | |
8296 | al = (struct alpha_links *) 0; | |
8297 | ||
8298 | cfunnode = splay_tree_lookup (alpha_funcs_tree, (splay_tree_key) cfundecl); | |
8299 | cfaf = (struct alpha_funcs *) cfunnode->value; | |
8300 | ||
8301 | if (cfaf->links) | |
8302 | { | |
8303 | splay_tree_node lnode; | |
8304 | ||
8305 | /* Is this name already defined? */ | |
8306 | ||
8307 | lnode = splay_tree_lookup (cfaf->links, (splay_tree_key) name); | |
8308 | if (lnode) | |
8309 | al = (struct alpha_links *) lnode->value; | |
8310 | } | |
8311 | else | |
9de382d9 | 8312 | cfaf->links = splay_tree_new_ggc ((splay_tree_compare_fn) strcmp); |
cf73d31f | 8313 | |
8314 | if (!al) | |
8315 | { | |
8316 | size_t name_len; | |
8317 | size_t buflen; | |
8318 | char buf [512]; | |
8319 | char *linksym; | |
8320 | splay_tree_node node = 0; | |
8321 | struct alpha_links *anl; | |
8322 | ||
8323 | if (name[0] == '*') | |
8324 | name++; | |
8325 | ||
8326 | name_len = strlen (name); | |
8327 | ||
9de382d9 | 8328 | al = (struct alpha_links *) ggc_alloc (sizeof (struct alpha_links)); |
cf73d31f | 8329 | al->num = cfaf->num; |
8330 | ||
8331 | node = splay_tree_lookup (alpha_links_tree, (splay_tree_key) name); | |
8332 | if (node) | |
8333 | { | |
8334 | anl = (struct alpha_links *) node->value; | |
8335 | al->lkind = anl->lkind; | |
8336 | } | |
8337 | ||
8338 | sprintf (buf, "$%d..%s..lk", cfaf->num, name); | |
8339 | buflen = strlen (buf); | |
8340 | linksym = alloca (buflen + 1); | |
8341 | memcpy (linksym, buf, buflen + 1); | |
8342 | ||
8343 | al->linkage = gen_rtx_SYMBOL_REF | |
8344 | (Pmode, ggc_alloc_string (linksym, buflen + 1)); | |
8345 | ||
8346 | splay_tree_insert (cfaf->links, (splay_tree_key) name, | |
8347 | (splay_tree_value) al); | |
8348 | } | |
8349 | ||
8350 | if (rflag) | |
8351 | al->rkind = KIND_CODEADDR; | |
8352 | else | |
8353 | al->rkind = KIND_LINKAGE; | |
9e7454d0 | 8354 | |
cf73d31f | 8355 | if (lflag) |
8356 | return gen_rtx_MEM (Pmode, plus_constant (al->linkage, 8)); | |
8357 | else | |
8358 | return al->linkage; | |
8359 | } | |
8360 | ||
57e47080 | 8361 | static int |
92643d95 | 8362 | alpha_write_one_linkage (splay_tree_node node, void *data) |
57e47080 | 8363 | { |
0d95286f | 8364 | const char *const name = (const char *) node->key; |
cf73d31f | 8365 | struct alpha_links *link = (struct alpha_links *) node->value; |
57e47080 | 8366 | FILE *stream = (FILE *) data; |
8367 | ||
cf73d31f | 8368 | fprintf (stream, "$%d..%s..lk:\n", link->num, name); |
8369 | if (link->rkind == KIND_CODEADDR) | |
57e47080 | 8370 | { |
cf73d31f | 8371 | if (link->lkind == KIND_LOCAL) |
8372 | { | |
8373 | /* Local and used */ | |
8374 | fprintf (stream, "\t.quad %s..en\n", name); | |
8375 | } | |
8376 | else | |
8377 | { | |
8378 | /* External and used, request code address. */ | |
8379 | fprintf (stream, "\t.code_address %s\n", name); | |
8380 | } | |
57e47080 | 8381 | } |
8382 | else | |
8383 | { | |
cf73d31f | 8384 | if (link->lkind == KIND_LOCAL) |
8385 | { | |
8386 | /* Local and used, build linkage pair. */ | |
8387 | fprintf (stream, "\t.quad %s..en\n", name); | |
8388 | fprintf (stream, "\t.quad %s\n", name); | |
8389 | } | |
8390 | else | |
8391 | { | |
8392 | /* External and used, request linkage pair. */ | |
8393 | fprintf (stream, "\t.linkage %s\n", name); | |
8394 | } | |
57e47080 | 8395 | } |
8396 | ||
8397 | return 0; | |
8398 | } | |
8df4a58b | 8399 | |
cf73d31f | 8400 | static void |
92643d95 | 8401 | alpha_write_linkage (FILE *stream, const char *funname, tree fundecl) |
8df4a58b | 8402 | { |
cf73d31f | 8403 | splay_tree_node node; |
8404 | struct alpha_funcs *func; | |
8405 | ||
8406 | link_section (); | |
8407 | fprintf (stream, "\t.align 3\n"); | |
8408 | node = splay_tree_lookup (alpha_funcs_tree, (splay_tree_key) fundecl); | |
8409 | func = (struct alpha_funcs *) node->value; | |
8410 | ||
8411 | fputs ("\t.name ", stream); | |
8412 | assemble_name (stream, funname); | |
8413 | fputs ("..na\n", stream); | |
8414 | ASM_OUTPUT_LABEL (stream, funname); | |
8415 | fprintf (stream, "\t.pdesc "); | |
8416 | assemble_name (stream, funname); | |
8417 | fprintf (stream, "..en,%s\n", | |
8418 | alpha_procedure_type == PT_STACK ? "stack" | |
8419 | : alpha_procedure_type == PT_REGISTER ? "reg" : "null"); | |
8420 | ||
8421 | if (func->links) | |
c64a8830 | 8422 | { |
cf73d31f | 8423 | splay_tree_foreach (func->links, alpha_write_one_linkage, stream); |
8424 | /* splay_tree_delete (func->links); */ | |
c64a8830 | 8425 | } |
8df4a58b | 8426 | } |
8427 | ||
2cb4ac60 | 8428 | /* Given a decl, a section name, and whether the decl initializer |
8429 | has relocs, choose attributes for the section. */ | |
8430 | ||
8431 | #define SECTION_VMS_OVERLAY SECTION_FORGET | |
c64a8830 | 8432 | #define SECTION_VMS_GLOBAL SECTION_MACH_DEP |
8433 | #define SECTION_VMS_INITIALIZE (SECTION_VMS_GLOBAL << 1) | |
2cb4ac60 | 8434 | |
8435 | static unsigned int | |
92643d95 | 8436 | vms_section_type_flags (tree decl, const char *name, int reloc) |
2cb4ac60 | 8437 | { |
8438 | unsigned int flags = default_section_type_flags (decl, name, reloc); | |
8439 | ||
e3c541f0 | 8440 | if (decl && DECL_ATTRIBUTES (decl) |
8441 | && lookup_attribute ("overlaid", DECL_ATTRIBUTES (decl))) | |
2cb4ac60 | 8442 | flags |= SECTION_VMS_OVERLAY; |
c64a8830 | 8443 | if (decl && DECL_ATTRIBUTES (decl) |
8444 | && lookup_attribute ("global", DECL_ATTRIBUTES (decl))) | |
8445 | flags |= SECTION_VMS_GLOBAL; | |
8446 | if (decl && DECL_ATTRIBUTES (decl) | |
8447 | && lookup_attribute ("initialize", DECL_ATTRIBUTES (decl))) | |
8448 | flags |= SECTION_VMS_INITIALIZE; | |
2cb4ac60 | 8449 | |
8450 | return flags; | |
8451 | } | |
8452 | ||
8453 | /* Switch to an arbitrary section NAME with attributes as specified | |
8454 | by FLAGS. ALIGN specifies any known alignment requirements for | |
8455 | the section; 0 if the default should be used. */ | |
8456 | ||
8457 | static void | |
537cd941 | 8458 | vms_asm_named_section (const char *name, unsigned int flags, |
8459 | tree decl ATTRIBUTE_UNUSED) | |
2cb4ac60 | 8460 | { |
c64a8830 | 8461 | fputc ('\n', asm_out_file); |
8462 | fprintf (asm_out_file, ".section\t%s", name); | |
2cb4ac60 | 8463 | |
8464 | if (flags & SECTION_VMS_OVERLAY) | |
c64a8830 | 8465 | fprintf (asm_out_file, ",OVR"); |
8466 | if (flags & SECTION_VMS_GLOBAL) | |
8467 | fprintf (asm_out_file, ",GBL"); | |
8468 | if (flags & SECTION_VMS_INITIALIZE) | |
8469 | fprintf (asm_out_file, ",NOMOD"); | |
8470 | if (flags & SECTION_DEBUG) | |
8471 | fprintf (asm_out_file, ",NOWRT"); | |
8472 | ||
8473 | fputc ('\n', asm_out_file); | |
2cb4ac60 | 8474 | } |
8475 | ||
01d15dc5 | 8476 | /* Record an element in the table of global constructors. SYMBOL is |
8477 | a SYMBOL_REF of the function to be called; PRIORITY is a number | |
9e7454d0 | 8478 | between 0 and MAX_INIT_PRIORITY. |
01d15dc5 | 8479 | |
8480 | Differs from default_ctors_section_asm_out_constructor in that the | |
8481 | width of the .ctors entry is always 64 bits, rather than the 32 bits | |
8482 | used by a normal pointer. */ | |
8483 | ||
8484 | static void | |
92643d95 | 8485 | vms_asm_out_constructor (rtx symbol, int priority ATTRIBUTE_UNUSED) |
01d15dc5 | 8486 | { |
8487 | ctors_section (); | |
09d688ff | 8488 | assemble_align (BITS_PER_WORD); |
8489 | assemble_integer (symbol, UNITS_PER_WORD, BITS_PER_WORD, 1); | |
01d15dc5 | 8490 | } |
8491 | ||
8492 | static void | |
92643d95 | 8493 | vms_asm_out_destructor (rtx symbol, int priority ATTRIBUTE_UNUSED) |
01d15dc5 | 8494 | { |
8495 | dtors_section (); | |
09d688ff | 8496 | assemble_align (BITS_PER_WORD); |
8497 | assemble_integer (symbol, UNITS_PER_WORD, BITS_PER_WORD, 1); | |
01d15dc5 | 8498 | } |
8df4a58b | 8499 | #else |
8500 | ||
57e47080 | 8501 | rtx |
92643d95 | 8502 | alpha_need_linkage (const char *name ATTRIBUTE_UNUSED, |
8503 | int is_local ATTRIBUTE_UNUSED) | |
8df4a58b | 8504 | { |
57e47080 | 8505 | return NULL_RTX; |
8df4a58b | 8506 | } |
8507 | ||
cf73d31f | 8508 | rtx |
92643d95 | 8509 | alpha_use_linkage (rtx linkage ATTRIBUTE_UNUSED, |
8510 | tree cfundecl ATTRIBUTE_UNUSED, | |
8511 | int lflag ATTRIBUTE_UNUSED, | |
8512 | int rflag ATTRIBUTE_UNUSED) | |
cf73d31f | 8513 | { |
8514 | return NULL_RTX; | |
8515 | } | |
8516 | ||
1467e953 | 8517 | #endif /* TARGET_ABI_OPEN_VMS */ |
9caef960 | 8518 | \f |
8519 | #if TARGET_ABI_UNICOSMK | |
8520 | ||
0336f0f0 | 8521 | /* This evaluates to true if we do not know how to pass TYPE solely in |
8522 | registers. This is the case for all arguments that do not fit in two | |
8523 | registers. */ | |
8524 | ||
8525 | static bool | |
8526 | unicosmk_must_pass_in_stack (enum machine_mode mode, tree type) | |
8527 | { | |
8528 | if (type == NULL) | |
8529 | return false; | |
8530 | ||
8531 | if (TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST) | |
8532 | return true; | |
8533 | if (TREE_ADDRESSABLE (type)) | |
8534 | return true; | |
8535 | ||
8536 | return ALPHA_ARG_SIZE (mode, type, 0) > 2; | |
8537 | } | |
8538 | ||
9caef960 | 8539 | /* Define the offset between two registers, one to be eliminated, and the |
8540 | other its replacement, at the start of a routine. */ | |
8541 | ||
8542 | int | |
92643d95 | 8543 | unicosmk_initial_elimination_offset (int from, int to) |
9caef960 | 8544 | { |
8545 | int fixed_size; | |
9e7454d0 | 8546 | |
9caef960 | 8547 | fixed_size = alpha_sa_size(); |
8548 | if (fixed_size != 0) | |
8549 | fixed_size += 48; | |
8550 | ||
8551 | if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM) | |
9e7454d0 | 8552 | return -fixed_size; |
9caef960 | 8553 | else if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM) |
8554 | return 0; | |
8555 | else if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM) | |
8556 | return (ALPHA_ROUND (current_function_outgoing_args_size) | |
8557 | + ALPHA_ROUND (get_frame_size())); | |
8558 | else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM) | |
8559 | return (ALPHA_ROUND (fixed_size) | |
9e7454d0 | 8560 | + ALPHA_ROUND (get_frame_size() |
9caef960 | 8561 | + current_function_outgoing_args_size)); |
8562 | else | |
8563 | abort (); | |
8564 | } | |
8565 | ||
8566 | /* Output the module name for .ident and .end directives. We have to strip | |
8567 | directories and add make sure that the module name starts with a letter | |
8568 | or '$'. */ | |
8569 | ||
8570 | static void | |
92643d95 | 8571 | unicosmk_output_module_name (FILE *file) |
9caef960 | 8572 | { |
8789d51c | 8573 | const char *name = lbasename (main_input_filename); |
8574 | unsigned len = strlen (name); | |
8575 | char *clean_name = alloca (len + 2); | |
8576 | char *ptr = clean_name; | |
9e7454d0 | 8577 | |
9caef960 | 8578 | /* CAM only accepts module names that start with a letter or '$'. We |
8579 | prefix the module name with a '$' if necessary. */ | |
8580 | ||
8581 | if (!ISALPHA (*name)) | |
8789d51c | 8582 | *ptr++ = '$'; |
8583 | memcpy (ptr, name, len + 1); | |
8584 | clean_symbol_name (clean_name); | |
8585 | fputs (clean_name, file); | |
9caef960 | 8586 | } |
8587 | ||
92643d95 | 8588 | /* Output the definition of a common variable. */ |
9caef960 | 8589 | |
92643d95 | 8590 | void |
8591 | unicosmk_output_common (FILE *file, const char *name, int size, int align) | |
9caef960 | 8592 | { |
92643d95 | 8593 | tree name_tree; |
8594 | printf ("T3E__: common %s\n", name); | |
9caef960 | 8595 | |
8596 | common_section (); | |
8597 | fputs("\t.endp\n\n\t.psect ", file); | |
8598 | assemble_name(file, name); | |
8599 | fprintf(file, ",%d,common\n", floor_log2 (align / BITS_PER_UNIT)); | |
8600 | fprintf(file, "\t.byte\t0:%d\n", size); | |
8601 | ||
8602 | /* Mark the symbol as defined in this module. */ | |
8603 | name_tree = get_identifier (name); | |
8604 | TREE_ASM_WRITTEN (name_tree) = 1; | |
8605 | } | |
8606 | ||
8607 | #define SECTION_PUBLIC SECTION_MACH_DEP | |
8608 | #define SECTION_MAIN (SECTION_PUBLIC << 1) | |
8609 | static int current_section_align; | |
8610 | ||
8611 | static unsigned int | |
92643d95 | 8612 | unicosmk_section_type_flags (tree decl, const char *name, |
8613 | int reloc ATTRIBUTE_UNUSED) | |
9caef960 | 8614 | { |
8615 | unsigned int flags = default_section_type_flags (decl, name, reloc); | |
8616 | ||
8617 | if (!decl) | |
8618 | return flags; | |
8619 | ||
8620 | if (TREE_CODE (decl) == FUNCTION_DECL) | |
8621 | { | |
8622 | current_section_align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT); | |
8623 | if (align_functions_log > current_section_align) | |
8624 | current_section_align = align_functions_log; | |
8625 | ||
8626 | if (! strcmp (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl)), "main")) | |
8627 | flags |= SECTION_MAIN; | |
8628 | } | |
8629 | else | |
8630 | current_section_align = floor_log2 (DECL_ALIGN (decl) / BITS_PER_UNIT); | |
8631 | ||
8632 | if (TREE_PUBLIC (decl)) | |
8633 | flags |= SECTION_PUBLIC; | |
8634 | ||
8635 | return flags; | |
8636 | } | |
8637 | ||
8638 | /* Generate a section name for decl and associate it with the | |
8639 | declaration. */ | |
8640 | ||
52470889 | 8641 | static void |
92643d95 | 8642 | unicosmk_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED) |
9caef960 | 8643 | { |
8644 | const char *name; | |
8645 | int len; | |
8646 | ||
9e7454d0 | 8647 | if (!decl) |
9caef960 | 8648 | abort (); |
8649 | ||
8650 | name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl)); | |
09a1f342 | 8651 | name = default_strip_name_encoding (name); |
9caef960 | 8652 | len = strlen (name); |
8653 | ||
8654 | if (TREE_CODE (decl) == FUNCTION_DECL) | |
8655 | { | |
8656 | char *string; | |
8657 | ||
9e7454d0 | 8658 | /* It is essential that we prefix the section name here because |
8659 | otherwise the section names generated for constructors and | |
9caef960 | 8660 | destructors confuse collect2. */ |
8661 | ||
8662 | string = alloca (len + 6); | |
8663 | sprintf (string, "code@%s", name); | |
8664 | DECL_SECTION_NAME (decl) = build_string (len + 5, string); | |
8665 | } | |
8666 | else if (TREE_PUBLIC (decl)) | |
8667 | DECL_SECTION_NAME (decl) = build_string (len, name); | |
8668 | else | |
8669 | { | |
8670 | char *string; | |
8671 | ||
8672 | string = alloca (len + 6); | |
8673 | sprintf (string, "data@%s", name); | |
8674 | DECL_SECTION_NAME (decl) = build_string (len + 5, string); | |
8675 | } | |
8676 | } | |
8677 | ||
8678 | /* Switch to an arbitrary section NAME with attributes as specified | |
8679 | by FLAGS. ALIGN specifies any known alignment requirements for | |
8680 | the section; 0 if the default should be used. */ | |
8681 | ||
8682 | static void | |
537cd941 | 8683 | unicosmk_asm_named_section (const char *name, unsigned int flags, |
8684 | tree decl ATTRIBUTE_UNUSED) | |
9caef960 | 8685 | { |
8686 | const char *kind; | |
8687 | ||
8688 | /* Close the previous section. */ | |
8689 | ||
8690 | fputs ("\t.endp\n\n", asm_out_file); | |
8691 | ||
8692 | /* Find out what kind of section we are opening. */ | |
8693 | ||
8694 | if (flags & SECTION_MAIN) | |
8695 | fputs ("\t.start\tmain\n", asm_out_file); | |
8696 | ||
8697 | if (flags & SECTION_CODE) | |
8698 | kind = "code"; | |
8699 | else if (flags & SECTION_PUBLIC) | |
8700 | kind = "common"; | |
8701 | else | |
8702 | kind = "data"; | |
8703 | ||
8704 | if (current_section_align != 0) | |
8705 | fprintf (asm_out_file, "\t.psect\t%s,%d,%s\n", name, | |
8706 | current_section_align, kind); | |
8707 | else | |
8708 | fprintf (asm_out_file, "\t.psect\t%s,%s\n", name, kind); | |
8709 | } | |
8710 | ||
8711 | static void | |
92643d95 | 8712 | unicosmk_insert_attributes (tree decl, tree *attr_ptr ATTRIBUTE_UNUSED) |
9caef960 | 8713 | { |
8714 | if (DECL_P (decl) | |
8715 | && (TREE_PUBLIC (decl) || TREE_CODE (decl) == FUNCTION_DECL)) | |
52470889 | 8716 | unicosmk_unique_section (decl, 0); |
9caef960 | 8717 | } |
8718 | ||
8719 | /* Output an alignment directive. We have to use the macro 'gcc@code@align' | |
8720 | in code sections because .align fill unused space with zeroes. */ | |
9e7454d0 | 8721 | |
9caef960 | 8722 | void |
92643d95 | 8723 | unicosmk_output_align (FILE *file, int align) |
9caef960 | 8724 | { |
8725 | if (inside_function) | |
8726 | fprintf (file, "\tgcc@code@align\t%d\n", align); | |
8727 | else | |
8728 | fprintf (file, "\t.align\t%d\n", align); | |
8729 | } | |
8730 | ||
8731 | /* Add a case vector to the current function's list of deferred case | |
8732 | vectors. Case vectors have to be put into a separate section because CAM | |
8733 | does not allow data definitions in code sections. */ | |
8734 | ||
8735 | void | |
92643d95 | 8736 | unicosmk_defer_case_vector (rtx lab, rtx vec) |
9caef960 | 8737 | { |
8738 | struct machine_function *machine = cfun->machine; | |
9e7454d0 | 8739 | |
9caef960 | 8740 | vec = gen_rtx_EXPR_LIST (VOIDmode, lab, vec); |
8741 | machine->addr_list = gen_rtx_EXPR_LIST (VOIDmode, vec, | |
9e7454d0 | 8742 | machine->addr_list); |
9caef960 | 8743 | } |
8744 | ||
8745 | /* Output a case vector. */ | |
8746 | ||
8747 | static void | |
92643d95 | 8748 | unicosmk_output_addr_vec (FILE *file, rtx vec) |
9caef960 | 8749 | { |
8750 | rtx lab = XEXP (vec, 0); | |
8751 | rtx body = XEXP (vec, 1); | |
8752 | int vlen = XVECLEN (body, 0); | |
8753 | int idx; | |
8754 | ||
805e22b2 | 8755 | (*targetm.asm_out.internal_label) (file, "L", CODE_LABEL_NUMBER (lab)); |
9caef960 | 8756 | |
8757 | for (idx = 0; idx < vlen; idx++) | |
8758 | { | |
8759 | ASM_OUTPUT_ADDR_VEC_ELT | |
8760 | (file, CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 0, idx), 0))); | |
8761 | } | |
8762 | } | |
8763 | ||
8764 | /* Output current function's deferred case vectors. */ | |
8765 | ||
8766 | static void | |
92643d95 | 8767 | unicosmk_output_deferred_case_vectors (FILE *file) |
9caef960 | 8768 | { |
8769 | struct machine_function *machine = cfun->machine; | |
8770 | rtx t; | |
8771 | ||
8772 | if (machine->addr_list == NULL_RTX) | |
8773 | return; | |
8774 | ||
8775 | data_section (); | |
8776 | for (t = machine->addr_list; t; t = XEXP (t, 1)) | |
8777 | unicosmk_output_addr_vec (file, XEXP (t, 0)); | |
8778 | } | |
8779 | ||
92643d95 | 8780 | /* Generate the name of the SSIB section for the current function. */ |
8781 | ||
8782 | #define SSIB_PREFIX "__SSIB_" | |
8783 | #define SSIB_PREFIX_LEN 7 | |
8784 | ||
8785 | static const char * | |
8786 | unicosmk_ssib_name (void) | |
8787 | { | |
9e7454d0 | 8788 | /* This is ok since CAM won't be able to deal with names longer than that |
92643d95 | 8789 | anyway. */ |
8790 | ||
8791 | static char name[256]; | |
8792 | ||
8793 | rtx x; | |
8794 | const char *fnname; | |
8795 | int len; | |
8796 | ||
8797 | x = DECL_RTL (cfun->decl); | |
8798 | if (GET_CODE (x) != MEM) | |
8799 | abort (); | |
8800 | x = XEXP (x, 0); | |
8801 | if (GET_CODE (x) != SYMBOL_REF) | |
8802 | abort (); | |
8803 | fnname = XSTR (x, 0); | |
8804 | ||
8805 | len = strlen (fnname); | |
8806 | if (len + SSIB_PREFIX_LEN > 255) | |
8807 | len = 255 - SSIB_PREFIX_LEN; | |
8808 | ||
8809 | strcpy (name, SSIB_PREFIX); | |
8810 | strncpy (name + SSIB_PREFIX_LEN, fnname, len); | |
8811 | name[len + SSIB_PREFIX_LEN] = 0; | |
8812 | ||
8813 | return name; | |
8814 | } | |
8815 | ||
9e7454d0 | 8816 | /* Set up the dynamic subprogram information block (DSIB) and update the |
8817 | frame pointer register ($15) for subroutines which have a frame. If the | |
9caef960 | 8818 | subroutine doesn't have a frame, simply increment $15. */ |
8819 | ||
8820 | static void | |
92643d95 | 8821 | unicosmk_gen_dsib (unsigned long *imaskP) |
9caef960 | 8822 | { |
b19d7ab1 | 8823 | if (alpha_procedure_type == PT_STACK) |
9caef960 | 8824 | { |
8825 | const char *ssib_name; | |
8826 | rtx mem; | |
8827 | ||
8828 | /* Allocate 64 bytes for the DSIB. */ | |
8829 | ||
8830 | FRP (emit_insn (gen_adddi3 (stack_pointer_rtx, stack_pointer_rtx, | |
8831 | GEN_INT (-64)))); | |
8832 | emit_insn (gen_blockage ()); | |
8833 | ||
8834 | /* Save the return address. */ | |
8835 | ||
8836 | mem = gen_rtx_MEM (DImode, plus_constant (stack_pointer_rtx, 56)); | |
8837 | set_mem_alias_set (mem, alpha_sr_alias_set); | |
8838 | FRP (emit_move_insn (mem, gen_rtx_REG (DImode, REG_RA))); | |
df7d0d23 | 8839 | (*imaskP) &= ~(1UL << REG_RA); |
9caef960 | 8840 | |
8841 | /* Save the old frame pointer. */ | |
8842 | ||
8843 | mem = gen_rtx_MEM (DImode, plus_constant (stack_pointer_rtx, 48)); | |
8844 | set_mem_alias_set (mem, alpha_sr_alias_set); | |
8845 | FRP (emit_move_insn (mem, hard_frame_pointer_rtx)); | |
df7d0d23 | 8846 | (*imaskP) &= ~(1UL << HARD_FRAME_POINTER_REGNUM); |
9caef960 | 8847 | |
8848 | emit_insn (gen_blockage ()); | |
8849 | ||
8850 | /* Store the SSIB pointer. */ | |
8851 | ||
8852 | ssib_name = ggc_strdup (unicosmk_ssib_name ()); | |
8853 | mem = gen_rtx_MEM (DImode, plus_constant (stack_pointer_rtx, 32)); | |
8854 | set_mem_alias_set (mem, alpha_sr_alias_set); | |
8855 | ||
8856 | FRP (emit_move_insn (gen_rtx_REG (DImode, 5), | |
8857 | gen_rtx_SYMBOL_REF (Pmode, ssib_name))); | |
8858 | FRP (emit_move_insn (mem, gen_rtx_REG (DImode, 5))); | |
8859 | ||
8860 | /* Save the CIW index. */ | |
8861 | ||
8862 | mem = gen_rtx_MEM (DImode, plus_constant (stack_pointer_rtx, 24)); | |
8863 | set_mem_alias_set (mem, alpha_sr_alias_set); | |
8864 | FRP (emit_move_insn (mem, gen_rtx_REG (DImode, 25))); | |
8865 | ||
8866 | emit_insn (gen_blockage ()); | |
8867 | ||
8868 | /* Set the new frame pointer. */ | |
8869 | ||
8870 | FRP (emit_insn (gen_adddi3 (hard_frame_pointer_rtx, | |
8871 | stack_pointer_rtx, GEN_INT (64)))); | |
8872 | ||
8873 | } | |
8874 | else | |
8875 | { | |
8876 | /* Increment the frame pointer register to indicate that we do not | |
8877 | have a frame. */ | |
8878 | ||
8879 | FRP (emit_insn (gen_adddi3 (hard_frame_pointer_rtx, | |
bcd9bd66 | 8880 | hard_frame_pointer_rtx, const1_rtx))); |
9caef960 | 8881 | } |
8882 | } | |
8883 | ||
9caef960 | 8884 | /* Output the static subroutine information block for the current |
8885 | function. */ | |
8886 | ||
8887 | static void | |
92643d95 | 8888 | unicosmk_output_ssib (FILE *file, const char *fnname) |
9caef960 | 8889 | { |
8890 | int len; | |
8891 | int i; | |
8892 | rtx x; | |
8893 | rtx ciw; | |
8894 | struct machine_function *machine = cfun->machine; | |
8895 | ||
8896 | ssib_section (); | |
8897 | fprintf (file, "\t.endp\n\n\t.psect\t%s%s,data\n", user_label_prefix, | |
8898 | unicosmk_ssib_name ()); | |
8899 | ||
8900 | /* Some required stuff and the function name length. */ | |
8901 | ||
8902 | len = strlen (fnname); | |
8903 | fprintf (file, "\t.quad\t^X20008%2.2X28\n", len); | |
8904 | ||
8905 | /* Saved registers | |
8906 | ??? We don't do that yet. */ | |
8907 | ||
8908 | fputs ("\t.quad\t0\n", file); | |
8909 | ||
8910 | /* Function address. */ | |
8911 | ||
8912 | fputs ("\t.quad\t", file); | |
8913 | assemble_name (file, fnname); | |
8914 | putc ('\n', file); | |
8915 | ||
8916 | fputs ("\t.quad\t0\n", file); | |
8917 | fputs ("\t.quad\t0\n", file); | |
8918 | ||
8919 | /* Function name. | |
8920 | ??? We do it the same way Cray CC does it but this could be | |
8921 | simplified. */ | |
8922 | ||
8923 | for( i = 0; i < len; i++ ) | |
8924 | fprintf (file, "\t.byte\t%d\n", (int)(fnname[i])); | |
8925 | if( (len % 8) == 0 ) | |
8926 | fputs ("\t.quad\t0\n", file); | |
8927 | else | |
8928 | fprintf (file, "\t.bits\t%d : 0\n", (8 - (len % 8))*8); | |
8929 | ||
8930 | /* All call information words used in the function. */ | |
8931 | ||
8932 | for (x = machine->first_ciw; x; x = XEXP (x, 1)) | |
8933 | { | |
8934 | ciw = XEXP (x, 0); | |
9caef960 | 8935 | #if HOST_BITS_PER_WIDE_INT == 32 |
4840a03a | 8936 | fprintf (file, "\t.quad\t" HOST_WIDE_INT_PRINT_DOUBLE_HEX "\n", |
9caef960 | 8937 | CONST_DOUBLE_HIGH (ciw), CONST_DOUBLE_LOW (ciw)); |
8938 | #else | |
4840a03a | 8939 | fprintf (file, "\t.quad\t" HOST_WIDE_INT_PRINT_HEX "\n", INTVAL (ciw)); |
9caef960 | 8940 | #endif |
9caef960 | 8941 | } |
8942 | } | |
8943 | ||
8944 | /* Add a call information word (CIW) to the list of the current function's | |
8945 | CIWs and return its index. | |
8946 | ||
8947 | X is a CONST_INT or CONST_DOUBLE representing the CIW. */ | |
8948 | ||
8949 | rtx | |
92643d95 | 8950 | unicosmk_add_call_info_word (rtx x) |
9caef960 | 8951 | { |
8952 | rtx node; | |
8953 | struct machine_function *machine = cfun->machine; | |
8954 | ||
8955 | node = gen_rtx_EXPR_LIST (VOIDmode, x, NULL_RTX); | |
8956 | if (machine->first_ciw == NULL_RTX) | |
8957 | machine->first_ciw = node; | |
8958 | else | |
8959 | XEXP (machine->last_ciw, 1) = node; | |
8960 | ||
8961 | machine->last_ciw = node; | |
8962 | ++machine->ciw_count; | |
8963 | ||
8964 | return GEN_INT (machine->ciw_count | |
35901471 | 8965 | + strlen (current_function_name ())/8 + 5); |
9caef960 | 8966 | } |
8967 | ||
8968 | static char unicosmk_section_buf[100]; | |
8969 | ||
8970 | char * | |
92643d95 | 8971 | unicosmk_text_section (void) |
9caef960 | 8972 | { |
8973 | static int count = 0; | |
9e7454d0 | 8974 | sprintf (unicosmk_section_buf, "\t.endp\n\n\t.psect\tgcc@text___%d,code", |
9caef960 | 8975 | count++); |
8976 | return unicosmk_section_buf; | |
8977 | } | |
8978 | ||
8979 | char * | |
92643d95 | 8980 | unicosmk_data_section (void) |
9caef960 | 8981 | { |
8982 | static int count = 1; | |
9e7454d0 | 8983 | sprintf (unicosmk_section_buf, "\t.endp\n\n\t.psect\tgcc@data___%d,data", |
9caef960 | 8984 | count++); |
8985 | return unicosmk_section_buf; | |
8986 | } | |
8987 | ||
8988 | /* The Cray assembler doesn't accept extern declarations for symbols which | |
8989 | are defined in the same file. We have to keep track of all global | |
8990 | symbols which are referenced and/or defined in a source file and output | |
8991 | extern declarations for those which are referenced but not defined at | |
8992 | the end of file. */ | |
8993 | ||
8994 | /* List of identifiers for which an extern declaration might have to be | |
8995 | emitted. */ | |
9de382d9 | 8996 | /* FIXME: needs to use GC, so it can be saved and restored for PCH. */ |
9caef960 | 8997 | |
8998 | struct unicosmk_extern_list | |
8999 | { | |
9000 | struct unicosmk_extern_list *next; | |
9001 | const char *name; | |
9002 | }; | |
9003 | ||
9004 | static struct unicosmk_extern_list *unicosmk_extern_head = 0; | |
9005 | ||
9006 | /* Output extern declarations which are required for every asm file. */ | |
9007 | ||
9008 | static void | |
92643d95 | 9009 | unicosmk_output_default_externs (FILE *file) |
9caef960 | 9010 | { |
0d95286f | 9011 | static const char *const externs[] = |
9caef960 | 9012 | { "__T3E_MISMATCH" }; |
9013 | ||
9014 | int i; | |
9015 | int n; | |
9016 | ||
9017 | n = ARRAY_SIZE (externs); | |
9018 | ||
9019 | for (i = 0; i < n; i++) | |
9020 | fprintf (file, "\t.extern\t%s\n", externs[i]); | |
9021 | } | |
9022 | ||
9023 | /* Output extern declarations for global symbols which are have been | |
9024 | referenced but not defined. */ | |
9025 | ||
9026 | static void | |
92643d95 | 9027 | unicosmk_output_externs (FILE *file) |
9caef960 | 9028 | { |
9029 | struct unicosmk_extern_list *p; | |
9030 | const char *real_name; | |
9031 | int len; | |
9032 | tree name_tree; | |
9033 | ||
9034 | len = strlen (user_label_prefix); | |
9035 | for (p = unicosmk_extern_head; p != 0; p = p->next) | |
9036 | { | |
9e7454d0 | 9037 | /* We have to strip the encoding and possibly remove user_label_prefix |
9caef960 | 9038 | from the identifier in order to handle -fleading-underscore and |
9039 | explicit asm names correctly (cf. gcc.dg/asm-names-1.c). */ | |
09a1f342 | 9040 | real_name = default_strip_name_encoding (p->name); |
9caef960 | 9041 | if (len && p->name[0] == '*' |
9042 | && !memcmp (real_name, user_label_prefix, len)) | |
9043 | real_name += len; | |
9e7454d0 | 9044 | |
9caef960 | 9045 | name_tree = get_identifier (real_name); |
9046 | if (! TREE_ASM_WRITTEN (name_tree)) | |
9047 | { | |
9048 | TREE_ASM_WRITTEN (name_tree) = 1; | |
9049 | fputs ("\t.extern\t", file); | |
9050 | assemble_name (file, p->name); | |
9051 | putc ('\n', file); | |
9052 | } | |
9053 | } | |
9054 | } | |
9e7454d0 | 9055 | |
9caef960 | 9056 | /* Record an extern. */ |
9057 | ||
9058 | void | |
92643d95 | 9059 | unicosmk_add_extern (const char *name) |
9caef960 | 9060 | { |
9061 | struct unicosmk_extern_list *p; | |
9062 | ||
9063 | p = (struct unicosmk_extern_list *) | |
92192583 | 9064 | xmalloc (sizeof (struct unicosmk_extern_list)); |
9caef960 | 9065 | p->next = unicosmk_extern_head; |
9066 | p->name = name; | |
9067 | unicosmk_extern_head = p; | |
9068 | } | |
9069 | ||
9070 | /* The Cray assembler generates incorrect code if identifiers which | |
9071 | conflict with register names are used as instruction operands. We have | |
9072 | to replace such identifiers with DEX expressions. */ | |
9073 | ||
9074 | /* Structure to collect identifiers which have been replaced by DEX | |
9075 | expressions. */ | |
9de382d9 | 9076 | /* FIXME: needs to use GC, so it can be saved and restored for PCH. */ |
9caef960 | 9077 | |
9078 | struct unicosmk_dex { | |
9079 | struct unicosmk_dex *next; | |
9080 | const char *name; | |
9081 | }; | |
9082 | ||
9e7454d0 | 9083 | /* List of identifiers which have been replaced by DEX expressions. The DEX |
9caef960 | 9084 | number is determined by the position in the list. */ |
9085 | ||
9e7454d0 | 9086 | static struct unicosmk_dex *unicosmk_dex_list = NULL; |
9caef960 | 9087 | |
9088 | /* The number of elements in the DEX list. */ | |
9089 | ||
9090 | static int unicosmk_dex_count = 0; | |
9091 | ||
9092 | /* Check if NAME must be replaced by a DEX expression. */ | |
9093 | ||
9094 | static int | |
92643d95 | 9095 | unicosmk_special_name (const char *name) |
9caef960 | 9096 | { |
9097 | if (name[0] == '*') | |
9098 | ++name; | |
9099 | ||
9100 | if (name[0] == '$') | |
9101 | ++name; | |
9102 | ||
9103 | if (name[0] != 'r' && name[0] != 'f' && name[0] != 'R' && name[0] != 'F') | |
9104 | return 0; | |
9105 | ||
9106 | switch (name[1]) | |
9107 | { | |
9108 | case '1': case '2': | |
9109 | return (name[2] == '\0' || (ISDIGIT (name[2]) && name[3] == '\0')); | |
9110 | ||
9111 | case '3': | |
9112 | return (name[2] == '\0' | |
9113 | || ((name[2] == '0' || name[2] == '1') && name[3] == '\0')); | |
9114 | ||
9115 | default: | |
9116 | return (ISDIGIT (name[1]) && name[2] == '\0'); | |
9117 | } | |
9118 | } | |
9119 | ||
9120 | /* Return the DEX number if X must be replaced by a DEX expression and 0 | |
9121 | otherwise. */ | |
9122 | ||
9123 | static int | |
92643d95 | 9124 | unicosmk_need_dex (rtx x) |
9caef960 | 9125 | { |
9126 | struct unicosmk_dex *dex; | |
9127 | const char *name; | |
9128 | int i; | |
9e7454d0 | 9129 | |
9caef960 | 9130 | if (GET_CODE (x) != SYMBOL_REF) |
9131 | return 0; | |
9132 | ||
9133 | name = XSTR (x,0); | |
9134 | if (! unicosmk_special_name (name)) | |
9135 | return 0; | |
9136 | ||
9137 | i = unicosmk_dex_count; | |
9138 | for (dex = unicosmk_dex_list; dex; dex = dex->next) | |
9139 | { | |
9140 | if (! strcmp (name, dex->name)) | |
9141 | return i; | |
9142 | --i; | |
9143 | } | |
9e7454d0 | 9144 | |
92192583 | 9145 | dex = (struct unicosmk_dex *) xmalloc (sizeof (struct unicosmk_dex)); |
9caef960 | 9146 | dex->name = name; |
9147 | dex->next = unicosmk_dex_list; | |
9148 | unicosmk_dex_list = dex; | |
9149 | ||
9150 | ++unicosmk_dex_count; | |
9151 | return unicosmk_dex_count; | |
9152 | } | |
9153 | ||
9154 | /* Output the DEX definitions for this file. */ | |
9155 | ||
9156 | static void | |
92643d95 | 9157 | unicosmk_output_dex (FILE *file) |
9caef960 | 9158 | { |
9159 | struct unicosmk_dex *dex; | |
9160 | int i; | |
9161 | ||
9162 | if (unicosmk_dex_list == NULL) | |
9163 | return; | |
9164 | ||
9165 | fprintf (file, "\t.dexstart\n"); | |
9166 | ||
9167 | i = unicosmk_dex_count; | |
9168 | for (dex = unicosmk_dex_list; dex; dex = dex->next) | |
9169 | { | |
9170 | fprintf (file, "\tDEX (%d) = ", i); | |
9171 | assemble_name (file, dex->name); | |
9172 | putc ('\n', file); | |
9173 | --i; | |
9174 | } | |
9e7454d0 | 9175 | |
9caef960 | 9176 | fprintf (file, "\t.dexend\n"); |
9177 | } | |
9178 | ||
92643d95 | 9179 | /* Output text that to appear at the beginning of an assembler file. */ |
9180 | ||
9e7454d0 | 9181 | static void |
92c473b8 | 9182 | unicosmk_file_start (void) |
92643d95 | 9183 | { |
9184 | int i; | |
9185 | ||
92c473b8 | 9186 | fputs ("\t.ident\t", asm_out_file); |
9187 | unicosmk_output_module_name (asm_out_file); | |
9188 | fputs ("\n\n", asm_out_file); | |
92643d95 | 9189 | |
9190 | /* The Unicos/Mk assembler uses different register names. Instead of trying | |
9191 | to support them, we simply use micro definitions. */ | |
9192 | ||
9193 | /* CAM has different register names: rN for the integer register N and fN | |
9194 | for the floating-point register N. Instead of trying to use these in | |
9195 | alpha.md, we define the symbols $N and $fN to refer to the appropriate | |
9196 | register. */ | |
9197 | ||
9198 | for (i = 0; i < 32; ++i) | |
92c473b8 | 9199 | fprintf (asm_out_file, "$%d <- r%d\n", i, i); |
92643d95 | 9200 | |
9201 | for (i = 0; i < 32; ++i) | |
92c473b8 | 9202 | fprintf (asm_out_file, "$f%d <- f%d\n", i, i); |
92643d95 | 9203 | |
92c473b8 | 9204 | putc ('\n', asm_out_file); |
92643d95 | 9205 | |
9206 | /* The .align directive fill unused space with zeroes which does not work | |
9207 | in code sections. We define the macro 'gcc@code@align' which uses nops | |
9208 | instead. Note that it assumes that code sections always have the | |
9209 | biggest possible alignment since . refers to the current offset from | |
9210 | the beginning of the section. */ | |
9211 | ||
92c473b8 | 9212 | fputs ("\t.macro gcc@code@align n\n", asm_out_file); |
9213 | fputs ("gcc@n@bytes = 1 << n\n", asm_out_file); | |
9214 | fputs ("gcc@here = . % gcc@n@bytes\n", asm_out_file); | |
9215 | fputs ("\t.if ne, gcc@here, 0\n", asm_out_file); | |
9216 | fputs ("\t.repeat (gcc@n@bytes - gcc@here) / 4\n", asm_out_file); | |
9217 | fputs ("\tbis r31,r31,r31\n", asm_out_file); | |
9218 | fputs ("\t.endr\n", asm_out_file); | |
9219 | fputs ("\t.endif\n", asm_out_file); | |
9220 | fputs ("\t.endm gcc@code@align\n\n", asm_out_file); | |
92643d95 | 9221 | |
9222 | /* Output extern declarations which should always be visible. */ | |
92c473b8 | 9223 | unicosmk_output_default_externs (asm_out_file); |
92643d95 | 9224 | |
9225 | /* Open a dummy section. We always need to be inside a section for the | |
9226 | section-switching code to work correctly. | |
9227 | ??? This should be a module id or something like that. I still have to | |
9228 | figure out what the rules for those are. */ | |
92c473b8 | 9229 | fputs ("\n\t.psect\t$SG00000,data\n", asm_out_file); |
92643d95 | 9230 | } |
9231 | ||
9232 | /* Output text to appear at the end of an assembler file. This includes all | |
9233 | pending extern declarations and DEX expressions. */ | |
9234 | ||
9235 | static void | |
9236 | unicosmk_file_end (void) | |
9237 | { | |
9238 | fputs ("\t.endp\n\n", asm_out_file); | |
9239 | ||
9240 | /* Output all pending externs. */ | |
9241 | ||
9242 | unicosmk_output_externs (asm_out_file); | |
9243 | ||
9e7454d0 | 9244 | /* Output dex definitions used for functions whose names conflict with |
92643d95 | 9245 | register names. */ |
9246 | ||
9247 | unicosmk_output_dex (asm_out_file); | |
9248 | ||
9249 | fputs ("\t.end\t", asm_out_file); | |
9250 | unicosmk_output_module_name (asm_out_file); | |
9251 | putc ('\n', asm_out_file); | |
9252 | } | |
9253 | ||
9caef960 | 9254 | #else |
9255 | ||
9256 | static void | |
92643d95 | 9257 | unicosmk_output_deferred_case_vectors (FILE *file ATTRIBUTE_UNUSED) |
9caef960 | 9258 | {} |
9259 | ||
9260 | static void | |
92643d95 | 9261 | unicosmk_gen_dsib (unsigned long *imaskP ATTRIBUTE_UNUSED) |
9caef960 | 9262 | {} |
9263 | ||
9264 | static void | |
92643d95 | 9265 | unicosmk_output_ssib (FILE * file ATTRIBUTE_UNUSED, |
9266 | const char * fnname ATTRIBUTE_UNUSED) | |
9caef960 | 9267 | {} |
9268 | ||
9269 | rtx | |
92643d95 | 9270 | unicosmk_add_call_info_word (rtx x ATTRIBUTE_UNUSED) |
9caef960 | 9271 | { |
9272 | return NULL_RTX; | |
9273 | } | |
9274 | ||
9275 | static int | |
92643d95 | 9276 | unicosmk_need_dex (rtx x ATTRIBUTE_UNUSED) |
9caef960 | 9277 | { |
9278 | return 0; | |
9279 | } | |
9280 | ||
9281 | #endif /* TARGET_ABI_UNICOSMK */ | |
1f3233d1 | 9282 | |
f2f543a3 | 9283 | static void |
9284 | alpha_init_libfuncs (void) | |
9285 | { | |
9286 | if (TARGET_ABI_UNICOSMK) | |
9287 | { | |
9288 | /* Prevent gcc from generating calls to __divsi3. */ | |
9289 | set_optab_libfunc (sdiv_optab, SImode, 0); | |
9290 | set_optab_libfunc (udiv_optab, SImode, 0); | |
9291 | ||
9292 | /* Use the functions provided by the system library | |
9293 | for DImode integer division. */ | |
9294 | set_optab_libfunc (sdiv_optab, DImode, "$sldiv"); | |
9295 | set_optab_libfunc (udiv_optab, DImode, "$uldiv"); | |
9296 | } | |
9297 | else if (TARGET_ABI_OPEN_VMS) | |
9298 | { | |
9299 | /* Use the VMS runtime library functions for division and | |
9300 | remainder. */ | |
9301 | set_optab_libfunc (sdiv_optab, SImode, "OTS$DIV_I"); | |
9302 | set_optab_libfunc (sdiv_optab, DImode, "OTS$DIV_L"); | |
9303 | set_optab_libfunc (udiv_optab, SImode, "OTS$DIV_UI"); | |
9304 | set_optab_libfunc (udiv_optab, DImode, "OTS$DIV_UL"); | |
9305 | set_optab_libfunc (smod_optab, SImode, "OTS$REM_I"); | |
9306 | set_optab_libfunc (smod_optab, DImode, "OTS$REM_L"); | |
9307 | set_optab_libfunc (umod_optab, SImode, "OTS$REM_UI"); | |
9308 | set_optab_libfunc (umod_optab, DImode, "OTS$REM_UL"); | |
9309 | } | |
9310 | } | |
9311 | ||
92643d95 | 9312 | \f |
9313 | /* Initialize the GCC target structure. */ | |
9314 | #if TARGET_ABI_OPEN_VMS | |
9315 | # undef TARGET_ATTRIBUTE_TABLE | |
9316 | # define TARGET_ATTRIBUTE_TABLE vms_attribute_table | |
9317 | # undef TARGET_SECTION_TYPE_FLAGS | |
9318 | # define TARGET_SECTION_TYPE_FLAGS vms_section_type_flags | |
9319 | #endif | |
9320 | ||
9321 | #undef TARGET_IN_SMALL_DATA_P | |
9322 | #define TARGET_IN_SMALL_DATA_P alpha_in_small_data_p | |
9323 | ||
9324 | #if TARGET_ABI_UNICOSMK | |
9325 | # undef TARGET_INSERT_ATTRIBUTES | |
9326 | # define TARGET_INSERT_ATTRIBUTES unicosmk_insert_attributes | |
9327 | # undef TARGET_SECTION_TYPE_FLAGS | |
9328 | # define TARGET_SECTION_TYPE_FLAGS unicosmk_section_type_flags | |
9329 | # undef TARGET_ASM_UNIQUE_SECTION | |
9330 | # define TARGET_ASM_UNIQUE_SECTION unicosmk_unique_section | |
76aec42f | 9331 | #undef TARGET_ASM_FUNCTION_RODATA_SECTION |
9332 | #define TARGET_ASM_FUNCTION_RODATA_SECTION default_no_function_rodata_section | |
92643d95 | 9333 | # undef TARGET_ASM_GLOBALIZE_LABEL |
9334 | # define TARGET_ASM_GLOBALIZE_LABEL hook_void_FILEptr_constcharptr | |
0336f0f0 | 9335 | # undef TARGET_MUST_PASS_IN_STACK |
9336 | # define TARGET_MUST_PASS_IN_STACK unicosmk_must_pass_in_stack | |
92643d95 | 9337 | #endif |
9338 | ||
9339 | #undef TARGET_ASM_ALIGNED_HI_OP | |
9340 | #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t" | |
9341 | #undef TARGET_ASM_ALIGNED_DI_OP | |
9342 | #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t" | |
9343 | ||
9344 | /* Default unaligned ops are provided for ELF systems. To get unaligned | |
9345 | data for non-ELF systems, we have to turn off auto alignment. */ | |
9346 | #ifndef OBJECT_FORMAT_ELF | |
9347 | #undef TARGET_ASM_UNALIGNED_HI_OP | |
9348 | #define TARGET_ASM_UNALIGNED_HI_OP "\t.align 0\n\t.word\t" | |
9349 | #undef TARGET_ASM_UNALIGNED_SI_OP | |
9350 | #define TARGET_ASM_UNALIGNED_SI_OP "\t.align 0\n\t.long\t" | |
9351 | #undef TARGET_ASM_UNALIGNED_DI_OP | |
9352 | #define TARGET_ASM_UNALIGNED_DI_OP "\t.align 0\n\t.quad\t" | |
9353 | #endif | |
9354 | ||
9355 | #ifdef OBJECT_FORMAT_ELF | |
9356 | #undef TARGET_ASM_SELECT_RTX_SECTION | |
9357 | #define TARGET_ASM_SELECT_RTX_SECTION alpha_elf_select_rtx_section | |
9358 | #endif | |
9359 | ||
9360 | #undef TARGET_ASM_FUNCTION_END_PROLOGUE | |
9361 | #define TARGET_ASM_FUNCTION_END_PROLOGUE alpha_output_function_end_prologue | |
9362 | ||
f2f543a3 | 9363 | #undef TARGET_INIT_LIBFUNCS |
9364 | #define TARGET_INIT_LIBFUNCS alpha_init_libfuncs | |
9365 | ||
92c473b8 | 9366 | #if TARGET_ABI_UNICOSMK |
9367 | #undef TARGET_ASM_FILE_START | |
9368 | #define TARGET_ASM_FILE_START unicosmk_file_start | |
9369 | #undef TARGET_ASM_FILE_END | |
9370 | #define TARGET_ASM_FILE_END unicosmk_file_end | |
9371 | #else | |
9372 | #undef TARGET_ASM_FILE_START | |
9373 | #define TARGET_ASM_FILE_START alpha_file_start | |
9374 | #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE | |
9375 | #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true | |
9376 | #endif | |
9377 | ||
92643d95 | 9378 | #undef TARGET_SCHED_ADJUST_COST |
9379 | #define TARGET_SCHED_ADJUST_COST alpha_adjust_cost | |
9380 | #undef TARGET_SCHED_ISSUE_RATE | |
9381 | #define TARGET_SCHED_ISSUE_RATE alpha_issue_rate | |
92643d95 | 9382 | #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD |
9383 | #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \ | |
9384 | alpha_multipass_dfa_lookahead | |
9385 | ||
9386 | #undef TARGET_HAVE_TLS | |
9387 | #define TARGET_HAVE_TLS HAVE_AS_TLS | |
9388 | ||
9389 | #undef TARGET_INIT_BUILTINS | |
9390 | #define TARGET_INIT_BUILTINS alpha_init_builtins | |
9391 | #undef TARGET_EXPAND_BUILTIN | |
9392 | #define TARGET_EXPAND_BUILTIN alpha_expand_builtin | |
9393 | ||
9394 | #undef TARGET_FUNCTION_OK_FOR_SIBCALL | |
9395 | #define TARGET_FUNCTION_OK_FOR_SIBCALL alpha_function_ok_for_sibcall | |
9396 | #undef TARGET_CANNOT_COPY_INSN_P | |
9397 | #define TARGET_CANNOT_COPY_INSN_P alpha_cannot_copy_insn_p | |
c0da4391 | 9398 | #undef TARGET_CANNOT_FORCE_CONST_MEM |
9399 | #define TARGET_CANNOT_FORCE_CONST_MEM alpha_cannot_force_const_mem | |
92643d95 | 9400 | |
9401 | #if TARGET_ABI_OSF | |
9402 | #undef TARGET_ASM_OUTPUT_MI_THUNK | |
9403 | #define TARGET_ASM_OUTPUT_MI_THUNK alpha_output_mi_thunk_osf | |
9404 | #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK | |
9405 | #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true | |
9406 | #endif | |
9407 | ||
9408 | #undef TARGET_RTX_COSTS | |
9409 | #define TARGET_RTX_COSTS alpha_rtx_costs | |
9410 | #undef TARGET_ADDRESS_COST | |
9411 | #define TARGET_ADDRESS_COST hook_int_rtx_0 | |
9412 | ||
9413 | #undef TARGET_MACHINE_DEPENDENT_REORG | |
9414 | #define TARGET_MACHINE_DEPENDENT_REORG alpha_reorg | |
9415 | ||
dd9f3024 | 9416 | #undef TARGET_PROMOTE_FUNCTION_ARGS |
9417 | #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true | |
9418 | #undef TARGET_PROMOTE_FUNCTION_RETURN | |
9419 | #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true | |
9420 | #undef TARGET_PROMOTE_PROTOTYPES | |
9421 | #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_false | |
dd9f3024 | 9422 | #undef TARGET_RETURN_IN_MEMORY |
9423 | #define TARGET_RETURN_IN_MEMORY alpha_return_in_memory | |
b981d932 | 9424 | #undef TARGET_PASS_BY_REFERENCE |
9425 | #define TARGET_PASS_BY_REFERENCE alpha_pass_by_reference | |
dd9f3024 | 9426 | #undef TARGET_SETUP_INCOMING_VARARGS |
9427 | #define TARGET_SETUP_INCOMING_VARARGS alpha_setup_incoming_varargs | |
9428 | #undef TARGET_STRICT_ARGUMENT_NAMING | |
9429 | #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true | |
9430 | #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED | |
9431 | #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true | |
92d40bc4 | 9432 | #undef TARGET_SPLIT_COMPLEX_ARG |
9433 | #define TARGET_SPLIT_COMPLEX_ARG alpha_split_complex_arg | |
de8f9b94 | 9434 | #undef TARGET_GIMPLIFY_VA_ARG_EXPR |
9435 | #define TARGET_GIMPLIFY_VA_ARG_EXPR alpha_gimplify_va_arg | |
b2aef146 | 9436 | |
9437 | #undef TARGET_SCALAR_MODE_SUPPORTED_P | |
9438 | #define TARGET_SCALAR_MODE_SUPPORTED_P alpha_scalar_mode_supported_p | |
9e7454d0 | 9439 | #undef TARGET_VECTOR_MODE_SUPPORTED_P |
9440 | #define TARGET_VECTOR_MODE_SUPPORTED_P alpha_vector_mode_supported_p | |
dd9f3024 | 9441 | |
2e15d750 | 9442 | #undef TARGET_BUILD_BUILTIN_VA_LIST |
9443 | #define TARGET_BUILD_BUILTIN_VA_LIST alpha_build_builtin_va_list | |
9444 | ||
92643d95 | 9445 | struct gcc_target targetm = TARGET_INITIALIZER; |
9446 | ||
9447 | \f | |
1f3233d1 | 9448 | #include "gt-alpha.h" |