]>
Commit | Line | Data |
---|---|---|
1a94ca49 | 1 | /* Definitions of target machine for GNU compiler, for DEC Alpha. |
5624e564 | 2 | Copyright (C) 1992-2015 Free Software Foundation, Inc. |
1e6c6f11 | 3 | Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) |
1a94ca49 | 4 | |
7ec022b2 | 5 | This file is part of GCC. |
1a94ca49 | 6 | |
7ec022b2 | 7 | GCC is free software; you can redistribute it and/or modify |
1a94ca49 | 8 | it under the terms of the GNU General Public License as published by |
2f83c7d6 | 9 | the Free Software Foundation; either version 3, or (at your option) |
1a94ca49 RK |
10 | any later version. |
11 | ||
7ec022b2 | 12 | GCC is distributed in the hope that it will be useful, |
1a94ca49 RK |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
18 | along with GCC; see the file COPYING3. If not see |
19 | <http://www.gnu.org/licenses/>. */ | |
1a94ca49 | 20 | |
12a41c22 NB |
21 | /* Target CPU builtins. */ |
22 | #define TARGET_CPU_CPP_BUILTINS() \ | |
23 | do \ | |
24 | { \ | |
25 | builtin_define ("__alpha"); \ | |
26 | builtin_define ("__alpha__"); \ | |
27 | builtin_assert ("cpu=alpha"); \ | |
28 | builtin_assert ("machine=alpha"); \ | |
29 | if (TARGET_CIX) \ | |
30 | { \ | |
31 | builtin_define ("__alpha_cix__"); \ | |
32 | builtin_assert ("cpu=cix"); \ | |
33 | } \ | |
34 | if (TARGET_FIX) \ | |
35 | { \ | |
36 | builtin_define ("__alpha_fix__"); \ | |
37 | builtin_assert ("cpu=fix"); \ | |
38 | } \ | |
39 | if (TARGET_BWX) \ | |
40 | { \ | |
41 | builtin_define ("__alpha_bwx__"); \ | |
42 | builtin_assert ("cpu=bwx"); \ | |
43 | } \ | |
44 | if (TARGET_MAX) \ | |
45 | { \ | |
46 | builtin_define ("__alpha_max__"); \ | |
47 | builtin_assert ("cpu=max"); \ | |
48 | } \ | |
8bea7f7c | 49 | if (alpha_cpu == PROCESSOR_EV6) \ |
12a41c22 NB |
50 | { \ |
51 | builtin_define ("__alpha_ev6__"); \ | |
52 | builtin_assert ("cpu=ev6"); \ | |
53 | } \ | |
8bea7f7c | 54 | else if (alpha_cpu == PROCESSOR_EV5) \ |
12a41c22 NB |
55 | { \ |
56 | builtin_define ("__alpha_ev5__"); \ | |
57 | builtin_assert ("cpu=ev5"); \ | |
58 | } \ | |
59 | else /* Presumably ev4. */ \ | |
60 | { \ | |
61 | builtin_define ("__alpha_ev4__"); \ | |
62 | builtin_assert ("cpu=ev4"); \ | |
63 | } \ | |
ac9cfada | 64 | if (TARGET_IEEE || TARGET_IEEE_WITH_INEXACT) \ |
f9ee10ab | 65 | builtin_define ("_IEEE_FP"); \ |
ac9cfada | 66 | if (TARGET_IEEE_WITH_INEXACT) \ |
f9ee10ab | 67 | builtin_define ("_IEEE_FP_INEXACT"); \ |
0f15adbd RH |
68 | if (TARGET_LONG_DOUBLE_128) \ |
69 | builtin_define ("__LONG_DOUBLE_128__"); \ | |
e0322d5c NB |
70 | \ |
71 | /* Macros dependent on the C dialect. */ \ | |
55f49e3d | 72 | SUBTARGET_LANGUAGE_CPP_BUILTINS(); \ |
ac9cfada | 73 | } while (0) |
1a94ca49 | 74 | |
55f49e3d JT |
75 | #ifndef SUBTARGET_LANGUAGE_CPP_BUILTINS |
76 | #define SUBTARGET_LANGUAGE_CPP_BUILTINS() \ | |
77 | do \ | |
78 | { \ | |
79 | if (preprocessing_asm_p ()) \ | |
80 | builtin_define_std ("LANGUAGE_ASSEMBLY"); \ | |
04df6730 | 81 | else if (c_dialect_cxx ()) \ |
55f49e3d JT |
82 | { \ |
83 | builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \ | |
84 | builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \ | |
85 | } \ | |
04df6730 NB |
86 | else \ |
87 | builtin_define_std ("LANGUAGE_C"); \ | |
88 | if (c_dialect_objc ()) \ | |
55f49e3d JT |
89 | { \ |
90 | builtin_define ("__LANGUAGE_OBJECTIVE_C"); \ | |
91 | builtin_define ("__LANGUAGE_OBJECTIVE_C__"); \ | |
92 | } \ | |
93 | } \ | |
94 | while (0) | |
95 | #endif | |
96 | ||
1a94ca49 RK |
97 | /* Run-time compilation parameters selecting different hardware subsets. */ |
98 | ||
f6f6a13c RK |
99 | /* Which processor to schedule for. The cpu attribute defines a list that |
100 | mirrors this list, so changes to alpha.md must be made at the same time. */ | |
101 | ||
102 | enum processor_type | |
3c50106f RH |
103 | { |
104 | PROCESSOR_EV4, /* 2106[46]{a,} */ | |
e9a25f70 | 105 | PROCESSOR_EV5, /* 21164{a,pc,} */ |
3c50106f RH |
106 | PROCESSOR_EV6, /* 21264 */ |
107 | PROCESSOR_MAX | |
108 | }; | |
f6f6a13c RK |
109 | |
110 | extern enum processor_type alpha_cpu; | |
8bea7f7c | 111 | extern enum processor_type alpha_tune; |
f6f6a13c | 112 | |
2bf6230d RK |
113 | enum alpha_trap_precision |
114 | { | |
115 | ALPHA_TP_PROG, /* No precision (default). */ | |
116 | ALPHA_TP_FUNC, /* Trap contained within originating function. */ | |
285a5742 | 117 | ALPHA_TP_INSN /* Instruction accuracy and code is resumption safe. */ |
2bf6230d RK |
118 | }; |
119 | ||
120 | enum alpha_fp_rounding_mode | |
121 | { | |
122 | ALPHA_FPRM_NORM, /* Normal rounding mode. */ | |
123 | ALPHA_FPRM_MINF, /* Round towards minus-infinity. */ | |
285a5742 | 124 | ALPHA_FPRM_CHOP, /* Chopped rounding mode (towards 0). */ |
2bf6230d RK |
125 | ALPHA_FPRM_DYN /* Dynamic rounding mode. */ |
126 | }; | |
127 | ||
128 | enum alpha_fp_trap_mode | |
129 | { | |
285a5742 | 130 | ALPHA_FPTM_N, /* Normal trap mode. */ |
2bf6230d RK |
131 | ALPHA_FPTM_U, /* Underflow traps enabled. */ |
132 | ALPHA_FPTM_SU, /* Software completion, w/underflow traps */ | |
133 | ALPHA_FPTM_SUI /* Software completion, w/underflow & inexact traps */ | |
134 | }; | |
135 | ||
2bf6230d RK |
136 | extern enum alpha_trap_precision alpha_tp; |
137 | extern enum alpha_fp_rounding_mode alpha_fprm; | |
138 | extern enum alpha_fp_trap_mode alpha_fptm; | |
139 | ||
8bea7f7c RH |
140 | /* Invert the easy way to make options work. */ |
141 | #define TARGET_FP (!TARGET_SOFT_FP) | |
8f87939b | 142 | |
9ba3994a | 143 | /* These are for target os support and cannot be changed at runtime. */ |
800d1de1 RH |
144 | #define TARGET_ABI_OPEN_VMS 0 |
145 | #define TARGET_ABI_OSF (!TARGET_ABI_OPEN_VMS) | |
9ba3994a | 146 | |
9c0e94a5 RH |
147 | #ifndef TARGET_CAN_FAULT_IN_PROLOGUE |
148 | #define TARGET_CAN_FAULT_IN_PROLOGUE 0 | |
149 | #endif | |
5495cc55 | 150 | #ifndef TARGET_HAS_XFLOATING_LIBS |
0f15adbd | 151 | #define TARGET_HAS_XFLOATING_LIBS TARGET_LONG_DOUBLE_128 |
5495cc55 | 152 | #endif |
4f1c5cce RH |
153 | #ifndef TARGET_PROFILING_NEEDS_GP |
154 | #define TARGET_PROFILING_NEEDS_GP 0 | |
155 | #endif | |
14291bc7 RH |
156 | #ifndef TARGET_FIXUP_EV5_PREFETCH |
157 | #define TARGET_FIXUP_EV5_PREFETCH 0 | |
158 | #endif | |
6f9b006d RH |
159 | #ifndef HAVE_AS_TLS |
160 | #define HAVE_AS_TLS 0 | |
161 | #endif | |
9ba3994a | 162 | |
8bea7f7c | 163 | #define TARGET_DEFAULT MASK_FPREGS |
1a94ca49 | 164 | |
88681624 ILT |
165 | #ifndef TARGET_CPU_DEFAULT |
166 | #define TARGET_CPU_DEFAULT 0 | |
167 | #endif | |
168 | ||
3a37b08e RH |
169 | #ifndef TARGET_DEFAULT_EXPLICIT_RELOCS |
170 | #ifdef HAVE_AS_EXPLICIT_RELOCS | |
171 | #define TARGET_DEFAULT_EXPLICIT_RELOCS MASK_EXPLICIT_RELOCS | |
8bea7f7c | 172 | #define TARGET_SUPPORT_ARCH 1 |
3a37b08e RH |
173 | #else |
174 | #define TARGET_DEFAULT_EXPLICIT_RELOCS 0 | |
175 | #endif | |
176 | #endif | |
177 | ||
8bea7f7c RH |
178 | #ifndef TARGET_SUPPORT_ARCH |
179 | #define TARGET_SUPPORT_ARCH 0 | |
180 | #endif | |
2bf6230d | 181 | |
7816bea0 DJ |
182 | /* Support for a compile-time default CPU, et cetera. The rules are: |
183 | --with-cpu is ignored if -mcpu is specified. | |
184 | --with-tune is ignored if -mtune is specified. */ | |
185 | #define OPTION_DEFAULT_SPECS \ | |
186 | {"cpu", "%{!mcpu=*:-mcpu=%(VALUE)}" }, \ | |
187 | {"tune", "%{!mtune=*:-mtune=%(VALUE)}" } | |
188 | ||
1a94ca49 RK |
189 | \f |
190 | /* target machine storage layout */ | |
191 | ||
192 | /* Define the size of `int'. The default is the same as the word size. */ | |
193 | #define INT_TYPE_SIZE 32 | |
194 | ||
195 | /* Define the size of `long long'. The default is the twice the word size. */ | |
196 | #define LONG_LONG_TYPE_SIZE 64 | |
197 | ||
198 | /* The two floating-point formats we support are S-floating, which is | |
199 | 4 bytes, and T-floating, which is 8 bytes. `float' is S and `double' | |
200 | and `long double' are T. */ | |
201 | ||
202 | #define FLOAT_TYPE_SIZE 32 | |
203 | #define DOUBLE_TYPE_SIZE 64 | |
0f15adbd RH |
204 | #define LONG_DOUBLE_TYPE_SIZE (TARGET_LONG_DOUBLE_128 ? 128 : 64) |
205 | ||
0f15adbd RH |
206 | /* Work around target_flags dependency in ada/targtyps.c. */ |
207 | #define WIDEST_HARDWARE_FP_SIZE 64 | |
1a94ca49 | 208 | |
5258d7ae RK |
209 | #define WCHAR_TYPE "unsigned int" |
210 | #define WCHAR_TYPE_SIZE 32 | |
1a94ca49 | 211 | |
13d39dbc | 212 | /* Define this macro if it is advisable to hold scalars in registers |
f676971a | 213 | in a wider mode than that declared by the program. In such cases, |
1a94ca49 RK |
214 | the value is constrained to be within the bounds of the declared |
215 | type, but kept valid in the wider mode. The signedness of the | |
216 | extension may differ from that of the type. | |
217 | ||
06d69cd3 RH |
218 | For Alpha, we always store objects in a full register. 32-bit integers |
219 | are always sign-extended, but smaller objects retain their signedness. | |
220 | ||
221 | Note that small vector types can get mapped onto integer modes at the | |
222 | whim of not appearing in alpha-modes.def. We never promoted these | |
c112cf2b | 223 | values before; don't do so now that we've trimmed the set of modes to |
06d69cd3 RH |
224 | those actually implemented in the backend. */ |
225 | ||
226 | #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \ | |
227 | if (GET_MODE_CLASS (MODE) == MODE_INT \ | |
228 | && (TYPE == NULL || TREE_CODE (TYPE) != VECTOR_TYPE) \ | |
229 | && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \ | |
230 | { \ | |
231 | if ((MODE) == SImode) \ | |
232 | (UNSIGNEDP) = 0; \ | |
233 | (MODE) = DImode; \ | |
1a94ca49 RK |
234 | } |
235 | ||
1a94ca49 RK |
236 | /* Define this if most significant bit is lowest numbered |
237 | in instructions that operate on numbered bit-fields. | |
238 | ||
239 | There are no such instructions on the Alpha, but the documentation | |
240 | is little endian. */ | |
241 | #define BITS_BIG_ENDIAN 0 | |
242 | ||
243 | /* Define this if most significant byte of a word is the lowest numbered. | |
244 | This is false on the Alpha. */ | |
245 | #define BYTES_BIG_ENDIAN 0 | |
246 | ||
247 | /* Define this if most significant word of a multiword number is lowest | |
248 | numbered. | |
249 | ||
250 | For Alpha we can decide arbitrarily since there are no machine instructions | |
285a5742 | 251 | for them. Might as well be consistent with bytes. */ |
1a94ca49 RK |
252 | #define WORDS_BIG_ENDIAN 0 |
253 | ||
1a94ca49 RK |
254 | /* Width of a word, in units (bytes). */ |
255 | #define UNITS_PER_WORD 8 | |
256 | ||
257 | /* Width in bits of a pointer. | |
258 | See also the macro `Pmode' defined below. */ | |
259 | #define POINTER_SIZE 64 | |
260 | ||
261 | /* Allocation boundary (in *bits*) for storing arguments in argument list. */ | |
262 | #define PARM_BOUNDARY 64 | |
263 | ||
264 | /* Boundary (in *bits*) on which stack pointer should be aligned. */ | |
e5e10fb4 | 265 | #define STACK_BOUNDARY 128 |
1a94ca49 RK |
266 | |
267 | /* Allocation boundary (in *bits*) for the code of a function. */ | |
c176c051 | 268 | #define FUNCTION_BOUNDARY 32 |
1a94ca49 RK |
269 | |
270 | /* Alignment of field after `int : 0' in a structure. */ | |
271 | #define EMPTY_FIELD_BOUNDARY 64 | |
272 | ||
273 | /* Every structure's size must be a multiple of this. */ | |
274 | #define STRUCTURE_SIZE_BOUNDARY 8 | |
275 | ||
43a88a8c | 276 | /* A bit-field declared as `int' forces `int' alignment for the struct. */ |
8f27fc6b | 277 | #undef PCC_BITFILED_TYPE_MATTERS |
1a94ca49 RK |
278 | #define PCC_BITFIELD_TYPE_MATTERS 1 |
279 | ||
1a94ca49 | 280 | /* No data type wants to be aligned rounder than this. */ |
5495cc55 | 281 | #define BIGGEST_ALIGNMENT 128 |
1a94ca49 | 282 | |
d16fe557 RK |
283 | /* For atomic access to objects, must have at least 32-bit alignment |
284 | unless the machine has byte operations. */ | |
13eb1f7f | 285 | #define MINIMUM_ATOMIC_ALIGNMENT ((unsigned int) (TARGET_BWX ? 8 : 32)) |
d16fe557 | 286 | |
442b1685 RK |
287 | /* Align all constants and variables to at least a word boundary so |
288 | we can pick up pieces of them faster. */ | |
6c174fc0 RH |
289 | /* ??? Only if block-move stuff knows about different source/destination |
290 | alignment. */ | |
291 | #if 0 | |
442b1685 RK |
292 | #define CONSTANT_ALIGNMENT(EXP, ALIGN) MAX ((ALIGN), BITS_PER_WORD) |
293 | #define DATA_ALIGNMENT(EXP, ALIGN) MAX ((ALIGN), BITS_PER_WORD) | |
6c174fc0 | 294 | #endif |
1a94ca49 | 295 | |
825dda42 | 296 | /* Set this nonzero if move instructions will actually fail to work |
1a94ca49 RK |
297 | when given unaligned data. |
298 | ||
299 | Since we get an error message when we do one, call them invalid. */ | |
300 | ||
301 | #define STRICT_ALIGNMENT 1 | |
302 | ||
825dda42 | 303 | /* Set this nonzero if unaligned move instructions are extremely slow. |
1a94ca49 RK |
304 | |
305 | On the Alpha, they trap. */ | |
130d2d72 | 306 | |
e1565e65 | 307 | #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1 |
e2ea71ea | 308 | |
1a94ca49 RK |
309 | /* Standard register usage. */ |
310 | ||
311 | /* Number of actual hardware registers. | |
312 | The hardware registers are assigned numbers for the compiler | |
313 | from 0 to just below FIRST_PSEUDO_REGISTER. | |
314 | All registers that the compiler knows about must be given numbers, | |
315 | even those that are not normally considered general registers. | |
316 | ||
317 | We define all 32 integer registers, even though $31 is always zero, | |
318 | and all 32 floating-point registers, even though $f31 is also | |
319 | always zero. We do not bother defining the FP status register and | |
f676971a | 320 | there are no other registers. |
130d2d72 RK |
321 | |
322 | Since $31 is always zero, we will use register number 31 as the | |
323 | argument pointer. It will never appear in the generated code | |
324 | because we will always be eliminating it in favor of the stack | |
52a69200 RK |
325 | pointer or hardware frame pointer. |
326 | ||
327 | Likewise, we use $f31 for the frame pointer, which will always | |
328 | be eliminated in favor of the hardware frame pointer or the | |
329 | stack pointer. */ | |
1a94ca49 RK |
330 | |
331 | #define FIRST_PSEUDO_REGISTER 64 | |
332 | ||
333 | /* 1 for registers that have pervasive standard uses | |
334 | and are not available for the register allocator. */ | |
335 | ||
336 | #define FIXED_REGISTERS \ | |
337 | {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
338 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, \ | |
339 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
340 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 } | |
341 | ||
342 | /* 1 for registers not available across function calls. | |
343 | These must include the FIXED_REGISTERS and also any | |
344 | registers that can be used without being saved. | |
345 | The latter must include the registers where values are returned | |
346 | and the register where structure-value addresses are passed. | |
347 | Aside from that, you can include as many other registers as you like. */ | |
348 | #define CALL_USED_REGISTERS \ | |
349 | {1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, \ | |
350 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, \ | |
351 | 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, \ | |
352 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 } | |
353 | ||
354 | /* List the order in which to allocate registers. Each register must be | |
ad5d827d RH |
355 | listed once, even those in FIXED_REGISTERS. */ |
356 | ||
357 | #define REG_ALLOC_ORDER { \ | |
358 | 1, 2, 3, 4, 5, 6, 7, 8, /* nonsaved integer registers */ \ | |
359 | 22, 23, 24, 25, 28, /* likewise */ \ | |
360 | 0, /* likewise, but return value */ \ | |
361 | 21, 20, 19, 18, 17, 16, /* likewise, but input args */ \ | |
362 | 27, /* likewise, but OSF procedure value */ \ | |
363 | \ | |
364 | 42, 43, 44, 45, 46, 47, /* nonsaved floating-point registers */ \ | |
365 | 54, 55, 56, 57, 58, 59, /* likewise */ \ | |
366 | 60, 61, 62, /* likewise */ \ | |
367 | 32, 33, /* likewise, but return values */ \ | |
368 | 53, 52, 51, 50, 49, 48, /* likewise, but input args */ \ | |
369 | \ | |
370 | 9, 10, 11, 12, 13, 14, /* saved integer registers */ \ | |
371 | 26, /* return address */ \ | |
372 | 15, /* hard frame pointer */ \ | |
373 | \ | |
374 | 34, 35, 36, 37, 38, 39, /* saved floating-point registers */ \ | |
375 | 40, 41, /* likewise */ \ | |
376 | \ | |
377 | 29, 30, 31, 63 /* gp, sp, ap, sfp */ \ | |
378 | } | |
1a94ca49 RK |
379 | |
380 | /* Return number of consecutive hard regs needed starting at reg REGNO | |
381 | to hold something of mode MODE. | |
382 | This is ordinarily the length in words of a value of mode MODE | |
383 | but can be less for certain modes in special long registers. */ | |
384 | ||
385 | #define HARD_REGNO_NREGS(REGNO, MODE) \ | |
386 | ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) | |
387 | ||
388 | /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. | |
389 | On Alpha, the integer registers can hold any mode. The floating-point | |
5c9948f4 | 390 | registers can hold 64-bit integers as well, but not smaller values. */ |
1a94ca49 | 391 | |
e6a8ebb4 | 392 | #define HARD_REGNO_MODE_OK(REGNO, MODE) \ |
7d83f4f5 | 393 | (IN_RANGE ((REGNO), 32, 62) \ |
5c9948f4 | 394 | ? (MODE) == SFmode || (MODE) == DFmode || (MODE) == DImode \ |
d416c0b3 | 395 | || (MODE) == SCmode || (MODE) == DCmode \ |
e6a8ebb4 RH |
396 | : 1) |
397 | ||
398 | /* A C expression that is nonzero if a value of mode | |
399 | MODE1 is accessible in mode MODE2 without copying. | |
1a94ca49 | 400 | |
e6a8ebb4 RH |
401 | This asymmetric test is true when MODE1 could be put |
402 | in an FP register but MODE2 could not. */ | |
1a94ca49 | 403 | |
a7adf08e | 404 | #define MODES_TIEABLE_P(MODE1, MODE2) \ |
e6a8ebb4 RH |
405 | (HARD_REGNO_MODE_OK (32, (MODE1)) \ |
406 | ? HARD_REGNO_MODE_OK (32, (MODE2)) \ | |
a7adf08e | 407 | : 1) |
1a94ca49 RK |
408 | |
409 | /* Specify the registers used for certain standard purposes. | |
410 | The values of these macros are register numbers. */ | |
411 | ||
412 | /* Alpha pc isn't overloaded on a register that the compiler knows about. */ | |
413 | /* #define PC_REGNUM */ | |
414 | ||
415 | /* Register to use for pushing function arguments. */ | |
416 | #define STACK_POINTER_REGNUM 30 | |
417 | ||
418 | /* Base register for access to local variables of the function. */ | |
52a69200 | 419 | #define HARD_FRAME_POINTER_REGNUM 15 |
1a94ca49 | 420 | |
1a94ca49 | 421 | /* Base register for access to arguments of the function. */ |
130d2d72 | 422 | #define ARG_POINTER_REGNUM 31 |
1a94ca49 | 423 | |
52a69200 RK |
424 | /* Base register for access to local variables of function. */ |
425 | #define FRAME_POINTER_REGNUM 63 | |
426 | ||
f676971a | 427 | /* Register in which static-chain is passed to a function. |
1a94ca49 RK |
428 | |
429 | For the Alpha, this is based on an example; the calling sequence | |
430 | doesn't seem to specify this. */ | |
431 | #define STATIC_CHAIN_REGNUM 1 | |
432 | ||
133d3133 RH |
433 | /* The register number of the register used to address a table of |
434 | static data addresses in memory. */ | |
435 | #define PIC_OFFSET_TABLE_REGNUM 29 | |
436 | ||
437 | /* Define this macro if the register defined by `PIC_OFFSET_TABLE_REGNUM' | |
438 | is clobbered by calls. */ | |
439 | /* ??? It is and it isn't. It's required to be valid for a given | |
440 | function when the function returns. It isn't clobbered by | |
441 | current_file functions. Moreover, we do not expose the ldgp | |
442 | until after reload, so we're probably safe. */ | |
443 | /* #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED */ | |
1a94ca49 RK |
444 | \f |
445 | /* Define the classes of registers for register constraints in the | |
446 | machine description. Also define ranges of constants. | |
447 | ||
448 | One of the classes must always be named ALL_REGS and include all hard regs. | |
449 | If there is more than one class, another class must be named NO_REGS | |
450 | and contain no registers. | |
451 | ||
452 | The name GENERAL_REGS must be the name of a class (or an alias for | |
453 | another name such as ALL_REGS). This is the class of registers | |
454 | that is allowed by "g" or "r" in a register constraint. | |
455 | Also, registers outside this class are allocated only when | |
456 | instructions express preferences for them. | |
457 | ||
458 | The classes must be numbered in nondecreasing order; that is, | |
459 | a larger-numbered class must never be contained completely | |
460 | in a smaller-numbered class. | |
461 | ||
462 | For any two classes, it is very desirable that there be another | |
463 | class that represents their union. */ | |
f676971a | 464 | |
b73c0bc8 | 465 | enum reg_class { |
6f9b006d | 466 | NO_REGS, R0_REG, R24_REG, R25_REG, R27_REG, |
b73c0bc8 RH |
467 | GENERAL_REGS, FLOAT_REGS, ALL_REGS, |
468 | LIM_REG_CLASSES | |
469 | }; | |
1a94ca49 RK |
470 | |
471 | #define N_REG_CLASSES (int) LIM_REG_CLASSES | |
472 | ||
285a5742 | 473 | /* Give names of register classes as strings for dump file. */ |
1a94ca49 | 474 | |
6f9b006d RH |
475 | #define REG_CLASS_NAMES \ |
476 | {"NO_REGS", "R0_REG", "R24_REG", "R25_REG", "R27_REG", \ | |
b73c0bc8 | 477 | "GENERAL_REGS", "FLOAT_REGS", "ALL_REGS" } |
1a94ca49 RK |
478 | |
479 | /* Define which registers fit in which classes. | |
480 | This is an initializer for a vector of HARD_REG_SET | |
481 | of length N_REG_CLASSES. */ | |
482 | ||
b73c0bc8 RH |
483 | #define REG_CLASS_CONTENTS \ |
484 | { {0x00000000, 0x00000000}, /* NO_REGS */ \ | |
6f9b006d | 485 | {0x00000001, 0x00000000}, /* R0_REG */ \ |
b73c0bc8 RH |
486 | {0x01000000, 0x00000000}, /* R24_REG */ \ |
487 | {0x02000000, 0x00000000}, /* R25_REG */ \ | |
488 | {0x08000000, 0x00000000}, /* R27_REG */ \ | |
489 | {0xffffffff, 0x80000000}, /* GENERAL_REGS */ \ | |
490 | {0x00000000, 0x7fffffff}, /* FLOAT_REGS */ \ | |
491 | {0xffffffff, 0xffffffff} } | |
1a94ca49 RK |
492 | |
493 | /* The same information, inverted: | |
494 | Return the class number of the smallest class containing | |
495 | reg number REGNO. This could be a conditional expression | |
496 | or could index an array. */ | |
497 | ||
93c89ab3 | 498 | #define REGNO_REG_CLASS(REGNO) \ |
6f9b006d RH |
499 | ((REGNO) == 0 ? R0_REG \ |
500 | : (REGNO) == 24 ? R24_REG \ | |
b73c0bc8 RH |
501 | : (REGNO) == 25 ? R25_REG \ |
502 | : (REGNO) == 27 ? R27_REG \ | |
7d83f4f5 | 503 | : IN_RANGE ((REGNO), 32, 62) ? FLOAT_REGS \ |
93c89ab3 | 504 | : GENERAL_REGS) |
1a94ca49 RK |
505 | |
506 | /* The class value for index registers, and the one for base regs. */ | |
507 | #define INDEX_REG_CLASS NO_REGS | |
508 | #define BASE_REG_CLASS GENERAL_REGS | |
509 | ||
1a94ca49 RK |
510 | /* Given an rtx X being reloaded into a reg required to be |
511 | in class CLASS, return the class of reg to actually use. | |
512 | In general this is just CLASS; but on some machines | |
551cc6fd | 513 | in some cases it is preferable to use a more restrictive class. */ |
1a94ca49 | 514 | |
551cc6fd | 515 | #define PREFERRED_RELOAD_CLASS alpha_preferred_reload_class |
1a94ca49 | 516 | |
1a94ca49 | 517 | /* If we are copying between general and FP registers, we need a memory |
de4abb91 | 518 | location unless the FIX extension is available. */ |
1a94ca49 | 519 | |
e9a25f70 | 520 | #define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \ |
bfd82dbf RK |
521 | (! TARGET_FIX && (((CLASS1) == FLOAT_REGS && (CLASS2) != FLOAT_REGS) \ |
522 | || ((CLASS2) == FLOAT_REGS && (CLASS1) != FLOAT_REGS))) | |
1a94ca49 | 523 | |
acd94aaf RK |
524 | /* Specify the mode to be used for memory when a secondary memory |
525 | location is needed. If MODE is floating-point, use it. Otherwise, | |
526 | widen to a word like the default. This is needed because we always | |
527 | store integers in FP registers in quadword format. This whole | |
528 | area is very tricky! */ | |
529 | #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \ | |
530 | (GET_MODE_CLASS (MODE) == MODE_FLOAT ? (MODE) \ | |
e868b518 | 531 | : GET_MODE_SIZE (MODE) >= 4 ? (MODE) \ |
acd94aaf RK |
532 | : mode_for_size (BITS_PER_WORD, GET_MODE_CLASS (MODE), 0)) |
533 | ||
cff9f8d5 | 534 | /* Return the class of registers that cannot change mode from FROM to TO. */ |
c31dfe4d | 535 | |
b0c42aed JH |
536 | #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ |
537 | (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \ | |
538 | ? reg_classes_intersect_p (FLOAT_REGS, CLASS) : 0) | |
c31dfe4d | 539 | |
1a94ca49 | 540 | /* Define the cost of moving between registers of various classes. Moving |
f676971a | 541 | between FLOAT_REGS and anything else except float regs is expensive. |
1a94ca49 RK |
542 | In fact, we make it quite expensive because we really don't want to |
543 | do these moves unless it is clearly worth it. Optimizations may | |
544 | reduce the impact of not being able to allocate a pseudo to a | |
545 | hard register. */ | |
546 | ||
72910a0b RH |
547 | #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \ |
548 | (((CLASS1) == FLOAT_REGS) == ((CLASS2) == FLOAT_REGS) ? 2 \ | |
549 | : TARGET_FIX ? ((CLASS1) == FLOAT_REGS ? 6 : 8) \ | |
550 | : 4+2*alpha_memory_latency) | |
1a94ca49 RK |
551 | |
552 | /* A C expressions returning the cost of moving data of MODE from a register to | |
553 | or from memory. | |
554 | ||
555 | On the Alpha, bump this up a bit. */ | |
556 | ||
bcbbac26 | 557 | extern int alpha_memory_latency; |
cbd5b9a2 | 558 | #define MEMORY_MOVE_COST(MODE,CLASS,IN) (2*alpha_memory_latency) |
1a94ca49 RK |
559 | |
560 | /* Provide the cost of a branch. Exact meaning under development. */ | |
3a4fd356 | 561 | #define BRANCH_COST(speed_p, predictable_p) 5 |
1a94ca49 RK |
562 | \f |
563 | /* Stack layout; function entry, exit and calling. */ | |
564 | ||
565 | /* Define this if pushing a word on the stack | |
566 | makes the stack pointer a smaller address. */ | |
62f9f30b | 567 | #define STACK_GROWS_DOWNWARD 1 |
1a94ca49 | 568 | |
a4d05547 | 569 | /* Define this to nonzero if the nominal address of the stack frame |
1a94ca49 RK |
570 | is at the high-address end of the local variables; |
571 | that is, each additional local variable allocated | |
572 | goes at a more negative offset in the frame. */ | |
f62c8a5c | 573 | /* #define FRAME_GROWS_DOWNWARD 0 */ |
1a94ca49 RK |
574 | |
575 | /* Offset within stack frame to start allocating local variables at. | |
576 | If FRAME_GROWS_DOWNWARD, this is the offset to the END of the | |
577 | first local allocated. Otherwise, it is the offset to the BEGINNING | |
578 | of the first local allocated. */ | |
579 | ||
52a69200 | 580 | #define STARTING_FRAME_OFFSET 0 |
1a94ca49 RK |
581 | |
582 | /* If we generate an insn to push BYTES bytes, | |
583 | this says how many the stack pointer really advances by. | |
584 | On Alpha, don't define this because there are no push insns. */ | |
585 | /* #define PUSH_ROUNDING(BYTES) */ | |
586 | ||
e008606e RK |
587 | /* Define this to be nonzero if stack checking is built into the ABI. */ |
588 | #define STACK_CHECK_BUILTIN 1 | |
589 | ||
1a94ca49 RK |
590 | /* Define this if the maximum size of all the outgoing args is to be |
591 | accumulated and pushed during the prologue. The amount can be | |
38173d38 | 592 | found in the variable crtl->outgoing_args_size. */ |
f73ad30e | 593 | #define ACCUMULATE_OUTGOING_ARGS 1 |
1a94ca49 RK |
594 | |
595 | /* Offset of first parameter from the argument pointer register value. */ | |
596 | ||
130d2d72 | 597 | #define FIRST_PARM_OFFSET(FNDECL) 0 |
1a94ca49 RK |
598 | |
599 | /* Definitions for register eliminations. | |
600 | ||
978e8952 | 601 | We have two registers that can be eliminated on the Alpha. First, the |
1a94ca49 | 602 | frame pointer register can often be eliminated in favor of the stack |
130d2d72 | 603 | pointer register. Secondly, the argument pointer register can always be |
285a5742 | 604 | eliminated; it is replaced with either the stack or frame pointer. */ |
1a94ca49 RK |
605 | |
606 | /* This is an array of structures. Each structure initializes one pair | |
607 | of eliminable registers. The "from" register number is given first, | |
608 | followed by "to". Eliminations of the same "from" register are listed | |
609 | in order of preference. */ | |
610 | ||
52a69200 RK |
611 | #define ELIMINABLE_REGS \ |
612 | {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
613 | { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ | |
614 | { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
615 | { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} | |
1a94ca49 | 616 | |
52a69200 RK |
617 | /* Round up to a multiple of 16 bytes. */ |
618 | #define ALPHA_ROUND(X) (((X) + 15) & ~ 15) | |
619 | ||
1a94ca49 RK |
620 | /* Define the offset between two registers, one to be eliminated, and the other |
621 | its replacement, at the start of a routine. */ | |
35d9c403 RH |
622 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ |
623 | ((OFFSET) = alpha_initial_elimination_offset(FROM, TO)) | |
1a94ca49 RK |
624 | |
625 | /* Define this if stack space is still allocated for a parameter passed | |
626 | in a register. */ | |
627 | /* #define REG_PARM_STACK_SPACE */ | |
628 | ||
1a94ca49 RK |
629 | /* Define how to find the value returned by a function. |
630 | VALTYPE is the data type of the value (as a tree). | |
631 | If the precise function being called is known, FUNC is its FUNCTION_DECL; | |
632 | otherwise, FUNC is 0. | |
633 | ||
634 | On Alpha the value is found in $0 for integer functions and | |
635 | $f0 for floating-point functions. */ | |
636 | ||
7e4fb06a RH |
637 | #define FUNCTION_VALUE(VALTYPE, FUNC) \ |
638 | function_value (VALTYPE, FUNC, VOIDmode) | |
1a94ca49 RK |
639 | |
640 | /* Define how to find the value returned by a library function | |
641 | assuming the value has mode MODE. */ | |
642 | ||
7e4fb06a RH |
643 | #define LIBCALL_VALUE(MODE) \ |
644 | function_value (NULL, NULL, MODE) | |
1a94ca49 RK |
645 | |
646 | /* 1 if N is a possible register number for a function value | |
647 | as seen by the caller. */ | |
648 | ||
e5958492 RK |
649 | #define FUNCTION_VALUE_REGNO_P(N) \ |
650 | ((N) == 0 || (N) == 1 || (N) == 32 || (N) == 33) | |
1a94ca49 RK |
651 | |
652 | /* 1 if N is a possible register number for function argument passing. | |
653 | On Alpha, these are $16-$21 and $f16-$f21. */ | |
654 | ||
655 | #define FUNCTION_ARG_REGNO_P(N) \ | |
7d83f4f5 | 656 | (IN_RANGE ((N), 16, 21) || ((N) >= 16 + 32 && (N) <= 21 + 32)) |
1a94ca49 RK |
657 | \f |
658 | /* Define a data type for recording info about an argument list | |
659 | during the scan of that argument list. This data type should | |
660 | hold all necessary information about the function itself | |
661 | and about the args processed so far, enough to enable macros | |
662 | such as FUNCTION_ARG to determine where the next arg should go. | |
663 | ||
664 | On Alpha, this is a single integer, which is a number of words | |
665 | of arguments scanned so far. | |
666 | Thus 6 or more means all following args should go on the stack. */ | |
667 | ||
668 | #define CUMULATIVE_ARGS int | |
669 | ||
670 | /* Initialize a variable CUM of type CUMULATIVE_ARGS | |
671 | for a call to a function whose data type is FNTYPE. | |
672 | For a library call, FNTYPE is 0. */ | |
673 | ||
0f6937fe AM |
674 | #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \ |
675 | (CUM) = 0 | |
1a94ca49 RK |
676 | |
677 | /* Define intermediate macro to compute the size (in registers) of an argument | |
678 | for the Alpha. */ | |
679 | ||
680 | #define ALPHA_ARG_SIZE(MODE, TYPE, NAMED) \ | |
5495cc55 RH |
681 | ((MODE) == TFmode || (MODE) == TCmode ? 1 \ |
682 | : (((MODE) == BLKmode ? int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE)) \ | |
683 | + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD) | |
1a94ca49 | 684 | |
e5958492 | 685 | /* Make (or fake) .linkage entry for function call. |
e5958492 | 686 | IS_LOCAL is 0 if name is used in call, 1 if name is used in definition. */ |
e5958492 | 687 | |
bcbbac26 RH |
688 | /* This macro defines the start of an assembly comment. */ |
689 | ||
690 | #define ASM_COMMENT_START " #" | |
691 | ||
acd92049 | 692 | /* This macro produces the initial definition of a function. */ |
1a94ca49 | 693 | |
8f27fc6b | 694 | #undef ASM_DECLARE_FUNCTION_NAME |
acd92049 RH |
695 | #define ASM_DECLARE_FUNCTION_NAME(FILE,NAME,DECL) \ |
696 | alpha_start_function(FILE,NAME,DECL); | |
1a94ca49 | 697 | |
acd92049 | 698 | /* This macro closes up a function definition for the assembler. */ |
9c0e94a5 | 699 | |
8f27fc6b | 700 | #undef ASM_DECLARE_FUNCTION_SIZE |
acd92049 RH |
701 | #define ASM_DECLARE_FUNCTION_SIZE(FILE,NAME,DECL) \ |
702 | alpha_end_function(FILE,NAME,DECL) | |
f676971a | 703 | |
acd92049 RH |
704 | /* Output any profiling code before the prologue. */ |
705 | ||
706 | #define PROFILE_BEFORE_PROLOGUE 1 | |
707 | ||
fbadafbc RH |
708 | /* Never use profile counters. */ |
709 | ||
710 | #define NO_PROFILE_COUNTERS 1 | |
711 | ||
1a94ca49 | 712 | /* Output assembler code to FILE to increment profiler label # LABELNO |
e0fb9029 | 713 | for profiling a function entry. Under OSF/1, profiling is enabled |
ddd5a7c1 | 714 | by simply passing -pg to the assembler and linker. */ |
85d159a3 | 715 | |
e0fb9029 | 716 | #define FUNCTION_PROFILER(FILE, LABELNO) |
85d159a3 | 717 | |
1a94ca49 RK |
718 | /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, |
719 | the stack pointer does not matter. The value is tested only in | |
720 | functions that have frame pointers. | |
721 | No definition is equivalent to always zero. */ | |
722 | ||
723 | #define EXIT_IGNORE_STACK 1 | |
c112e233 RH |
724 | |
725 | /* Define registers used by the epilogue and return instruction. */ | |
726 | ||
727 | #define EPILOGUE_USES(REGNO) ((REGNO) == 26) | |
1a94ca49 | 728 | \f |
1a94ca49 RK |
729 | /* Length in units of the trampoline for entering a nested function. */ |
730 | ||
7981384f | 731 | #define TRAMPOLINE_SIZE 32 |
1a94ca49 | 732 | |
30864e14 RH |
733 | /* The alignment of a trampoline, in bits. */ |
734 | ||
735 | #define TRAMPOLINE_ALIGNMENT 64 | |
736 | ||
675f0e7c RK |
737 | /* A C expression whose value is RTL representing the value of the return |
738 | address for the frame COUNT steps up from the current frame. | |
739 | FRAMEADDR is the frame pointer of the COUNT frame, or the frame pointer of | |
952fc2ed | 740 | the COUNT-1 frame if RETURN_ADDR_IN_PREVIOUS_FRAME is defined. */ |
675f0e7c | 741 | |
9ecc37f0 | 742 | #define RETURN_ADDR_RTX alpha_return_addr |
9ecc37f0 | 743 | |
221cf9ab OH |
744 | /* Provide a definition of DWARF_FRAME_REGNUM here so that fallback unwinders |
745 | can use DWARF_ALT_FRAME_RETURN_COLUMN defined below. This is just the same | |
746 | as the default definition in dwarf2out.c. */ | |
747 | #undef DWARF_FRAME_REGNUM | |
748 | #define DWARF_FRAME_REGNUM(REG) DBX_REGISTER_NUMBER (REG) | |
749 | ||
285a5742 | 750 | /* Before the prologue, RA lives in $26. */ |
6abc6f40 | 751 | #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, 26) |
8034da37 | 752 | #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (26) |
ed80cd68 | 753 | #define DWARF_ALT_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (64) |
282efe1c | 754 | #define DWARF_ZERO_REG 31 |
4573b4de RH |
755 | |
756 | /* Describe how we implement __builtin_eh_return. */ | |
757 | #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 16 : INVALID_REGNUM) | |
758 | #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 28) | |
759 | #define EH_RETURN_HANDLER_RTX \ | |
0a81f074 | 760 | gen_rtx_MEM (Pmode, plus_constant (Pmode, stack_pointer_rtx, \ |
38173d38 | 761 | crtl->outgoing_args_size)) |
675f0e7c | 762 | \f |
1a94ca49 RK |
763 | /* Addressing modes, and classification of registers for them. */ |
764 | ||
1a94ca49 RK |
765 | /* Macros to check register numbers against specific register classes. */ |
766 | ||
767 | /* These assume that REGNO is a hard or pseudo reg number. | |
768 | They give nonzero only if REGNO is a hard reg of the suitable class | |
769 | or a pseudo reg currently allocated to a suitable hard reg. | |
770 | Since they use reg_renumber, they are safe only once reg_renumber | |
aeb9f7cf SB |
771 | has been allocated, which happens in reginfo.c during register |
772 | allocation. */ | |
1a94ca49 RK |
773 | |
774 | #define REGNO_OK_FOR_INDEX_P(REGNO) 0 | |
775 | #define REGNO_OK_FOR_BASE_P(REGNO) \ | |
52a69200 RK |
776 | ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32 \ |
777 | || (REGNO) == 63 || reg_renumber[REGNO] == 63) | |
1a94ca49 RK |
778 | \f |
779 | /* Maximum number of registers that can appear in a valid memory address. */ | |
780 | #define MAX_REGS_PER_ADDRESS 1 | |
781 | ||
782 | /* Recognize any constant value that is a valid address. For the Alpha, | |
783 | there are only constants none since we want to use LDA to load any | |
784 | symbolic addresses into registers. */ | |
785 | ||
786 | #define CONSTANT_ADDRESS_P(X) \ | |
7d83f4f5 | 787 | (CONST_INT_P (X) \ |
1a94ca49 RK |
788 | && (unsigned HOST_WIDE_INT) (INTVAL (X) + 0x8000) < 0x10000) |
789 | ||
1a94ca49 RK |
790 | /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx |
791 | and check its validity for a certain class. | |
792 | We have two alternate definitions for each of them. | |
793 | The usual definition accepts all pseudo regs; the other rejects | |
794 | them unless they have been allocated suitable hard regs. | |
795 | The symbol REG_OK_STRICT causes the latter definition to be used. | |
796 | ||
797 | Most source files want to accept pseudo regs in the hope that | |
798 | they will get allocated to the class that the insn wants them to be in. | |
799 | Source files for reload pass need to be strict. | |
800 | After reload, it makes no difference, since pseudo regs have | |
801 | been eliminated by then. */ | |
802 | ||
1a94ca49 RK |
803 | /* Nonzero if X is a hard reg that can be used as an index |
804 | or if it is a pseudo reg. */ | |
805 | #define REG_OK_FOR_INDEX_P(X) 0 | |
5d02b6c2 | 806 | |
1a94ca49 RK |
807 | /* Nonzero if X is a hard reg that can be used as a base reg |
808 | or if it is a pseudo reg. */ | |
a39bdefc | 809 | #define NONSTRICT_REG_OK_FOR_BASE_P(X) \ |
52a69200 | 810 | (REGNO (X) < 32 || REGNO (X) == 63 || REGNO (X) >= FIRST_PSEUDO_REGISTER) |
1a94ca49 | 811 | |
5d02b6c2 RH |
812 | /* ??? Nonzero if X is the frame pointer, or some virtual register |
813 | that may eliminate to the frame pointer. These will be allowed to | |
814 | have offsets greater than 32K. This is done because register | |
815 | elimination offsets will change the hi/lo split, and if we split | |
285a5742 | 816 | before reload, we will require additional instructions. */ |
a39bdefc | 817 | #define NONSTRICT_REG_OK_FP_BASE_P(X) \ |
5d02b6c2 RH |
818 | (REGNO (X) == 31 || REGNO (X) == 63 \ |
819 | || (REGNO (X) >= FIRST_PSEUDO_REGISTER \ | |
32990d5b | 820 | && REGNO (X) < LAST_VIRTUAL_POINTER_REGISTER)) |
5d02b6c2 | 821 | |
1a94ca49 | 822 | /* Nonzero if X is a hard reg that can be used as a base reg. */ |
a39bdefc | 823 | #define STRICT_REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) |
5d02b6c2 | 824 | |
a39bdefc RH |
825 | #ifdef REG_OK_STRICT |
826 | #define REG_OK_FOR_BASE_P(X) STRICT_REG_OK_FOR_BASE_P (X) | |
827 | #else | |
828 | #define REG_OK_FOR_BASE_P(X) NONSTRICT_REG_OK_FOR_BASE_P (X) | |
1a94ca49 RK |
829 | #endif |
830 | \f | |
a9a2595b JR |
831 | /* Try a machine-dependent way of reloading an illegitimate address |
832 | operand. If we find one, push the reload and jump to WIN. This | |
aead1ca3 | 833 | macro is used in only one place: `find_reloads_address' in reload.c. */ |
f676971a | 834 | |
aead1ca3 RH |
835 | #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_L,WIN) \ |
836 | do { \ | |
837 | rtx new_x = alpha_legitimize_reload_address (X, MODE, OPNUM, TYPE, IND_L); \ | |
838 | if (new_x) \ | |
839 | { \ | |
840 | X = new_x; \ | |
841 | goto WIN; \ | |
842 | } \ | |
a9a2595b JR |
843 | } while (0) |
844 | ||
1a94ca49 RK |
845 | \f |
846 | /* Specify the machine mode that this machine uses | |
847 | for the index in the tablejump instruction. */ | |
848 | #define CASE_VECTOR_MODE SImode | |
849 | ||
18543a22 ILT |
850 | /* Define as C expression which evaluates to nonzero if the tablejump |
851 | instruction expects the table to contain offsets from the address of the | |
3aa9d5b6 | 852 | table. |
b0435cf4 | 853 | |
3aa9d5b6 | 854 | Do not define this if the table should contain absolute addresses. |
260ced47 RK |
855 | On the Alpha, the table is really GP-relative, not relative to the PC |
856 | of the table, but we pretend that it is PC-relative; this should be OK, | |
0076aa6b | 857 | but we should try to find some better way sometime. */ |
18543a22 | 858 | #define CASE_VECTOR_PC_RELATIVE 1 |
1a94ca49 | 859 | |
1a94ca49 RK |
860 | /* Define this as 1 if `char' should by default be signed; else as 0. */ |
861 | #define DEFAULT_SIGNED_CHAR 1 | |
862 | ||
1a94ca49 RK |
863 | /* Max number of bytes we can move to or from memory |
864 | in one reasonably fast instruction. */ | |
865 | ||
866 | #define MOVE_MAX 8 | |
867 | ||
7e24ffc9 | 868 | /* If a memory-to-memory move would take MOVE_RATIO or more simple |
70128ad9 | 869 | move-instruction pairs, we will do a movmem or libcall instead. |
7e24ffc9 HPN |
870 | |
871 | Without byte/word accesses, we want no more than four instructions; | |
285a5742 | 872 | with, several single byte accesses are better. */ |
6c174fc0 | 873 | |
e04ad03d | 874 | #define MOVE_RATIO(speed) (TARGET_BWX ? 7 : 2) |
6c174fc0 | 875 | |
1a94ca49 RK |
876 | /* Largest number of bytes of an object that can be placed in a register. |
877 | On the Alpha we have plenty of registers, so use TImode. */ | |
878 | #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TImode) | |
879 | ||
880 | /* Nonzero if access to memory by bytes is no faster than for words. | |
825dda42 | 881 | Also nonzero if doing byte operations (specifically shifts) in registers |
f676971a | 882 | is undesirable. |
1a94ca49 RK |
883 | |
884 | On the Alpha, we want to not use the byte operation and instead use | |
885 | masking operations to access fields; these will save instructions. */ | |
886 | ||
887 | #define SLOW_BYTE_ACCESS 1 | |
888 | ||
9a63901f RK |
889 | /* Define if operations between registers always perform the operation |
890 | on the full register even if a narrower mode is specified. */ | |
891 | #define WORD_REGISTER_OPERATIONS | |
892 | ||
893 | /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD | |
894 | will either zero-extend or sign-extend. The value of this macro should | |
895 | be the code that says which one of the two operations is implicitly | |
f822d252 | 896 | done, UNKNOWN if none. */ |
b7747781 | 897 | #define LOAD_EXTEND_OP(MODE) ((MODE) == SImode ? SIGN_EXTEND : ZERO_EXTEND) |
1a94ca49 | 898 | |
225211e2 | 899 | /* Define if loading short immediate values into registers sign extends. */ |
58f2ae18 | 900 | #define SHORT_IMMEDIATES_SIGN_EXTEND 1 |
225211e2 | 901 | |
1a94ca49 RK |
902 | /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits |
903 | is done just by pretending it is already truncated. */ | |
904 | #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 | |
905 | ||
7dba8395 | 906 | /* The CIX ctlz and cttz instructions return 64 for zero. */ |
1068ced5 MP |
907 | #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 64, \ |
908 | TARGET_CIX ? 1 : 0) | |
909 | #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 64, \ | |
910 | TARGET_CIX ? 1 : 0) | |
7dba8395 | 911 | |
1a94ca49 RK |
912 | /* Define the value returned by a floating-point comparison instruction. */ |
913 | ||
12530dbe RH |
914 | #define FLOAT_STORE_FLAG_VALUE(MODE) \ |
915 | REAL_VALUE_ATOF ((TARGET_FLOAT_VAX ? "0.5" : "2.0"), (MODE)) | |
1a94ca49 RK |
916 | |
917 | /* Specify the machine mode that pointers have. | |
918 | After generation of rtl, the compiler makes no further distinction | |
919 | between pointers and any other objects of this machine mode. */ | |
920 | #define Pmode DImode | |
921 | ||
285a5742 | 922 | /* Mode of a function address in a call instruction (for indexing purposes). */ |
1a94ca49 RK |
923 | |
924 | #define FUNCTION_MODE Pmode | |
925 | ||
926 | /* Define this if addresses of constant functions | |
927 | shouldn't be put through pseudo regs where they can be cse'd. | |
928 | Desirable on machines where ordinary constants are expensive | |
929 | but a CALL with constant address is cheap. | |
930 | ||
931 | We define this on the Alpha so that gen_call and gen_call_value | |
932 | get to see the SYMBOL_REF (for the hint field of the jsr). It will | |
933 | then copy it into a register, thus actually letting the address be | |
934 | cse'ed. */ | |
935 | ||
1e8552c2 | 936 | #define NO_FUNCTION_CSE 1 |
1a94ca49 | 937 | |
d969caf8 | 938 | /* Define this to be nonzero if shift instructions ignore all but the low-order |
285a5742 | 939 | few bits. */ |
d969caf8 | 940 | #define SHIFT_COUNT_TRUNCATED 1 |
1a94ca49 RK |
941 | \f |
942 | /* Control the assembler format that we output. */ | |
943 | ||
1a94ca49 RK |
944 | /* Output to assembler file text saying following lines |
945 | may contain character constants, extra white space, comments, etc. */ | |
1eb356b9 | 946 | #define ASM_APP_ON (TARGET_EXPLICIT_RELOCS ? "\t.set\tmacro\n" : "") |
1a94ca49 RK |
947 | |
948 | /* Output to assembler file text saying following lines | |
949 | no longer contain unusual constructs. */ | |
1eb356b9 | 950 | #define ASM_APP_OFF (TARGET_EXPLICIT_RELOCS ? "\t.set\tnomacro\n" : "") |
1a94ca49 | 951 | |
93de6f51 | 952 | #define TEXT_SECTION_ASM_OP "\t.text" |
1a94ca49 | 953 | |
1a94ca49 RK |
954 | /* Output before writable data. */ |
955 | ||
93de6f51 | 956 | #define DATA_SECTION_ASM_OP "\t.data" |
1a94ca49 | 957 | |
1a94ca49 RK |
958 | /* How to refer to registers in assembler output. |
959 | This sequence is indexed by compiler's hard-register-number (see above). */ | |
960 | ||
961 | #define REGISTER_NAMES \ | |
962 | {"$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", "$8", \ | |
963 | "$9", "$10", "$11", "$12", "$13", "$14", "$15", \ | |
964 | "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \ | |
130d2d72 | 965 | "$24", "$25", "$26", "$27", "$28", "$29", "$30", "AP", \ |
1a94ca49 RK |
966 | "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", "$f8", \ |
967 | "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \ | |
968 | "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",\ | |
52a69200 | 969 | "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "FP"} |
1a94ca49 | 970 | |
1eb356b9 RH |
971 | /* Strip name encoding when emitting labels. */ |
972 | ||
973 | #define ASM_OUTPUT_LABELREF(STREAM, NAME) \ | |
974 | do { \ | |
975 | const char *name_ = NAME; \ | |
53e8b0b8 | 976 | if (*name_ == '@' || *name_ == '%') \ |
1eb356b9 RH |
977 | name_ += 2; \ |
978 | if (*name_ == '*') \ | |
979 | name_++; \ | |
980 | else \ | |
981 | fputs (user_label_prefix, STREAM); \ | |
982 | fputs (name_, STREAM); \ | |
983 | } while (0) | |
984 | ||
506a61b1 KG |
985 | /* Globalizing directive for a label. */ |
986 | #define GLOBAL_ASM_OP "\t.globl " | |
1a94ca49 | 987 | |
8f27fc6b | 988 | /* Use dollar signs rather than periods in special g++ assembler names. */ |
1a94ca49 | 989 | |
8f27fc6b | 990 | #undef NO_DOLLAR_IN_LABEL |
1a94ca49 RK |
991 | |
992 | /* This is how to store into the string LABEL | |
993 | the symbol_ref name of an internal numbered label where | |
994 | PREFIX is the class of label and NUM is the number within the class. | |
995 | This is suitable for output with `assemble_name'. */ | |
996 | ||
8f27fc6b | 997 | #undef ASM_GENERATE_INTERNAL_LABEL |
1a94ca49 | 998 | #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ |
d1e6b55b | 999 | sprintf ((LABEL), "*$%s%ld", (PREFIX), (long)(NUM)) |
1a94ca49 | 1000 | |
260ced47 | 1001 | /* This is how to output an element of a case-vector that is relative. */ |
1a94ca49 | 1002 | |
33f7f353 | 1003 | #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ |
800d1de1 | 1004 | fprintf (FILE, "\t.gprel32 $L%d\n", (VALUE)) |
60593797 | 1005 | \f |
9ec36da5 | 1006 | |
1a94ca49 RK |
1007 | /* Print operand X (an rtx) in assembler syntax to file FILE. |
1008 | CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. | |
1009 | For `%' followed by punctuation, CODE is the punctuation and X is null. */ | |
1010 | ||
1011 | #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) | |
1012 | ||
1013 | /* Determine which codes are valid without a following integer. These must | |
941cc05a RK |
1014 | not be alphabetic. |
1015 | ||
1016 | ~ Generates the name of the current function. | |
2bf6230d | 1017 | |
be7560ea RH |
1018 | / Generates the instruction suffix. The TRAP_SUFFIX and ROUND_SUFFIX |
1019 | attributes are examined to determine what is appropriate. | |
e5958492 RK |
1020 | |
1021 | , Generates single precision suffix for floating point | |
1022 | instructions (s for IEEE, f for VAX) | |
1023 | ||
1024 | - Generates double precision suffix for floating point | |
1025 | instructions (t for IEEE, g for VAX) | |
2bf6230d | 1026 | */ |
1a94ca49 | 1027 | |
be7560ea | 1028 | #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ |
1eb356b9 | 1029 | ((CODE) == '/' || (CODE) == ',' || (CODE) == '-' || (CODE) == '~' \ |
e4bec638 | 1030 | || (CODE) == '#' || (CODE) == '*' || (CODE) == '&') |
201312c2 | 1031 | |
1a94ca49 RK |
1032 | /* Print a memory address as an operand to reference that memory location. */ |
1033 | ||
714b019c RH |
1034 | #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ |
1035 | print_operand_address((FILE), (ADDR)) | |
03f8c4cc | 1036 | \f |
34fa88ab RK |
1037 | /* If we use NM, pass -g to it so it only lists globals. */ |
1038 | #define NM_FLAGS "-pg" | |
1039 | ||
03f8c4cc RK |
1040 | /* Definitions for debugging. */ |
1041 | ||
03f8c4cc RK |
1042 | /* Correct the offset of automatic variables and arguments. Note that |
1043 | the Alpha debug format wants all automatic variables and arguments | |
1044 | to be in terms of two different offsets from the virtual frame pointer, | |
1045 | which is the stack pointer before any adjustment in the function. | |
1046 | The offset for the argument pointer is fixed for the native compiler, | |
1047 | it is either zero (for the no arguments case) or large enough to hold | |
1048 | all argument registers. | |
1049 | The offset for the auto pointer is the fourth argument to the .frame | |
1050 | directive (local_offset). | |
1051 | To stay compatible with the native tools we use the same offsets | |
1052 | from the virtual frame pointer and adjust the debugger arg/auto offsets | |
1053 | accordingly. These debugger offsets are set up in output_prolog. */ | |
1054 | ||
9a0b18f2 RK |
1055 | extern long alpha_arg_offset; |
1056 | extern long alpha_auto_offset; | |
03f8c4cc RK |
1057 | #define DEBUGGER_AUTO_OFFSET(X) \ |
1058 | ((GET_CODE (X) == PLUS ? INTVAL (XEXP (X, 1)) : 0) + alpha_auto_offset) | |
1059 | #define DEBUGGER_ARG_OFFSET(OFFSET, X) (OFFSET + alpha_arg_offset) | |
1060 | ||
03f8c4cc RK |
1061 | #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \ |
1062 | alpha_output_filename (STREAM, NAME) | |
03f8c4cc | 1063 | |
03f8c4cc RK |
1064 | /* By default, turn on GDB extensions. */ |
1065 | #define DEFAULT_GDB_EXTENSIONS 1 | |
1066 | ||
b0435cf4 RH |
1067 | /* The system headers under Alpha systems are generally C++-aware. */ |
1068 | #define NO_IMPLICIT_EXTERN_C | |
f06ed650 UB |
1069 | |
1070 | #define TARGET_SUPPORTS_WIDE_INT 1 |