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1a94ca49 | 1 | /* Definitions of target machine for GNU compiler, for DEC Alpha. |
9ddd9abd | 2 | Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, |
16c484c7 | 3 | 2000, 2001, 2002 Free Software Foundation, Inc. |
1e6c6f11 | 4 | Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) |
1a94ca49 RK |
5 | |
6 | This file is part of GNU CC. | |
7 | ||
8 | GNU CC is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2, or (at your option) | |
11 | any later version. | |
12 | ||
13 | GNU CC is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with GNU CC; see the file COPYING. If not, write to | |
38ead7f3 RK |
20 | the Free Software Foundation, 59 Temple Place - Suite 330, |
21 | Boston, MA 02111-1307, USA. */ | |
1a94ca49 | 22 | |
12a41c22 NB |
23 | /* Target CPU builtins. */ |
24 | #define TARGET_CPU_CPP_BUILTINS() \ | |
25 | do \ | |
26 | { \ | |
27 | builtin_define ("__alpha"); \ | |
28 | builtin_define ("__alpha__"); \ | |
29 | builtin_assert ("cpu=alpha"); \ | |
30 | builtin_assert ("machine=alpha"); \ | |
31 | if (TARGET_CIX) \ | |
32 | { \ | |
33 | builtin_define ("__alpha_cix__"); \ | |
34 | builtin_assert ("cpu=cix"); \ | |
35 | } \ | |
36 | if (TARGET_FIX) \ | |
37 | { \ | |
38 | builtin_define ("__alpha_fix__"); \ | |
39 | builtin_assert ("cpu=fix"); \ | |
40 | } \ | |
41 | if (TARGET_BWX) \ | |
42 | { \ | |
43 | builtin_define ("__alpha_bwx__"); \ | |
44 | builtin_assert ("cpu=bwx"); \ | |
45 | } \ | |
46 | if (TARGET_MAX) \ | |
47 | { \ | |
48 | builtin_define ("__alpha_max__"); \ | |
49 | builtin_assert ("cpu=max"); \ | |
50 | } \ | |
51 | if (TARGET_CPU_EV6) \ | |
52 | { \ | |
53 | builtin_define ("__alpha_ev6__"); \ | |
54 | builtin_assert ("cpu=ev6"); \ | |
55 | } \ | |
56 | else if (TARGET_CPU_EV5) \ | |
57 | { \ | |
58 | builtin_define ("__alpha_ev5__"); \ | |
59 | builtin_assert ("cpu=ev5"); \ | |
60 | } \ | |
61 | else /* Presumably ev4. */ \ | |
62 | { \ | |
63 | builtin_define ("__alpha_ev4__"); \ | |
64 | builtin_assert ("cpu=ev4"); \ | |
65 | } \ | |
ac9cfada | 66 | if (TARGET_IEEE || TARGET_IEEE_WITH_INEXACT) \ |
f9ee10ab | 67 | builtin_define ("_IEEE_FP"); \ |
ac9cfada | 68 | if (TARGET_IEEE_WITH_INEXACT) \ |
f9ee10ab | 69 | builtin_define ("_IEEE_FP_INEXACT"); \ |
e0322d5c NB |
70 | \ |
71 | /* Macros dependent on the C dialect. */ \ | |
55f49e3d | 72 | SUBTARGET_LANGUAGE_CPP_BUILTINS(); \ |
ac9cfada | 73 | } while (0) |
1a94ca49 | 74 | |
55f49e3d JT |
75 | #ifndef SUBTARGET_LANGUAGE_CPP_BUILTINS |
76 | #define SUBTARGET_LANGUAGE_CPP_BUILTINS() \ | |
77 | do \ | |
78 | { \ | |
79 | if (preprocessing_asm_p ()) \ | |
80 | builtin_define_std ("LANGUAGE_ASSEMBLY"); \ | |
81 | else if (c_language == clk_c) \ | |
82 | builtin_define_std ("LANGUAGE_C"); \ | |
83 | else if (c_language == clk_cplusplus) \ | |
84 | { \ | |
85 | builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \ | |
86 | builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \ | |
87 | } \ | |
88 | if (flag_objc) \ | |
89 | { \ | |
90 | builtin_define ("__LANGUAGE_OBJECTIVE_C"); \ | |
91 | builtin_define ("__LANGUAGE_OBJECTIVE_C__"); \ | |
92 | } \ | |
93 | } \ | |
94 | while (0) | |
95 | #endif | |
96 | ||
e0322d5c | 97 | #define CPP_SPEC "%(cpp_subtarget)" |
952fc2ed RH |
98 | |
99 | #ifndef CPP_SUBTARGET_SPEC | |
100 | #define CPP_SUBTARGET_SPEC "" | |
101 | #endif | |
1a94ca49 | 102 | |
b890f297 | 103 | #define WORD_SWITCH_TAKES_ARG(STR) \ |
2efe55c1 | 104 | (!strcmp (STR, "rpath") || DEFAULT_WORD_SWITCH_TAKES_ARG(STR)) |
8877eb00 | 105 | |
1a94ca49 RK |
106 | /* Print subsidiary information on the compiler version in use. */ |
107 | #define TARGET_VERSION | |
108 | ||
1a94ca49 RK |
109 | /* Run-time compilation parameters selecting different hardware subsets. */ |
110 | ||
f6f6a13c RK |
111 | /* Which processor to schedule for. The cpu attribute defines a list that |
112 | mirrors this list, so changes to alpha.md must be made at the same time. */ | |
113 | ||
114 | enum processor_type | |
3c50106f RH |
115 | { |
116 | PROCESSOR_EV4, /* 2106[46]{a,} */ | |
e9a25f70 | 117 | PROCESSOR_EV5, /* 21164{a,pc,} */ |
3c50106f RH |
118 | PROCESSOR_EV6, /* 21264 */ |
119 | PROCESSOR_MAX | |
120 | }; | |
f6f6a13c RK |
121 | |
122 | extern enum processor_type alpha_cpu; | |
123 | ||
2bf6230d RK |
124 | enum alpha_trap_precision |
125 | { | |
126 | ALPHA_TP_PROG, /* No precision (default). */ | |
127 | ALPHA_TP_FUNC, /* Trap contained within originating function. */ | |
285a5742 | 128 | ALPHA_TP_INSN /* Instruction accuracy and code is resumption safe. */ |
2bf6230d RK |
129 | }; |
130 | ||
131 | enum alpha_fp_rounding_mode | |
132 | { | |
133 | ALPHA_FPRM_NORM, /* Normal rounding mode. */ | |
134 | ALPHA_FPRM_MINF, /* Round towards minus-infinity. */ | |
285a5742 | 135 | ALPHA_FPRM_CHOP, /* Chopped rounding mode (towards 0). */ |
2bf6230d RK |
136 | ALPHA_FPRM_DYN /* Dynamic rounding mode. */ |
137 | }; | |
138 | ||
139 | enum alpha_fp_trap_mode | |
140 | { | |
285a5742 | 141 | ALPHA_FPTM_N, /* Normal trap mode. */ |
2bf6230d RK |
142 | ALPHA_FPTM_U, /* Underflow traps enabled. */ |
143 | ALPHA_FPTM_SU, /* Software completion, w/underflow traps */ | |
144 | ALPHA_FPTM_SUI /* Software completion, w/underflow & inexact traps */ | |
145 | }; | |
146 | ||
1a94ca49 RK |
147 | extern int target_flags; |
148 | ||
2bf6230d RK |
149 | extern enum alpha_trap_precision alpha_tp; |
150 | extern enum alpha_fp_rounding_mode alpha_fprm; | |
151 | extern enum alpha_fp_trap_mode alpha_fptm; | |
6f9b006d | 152 | extern int alpha_tls_size; |
2bf6230d | 153 | |
1a94ca49 RK |
154 | /* This means that floating-point support exists in the target implementation |
155 | of the Alpha architecture. This is usually the default. */ | |
de4abb91 | 156 | #define MASK_FP (1 << 0) |
2bf6230d | 157 | #define TARGET_FP (target_flags & MASK_FP) |
1a94ca49 RK |
158 | |
159 | /* This means that floating-point registers are allowed to be used. Note | |
160 | that Alpha implementations without FP operations are required to | |
161 | provide the FP registers. */ | |
162 | ||
de4abb91 | 163 | #define MASK_FPREGS (1 << 1) |
2bf6230d | 164 | #define TARGET_FPREGS (target_flags & MASK_FPREGS) |
03f8c4cc RK |
165 | |
166 | /* This means that gas is used to process the assembler file. */ | |
167 | ||
de4abb91 | 168 | #define MASK_GAS (1 << 2) |
03f8c4cc | 169 | #define TARGET_GAS (target_flags & MASK_GAS) |
1a94ca49 | 170 | |
285a5742 | 171 | /* This means that we should mark procedures as IEEE conformant. */ |
2bf6230d | 172 | |
de4abb91 | 173 | #define MASK_IEEE_CONFORMANT (1 << 3) |
2bf6230d RK |
174 | #define TARGET_IEEE_CONFORMANT (target_flags & MASK_IEEE_CONFORMANT) |
175 | ||
176 | /* This means we should be IEEE-compliant except for inexact. */ | |
177 | ||
de4abb91 | 178 | #define MASK_IEEE (1 << 4) |
2bf6230d RK |
179 | #define TARGET_IEEE (target_flags & MASK_IEEE) |
180 | ||
181 | /* This means we should be fully IEEE-compliant. */ | |
182 | ||
de4abb91 | 183 | #define MASK_IEEE_WITH_INEXACT (1 << 5) |
2bf6230d RK |
184 | #define TARGET_IEEE_WITH_INEXACT (target_flags & MASK_IEEE_WITH_INEXACT) |
185 | ||
803fee69 RK |
186 | /* This means we must construct all constants rather than emitting |
187 | them as literal data. */ | |
188 | ||
de4abb91 | 189 | #define MASK_BUILD_CONSTANTS (1 << 6) |
803fee69 RK |
190 | #define TARGET_BUILD_CONSTANTS (target_flags & MASK_BUILD_CONSTANTS) |
191 | ||
e5958492 RK |
192 | /* This means we handle floating points in VAX F- (float) |
193 | or G- (double) Format. */ | |
194 | ||
de4abb91 | 195 | #define MASK_FLOAT_VAX (1 << 7) |
e5958492 RK |
196 | #define TARGET_FLOAT_VAX (target_flags & MASK_FLOAT_VAX) |
197 | ||
e9a25f70 JL |
198 | /* This means that the processor has byte and half word loads and stores |
199 | (the BWX extension). */ | |
025f3281 | 200 | |
de4abb91 | 201 | #define MASK_BWX (1 << 8) |
e9a25f70 | 202 | #define TARGET_BWX (target_flags & MASK_BWX) |
025f3281 | 203 | |
e9a25f70 | 204 | /* This means that the processor has the MAX extension. */ |
de4abb91 | 205 | #define MASK_MAX (1 << 9) |
e9a25f70 JL |
206 | #define TARGET_MAX (target_flags & MASK_MAX) |
207 | ||
de4abb91 RH |
208 | /* This means that the processor has the FIX extension. */ |
209 | #define MASK_FIX (1 << 10) | |
210 | #define TARGET_FIX (target_flags & MASK_FIX) | |
211 | ||
212 | /* This means that the processor has the CIX extension. */ | |
213 | #define MASK_CIX (1 << 11) | |
214 | #define TARGET_CIX (target_flags & MASK_CIX) | |
215 | ||
1eb356b9 RH |
216 | /* This means use !literal style explicit relocations. */ |
217 | #define MASK_EXPLICIT_RELOCS (1 << 12) | |
218 | #define TARGET_EXPLICIT_RELOCS (target_flags & MASK_EXPLICIT_RELOCS) | |
219 | ||
133d3133 RH |
220 | /* This means use 16-bit relocations to .sdata/.sbss. */ |
221 | #define MASK_SMALL_DATA (1 << 13) | |
222 | #define TARGET_SMALL_DATA (target_flags & MASK_SMALL_DATA) | |
223 | ||
6f9b006d RH |
224 | /* This means emit thread pointer loads for kernel not user. */ |
225 | #define MASK_TLS_KERNEL (1 << 14) | |
226 | #define TARGET_TLS_KERNEL (target_flags & MASK_TLS_KERNEL) | |
227 | ||
3094247f RH |
228 | /* This means use direct branches to local functions. */ |
229 | #define MASK_SMALL_TEXT (1 << 15) | |
230 | #define TARGET_SMALL_TEXT (target_flags & MASK_SMALL_TEXT) | |
231 | ||
a3b815cb JJ |
232 | /* This means that the processor is an EV5, EV56, or PCA56. |
233 | Unlike alpha_cpu this is not affected by -mtune= setting. */ | |
a76c0119 | 234 | #define MASK_CPU_EV5 (1 << 28) |
a3b815cb | 235 | #define TARGET_CPU_EV5 (target_flags & MASK_CPU_EV5) |
e9a25f70 JL |
236 | |
237 | /* Likewise for EV6. */ | |
a76c0119 | 238 | #define MASK_CPU_EV6 (1 << 29) |
a3b815cb | 239 | #define TARGET_CPU_EV6 (target_flags & MASK_CPU_EV6) |
e9a25f70 JL |
240 | |
241 | /* This means we support the .arch directive in the assembler. Only | |
242 | defined in TARGET_CPU_DEFAULT. */ | |
a76c0119 | 243 | #define MASK_SUPPORT_ARCH (1 << 30) |
e9a25f70 | 244 | #define TARGET_SUPPORT_ARCH (target_flags & MASK_SUPPORT_ARCH) |
8f87939b | 245 | |
9ba3994a | 246 | /* These are for target os support and cannot be changed at runtime. */ |
be7b80f4 RH |
247 | #define TARGET_ABI_WINDOWS_NT 0 |
248 | #define TARGET_ABI_OPEN_VMS 0 | |
30102605 RH |
249 | #define TARGET_ABI_UNICOSMK 0 |
250 | #define TARGET_ABI_OSF (!TARGET_ABI_WINDOWS_NT \ | |
251 | && !TARGET_ABI_OPEN_VMS \ | |
252 | && !TARGET_ABI_UNICOSMK) | |
9ba3994a RH |
253 | |
254 | #ifndef TARGET_AS_CAN_SUBTRACT_LABELS | |
255 | #define TARGET_AS_CAN_SUBTRACT_LABELS TARGET_GAS | |
256 | #endif | |
30102605 RH |
257 | #ifndef TARGET_AS_SLASH_BEFORE_SUFFIX |
258 | #define TARGET_AS_SLASH_BEFORE_SUFFIX TARGET_GAS | |
259 | #endif | |
9c0e94a5 RH |
260 | #ifndef TARGET_CAN_FAULT_IN_PROLOGUE |
261 | #define TARGET_CAN_FAULT_IN_PROLOGUE 0 | |
262 | #endif | |
5495cc55 RH |
263 | #ifndef TARGET_HAS_XFLOATING_LIBS |
264 | #define TARGET_HAS_XFLOATING_LIBS 0 | |
265 | #endif | |
4f1c5cce RH |
266 | #ifndef TARGET_PROFILING_NEEDS_GP |
267 | #define TARGET_PROFILING_NEEDS_GP 0 | |
268 | #endif | |
ccb83cbc RH |
269 | #ifndef TARGET_LD_BUGGY_LDGP |
270 | #define TARGET_LD_BUGGY_LDGP 0 | |
271 | #endif | |
14291bc7 RH |
272 | #ifndef TARGET_FIXUP_EV5_PREFETCH |
273 | #define TARGET_FIXUP_EV5_PREFETCH 0 | |
274 | #endif | |
6f9b006d RH |
275 | #ifndef HAVE_AS_TLS |
276 | #define HAVE_AS_TLS 0 | |
277 | #endif | |
9ba3994a | 278 | |
1a94ca49 RK |
279 | /* Macro to define tables used to set the flags. |
280 | This is a list in braces of pairs in braces, | |
281 | each pair being { "NAME", VALUE } | |
282 | where VALUE is the bits to set or minus the bits to clear. | |
283 | An empty string NAME is used to identify the default VALUE. */ | |
284 | ||
f8e52397 | 285 | #define TARGET_SWITCHES \ |
047142d3 PT |
286 | { {"no-soft-float", MASK_FP, N_("Use hardware fp")}, \ |
287 | {"soft-float", - MASK_FP, N_("Do not use hardware fp")}, \ | |
288 | {"fp-regs", MASK_FPREGS, N_("Use fp registers")}, \ | |
289 | {"no-fp-regs", - (MASK_FP|MASK_FPREGS), \ | |
290 | N_("Do not use fp registers")}, \ | |
291 | {"alpha-as", -MASK_GAS, N_("Do not assume GAS")}, \ | |
292 | {"gas", MASK_GAS, N_("Assume GAS")}, \ | |
f8e52397 | 293 | {"ieee-conformant", MASK_IEEE_CONFORMANT, \ |
047142d3 | 294 | N_("Request IEEE-conformant math library routines (OSF/1)")}, \ |
f8e52397 | 295 | {"ieee", MASK_IEEE|MASK_IEEE_CONFORMANT, \ |
047142d3 | 296 | N_("Emit IEEE-conformant code, without inexact exceptions")}, \ |
f8e52397 | 297 | {"ieee-with-inexact", MASK_IEEE_WITH_INEXACT|MASK_IEEE_CONFORMANT, \ |
047142d3 | 298 | N_("Emit IEEE-conformant code, with inexact exceptions")}, \ |
f8e52397 | 299 | {"build-constants", MASK_BUILD_CONSTANTS, \ |
047142d3 PT |
300 | N_("Do not emit complex integer constants to read-only memory")}, \ |
301 | {"float-vax", MASK_FLOAT_VAX, N_("Use VAX fp")}, \ | |
302 | {"float-ieee", -MASK_FLOAT_VAX, N_("Do not use VAX fp")}, \ | |
303 | {"bwx", MASK_BWX, N_("Emit code for the byte/word ISA extension")}, \ | |
f8e52397 | 304 | {"no-bwx", -MASK_BWX, ""}, \ |
047142d3 PT |
305 | {"max", MASK_MAX, \ |
306 | N_("Emit code for the motion video ISA extension")}, \ | |
f8e52397 | 307 | {"no-max", -MASK_MAX, ""}, \ |
047142d3 PT |
308 | {"fix", MASK_FIX, \ |
309 | N_("Emit code for the fp move and sqrt ISA extension")}, \ | |
de4abb91 | 310 | {"no-fix", -MASK_FIX, ""}, \ |
047142d3 | 311 | {"cix", MASK_CIX, N_("Emit code for the counting ISA extension")}, \ |
de4abb91 | 312 | {"no-cix", -MASK_CIX, ""}, \ |
1eb356b9 RH |
313 | {"explicit-relocs", MASK_EXPLICIT_RELOCS, \ |
314 | N_("Emit code using explicit relocation directives")}, \ | |
315 | {"no-explicit-relocs", -MASK_EXPLICIT_RELOCS, ""}, \ | |
133d3133 RH |
316 | {"small-data", MASK_SMALL_DATA, \ |
317 | N_("Emit 16-bit relocations to the small data areas")}, \ | |
318 | {"large-data", -MASK_SMALL_DATA, \ | |
319 | N_("Emit 32-bit relocations to the small data areas")}, \ | |
3094247f RH |
320 | {"small-text", MASK_SMALL_TEXT, \ |
321 | N_("Emit direct branches to local functions")}, \ | |
322 | {"large-text", -MASK_SMALL_TEXT, ""}, \ | |
6f9b006d RH |
323 | {"tls-kernel", MASK_TLS_KERNEL, \ |
324 | N_("Emit rdval instead of rduniq for thread pointer")}, \ | |
3a37b08e RH |
325 | {"", TARGET_DEFAULT | TARGET_CPU_DEFAULT \ |
326 | | TARGET_DEFAULT_EXPLICIT_RELOCS, ""} } | |
1a94ca49 | 327 | |
c01b5470 | 328 | #define TARGET_DEFAULT MASK_FP|MASK_FPREGS |
1a94ca49 | 329 | |
88681624 ILT |
330 | #ifndef TARGET_CPU_DEFAULT |
331 | #define TARGET_CPU_DEFAULT 0 | |
332 | #endif | |
333 | ||
3a37b08e RH |
334 | #ifndef TARGET_DEFAULT_EXPLICIT_RELOCS |
335 | #ifdef HAVE_AS_EXPLICIT_RELOCS | |
336 | #define TARGET_DEFAULT_EXPLICIT_RELOCS MASK_EXPLICIT_RELOCS | |
337 | #else | |
338 | #define TARGET_DEFAULT_EXPLICIT_RELOCS 0 | |
339 | #endif | |
340 | #endif | |
341 | ||
df45c7ea | 342 | extern const char *alpha_cpu_string; /* For -mcpu= */ |
a3b815cb | 343 | extern const char *alpha_tune_string; /* For -mtune= */ |
df45c7ea KG |
344 | extern const char *alpha_fprm_string; /* For -mfp-rounding-mode=[n|m|c|d] */ |
345 | extern const char *alpha_fptm_string; /* For -mfp-trap-mode=[n|u|su|sui] */ | |
346 | extern const char *alpha_tp_string; /* For -mtrap-precision=[p|f|i] */ | |
347 | extern const char *alpha_mlat_string; /* For -mmemory-latency= */ | |
6f9b006d | 348 | extern const char *alpha_tls_size_string; /* For -mtls-size= */ |
2bf6230d | 349 | |
f8e52397 RH |
350 | #define TARGET_OPTIONS \ |
351 | { \ | |
352 | {"cpu=", &alpha_cpu_string, \ | |
a3b815cb JJ |
353 | N_("Use features of and schedule given CPU")}, \ |
354 | {"tune=", &alpha_tune_string, \ | |
355 | N_("Schedule given CPU")}, \ | |
f8e52397 | 356 | {"fp-rounding-mode=", &alpha_fprm_string, \ |
047142d3 | 357 | N_("Control the generated fp rounding mode")}, \ |
f8e52397 | 358 | {"fp-trap-mode=", &alpha_fptm_string, \ |
047142d3 | 359 | N_("Control the IEEE trap mode")}, \ |
f8e52397 | 360 | {"trap-precision=", &alpha_tp_string, \ |
047142d3 | 361 | N_("Control the precision given to fp exceptions")}, \ |
f8e52397 | 362 | {"memory-latency=", &alpha_mlat_string, \ |
047142d3 | 363 | N_("Tune expected memory latency")}, \ |
6f9b006d RH |
364 | {"tls-size=", &alpha_tls_size_string, \ |
365 | N_("Specify bit size of immediate TLS offsets")}, \ | |
2bf6230d RK |
366 | } |
367 | ||
952fc2ed RH |
368 | /* This macro defines names of additional specifications to put in the |
369 | specs that can be used in various specifications like CC1_SPEC. Its | |
370 | definition is an initializer with a subgrouping for each command option. | |
371 | ||
372 | Each subgrouping contains a string constant, that defines the | |
373 | specification name, and a string constant that used by the GNU CC driver | |
374 | program. | |
375 | ||
376 | Do not define this macro if it does not need to do anything. */ | |
377 | ||
378 | #ifndef SUBTARGET_EXTRA_SPECS | |
379 | #define SUBTARGET_EXTRA_SPECS | |
380 | #endif | |
381 | ||
829245be | 382 | #define EXTRA_SPECS \ |
829245be | 383 | { "cpp_subtarget", CPP_SUBTARGET_SPEC }, \ |
952fc2ed RH |
384 | SUBTARGET_EXTRA_SPECS |
385 | ||
386 | ||
2bf6230d RK |
387 | /* Sometimes certain combinations of command options do not make sense |
388 | on a particular target machine. You can define a macro | |
389 | `OVERRIDE_OPTIONS' to take account of this. This macro, if | |
390 | defined, is executed once just after all the command options have | |
391 | been parsed. | |
392 | ||
393 | On the Alpha, it is used to translate target-option strings into | |
394 | numeric values. */ | |
395 | ||
2bf6230d RK |
396 | #define OVERRIDE_OPTIONS override_options () |
397 | ||
398 | ||
1a94ca49 RK |
399 | /* Define this macro to change register usage conditional on target flags. |
400 | ||
401 | On the Alpha, we use this to disable the floating-point registers when | |
402 | they don't exist. */ | |
403 | ||
e9e4208a WC |
404 | #define CONDITIONAL_REGISTER_USAGE \ |
405 | { \ | |
406 | int i; \ | |
407 | if (! TARGET_FPREGS) \ | |
408 | for (i = 32; i < 63; i++) \ | |
409 | fixed_regs[i] = call_used_regs[i] = 1; \ | |
410 | } | |
411 | ||
1a94ca49 | 412 | |
4f074454 RK |
413 | /* Show we can debug even without a frame pointer. */ |
414 | #define CAN_DEBUG_WITHOUT_FP | |
1a94ca49 RK |
415 | \f |
416 | /* target machine storage layout */ | |
417 | ||
418 | /* Define the size of `int'. The default is the same as the word size. */ | |
419 | #define INT_TYPE_SIZE 32 | |
420 | ||
421 | /* Define the size of `long long'. The default is the twice the word size. */ | |
422 | #define LONG_LONG_TYPE_SIZE 64 | |
423 | ||
3dc85dfb RH |
424 | /* We're IEEE unless someone says to use VAX. */ |
425 | #define TARGET_FLOAT_FORMAT \ | |
426 | (TARGET_FLOAT_VAX ? VAX_FLOAT_FORMAT : IEEE_FLOAT_FORMAT) | |
427 | ||
1a94ca49 RK |
428 | /* The two floating-point formats we support are S-floating, which is |
429 | 4 bytes, and T-floating, which is 8 bytes. `float' is S and `double' | |
430 | and `long double' are T. */ | |
431 | ||
432 | #define FLOAT_TYPE_SIZE 32 | |
433 | #define DOUBLE_TYPE_SIZE 64 | |
434 | #define LONG_DOUBLE_TYPE_SIZE 64 | |
435 | ||
5258d7ae RK |
436 | #define WCHAR_TYPE "unsigned int" |
437 | #define WCHAR_TYPE_SIZE 32 | |
1a94ca49 | 438 | |
13d39dbc | 439 | /* Define this macro if it is advisable to hold scalars in registers |
1a94ca49 RK |
440 | in a wider mode than that declared by the program. In such cases, |
441 | the value is constrained to be within the bounds of the declared | |
442 | type, but kept valid in the wider mode. The signedness of the | |
443 | extension may differ from that of the type. | |
444 | ||
445 | For Alpha, we always store objects in a full register. 32-bit objects | |
446 | are always sign-extended, but smaller objects retain their signedness. */ | |
447 | ||
448 | #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \ | |
449 | if (GET_MODE_CLASS (MODE) == MODE_INT \ | |
450 | && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \ | |
451 | { \ | |
452 | if ((MODE) == SImode) \ | |
453 | (UNSIGNEDP) = 0; \ | |
454 | (MODE) = DImode; \ | |
455 | } | |
456 | ||
457 | /* Define this if function arguments should also be promoted using the above | |
458 | procedure. */ | |
459 | ||
460 | #define PROMOTE_FUNCTION_ARGS | |
461 | ||
462 | /* Likewise, if the function return value is promoted. */ | |
463 | ||
464 | #define PROMOTE_FUNCTION_RETURN | |
465 | ||
466 | /* Define this if most significant bit is lowest numbered | |
467 | in instructions that operate on numbered bit-fields. | |
468 | ||
469 | There are no such instructions on the Alpha, but the documentation | |
470 | is little endian. */ | |
471 | #define BITS_BIG_ENDIAN 0 | |
472 | ||
473 | /* Define this if most significant byte of a word is the lowest numbered. | |
474 | This is false on the Alpha. */ | |
475 | #define BYTES_BIG_ENDIAN 0 | |
476 | ||
477 | /* Define this if most significant word of a multiword number is lowest | |
478 | numbered. | |
479 | ||
480 | For Alpha we can decide arbitrarily since there are no machine instructions | |
285a5742 | 481 | for them. Might as well be consistent with bytes. */ |
1a94ca49 RK |
482 | #define WORDS_BIG_ENDIAN 0 |
483 | ||
1a94ca49 RK |
484 | /* Width of a word, in units (bytes). */ |
485 | #define UNITS_PER_WORD 8 | |
486 | ||
487 | /* Width in bits of a pointer. | |
488 | See also the macro `Pmode' defined below. */ | |
489 | #define POINTER_SIZE 64 | |
490 | ||
491 | /* Allocation boundary (in *bits*) for storing arguments in argument list. */ | |
492 | #define PARM_BOUNDARY 64 | |
493 | ||
494 | /* Boundary (in *bits*) on which stack pointer should be aligned. */ | |
495 | #define STACK_BOUNDARY 64 | |
496 | ||
497 | /* Allocation boundary (in *bits*) for the code of a function. */ | |
c176c051 | 498 | #define FUNCTION_BOUNDARY 32 |
1a94ca49 RK |
499 | |
500 | /* Alignment of field after `int : 0' in a structure. */ | |
501 | #define EMPTY_FIELD_BOUNDARY 64 | |
502 | ||
503 | /* Every structure's size must be a multiple of this. */ | |
504 | #define STRUCTURE_SIZE_BOUNDARY 8 | |
505 | ||
43a88a8c | 506 | /* A bit-field declared as `int' forces `int' alignment for the struct. */ |
1a94ca49 RK |
507 | #define PCC_BITFIELD_TYPE_MATTERS 1 |
508 | ||
1a94ca49 | 509 | /* No data type wants to be aligned rounder than this. */ |
5495cc55 | 510 | #define BIGGEST_ALIGNMENT 128 |
1a94ca49 | 511 | |
d16fe557 RK |
512 | /* For atomic access to objects, must have at least 32-bit alignment |
513 | unless the machine has byte operations. */ | |
13eb1f7f | 514 | #define MINIMUM_ATOMIC_ALIGNMENT ((unsigned int) (TARGET_BWX ? 8 : 32)) |
d16fe557 | 515 | |
442b1685 RK |
516 | /* Align all constants and variables to at least a word boundary so |
517 | we can pick up pieces of them faster. */ | |
6c174fc0 RH |
518 | /* ??? Only if block-move stuff knows about different source/destination |
519 | alignment. */ | |
520 | #if 0 | |
442b1685 RK |
521 | #define CONSTANT_ALIGNMENT(EXP, ALIGN) MAX ((ALIGN), BITS_PER_WORD) |
522 | #define DATA_ALIGNMENT(EXP, ALIGN) MAX ((ALIGN), BITS_PER_WORD) | |
6c174fc0 | 523 | #endif |
1a94ca49 | 524 | |
825dda42 | 525 | /* Set this nonzero if move instructions will actually fail to work |
1a94ca49 RK |
526 | when given unaligned data. |
527 | ||
528 | Since we get an error message when we do one, call them invalid. */ | |
529 | ||
530 | #define STRICT_ALIGNMENT 1 | |
531 | ||
825dda42 | 532 | /* Set this nonzero if unaligned move instructions are extremely slow. |
1a94ca49 RK |
533 | |
534 | On the Alpha, they trap. */ | |
130d2d72 | 535 | |
e1565e65 | 536 | #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1 |
1a94ca49 RK |
537 | \f |
538 | /* Standard register usage. */ | |
539 | ||
540 | /* Number of actual hardware registers. | |
541 | The hardware registers are assigned numbers for the compiler | |
542 | from 0 to just below FIRST_PSEUDO_REGISTER. | |
543 | All registers that the compiler knows about must be given numbers, | |
544 | even those that are not normally considered general registers. | |
545 | ||
546 | We define all 32 integer registers, even though $31 is always zero, | |
547 | and all 32 floating-point registers, even though $f31 is also | |
548 | always zero. We do not bother defining the FP status register and | |
130d2d72 RK |
549 | there are no other registers. |
550 | ||
551 | Since $31 is always zero, we will use register number 31 as the | |
552 | argument pointer. It will never appear in the generated code | |
553 | because we will always be eliminating it in favor of the stack | |
52a69200 RK |
554 | pointer or hardware frame pointer. |
555 | ||
556 | Likewise, we use $f31 for the frame pointer, which will always | |
557 | be eliminated in favor of the hardware frame pointer or the | |
558 | stack pointer. */ | |
1a94ca49 RK |
559 | |
560 | #define FIRST_PSEUDO_REGISTER 64 | |
561 | ||
562 | /* 1 for registers that have pervasive standard uses | |
563 | and are not available for the register allocator. */ | |
564 | ||
565 | #define FIXED_REGISTERS \ | |
566 | {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
567 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, \ | |
568 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
569 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 } | |
570 | ||
571 | /* 1 for registers not available across function calls. | |
572 | These must include the FIXED_REGISTERS and also any | |
573 | registers that can be used without being saved. | |
574 | The latter must include the registers where values are returned | |
575 | and the register where structure-value addresses are passed. | |
576 | Aside from that, you can include as many other registers as you like. */ | |
577 | #define CALL_USED_REGISTERS \ | |
578 | {1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, \ | |
579 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, \ | |
580 | 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, \ | |
581 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 } | |
582 | ||
583 | /* List the order in which to allocate registers. Each register must be | |
584 | listed once, even those in FIXED_REGISTERS. | |
585 | ||
586 | We allocate in the following order: | |
2c4be73e | 587 | $f10-$f15 (nonsaved floating-point register) |
1a94ca49 RK |
588 | $f22-$f30 (likewise) |
589 | $f21-$f16 (likewise, but input args) | |
590 | $f0 (nonsaved, but return value) | |
2c4be73e | 591 | $f1 (nonsaved, but immediate before saved) |
1a94ca49 RK |
592 | $f2-$f9 (saved floating-point registers) |
593 | $1-$8 (nonsaved integer registers) | |
594 | $22-$25 (likewise) | |
595 | $28 (likewise) | |
596 | $0 (likewise, but return value) | |
597 | $21-$16 (likewise, but input args) | |
0076aa6b | 598 | $27 (procedure value in OSF, nonsaved in NT) |
1a94ca49 RK |
599 | $9-$14 (saved integer registers) |
600 | $26 (return PC) | |
601 | $15 (frame pointer) | |
602 | $29 (global pointer) | |
52a69200 | 603 | $30, $31, $f31 (stack pointer and always zero/ap & fp) */ |
1a94ca49 RK |
604 | |
605 | #define REG_ALLOC_ORDER \ | |
2c4be73e | 606 | {42, 43, 44, 45, 46, 47, \ |
1a94ca49 RK |
607 | 54, 55, 56, 57, 58, 59, 60, 61, 62, \ |
608 | 53, 52, 51, 50, 49, 48, \ | |
2c4be73e | 609 | 32, 33, \ |
1a94ca49 RK |
610 | 34, 35, 36, 37, 38, 39, 40, 41, \ |
611 | 1, 2, 3, 4, 5, 6, 7, 8, \ | |
612 | 22, 23, 24, 25, \ | |
613 | 28, \ | |
614 | 0, \ | |
615 | 21, 20, 19, 18, 17, 16, \ | |
616 | 27, \ | |
617 | 9, 10, 11, 12, 13, 14, \ | |
618 | 26, \ | |
619 | 15, \ | |
620 | 29, \ | |
621 | 30, 31, 63 } | |
622 | ||
623 | /* Return number of consecutive hard regs needed starting at reg REGNO | |
624 | to hold something of mode MODE. | |
625 | This is ordinarily the length in words of a value of mode MODE | |
626 | but can be less for certain modes in special long registers. */ | |
627 | ||
628 | #define HARD_REGNO_NREGS(REGNO, MODE) \ | |
629 | ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) | |
630 | ||
631 | /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. | |
632 | On Alpha, the integer registers can hold any mode. The floating-point | |
633 | registers can hold 32-bit and 64-bit integers as well, but not 16-bit | |
a7adf08e | 634 | or 8-bit values. */ |
1a94ca49 | 635 | |
e6a8ebb4 RH |
636 | #define HARD_REGNO_MODE_OK(REGNO, MODE) \ |
637 | ((REGNO) >= 32 && (REGNO) <= 62 \ | |
638 | ? GET_MODE_UNIT_SIZE (MODE) == 8 || GET_MODE_UNIT_SIZE (MODE) == 4 \ | |
639 | : 1) | |
640 | ||
6d8fd7bb RH |
641 | /* Value is 1 if MODE is a supported vector mode. */ |
642 | ||
643 | #define VECTOR_MODE_SUPPORTED_P(MODE) \ | |
644 | (TARGET_MAX \ | |
645 | && ((MODE) == V8QImode || (MODE) == V4HImode || (MODE) == V2SImode)) | |
646 | ||
e6a8ebb4 RH |
647 | /* A C expression that is nonzero if a value of mode |
648 | MODE1 is accessible in mode MODE2 without copying. | |
1a94ca49 | 649 | |
e6a8ebb4 RH |
650 | This asymmetric test is true when MODE1 could be put |
651 | in an FP register but MODE2 could not. */ | |
1a94ca49 | 652 | |
a7adf08e | 653 | #define MODES_TIEABLE_P(MODE1, MODE2) \ |
e6a8ebb4 RH |
654 | (HARD_REGNO_MODE_OK (32, (MODE1)) \ |
655 | ? HARD_REGNO_MODE_OK (32, (MODE2)) \ | |
a7adf08e | 656 | : 1) |
1a94ca49 RK |
657 | |
658 | /* Specify the registers used for certain standard purposes. | |
659 | The values of these macros are register numbers. */ | |
660 | ||
661 | /* Alpha pc isn't overloaded on a register that the compiler knows about. */ | |
662 | /* #define PC_REGNUM */ | |
663 | ||
664 | /* Register to use for pushing function arguments. */ | |
665 | #define STACK_POINTER_REGNUM 30 | |
666 | ||
667 | /* Base register for access to local variables of the function. */ | |
52a69200 | 668 | #define HARD_FRAME_POINTER_REGNUM 15 |
1a94ca49 RK |
669 | |
670 | /* Value should be nonzero if functions must have frame pointers. | |
671 | Zero means the frame pointer need not be set up (and parms | |
672 | may be accessed via the stack pointer) in functions that seem suitable. | |
673 | This is computed in `reload', in reload1.c. */ | |
674 | #define FRAME_POINTER_REQUIRED 0 | |
675 | ||
676 | /* Base register for access to arguments of the function. */ | |
130d2d72 | 677 | #define ARG_POINTER_REGNUM 31 |
1a94ca49 | 678 | |
52a69200 RK |
679 | /* Base register for access to local variables of function. */ |
680 | #define FRAME_POINTER_REGNUM 63 | |
681 | ||
1a94ca49 RK |
682 | /* Register in which static-chain is passed to a function. |
683 | ||
684 | For the Alpha, this is based on an example; the calling sequence | |
685 | doesn't seem to specify this. */ | |
686 | #define STATIC_CHAIN_REGNUM 1 | |
687 | ||
133d3133 RH |
688 | /* The register number of the register used to address a table of |
689 | static data addresses in memory. */ | |
690 | #define PIC_OFFSET_TABLE_REGNUM 29 | |
691 | ||
692 | /* Define this macro if the register defined by `PIC_OFFSET_TABLE_REGNUM' | |
693 | is clobbered by calls. */ | |
694 | /* ??? It is and it isn't. It's required to be valid for a given | |
695 | function when the function returns. It isn't clobbered by | |
696 | current_file functions. Moreover, we do not expose the ldgp | |
697 | until after reload, so we're probably safe. */ | |
698 | /* #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED */ | |
699 | ||
1a94ca49 RK |
700 | /* Register in which address to store a structure value |
701 | arrives in the function. On the Alpha, the address is passed | |
702 | as a hidden argument. */ | |
703 | #define STRUCT_VALUE 0 | |
704 | \f | |
705 | /* Define the classes of registers for register constraints in the | |
706 | machine description. Also define ranges of constants. | |
707 | ||
708 | One of the classes must always be named ALL_REGS and include all hard regs. | |
709 | If there is more than one class, another class must be named NO_REGS | |
710 | and contain no registers. | |
711 | ||
712 | The name GENERAL_REGS must be the name of a class (or an alias for | |
713 | another name such as ALL_REGS). This is the class of registers | |
714 | that is allowed by "g" or "r" in a register constraint. | |
715 | Also, registers outside this class are allocated only when | |
716 | instructions express preferences for them. | |
717 | ||
718 | The classes must be numbered in nondecreasing order; that is, | |
719 | a larger-numbered class must never be contained completely | |
720 | in a smaller-numbered class. | |
721 | ||
722 | For any two classes, it is very desirable that there be another | |
723 | class that represents their union. */ | |
724 | ||
b73c0bc8 | 725 | enum reg_class { |
6f9b006d | 726 | NO_REGS, R0_REG, R24_REG, R25_REG, R27_REG, |
b73c0bc8 RH |
727 | GENERAL_REGS, FLOAT_REGS, ALL_REGS, |
728 | LIM_REG_CLASSES | |
729 | }; | |
1a94ca49 RK |
730 | |
731 | #define N_REG_CLASSES (int) LIM_REG_CLASSES | |
732 | ||
285a5742 | 733 | /* Give names of register classes as strings for dump file. */ |
1a94ca49 | 734 | |
6f9b006d RH |
735 | #define REG_CLASS_NAMES \ |
736 | {"NO_REGS", "R0_REG", "R24_REG", "R25_REG", "R27_REG", \ | |
b73c0bc8 | 737 | "GENERAL_REGS", "FLOAT_REGS", "ALL_REGS" } |
1a94ca49 RK |
738 | |
739 | /* Define which registers fit in which classes. | |
740 | This is an initializer for a vector of HARD_REG_SET | |
741 | of length N_REG_CLASSES. */ | |
742 | ||
b73c0bc8 RH |
743 | #define REG_CLASS_CONTENTS \ |
744 | { {0x00000000, 0x00000000}, /* NO_REGS */ \ | |
6f9b006d | 745 | {0x00000001, 0x00000000}, /* R0_REG */ \ |
b73c0bc8 RH |
746 | {0x01000000, 0x00000000}, /* R24_REG */ \ |
747 | {0x02000000, 0x00000000}, /* R25_REG */ \ | |
748 | {0x08000000, 0x00000000}, /* R27_REG */ \ | |
749 | {0xffffffff, 0x80000000}, /* GENERAL_REGS */ \ | |
750 | {0x00000000, 0x7fffffff}, /* FLOAT_REGS */ \ | |
751 | {0xffffffff, 0xffffffff} } | |
1a94ca49 RK |
752 | |
753 | /* The same information, inverted: | |
754 | Return the class number of the smallest class containing | |
755 | reg number REGNO. This could be a conditional expression | |
756 | or could index an array. */ | |
757 | ||
93c89ab3 | 758 | #define REGNO_REG_CLASS(REGNO) \ |
6f9b006d RH |
759 | ((REGNO) == 0 ? R0_REG \ |
760 | : (REGNO) == 24 ? R24_REG \ | |
b73c0bc8 RH |
761 | : (REGNO) == 25 ? R25_REG \ |
762 | : (REGNO) == 27 ? R27_REG \ | |
93c89ab3 RH |
763 | : (REGNO) >= 32 && (REGNO) <= 62 ? FLOAT_REGS \ |
764 | : GENERAL_REGS) | |
1a94ca49 RK |
765 | |
766 | /* The class value for index registers, and the one for base regs. */ | |
767 | #define INDEX_REG_CLASS NO_REGS | |
768 | #define BASE_REG_CLASS GENERAL_REGS | |
769 | ||
770 | /* Get reg_class from a letter such as appears in the machine description. */ | |
771 | ||
772 | #define REG_CLASS_FROM_LETTER(C) \ | |
b73c0bc8 RH |
773 | ((C) == 'a' ? R24_REG \ |
774 | : (C) == 'b' ? R25_REG \ | |
775 | : (C) == 'c' ? R27_REG \ | |
776 | : (C) == 'f' ? FLOAT_REGS \ | |
6f9b006d | 777 | : (C) == 'v' ? R0_REG \ |
b73c0bc8 | 778 | : NO_REGS) |
1a94ca49 RK |
779 | |
780 | /* Define this macro to change register usage conditional on target flags. */ | |
781 | /* #define CONDITIONAL_REGISTER_USAGE */ | |
782 | ||
783 | /* The letters I, J, K, L, M, N, O, and P in a register constraint string | |
784 | can be used to stand for particular ranges of immediate operands. | |
785 | This macro defines what the ranges are. | |
786 | C is the letter, and VALUE is a constant value. | |
787 | Return 1 if VALUE is in the range specified by C. | |
788 | ||
789 | For Alpha: | |
790 | `I' is used for the range of constants most insns can contain. | |
791 | `J' is the constant zero. | |
792 | `K' is used for the constant in an LDA insn. | |
793 | `L' is used for the constant in a LDAH insn. | |
794 | `M' is used for the constants that can be AND'ed with using a ZAP insn. | |
795 | `N' is used for complemented 8-bit constants. | |
796 | `O' is used for negated 8-bit constants. | |
797 | `P' is used for the constants 1, 2 and 3. */ | |
798 | ||
551cc6fd | 799 | #define CONST_OK_FOR_LETTER_P alpha_const_ok_for_letter_p |
1a94ca49 RK |
800 | |
801 | /* Similar, but for floating or large integer constants, and defining letters | |
802 | G and H. Here VALUE is the CONST_DOUBLE rtx itself. | |
803 | ||
804 | For Alpha, `G' is the floating-point constant zero. `H' is a CONST_DOUBLE | |
805 | that is the operand of a ZAP insn. */ | |
806 | ||
551cc6fd | 807 | #define CONST_DOUBLE_OK_FOR_LETTER_P alpha_const_double_ok_for_letter_p |
1a94ca49 | 808 | |
e560f226 RK |
809 | /* Optional extra constraints for this machine. |
810 | ||
811 | For the Alpha, `Q' means that this is a memory operand but not a | |
ac030a7b | 812 | reference to an unaligned location. |
9ec36da5 | 813 | |
ac030a7b | 814 | `R' is a SYMBOL_REF that has SYMBOL_REF_FLAG set or is the current |
9ec36da5 JL |
815 | function. |
816 | ||
30102605 RH |
817 | 'S' is a 6-bit constant (valid for a shift insn). |
818 | ||
551cc6fd RH |
819 | 'T' is a HIGH. |
820 | ||
6d8fd7bb RH |
821 | 'U' is a symbolic operand. |
822 | ||
823 | 'W' is a vector zero. */ | |
e560f226 | 824 | |
551cc6fd | 825 | #define EXTRA_CONSTRAINT alpha_extra_constraint |
e560f226 | 826 | |
1a94ca49 RK |
827 | /* Given an rtx X being reloaded into a reg required to be |
828 | in class CLASS, return the class of reg to actually use. | |
829 | In general this is just CLASS; but on some machines | |
551cc6fd | 830 | in some cases it is preferable to use a more restrictive class. */ |
1a94ca49 | 831 | |
551cc6fd | 832 | #define PREFERRED_RELOAD_CLASS alpha_preferred_reload_class |
1a94ca49 RK |
833 | |
834 | /* Loading and storing HImode or QImode values to and from memory | |
835 | usually requires a scratch register. The exceptions are loading | |
e008606e RK |
836 | QImode and HImode from an aligned address to a general register |
837 | unless byte instructions are permitted. | |
ddd5a7c1 | 838 | We also cannot load an unaligned address or a paradoxical SUBREG into an |
285a5742 | 839 | FP register. */ |
1a94ca49 | 840 | |
3611aef0 RH |
841 | #define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,IN) \ |
842 | secondary_reload_class((CLASS), (MODE), (IN), 1) | |
843 | ||
844 | #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,OUT) \ | |
845 | secondary_reload_class((CLASS), (MODE), (OUT), 0) | |
1a94ca49 RK |
846 | |
847 | /* If we are copying between general and FP registers, we need a memory | |
de4abb91 | 848 | location unless the FIX extension is available. */ |
1a94ca49 | 849 | |
e9a25f70 | 850 | #define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \ |
bfd82dbf RK |
851 | (! TARGET_FIX && (((CLASS1) == FLOAT_REGS && (CLASS2) != FLOAT_REGS) \ |
852 | || ((CLASS2) == FLOAT_REGS && (CLASS1) != FLOAT_REGS))) | |
1a94ca49 | 853 | |
acd94aaf RK |
854 | /* Specify the mode to be used for memory when a secondary memory |
855 | location is needed. If MODE is floating-point, use it. Otherwise, | |
856 | widen to a word like the default. This is needed because we always | |
857 | store integers in FP registers in quadword format. This whole | |
858 | area is very tricky! */ | |
859 | #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \ | |
860 | (GET_MODE_CLASS (MODE) == MODE_FLOAT ? (MODE) \ | |
e868b518 | 861 | : GET_MODE_SIZE (MODE) >= 4 ? (MODE) \ |
acd94aaf RK |
862 | : mode_for_size (BITS_PER_WORD, GET_MODE_CLASS (MODE), 0)) |
863 | ||
1a94ca49 RK |
864 | /* Return the maximum number of consecutive registers |
865 | needed to represent mode MODE in a register of class CLASS. */ | |
866 | ||
867 | #define CLASS_MAX_NREGS(CLASS, MODE) \ | |
868 | ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) | |
869 | ||
cff9f8d5 | 870 | /* Return the class of registers that cannot change mode from FROM to TO. */ |
c31dfe4d | 871 | |
b0c42aed JH |
872 | #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ |
873 | (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \ | |
874 | ? reg_classes_intersect_p (FLOAT_REGS, CLASS) : 0) | |
c31dfe4d | 875 | |
1a94ca49 RK |
876 | /* Define the cost of moving between registers of various classes. Moving |
877 | between FLOAT_REGS and anything else except float regs is expensive. | |
878 | In fact, we make it quite expensive because we really don't want to | |
879 | do these moves unless it is clearly worth it. Optimizations may | |
880 | reduce the impact of not being able to allocate a pseudo to a | |
881 | hard register. */ | |
882 | ||
cf011243 | 883 | #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \ |
71d9b493 RH |
884 | (((CLASS1) == FLOAT_REGS) == ((CLASS2) == FLOAT_REGS) \ |
885 | ? 2 \ | |
de4abb91 | 886 | : TARGET_FIX ? 3 : 4+2*alpha_memory_latency) |
1a94ca49 RK |
887 | |
888 | /* A C expressions returning the cost of moving data of MODE from a register to | |
889 | or from memory. | |
890 | ||
891 | On the Alpha, bump this up a bit. */ | |
892 | ||
bcbbac26 | 893 | extern int alpha_memory_latency; |
cbd5b9a2 | 894 | #define MEMORY_MOVE_COST(MODE,CLASS,IN) (2*alpha_memory_latency) |
1a94ca49 RK |
895 | |
896 | /* Provide the cost of a branch. Exact meaning under development. */ | |
897 | #define BRANCH_COST 5 | |
1a94ca49 RK |
898 | \f |
899 | /* Stack layout; function entry, exit and calling. */ | |
900 | ||
901 | /* Define this if pushing a word on the stack | |
902 | makes the stack pointer a smaller address. */ | |
903 | #define STACK_GROWS_DOWNWARD | |
904 | ||
905 | /* Define this if the nominal address of the stack frame | |
906 | is at the high-address end of the local variables; | |
907 | that is, each additional local variable allocated | |
908 | goes at a more negative offset in the frame. */ | |
130d2d72 | 909 | /* #define FRAME_GROWS_DOWNWARD */ |
1a94ca49 RK |
910 | |
911 | /* Offset within stack frame to start allocating local variables at. | |
912 | If FRAME_GROWS_DOWNWARD, this is the offset to the END of the | |
913 | first local allocated. Otherwise, it is the offset to the BEGINNING | |
914 | of the first local allocated. */ | |
915 | ||
52a69200 | 916 | #define STARTING_FRAME_OFFSET 0 |
1a94ca49 RK |
917 | |
918 | /* If we generate an insn to push BYTES bytes, | |
919 | this says how many the stack pointer really advances by. | |
920 | On Alpha, don't define this because there are no push insns. */ | |
921 | /* #define PUSH_ROUNDING(BYTES) */ | |
922 | ||
e008606e RK |
923 | /* Define this to be nonzero if stack checking is built into the ABI. */ |
924 | #define STACK_CHECK_BUILTIN 1 | |
925 | ||
1a94ca49 RK |
926 | /* Define this if the maximum size of all the outgoing args is to be |
927 | accumulated and pushed during the prologue. The amount can be | |
928 | found in the variable current_function_outgoing_args_size. */ | |
f73ad30e | 929 | #define ACCUMULATE_OUTGOING_ARGS 1 |
1a94ca49 RK |
930 | |
931 | /* Offset of first parameter from the argument pointer register value. */ | |
932 | ||
130d2d72 | 933 | #define FIRST_PARM_OFFSET(FNDECL) 0 |
1a94ca49 RK |
934 | |
935 | /* Definitions for register eliminations. | |
936 | ||
978e8952 | 937 | We have two registers that can be eliminated on the Alpha. First, the |
1a94ca49 | 938 | frame pointer register can often be eliminated in favor of the stack |
130d2d72 | 939 | pointer register. Secondly, the argument pointer register can always be |
285a5742 | 940 | eliminated; it is replaced with either the stack or frame pointer. */ |
1a94ca49 RK |
941 | |
942 | /* This is an array of structures. Each structure initializes one pair | |
943 | of eliminable registers. The "from" register number is given first, | |
944 | followed by "to". Eliminations of the same "from" register are listed | |
945 | in order of preference. */ | |
946 | ||
52a69200 RK |
947 | #define ELIMINABLE_REGS \ |
948 | {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
949 | { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ | |
950 | { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
951 | { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} | |
1a94ca49 RK |
952 | |
953 | /* Given FROM and TO register numbers, say whether this elimination is allowed. | |
954 | Frame pointer elimination is automatically handled. | |
955 | ||
130d2d72 | 956 | All eliminations are valid since the cases where FP can't be |
1a94ca49 RK |
957 | eliminated are already handled. */ |
958 | ||
130d2d72 | 959 | #define CAN_ELIMINATE(FROM, TO) 1 |
1a94ca49 | 960 | |
52a69200 RK |
961 | /* Round up to a multiple of 16 bytes. */ |
962 | #define ALPHA_ROUND(X) (((X) + 15) & ~ 15) | |
963 | ||
1a94ca49 RK |
964 | /* Define the offset between two registers, one to be eliminated, and the other |
965 | its replacement, at the start of a routine. */ | |
966 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ | |
52a69200 RK |
967 | { if ((FROM) == FRAME_POINTER_REGNUM) \ |
968 | (OFFSET) = (ALPHA_ROUND (current_function_outgoing_args_size) \ | |
969 | + alpha_sa_size ()); \ | |
970 | else if ((FROM) == ARG_POINTER_REGNUM) \ | |
971 | (OFFSET) = (ALPHA_ROUND (current_function_outgoing_args_size) \ | |
972 | + alpha_sa_size () \ | |
d772039b RK |
973 | + (ALPHA_ROUND (get_frame_size () \ |
974 | + current_function_pretend_args_size) \ | |
975 | - current_function_pretend_args_size)); \ | |
c8d8ed65 RK |
976 | else \ |
977 | abort (); \ | |
1a94ca49 RK |
978 | } |
979 | ||
980 | /* Define this if stack space is still allocated for a parameter passed | |
981 | in a register. */ | |
982 | /* #define REG_PARM_STACK_SPACE */ | |
983 | ||
984 | /* Value is the number of bytes of arguments automatically | |
985 | popped when returning from a subroutine call. | |
8b109b37 | 986 | FUNDECL is the declaration node of the function (as a tree), |
1a94ca49 RK |
987 | FUNTYPE is the data type of the function (as a tree), |
988 | or for a library call it is an identifier node for the subroutine name. | |
989 | SIZE is the number of bytes of arguments passed on the stack. */ | |
990 | ||
8b109b37 | 991 | #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0 |
1a94ca49 RK |
992 | |
993 | /* Define how to find the value returned by a function. | |
994 | VALTYPE is the data type of the value (as a tree). | |
995 | If the precise function being called is known, FUNC is its FUNCTION_DECL; | |
996 | otherwise, FUNC is 0. | |
997 | ||
998 | On Alpha the value is found in $0 for integer functions and | |
999 | $f0 for floating-point functions. */ | |
1000 | ||
c5c76735 | 1001 | #define FUNCTION_VALUE(VALTYPE, FUNC) \ |
4c020733 | 1002 | gen_rtx_REG (((INTEGRAL_TYPE_P (VALTYPE) \ |
c5c76735 JL |
1003 | && TYPE_PRECISION (VALTYPE) < BITS_PER_WORD) \ |
1004 | || POINTER_TYPE_P (VALTYPE)) \ | |
4c020733 RH |
1005 | ? word_mode : TYPE_MODE (VALTYPE), \ |
1006 | ((TARGET_FPREGS \ | |
c5c76735 | 1007 | && (TREE_CODE (VALTYPE) == REAL_TYPE \ |
4c020733 | 1008 | || TREE_CODE (VALTYPE) == COMPLEX_TYPE)) \ |
c5c76735 | 1009 | ? 32 : 0)) |
1a94ca49 RK |
1010 | |
1011 | /* Define how to find the value returned by a library function | |
1012 | assuming the value has mode MODE. */ | |
1013 | ||
c5c76735 | 1014 | #define LIBCALL_VALUE(MODE) \ |
4c020733 | 1015 | gen_rtx_REG (MODE, \ |
c5c76735 JL |
1016 | (TARGET_FPREGS \ |
1017 | && (GET_MODE_CLASS (MODE) == MODE_FLOAT \ | |
4c020733 | 1018 | || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \ |
c5c76735 | 1019 | ? 32 : 0)) |
1a94ca49 | 1020 | |
130d2d72 RK |
1021 | /* The definition of this macro implies that there are cases where |
1022 | a scalar value cannot be returned in registers. | |
1023 | ||
1024 | For the Alpha, any structure or union type is returned in memory, as | |
1025 | are integers whose size is larger than 64 bits. */ | |
1026 | ||
1027 | #define RETURN_IN_MEMORY(TYPE) \ | |
e14fa9c4 | 1028 | (TYPE_MODE (TYPE) == BLKmode \ |
5495cc55 RH |
1029 | || TYPE_MODE (TYPE) == TFmode \ |
1030 | || TYPE_MODE (TYPE) == TCmode \ | |
130d2d72 RK |
1031 | || (TREE_CODE (TYPE) == INTEGER_TYPE && TYPE_PRECISION (TYPE) > 64)) |
1032 | ||
1a94ca49 RK |
1033 | /* 1 if N is a possible register number for a function value |
1034 | as seen by the caller. */ | |
1035 | ||
e5958492 RK |
1036 | #define FUNCTION_VALUE_REGNO_P(N) \ |
1037 | ((N) == 0 || (N) == 1 || (N) == 32 || (N) == 33) | |
1a94ca49 RK |
1038 | |
1039 | /* 1 if N is a possible register number for function argument passing. | |
1040 | On Alpha, these are $16-$21 and $f16-$f21. */ | |
1041 | ||
1042 | #define FUNCTION_ARG_REGNO_P(N) \ | |
1043 | (((N) >= 16 && (N) <= 21) || ((N) >= 16 + 32 && (N) <= 21 + 32)) | |
1044 | \f | |
1045 | /* Define a data type for recording info about an argument list | |
1046 | during the scan of that argument list. This data type should | |
1047 | hold all necessary information about the function itself | |
1048 | and about the args processed so far, enough to enable macros | |
1049 | such as FUNCTION_ARG to determine where the next arg should go. | |
1050 | ||
1051 | On Alpha, this is a single integer, which is a number of words | |
1052 | of arguments scanned so far. | |
1053 | Thus 6 or more means all following args should go on the stack. */ | |
1054 | ||
1055 | #define CUMULATIVE_ARGS int | |
1056 | ||
1057 | /* Initialize a variable CUM of type CUMULATIVE_ARGS | |
1058 | for a call to a function whose data type is FNTYPE. | |
1059 | For a library call, FNTYPE is 0. */ | |
1060 | ||
2c7ee1a6 | 1061 | #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) (CUM) = 0 |
1a94ca49 RK |
1062 | |
1063 | /* Define intermediate macro to compute the size (in registers) of an argument | |
1064 | for the Alpha. */ | |
1065 | ||
1066 | #define ALPHA_ARG_SIZE(MODE, TYPE, NAMED) \ | |
5495cc55 RH |
1067 | ((MODE) == TFmode || (MODE) == TCmode ? 1 \ |
1068 | : (((MODE) == BLKmode ? int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE)) \ | |
1069 | + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD) | |
1a94ca49 RK |
1070 | |
1071 | /* Update the data in CUM to advance over an argument | |
1072 | of mode MODE and data type TYPE. | |
1073 | (TYPE is null for libcalls where that information may not be available.) */ | |
1074 | ||
1075 | #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ | |
1076 | if (MUST_PASS_IN_STACK (MODE, TYPE)) \ | |
1077 | (CUM) = 6; \ | |
1078 | else \ | |
1079 | (CUM) += ALPHA_ARG_SIZE (MODE, TYPE, NAMED) | |
1080 | ||
1081 | /* Determine where to put an argument to a function. | |
1082 | Value is zero to push the argument on the stack, | |
1083 | or a hard register in which to store the argument. | |
1084 | ||
1085 | MODE is the argument's machine mode. | |
1086 | TYPE is the data type of the argument (as a tree). | |
1087 | This is null for libcalls where that information may | |
1088 | not be available. | |
1089 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
1090 | the preceding args and about the function being called. | |
1091 | NAMED is nonzero if this argument is a named parameter | |
1092 | (otherwise it is an extra parameter matching an ellipsis). | |
1093 | ||
1094 | On Alpha the first 6 words of args are normally in registers | |
1095 | and the rest are pushed. */ | |
1096 | ||
1097 | #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ | |
5495cc55 RH |
1098 | function_arg((CUM), (MODE), (TYPE), (NAMED)) |
1099 | ||
1100 | /* A C expression that indicates when an argument must be passed by | |
1101 | reference. If nonzero for an argument, a copy of that argument is | |
1102 | made in memory and a pointer to the argument is passed instead of | |
1103 | the argument itself. The pointer is passed in whatever way is | |
285a5742 | 1104 | appropriate for passing a pointer to that type. */ |
5495cc55 RH |
1105 | |
1106 | #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \ | |
1107 | ((MODE) == TFmode || (MODE) == TCmode) | |
1a94ca49 | 1108 | |
1a94ca49 RK |
1109 | /* Specify the padding direction of arguments. |
1110 | ||
1111 | On the Alpha, we must pad upwards in order to be able to pass args in | |
1112 | registers. */ | |
1113 | ||
1114 | #define FUNCTION_ARG_PADDING(MODE, TYPE) upward | |
1115 | ||
1116 | /* For an arg passed partly in registers and partly in memory, | |
1117 | this is the number of registers used. | |
1118 | For args passed entirely in registers or entirely in memory, zero. */ | |
1119 | ||
1120 | #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \ | |
1121 | ((CUM) < 6 && 6 < (CUM) + ALPHA_ARG_SIZE (MODE, TYPE, NAMED) \ | |
1122 | ? 6 - (CUM) : 0) | |
1123 | ||
130d2d72 RK |
1124 | /* Perform any needed actions needed for a function that is receiving a |
1125 | variable number of arguments. | |
1126 | ||
1127 | CUM is as above. | |
1128 | ||
1129 | MODE and TYPE are the mode and type of the current parameter. | |
1130 | ||
1131 | PRETEND_SIZE is a variable that should be set to the amount of stack | |
1132 | that must be pushed by the prolog to pretend that our caller pushed | |
1133 | it. | |
1134 | ||
1135 | Normally, this macro will push all remaining incoming registers on the | |
1136 | stack and set PRETEND_SIZE to the length of the registers pushed. | |
1137 | ||
1138 | On the Alpha, we allocate space for all 12 arg registers, but only | |
1139 | push those that are remaining. | |
1140 | ||
1141 | However, if NO registers need to be saved, don't allocate any space. | |
1142 | This is not only because we won't need the space, but because AP includes | |
1143 | the current_pretend_args_size and we don't want to mess up any | |
7a92339b RK |
1144 | ap-relative addresses already made. |
1145 | ||
1146 | If we are not to use the floating-point registers, save the integer | |
1147 | registers where we would put the floating-point registers. This is | |
1148 | not the most efficient way to implement varargs with just one register | |
1149 | class, but it isn't worth doing anything more efficient in this rare | |
1150 | case. */ | |
1151 | ||
130d2d72 RK |
1152 | #define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL) \ |
1153 | { if ((CUM) < 6) \ | |
1154 | { \ | |
1155 | if (! (NO_RTL)) \ | |
1156 | { \ | |
63966b3b RH |
1157 | rtx tmp; int set = get_varargs_alias_set (); \ |
1158 | tmp = gen_rtx_MEM (BLKmode, \ | |
1159 | plus_constant (virtual_incoming_args_rtx, \ | |
1160 | ((CUM) + 6)* UNITS_PER_WORD)); \ | |
6a1d250e | 1161 | set_mem_alias_set (tmp, set); \ |
130d2d72 | 1162 | move_block_from_reg \ |
63966b3b | 1163 | (16 + CUM, tmp, \ |
02892e06 | 1164 | 6 - (CUM), (6 - (CUM)) * UNITS_PER_WORD); \ |
63966b3b RH |
1165 | \ |
1166 | tmp = gen_rtx_MEM (BLKmode, \ | |
1167 | plus_constant (virtual_incoming_args_rtx, \ | |
1168 | (CUM) * UNITS_PER_WORD)); \ | |
6a1d250e | 1169 | set_mem_alias_set (tmp, set); \ |
130d2d72 | 1170 | move_block_from_reg \ |
63966b3b | 1171 | (16 + (TARGET_FPREGS ? 32 : 0) + CUM, tmp, \ |
02892e06 | 1172 | 6 - (CUM), (6 - (CUM)) * UNITS_PER_WORD); \ |
130d2d72 RK |
1173 | } \ |
1174 | PRETEND_SIZE = 12 * UNITS_PER_WORD; \ | |
1175 | } \ | |
1176 | } | |
1177 | ||
c8e9adec RK |
1178 | /* Try to output insns to set TARGET equal to the constant C if it can be |
1179 | done in less than N insns. Do all computations in MODE. Returns the place | |
1180 | where the output has been placed if it can be done and the insns have been | |
1181 | emitted. If it would take more than N insns, zero is returned and no | |
1182 | insns and emitted. */ | |
92e40a7a | 1183 | |
1a94ca49 RK |
1184 | /* Define the information needed to generate branch and scc insns. This is |
1185 | stored from the compare operation. Note that we can't use "rtx" here | |
1186 | since it hasn't been defined! */ | |
1187 | ||
6db21c7f RH |
1188 | struct alpha_compare |
1189 | { | |
1190 | struct rtx_def *op0, *op1; | |
1191 | int fp_p; | |
1192 | }; | |
1193 | ||
1194 | extern struct alpha_compare alpha_compare; | |
1a94ca49 | 1195 | |
e5958492 | 1196 | /* Make (or fake) .linkage entry for function call. |
e5958492 | 1197 | IS_LOCAL is 0 if name is used in call, 1 if name is used in definition. */ |
e5958492 | 1198 | |
bcbbac26 RH |
1199 | /* This macro defines the start of an assembly comment. */ |
1200 | ||
1201 | #define ASM_COMMENT_START " #" | |
1202 | ||
acd92049 | 1203 | /* This macro produces the initial definition of a function. */ |
1a94ca49 | 1204 | |
acd92049 RH |
1205 | #define ASM_DECLARE_FUNCTION_NAME(FILE,NAME,DECL) \ |
1206 | alpha_start_function(FILE,NAME,DECL); | |
1a94ca49 | 1207 | |
acd92049 | 1208 | /* This macro closes up a function definition for the assembler. */ |
9c0e94a5 | 1209 | |
acd92049 RH |
1210 | #define ASM_DECLARE_FUNCTION_SIZE(FILE,NAME,DECL) \ |
1211 | alpha_end_function(FILE,NAME,DECL) | |
acd92049 | 1212 | |
acd92049 RH |
1213 | /* Output any profiling code before the prologue. */ |
1214 | ||
1215 | #define PROFILE_BEFORE_PROLOGUE 1 | |
1216 | ||
fbadafbc RH |
1217 | /* Never use profile counters. */ |
1218 | ||
1219 | #define NO_PROFILE_COUNTERS 1 | |
1220 | ||
1a94ca49 | 1221 | /* Output assembler code to FILE to increment profiler label # LABELNO |
e0fb9029 | 1222 | for profiling a function entry. Under OSF/1, profiling is enabled |
ddd5a7c1 | 1223 | by simply passing -pg to the assembler and linker. */ |
85d159a3 | 1224 | |
e0fb9029 | 1225 | #define FUNCTION_PROFILER(FILE, LABELNO) |
85d159a3 | 1226 | |
1a94ca49 RK |
1227 | /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, |
1228 | the stack pointer does not matter. The value is tested only in | |
1229 | functions that have frame pointers. | |
1230 | No definition is equivalent to always zero. */ | |
1231 | ||
1232 | #define EXIT_IGNORE_STACK 1 | |
c112e233 RH |
1233 | |
1234 | /* Define registers used by the epilogue and return instruction. */ | |
1235 | ||
1236 | #define EPILOGUE_USES(REGNO) ((REGNO) == 26) | |
1a94ca49 RK |
1237 | \f |
1238 | /* Output assembler code for a block containing the constant parts | |
1239 | of a trampoline, leaving space for the variable parts. | |
1240 | ||
1241 | The trampoline should set the static chain pointer to value placed | |
7981384f RK |
1242 | into the trampoline and should branch to the specified routine. |
1243 | Note that $27 has been set to the address of the trampoline, so we can | |
30864e14 | 1244 | use it for addressability of the two data items. */ |
1a94ca49 RK |
1245 | |
1246 | #define TRAMPOLINE_TEMPLATE(FILE) \ | |
c714f03d | 1247 | do { \ |
7981384f | 1248 | fprintf (FILE, "\tldq $1,24($27)\n"); \ |
1a94ca49 | 1249 | fprintf (FILE, "\tldq $27,16($27)\n"); \ |
7981384f RK |
1250 | fprintf (FILE, "\tjmp $31,($27),0\n"); \ |
1251 | fprintf (FILE, "\tnop\n"); \ | |
1a94ca49 | 1252 | fprintf (FILE, "\t.quad 0,0\n"); \ |
c714f03d | 1253 | } while (0) |
1a94ca49 | 1254 | |
3a523eeb RS |
1255 | /* Section in which to place the trampoline. On Alpha, instructions |
1256 | may only be placed in a text segment. */ | |
1257 | ||
1258 | #define TRAMPOLINE_SECTION text_section | |
1259 | ||
1a94ca49 RK |
1260 | /* Length in units of the trampoline for entering a nested function. */ |
1261 | ||
7981384f | 1262 | #define TRAMPOLINE_SIZE 32 |
1a94ca49 | 1263 | |
30864e14 RH |
1264 | /* The alignment of a trampoline, in bits. */ |
1265 | ||
1266 | #define TRAMPOLINE_ALIGNMENT 64 | |
1267 | ||
1a94ca49 RK |
1268 | /* Emit RTL insns to initialize the variable parts of a trampoline. |
1269 | FNADDR is an RTX for the address of the function's pure code. | |
c714f03d | 1270 | CXT is an RTX for the static chain value for the function. */ |
1a94ca49 | 1271 | |
9ec36da5 | 1272 | #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ |
c714f03d | 1273 | alpha_initialize_trampoline (TRAMP, FNADDR, CXT, 16, 24, 8) |
675f0e7c RK |
1274 | |
1275 | /* A C expression whose value is RTL representing the value of the return | |
1276 | address for the frame COUNT steps up from the current frame. | |
1277 | FRAMEADDR is the frame pointer of the COUNT frame, or the frame pointer of | |
952fc2ed | 1278 | the COUNT-1 frame if RETURN_ADDR_IN_PREVIOUS_FRAME is defined. */ |
675f0e7c | 1279 | |
9ecc37f0 | 1280 | #define RETURN_ADDR_RTX alpha_return_addr |
9ecc37f0 | 1281 | |
285a5742 | 1282 | /* Before the prologue, RA lives in $26. */ |
6abc6f40 | 1283 | #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, 26) |
8034da37 | 1284 | #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (26) |
4573b4de RH |
1285 | |
1286 | /* Describe how we implement __builtin_eh_return. */ | |
1287 | #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 16 : INVALID_REGNUM) | |
1288 | #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 28) | |
1289 | #define EH_RETURN_HANDLER_RTX \ | |
1290 | gen_rtx_MEM (Pmode, plus_constant (stack_pointer_rtx, \ | |
1291 | current_function_outgoing_args_size)) | |
675f0e7c | 1292 | \f |
1a94ca49 RK |
1293 | /* Addressing modes, and classification of registers for them. */ |
1294 | ||
1a94ca49 RK |
1295 | /* Macros to check register numbers against specific register classes. */ |
1296 | ||
1297 | /* These assume that REGNO is a hard or pseudo reg number. | |
1298 | They give nonzero only if REGNO is a hard reg of the suitable class | |
1299 | or a pseudo reg currently allocated to a suitable hard reg. | |
1300 | Since they use reg_renumber, they are safe only once reg_renumber | |
1301 | has been allocated, which happens in local-alloc.c. */ | |
1302 | ||
1303 | #define REGNO_OK_FOR_INDEX_P(REGNO) 0 | |
1304 | #define REGNO_OK_FOR_BASE_P(REGNO) \ | |
52a69200 RK |
1305 | ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32 \ |
1306 | || (REGNO) == 63 || reg_renumber[REGNO] == 63) | |
1a94ca49 RK |
1307 | \f |
1308 | /* Maximum number of registers that can appear in a valid memory address. */ | |
1309 | #define MAX_REGS_PER_ADDRESS 1 | |
1310 | ||
1311 | /* Recognize any constant value that is a valid address. For the Alpha, | |
1312 | there are only constants none since we want to use LDA to load any | |
1313 | symbolic addresses into registers. */ | |
1314 | ||
1315 | #define CONSTANT_ADDRESS_P(X) \ | |
1316 | (GET_CODE (X) == CONST_INT \ | |
1317 | && (unsigned HOST_WIDE_INT) (INTVAL (X) + 0x8000) < 0x10000) | |
1318 | ||
1319 | /* Include all constant integers and constant doubles, but not | |
1320 | floating-point, except for floating-point zero. */ | |
1321 | ||
1322 | #define LEGITIMATE_CONSTANT_P(X) \ | |
1323 | (GET_MODE_CLASS (GET_MODE (X)) != MODE_FLOAT \ | |
1324 | || (X) == CONST0_RTX (GET_MODE (X))) | |
1325 | ||
1326 | /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx | |
1327 | and check its validity for a certain class. | |
1328 | We have two alternate definitions for each of them. | |
1329 | The usual definition accepts all pseudo regs; the other rejects | |
1330 | them unless they have been allocated suitable hard regs. | |
1331 | The symbol REG_OK_STRICT causes the latter definition to be used. | |
1332 | ||
1333 | Most source files want to accept pseudo regs in the hope that | |
1334 | they will get allocated to the class that the insn wants them to be in. | |
1335 | Source files for reload pass need to be strict. | |
1336 | After reload, it makes no difference, since pseudo regs have | |
1337 | been eliminated by then. */ | |
1338 | ||
1a94ca49 RK |
1339 | /* Nonzero if X is a hard reg that can be used as an index |
1340 | or if it is a pseudo reg. */ | |
1341 | #define REG_OK_FOR_INDEX_P(X) 0 | |
5d02b6c2 | 1342 | |
1a94ca49 RK |
1343 | /* Nonzero if X is a hard reg that can be used as a base reg |
1344 | or if it is a pseudo reg. */ | |
a39bdefc | 1345 | #define NONSTRICT_REG_OK_FOR_BASE_P(X) \ |
52a69200 | 1346 | (REGNO (X) < 32 || REGNO (X) == 63 || REGNO (X) >= FIRST_PSEUDO_REGISTER) |
1a94ca49 | 1347 | |
5d02b6c2 RH |
1348 | /* ??? Nonzero if X is the frame pointer, or some virtual register |
1349 | that may eliminate to the frame pointer. These will be allowed to | |
1350 | have offsets greater than 32K. This is done because register | |
1351 | elimination offsets will change the hi/lo split, and if we split | |
285a5742 | 1352 | before reload, we will require additional instructions. */ |
a39bdefc | 1353 | #define NONSTRICT_REG_OK_FP_BASE_P(X) \ |
5d02b6c2 RH |
1354 | (REGNO (X) == 31 || REGNO (X) == 63 \ |
1355 | || (REGNO (X) >= FIRST_PSEUDO_REGISTER \ | |
1356 | && REGNO (X) < LAST_VIRTUAL_REGISTER)) | |
1357 | ||
1a94ca49 | 1358 | /* Nonzero if X is a hard reg that can be used as a base reg. */ |
a39bdefc | 1359 | #define STRICT_REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) |
5d02b6c2 | 1360 | |
a39bdefc RH |
1361 | #ifdef REG_OK_STRICT |
1362 | #define REG_OK_FOR_BASE_P(X) STRICT_REG_OK_FOR_BASE_P (X) | |
1363 | #else | |
1364 | #define REG_OK_FOR_BASE_P(X) NONSTRICT_REG_OK_FOR_BASE_P (X) | |
1a94ca49 RK |
1365 | #endif |
1366 | \f | |
a39bdefc RH |
1367 | /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression that is a |
1368 | valid memory address for an instruction. */ | |
1a94ca49 | 1369 | |
a39bdefc RH |
1370 | #ifdef REG_OK_STRICT |
1371 | #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \ | |
1372 | do { \ | |
1373 | if (alpha_legitimate_address_p (MODE, X, 1)) \ | |
1374 | goto WIN; \ | |
1375 | } while (0) | |
1376 | #else | |
1377 | #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \ | |
1378 | do { \ | |
1379 | if (alpha_legitimate_address_p (MODE, X, 0)) \ | |
1380 | goto WIN; \ | |
1381 | } while (0) | |
1382 | #endif | |
1a94ca49 RK |
1383 | |
1384 | /* Try machine-dependent ways of modifying an illegitimate address | |
1385 | to be legitimate. If we find one, return the new, valid address. | |
a39bdefc | 1386 | This macro is used in only one place: `memory_address' in explow.c. */ |
aead1ca3 | 1387 | |
551cc6fd RH |
1388 | #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \ |
1389 | do { \ | |
1390 | rtx new_x = alpha_legitimize_address (X, NULL_RTX, MODE); \ | |
1391 | if (new_x) \ | |
1392 | { \ | |
1393 | X = new_x; \ | |
1394 | goto WIN; \ | |
1395 | } \ | |
aead1ca3 | 1396 | } while (0) |
1a94ca49 | 1397 | |
a9a2595b JR |
1398 | /* Try a machine-dependent way of reloading an illegitimate address |
1399 | operand. If we find one, push the reload and jump to WIN. This | |
aead1ca3 | 1400 | macro is used in only one place: `find_reloads_address' in reload.c. */ |
a9a2595b | 1401 | |
aead1ca3 RH |
1402 | #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_L,WIN) \ |
1403 | do { \ | |
1404 | rtx new_x = alpha_legitimize_reload_address (X, MODE, OPNUM, TYPE, IND_L); \ | |
1405 | if (new_x) \ | |
1406 | { \ | |
1407 | X = new_x; \ | |
1408 | goto WIN; \ | |
1409 | } \ | |
a9a2595b JR |
1410 | } while (0) |
1411 | ||
1a94ca49 RK |
1412 | /* Go to LABEL if ADDR (a legitimate address expression) |
1413 | has an effect that depends on the machine mode it is used for. | |
1414 | On the Alpha this is true only for the unaligned modes. We can | |
1415 | simplify this test since we know that the address must be valid. */ | |
1416 | ||
1417 | #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \ | |
1418 | { if (GET_CODE (ADDR) == AND) goto LABEL; } | |
1419 | ||
285a5742 | 1420 | /* Machine-dependent reorg pass. */ |
2ea844d3 | 1421 | #define MACHINE_DEPENDENT_REORG(X) alpha_reorg(X) |
1a94ca49 RK |
1422 | \f |
1423 | /* Specify the machine mode that this machine uses | |
1424 | for the index in the tablejump instruction. */ | |
1425 | #define CASE_VECTOR_MODE SImode | |
1426 | ||
18543a22 ILT |
1427 | /* Define as C expression which evaluates to nonzero if the tablejump |
1428 | instruction expects the table to contain offsets from the address of the | |
3aa9d5b6 | 1429 | table. |
b0435cf4 | 1430 | |
3aa9d5b6 | 1431 | Do not define this if the table should contain absolute addresses. |
260ced47 RK |
1432 | On the Alpha, the table is really GP-relative, not relative to the PC |
1433 | of the table, but we pretend that it is PC-relative; this should be OK, | |
0076aa6b | 1434 | but we should try to find some better way sometime. */ |
18543a22 | 1435 | #define CASE_VECTOR_PC_RELATIVE 1 |
1a94ca49 | 1436 | |
1a94ca49 RK |
1437 | /* Define this as 1 if `char' should by default be signed; else as 0. */ |
1438 | #define DEFAULT_SIGNED_CHAR 1 | |
1439 | ||
1440 | /* This flag, if defined, says the same insns that convert to a signed fixnum | |
1441 | also convert validly to an unsigned one. | |
1442 | ||
1443 | We actually lie a bit here as overflow conditions are different. But | |
1444 | they aren't being checked anyway. */ | |
1445 | ||
1446 | #define FIXUNS_TRUNC_LIKE_FIX_TRUNC | |
1447 | ||
1448 | /* Max number of bytes we can move to or from memory | |
1449 | in one reasonably fast instruction. */ | |
1450 | ||
1451 | #define MOVE_MAX 8 | |
1452 | ||
7e24ffc9 HPN |
1453 | /* If a memory-to-memory move would take MOVE_RATIO or more simple |
1454 | move-instruction pairs, we will do a movstr or libcall instead. | |
1455 | ||
1456 | Without byte/word accesses, we want no more than four instructions; | |
285a5742 | 1457 | with, several single byte accesses are better. */ |
6c174fc0 RH |
1458 | |
1459 | #define MOVE_RATIO (TARGET_BWX ? 7 : 2) | |
1460 | ||
1a94ca49 RK |
1461 | /* Largest number of bytes of an object that can be placed in a register. |
1462 | On the Alpha we have plenty of registers, so use TImode. */ | |
1463 | #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TImode) | |
1464 | ||
1465 | /* Nonzero if access to memory by bytes is no faster than for words. | |
825dda42 | 1466 | Also nonzero if doing byte operations (specifically shifts) in registers |
1a94ca49 RK |
1467 | is undesirable. |
1468 | ||
1469 | On the Alpha, we want to not use the byte operation and instead use | |
1470 | masking operations to access fields; these will save instructions. */ | |
1471 | ||
1472 | #define SLOW_BYTE_ACCESS 1 | |
1473 | ||
9a63901f RK |
1474 | /* Define if operations between registers always perform the operation |
1475 | on the full register even if a narrower mode is specified. */ | |
1476 | #define WORD_REGISTER_OPERATIONS | |
1477 | ||
1478 | /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD | |
1479 | will either zero-extend or sign-extend. The value of this macro should | |
1480 | be the code that says which one of the two operations is implicitly | |
1481 | done, NIL if none. */ | |
b7747781 | 1482 | #define LOAD_EXTEND_OP(MODE) ((MODE) == SImode ? SIGN_EXTEND : ZERO_EXTEND) |
1a94ca49 | 1483 | |
225211e2 RK |
1484 | /* Define if loading short immediate values into registers sign extends. */ |
1485 | #define SHORT_IMMEDIATES_SIGN_EXTEND | |
1486 | ||
1a94ca49 RK |
1487 | /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits |
1488 | is done just by pretending it is already truncated. */ | |
1489 | #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 | |
1490 | ||
1491 | /* We assume that the store-condition-codes instructions store 0 for false | |
1492 | and some other value for true. This is the value stored for true. */ | |
1493 | ||
1494 | #define STORE_FLAG_VALUE 1 | |
1495 | ||
7dba8395 RH |
1496 | /* The CIX ctlz and cttz instructions return 64 for zero. */ |
1497 | #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 64, TARGET_CIX) | |
1498 | #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 64, TARGET_CIX) | |
1499 | ||
1a94ca49 RK |
1500 | /* Define the value returned by a floating-point comparison instruction. */ |
1501 | ||
12530dbe RH |
1502 | #define FLOAT_STORE_FLAG_VALUE(MODE) \ |
1503 | REAL_VALUE_ATOF ((TARGET_FLOAT_VAX ? "0.5" : "2.0"), (MODE)) | |
1a94ca49 | 1504 | |
35bb77fd RK |
1505 | /* Canonicalize a comparison from one we don't have to one we do have. */ |
1506 | ||
1507 | #define CANONICALIZE_COMPARISON(CODE,OP0,OP1) \ | |
1508 | do { \ | |
1509 | if (((CODE) == GE || (CODE) == GT || (CODE) == GEU || (CODE) == GTU) \ | |
1510 | && (GET_CODE (OP1) == REG || (OP1) == const0_rtx)) \ | |
1511 | { \ | |
1512 | rtx tem = (OP0); \ | |
1513 | (OP0) = (OP1); \ | |
1514 | (OP1) = tem; \ | |
1515 | (CODE) = swap_condition (CODE); \ | |
1516 | } \ | |
1517 | if (((CODE) == LT || (CODE) == LTU) \ | |
1518 | && GET_CODE (OP1) == CONST_INT && INTVAL (OP1) == 256) \ | |
1519 | { \ | |
1520 | (CODE) = (CODE) == LT ? LE : LEU; \ | |
1521 | (OP1) = GEN_INT (255); \ | |
1522 | } \ | |
1523 | } while (0) | |
1524 | ||
1a94ca49 RK |
1525 | /* Specify the machine mode that pointers have. |
1526 | After generation of rtl, the compiler makes no further distinction | |
1527 | between pointers and any other objects of this machine mode. */ | |
1528 | #define Pmode DImode | |
1529 | ||
285a5742 | 1530 | /* Mode of a function address in a call instruction (for indexing purposes). */ |
1a94ca49 RK |
1531 | |
1532 | #define FUNCTION_MODE Pmode | |
1533 | ||
1534 | /* Define this if addresses of constant functions | |
1535 | shouldn't be put through pseudo regs where they can be cse'd. | |
1536 | Desirable on machines where ordinary constants are expensive | |
1537 | but a CALL with constant address is cheap. | |
1538 | ||
1539 | We define this on the Alpha so that gen_call and gen_call_value | |
1540 | get to see the SYMBOL_REF (for the hint field of the jsr). It will | |
1541 | then copy it into a register, thus actually letting the address be | |
1542 | cse'ed. */ | |
1543 | ||
1544 | #define NO_FUNCTION_CSE | |
1545 | ||
d969caf8 | 1546 | /* Define this to be nonzero if shift instructions ignore all but the low-order |
285a5742 | 1547 | few bits. */ |
d969caf8 | 1548 | #define SHIFT_COUNT_TRUNCATED 1 |
1a94ca49 RK |
1549 | \f |
1550 | /* Control the assembler format that we output. */ | |
1551 | ||
1a94ca49 RK |
1552 | /* Output to assembler file text saying following lines |
1553 | may contain character constants, extra white space, comments, etc. */ | |
1eb356b9 | 1554 | #define ASM_APP_ON (TARGET_EXPLICIT_RELOCS ? "\t.set\tmacro\n" : "") |
1a94ca49 RK |
1555 | |
1556 | /* Output to assembler file text saying following lines | |
1557 | no longer contain unusual constructs. */ | |
1eb356b9 | 1558 | #define ASM_APP_OFF (TARGET_EXPLICIT_RELOCS ? "\t.set\tnomacro\n" : "") |
1a94ca49 | 1559 | |
93de6f51 | 1560 | #define TEXT_SECTION_ASM_OP "\t.text" |
1a94ca49 RK |
1561 | |
1562 | /* Output before read-only data. */ | |
1563 | ||
93de6f51 | 1564 | #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" |
1a94ca49 RK |
1565 | |
1566 | /* Output before writable data. */ | |
1567 | ||
93de6f51 | 1568 | #define DATA_SECTION_ASM_OP "\t.data" |
1a94ca49 | 1569 | |
1a94ca49 RK |
1570 | /* How to refer to registers in assembler output. |
1571 | This sequence is indexed by compiler's hard-register-number (see above). */ | |
1572 | ||
1573 | #define REGISTER_NAMES \ | |
1574 | {"$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", "$8", \ | |
1575 | "$9", "$10", "$11", "$12", "$13", "$14", "$15", \ | |
1576 | "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \ | |
130d2d72 | 1577 | "$24", "$25", "$26", "$27", "$28", "$29", "$30", "AP", \ |
1a94ca49 RK |
1578 | "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", "$f8", \ |
1579 | "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \ | |
1580 | "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",\ | |
52a69200 | 1581 | "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "FP"} |
1a94ca49 | 1582 | |
1eb356b9 RH |
1583 | /* Strip name encoding when emitting labels. */ |
1584 | ||
1585 | #define ASM_OUTPUT_LABELREF(STREAM, NAME) \ | |
1586 | do { \ | |
1587 | const char *name_ = NAME; \ | |
53e8b0b8 | 1588 | if (*name_ == '@' || *name_ == '%') \ |
1eb356b9 RH |
1589 | name_ += 2; \ |
1590 | if (*name_ == '*') \ | |
1591 | name_++; \ | |
1592 | else \ | |
1593 | fputs (user_label_prefix, STREAM); \ | |
1594 | fputs (name_, STREAM); \ | |
1595 | } while (0) | |
1596 | ||
506a61b1 KG |
1597 | /* Globalizing directive for a label. */ |
1598 | #define GLOBAL_ASM_OP "\t.globl " | |
1a94ca49 | 1599 | |
285a5742 | 1600 | /* The prefix to add to user-visible assembler symbols. */ |
1a94ca49 | 1601 | |
4e0c8ad2 | 1602 | #define USER_LABEL_PREFIX "" |
1a94ca49 | 1603 | |
1a94ca49 | 1604 | /* This is how to output a label for a jump table. Arguments are the same as |
4977bab6 | 1605 | for (*targetm.asm_out.internal_label), except the insn for the jump table is |
285a5742 | 1606 | passed. */ |
1a94ca49 RK |
1607 | |
1608 | #define ASM_OUTPUT_CASE_LABEL(FILE,PREFIX,NUM,TABLEINSN) \ | |
4977bab6 | 1609 | { ASM_OUTPUT_ALIGN (FILE, 2); (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); } |
1a94ca49 RK |
1610 | |
1611 | /* This is how to store into the string LABEL | |
1612 | the symbol_ref name of an internal numbered label where | |
1613 | PREFIX is the class of label and NUM is the number within the class. | |
1614 | This is suitable for output with `assemble_name'. */ | |
1615 | ||
1616 | #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ | |
d1e6b55b | 1617 | sprintf ((LABEL), "*$%s%ld", (PREFIX), (long)(NUM)) |
1a94ca49 | 1618 | |
1a94ca49 RK |
1619 | /* We use the default ASCII-output routine, except that we don't write more |
1620 | than 50 characters since the assembler doesn't support very long lines. */ | |
1621 | ||
1622 | #define ASM_OUTPUT_ASCII(MYFILE, MYSTRING, MYLENGTH) \ | |
1623 | do { \ | |
1624 | FILE *_hide_asm_out_file = (MYFILE); \ | |
e03c5670 | 1625 | const unsigned char *_hide_p = (const unsigned char *) (MYSTRING); \ |
1a94ca49 RK |
1626 | int _hide_thissize = (MYLENGTH); \ |
1627 | int _size_so_far = 0; \ | |
1628 | { \ | |
1629 | FILE *asm_out_file = _hide_asm_out_file; \ | |
e03c5670 | 1630 | const unsigned char *p = _hide_p; \ |
1a94ca49 RK |
1631 | int thissize = _hide_thissize; \ |
1632 | int i; \ | |
1633 | fprintf (asm_out_file, "\t.ascii \""); \ | |
1634 | \ | |
1635 | for (i = 0; i < thissize; i++) \ | |
1636 | { \ | |
1637 | register int c = p[i]; \ | |
1638 | \ | |
1639 | if (_size_so_far ++ > 50 && i < thissize - 4) \ | |
1640 | _size_so_far = 0, fprintf (asm_out_file, "\"\n\t.ascii \""); \ | |
1641 | \ | |
1642 | if (c == '\"' || c == '\\') \ | |
1643 | putc ('\\', asm_out_file); \ | |
1644 | if (c >= ' ' && c < 0177) \ | |
1645 | putc (c, asm_out_file); \ | |
1646 | else \ | |
1647 | { \ | |
1648 | fprintf (asm_out_file, "\\%o", c); \ | |
1649 | /* After an octal-escape, if a digit follows, \ | |
1650 | terminate one string constant and start another. \ | |
8aeea6e6 | 1651 | The VAX assembler fails to stop reading the escape \ |
1a94ca49 RK |
1652 | after three digits, so this is the only way we \ |
1653 | can get it to parse the data properly. */ \ | |
0df6c2c7 | 1654 | if (i < thissize - 1 && ISDIGIT (p[i + 1])) \ |
b2d5e311 | 1655 | _size_so_far = 0, fprintf (asm_out_file, "\"\n\t.ascii \""); \ |
1a94ca49 RK |
1656 | } \ |
1657 | } \ | |
1658 | fprintf (asm_out_file, "\"\n"); \ | |
1659 | } \ | |
1660 | } \ | |
1661 | while (0) | |
52a69200 | 1662 | |
260ced47 RK |
1663 | /* This is how to output an element of a case-vector that is absolute. |
1664 | (Alpha does not use such vectors, but we must define this macro anyway.) */ | |
1a94ca49 | 1665 | |
260ced47 | 1666 | #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) abort () |
1a94ca49 | 1667 | |
260ced47 | 1668 | /* This is how to output an element of a case-vector that is relative. */ |
1a94ca49 | 1669 | |
33f7f353 | 1670 | #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ |
be7b80f4 | 1671 | fprintf (FILE, "\t.%s $L%d\n", TARGET_ABI_WINDOWS_NT ? "long" : "gprel32", \ |
8dfe3c62 | 1672 | (VALUE)) |
1a94ca49 RK |
1673 | |
1674 | /* This is how to output an assembler line | |
1675 | that says to advance the location counter | |
1676 | to a multiple of 2**LOG bytes. */ | |
1677 | ||
1678 | #define ASM_OUTPUT_ALIGN(FILE,LOG) \ | |
1679 | if ((LOG) != 0) \ | |
1680 | fprintf (FILE, "\t.align %d\n", LOG); | |
1681 | ||
1682 | /* This is how to advance the location counter by SIZE bytes. */ | |
1683 | ||
1684 | #define ASM_OUTPUT_SKIP(FILE,SIZE) \ | |
1685 | fprintf (FILE, "\t.space %d\n", (SIZE)) | |
1686 | ||
1687 | /* This says how to output an assembler line | |
1688 | to define a global common symbol. */ | |
1689 | ||
1690 | #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ | |
1691 | ( fputs ("\t.comm ", (FILE)), \ | |
1692 | assemble_name ((FILE), (NAME)), \ | |
1693 | fprintf ((FILE), ",%d\n", (SIZE))) | |
1694 | ||
1695 | /* This says how to output an assembler line | |
1696 | to define a local common symbol. */ | |
1697 | ||
1698 | #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE,ROUNDED) \ | |
1699 | ( fputs ("\t.lcomm ", (FILE)), \ | |
1700 | assemble_name ((FILE), (NAME)), \ | |
1701 | fprintf ((FILE), ",%d\n", (SIZE))) | |
60593797 | 1702 | \f |
9ec36da5 | 1703 | |
1a94ca49 RK |
1704 | /* Print operand X (an rtx) in assembler syntax to file FILE. |
1705 | CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. | |
1706 | For `%' followed by punctuation, CODE is the punctuation and X is null. */ | |
1707 | ||
1708 | #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) | |
1709 | ||
1710 | /* Determine which codes are valid without a following integer. These must | |
941cc05a RK |
1711 | not be alphabetic. |
1712 | ||
1713 | ~ Generates the name of the current function. | |
2bf6230d | 1714 | |
be7560ea RH |
1715 | / Generates the instruction suffix. The TRAP_SUFFIX and ROUND_SUFFIX |
1716 | attributes are examined to determine what is appropriate. | |
e5958492 RK |
1717 | |
1718 | , Generates single precision suffix for floating point | |
1719 | instructions (s for IEEE, f for VAX) | |
1720 | ||
1721 | - Generates double precision suffix for floating point | |
1722 | instructions (t for IEEE, g for VAX) | |
39ee7fa9 OH |
1723 | |
1724 | + Generates a nop instruction after a noreturn call at the very end | |
1725 | of the function | |
2bf6230d | 1726 | */ |
1a94ca49 | 1727 | |
be7560ea | 1728 | #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ |
1eb356b9 | 1729 | ((CODE) == '/' || (CODE) == ',' || (CODE) == '-' || (CODE) == '~' \ |
39ee7fa9 | 1730 | || (CODE) == '#' || (CODE) == '*' || (CODE) == '&' || (CODE) == '+') |
1a94ca49 RK |
1731 | \f |
1732 | /* Print a memory address as an operand to reference that memory location. */ | |
1733 | ||
714b019c RH |
1734 | #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ |
1735 | print_operand_address((FILE), (ADDR)) | |
1736 | ||
1a94ca49 RK |
1737 | /* Define the codes that are matched by predicates in alpha.c. */ |
1738 | ||
e3208d53 | 1739 | #define PREDICATE_CODES \ |
73db7137 RH |
1740 | {"reg_or_0_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE, \ |
1741 | CONST_VECTOR}}, \ | |
eb8da868 RH |
1742 | {"reg_or_6bit_operand", {SUBREG, REG, CONST_INT}}, \ |
1743 | {"reg_or_8bit_operand", {SUBREG, REG, CONST_INT}}, \ | |
6d8fd7bb | 1744 | {"reg_or_const_int_operand", {SUBREG, REG, CONST_INT}}, \ |
eb8da868 RH |
1745 | {"cint8_operand", {CONST_INT}}, \ |
1746 | {"reg_or_cint_operand", {SUBREG, REG, CONST_INT}}, \ | |
1747 | {"add_operand", {SUBREG, REG, CONST_INT}}, \ | |
1748 | {"sext_add_operand", {SUBREG, REG, CONST_INT}}, \ | |
e3208d53 | 1749 | {"const48_operand", {CONST_INT}}, \ |
eb8da868 RH |
1750 | {"and_operand", {SUBREG, REG, CONST_INT}}, \ |
1751 | {"or_operand", {SUBREG, REG, CONST_INT}}, \ | |
e3208d53 RH |
1752 | {"mode_mask_operand", {CONST_INT}}, \ |
1753 | {"mul8_operand", {CONST_INT}}, \ | |
1754 | {"mode_width_operand", {CONST_INT}}, \ | |
e3208d53 | 1755 | {"alpha_comparison_operator", {EQ, LE, LT, LEU, LTU}}, \ |
8f4773ea | 1756 | {"alpha_zero_comparison_operator", {EQ, NE, LE, LT, LEU, LTU}}, \ |
e3208d53 RH |
1757 | {"alpha_swapped_comparison_operator", {EQ, GE, GT, GEU, GTU}}, \ |
1758 | {"signed_comparison_operator", {EQ, NE, LE, LT, GE, GT}}, \ | |
1eb8759b | 1759 | {"alpha_fp_comparison_operator", {EQ, LE, LT, UNORDERED}}, \ |
e3208d53 | 1760 | {"divmod_operator", {DIV, MOD, UDIV, UMOD}}, \ |
73db7137 | 1761 | {"const0_operand", {CONST_INT, CONST_DOUBLE, CONST_VECTOR}}, \ |
3094247f | 1762 | {"samegp_function_operand", {SYMBOL_REF}}, \ |
1afec8ad | 1763 | {"direct_call_operand", {SYMBOL_REF}}, \ |
1eb356b9 | 1764 | {"local_symbolic_operand", {SYMBOL_REF, CONST, LABEL_REF}}, \ |
e2c9fb9b RH |
1765 | {"small_symbolic_operand", {SYMBOL_REF, CONST}}, \ |
1766 | {"global_symbolic_operand", {SYMBOL_REF, CONST}}, \ | |
6f9b006d RH |
1767 | {"dtp16_symbolic_operand", {CONST}}, \ |
1768 | {"dtp32_symbolic_operand", {CONST}}, \ | |
1769 | {"gotdtp_symbolic_operand", {CONST}}, \ | |
1770 | {"tp16_symbolic_operand", {CONST}}, \ | |
1771 | {"tp32_symbolic_operand", {CONST}}, \ | |
1772 | {"gottp_symbolic_operand", {CONST}}, \ | |
e3208d53 RH |
1773 | {"call_operand", {REG, SYMBOL_REF}}, \ |
1774 | {"input_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE, \ | |
6d8fd7bb | 1775 | CONST_VECTOR, SYMBOL_REF, CONST, LABEL_REF, HIGH}},\ |
e3208d53 | 1776 | {"some_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE, \ |
6d8fd7bb | 1777 | CONST_VECTOR, SYMBOL_REF, CONST, LABEL_REF, HIGH}}, \ |
f711a22b | 1778 | {"some_ni_operand", {SUBREG, REG, MEM}}, \ |
e3208d53 RH |
1779 | {"aligned_memory_operand", {MEM}}, \ |
1780 | {"unaligned_memory_operand", {MEM}}, \ | |
1781 | {"reg_or_unaligned_mem_operand", {SUBREG, REG, MEM}}, \ | |
1782 | {"any_memory_operand", {MEM}}, \ | |
40b80dad | 1783 | {"hard_fp_register_operand", {SUBREG, REG}}, \ |
d2c6a1b6 | 1784 | {"hard_int_register_operand", {SUBREG, REG}}, \ |
67070f5c | 1785 | {"reg_not_elim_operand", {SUBREG, REG}}, \ |
3611aef0 | 1786 | {"reg_no_subreg_operand", {REG}}, \ |
30102605 | 1787 | {"addition_operation", {PLUS}}, \ |
551cc6fd | 1788 | {"symbolic_operand", {SYMBOL_REF, LABEL_REF, CONST}}, \ |
a615ca3e RH |
1789 | {"some_small_symbolic_operand", {SET, PARALLEL, PREFETCH, UNSPEC, \ |
1790 | UNSPEC_VOLATILE}}, | |
03f8c4cc | 1791 | \f |
63966b3b RH |
1792 | /* Define the `__builtin_va_list' type for the ABI. */ |
1793 | #define BUILD_VA_LIST_TYPE(VALIST) \ | |
1794 | (VALIST) = alpha_build_va_list () | |
1795 | ||
1796 | /* Implement `va_start' for varargs and stdarg. */ | |
e5faf155 ZW |
1797 | #define EXPAND_BUILTIN_VA_START(valist, nextarg) \ |
1798 | alpha_va_start (valist, nextarg) | |
63966b3b RH |
1799 | |
1800 | /* Implement `va_arg'. */ | |
1801 | #define EXPAND_BUILTIN_VA_ARG(valist, type) \ | |
1802 | alpha_va_arg (valist, type) | |
1803 | \f | |
34fa88ab RK |
1804 | /* Tell collect that the object format is ECOFF. */ |
1805 | #define OBJECT_FORMAT_COFF | |
1806 | #define EXTENDED_COFF | |
1807 | ||
1808 | /* If we use NM, pass -g to it so it only lists globals. */ | |
1809 | #define NM_FLAGS "-pg" | |
1810 | ||
03f8c4cc RK |
1811 | /* Definitions for debugging. */ |
1812 | ||
23532de9 JT |
1813 | #define SDB_DEBUGGING_INFO 1 /* generate info for mips-tfile */ |
1814 | #define DBX_DEBUGGING_INFO 1 /* generate embedded stabs */ | |
1815 | #define MIPS_DEBUGGING_INFO 1 /* MIPS specific debugging info */ | |
03f8c4cc RK |
1816 | |
1817 | #ifndef PREFERRED_DEBUGGING_TYPE /* assume SDB_DEBUGGING_INFO */ | |
fe0986b4 | 1818 | #define PREFERRED_DEBUGGING_TYPE SDB_DEBUG |
03f8c4cc RK |
1819 | #endif |
1820 | ||
1821 | ||
1822 | /* Correct the offset of automatic variables and arguments. Note that | |
1823 | the Alpha debug format wants all automatic variables and arguments | |
1824 | to be in terms of two different offsets from the virtual frame pointer, | |
1825 | which is the stack pointer before any adjustment in the function. | |
1826 | The offset for the argument pointer is fixed for the native compiler, | |
1827 | it is either zero (for the no arguments case) or large enough to hold | |
1828 | all argument registers. | |
1829 | The offset for the auto pointer is the fourth argument to the .frame | |
1830 | directive (local_offset). | |
1831 | To stay compatible with the native tools we use the same offsets | |
1832 | from the virtual frame pointer and adjust the debugger arg/auto offsets | |
1833 | accordingly. These debugger offsets are set up in output_prolog. */ | |
1834 | ||
9a0b18f2 RK |
1835 | extern long alpha_arg_offset; |
1836 | extern long alpha_auto_offset; | |
03f8c4cc RK |
1837 | #define DEBUGGER_AUTO_OFFSET(X) \ |
1838 | ((GET_CODE (X) == PLUS ? INTVAL (XEXP (X, 1)) : 0) + alpha_auto_offset) | |
1839 | #define DEBUGGER_ARG_OFFSET(OFFSET, X) (OFFSET + alpha_arg_offset) | |
1840 | ||
1841 | ||
1842 | #define ASM_OUTPUT_SOURCE_LINE(STREAM, LINE) \ | |
1843 | alpha_output_lineno (STREAM, LINE) | |
03f8c4cc RK |
1844 | |
1845 | #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \ | |
1846 | alpha_output_filename (STREAM, NAME) | |
03f8c4cc | 1847 | |
4330b0e7 JW |
1848 | /* mips-tfile.c limits us to strings of one page. We must underestimate this |
1849 | number, because the real length runs past this up to the next | |
1850 | continuation point. This is really a dbxout.c bug. */ | |
1851 | #define DBX_CONTIN_LENGTH 3000 | |
03f8c4cc RK |
1852 | |
1853 | /* By default, turn on GDB extensions. */ | |
1854 | #define DEFAULT_GDB_EXTENSIONS 1 | |
1855 | ||
7aadc7c2 RK |
1856 | /* Stabs-in-ECOFF can't handle dbxout_function_end(). */ |
1857 | #define NO_DBX_FUNCTION_END 1 | |
1858 | ||
03f8c4cc RK |
1859 | /* If we are smuggling stabs through the ALPHA ECOFF object |
1860 | format, put a comment in front of the .stab<x> operation so | |
1861 | that the ALPHA assembler does not choke. The mips-tfile program | |
1862 | will correctly put the stab into the object file. */ | |
1863 | ||
93de6f51 HPN |
1864 | #define ASM_STABS_OP ((TARGET_GAS) ? "\t.stabs\t" : " #.stabs\t") |
1865 | #define ASM_STABN_OP ((TARGET_GAS) ? "\t.stabn\t" : " #.stabn\t") | |
1866 | #define ASM_STABD_OP ((TARGET_GAS) ? "\t.stabd\t" : " #.stabd\t") | |
03f8c4cc RK |
1867 | |
1868 | /* Forward references to tags are allowed. */ | |
1869 | #define SDB_ALLOW_FORWARD_REFERENCES | |
1870 | ||
1871 | /* Unknown tags are also allowed. */ | |
1872 | #define SDB_ALLOW_UNKNOWN_REFERENCES | |
1873 | ||
1874 | #define PUT_SDB_DEF(a) \ | |
1875 | do { \ | |
1876 | fprintf (asm_out_file, "\t%s.def\t", \ | |
1877 | (TARGET_GAS) ? "" : "#"); \ | |
1878 | ASM_OUTPUT_LABELREF (asm_out_file, a); \ | |
1879 | fputc (';', asm_out_file); \ | |
1880 | } while (0) | |
1881 | ||
1882 | #define PUT_SDB_PLAIN_DEF(a) \ | |
1883 | do { \ | |
1884 | fprintf (asm_out_file, "\t%s.def\t.%s;", \ | |
1885 | (TARGET_GAS) ? "" : "#", (a)); \ | |
1886 | } while (0) | |
1887 | ||
1888 | #define PUT_SDB_TYPE(a) \ | |
1889 | do { \ | |
1890 | fprintf (asm_out_file, "\t.type\t0x%x;", (a)); \ | |
1891 | } while (0) | |
1892 | ||
1893 | /* For block start and end, we create labels, so that | |
1894 | later we can figure out where the correct offset is. | |
1895 | The normal .ent/.end serve well enough for functions, | |
1896 | so those are just commented out. */ | |
1897 | ||
1898 | extern int sdb_label_count; /* block start/end next label # */ | |
1899 | ||
1900 | #define PUT_SDB_BLOCK_START(LINE) \ | |
1901 | do { \ | |
1902 | fprintf (asm_out_file, \ | |
1903 | "$Lb%d:\n\t%s.begin\t$Lb%d\t%d\n", \ | |
1904 | sdb_label_count, \ | |
1905 | (TARGET_GAS) ? "" : "#", \ | |
1906 | sdb_label_count, \ | |
1907 | (LINE)); \ | |
1908 | sdb_label_count++; \ | |
1909 | } while (0) | |
1910 | ||
1911 | #define PUT_SDB_BLOCK_END(LINE) \ | |
1912 | do { \ | |
1913 | fprintf (asm_out_file, \ | |
1914 | "$Le%d:\n\t%s.bend\t$Le%d\t%d\n", \ | |
1915 | sdb_label_count, \ | |
1916 | (TARGET_GAS) ? "" : "#", \ | |
1917 | sdb_label_count, \ | |
1918 | (LINE)); \ | |
1919 | sdb_label_count++; \ | |
1920 | } while (0) | |
1921 | ||
1922 | #define PUT_SDB_FUNCTION_START(LINE) | |
1923 | ||
1924 | #define PUT_SDB_FUNCTION_END(LINE) | |
1925 | ||
3c303f52 | 1926 | #define PUT_SDB_EPILOGUE_END(NAME) ((void)(NAME)) |
03f8c4cc | 1927 | |
03f8c4cc RK |
1928 | /* Macros for mips-tfile.c to encapsulate stabs in ECOFF, and for |
1929 | mips-tdump.c to print them out. | |
1930 | ||
1931 | These must match the corresponding definitions in gdb/mipsread.c. | |
285a5742 | 1932 | Unfortunately, gcc and gdb do not currently share any directories. */ |
03f8c4cc RK |
1933 | |
1934 | #define CODE_MASK 0x8F300 | |
1935 | #define MIPS_IS_STAB(sym) (((sym)->index & 0xFFF00) == CODE_MASK) | |
1936 | #define MIPS_MARK_STAB(code) ((code)+CODE_MASK) | |
1937 | #define MIPS_UNMARK_STAB(code) ((code)-CODE_MASK) | |
1938 | ||
1939 | /* Override some mips-tfile definitions. */ | |
1940 | ||
1941 | #define SHASH_SIZE 511 | |
1942 | #define THASH_SIZE 55 | |
1e6c6f11 RK |
1943 | |
1944 | /* Align ecoff symbol tables to avoid OSF1/1.3 nm complaints. */ | |
1945 | ||
1946 | #define ALIGN_SYMTABLE_OFFSET(OFFSET) (((OFFSET) + 7) & ~7) | |
2f55b70b | 1947 | |
b0435cf4 RH |
1948 | /* The system headers under Alpha systems are generally C++-aware. */ |
1949 | #define NO_IMPLICIT_EXTERN_C | |
b517dcd2 | 1950 | |
285a5742 | 1951 | /* Generate calls to memcpy, etc., not bcopy, etc. */ |
b517dcd2 | 1952 | #define TARGET_MEM_FUNCTIONS 1 |