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7eb0c947 | 1 | ;; Scheduling description for Alpha EV4. |
f1717362 | 2 | ;; Copyright (C) 2002-2016 Free Software Foundation, Inc. |
7eb0c947 | 3 | ;; |
187b36cf | 4 | ;; This file is part of GCC. |
7eb0c947 | 5 | ;; |
187b36cf | 6 | ;; GCC is free software; you can redistribute it and/or modify |
7eb0c947 | 7 | ;; it under the terms of the GNU General Public License as published by |
038d1e19 | 8 | ;; the Free Software Foundation; either version 3, or (at your option) |
7eb0c947 | 9 | ;; any later version. |
10 | ;; | |
187b36cf | 11 | ;; GCC is distributed in the hope that it will be useful, |
7eb0c947 | 12 | ;; but WITHOUT ANY WARRANTY; without even the implied warranty of |
13 | ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | ;; GNU General Public License for more details. | |
15 | ;; | |
16 | ;; You should have received a copy of the GNU General Public License | |
038d1e19 | 17 | ;; along with GCC; see the file COPYING3. If not see |
18 | ;; <http://www.gnu.org/licenses/>. | |
7eb0c947 | 19 | |
20 | ; On EV4 there are two classes of resources to consider: resources needed | |
21 | ; to issue, and resources needed to execute. IBUS[01] are in the first | |
22 | ; category. ABOX, BBOX, EBOX, FBOX, IMUL & FDIV make up the second. | |
23 | ; (There are a few other register-like resources, but ...) | |
24 | ||
25 | (define_automaton "ev4_0,ev4_1,ev4_2") | |
26 | (define_cpu_unit "ev4_ib0,ev4_ib1,ev4_abox,ev4_bbox" "ev4_0") | |
27 | (define_cpu_unit "ev4_ebox,ev4_imul" "ev4_1") | |
28 | (define_cpu_unit "ev4_fbox,ev4_fdiv" "ev4_2") | |
29 | (define_reservation "ev4_ib01" "ev4_ib0|ev4_ib1") | |
30 | ||
31 | ; Assume type "multi" single issues. | |
32 | (define_insn_reservation "ev4_multi" 1 | |
fb64edde | 33 | (and (eq_attr "tune" "ev4") |
7eb0c947 | 34 | (eq_attr "type" "multi")) |
35 | "ev4_ib0+ev4_ib1") | |
36 | ||
37 | ; Loads from L0 completes in three cycles. adjust_cost still factors | |
38 | ; in user-specified memory latency, so return 1 here. | |
39 | (define_insn_reservation "ev4_ld" 1 | |
fb64edde | 40 | (and (eq_attr "tune" "ev4") |
f155876e | 41 | (eq_attr "type" "ild,fld,ldsym,ld_l")) |
7eb0c947 | 42 | "ev4_ib01+ev4_abox") |
43 | ||
44 | ; Stores can issue before the data (but not address) is ready. | |
45 | (define_insn_reservation "ev4_ist" 1 | |
fb64edde | 46 | (and (eq_attr "tune" "ev4") |
7eb0c947 | 47 | (eq_attr "type" "ist")) |
48 | "ev4_ib1+ev4_abox") | |
49 | ||
f155876e | 50 | ; ??? Separate from ev4_ist because store_data_bypass_p can't handle |
51 | ; the patterns with multiple sets, like store-conditional. | |
52 | (define_insn_reservation "ev4_ist_c" 1 | |
53 | (and (eq_attr "tune" "ev4") | |
54 | (eq_attr "type" "st_c")) | |
55 | "ev4_ib1+ev4_abox") | |
56 | ||
7eb0c947 | 57 | (define_insn_reservation "ev4_fst" 1 |
fb64edde | 58 | (and (eq_attr "tune" "ev4") |
7eb0c947 | 59 | (eq_attr "type" "fst")) |
60 | "ev4_ib0+ev4_abox") | |
61 | ||
f155876e | 62 | ; Memory barrier blocks ABOX insns until it's acknowledged by the external |
63 | ; memory bus. This may be *quite* slow. Setting this to 4 cycles gets | |
64 | ; about all the benefit without making the DFA too large. | |
65 | (define_insn_reservation "ev4_mb" 4 | |
66 | (and (eq_attr "tune" "ev4") | |
67 | (eq_attr "type" "mb")) | |
68 | "ev4_ib1+ev4_abox,ev4_abox*3") | |
69 | ||
7eb0c947 | 70 | ; Branches have no delay cost, but do tie up the unit for two cycles. |
71 | (define_insn_reservation "ev4_ibr" 2 | |
fb64edde | 72 | (and (eq_attr "tune" "ev4") |
7eb0c947 | 73 | (eq_attr "type" "ibr,jsr")) |
74 | "ev4_ib1+ev4_bbox,ev4_bbox") | |
75 | ||
1050b77e | 76 | (define_insn_reservation "ev4_callpal" 2 |
fb64edde | 77 | (and (eq_attr "tune" "ev4") |
1050b77e | 78 | (eq_attr "type" "callpal")) |
79 | "ev4_ib1+ev4_bbox,ev4_bbox") | |
80 | ||
7eb0c947 | 81 | (define_insn_reservation "ev4_fbr" 2 |
fb64edde | 82 | (and (eq_attr "tune" "ev4") |
7eb0c947 | 83 | (eq_attr "type" "fbr")) |
84 | "ev4_ib0+ev4_bbox,ev4_bbox") | |
85 | ||
86 | ; Arithmetic insns are normally have their results available after | |
87 | ; two cycles. There are a number of exceptions. | |
88 | ||
89 | (define_insn_reservation "ev4_iaddlog" 2 | |
fb64edde | 90 | (and (eq_attr "tune" "ev4") |
7eb0c947 | 91 | (eq_attr "type" "iadd,ilog")) |
92 | "ev4_ib0+ev4_ebox") | |
93 | ||
94 | (define_bypass 1 | |
95 | "ev4_iaddlog" | |
96 | "ev4_ibr,ev4_iaddlog,ev4_shiftcm,ev4_icmp,ev4_imulsi,ev4_imuldi") | |
97 | ||
98 | (define_insn_reservation "ev4_shiftcm" 2 | |
fb64edde | 99 | (and (eq_attr "tune" "ev4") |
7eb0c947 | 100 | (eq_attr "type" "shift,icmov")) |
101 | "ev4_ib0+ev4_ebox") | |
102 | ||
103 | (define_insn_reservation "ev4_icmp" 2 | |
fb64edde | 104 | (and (eq_attr "tune" "ev4") |
7eb0c947 | 105 | (eq_attr "type" "icmp")) |
106 | "ev4_ib0+ev4_ebox") | |
107 | ||
108 | (define_bypass 1 "ev4_icmp" "ev4_ibr") | |
109 | ||
110 | (define_bypass 0 | |
111 | "ev4_iaddlog,ev4_shiftcm,ev4_icmp" | |
112 | "ev4_ist" | |
113 | "store_data_bypass_p") | |
114 | ||
7bd28bba | 115 | ; Multiplies use a non-pipelined imul unit. Also, "no [ebox] insn can |
7eb0c947 | 116 | ; be issued exactly three cycles before an integer multiply completes". |
117 | ||
118 | (define_insn_reservation "ev4_imulsi" 21 | |
fb64edde | 119 | (and (eq_attr "tune" "ev4") |
7eb0c947 | 120 | (and (eq_attr "type" "imul") |
121 | (eq_attr "opsize" "si"))) | |
122 | "ev4_ib0+ev4_imul,ev4_imul*18,ev4_ebox") | |
123 | ||
124 | (define_bypass 20 "ev4_imulsi" "ev4_ist" "store_data_bypass_p") | |
125 | ||
126 | (define_insn_reservation "ev4_imuldi" 23 | |
fb64edde | 127 | (and (eq_attr "tune" "ev4") |
7eb0c947 | 128 | (and (eq_attr "type" "imul") |
129 | (eq_attr "opsize" "!si"))) | |
130 | "ev4_ib0+ev4_imul,ev4_imul*20,ev4_ebox") | |
131 | ||
132 | (define_bypass 22 "ev4_imuldi" "ev4_ist" "store_data_bypass_p") | |
133 | ||
134 | ; Most FP insns have a 6 cycle latency, but with a 4 cycle bypass back in. | |
135 | (define_insn_reservation "ev4_fpop" 6 | |
fb64edde | 136 | (and (eq_attr "tune" "ev4") |
7eb0c947 | 137 | (eq_attr "type" "fadd,fmul,fcpys,fcmov")) |
138 | "ev4_ib1+ev4_fbox") | |
139 | ||
140 | (define_bypass 4 "ev4_fpop" "ev4_fpop") | |
141 | ||
142 | ; The floating point divider is not pipelined. Also, "no FPOP insn can be | |
143 | ; issued exactly five or exactly six cycles before an fdiv insn completes". | |
144 | ||
145 | (define_insn_reservation "ev4_fdivsf" 34 | |
fb64edde | 146 | (and (eq_attr "tune" "ev4") |
7eb0c947 | 147 | (and (eq_attr "type" "fdiv") |
148 | (eq_attr "opsize" "si"))) | |
149 | "ev4_ib1+ev4_fdiv,ev4_fdiv*28,ev4_fdiv+ev4_fbox,ev4_fbox") | |
150 | ||
151 | (define_insn_reservation "ev4_fdivdf" 63 | |
fb64edde | 152 | (and (eq_attr "tune" "ev4") |
7eb0c947 | 153 | (and (eq_attr "type" "fdiv") |
154 | (eq_attr "opsize" "di"))) | |
155 | "ev4_ib1+ev4_fdiv,ev4_fdiv*57,ev4_fdiv+ev4_fbox,ev4_fbox") | |
156 | ||
157 | ; Traps don't consume or produce data. | |
158 | (define_insn_reservation "ev4_misc" 1 | |
fb64edde | 159 | (and (eq_attr "tune" "ev4") |
7eb0c947 | 160 | (eq_attr "type" "misc")) |
161 | "ev4_ib1") |