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526b7aee | 1 | /* Synopsys DesignWare ARC SIMD include file. |
23a5b65a | 2 | Copyright (C) 2007-2014 Free Software Foundation, Inc. |
526b7aee SV |
3 | Written by Saurabh Verma (saurabh.verma@celunite.com) on behalf os Synopsys |
4 | Inc. | |
5 | ||
6 | This file is part of GCC. | |
7 | ||
8 | GCC is free software; you can redistribute it and/or modify it | |
9 | under the terms of the GNU General Public License as published | |
10 | by the Free Software Foundation; either version 3, or (at your | |
11 | option) any later version. | |
12 | ||
13 | GCC is distributed in the hope that it will be useful, but WITHOUT | |
14 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
15 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
16 | License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with GCC; see the file COPYING3. If not see | |
20 | <http://www.gnu.org/licenses/>. */ | |
21 | ||
22 | /* As a special exception, if you include this header file into source | |
23 | files compiled by GCC, this header file does not by itself cause | |
24 | the resulting executable to be covered by the GNU General Public | |
25 | License. This exception does not however invalidate any other | |
26 | reasons why the executable file might be covered by the GNU General | |
27 | Public License. */ | |
28 | ||
29 | #ifndef _ARC_SIMD_H | |
30 | #define _ARC_SIMD_H 1 | |
31 | ||
32 | #ifndef __ARC_SIMD__ | |
33 | #error Use the "-msimd" flag to enable ARC SIMD support | |
34 | #endif | |
35 | ||
36 | /* I0-I7 registers. */ | |
37 | #define _IREG_I0 0 | |
38 | #define _IREG_I1 1 | |
39 | #define _IREG_I2 2 | |
40 | #define _IREG_I3 3 | |
41 | #define _IREG_I4 4 | |
42 | #define _IREG_I5 5 | |
43 | #define _IREG_I6 6 | |
44 | #define _IREG_I7 7 | |
45 | ||
46 | /* DMA configuration registers. */ | |
47 | #define _DMA_REG_DR0 0 | |
48 | #define _DMA_SDM_SRC_ADR_REG _DMA_REG_DR0 | |
49 | #define _DMA_SDM_DEST_ADR_REG _DMA_REG_DR0 | |
50 | ||
51 | #define _DMA_REG_DR1 1 | |
52 | #define _DMA_SDM_STRIDE_REG _DMA_REG_DR1 | |
53 | ||
54 | #define _DMA_REG_DR2 2 | |
55 | #define _DMA_BLK_REG _DMA_REG_DR2 | |
56 | ||
57 | #define _DMA_REG_DR3 3 | |
58 | #define _DMA_LOC_REG _DMA_REG_DR3 | |
59 | ||
60 | #define _DMA_REG_DR4 4 | |
61 | #define _DMA_SYS_SRC_ADR_REG _DMA_REG_DR4 | |
62 | #define _DMA_SYS_DEST_ADR_REG _DMA_REG_DR4 | |
63 | ||
64 | #define _DMA_REG_DR5 5 | |
65 | #define _DMA_SYS_STRIDE_REG _DMA_REG_DR5 | |
66 | ||
67 | #define _DMA_REG_DR6 6 | |
68 | #define _DMA_CFG_REG _DMA_REG_DR6 | |
69 | ||
70 | #define _DMA_REG_DR7 7 | |
71 | #define _DMA_FT_BASE_ADR_REG _DMA_REG_DR7 | |
72 | ||
73 | /* Predefined types used in vector instructions. */ | |
74 | typedef int __v4si __attribute__((vector_size(16))); | |
75 | typedef short __v8hi __attribute__((vector_size(16))); | |
76 | ||
77 | /* Synonyms */ | |
78 | #define _vaddaw __builtin_arc_vaddaw | |
79 | #define _vaddw __builtin_arc_vaddw | |
80 | #define _vavb __builtin_arc_vavb | |
81 | #define _vavrb __builtin_arc_vavrb | |
82 | #define _vdifaw __builtin_arc_vdifaw | |
83 | #define _vdifw __builtin_arc_vdifw | |
84 | #define _vmaxaw __builtin_arc_vmaxaw | |
85 | #define _vmaxw __builtin_arc_vmaxw | |
86 | #define _vminaw __builtin_arc_vminaw | |
87 | #define _vminw __builtin_arc_vminw | |
88 | #define _vmulaw __builtin_arc_vmulaw | |
89 | #define _vmulfaw __builtin_arc_vmulfaw | |
90 | #define _vmulfw __builtin_arc_vmulfw | |
91 | #define _vmulw __builtin_arc_vmulw | |
92 | #define _vsubaw __builtin_arc_vsubaw | |
93 | #define _vsubw __builtin_arc_vsubw | |
94 | #define _vsummw __builtin_arc_vsummw | |
95 | #define _vand __builtin_arc_vand | |
96 | #define _vandaw __builtin_arc_vandaw | |
97 | #define _vbic __builtin_arc_vbic | |
98 | #define _vbicaw __builtin_arc_vbicaw | |
99 | #define _vor __builtin_arc_vor | |
100 | #define _vxor __builtin_arc_vxor | |
101 | #define _vxoraw __builtin_arc_vxoraw | |
102 | #define _veqw __builtin_arc_veqw | |
103 | #define _vlew __builtin_arc_vlew | |
104 | #define _vltw __builtin_arc_vltw | |
105 | #define _vnew __builtin_arc_vnew | |
106 | #define _vmr1aw __builtin_arc_vmr1aw | |
107 | #define _vmr1w __builtin_arc_vmr1w | |
108 | #define _vmr2aw __builtin_arc_vmr2aw | |
109 | #define _vmr2w __builtin_arc_vmr2w | |
110 | #define _vmr3aw __builtin_arc_vmr3aw | |
111 | #define _vmr3w __builtin_arc_vmr3w | |
112 | #define _vmr4aw __builtin_arc_vmr4aw | |
113 | #define _vmr4w __builtin_arc_vmr4w | |
114 | #define _vmr5aw __builtin_arc_vmr5aw | |
115 | #define _vmr5w __builtin_arc_vmr5w | |
116 | #define _vmr6aw __builtin_arc_vmr6aw | |
117 | #define _vmr6w __builtin_arc_vmr6w | |
118 | #define _vmr7aw __builtin_arc_vmr7aw | |
119 | #define _vmr7w __builtin_arc_vmr7w | |
120 | #define _vmrb __builtin_arc_vmrb | |
121 | #define _vh264f __builtin_arc_vh264f | |
122 | #define _vh264ft __builtin_arc_vh264ft | |
123 | #define _vh264fw __builtin_arc_vh264fw | |
124 | #define _vvc1f __builtin_arc_vvc1f | |
125 | #define _vvc1ft __builtin_arc_vvc1ft | |
126 | #define _vbaddw __builtin_arc_vbaddw | |
127 | #define _vbmaxw __builtin_arc_vbmaxw | |
128 | #define _vbminw __builtin_arc_vbminw | |
129 | #define _vbmulaw __builtin_arc_vbmulaw | |
130 | #define _vbmulfw __builtin_arc_vbmulfw | |
131 | #define _vbmulw __builtin_arc_vbmulw | |
132 | #define _vbrsubw __builtin_arc_vbrsubw | |
133 | #define _vbsubw __builtin_arc_vbsubw | |
134 | #define _vasrw __builtin_arc_vasrw | |
135 | #define _vsr8 __builtin_arc_vsr8 | |
136 | #define _vsr8aw __builtin_arc_vsr8aw | |
137 | #define _vasrrwi __builtin_arc_vasrrwi | |
138 | #define _vasrsrwi __builtin_arc_vasrsrwi | |
139 | #define _vasrwi __builtin_arc_vasrwi | |
140 | #define _vasrpwbi __builtin_arc_vasrpwbi | |
141 | #define _vasrrpwbi __builtin_arc_vasrrpwbi | |
142 | #define _vsr8awi __builtin_arc_vsr8awi | |
143 | #define _vsr8i __builtin_arc_vsr8i | |
144 | #define _vmvaw __builtin_arc_vmvaw | |
145 | #define _vmvw __builtin_arc_vmvw | |
146 | #define _vmvzw __builtin_arc_vmvzw | |
147 | #define _vd6tapf __builtin_arc_vd6tapf | |
148 | #define _vmovaw __builtin_arc_vmovaw | |
149 | #define _vmovw __builtin_arc_vmovw | |
150 | #define _vmovzw __builtin_arc_vmovzw | |
151 | #define _vabsaw __builtin_arc_vabsaw | |
152 | #define _vabsw __builtin_arc_vabsw | |
153 | #define _vaddsuw __builtin_arc_vaddsuw | |
154 | #define _vsignw __builtin_arc_vsignw | |
155 | #define _vexch1 __builtin_arc_vexch1 | |
156 | #define _vexch2 __builtin_arc_vexch2 | |
157 | #define _vexch4 __builtin_arc_vexch4 | |
158 | #define _vupbaw __builtin_arc_vupbaw | |
159 | #define _vupbw __builtin_arc_vupbw | |
160 | #define _vupsbaw __builtin_arc_vupsbaw | |
161 | #define _vupsbw __builtin_arc_vupsbw | |
162 | #define _vdirun __builtin_arc_vdirun | |
163 | #define _vdorun __builtin_arc_vdorun | |
164 | #define _vdiwr __builtin_arc_vdiwr | |
165 | #define _vdowr __builtin_arc_vdowr | |
166 | #define _vrec __builtin_arc_vrec | |
167 | #define _vrun __builtin_arc_vrun | |
168 | #define _vrecrun __builtin_arc_vrecrun | |
169 | #define _vendrec __builtin_arc_vendrec | |
170 | #define _vld32wh __builtin_arc_vld32wh | |
171 | #define _vld32wl __builtin_arc_vld32wl | |
172 | #define _vld64 __builtin_arc_vld64 | |
173 | #define _vld32 __builtin_arc_vld32 | |
174 | #define _vld64w __builtin_arc_vld64w | |
175 | #define _vld128 __builtin_arc_vld128 | |
176 | #define _vst128 __builtin_arc_vst128 | |
177 | #define _vst64 __builtin_arc_vst64 | |
178 | #define _vst16_n __builtin_arc_vst16_n | |
179 | #define _vst32_n __builtin_arc_vst32_n | |
180 | #define _vinti __builtin_arc_vinti | |
181 | ||
182 | /* Additional synonyms to ease programming. */ | |
183 | #define _setup_dma_in_channel_reg _vdiwr | |
184 | #define _setup_dma_out_channel_reg _vdowr | |
185 | ||
186 | #endif /* _ARC_SIMD_H */ |