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526b7aee | 1 | /* Definitions of target machine for GNU compiler, Synopsys DesignWare ARC cpu. |
7adcbafe | 2 | Copyright (C) 1994-2022 Free Software Foundation, Inc. |
526b7aee | 3 | |
526b7aee SV |
4 | This file is part of GCC. |
5 | ||
6 | GCC is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 3, or (at your option) | |
9 | any later version. | |
10 | ||
11 | GCC is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GCC; see the file COPYING3. If not see | |
18 | <http://www.gnu.org/licenses/>. */ | |
19 | ||
20 | #ifndef GCC_ARC_H | |
21 | #define GCC_ARC_H | |
22 | ||
f9ccf899 CZ |
23 | #include <stdbool.h> |
24 | ||
526b7aee SV |
25 | /* Things to do: |
26 | ||
27 | - incscc, decscc? | |
28 | ||
29 | */ | |
30 | ||
31 | #define SYMBOL_FLAG_SHORT_CALL (SYMBOL_FLAG_MACH_DEP << 0) | |
32 | #define SYMBOL_FLAG_MEDIUM_CALL (SYMBOL_FLAG_MACH_DEP << 1) | |
33 | #define SYMBOL_FLAG_LONG_CALL (SYMBOL_FLAG_MACH_DEP << 2) | |
4d03dc2f | 34 | #define SYMBOL_FLAG_CMEM (SYMBOL_FLAG_MACH_DEP << 3) |
526b7aee | 35 | |
f9ccf899 | 36 | #ifndef TARGET_CPU_DEFAULT |
46d04271 | 37 | #define TARGET_CPU_DEFAULT PROCESSOR_hs38_linux |
f9ccf899 CZ |
38 | #endif |
39 | ||
526b7aee SV |
40 | /* Check if this symbol has a long_call attribute in its declaration */ |
41 | #define SYMBOL_REF_LONG_CALL_P(X) \ | |
42 | ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_LONG_CALL) != 0) | |
43 | ||
44 | /* Check if this symbol has a medium_call attribute in its declaration */ | |
45 | #define SYMBOL_REF_MEDIUM_CALL_P(X) \ | |
46 | ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_MEDIUM_CALL) != 0) | |
47 | ||
48 | /* Check if this symbol has a short_call attribute in its declaration */ | |
49 | #define SYMBOL_REF_SHORT_CALL_P(X) \ | |
50 | ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_SHORT_CALL) != 0) | |
51 | ||
526b7aee | 52 | /* Names to predefine in the preprocessor for this target machine. */ |
cf07c3de | 53 | #define TARGET_CPU_CPP_BUILTINS() arc_cpu_cpp_builtins (pfile) |
526b7aee | 54 | |
f9ccf899 CZ |
55 | /* Macros enabled by specific command line option. FIXME: to be |
56 | deprecatd. */ | |
526b7aee SV |
57 | #define CPP_SPEC "\ |
58 | %{msimd:-D__Xsimd} %{mno-mpy:-D__Xno_mpy} %{mswap:-D__Xswap} \ | |
59 | %{mmin-max:-D__Xmin_max} %{mEA:-D__Xea} \ | |
60 | %{mspfp*:-D__Xspfp} %{mdpfp*:-D__Xdpfp} \ | |
61 | %{mmac-d16:-D__Xxmac_d16} %{mmac-24:-D__Xxmac_24} \ | |
62 | %{mdsp-packa:-D__Xdsp_packa} %{mcrc:-D__Xcrc} %{mdvbf:-D__Xdvbf} \ | |
63 | %{mtelephony:-D__Xtelephony} %{mxy:-D__Xxy} %{mmul64: -D__Xmult32} \ | |
0dee55fe CZ |
64 | %{mlock:-D__Xlock} %{mswape:-D__Xswape} %{mrtsc:-D__Xrtsc} \ |
65 | %(subtarget_cpp_spec)" | |
526b7aee | 66 | |
fad92291 | 67 | #undef CC1_SPEC |
9f532472 CZ |
68 | #define CC1_SPEC "%{EB:%{EL:%emay not use both -EB and -EL}} \ |
69 | %{EB:-mbig-endian} %{EL:-mlittle-endian} \ | |
70 | %{G*} \ | |
526b7aee | 71 | " |
f9ccf899 CZ |
72 | extern const char *arc_cpu_to_as (int argc, const char **argv); |
73 | ||
74 | #define EXTRA_SPEC_FUNCTIONS \ | |
75 | { "cpu_to_as", arc_cpu_to_as }, | |
76 | ||
0dee55fe CZ |
77 | /* This macro defines names of additional specifications to put in the specs |
78 | that can be used in various specifications like CC1_SPEC. Its definition | |
79 | is an initializer with a subgrouping for each command option. | |
80 | ||
81 | Each subgrouping contains a string constant, that defines the | |
82 | specification name, and a string constant that used by the GCC driver | |
83 | program. | |
84 | ||
85 | Do not define this macro if it does not need to do anything. */ | |
86 | #define EXTRA_SPECS \ | |
87 | { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \ | |
88 | SUBTARGET_EXTRA_SPECS | |
89 | ||
90 | #ifndef SUBTARGET_EXTRA_SPECS | |
91 | #define SUBTARGET_EXTRA_SPECS | |
92 | #endif | |
93 | ||
94 | #ifndef SUBTARGET_CPP_SPEC | |
95 | #define SUBTARGET_CPP_SPEC "" | |
96 | #endif | |
97 | ||
fad92291 | 98 | #undef ASM_SPEC |
f9ccf899 | 99 | #define ASM_SPEC "%{mbig-endian|EB:-EB} %{EL} " \ |
d94b1602 SV |
100 | "%:cpu_to_as(%{mcpu=*:%*}) %{mspfp*} %{mdpfp*} " \ |
101 | "%{mfpu=fpuda*:-mfpuda} %{mcode-density}" | |
526b7aee | 102 | |
c4c47a84 CZ |
103 | /* Support for a compile-time default CPU and FPU. The rules are: |
104 | --with-cpu is ignored if -mcpu, mARC*, marc*, mA7, mA6 are specified. | |
105 | --with-fpu is ignored if -mfpu is specified. */ | |
f9ccf899 | 106 | #define OPTION_DEFAULT_SPECS \ |
c4c47a84 | 107 | {"fpu", "%{!mfpu=*:-mfpu=%(VALUE)}"}, \ |
f9ccf899 | 108 | {"cpu", "%{!mcpu=*:%{!mARC*:%{!marc*:%{!mA7:%{!mA6:-mcpu=%(VALUE)}}}}}" } |
526b7aee | 109 | |
526b7aee SV |
110 | #ifndef DRIVER_ENDIAN_SELF_SPECS |
111 | #define DRIVER_ENDIAN_SELF_SPECS "" | |
112 | #endif | |
526b7aee | 113 | |
f9ccf899 CZ |
114 | #define DRIVER_SELF_SPECS DRIVER_ENDIAN_SELF_SPECS \ |
115 | "%{mARC600|mA6: -mcpu=arc600 %<mARC600 %<mA6 %<mARC600}" \ | |
116 | "%{mARC601: -mcpu=arc601 %<mARC601}" \ | |
117 | "%{mARC700|mA7: -mcpu=arc700 %<mARC700 %<mA7}" \ | |
118 | "%{mEA: -mea %<mEA}" | |
526b7aee SV |
119 | |
120 | /* Run-time compilation parameters selecting different hardware subsets. */ | |
121 | ||
526b7aee | 122 | #define TARGET_SPFP (TARGET_SPFP_FAST_SET || TARGET_SPFP_COMPACT_SET) |
8f3304d0 CZ |
123 | #define TARGET_DPFP (TARGET_DPFP_FAST_SET || TARGET_DPFP_COMPACT_SET \ |
124 | || TARGET_FP_DP_AX) | |
526b7aee SV |
125 | |
126 | #define SUBTARGET_SWITCHES | |
127 | ||
128 | /* Instruction set characteristics. | |
129 | These are internal macros, set by the appropriate -m option. */ | |
130 | ||
131 | /* Non-zero means the cpu supports norm instruction. This flag is set by | |
132 | default for A7, and only for pre A7 cores when -mnorm is given. */ | |
f50bb868 | 133 | #define TARGET_NORM (TARGET_ARC700 || TARGET_NORM_SET || TARGET_HS) |
526b7aee | 134 | /* Indicate if an optimized floating point emulation library is available. */ |
c4014855 | 135 | #define TARGET_OPTFPE (TARGET_ARC700 || TARGET_FPX_QUARK) |
526b7aee SV |
136 | |
137 | /* Non-zero means the cpu supports swap instruction. This flag is set by | |
138 | default for A7, and only for pre A7 cores when -mswap is given. */ | |
139 | #define TARGET_SWAP (TARGET_ARC700 || TARGET_SWAP_SET) | |
140 | ||
141 | /* Provide some macros for size / scheduling features of the ARC700, so | |
142 | that we can pick & choose features if we get a new cpu family member. */ | |
143 | ||
144 | /* Should we try to unalign likely taken branches without a delay slot. */ | |
145 | #define TARGET_UNALIGN_BRANCH (TARGET_ARC700 && !optimize_size) | |
146 | ||
526b7aee SV |
147 | /* Should we add padding before a return insn to avoid mispredict? */ |
148 | #define TARGET_PAD_RETURN (TARGET_ARC700 && !optimize_size) | |
149 | ||
150 | /* For an anulled-true delay slot insn for a delayed branch, should we only | |
151 | use conditional execution? */ | |
f50bb868 | 152 | #define TARGET_AT_DBR_CONDEXEC (!TARGET_ARC700 && !TARGET_V2) |
526b7aee | 153 | |
c3bde35a AB |
154 | #define TARGET_ARC600 ((arc_selected_cpu->arch_info->arch_id \ |
155 | == BASE_ARCH_6xx) \ | |
f9ccf899 | 156 | && (TARGET_BARREL_SHIFTER)) |
c3bde35a AB |
157 | #define TARGET_ARC601 ((arc_selected_cpu->arch_info->arch_id \ |
158 | == BASE_ARCH_6xx) \ | |
f9ccf899 | 159 | && (!TARGET_BARREL_SHIFTER)) |
c3bde35a AB |
160 | #define TARGET_ARC700 (arc_selected_cpu->arch_info->arch_id \ |
161 | == BASE_ARCH_700) | |
3a9abd23 AB |
162 | /* An NPS400 is a specialisation of ARC700, so it is correct for NPS400 |
163 | TARGET_ARC700 is true, and TARGET_NPS400 is true. */ | |
164 | #define TARGET_NPS400 ((arc_selected_cpu->arch_info->arch_id \ | |
165 | == BASE_ARCH_700) \ | |
166 | && (arc_selected_cpu->processor \ | |
167 | == PROCESSOR_nps400)) | |
c3bde35a AB |
168 | #define TARGET_EM (arc_selected_cpu->arch_info->arch_id == BASE_ARCH_em) |
169 | #define TARGET_HS (arc_selected_cpu->arch_info->arch_id == BASE_ARCH_hs) | |
f9ccf899 CZ |
170 | #define TARGET_V2 (TARGET_EM || TARGET_HS) |
171 | ||
4d03dc2f JR |
172 | #ifndef UNALIGNED_ACCESS_DEFAULT |
173 | #define UNALIGNED_ACCESS_DEFAULT 0 | |
174 | #endif | |
175 | ||
ceaaa9fe JR |
176 | #ifndef TARGET_NPS_BITOPS_DEFAULT |
177 | #define TARGET_NPS_BITOPS_DEFAULT 0 | |
178 | #endif | |
179 | ||
4d03dc2f JR |
180 | #ifndef TARGET_NPS_CMEM_DEFAULT |
181 | #define TARGET_NPS_CMEM_DEFAULT 0 | |
182 | #endif | |
183 | ||
ceaaa9fe JR |
184 | /* Enable the RRQ instruction alternatives. */ |
185 | ||
186 | #define TARGET_RRQ_CLASS TARGET_NPS_BITOPS | |
187 | ||
526b7aee SV |
188 | /* Target machine storage layout. */ |
189 | ||
190 | /* We want zero_extract to mean the same | |
191 | no matter what the byte endianness is. */ | |
192 | #define BITS_BIG_ENDIAN 0 | |
193 | ||
194 | /* Define this if most significant byte of a word is the lowest numbered. */ | |
195 | #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN) | |
196 | ||
197 | /* Define this if most significant word of a multiword number is the lowest | |
198 | numbered. */ | |
199 | #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN) | |
200 | ||
526b7aee SV |
201 | /* Width in bits of a "word", which is the contents of a machine register. |
202 | Note that this is not necessarily the width of data type `int'; | |
203 | if using 16-bit ints on a 68000, this would still be 32. | |
204 | But on a machine with 16-bit registers, this would be 16. */ | |
205 | #define BITS_PER_WORD 32 | |
206 | ||
207 | /* Width of a word, in units (bytes). */ | |
208 | #define UNITS_PER_WORD 4 | |
209 | ||
210 | /* Define this macro if it is advisable to hold scalars in registers | |
211 | in a wider mode than that declared by the program. In such cases, | |
212 | the value is constrained to be within the bounds of the declared | |
213 | type, but kept valid in the wider mode. The signedness of the | |
214 | extension may differ from that of the type. */ | |
215 | #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \ | |
216 | if (GET_MODE_CLASS (MODE) == MODE_INT \ | |
217 | && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \ | |
218 | { \ | |
219 | (MODE) = SImode; \ | |
220 | } | |
221 | ||
222 | /* Width in bits of a pointer. | |
223 | See also the macro `Pmode' defined below. */ | |
224 | #define POINTER_SIZE 32 | |
225 | ||
226 | /* Allocation boundary (in *bits*) for storing arguments in argument list. */ | |
227 | #define PARM_BOUNDARY 32 | |
228 | ||
229 | /* Boundary (in *bits*) on which stack pointer should be aligned. */ | |
230 | /* TOCHECK: Changed from 64 to 32 */ | |
231 | #define STACK_BOUNDARY 32 | |
232 | ||
233 | /* ALIGN FRAMES on word boundaries. */ | |
234 | #define ARC_STACK_ALIGN(LOC) \ | |
235 | (((LOC) + STACK_BOUNDARY / BITS_PER_UNIT - 1) & -STACK_BOUNDARY/BITS_PER_UNIT) | |
236 | ||
237 | /* Allocation boundary (in *bits*) for the code of a function. */ | |
238 | #define FUNCTION_BOUNDARY 32 | |
239 | ||
240 | /* Alignment of field after `int : 0' in a structure. */ | |
241 | #define EMPTY_FIELD_BOUNDARY 32 | |
242 | ||
243 | /* Every structure's size must be a multiple of this. */ | |
244 | #define STRUCTURE_SIZE_BOUNDARY 8 | |
245 | ||
246 | /* A bitfield declared as `int' forces `int' alignment for the struct. */ | |
247 | #define PCC_BITFIELD_TYPE_MATTERS 1 | |
248 | ||
249 | /* An expression for the alignment of a structure field FIELD if the | |
250 | alignment computed in the usual way (including applying of | |
251 | `BIGGEST_ALIGNMENT' and `BIGGEST_FIELD_ALIGNMENT' to the | |
252 | alignment) is COMPUTED. It overrides alignment only if the field | |
253 | alignment has not been set by the `__attribute__ ((aligned (N)))' | |
254 | construct. | |
255 | */ | |
256 | ||
a4cf4b64 RB |
257 | #define ADJUST_FIELD_ALIGN(FIELD, TYPE, COMPUTED) \ |
258 | (TYPE_MODE (strip_array_types (TYPE)) == DFmode \ | |
526b7aee SV |
259 | ? MIN ((COMPUTED), 32) : (COMPUTED)) |
260 | ||
261 | ||
262 | ||
263 | /* No data type wants to be aligned rounder than this. */ | |
264 | /* This is bigger than currently necessary for the ARC. If 8 byte floats are | |
265 | ever added it's not clear whether they'll need such alignment or not. For | |
266 | now we assume they will. We can always relax it if necessary but the | |
267 | reverse isn't true. */ | |
268 | /* TOCHECK: Changed from 64 to 32 */ | |
269 | #define BIGGEST_ALIGNMENT 32 | |
270 | ||
271 | /* The best alignment to use in cases where we have a choice. */ | |
272 | #define FASTEST_ALIGNMENT 32 | |
273 | ||
526b7aee SV |
274 | /* Make arrays of chars word-aligned for the same reasons. */ |
275 | #define LOCAL_ALIGNMENT(TYPE, ALIGN) \ | |
276 | (TREE_CODE (TYPE) == ARRAY_TYPE \ | |
277 | && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ | |
278 | && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN)) | |
279 | ||
280 | #define DATA_ALIGNMENT(TYPE, ALIGN) \ | |
281 | (TREE_CODE (TYPE) == ARRAY_TYPE \ | |
282 | && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ | |
283 | && arc_size_opt_level < 3 \ | |
284 | && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN)) | |
285 | ||
286 | /* Set this nonzero if move instructions will actually fail to work | |
287 | when given unaligned data. */ | |
288 | /* On the ARC the lower address bits are masked to 0 as necessary. The chip | |
289 | won't croak when given an unaligned address, but the insn will still fail | |
290 | to produce the correct result. */ | |
9f54ba8f | 291 | #define STRICT_ALIGNMENT (!unaligned_access) |
526b7aee SV |
292 | |
293 | /* Layout of source language data types. */ | |
294 | ||
295 | #define SHORT_TYPE_SIZE 16 | |
296 | #define INT_TYPE_SIZE 32 | |
297 | #define LONG_TYPE_SIZE 32 | |
298 | #define LONG_LONG_TYPE_SIZE 64 | |
299 | #define FLOAT_TYPE_SIZE 32 | |
300 | #define DOUBLE_TYPE_SIZE 64 | |
301 | #define LONG_DOUBLE_TYPE_SIZE 64 | |
302 | ||
303 | /* Define this as 1 if `char' should by default be signed; else as 0. */ | |
304 | #define DEFAULT_SIGNED_CHAR 0 | |
305 | ||
fad92291 | 306 | #undef SIZE_TYPE |
db64c64e | 307 | #define SIZE_TYPE "unsigned int" |
fad92291 CZ |
308 | |
309 | #undef PTRDIFF_TYPE | |
db64c64e | 310 | #define PTRDIFF_TYPE "int" |
fad92291 CZ |
311 | |
312 | #undef WCHAR_TYPE | |
526b7aee | 313 | #define WCHAR_TYPE "int" |
526b7aee | 314 | |
fad92291 CZ |
315 | #undef WCHAR_TYPE_SIZE |
316 | #define WCHAR_TYPE_SIZE 32 | |
526b7aee | 317 | |
526b7aee SV |
318 | /* Standard register usage. */ |
319 | ||
320 | /* Number of actual hardware registers. | |
321 | The hardware registers are assigned numbers for the compiler | |
322 | from 0 to just below FIRST_PSEUDO_REGISTER. | |
323 | All registers that the compiler knows about must be given numbers, | |
324 | even those that are not normally considered general registers. | |
325 | ||
326 | Registers 61, 62, and 63 are not really registers and we needn't treat | |
327 | them as such. We still need a register for the condition code and | |
328 | argument pointer. */ | |
329 | ||
330 | /* r63 is pc, r64-r127 = simd vregs, r128-r143 = simd dma config regs | |
47d8cb23 | 331 | r144, r145 = ARG_POINTER, FRAME_POINTER |
526b7aee SV |
332 | and therefore the pseudo registers start from r146. */ |
333 | #define FIRST_PSEUDO_REGISTER 146 | |
334 | ||
335 | /* 1 for registers that have pervasive standard uses | |
336 | and are not available for the register allocator. | |
337 | ||
338 | 0-28 - general purpose registers | |
339 | 29 - ilink1 (interrupt link register) | |
340 | 30 - ilink2 (interrupt link register) | |
341 | 31 - blink (branch link register) | |
342 | 32-59 - reserved for extensions | |
343 | 60 - LP_COUNT | |
344 | 61 - condition code | |
345 | 62 - argument pointer | |
346 | 63 - program counter | |
347 | ||
348 | FWIW, this is how the 61-63 encodings are used by the hardware: | |
349 | 61 - reserved | |
350 | 62 - long immediate data indicator | |
351 | 63 - PCL (program counter aligned to 32 bit, read-only) | |
352 | ||
353 | The general purpose registers are further broken down into: | |
354 | ||
355 | 0-7 - arguments/results | |
356 | 8-12 - call used (r11 - static chain pointer) | |
357 | 13-25 - call saved | |
358 | 26 - global pointer | |
359 | 27 - frame pointer | |
360 | 28 - stack pointer | |
361 | 29 - ilink1 | |
362 | 30 - ilink2 | |
363 | 31 - return address register | |
364 | ||
365 | By default, the extension registers are not available. */ | |
366 | /* Present implementations only have VR0-VR23 only. */ | |
526b7aee SV |
367 | #define FIXED_REGISTERS \ |
368 | { 0, 0, 0, 0, 0, 0, 0, 0, \ | |
369 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
370 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
47d8cb23 | 371 | 0, 0, 1, 0, 1, 1, 1, 1, \ |
526b7aee SV |
372 | \ |
373 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
374 | 0, 0, 0, 0, 1, 1, 1, 1, \ | |
375 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
73dac59b | 376 | 1, 1, 1, 1, 1, 1, 1, 1, \ |
526b7aee SV |
377 | \ |
378 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
379 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
380 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
381 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
382 | \ | |
383 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
384 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
385 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
386 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
387 | \ | |
388 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
389 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
390 | 1, 1} | |
391 | ||
392 | /* 1 for registers not available across function calls. | |
393 | These must include the FIXED_REGISTERS and also any | |
394 | registers that can be used without being saved. | |
395 | The latter must include the registers where values are returned | |
396 | and the register where structure-value addresses are passed. | |
397 | Aside from that, you can include as many other registers as you like. */ | |
398 | #define CALL_USED_REGISTERS \ | |
399 | { \ | |
400 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
401 | 1, 1, 1, 1, 1, 0, 0, 0, \ | |
402 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
47d8cb23 | 403 | 0, 0, 1, 0, 1, 1, 1, 1, \ |
526b7aee SV |
404 | \ |
405 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
406 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
407 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
408 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
409 | \ | |
410 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
411 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
412 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
413 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
414 | \ | |
415 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
416 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
417 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
418 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
419 | \ | |
420 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
421 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
422 | 1, 1} | |
423 | ||
424 | /* If defined, an initializer for a vector of integers, containing the | |
425 | numbers of hard registers in the order in which GCC should | |
426 | prefer to use them (from most preferred to least). */ | |
864e2eaa CZ |
427 | #define REG_ALLOC_ORDER \ |
428 | { \ | |
429 | /* General registers. */ \ | |
430 | 2, 3, 12, 13, 14, 15, 1, 0, 4, 5, 6, 7, 8, 9, 10, 11, \ | |
431 | 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 30, \ | |
432 | /* Extension core registers. */ \ | |
526b7aee | 433 | 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \ |
864e2eaa CZ |
434 | 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, \ |
435 | /* VR regs. */ \ | |
436 | 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \ | |
437 | 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \ | |
438 | 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, \ | |
439 | 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, \ | |
440 | 124, 125, 126, 127, \ | |
441 | /* DMA registers. */ \ | |
442 | 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, \ | |
443 | 142, 143, \ | |
444 | /* Register not used for general use. */ \ | |
445 | 62, FRAME_POINTER_REGNUM, ARG_POINTER_REGNUM, \ | |
446 | SP_REG, ILINK1_REG, RETURN_ADDR_REGNUM, LP_COUNT, CC_REG, PCL_REG \ | |
447 | } | |
448 | ||
449 | /* Use different register alloc ordering for Thumb. */ | |
450 | #define ADJUST_REG_ALLOC_ORDER arc_adjust_reg_alloc_order () | |
451 | ||
452 | /* Tell IRA to use the order we define rather than messing it up with its | |
453 | own cost calculations. */ | |
454 | #define HONOR_REG_ALLOC_ORDER 1 | |
526b7aee | 455 | |
526b7aee SV |
456 | /* Internal macros to classify a register number as to whether it's a |
457 | general purpose register for compact insns (r0-r3,r12-r15), or | |
458 | stack pointer (r28). */ | |
459 | ||
460 | #define COMPACT_GP_REG_P(REGNO) \ | |
461 | (((signed)(REGNO) >= 0 && (REGNO) <= 3) || ((REGNO) >= 12 && (REGNO) <= 15)) | |
462 | #define SP_REG_P(REGNO) ((REGNO) == 28) | |
463 | ||
464 | ||
465 | ||
466 | /* Register classes and constants. */ | |
467 | ||
468 | /* Define the classes of registers for register constraints in the | |
469 | machine description. Also define ranges of constants. | |
470 | ||
471 | One of the classes must always be named ALL_REGS and include all hard regs. | |
472 | If there is more than one class, another class must be named NO_REGS | |
473 | and contain no registers. | |
474 | ||
475 | The name GENERAL_REGS must be the name of a class (or an alias for | |
476 | another name such as ALL_REGS). This is the class of registers | |
477 | that is allowed by "g" or "r" in a register constraint. | |
478 | Also, registers outside this class are allocated only when | |
479 | instructions express preferences for them. | |
480 | ||
481 | The classes must be numbered in nondecreasing order; that is, | |
482 | a larger-numbered class must never be contained completely | |
483 | in a smaller-numbered class. | |
484 | ||
485 | For any two classes, it is very desirable that there be another | |
486 | class that represents their union. | |
487 | ||
488 | It is important that any condition codes have class NO_REGS. | |
489 | See `register_operand'. */ | |
490 | ||
491 | enum reg_class | |
492 | { | |
493 | NO_REGS, | |
494 | R0_REGS, /* 'x' */ | |
73dac59b CZ |
495 | R0R1_CD_REGS, /* 'Rsd' */ |
496 | R0R3_CD_REGS, /* 'Rcd' */ | |
526b7aee | 497 | ARCOMPACT16_REGS, /* 'q' */ |
526b7aee | 498 | SIBCALL_REGS, /* "Rsc" */ |
fc1c2d04 | 499 | AC16_H_REGS, /* 'h' */ |
73dac59b CZ |
500 | DOUBLE_REGS, /* 'D' */ |
501 | GENERAL_REGS, /* 'r' */ | |
502 | SIMD_VR_REGS, /* 'v' */ | |
503 | SIMD_DMA_CONFIG_REGS, /* 'd' */ | |
526b7aee SV |
504 | ALL_REGS, |
505 | LIM_REG_CLASSES | |
506 | }; | |
507 | ||
508 | #define N_REG_CLASSES (int) LIM_REG_CLASSES | |
509 | ||
510 | /* Give names of register classes as strings for dump file. */ | |
511 | #define REG_CLASS_NAMES \ | |
73dac59b CZ |
512 | { \ |
513 | "NO_REGS", \ | |
514 | "R0_REGS", \ | |
515 | "R0R1_CD_REGS", \ | |
516 | "R0R3_CD_REGS", \ | |
517 | "ARCOMPACT16_REGS", \ | |
d77aa5cd | 518 | "SIBCALL_REGS", \ |
73dac59b CZ |
519 | "AC16_H_REGS", \ |
520 | "DOUBLE_REGS", \ | |
521 | "GENERAL_REGS", \ | |
522 | "SIMD_VR_REGS", \ | |
526b7aee | 523 | "SIMD_DMA_CONFIG_REGS", \ |
73dac59b | 524 | "ALL_REGS" \ |
526b7aee SV |
525 | } |
526 | ||
527 | /* Define which registers fit in which classes. | |
528 | This is an initializer for a vector of HARD_REG_SET | |
529 | of length N_REG_CLASSES. */ | |
530 | ||
531 | #define REG_CLASS_CONTENTS \ | |
73dac59b CZ |
532 | { \ |
533 | {0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, /* NO_REGS. */\ | |
534 | {0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, /* 'x'. */ \ | |
535 | {0x00000003, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, /* 'Rsd'. */ \ | |
536 | {0x0000000f, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, /* 'Rcd'. */ \ | |
537 | {0x0000f00f, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, /* 'q'. */ \ | |
47d8cb23 | 538 | {0x00001fff, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, /* 'Rsc'. */ \ |
73dac59b CZ |
539 | {0x9fffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, /* 'h'. */ \ |
540 | {0x00000000, 0x00000f00, 0x00000000, 0x00000000, 0x00000000}, /* 'D'. */ \ | |
47d8cb23 | 541 | {0xffffffff, 0x8fffffff, 0x00000000, 0x00000000, 0x00030000}, /* 'r'. */ \ |
73dac59b CZ |
542 | {0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x00000000}, /* 'v'. */ \ |
543 | {0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0000ffff}, /* 'd'. */ \ | |
544 | {0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x0003ffff} /* ALL_REGS. */\ | |
526b7aee SV |
545 | } |
546 | ||
547 | /* Local macros to mark the first and last regs of different classes. */ | |
548 | #define ARC_FIRST_SIMD_VR_REG 64 | |
549 | #define ARC_LAST_SIMD_VR_REG 127 | |
550 | ||
551 | #define ARC_FIRST_SIMD_DMA_CONFIG_REG 128 | |
552 | #define ARC_FIRST_SIMD_DMA_CONFIG_IN_REG 128 | |
553 | #define ARC_FIRST_SIMD_DMA_CONFIG_OUT_REG 136 | |
554 | #define ARC_LAST_SIMD_DMA_CONFIG_REG 143 | |
555 | ||
8f3304d0 CZ |
556 | /* ARCv2 double-register accumulator. */ |
557 | #define ACC_REG_FIRST 58 | |
558 | #define ACC_REG_LAST 59 | |
559 | #define ACCL_REGNO (TARGET_BIG_ENDIAN ? ACC_REG_FIRST + 1 : ACC_REG_FIRST) | |
560 | #define ACCH_REGNO (TARGET_BIG_ENDIAN ? ACC_REG_FIRST : ACC_REG_FIRST + 1) | |
561 | ||
526b7aee SV |
562 | /* The same information, inverted: |
563 | Return the class number of the smallest class containing | |
564 | reg number REGNO. This could be a conditional expression | |
565 | or could index an array. */ | |
566 | ||
567 | extern enum reg_class arc_regno_reg_class[]; | |
568 | ||
569 | #define REGNO_REG_CLASS(REGNO) (arc_regno_reg_class[REGNO]) | |
570 | ||
571 | /* The class value for valid index registers. An index register is | |
572 | one used in an address where its value is either multiplied by | |
573 | a scale factor or added to another register (as well as added to a | |
574 | displacement). */ | |
575 | ||
592ed7db | 576 | #define INDEX_REG_CLASS GENERAL_REGS |
526b7aee SV |
577 | |
578 | /* The class value for valid base registers. A base register is one used in | |
579 | an address which is the register value plus a displacement. */ | |
580 | ||
73dac59b | 581 | #define BASE_REG_CLASS GENERAL_REGS |
526b7aee SV |
582 | |
583 | /* These assume that REGNO is a hard or pseudo reg number. | |
584 | They give nonzero only if REGNO is a hard reg of the suitable class | |
585 | or a pseudo reg currently allocated to a suitable hard reg. | |
586 | Since they use reg_renumber, they are safe only once reg_renumber | |
587 | has been allocated, which happens in local-alloc.c. */ | |
28633bbd | 588 | #define REGNO_OK_FOR_BASE_P(REGNO) \ |
47d8cb23 CZ |
589 | ((REGNO) < 29 \ |
590 | || ((REGNO) == ARG_POINTER_REGNUM) \ | |
591 | || ((REGNO) == FRAME_POINTER_REGNUM) \ | |
592 | || ((REGNO) == PCL_REG) \ | |
5ccd07e3 | 593 | || (reg_renumber && ((unsigned) reg_renumber[REGNO] < 29)) \ |
4f9c5d5c | 594 | || ((unsigned) (REGNO) == (unsigned) arc_tp_regno) \ |
23c98523 | 595 | || (fixed_regs[REGNO] == 0 && IN_RANGE (REGNO, 32, 59)) \ |
47d8cb23 | 596 | || (fixed_regs[REGNO] == 0 && (REGNO) == R30_REG)) |
526b7aee SV |
597 | |
598 | #define REGNO_OK_FOR_INDEX_P(REGNO) REGNO_OK_FOR_BASE_P(REGNO) | |
599 | ||
600 | /* Given an rtx X being reloaded into a reg required to be | |
601 | in class CLASS, return the class of reg to actually use. | |
602 | In general this is just CLASS; but on some machines | |
603 | in some cases it is preferable to use a more restrictive class. */ | |
604 | ||
605 | #define PREFERRED_RELOAD_CLASS(X, CLASS) \ | |
606 | arc_preferred_reload_class((X), (CLASS)) | |
607 | ||
608 | extern enum reg_class arc_preferred_reload_class (rtx, enum reg_class); | |
609 | ||
610 | /* Return the maximum number of consecutive registers | |
611 | needed to represent mode MODE in a register of class CLASS. */ | |
612 | ||
613 | #define CLASS_MAX_NREGS(CLASS, MODE) \ | |
614 | (( GET_MODE_SIZE (MODE) == 16 && CLASS == SIMD_VR_REGS) ? 1: \ | |
615 | ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) | |
616 | ||
617 | #define SMALL_INT(X) ((unsigned) ((X) + 0x100) < 0x200) | |
618 | #define SMALL_INT_RANGE(X, OFFSET, SHIFT) \ | |
619 | ((unsigned) (((X) >> (SHIFT)) + 0x100) \ | |
620 | < 0x200 - ((unsigned) (OFFSET) >> (SHIFT))) | |
621 | #define SIGNED_INT12(X) ((unsigned) ((X) + 0x800) < 0x1000) | |
f50bb868 | 622 | #define SIGNED_INT16(X) ((unsigned) ((X) + 0x8000) < 0x10000) |
526b7aee SV |
623 | #define LARGE_INT(X) \ |
624 | (((X) < 0) \ | |
625 | ? (X) >= (-(HOST_WIDE_INT) 0x7fffffff - 1) \ | |
626 | : (unsigned HOST_WIDE_INT) (X) <= (unsigned HOST_WIDE_INT) 0xffffffff) | |
627 | #define UNSIGNED_INT3(X) ((unsigned) (X) < 0x8) | |
628 | #define UNSIGNED_INT5(X) ((unsigned) (X) < 0x20) | |
629 | #define UNSIGNED_INT6(X) ((unsigned) (X) < 0x40) | |
630 | #define UNSIGNED_INT7(X) ((unsigned) (X) < 0x80) | |
631 | #define UNSIGNED_INT8(X) ((unsigned) (X) < 0x100) | |
7132ae19 CZ |
632 | #define UNSIGNED_INT12(X) ((unsigned) (X) < 0x800) |
633 | #define UNSIGNED_INT16(X) ((unsigned) (X) < 0x10000) | |
526b7aee SV |
634 | #define IS_ONE(X) ((X) == 1) |
635 | #define IS_ZERO(X) ((X) == 0) | |
636 | ||
637 | /* Stack layout and stack pointer usage. */ | |
638 | ||
639 | /* Define this macro if pushing a word onto the stack moves the stack | |
640 | pointer to a smaller address. */ | |
62f9f30b | 641 | #define STACK_GROWS_DOWNWARD 1 |
526b7aee SV |
642 | |
643 | /* Define this if the nominal address of the stack frame | |
644 | is at the high-address end of the local variables; | |
645 | that is, each additional local variable allocated | |
646 | goes at a more negative offset in the frame. */ | |
647 | #define FRAME_GROWS_DOWNWARD 1 | |
648 | ||
526b7aee SV |
649 | /* Offset from the stack pointer register to the first location at which |
650 | outgoing arguments are placed. */ | |
651 | #define STACK_POINTER_OFFSET (0) | |
652 | ||
653 | /* Offset of first parameter from the argument pointer register value. */ | |
654 | #define FIRST_PARM_OFFSET(FNDECL) (0) | |
655 | ||
656 | /* A C expression whose value is RTL representing the address in a | |
657 | stack frame where the pointer to the caller's frame is stored. | |
658 | Assume that FRAMEADDR is an RTL expression for the address of the | |
659 | stack frame itself. | |
660 | ||
661 | If you don't define this macro, the default is to return the value | |
662 | of FRAMEADDR--that is, the stack frame address is also the address | |
663 | of the stack word that points to the previous frame. */ | |
664 | /* ??? unfinished */ | |
665 | /*define DYNAMIC_CHAIN_ADDRESS (FRAMEADDR)*/ | |
666 | ||
667 | /* A C expression whose value is RTL representing the value of the | |
668 | return address for the frame COUNT steps up from the current frame. | |
669 | FRAMEADDR is the frame pointer of the COUNT frame, or the frame | |
670 | pointer of the COUNT - 1 frame if `RETURN_ADDR_IN_PREVIOUS_FRAME' | |
671 | is defined. */ | |
672 | /* The current return address is in r31. The return address of anything | |
673 | farther back is at [%fp,4]. */ | |
674 | ||
675 | #define RETURN_ADDR_RTX(COUNT, FRAME) \ | |
676 | arc_return_addr_rtx(COUNT,FRAME) | |
677 | ||
678 | /* Register to use for pushing function arguments. */ | |
679 | #define STACK_POINTER_REGNUM 28 | |
680 | ||
681 | /* Base register for access to local variables of the function. */ | |
47d8cb23 CZ |
682 | #define FRAME_POINTER_REGNUM 145 |
683 | #define HARD_FRAME_POINTER_REGNUM 27 | |
526b7aee SV |
684 | |
685 | /* Base register for access to arguments of the function. This register | |
686 | will be eliminated into either fp or sp. */ | |
47d8cb23 | 687 | #define ARG_POINTER_REGNUM 144 |
526b7aee SV |
688 | |
689 | #define RETURN_ADDR_REGNUM 31 | |
690 | ||
691 | /* TODO - check usage of STATIC_CHAIN_REGNUM with a testcase */ | |
692 | /* Register in which static-chain is passed to a function. This must | |
693 | not be a register used by the prologue. */ | |
694 | #define STATIC_CHAIN_REGNUM 11 | |
695 | ||
696 | /* Function argument passing. */ | |
697 | ||
698 | /* If defined, the maximum amount of space required for outgoing | |
699 | arguments will be computed and placed into the variable | |
700 | `crtl->outgoing_args_size'. No space will be pushed | |
701 | onto the stack for each call; instead, the function prologue should | |
702 | increase the stack frame size by this amount. */ | |
703 | #define ACCUMULATE_OUTGOING_ARGS 1 | |
704 | ||
705 | /* Define a data type for recording info about an argument list | |
706 | during the scan of that argument list. This data type should | |
707 | hold all necessary information about the function itself | |
708 | and about the args processed so far, enough to enable macros | |
709 | such as FUNCTION_ARG to determine where the next arg should go. */ | |
710 | #define CUMULATIVE_ARGS int | |
711 | ||
712 | /* Initialize a variable CUM of type CUMULATIVE_ARGS | |
713 | for a call to a function whose data type is FNTYPE. | |
714 | For a library call, FNTYPE is 0. */ | |
715 | #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT,N_NAMED_ARGS) \ | |
8f3304d0 | 716 | ((CUM) = 0) |
526b7aee SV |
717 | |
718 | /* The number of registers used for parameter passing. Local to this file. */ | |
048c6a9a | 719 | #define MAX_ARC_PARM_REGS (TARGET_RF16 ? 4 : 8) |
526b7aee SV |
720 | |
721 | /* 1 if N is a possible register number for function argument passing. */ | |
722 | #define FUNCTION_ARG_REGNO_P(N) \ | |
723 | ((unsigned) (N) < MAX_ARC_PARM_REGS) | |
724 | ||
725 | /* The ROUND_ADVANCE* macros are local to this file. */ | |
726 | /* Round SIZE up to a word boundary. */ | |
727 | #define ROUND_ADVANCE(SIZE) \ | |
728 | (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) | |
729 | ||
730 | /* Round arg MODE/TYPE up to the next word boundary. */ | |
731 | #define ROUND_ADVANCE_ARG(MODE, TYPE) \ | |
732 | ((MODE) == BLKmode \ | |
733 | ? ROUND_ADVANCE (int_size_in_bytes (TYPE)) \ | |
734 | : ROUND_ADVANCE (GET_MODE_SIZE (MODE))) | |
735 | ||
736 | #define ARC_FUNCTION_ARG_BOUNDARY(MODE,TYPE) PARM_BOUNDARY | |
737 | /* Round CUM up to the necessary point for argument MODE/TYPE. */ | |
738 | /* N.B. Vectors have alignment exceeding BIGGEST_ALIGNMENT. | |
739 | ARC_FUNCTION_ARG_BOUNDARY reduces this to no more than 32 bit. */ | |
740 | #define ROUND_ADVANCE_CUM(CUM, MODE, TYPE) \ | |
741 | ((((CUM) - 1) | (ARC_FUNCTION_ARG_BOUNDARY ((MODE), (TYPE)) - 1)/BITS_PER_WORD)\ | |
742 | + 1) | |
743 | ||
744 | /* Return boolean indicating arg of type TYPE and mode MODE will be passed in | |
745 | a reg. This includes arguments that have to be passed by reference as the | |
746 | pointer to them is passed in a reg if one is available (and that is what | |
747 | we're given). | |
748 | When passing arguments NAMED is always 1. When receiving arguments NAMED | |
749 | is 1 for each argument except the last in a stdarg/varargs function. In | |
750 | a stdarg function we want to treat the last named arg as named. In a | |
751 | varargs function we want to treat the last named arg (which is | |
752 | `__builtin_va_alist') as unnamed. | |
753 | This macro is only used in this file. */ | |
754 | #define PASS_IN_REG_P(CUM, MODE, TYPE) \ | |
755 | ((CUM) < MAX_ARC_PARM_REGS) | |
756 | ||
757 | ||
758 | /* Function results. */ | |
759 | ||
760 | /* Define how to find the value returned by a library function | |
761 | assuming the value has mode MODE. */ | |
762 | #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, 0) | |
763 | ||
764 | /* 1 if N is a possible register number for a function value | |
765 | as seen by the caller. */ | |
766 | /* ??? What about r1 in DI/DF values. */ | |
767 | #define FUNCTION_VALUE_REGNO_P(N) ((N) == 0) | |
768 | ||
769 | /* Tell GCC to use RETURN_IN_MEMORY. */ | |
770 | #define DEFAULT_PCC_STRUCT_RETURN 0 | |
771 | ||
526b7aee SV |
772 | /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, |
773 | the stack pointer does not matter. The value is tested only in | |
774 | functions that have frame pointers. | |
775 | No definition is equivalent to always zero. */ | |
776 | #define EXIT_IGNORE_STACK 0 | |
777 | ||
778 | #define EPILOGUE_USES(REGNO) arc_epilogue_uses ((REGNO)) | |
779 | ||
28633bbd CZ |
780 | #define EH_USES(REGNO) arc_eh_uses((REGNO)) |
781 | ||
526b7aee SV |
782 | /* Definitions for register eliminations. |
783 | ||
784 | This is an array of structures. Each structure initializes one pair | |
785 | of eliminable registers. The "from" register number is given first, | |
786 | followed by "to". Eliminations of the same "from" register are listed | |
787 | in order of preference. | |
788 | ||
789 | We have two registers that can be eliminated on the ARC. First, the | |
790 | argument pointer register can always be eliminated in favor of the stack | |
791 | pointer register or frame pointer register. Secondly, the frame pointer | |
792 | register can often be eliminated in favor of the stack pointer register. | |
793 | */ | |
794 | ||
795 | #define ELIMINABLE_REGS \ | |
796 | {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
47d8cb23 CZ |
797 | {ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ |
798 | {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
799 | {FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} | |
526b7aee SV |
800 | |
801 | /* Define the offset between two registers, one to be eliminated, and the other | |
802 | its replacement, at the start of a routine. */ | |
803 | extern int arc_initial_elimination_offset(int from, int to); | |
804 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ | |
805 | (OFFSET) = arc_initial_elimination_offset ((FROM), (TO)) | |
806 | ||
9de6af45 CZ |
807 | /* All the work done in PROFILE_HOOK, but still required. */ |
808 | #undef FUNCTION_PROFILER | |
809 | #define FUNCTION_PROFILER(STREAM, LABELNO) do { } while (0) | |
526b7aee SV |
810 | |
811 | #define NO_PROFILE_COUNTERS 1 | |
812 | ||
813 | /* Trampolines. */ | |
814 | ||
815 | /* Length in units of the trampoline for entering a nested function. */ | |
efcc2e30 | 816 | #define TRAMPOLINE_SIZE 16 |
526b7aee SV |
817 | |
818 | /* Alignment required for a trampoline in bits . */ | |
819 | /* For actual data alignment we just need 32, no more than the stack; | |
820 | however, to reduce cache coherency issues, we want to make sure that | |
821 | trampoline instructions always appear the same in any given cache line. */ | |
822 | #define TRAMPOLINE_ALIGNMENT 256 | |
823 | ||
824 | /* Library calls. */ | |
825 | ||
826 | /* Addressing modes, and classification of registers for them. */ | |
827 | ||
828 | /* Maximum number of registers that can appear in a valid memory address. */ | |
829 | /* The `ld' insn allows 2, but the `st' insn only allows 1. */ | |
830 | #define MAX_REGS_PER_ADDRESS 1 | |
831 | ||
832 | /* We have pre inc/dec (load/store with update). */ | |
833 | #define HAVE_PRE_INCREMENT 1 | |
834 | #define HAVE_PRE_DECREMENT 1 | |
835 | #define HAVE_POST_INCREMENT 1 | |
836 | #define HAVE_POST_DECREMENT 1 | |
837 | #define HAVE_PRE_MODIFY_DISP 1 | |
838 | #define HAVE_POST_MODIFY_DISP 1 | |
839 | #define HAVE_PRE_MODIFY_REG 1 | |
840 | #define HAVE_POST_MODIFY_REG 1 | |
841 | /* ??? should also do PRE_MODIFY_REG / POST_MODIFY_REG, but that requires | |
842 | a special predicate for the memory operand of stores, like for the SH. */ | |
843 | ||
844 | /* Recognize any constant value that is a valid address. */ | |
b6c354eb CZ |
845 | #define CONSTANT_ADDRESS_P(X) \ |
846 | (flag_pic ? (arc_legitimate_pic_addr_p (X) || LABEL_P (X)): \ | |
847 | (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ | |
848 | || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST)) | |
526b7aee SV |
849 | |
850 | /* Is the argument a const_int rtx, containing an exact power of 2 */ | |
851 | #define IS_POWEROF2_P(X) (! ( (X) & ((X) - 1)) && (X)) | |
ceaaa9fe | 852 | #define IS_POWEROF2_OR_0_P(X) (! ( (X) & ((X) - 1))) |
526b7aee SV |
853 | |
854 | /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx | |
855 | and check its validity for a certain class. | |
856 | We have two alternate definitions for each of them. | |
857 | The *_NONSTRICT definition accepts all pseudo regs; the other rejects | |
858 | them unless they have been allocated suitable hard regs. | |
859 | ||
860 | Most source files want to accept pseudo regs in the hope that | |
861 | they will get allocated to the class that the insn wants them to be in. | |
862 | Source files for reload pass need to be strict. | |
863 | After reload, it makes no difference, since pseudo regs have | |
864 | been eliminated by then. */ | |
865 | ||
866 | /* Nonzero if X is a hard reg that can be used as an index | |
867 | or if it is a pseudo reg. */ | |
4f9c5d5c CZ |
868 | #define REG_OK_FOR_INDEX_P_NONSTRICT(X) \ |
869 | ((unsigned) REGNO (X) >= FIRST_PSEUDO_REGISTER \ | |
870 | || REGNO_OK_FOR_BASE_P (REGNO (X))) | |
871 | ||
526b7aee SV |
872 | /* Nonzero if X is a hard reg that can be used as a base reg |
873 | or if it is a pseudo reg. */ | |
4f9c5d5c CZ |
874 | #define REG_OK_FOR_BASE_P_NONSTRICT(X) \ |
875 | ((unsigned) REGNO (X) >= FIRST_PSEUDO_REGISTER \ | |
876 | || REGNO_OK_FOR_BASE_P (REGNO (X))) | |
526b7aee SV |
877 | |
878 | /* Nonzero if X is a hard reg that can be used as an index. */ | |
879 | #define REG_OK_FOR_INDEX_P_STRICT(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) | |
880 | /* Nonzero if X is a hard reg that can be used as a base reg. */ | |
881 | #define REG_OK_FOR_BASE_P_STRICT(X) REGNO_OK_FOR_BASE_P (REGNO (X)) | |
882 | ||
883 | /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression | |
884 | that is a valid memory address for an instruction. | |
885 | The MODE argument is the machine mode for the MEM expression | |
886 | that wants to use this address. */ | |
887 | /* The `ld' insn allows [reg],[reg+shimm],[reg+limm],[reg+reg],[limm] | |
888 | but the `st' insn only allows [reg],[reg+shimm],[limm]. | |
889 | The only thing we can do is only allow the most strict case `st' and hope | |
890 | other parts optimize out the restrictions for `ld'. */ | |
891 | ||
892 | #define RTX_OK_FOR_BASE_P(X, STRICT) \ | |
893 | (REG_P (X) \ | |
894 | && ((STRICT) ? REG_OK_FOR_BASE_P_STRICT (X) : REG_OK_FOR_BASE_P_NONSTRICT (X))) | |
895 | ||
896 | #define RTX_OK_FOR_INDEX_P(X, STRICT) \ | |
897 | (REG_P (X) \ | |
898 | && ((STRICT) ? REG_OK_FOR_INDEX_P_STRICT (X) : REG_OK_FOR_INDEX_P_NONSTRICT (X))) | |
899 | ||
900 | /* A C compound statement that attempts to replace X, which is an address | |
901 | that needs reloading, with a valid memory address for an operand of | |
902 | mode MODE. WIN is a C statement label elsewhere in the code. | |
903 | ||
904 | We try to get a normal form | |
905 | of the address. That will allow inheritance of the address reloads. */ | |
906 | ||
907 | #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \ | |
908 | do { \ | |
909 | if (arc_legitimize_reload_address (&(X), (MODE), (OPNUM), (TYPE))) \ | |
910 | goto WIN; \ | |
911 | } while (0) | |
912 | ||
913 | /* Reading lp_count for anything but the lp instruction is very slow on the | |
914 | ARC700. */ | |
915 | #define DONT_REALLOC(REGNO,MODE) \ | |
916 | (TARGET_ARC700 && (REGNO) == 60) | |
917 | ||
918 | ||
919 | /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, | |
920 | return the mode to be used for the comparison. */ | |
ef4bddc2 | 921 | /*extern machine_mode arc_select_cc_mode ();*/ |
526b7aee SV |
922 | #define SELECT_CC_MODE(OP, X, Y) \ |
923 | arc_select_cc_mode (OP, X, Y) | |
924 | ||
925 | /* Return non-zero if SELECT_CC_MODE will never return MODE for a | |
926 | floating point inequality comparison. */ | |
927 | #define REVERSIBLE_CC_MODE(MODE) 1 /*???*/ | |
928 | ||
929 | /* Costs. */ | |
930 | ||
526b7aee SV |
931 | /* The cost of a branch insn. */ |
932 | /* ??? What's the right value here? Branches are certainly more | |
933 | expensive than reg->reg moves. */ | |
934 | #define BRANCH_COST(speed_p, predictable_p) 2 | |
935 | ||
b4e23970 JR |
936 | /* Scc sets the destination to 1 and then conditionally zeroes it. |
937 | Best case, ORed SCCs can be made into clear - condset - condset. | |
938 | But it could also end up as five insns. So say it costs four on | |
939 | average. | |
940 | These extra instructions - and the second comparison - will also be | |
941 | an extra cost if the first comparison would have been decisive. | |
942 | So get an average saving, with a probability of the first branch | |
943 | beging decisive of p0, we want: | |
944 | p0 * (branch_cost - 4) > (1 - p0) * 5 | |
945 | ??? We don't get to see that probability to evaluate, so we can | |
946 | only wildly guess that it might be 50%. | |
947 | ??? The compiler also lacks the notion of branch predictability. */ | |
948 | #define LOGICAL_OP_NON_SHORT_CIRCUIT \ | |
949 | (BRANCH_COST (optimize_function_for_speed_p (cfun), \ | |
950 | false) > 9) | |
951 | ||
526b7aee SV |
952 | /* Nonzero if access to memory by bytes is slow and undesirable. |
953 | For RISC chips, it means that access to memory by bytes is no | |
954 | better than access by words when possible, so grab a whole word | |
955 | and maybe make use of that. */ | |
956 | #define SLOW_BYTE_ACCESS 0 | |
957 | ||
958 | /* Define this macro if it is as good or better to call a constant | |
959 | function address than to call an address kept in a register. */ | |
960 | /* On the ARC, calling through registers is slow. */ | |
1e8552c2 | 961 | #define NO_FUNCTION_CSE 1 |
526b7aee SV |
962 | |
963 | /* Section selection. */ | |
964 | /* WARNING: These section names also appear in dwarfout.c. */ | |
965 | ||
966 | #define TEXT_SECTION_ASM_OP "\t.section\t.text" | |
967 | #define DATA_SECTION_ASM_OP "\t.section\t.data" | |
968 | ||
969 | #define BSS_SECTION_ASM_OP "\t.section\t.bss" | |
970 | #define SDATA_SECTION_ASM_OP "\t.section\t.sdata" | |
971 | #define SBSS_SECTION_ASM_OP "\t.section\t.sbss" | |
972 | ||
973 | /* Expression whose value is a string, including spacing, containing the | |
974 | assembler operation to identify the following data as initialization/termination | |
975 | code. If not defined, GCC will assume such a section does not exist. */ | |
976 | #define INIT_SECTION_ASM_OP "\t.section\t.init" | |
977 | #define FINI_SECTION_ASM_OP "\t.section\t.fini" | |
978 | ||
979 | /* Define this macro if jump tables (for tablejump insns) should be | |
980 | output in the text section, along with the assembler instructions. | |
981 | Otherwise, the readonly data section is used. | |
982 | This macro is irrelevant if there is no separate readonly data section. */ | |
983 | #define JUMP_TABLES_IN_TEXT_SECTION (flag_pic || CASE_VECTOR_PC_RELATIVE) | |
984 | ||
985 | /* For DWARF. Marginally different than default so output is "prettier" | |
986 | (and consistent with above). */ | |
987 | #define PUSHSECTION_FORMAT "\t%s %s\n" | |
988 | ||
989 | /* Tell crtstuff.c we're using ELF. */ | |
990 | #define OBJECT_FORMAT_ELF | |
991 | ||
992 | /* PIC */ | |
993 | ||
994 | /* The register number of the register used to address a table of static | |
995 | data addresses in memory. In some cases this register is defined by a | |
996 | processor's ``application binary interface'' (ABI). When this macro | |
997 | is defined, RTL is generated for this register once, as with the stack | |
998 | pointer and frame pointer registers. If this macro is not defined, it | |
999 | is up to the machine-dependent files to allocate such a register (if | |
1000 | necessary). */ | |
1001 | #define PIC_OFFSET_TABLE_REGNUM 26 | |
1002 | ||
1003 | /* Define this macro if the register defined by PIC_OFFSET_TABLE_REGNUM is | |
1004 | clobbered by calls. Do not define this macro if PIC_OFFSET_TABLE_REGNUM | |
1005 | is not defined. */ | |
1006 | /* This register is call-saved on the ARC. */ | |
1007 | /*#define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED*/ | |
1008 | ||
1009 | /* A C expression that is nonzero if X is a legitimate immediate | |
1010 | operand on the target machine when generating position independent code. | |
1011 | You can assume that X satisfies CONSTANT_P, so you need not | |
1012 | check this. You can also assume `flag_pic' is true, so you need not | |
1013 | check it either. You need not define this macro if all constants | |
1014 | (including SYMBOL_REF) can be immediate operands when generating | |
1015 | position independent code. */ | |
b6c354eb CZ |
1016 | #define LEGITIMATE_PIC_OPERAND_P(X) \ |
1017 | (!arc_raw_symbolic_reference_mentioned_p ((X), true)) | |
526b7aee SV |
1018 | |
1019 | /* PIC and small data don't mix on ARC because they use the same register. */ | |
1020 | #define SDATA_BASE_REGNUM 26 | |
1021 | ||
1022 | #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ | |
1023 | (flag_pic \ | |
1024 | ? (GLOBAL ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4 \ | |
1025 | : DW_EH_PE_absptr) | |
1026 | ||
1027 | /* Control the assembler format that we output. */ | |
1028 | ||
1029 | /* A C string constant describing how to begin a comment in the target | |
1030 | assembler language. The compiler assumes that the comment will | |
1031 | end at the end of the line. */ | |
1032 | /* Gas needs this to be "#" in order to recognize line directives. */ | |
1033 | #define ASM_COMMENT_START "#" | |
1034 | ||
1035 | /* Output to assembler file text saying following lines | |
1036 | may contain character constants, extra white space, comments, etc. */ | |
fad92291 | 1037 | #undef ASM_APP_ON |
526b7aee SV |
1038 | #define ASM_APP_ON "" |
1039 | ||
1040 | /* Output to assembler file text saying following lines | |
1041 | no longer contain unusual constructs. */ | |
fad92291 | 1042 | #undef ASM_APP_OFF |
526b7aee SV |
1043 | #define ASM_APP_OFF "" |
1044 | ||
1045 | /* Globalizing directive for a label. */ | |
1046 | #define GLOBAL_ASM_OP "\t.global\t" | |
1047 | ||
1048 | /* This is how to output an assembler line defining a `char' constant. */ | |
1049 | #define ASM_OUTPUT_CHAR(FILE, VALUE) \ | |
1050 | ( fprintf (FILE, "\t.byte\t"), \ | |
1051 | output_addr_const (FILE, (VALUE)), \ | |
1052 | fprintf (FILE, "\n")) | |
1053 | ||
1054 | /* This is how to output an assembler line defining a `short' constant. */ | |
1055 | #define ASM_OUTPUT_SHORT(FILE, VALUE) \ | |
1056 | ( fprintf (FILE, "\t.hword\t"), \ | |
1057 | output_addr_const (FILE, (VALUE)), \ | |
1058 | fprintf (FILE, "\n")) | |
1059 | ||
1060 | /* This is how to output an assembler line defining an `int' constant. | |
1061 | We also handle symbol output here. Code addresses must be right shifted | |
1062 | by 2 because that's how the jump instruction wants them. */ | |
1063 | #define ASM_OUTPUT_INT(FILE, VALUE) \ | |
1064 | do { \ | |
1065 | fprintf (FILE, "\t.word\t"); \ | |
1066 | if (GET_CODE (VALUE) == LABEL_REF) \ | |
1067 | { \ | |
1068 | fprintf (FILE, "%%st(@"); \ | |
1069 | output_addr_const (FILE, (VALUE)); \ | |
1070 | fprintf (FILE, ")"); \ | |
1071 | } \ | |
1072 | else \ | |
1073 | output_addr_const (FILE, (VALUE)); \ | |
1074 | fprintf (FILE, "\n"); \ | |
1075 | } while (0) | |
1076 | ||
1077 | /* This is how to output an assembler line defining a `float' constant. */ | |
1078 | #define ASM_OUTPUT_FLOAT(FILE, VALUE) \ | |
1079 | { \ | |
1080 | long t; \ | |
1081 | char str[30]; \ | |
1082 | REAL_VALUE_TO_TARGET_SINGLE ((VALUE), t); \ | |
1083 | REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", str); \ | |
1084 | fprintf (FILE, "\t.word\t0x%lx %s %s\n", \ | |
1085 | t, ASM_COMMENT_START, str); \ | |
1086 | } | |
1087 | ||
1088 | /* This is how to output an assembler line defining a `double' constant. */ | |
1089 | #define ASM_OUTPUT_DOUBLE(FILE, VALUE) \ | |
1090 | { \ | |
1091 | long t[2]; \ | |
1092 | char str[30]; \ | |
1093 | REAL_VALUE_TO_TARGET_DOUBLE ((VALUE), t); \ | |
1094 | REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", str); \ | |
1095 | fprintf (FILE, "\t.word\t0x%lx %s %s\n\t.word\t0x%lx\n", \ | |
1096 | t[0], ASM_COMMENT_START, str, t[1]); \ | |
1097 | } | |
1098 | ||
1099 | /* This is how to output the definition of a user-level label named NAME, | |
1100 | such as the label on a static function or variable NAME. */ | |
1101 | #define ASM_OUTPUT_LABEL(FILE, NAME) \ | |
1102 | do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0) | |
1103 | ||
1104 | #define ASM_NAME_P(NAME) ( NAME[0]=='*') | |
1105 | ||
1106 | /* This is how to output a reference to a user-level label named NAME. | |
1107 | `assemble_name' uses this. */ | |
1108 | /* We work around a dwarfout.c deficiency by watching for labels from it and | |
1109 | not adding the '_' prefix. There is a comment in | |
1110 | dwarfout.c that says it should be using ASM_OUTPUT_INTERNAL_LABEL. */ | |
1111 | #define ASM_OUTPUT_LABELREF(FILE, NAME1) \ | |
1112 | do { \ | |
1113 | const char *NAME; \ | |
1114 | NAME = (*targetm.strip_name_encoding)(NAME1); \ | |
1115 | if ((NAME)[0] == '.' && (NAME)[1] == 'L') \ | |
1116 | fprintf (FILE, "%s", NAME); \ | |
1117 | else \ | |
1118 | { \ | |
1119 | if (!ASM_NAME_P (NAME1)) \ | |
1120 | fprintf (FILE, "%s", user_label_prefix); \ | |
1121 | fprintf (FILE, "%s", NAME); \ | |
1122 | } \ | |
1123 | } while (0) | |
1124 | ||
1125 | /* This is how to output a reference to a symbol_ref / label_ref as | |
1126 | (part of) an operand. To disambiguate from register names like | |
1127 | a1 / a2 / status etc, symbols are preceded by '@'. */ | |
1128 | #define ASM_OUTPUT_SYMBOL_REF(FILE,SYM) \ | |
1129 | ASM_OUTPUT_LABEL_REF ((FILE), XSTR ((SYM), 0)) | |
1130 | #define ASM_OUTPUT_LABEL_REF(FILE,STR) \ | |
1131 | do \ | |
1132 | { \ | |
1133 | fputc ('@', file); \ | |
1134 | assemble_name ((FILE), (STR)); \ | |
1135 | } \ | |
1136 | while (0) | |
1137 | ||
1138 | /* Store in OUTPUT a string (made with alloca) containing | |
1139 | an assembler-name for a local static variable named NAME. | |
1140 | LABELNO is an integer which is different for each call. */ | |
d08a318b CZ |
1141 | #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \ |
1142 | ((OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \ | |
1143 | sprintf ((OUTPUT), "%s.%u", (NAME), (unsigned int)(LABELNO))) | |
526b7aee SV |
1144 | |
1145 | /* The following macro defines the format used to output the second | |
1146 | operand of the .type assembler directive. Different svr4 assemblers | |
1147 | expect various different forms for this operand. The one given here | |
1148 | is just a default. You may need to override it in your machine- | |
1149 | specific tm.h file (depending upon the particulars of your assembler). */ | |
1150 | ||
1151 | #undef TYPE_OPERAND_FMT | |
1152 | #define TYPE_OPERAND_FMT "@%s" | |
1153 | ||
1154 | /* A C string containing the appropriate assembler directive to | |
1155 | specify the size of a symbol, without any arguments. On systems | |
1156 | that use ELF, the default (in `config/elfos.h') is `"\t.size\t"'; | |
1157 | on other systems, the default is not to define this macro. */ | |
1158 | #undef SIZE_ASM_OP | |
1159 | #define SIZE_ASM_OP "\t.size\t" | |
1160 | ||
1161 | /* Assembler pseudo-op to equate one value with another. */ | |
1162 | /* ??? This is needed because dwarfout.c provides a default definition too | |
1163 | late for defaults.h (which contains the default definition of ASM_OTPUT_DEF | |
1164 | that we use). */ | |
1165 | #ifdef SET_ASM_OP | |
1166 | #undef SET_ASM_OP | |
1167 | #endif | |
1168 | #define SET_ASM_OP "\t.set\t" | |
1169 | ||
f50bb868 | 1170 | extern char rname29[], rname30[]; |
526b7aee SV |
1171 | extern char rname56[], rname57[], rname58[], rname59[]; |
1172 | /* How to refer to registers in assembler output. | |
1173 | This sequence is indexed by compiler's hard-register-number (see above). */ | |
1174 | #define REGISTER_NAMES \ | |
1175 | { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \ | |
1176 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \ | |
1177 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \ | |
f50bb868 | 1178 | "r24", "r25", "gp", "fp", "sp", rname29, rname30, "blink", \ |
526b7aee SV |
1179 | "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", \ |
1180 | "d1", "d1", "d2", "d2", "r44", "r45", "r46", "r47", \ | |
1181 | "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", \ | |
47d8cb23 | 1182 | rname56,rname57,rname58,rname59,"lp_count", "cc", "limm", "pcl", \ |
526b7aee SV |
1183 | "vr0", "vr1", "vr2", "vr3", "vr4", "vr5", "vr6", "vr7", \ |
1184 | "vr8", "vr9", "vr10", "vr11", "vr12", "vr13", "vr14", "vr15", \ | |
1185 | "vr16", "vr17", "vr18", "vr19", "vr20", "vr21", "vr22", "vr23", \ | |
1186 | "vr24", "vr25", "vr26", "vr27", "vr28", "vr29", "vr30", "vr31", \ | |
1187 | "vr32", "vr33", "vr34", "vr35", "vr36", "vr37", "vr38", "vr39", \ | |
1188 | "vr40", "vr41", "vr42", "vr43", "vr44", "vr45", "vr46", "vr47", \ | |
1189 | "vr48", "vr49", "vr50", "vr51", "vr52", "vr53", "vr54", "vr55", \ | |
1190 | "vr56", "vr57", "vr58", "vr59", "vr60", "vr61", "vr62", "vr63", \ | |
1191 | "dr0", "dr1", "dr2", "dr3", "dr4", "dr5", "dr6", "dr7", \ | |
1192 | "dr0", "dr1", "dr2", "dr3", "dr4", "dr5", "dr6", "dr7", \ | |
47d8cb23 | 1193 | "arg", "frame" \ |
526b7aee SV |
1194 | } |
1195 | ||
0a98ae06 CZ |
1196 | #define ADDITIONAL_REGISTER_NAMES \ |
1197 | { \ | |
3b9eb2f8 CZ |
1198 | {"r26", 26}, \ |
1199 | {"r27", 27}, \ | |
0a98ae06 CZ |
1200 | {"ilink", 29}, \ |
1201 | {"r29", 29}, \ | |
8f176ba2 CZ |
1202 | {"r30", 30}, \ |
1203 | {"r40", 40}, \ | |
1204 | {"r41", 41}, \ | |
1205 | {"r42", 42}, \ | |
1206 | {"r43", 43}, \ | |
1207 | {"r56", 56}, \ | |
1208 | {"r57", 57}, \ | |
1209 | {"r58", 58}, \ | |
1210 | {"r59", 59} \ | |
0a98ae06 CZ |
1211 | } |
1212 | ||
526b7aee SV |
1213 | /* Entry to the insn conditionalizer. */ |
1214 | #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \ | |
1215 | arc_final_prescan_insn (INSN, OPVEC, NOPERANDS) | |
1216 | ||
1217 | /* A C expression which evaluates to true if CODE is a valid | |
1218 | punctuation character for use in the `PRINT_OPERAND' macro. */ | |
1219 | extern char arc_punct_chars[]; | |
1220 | #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \ | |
1221 | arc_punct_chars[(unsigned char) (CHAR)] | |
1222 | ||
1223 | /* Print operand X (an rtx) in assembler syntax to file FILE. | |
1224 | CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. | |
1225 | For `%' followed by punctuation, CODE is the punctuation and X is null. */ | |
1226 | #define PRINT_OPERAND(FILE, X, CODE) \ | |
1227 | arc_print_operand (FILE, X, CODE) | |
1228 | ||
1229 | /* A C compound statement to output to stdio stream STREAM the | |
1230 | assembler syntax for an instruction operand that is a memory | |
1231 | reference whose address is ADDR. ADDR is an RTL expression. | |
1232 | ||
1233 | On some machines, the syntax for a symbolic address depends on | |
1234 | the section that the address refers to. On these machines, | |
1235 | define the macro `ENCODE_SECTION_INFO' to store the information | |
1236 | into the `symbol_ref', and then check for it here. */ | |
1237 | #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ | |
1238 | arc_print_operand_address (FILE, ADDR) | |
1239 | ||
1240 | /* This is how to output an element of a case-vector that is absolute. */ | |
1241 | #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ | |
1242 | do { \ | |
1243 | char label[30]; \ | |
1244 | ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \ | |
1245 | fprintf (FILE, "\t.word "); \ | |
1246 | assemble_name (FILE, label); \ | |
aac1c11c | 1247 | fprintf (FILE, "\n"); \ |
526b7aee SV |
1248 | } while (0) |
1249 | ||
1250 | /* This is how to output an element of a case-vector that is relative. */ | |
aac1c11c CZ |
1251 | #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ |
1252 | do { \ | |
1253 | char label[30]; \ | |
1254 | ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \ | |
1255 | if (!TARGET_BI_BIH) \ | |
1256 | { \ | |
1257 | switch (GET_MODE (BODY)) \ | |
1258 | { \ | |
1259 | case E_QImode: fprintf (FILE, "\t.byte "); break; \ | |
1260 | case E_HImode: fprintf (FILE, "\t.hword "); break; \ | |
1261 | case E_SImode: fprintf (FILE, "\t.word "); break; \ | |
1262 | default: gcc_unreachable (); \ | |
1263 | } \ | |
1264 | assemble_name (FILE, label); \ | |
1265 | fprintf (FILE, "-"); \ | |
1266 | ASM_GENERATE_INTERNAL_LABEL (label, "L", REL); \ | |
1267 | assemble_name (FILE, label); \ | |
1268 | fprintf (FILE, "\n"); \ | |
1269 | } \ | |
1270 | else \ | |
1271 | { \ | |
1272 | switch (GET_MODE (BODY)) \ | |
1273 | { \ | |
1274 | case E_SImode: fprintf (FILE, "\tb\t@"); break; \ | |
1275 | case E_HImode: \ | |
1276 | case E_QImode: fprintf (FILE, "\tb_s\t@"); break; \ | |
1277 | default: gcc_unreachable (); \ | |
1278 | } \ | |
1279 | assemble_name (FILE, label); \ | |
1280 | fprintf(FILE, "\n"); \ | |
1281 | } \ | |
1282 | } while (0) | |
1283 | ||
1284 | /* Defined to also emit an .align in elfos.h. We don't want that. */ | |
1285 | #undef ASM_OUTPUT_CASE_LABEL | |
526b7aee SV |
1286 | |
1287 | /* ADDR_DIFF_VECs are in the text section and thus can affect the | |
1288 | current alignment. */ | |
1289 | #define ASM_OUTPUT_CASE_END(FILE, NUM, JUMPTABLE) \ | |
1290 | do \ | |
1291 | { \ | |
1292 | if (GET_CODE (PATTERN (JUMPTABLE)) == ADDR_DIFF_VEC \ | |
cf098191 RS |
1293 | && ((GET_MODE_SIZE (as_a <scalar_int_mode> \ |
1294 | (GET_MODE (PATTERN (JUMPTABLE)))) \ | |
526b7aee SV |
1295 | * XVECLEN (PATTERN (JUMPTABLE), 1) + 1) \ |
1296 | & 2)) \ | |
1297 | arc_toggle_unalign (); \ | |
1298 | } \ | |
1299 | while (0) | |
1300 | ||
1301 | #define JUMP_ALIGN(LABEL) (arc_size_opt_level < 2 ? 2 : 0) | |
1302 | #define LABEL_ALIGN_AFTER_BARRIER(LABEL) \ | |
1303 | (JUMP_ALIGN(LABEL) \ | |
1304 | ? JUMP_ALIGN(LABEL) \ | |
1305 | : GET_CODE (PATTERN (prev_active_insn (LABEL))) == ADDR_DIFF_VEC \ | |
1306 | ? 1 : 0) | |
1307 | /* The desired alignment for the location counter at the beginning | |
1308 | of a loop. */ | |
1309 | /* On the ARC, align loops to 4 byte boundaries unless doing all-out size | |
1310 | optimization. */ | |
a2de90a4 | 1311 | #define LOOP_ALIGN(X) 0 |
526b7aee SV |
1312 | |
1313 | #define LABEL_ALIGN(LABEL) (arc_label_align (LABEL)) | |
1314 | ||
1315 | /* This is how to output an assembler line | |
1316 | that says to advance the location counter | |
1317 | to a multiple of 2**LOG bytes. */ | |
1318 | #define ASM_OUTPUT_ALIGN(FILE,LOG) \ | |
1319 | do { \ | |
1320 | if ((LOG) != 0) fprintf (FILE, "\t.align %d\n", 1 << (LOG)); \ | |
1321 | if ((LOG) > 1) \ | |
1322 | arc_clear_unalign (); \ | |
1323 | } while (0) | |
1324 | ||
1325 | /* ASM_OUTPUT_ALIGNED_DECL_LOCAL (STREAM, DECL, NAME, SIZE, ALIGNMENT) | |
1326 | Define this macro when you need to see the variable's decl in order to | |
1327 | chose what to output. */ | |
1328 | #define ASM_OUTPUT_ALIGNED_DECL_LOCAL(STREAM, DECL, NAME, SIZE, ALIGNMENT) \ | |
1329 | arc_asm_output_aligned_decl_local (STREAM, DECL, NAME, SIZE, ALIGNMENT, 0) | |
1330 | ||
526b7aee SV |
1331 | /* Debugging information. */ |
1332 | ||
7e0db0cd | 1333 | /* Generate DWARF debugging information. */ |
526b7aee SV |
1334 | #ifdef DWARF2_DEBUGGING_INFO |
1335 | #undef DWARF2_DEBUGGING_INFO | |
1336 | #endif | |
1337 | #define DWARF2_DEBUGGING_INFO | |
1338 | ||
1339 | /* Prefer STABS (for now). */ | |
1340 | #undef PREFERRED_DEBUGGING_TYPE | |
1341 | #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG | |
1342 | ||
ca60bd93 ML |
1343 | /* How to renumber registers for gdb. */ |
1344 | #define DEBUGGER_REGNO(REGNO) \ | |
526b7aee | 1345 | ((TARGET_MULMAC_32BY16_SET && (REGNO) >= 56 && (REGNO) <= 57) \ |
82cd9a96 CZ |
1346 | ? ((REGNO) ^ !TARGET_BIG_ENDIAN) \ |
1347 | : (TARGET_MUL64_SET && (REGNO) >= 57 && (REGNO) <= 58) \ | |
1348 | ? (((REGNO) == 57) \ | |
1349 | ? 58 /* MMED */ \ | |
1350 | : 57 + !!TARGET_MULMAC_32BY16_SET) /* MLO */ \ | |
526b7aee SV |
1351 | : (REGNO)) |
1352 | ||
82cd9a96 | 1353 | /* Use gcc hard register numbering for eh_frame. */ |
68a650ba | 1354 | #define DWARF_FRAME_REGNUM(REG) ((REG) < 144 ? REG : INVALID_REGNUM) |
526b7aee | 1355 | |
82cd9a96 CZ |
1356 | /* Map register numbers held in the call frame info that gcc has |
1357 | collected using DWARF_FRAME_REGNUM to those that should be output | |
1358 | in .debug_frame and .eh_frame. */ | |
1359 | #define DWARF2_FRAME_REG_OUT(REGNO, FOR_EH) \ | |
1360 | ((TARGET_MULMAC_32BY16_SET && (REGNO) >= 56 && (REGNO) <= 57) \ | |
1361 | ? ((REGNO) ^ !TARGET_BIG_ENDIAN) \ | |
1362 | : (TARGET_MUL64_SET && (REGNO) >= 57 && (REGNO) <= 58) \ | |
1363 | ? (((REGNO) == 57) \ | |
1364 | ? 58 /* MMED */ \ | |
1365 | : 57 + !!TARGET_MULMAC_32BY16_SET) /* MLO */ \ | |
1366 | : (REGNO)) | |
1367 | ||
68a650ba CZ |
1368 | /* The DWARF 2 CFA column which tracks the return address. */ |
1369 | #define DWARF_FRAME_RETURN_COLUMN RETURN_ADDR_REGNUM | |
1370 | #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM) | |
526b7aee | 1371 | |
68a650ba CZ |
1372 | /* The DWARF 2 CFA column which tracks the return address from a signal handler |
1373 | context. This value must not correspond to a hard register and must be out | |
1374 | of the range of DWARF_FRAME_REGNUM(). */ | |
1375 | #define DWARF_ALT_FRAME_RETURN_COLUMN 144 | |
526b7aee SV |
1376 | |
1377 | /* Frame info. */ | |
1378 | ||
6fe5e235 CZ |
1379 | #define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM) |
1380 | ||
1381 | #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 2) | |
1382 | ||
526b7aee SV |
1383 | /* Miscellaneous. */ |
1384 | ||
1385 | /* Specify the machine mode that this machine uses | |
1386 | for the index in the tablejump instruction. | |
1387 | If we have pc relative case vectors, we start the case vector shortening | |
1388 | with QImode. */ | |
aac1c11c CZ |
1389 | #define CASE_VECTOR_MODE \ |
1390 | (TARGET_BI_BIH ? SImode \ | |
1391 | : (optimize && (CASE_VECTOR_PC_RELATIVE || flag_pic)) ? QImode : Pmode) | |
526b7aee SV |
1392 | |
1393 | /* Define as C expression which evaluates to nonzero if the tablejump | |
1394 | instruction expects the table to contain offsets from the address of the | |
1395 | table. | |
1396 | Do not define this if the table should contain absolute addresses. */ | |
aac1c11c CZ |
1397 | #define CASE_VECTOR_PC_RELATIVE \ |
1398 | (TARGET_CASE_VECTOR_PC_RELATIVE || TARGET_BI_BIH) | |
1399 | ||
1400 | #define CASE_VECTOR_SHORTEN_MODE(MIN_OFFSET, MAX_OFFSET, BODY) \ | |
1401 | (TARGET_BI_BIH ? \ | |
1402 | ((MIN_OFFSET) >= -512 && (MAX_OFFSET) <= 508 ? HImode : SImode) \ | |
1403 | : ((MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 255 \ | |
1404 | ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 1, QImode) \ | |
1405 | : (MIN_OFFSET) >= -128 && (MAX_OFFSET) <= 127 \ | |
1406 | ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 0, QImode) \ | |
1407 | : (MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 65535 \ | |
1408 | ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 1, HImode) \ | |
1409 | : (MIN_OFFSET) >= -32768 && (MAX_OFFSET) <= 32767 \ | |
1410 | ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 0, HImode) \ | |
1411 | : SImode)) | |
1412 | ||
1413 | #define ADDR_VEC_ALIGN(VEC_INSN) \ | |
1414 | (TARGET_BI_BIH ? 0 \ | |
1415 | : exact_log2 (GET_MODE_SIZE (as_a <scalar_int_mode> \ | |
1416 | (GET_MODE (PATTERN (VEC_INSN)))))) | |
526b7aee | 1417 | |
d4fe8839 CZ |
1418 | #define INSN_LENGTH_ALIGNMENT(INSN) \ |
1419 | ((JUMP_TABLE_DATA_P (INSN) \ | |
526b7aee | 1420 | && GET_CODE (PATTERN (INSN)) == ADDR_DIFF_VEC \ |
d4fe8839 | 1421 | && GET_MODE (PATTERN (INSN)) == QImode) \ |
526b7aee SV |
1422 | ? 0 : length_unit_log) |
1423 | ||
1424 | /* Define if operations between registers always perform the operation | |
1425 | on the full register even if a narrower mode is specified. */ | |
9e11bfef | 1426 | #define WORD_REGISTER_OPERATIONS 1 |
526b7aee SV |
1427 | |
1428 | /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD | |
1429 | will either zero-extend or sign-extend. The value of this macro should | |
1430 | be the code that says which one of the two operations is implicitly | |
1431 | done, NIL if none. */ | |
1432 | #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND | |
1433 | ||
1434 | ||
1435 | /* Max number of bytes we can move from memory to memory | |
1436 | in one reasonably fast instruction. */ | |
1437 | #define MOVE_MAX 4 | |
1438 | ||
76715c32 | 1439 | /* Undo the effects of the cpymem pattern presence on STORE_BY_PIECES_P . */ |
526b7aee SV |
1440 | #define MOVE_RATIO(SPEED) ((SPEED) ? 15 : 3) |
1441 | ||
491483b0 CZ |
1442 | /* Define this to be nonzero if shift instructions ignore all but the |
1443 | low-order few bits. | |
526b7aee | 1444 | */ |
491483b0 | 1445 | #define SHIFT_COUNT_TRUNCATED 1 |
526b7aee | 1446 | |
b70c7c06 CZ |
1447 | /* Defines if the CLZ result is undefined or has a useful value. */ |
1448 | #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 31, 2) | |
1449 | ||
1450 | /* Defines if the CTZ result is undefined or has a useful value. */ | |
1451 | #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 31, 2) | |
1452 | ||
526b7aee SV |
1453 | /* We assume that the store-condition-codes instructions store 0 for false |
1454 | and some other value for true. This is the value stored for true. */ | |
1455 | #define STORE_FLAG_VALUE 1 | |
1456 | ||
1457 | /* Specify the machine mode that pointers have. | |
1458 | After generation of rtl, the compiler makes no further distinction | |
1459 | between pointers and any other objects of this machine mode. */ | |
1460 | /* ARCompact has full 32-bit pointers. */ | |
1461 | #define Pmode SImode | |
1462 | ||
1463 | /* A function address in a call instruction. */ | |
1464 | #define FUNCTION_MODE SImode | |
1465 | ||
1466 | /* Define the information needed to generate branch and scc insns. This is | |
1467 | stored from the compare operation. Note that we can't use "rtx" here | |
1468 | since it hasn't been defined! */ | |
1469 | extern struct rtx_def *arc_compare_op0, *arc_compare_op1; | |
1470 | ||
1471 | /* ARC function types. */ | |
1472 | enum arc_function_type { | |
1825c61e CZ |
1473 | /* No function should have the unknown type. This value is used to |
1474 | indicate the that function type has not yet been computed. */ | |
1475 | ARC_FUNCTION_UNKNOWN = 0, | |
1476 | ||
1477 | /* The normal function type indicates that the function has the | |
1478 | standard prologue and epilogue. */ | |
1479 | ARC_FUNCTION_NORMAL = 1 << 0, | |
526b7aee SV |
1480 | /* These are interrupt handlers. The name corresponds to the register |
1481 | name that contains the return address. */ | |
1825c61e CZ |
1482 | ARC_FUNCTION_ILINK1 = 1 << 1, |
1483 | ARC_FUNCTION_ILINK2 = 1 << 2, | |
c7314bc1 | 1484 | /* Fast interrupt is only available on ARCv2 processors. */ |
1825c61e CZ |
1485 | ARC_FUNCTION_FIRQ = 1 << 3, |
1486 | /* The naked function type indicates that the function does not have | |
1487 | prologue or epilogue, and that no stack frame is available. */ | |
1488 | ARC_FUNCTION_NAKED = 1 << 4 | |
526b7aee | 1489 | }; |
c7314bc1 | 1490 | |
1825c61e CZ |
1491 | /* Check if a function is an interrupt function. */ |
1492 | #define ARC_INTERRUPT_P(TYPE) \ | |
1493 | (((TYPE) & (ARC_FUNCTION_ILINK1 | ARC_FUNCTION_ILINK2 \ | |
1494 | | ARC_FUNCTION_FIRQ)) != 0) | |
1495 | ||
1496 | /* Check if a function is a fast interrupt function. */ | |
1497 | #define ARC_FAST_INTERRUPT_P(TYPE) (((TYPE) & ARC_FUNCTION_FIRQ) != 0) | |
1498 | ||
1499 | /* Check if a function is normal, that is, has standard prologue and | |
1500 | epilogue. */ | |
1501 | #define ARC_NORMAL_P(TYPE) (((TYPE) & ARC_FUNCTION_NORMAL) != 0) | |
526b7aee | 1502 | |
1825c61e CZ |
1503 | /* Check if a function is naked. */ |
1504 | #define ARC_NAKED_P(TYPE) (((TYPE) & ARC_FUNCTION_NAKED) != 0) | |
526b7aee SV |
1505 | |
1506 | /* Called by crtstuff.c to make calls to function FUNCTION that are defined in | |
1507 | SECTION_OP, and then to switch back to text section. */ | |
1508 | #undef CRT_CALL_STATIC_FUNCTION | |
19b250c4 CZ |
1509 | #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ |
1510 | asm (SECTION_OP "\n\t" \ | |
1511 | "add r12,pcl,@" USER_LABEL_PREFIX #FUNC "@pcl\n\t" \ | |
1512 | "jl [r12]\n" \ | |
1513 | TEXT_SECTION_ASM_OP); | |
526b7aee SV |
1514 | |
1515 | /* This macro expands to the name of the scratch register r12, used for | |
1516 | temporary calculations according to the ABI. */ | |
1517 | #define ARC_TEMP_SCRATCH_REG "r12" | |
1518 | ||
1519 | /* The C++ compiler must use one bit to indicate whether the function | |
1520 | that will be called through a pointer-to-member-function is | |
1521 | virtual. Normally, we assume that the low-order bit of a function | |
1522 | pointer must always be zero. Then, by ensuring that the | |
1523 | vtable_index is odd, we can distinguish which variant of the union | |
1524 | is in use. But, on some platforms function pointers can be odd, | |
1525 | and so this doesn't work. In that case, we use the low-order bit | |
1526 | of the `delta' field, and shift the remainder of the `delta' field | |
1527 | to the left. We needed to do this for A4 because the address was always | |
1528 | shifted and thus could be odd. */ | |
1529 | #define TARGET_PTRMEMFUNC_VBIT_LOCATION \ | |
1530 | (ptrmemfunc_vbit_in_pfn) | |
1531 | ||
1532 | #define INSN_SETS_ARE_DELAYED(X) \ | |
1533 | (GET_CODE (X) == INSN \ | |
1534 | && GET_CODE (PATTERN (X)) != SEQUENCE \ | |
1535 | && GET_CODE (PATTERN (X)) != USE \ | |
1536 | && GET_CODE (PATTERN (X)) != CLOBBER \ | |
1537 | && (get_attr_type (X) == TYPE_CALL || get_attr_type (X) == TYPE_SFUNC)) | |
1538 | ||
28633bbd | 1539 | #define INSN_REFERENCES_ARE_DELAYED(insn) \ |
5a5c5784 | 1540 | (INSN_SETS_ARE_DELAYED (insn)) |
526b7aee SV |
1541 | |
1542 | #define CALL_ATTR(X, NAME) \ | |
1543 | ((CALL_P (X) || NONJUMP_INSN_P (X)) \ | |
1544 | && GET_CODE (PATTERN (X)) != USE \ | |
1545 | && GET_CODE (PATTERN (X)) != CLOBBER \ | |
1546 | && get_attr_is_##NAME (X) == IS_##NAME##_YES) \ | |
1547 | ||
8f3304d0 CZ |
1548 | #define REVERSE_CONDITION(CODE,MODE) \ |
1549 | (((MODE) == CC_FP_GTmode || (MODE) == CC_FP_GEmode \ | |
1550 | || (MODE) == CC_FP_UNEQmode || (MODE) == CC_FP_ORDmode \ | |
1551 | || (MODE) == CC_FPXmode || (MODE) == CC_FPU_UNEQmode \ | |
fbf8314b | 1552 | || (MODE) == CC_FPUmode || (MODE) == CC_FPUEmode) \ |
8f3304d0 CZ |
1553 | ? reverse_condition_maybe_unordered ((CODE)) \ |
1554 | : reverse_condition ((CODE))) | |
526b7aee SV |
1555 | |
1556 | #define ADJUST_INSN_LENGTH(X, LENGTH) \ | |
1557 | ((LENGTH) \ | |
1558 | = (GET_CODE (PATTERN (X)) == SEQUENCE \ | |
1559 | ? ((LENGTH) \ | |
84034c69 DM |
1560 | + arc_adjust_insn_length ( \ |
1561 | as_a <rtx_sequence *> (PATTERN (X))->insn (0), \ | |
1562 | get_attr_length (as_a <rtx_sequence *> (PATTERN (X))->insn (0)), \ | |
1563 | true) \ | |
1564 | - get_attr_length (as_a <rtx_sequence *> (PATTERN (X))->insn (0)) \ | |
1565 | + arc_adjust_insn_length ( \ | |
1566 | as_a <rtx_sequence *> (PATTERN (X))->insn (1), \ | |
1567 | get_attr_length (as_a <rtx_sequence *> (PATTERN (X))->insn (1)), \ | |
1568 | true) \ | |
1569 | - get_attr_length (as_a <rtx_sequence *> (PATTERN (X))->insn (1))) \ | |
526b7aee SV |
1570 | : arc_adjust_insn_length ((X), (LENGTH), false))) |
1571 | ||
1572 | #define IS_ASM_LOGICAL_LINE_SEPARATOR(C,STR) ((C) == '`') | |
1573 | ||
1574 | #define INIT_EXPANDERS arc_init_expanders () | |
1575 | ||
526b7aee SV |
1576 | enum |
1577 | { | |
1578 | ARC_LRA_PRIORITY_NONE, ARC_LRA_PRIORITY_NONCOMPACT, ARC_LRA_PRIORITY_COMPACT | |
1579 | }; | |
1580 | ||
1581 | /* The define_cond_exec construct is rather crude, as we can't have | |
1582 | different ones with different conditions apply to different sets | |
1583 | of instructions. We can't use an attribute test inside the condition, | |
1584 | because that would lead to infinite recursion as the attribute test | |
1585 | needs to recognize the insn. So, instead we have a clause for | |
1586 | the pattern condition of all sfunc patterns which is only relevant for | |
1587 | the predicated varaint. */ | |
1588 | #define SFUNC_CHECK_PREDICABLE \ | |
1589 | (GET_CODE (PATTERN (insn)) != COND_EXEC || !flag_pic || !TARGET_MEDIUM_CALLS) | |
1590 | ||
f50bb868 CZ |
1591 | /* MPYW feature macro. Only valid for ARCHS and ARCEM cores. */ |
1592 | #define TARGET_MPYW ((arc_mpy_option > 0) && TARGET_V2) | |
1593 | /* Full ARCv2 multiplication feature macro. */ | |
1594 | #define TARGET_MULTI ((arc_mpy_option > 1) && TARGET_V2) | |
1595 | /* General MPY feature macro. */ | |
1596 | #define TARGET_MPY ((TARGET_ARC700 && (!TARGET_NOMPY_SET)) || TARGET_MULTI) | |
1597 | /* ARC700 MPY feature macro. */ | |
1598 | #define TARGET_ARC700_MPY (TARGET_ARC700 && (!TARGET_NOMPY_SET)) | |
1599 | /* Any multiplication feature macro. */ | |
1600 | #define TARGET_ANY_MPY \ | |
1601 | (TARGET_MPY || TARGET_MUL64_SET || TARGET_MULMAC_32BY16_SET) | |
00c072ae CZ |
1602 | /* PLUS_DMPY feature macro. */ |
1603 | #define TARGET_PLUS_DMPY ((arc_mpy_option > 6) && TARGET_HS) | |
1604 | /* PLUS_MACD feature macro. */ | |
1605 | #define TARGET_PLUS_MACD ((arc_mpy_option > 7) && TARGET_HS) | |
1606 | /* PLUS_QMACW feature macro. */ | |
1607 | #define TARGET_PLUS_QMACW ((arc_mpy_option > 8) && TARGET_HS) | |
f50bb868 CZ |
1608 | |
1609 | /* ARC600 and ARC601 feature macro. */ | |
1610 | #define TARGET_ARC600_FAMILY (TARGET_ARC600 || TARGET_ARC601) | |
1611 | /* ARC600, ARC601 and ARC700 feature macro. */ | |
1612 | #define TARGET_ARCOMPACT_FAMILY \ | |
1613 | (TARGET_ARC600 || TARGET_ARC601 || TARGET_ARC700) | |
1614 | /* Loop count register can be read in very next instruction after has | |
1615 | been written to by an ordinary instruction. */ | |
1616 | #define TARGET_LP_WR_INTERLOCK (!TARGET_ARC600_FAMILY) | |
1617 | ||
8f3304d0 CZ |
1618 | /* FPU defines. */ |
1619 | /* Any FPU support. */ | |
c4014855 | 1620 | #define TARGET_HARD_FLOAT ((arc_fpu_build & (FPU_SP | FPU_DP)) != 0) |
8f3304d0 CZ |
1621 | /* Single precision floating point support. */ |
1622 | #define TARGET_FP_SP_BASE ((arc_fpu_build & FPU_SP) != 0) | |
1623 | /* Double precision floating point support. */ | |
1624 | #define TARGET_FP_DP_BASE ((arc_fpu_build & FPU_DP) != 0) | |
1625 | /* Single precision floating point support with fused operation. */ | |
1626 | #define TARGET_FP_SP_FUSED ((arc_fpu_build & FPU_SF) != 0) | |
1627 | /* Double precision floating point support with fused operation. */ | |
1628 | #define TARGET_FP_DP_FUSED ((arc_fpu_build & FPU_DF) != 0) | |
1629 | /* Single precision floating point conversion instruction support. */ | |
1630 | #define TARGET_FP_SP_CONV ((arc_fpu_build & FPU_SC) != 0) | |
1631 | /* Double precision floating point conversion instruction support. */ | |
1632 | #define TARGET_FP_DP_CONV ((arc_fpu_build & FPU_DC) != 0) | |
1633 | /* Single precision floating point SQRT/DIV instruction support. */ | |
1634 | #define TARGET_FP_SP_SQRT ((arc_fpu_build & FPU_SD) != 0) | |
1635 | /* Double precision floating point SQRT/DIV instruction support. */ | |
1636 | #define TARGET_FP_DP_SQRT ((arc_fpu_build & FPU_DD) != 0) | |
1637 | /* Double precision floating point assist instruction support. */ | |
1638 | #define TARGET_FP_DP_AX ((arc_fpu_build & FPX_DP) != 0) | |
c4014855 CZ |
1639 | /* Custom FP instructions used by QuarkSE EM cpu. */ |
1640 | #define TARGET_FPX_QUARK (TARGET_EM && TARGET_SPFP \ | |
1641 | && (arc_fpu_build == FPX_QK)) | |
dd1fd744 VG |
1642 | /* DBNZ support is available for ARCv2 core3 and newer cpus. */ |
1643 | #define TARGET_DBNZ (TARGET_V2 && (arc_tune >= ARC_TUNE_CORE_3)) | |
8f3304d0 | 1644 | |
aac1c11c CZ |
1645 | /* BI/BIH feature macro. */ |
1646 | #define TARGET_BI_BIH (TARGET_BRANCH_INDEX && TARGET_CODE_DENSITY) | |
1647 | ||
1648 | /* The default option for BI/BIH instructions. */ | |
1649 | #define DEFAULT_BRANCH_INDEX 0 | |
1650 | ||
73dac59b CZ |
1651 | #ifndef TARGET_LRA |
1652 | #define TARGET_LRA arc_lra_p() | |
1653 | #endif | |
1654 | ||
526b7aee | 1655 | #endif /* GCC_ARC_H */ |