]>
Commit | Line | Data |
---|---|---|
526b7aee SV |
1 | ; Options for the Synopsys DesignWare ARC port of the compiler |
2 | ; | |
cbe34bb5 | 3 | ; Copyright (C) 2005-2017 Free Software Foundation, Inc. |
526b7aee SV |
4 | ; |
5 | ; This file is part of GCC. | |
6 | ; | |
7 | ; GCC is free software; you can redistribute it and/or modify it under | |
8 | ; the terms of the GNU General Public License as published by the Free | |
9 | ; Software Foundation; either version 3, or (at your option) any later | |
10 | ; version. | |
11 | ; | |
12 | ; GCC is distributed in the hope that it will be useful, but WITHOUT | |
13 | ; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
14 | ; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
15 | ; License for more details. | |
16 | ; | |
17 | ; You should have received a copy of the GNU General Public License | |
18 | ; along with GCC; see the file COPYING3. If not see | |
19 | ; <http://www.gnu.org/licenses/>. | |
20 | ||
21 | HeaderInclude | |
22 | config/arc/arc-opts.h | |
23 | ||
24 | mbig-endian | |
25 | Target Report RejectNegative Mask(BIG_ENDIAN) | |
a7b2e184 | 26 | Compile code for big endian mode. |
526b7aee SV |
27 | |
28 | mlittle-endian | |
29 | Target Report RejectNegative InverseMask(BIG_ENDIAN) | |
a7b2e184 | 30 | Compile code for little endian mode. This is the default. |
526b7aee SV |
31 | |
32 | mno-cond-exec | |
33 | Target Report RejectNegative Mask(NO_COND_EXEC) | |
a7b2e184 | 34 | Disable ARCompact specific pass to generate conditional execution instructions. |
526b7aee | 35 | |
526b7aee SV |
36 | mA6 |
37 | Target Report | |
a7b2e184 | 38 | Generate ARCompact 32-bit code for ARC600 processor. |
526b7aee SV |
39 | |
40 | mARC600 | |
41 | Target Report | |
a7b2e184 | 42 | Same as -mA6. |
526b7aee SV |
43 | |
44 | mARC601 | |
45 | Target Report | |
a7b2e184 | 46 | Generate ARCompact 32-bit code for ARC601 processor. |
526b7aee SV |
47 | |
48 | mA7 | |
49 | Target Report | |
a7b2e184 | 50 | Generate ARCompact 32-bit code for ARC700 processor. |
526b7aee SV |
51 | |
52 | mARC700 | |
53 | Target Report | |
a7b2e184 | 54 | Same as -mA7. |
526b7aee | 55 | |
f50bb868 | 56 | mmpy-option= |
f9ccf899 CZ |
57 | Target RejectNegative Joined Enum(arc_mpy) Var(arc_mpy_option) Init(DEFAULT_arc_mpy_option) |
58 | -mmpy-option=MPY Compile ARCv2 code with a multiplier design option. | |
59 | ||
60 | Enum | |
61 | Name(arc_mpy) Type(int) | |
62 | ||
63 | EnumValue | |
64 | Enum(arc_mpy) String(0) Value(0) | |
65 | ||
66 | EnumValue | |
67 | Enum(arc_mpy) String(none) Value(0) Canonical | |
68 | ||
69 | EnumValue | |
70 | Enum(arc_mpy) String(1) Value(1) | |
71 | ||
72 | EnumValue | |
73 | Enum(arc_mpy) String(w) Value(1) Canonical | |
74 | ||
75 | EnumValue | |
76 | Enum(arc_mpy) String(2) Value(2) | |
77 | ||
78 | EnumValue | |
79 | Enum(arc_mpy) String(mpy) Value(2) | |
80 | ||
81 | EnumValue | |
82 | Enum(arc_mpy) String(wlh1) Value(2) Canonical | |
83 | ||
84 | EnumValue | |
85 | Enum(arc_mpy) String(3) Value(3) | |
86 | ||
87 | EnumValue | |
88 | Enum(arc_mpy) String(wlh2) Value(3) Canonical | |
89 | ||
90 | EnumValue | |
91 | Enum(arc_mpy) String(4) Value(4) | |
92 | ||
93 | EnumValue | |
94 | Enum(arc_mpy) String(wlh3) Value(4) Canonical | |
95 | ||
96 | EnumValue | |
97 | Enum(arc_mpy) String(5) Value(5) | |
98 | ||
99 | EnumValue | |
100 | Enum(arc_mpy) String(wlh4) Value(5) Canonical | |
101 | ||
102 | EnumValue | |
103 | Enum(arc_mpy) String(6) Value(6) | |
104 | ||
105 | EnumValue | |
106 | Enum(arc_mpy) String(wlh5) Value(6) Canonical | |
107 | ||
108 | EnumValue | |
109 | Enum(arc_mpy) String(7) Value(7) | |
110 | ||
111 | EnumValue | |
112 | Enum(arc_mpy) String(plus_dmpy) Value(7) Canonical | |
113 | ||
114 | EnumValue | |
115 | Enum(arc_mpy) String(8) Value(8) | |
116 | ||
117 | EnumValue | |
118 | Enum(arc_mpy) String(plus_macd) Value(8) Canonical | |
119 | ||
120 | EnumValue | |
121 | Enum(arc_mpy) String(9) Value(9) | |
122 | ||
123 | EnumValue | |
124 | Enum(arc_mpy) String(plus_qmacw) Value(9) Canonical | |
f50bb868 CZ |
125 | |
126 | mdiv-rem | |
127 | Target Report Mask(DIVREM) | |
80646541 | 128 | Enable DIV-REM instructions for ARCv2. |
f50bb868 CZ |
129 | |
130 | mcode-density | |
131 | Target Report Mask(CODE_DENSITY) | |
80646541 | 132 | Enable code density instructions for ARCv2. |
f50bb868 | 133 | |
526b7aee SV |
134 | mmixed-code |
135 | Target Report Mask(MIXED_CODE_SET) | |
a7b2e184 | 136 | Tweak register allocation to help 16-bit instruction generation. |
526b7aee | 137 | ; originally this was: |
fb155425 | 138 | ;Generate ARCompact 16-bit instructions intermixed with 32-bit instructions |
526b7aee SV |
139 | ; but we do that without -mmixed-code, too, it's just a different instruction |
140 | ; count / size tradeoff. | |
141 | ||
142 | ; We use an explict definition for the negative form because that is the | |
143 | ; actually interesting option, and we want that to have its own comment. | |
144 | mvolatile-cache | |
145 | Target Report RejectNegative Mask(VOLATILE_CACHE_SET) | |
a7b2e184 | 146 | Use ordinarily cached memory accesses for volatile references. |
526b7aee SV |
147 | |
148 | mno-volatile-cache | |
149 | Target Report RejectNegative InverseMask(VOLATILE_CACHE_SET) | |
a7b2e184 | 150 | Enable cache bypass for volatile references. |
526b7aee SV |
151 | |
152 | mbarrel-shifter | |
153 | Target Report Mask(BARREL_SHIFTER) | |
a7b2e184 | 154 | Generate instructions supported by barrel shifter. |
526b7aee SV |
155 | |
156 | mnorm | |
157 | Target Report Mask(NORM_SET) | |
a7b2e184 | 158 | Generate norm instruction. |
526b7aee SV |
159 | |
160 | mswap | |
161 | Target Report Mask(SWAP_SET) | |
a7b2e184 | 162 | Generate swap instruction. |
526b7aee SV |
163 | |
164 | mmul64 | |
165 | Target Report Mask(MUL64_SET) | |
a7b2e184 | 166 | Generate mul64 and mulu64 instructions. |
526b7aee SV |
167 | |
168 | mno-mpy | |
f9ccf899 | 169 | Target Report Mask(NOMPY_SET) Warn(%qs is deprecated) |
a7b2e184 | 170 | Do not generate mpy instructions for ARC700. |
526b7aee SV |
171 | |
172 | mea | |
173 | Target Report Mask(EA_SET) | |
a7b2e184 | 174 | Generate Extended arithmetic instructions. Currently only divaw, adds, subs and sat16 are supported. |
526b7aee SV |
175 | |
176 | msoft-float | |
177 | Target Report Mask(0) | |
a7b2e184 | 178 | Dummy flag. This is the default unless FPX switches are provided explicitly. |
526b7aee SV |
179 | |
180 | mlong-calls | |
181 | Target Report Mask(LONG_CALLS_SET) | |
a7b2e184 | 182 | Generate call insns as register indirect calls. |
526b7aee SV |
183 | |
184 | mno-brcc | |
185 | Target Report Mask(NO_BRCC_SET) | |
186 | Do no generate BRcc instructions in arc_reorg. | |
187 | ||
188 | msdata | |
189 | Target Report InverseMask(NO_SDATA_SET) | |
190 | Generate sdata references. This is the default, unless you compile for PIC. | |
191 | ||
192 | mno-millicode | |
193 | Target Report Mask(NO_MILLICODE_THUNK_SET) | |
a7b2e184 | 194 | Do not generate millicode thunks (needed only with -Os). |
526b7aee SV |
195 | |
196 | mspfp | |
197 | Target Report Mask(SPFP_COMPACT_SET) | |
198 | FPX: Generate Single Precision FPX (compact) instructions. | |
199 | ||
200 | mspfp-compact | |
201 | Target Report Mask(SPFP_COMPACT_SET) MaskExists | |
202 | FPX: Generate Single Precision FPX (compact) instructions. | |
203 | ||
204 | mspfp-fast | |
205 | Target Report Mask(SPFP_FAST_SET) | |
206 | FPX: Generate Single Precision FPX (fast) instructions. | |
207 | ||
208 | margonaut | |
209 | Target Report Mask(ARGONAUT_SET) | |
210 | FPX: Enable Argonaut ARC CPU Double Precision Floating Point extensions. | |
211 | ||
212 | mdpfp | |
213 | Target Report Mask(DPFP_COMPACT_SET) | |
214 | FPX: Generate Double Precision FPX (compact) instructions. | |
215 | ||
216 | mdpfp-compact | |
217 | Target Report Mask(DPFP_COMPACT_SET) MaskExists | |
218 | FPX: Generate Double Precision FPX (compact) instructions. | |
219 | ||
220 | mdpfp-fast | |
221 | Target Report Mask(DPFP_FAST_SET) | |
222 | FPX: Generate Double Precision FPX (fast) instructions. | |
223 | ||
224 | mno-dpfp-lrsr | |
225 | Target Report Mask(DPFP_DISABLE_LRSR) | |
226 | Disable LR and SR instructions from using FPX extension aux registers. | |
227 | ||
228 | msimd | |
229 | Target Report Mask(SIMD_SET) | |
230 | Enable generation of ARC SIMD instructions via target-specific builtins. | |
231 | ||
232 | mcpu= | |
233 | Target RejectNegative Joined Var(arc_cpu) Enum(processor_type) Init(PROCESSOR_NONE) | |
a7b2e184 | 234 | -mcpu=CPU Compile code for ARC variant CPU. |
526b7aee | 235 | |
526b7aee SV |
236 | msize-level= |
237 | Target RejectNegative Joined UInteger Var(arc_size_opt_level) Init(-1) | |
a7b2e184 | 238 | size optimization level: 0:none 1:opportunistic 2: regalloc 3:drop align, -Os. |
526b7aee SV |
239 | |
240 | misize | |
7a3d0a39 | 241 | Target Report PchIgnore Var(TARGET_DUMPISIZE) |
a7b2e184 | 242 | Annotate assembler instructions with estimated addresses. |
526b7aee SV |
243 | |
244 | mmultcost= | |
245 | Target RejectNegative Joined UInteger Var(arc_multcost) Init(-1) | |
246 | Cost to assume for a multiply instruction, with 4 being equal to a normal insn. | |
247 | ||
248 | mtune=ARC600 | |
249 | Target RejectNegative Var(arc_tune, TUNE_ARC600) | |
250 | Tune for ARC600 cpu. | |
251 | ||
252 | mtune=ARC601 | |
253 | Target RejectNegative Var(arc_tune, TUNE_ARC600) | |
254 | Tune for ARC601 cpu. | |
255 | ||
256 | mtune=ARC700 | |
257 | Target RejectNegative Var(arc_tune, TUNE_ARC700_4_2_STD) | |
258 | Tune for ARC700 R4.2 Cpu with standard multiplier block. | |
259 | ||
260 | mtune=ARC700-xmac | |
261 | Target RejectNegative Var(arc_tune, TUNE_ARC700_4_2_XMAC) | |
262 | Tune for ARC700 R4.2 Cpu with XMAC block. | |
263 | ||
264 | mtune=ARC725D | |
265 | Target RejectNegative Var(arc_tune, TUNE_ARC700_4_2_XMAC) | |
266 | Tune for ARC700 R4.2 Cpu with XMAC block. | |
267 | ||
268 | mtune=ARC750D | |
269 | Target RejectNegative Var(arc_tune, TUNE_ARC700_4_2_XMAC) | |
270 | Tune for ARC700 R4.2 Cpu with XMAC block. | |
271 | ||
272 | mindexed-loads | |
f26322a6 | 273 | Target Var(TARGET_INDEXED_LOADS) Init(TARGET_INDEXED_LOADS_DEFAULT) |
a7b2e184 | 274 | Enable the use of indexed loads. |
526b7aee SV |
275 | |
276 | mauto-modify-reg | |
f26322a6 | 277 | Target Var(TARGET_AUTO_MODIFY_REG) Init(TARGET_AUTO_MODIFY_REG_DEFAULT) |
526b7aee SV |
278 | Enable the use of pre/post modify with register displacement. |
279 | ||
280 | mmul32x16 | |
281 | Target Report Mask(MULMAC_32BY16_SET) | |
a7b2e184 | 282 | Generate 32x16 multiply and mac instructions. |
526b7aee SV |
283 | |
284 | ; the initializer is supposed to be: Init(REG_BR_PROB_BASE/2) , | |
285 | ; alas, basic-block.h is not included in options.c . | |
286 | munalign-prob-threshold= | |
287 | Target RejectNegative Joined UInteger Var(arc_unalign_prob_threshold) Init(10000/2) | |
a7b2e184 | 288 | Set probability threshold for unaligning branches. |
526b7aee SV |
289 | |
290 | mmedium-calls | |
291 | Target Var(TARGET_MEDIUM_CALLS) Init(TARGET_MMEDIUM_CALLS_DEFAULT) | |
292 | Don't use less than 25 bit addressing range for calls. | |
293 | ||
294 | mannotate-align | |
295 | Target Var(TARGET_ANNOTATE_ALIGN) | |
296 | Explain what alignment considerations lead to the decision to make an insn short or long. | |
297 | ||
298 | malign-call | |
299 | Target Var(TARGET_ALIGN_CALL) | |
300 | Do alignment optimizations for call instructions. | |
301 | ||
302 | mRcq | |
303 | Target Var(TARGET_Rcq) | |
304 | Enable Rcq constraint handling - most short code generation depends on this. | |
305 | ||
306 | mRcw | |
307 | Target Var(TARGET_Rcw) | |
308 | Enable Rcw constraint handling - ccfsm condexec mostly depends on this. | |
309 | ||
310 | mearly-cbranchsi | |
311 | Target Var(TARGET_EARLY_CBRANCHSI) | |
a7b2e184 | 312 | Enable pre-reload use of cbranchsi pattern. |
526b7aee SV |
313 | |
314 | mbbit-peephole | |
315 | Target Var(TARGET_BBIT_PEEPHOLE) | |
a7b2e184 | 316 | Enable bbit peephole2. |
526b7aee SV |
317 | |
318 | mcase-vector-pcrel | |
319 | Target Var(TARGET_CASE_VECTOR_PC_RELATIVE) | |
320 | Use pc-relative switch case tables - this enables case table shortening. | |
321 | ||
322 | mcompact-casesi | |
323 | Target Var(TARGET_COMPACT_CASESI) | |
a7b2e184 | 324 | Enable compact casesi pattern. |
526b7aee SV |
325 | |
326 | mq-class | |
327 | Target Var(TARGET_Q_CLASS) | |
328 | Enable 'q' instruction alternatives. | |
329 | ||
330 | mexpand-adddi | |
331 | Target Var(TARGET_EXPAND_ADDDI) | |
332 | Expand adddi3 and subdi3 at rtl generation time into add.f / adc etc. | |
333 | ||
334 | ||
335 | ; Flags used by the assembler, but for which we define preprocessor | |
336 | ; macro symbols as well. | |
337 | mcrc | |
f9ccf899 | 338 | Target Report Warn(%qs is deprecated) |
a7b2e184 | 339 | Enable variable polynomial CRC extension. |
526b7aee SV |
340 | |
341 | mdsp-packa | |
f9ccf899 | 342 | Target Report Warn(%qs is deprecated) |
a7b2e184 | 343 | Enable DSP 3.1 Pack A extensions. |
526b7aee SV |
344 | |
345 | mdvbf | |
f9ccf899 | 346 | Target Report Warn(%qs is deprecated) |
a7b2e184 | 347 | Enable dual viterbi butterfly extension. |
526b7aee SV |
348 | |
349 | mmac-d16 | |
f9ccf899 | 350 | Target Report Undocumented Warn(%qs is deprecated) |
526b7aee SV |
351 | |
352 | mmac-24 | |
f9ccf899 | 353 | Target Report Undocumented Warn(%qs is deprecated) |
526b7aee SV |
354 | |
355 | mtelephony | |
f9ccf899 | 356 | Target Report RejectNegative Warn(%qs is deprecated) |
a7b2e184 | 357 | Enable Dual and Single Operand Instructions for Telephony. |
526b7aee SV |
358 | |
359 | mxy | |
360 | Target Report | |
a7b2e184 | 361 | Enable XY Memory extension (DSP version 3). |
526b7aee SV |
362 | |
363 | ; ARC700 4.10 extension instructions | |
364 | mlock | |
365 | Target Report | |
a7b2e184 | 366 | Enable Locked Load/Store Conditional extension. |
526b7aee SV |
367 | |
368 | mswape | |
369 | Target Report | |
a7b2e184 | 370 | Enable swap byte ordering extension instruction. |
526b7aee SV |
371 | |
372 | mrtsc | |
f9ccf899 | 373 | Target Report Warn(%qs is deprecated) |
a7b2e184 | 374 | Enable 64-bit Time-Stamp Counter extension instruction. |
526b7aee | 375 | |
526b7aee SV |
376 | EB |
377 | Target | |
378 | Pass -EB option through to linker. | |
379 | ||
380 | EL | |
381 | Target | |
382 | Pass -EL option through to linker. | |
383 | ||
384 | marclinux | |
61e72afb | 385 | Target |
526b7aee SV |
386 | Pass -marclinux option through to linker. |
387 | ||
388 | marclinux_prof | |
61e72afb | 389 | Target |
526b7aee SV |
390 | Pass -marclinux_prof option through to linker. |
391 | ||
392 | ;; lra is still unproven for ARC, so allow to fall back to reload with -mno-lra. | |
393 | ;Target InverseMask(NO_LRA) | |
526b7aee SV |
394 | ; lra still won't allow to configure libgcc; see PR rtl-optimization/55464. |
395 | ; so don't enable by default. | |
e5bd20a4 | 396 | mlra |
526b7aee | 397 | Target Mask(LRA) |
a7b2e184 | 398 | Enable lra. |
526b7aee SV |
399 | |
400 | mlra-priority-none | |
401 | Target RejectNegative Var(arc_lra_priority_tag, ARC_LRA_PRIORITY_NONE) | |
a7b2e184 | 402 | Don't indicate any priority with TARGET_REGISTER_PRIORITY. |
526b7aee SV |
403 | |
404 | mlra-priority-compact | |
405 | Target RejectNegative Var(arc_lra_prioritytag, ARC_LRA_PRIORITY_COMPACT) | |
a7b2e184 | 406 | Indicate priority for r0..r3 / r12..r15 with TARGET_REGISTER_PRIORITY. |
526b7aee SV |
407 | |
408 | mlra-priority-noncompact | |
409 | Target RejectNegative Var(arc_lra_prioritytag, ARC_LRA_PRIORITY_NONCOMPACT) | |
a7b2e184 | 410 | Reduce priority for r0..r3 / r12..r15 with TARGET_REGISTER_PRIORITY. |
526b7aee | 411 | |
526b7aee SV |
412 | ; backward-compatibility aliases, translated by DRIVER_SELF_SPECS |
413 | ||
414 | mEA | |
415 | Target | |
416 | ||
417 | multcost= | |
418 | Target RejectNegative Joined | |
419 | ||
b8a64b7f CZ |
420 | matomic |
421 | Target Report Mask(ATOMIC) | |
422 | Enable atomic instructions. | |
d34a0fdc CZ |
423 | |
424 | mll64 | |
425 | Target Report Mask(LL64) | |
426 | Enable double load/store instructions for ARC HS. | |
8f3304d0 CZ |
427 | |
428 | mfpu= | |
f9ccf899 | 429 | Target RejectNegative Joined Enum(arc_fpu) Var(arc_fpu_build) Init(DEFAULT_arc_fpu_build) |
8f3304d0 CZ |
430 | Specify the name of the target floating point configuration. |
431 | ||
432 | Enum | |
433 | Name(arc_fpu) Type(int) | |
434 | ||
435 | EnumValue | |
f9ccf899 | 436 | Enum(arc_fpu) String(fpus) Value(FPU_FPUS) |
8f3304d0 CZ |
437 | |
438 | EnumValue | |
f9ccf899 | 439 | Enum(arc_fpu) String(fpud) Value(FPU_FPUD) |
8f3304d0 CZ |
440 | |
441 | EnumValue | |
f9ccf899 | 442 | Enum(arc_fpu) String(fpuda) Value(FPU_FPUDA) |
8f3304d0 CZ |
443 | |
444 | EnumValue | |
f9ccf899 | 445 | Enum(arc_fpu) String(fpuda_div) Value(FPU_FPUDA_DIV) |
8f3304d0 CZ |
446 | |
447 | EnumValue | |
f9ccf899 | 448 | Enum(arc_fpu) String(fpuda_fma) Value(FPU_FPUDA_FMA) |
8f3304d0 CZ |
449 | |
450 | EnumValue | |
f9ccf899 | 451 | Enum(arc_fpu) String(fpuda_all) Value(FPU_FPUDA_ALL) |
8f3304d0 CZ |
452 | |
453 | EnumValue | |
f9ccf899 | 454 | Enum(arc_fpu) String(fpus_div) Value(FPU_FPUS_DIV) |
8f3304d0 CZ |
455 | |
456 | EnumValue | |
f9ccf899 | 457 | Enum(arc_fpu) String(fpud_div) Value(FPU_FPUD_DIV) |
8f3304d0 CZ |
458 | |
459 | EnumValue | |
f9ccf899 | 460 | Enum(arc_fpu) String(fpus_fma) Value(FPU_FPUS_FMA) |
8f3304d0 CZ |
461 | |
462 | EnumValue | |
f9ccf899 | 463 | Enum(arc_fpu) String(fpud_fma) Value(FPU_FPUD_FMA) |
8f3304d0 CZ |
464 | |
465 | EnumValue | |
f9ccf899 | 466 | Enum(arc_fpu) String(fpus_all) Value(FPU_FPUS_ALL) |
8f3304d0 CZ |
467 | |
468 | EnumValue | |
f9ccf899 | 469 | Enum(arc_fpu) String(fpud_all) Value(FPU_FPUD_ALL) |
28633bbd CZ |
470 | |
471 | mtp-regno= | |
81b98ef7 | 472 | Target RejectNegative Joined UInteger Var(arc_tp_regno) Init(TARGET_ARC_TP_REGNO_DEFAULT) |
08f599e8 | 473 | Specify thread pointer register number. |
28633bbd CZ |
474 | |
475 | mtp-regno=none | |
476 | Target RejectNegative Var(arc_tp_regno,-1) | |
4d03dc2f | 477 | |
ceaaa9fe JR |
478 | mbitops |
479 | Target Report Var(TARGET_NPS_BITOPS) Init(TARGET_NPS_BITOPS_DEFAULT) | |
480 | Enable use of NPS400 bit operations. | |
481 | ||
4d03dc2f JR |
482 | mcmem |
483 | Target Report Var(TARGET_NPS_CMEM) Init(TARGET_NPS_CMEM_DEFAULT) | |
484 | Enable use of NPS400 xld/xst extension. | |
485 | ||
486 | munaligned-access | |
487 | Target Report Var(unaligned_access) Init(UNALIGNED_ACCESS_DEFAULT) | |
488 | Enable unaligned word and halfword accesses to packed data. | |
41453183 CZ |
489 | |
490 | mirq-ctrl-saved= | |
491 | Target RejectNegative Joined Var(arc_deferred_options) Defer | |
492 | Specifies the registers that the processor saves on an interrupt entry and exit. | |
c7314bc1 CZ |
493 | |
494 | mrgf-banked-regs= | |
495 | Target RejectNegative Joined Var(arc_deferred_options) Defer | |
496 | Specifies the number of registers replicated in second register bank on entry to fast interrupt. |