[thirdparty/gcc.git] / gcc / config / arc / constraints.md

;; Constraint definitions for Synopsys DesignWare ARC.
;; Copyright (C) 2007-2015 Free Software Foundation, Inc.
;;
;; This file is part of GCC.
;;
;; GCC is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 3, or (at your option)
;; any later version.
;;
;; GCC is distributed in the hope that it will be useful,
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
;; GNU General Public License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3.  If not see
;; <http://www.gnu.org/licenses/>.

;; Register constraints

; Most instructions accept arbitrary core registers for their inputs, even
; if the core register in question cannot be written to, like the multiply
; result registers of ARC600.
; First, define a class for core registers that can be read cheaply.  This
; is most or all core registers for ARC600, but only r0-r31 for ARC700
(define_register_constraint "c" "CHEAP_CORE_REGS"
  "core register @code{r0}-@code{r31}, @code{ap},@code{pcl}")

; All core regs - e.g. for when we must have a way to reload a register.
(define_register_constraint "Rac" "ALL_CORE_REGS"
  "core register @code{r0}-@code{r60}, @code{ap},@code{pcl}")

; Some core registers (.e.g lp_count) aren't general registers because they
; can't be used as the destination of a multi-cycle operation like
; load and/or multiply, yet they are still writable in the sense that
; register-register moves and single-cycle arithmetic (e.g "add", "and",
; but not "mpy") can write to them.
(define_register_constraint "w" "WRITABLE_CORE_REGS"
  "writable core register: @code{r0}-@code{r31}, @code{r60}, nonfixed core register")

(define_register_constraint "W" "MPY_WRITABLE_CORE_REGS"
  "writable core register except @code{LP_COUNT} (@code{r60}): @code{r0}-@code{r31}, nonfixed core register")

(define_register_constraint "l" "LPCOUNT_REG"
  "@internal
   Loop count register @code{r60}")

(define_register_constraint "x" "R0_REGS"
  "@code{R0} register.")

(define_register_constraint "Rgp" "GP_REG"
  "@internal
   Global Pointer register @code{r26}")

(define_register_constraint "f" "FP_REG"
  "@internal
   Frame Pointer register @code{r27}")

(define_register_constraint "b" "SP_REGS"
  "@internal
   Stack Pointer register @code{r28}")

(define_register_constraint "k" "LINK_REGS"
  "@internal
   Link Registers @code{ilink1}:@code{r29}, @code{ilink2}:@code{r30},
   @code{blink}:@code{r31},")

(define_register_constraint "q" "ARCOMPACT16_REGS"
  "Registers usable in ARCompact 16-bit instructions: @code{r0}-@code{r3},
   @code{r12}-@code{r15}")

(define_register_constraint "e" "AC16_BASE_REGS"
  "Registers usable as base-regs of memory addresses in ARCompact 16-bit memory
   instructions: @code{r0}-@code{r3}, @code{r12}-@code{r15}, @code{sp}")

(define_register_constraint "D" "DOUBLE_REGS"
  "ARC FPX (dpfp) 64-bit registers. @code{D0}, @code{D1}")

(define_register_constraint "d" "SIMD_DMA_CONFIG_REGS"
  "@internal
   ARC SIMD DMA configuration registers @code{di0}-@code{di7},
   @code{do0}-@code{do7}")

(define_register_constraint "v" "SIMD_VR_REGS"
  "ARC SIMD 128-bit registers @code{VR0}-@code{VR23}")

; We could allow call-saved registers for sibling calls if we restored them
; in the delay slot of the call.  However, that would not allow to adjust the
; stack pointer afterwards, so the call-saved register would have to be
; restored from a call-used register that was just loaded with the value
; before.  So sticking to call-used registers for sibcalls will likely
; generate better code overall.
(define_register_constraint "Rsc" "SIBCALL_REGS"
  "@internal
   Sibling call register")

;; Integer constraints

(define_constraint "I"
  "@internal
   A signed 12-bit integer constant."
  (and (match_code "const_int")
       (match_test "SIGNED_INT12 (ival)")))

(define_constraint "K"
  "@internal
   A 3-bit unsigned integer constant"
  (and (match_code "const_int")
       (match_test "UNSIGNED_INT3 (ival)")))

(define_constraint "L"
  "@internal
   A 6-bit unsigned integer constant"
  (and (match_code "const_int")
       (match_test "UNSIGNED_INT6 (ival)")))

(define_constraint "CnL"
  "@internal
   One's complement of a 6-bit unsigned integer constant"
  (and (match_code "const_int")
       (match_test "UNSIGNED_INT6 (~ival)")))

(define_constraint "CmL"
  "@internal
   Two's complement of a 6-bit unsigned integer constant"
  (and (match_code "const_int")
       (match_test "UNSIGNED_INT6 (-ival)")))

(define_constraint "C16"
  "@internal
   A 16-bit signed integer constant"
  (and (match_code "const_int")
       (match_test "SIGNED_INT16 (ival)")))

(define_constraint "M"
  "@internal
   A 5-bit unsigned integer constant"
  (and (match_code "const_int")
       (match_test "UNSIGNED_INT5 (ival)")))

(define_constraint "N"
  "@internal
   Integer constant 1"
  (and (match_code "const_int")
       (match_test "IS_ONE (ival)")))

(define_constraint "O"
  "@internal
   A 7-bit unsigned integer constant"
  (and (match_code "const_int")
       (match_test "UNSIGNED_INT7 (ival)")))

(define_constraint "P"
  "@internal
   An 8-bit unsigned integer constant"
  (and (match_code "const_int")
       (match_test "UNSIGNED_INT8 (ival)")))

(define_constraint "C_0"
  "@internal
   Zero"
  (and (match_code "const_int")
       (match_test "ival == 0")))

(define_constraint "Cn0"
  "@internal
   Negative or zero"
  (and (match_code "const_int")
       (match_test "ival <= 0")))

(define_constraint "Cca"
  "@internal
   Conditional or three-address add / sub constant"
  (and (match_code "const_int")
       (match_test "ival == (HOST_WIDE_INT)(HOST_WIDE_INT_M1U << 31)
		    || (ival >= -0x1f8 && ival <= 0x1f8
			&& ((ival >= 0 ? ival : -ival)
			    <= 0x3f * (ival & -ival)))")))

; intersection of "O" and "Cca".
(define_constraint "CL2"
  "@internal
   A 6-bit unsigned integer constant times 2"
  (and (match_code "const_int")
       (match_test "!(ival & ~126)")))

(define_constraint "CM4"
  "@internal
   A 5-bit unsigned integer constant times 4"
  (and (match_code "const_int")
       (match_test "!(ival & ~124)")))

(define_constraint "Csp"
  "@internal
   A valid stack pointer offset for a short add"
  (and (match_code "const_int")
       (match_test "!(ival & ~124) || !(-ival & ~124)")))

(define_constraint "C2a"
  "@internal
   Unconditional two-address add / sub constant"
  (and (match_code "const_int")
       (match_test "ival == (HOST_WIDE_INT) (HOST_WIDE_INT_M1U << 31)
		    || (ival >= -0x4000 && ival <= 0x4000
			&& ((ival >= 0 ? ival : -ival)
			    <= 0x7ff * (ival & -ival)))")))

(define_constraint "C0p"
 "@internal
  power of two"
  (and (match_code "const_int")
       (match_test "IS_POWEROF2_P (ival)")))

(define_constraint "C1p"
 "@internal
  constant such that x+1 is a power of two, and x != 0"
  (and (match_code "const_int")
       (match_test "ival && IS_POWEROF2_P (ival + 1)")))

(define_constraint "C3p"
 "@internal
  constant int used to select xbfu a,b,u6 instruction.  The values accepted are 1 and 2."
  (and (match_code "const_int")
       (match_test "((ival == 1) || (ival == 2))")))

(define_constraint "Ccp"
 "@internal
  constant such that ~x (one's Complement) is a power of two"
  (and (match_code "const_int")
       (match_test "IS_POWEROF2_P (~ival)")))

(define_constraint "Cux"
 "@internal
  constant such that AND gives an unsigned extension"
  (and (match_code "const_int")
       (match_test "ival == 0xff || ival == 0xffff")))

(define_constraint "Crr"
 "@internal
  constant that can be loaded with ror b,u6"
  (and (match_code "const_int")
       (match_test "(ival & ~0x8000001f) == 0 && !arc_ccfsm_cond_exec_p ()")))

;; Floating-point constraints

(define_constraint "G"
  "@internal
   A 32-bit constant double value"
  (and (match_code "const_double")
       (match_test "arc_double_limm_p (op)")))

(define_constraint "H"
  "@internal
   All const_double values (including 64-bit values)"
  (and (match_code "const_double")
       (match_test "1")))

;; Memory constraints
(define_memory_constraint "T"
  "@internal
   A valid memory operand for ARCompact load instructions"
  (and (match_code "mem")
       (match_test "compact_load_memory_operand (op, VOIDmode)")))

(define_memory_constraint "S"
  "@internal
   A valid memory operand for ARCompact store instructions"
  (and (match_code "mem")
       (match_test "compact_store_memory_operand (op, VOIDmode)")))

(define_memory_constraint "Usd"
  "@internal
   A valid _small-data_ memory operand for ARCompact instructions"
  (and (match_code "mem")
       (match_test "compact_sda_memory_operand (op, VOIDmode)")))

(define_memory_constraint "Usc"
  "@internal
   A valid memory operand for storing constants"
  (and (match_code "mem")
       (match_test "!CONSTANT_P (XEXP (op,0))")
;; ??? the assembler rejects stores of immediates to small data.
       (match_test "!compact_sda_memory_operand (op, VOIDmode)")))

(define_memory_constraint "Us<"
  "@internal
   Stack pre-decrement"
  (and (match_code "mem")
       (match_test "GET_CODE (XEXP (op, 0)) == PRE_DEC")
       (match_test "REG_P (XEXP (XEXP (op, 0), 0))")
       (match_test "REGNO (XEXP (XEXP (op, 0), 0)) == SP_REG")))

(define_memory_constraint "Us>"
  "@internal
   Stack post-increment"
  (and (match_code "mem")
       (match_test "GET_CODE (XEXP (op, 0)) == POST_INC")
       (match_test "REG_P (XEXP (XEXP (op, 0), 0))")
       (match_test "REGNO (XEXP (XEXP (op, 0), 0)) == SP_REG")))

;; General constraints

(define_constraint "Cbr"
  "Branch destination"
  (ior (and (match_code "symbol_ref")
	    (match_test "!arc_is_longcall_p (op)"))
       (match_code "label_ref")))

(define_constraint "Cbp"
  "predicable branch/call destination"
  (ior (and (match_code "symbol_ref")
	    (match_test "arc_is_shortcall_p (op)"))
       (match_code "label_ref")))

(define_constraint "Cpc"
  "pc-relative constant"
  (match_test "arc_legitimate_pc_offset_p (op)"))

(define_constraint "Clb"
  "label"
  (and (match_code "label_ref")
       (match_test "arc_text_label (as_a <rtx_insn *> (XEXP (op, 0)))")))

(define_constraint "Cal"
  "constant for arithmetic/logical operations"
  (match_test "immediate_operand (op, VOIDmode) && !arc_legitimate_pc_offset_p (op)"))

(define_constraint "C32"
  "32 bit constant for arithmetic/logical operations"
  (match_test "immediate_operand (op, VOIDmode)
	       && !arc_legitimate_pc_offset_p (op)
	       && !satisfies_constraint_I (op)"))

; Note that the 'cryptic' register constraints will not make reload use the
; associated class to reload into, but this will not penalize reloading of any
; other operands, or using an alternate part of the same alternative.

; Rcq is different in three important ways from a register class constraint:
; - It does not imply a register class, hence reload will not use it to drive
;   reloads.
; - It matches even when there is no register class to describe its accepted
;   set; not having such a set again lessens the impact on register allocation.
; - It won't match when the instruction is conditionalized by the ccfsm.
(define_constraint "Rcq"
  "@internal
   Cryptic q - for short insn generation while not affecting register allocation
   Registers usable in ARCompact 16-bit instructions: @code{r0}-@code{r3},
   @code{r12}-@code{r15}"
  (and (match_code "reg")
       (match_test "TARGET_Rcq
		    && !arc_ccfsm_cond_exec_p ()
		    && IN_RANGE (REGNO (op) ^ 4, 4, 11)")))

; If we need a reload, we generally want to steer reload to use three-address
; alternatives in preference of two-address alternatives, unless the
; three-address alternative introduces a LIMM that is unnecessary for the
; two-address alternative.
(define_constraint "Rcw"
  "@internal
   Cryptic w - for use in early alternatives with matching constraint"
  (and (match_code "reg")
       (match_test
	"TARGET_Rcw
	 && REGNO (op) < FIRST_PSEUDO_REGISTER
	 && TEST_HARD_REG_BIT (reg_class_contents[WRITABLE_CORE_REGS],
			       REGNO (op))")))

(define_constraint "Rcr"
  "@internal
   Cryptic r - for use in early alternatives with matching constraint"
  (and (match_code "reg")
       (match_test
	"TARGET_Rcw
	 && REGNO (op) < FIRST_PSEUDO_REGISTER
	 && TEST_HARD_REG_BIT (reg_class_contents[GENERAL_REGS],
			       REGNO (op))")))

(define_constraint "Rcb"
  "@internal
   Stack Pointer register @code{r28} - do not reload into its class"
  (and (match_code "reg")
       (match_test "REGNO (op) == 28")))

(define_constraint "Rck"
  "@internal
   blink (usful for push_s / pop_s)"
  (and (match_code "reg")
       (match_test "REGNO (op) == 31")))

(define_constraint "Rs5"
  "@internal
   sibcall register - only allow one of the five available 16 bit isnsn.
   Registers usable in ARCompact 16-bit instructions: @code{r0}-@code{r3},
   @code{r12}"
  (and (match_code "reg")
       (match_test "!arc_ccfsm_cond_exec_p ()")
       (ior (match_test "(unsigned) REGNO (op) <= 3")
	    (match_test "REGNO (op) == 12"))))

(define_constraint "Rcc"
  "@internal
  Condition Codes"
  (and (match_code "reg") (match_test "cc_register (op, VOIDmode)")))


(define_constraint "Q"
  "@internal
   Integer constant zero"
  (and (match_code "const_int")
       (match_test "IS_ZERO (ival)")))

(define_constraint "Cm2"
  "@internal
   A signed 9-bit integer constant."
  (and (match_code "const_int")
       (match_test "(ival >= -256) && (ival <=255)")))

(define_constraint "C62"
  "@internal
   An unsigned 6-bit integer constant, up to 62."
  (and (match_code "const_int")
       (match_test "UNSIGNED_INT6 (ival - 1)")))
Commit	Line	Data
526b7aee	1	;; Constraint definitions for Synopsys DesignWare ARC.
5624e564	2	;; Copyright (C) 2007-2015 Free Software Foundation, Inc.
526b7aee SV	3	;;
	4	;; This file is part of GCC.
	5	;;
	6	;; GCC is free software; you can redistribute it and/or modify
	7	;; it under the terms of the GNU General Public License as published by
	8	;; the Free Software Foundation; either version 3, or (at your option)
	9	;; any later version.
	10	;;
	11	;; GCC is distributed in the hope that it will be useful,
	12	;; but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	;; GNU General Public License for more details.
	15	;;
	16	;; You should have received a copy of the GNU General Public License
	17	;; along with GCC; see the file COPYING3. If not see
	18	;; <http://www.gnu.org/licenses/>.
	19
	20	;; Register constraints
	21
	22	; Most instructions accept arbitrary core registers for their inputs, even
	23	; if the core register in question cannot be written to, like the multiply
fb155425	24	; result registers of ARC600.
526b7aee SV	25	; First, define a class for core registers that can be read cheaply. This
	26	; is most or all core registers for ARC600, but only r0-r31 for ARC700
	27	(define_register_constraint "c" "CHEAP_CORE_REGS"
	28	"core register @code{r0}-@code{r31}, @code{ap},@code{pcl}")
	29
	30	; All core regs - e.g. for when we must have a way to reload a register.
	31	(define_register_constraint "Rac" "ALL_CORE_REGS"
	32	"core register @code{r0}-@code{r60}, @code{ap},@code{pcl}")
	33
	34	; Some core registers (.e.g lp_count) aren't general registers because they
	35	; can't be used as the destination of a multi-cycle operation like
	36	; load and/or multiply, yet they are still writable in the sense that
	37	; register-register moves and single-cycle arithmetic (e.g "add", "and",
	38	; but not "mpy") can write to them.
	39	(define_register_constraint "w" "WRITABLE_CORE_REGS"
	40	"writable core register: @code{r0}-@code{r31}, @code{r60}, nonfixed core register")
	41
	42	(define_register_constraint "W" "MPY_WRITABLE_CORE_REGS"
	43	"writable core register except @code{LP_COUNT} (@code{r60}): @code{r0}-@code{r31}, nonfixed core register")
	44
	45	(define_register_constraint "l" "LPCOUNT_REG"
	46	"@internal
	47	Loop count register @code{r60}")
	48
	49	(define_register_constraint "x" "R0_REGS"
	50	"@code{R0} register.")
	51
	52	(define_register_constraint "Rgp" "GP_REG"
	53	"@internal
	54	Global Pointer register @code{r26}")
	55
	56	(define_register_constraint "f" "FP_REG"
	57	"@internal
	58	Frame Pointer register @code{r27}")
	59
	60	(define_register_constraint "b" "SP_REGS"
	61	"@internal
	62	Stack Pointer register @code{r28}")
	63
	64	(define_register_constraint "k" "LINK_REGS"
	65	"@internal
	66	Link Registers @code{ilink1}:@code{r29}, @code{ilink2}:@code{r30},
	67	@code{blink}:@code{r31},")
	68
	69	(define_register_constraint "q" "ARCOMPACT16_REGS"
	70	"Registers usable in ARCompact 16-bit instructions: @code{r0}-@code{r3},
	71	@code{r12}-@code{r15}")
	72
	73	(define_register_constraint "e" "AC16_BASE_REGS"
	74	"Registers usable as base-regs of memory addresses in ARCompact 16-bit memory
	75	instructions: @code{r0}-@code{r3}, @code{r12}-@code{r15}, @code{sp}")
	76
	77	(define_register_constraint "D" "DOUBLE_REGS"
	78	"ARC FPX (dpfp) 64-bit registers. @code{D0}, @code{D1}")
	79
	80	(define_register_constraint "d" "SIMD_DMA_CONFIG_REGS"
	81	"@internal
	82	ARC SIMD DMA configuration registers @code{di0}-@code{di7},
	83	@code{do0}-@code{do7}")
	84
	85	(define_register_constraint "v" "SIMD_VR_REGS"
	86	"ARC SIMD 128-bit registers @code{VR0}-@code{VR23}")
	87
	88	; We could allow call-saved registers for sibling calls if we restored them
89	; in the delay slot of the call. However, that would not allow to adjust the
90	; stack pointer afterwards, so the call-saved register would have to be
91	; restored from a call-used register that was just loaded with the value
92	; before. So sticking to call-used registers for sibcalls will likely
93	; generate better code overall.
94	(define_register_constraint "Rsc" "SIBCALL_REGS"
95	"@internal
96	Sibling call register")
97
98	;; Integer constraints
99
100	(define_constraint "I"
101	"@internal
102	A signed 12-bit integer constant."
103	(and (match_code "const_int")
104	(match_test "SIGNED_INT12 (ival)")))
105
106	(define_constraint "K"
107	"@internal
108	A 3-bit unsigned integer constant"
109	(and (match_code "const_int")
110	(match_test "UNSIGNED_INT3 (ival)")))
111
112	(define_constraint "L"
113	"@internal
114	A 6-bit unsigned integer constant"
115	(and (match_code "const_int")
116	(match_test "UNSIGNED_INT6 (ival)")))
117
118	(define_constraint "CnL"
119	"@internal
120	One's complement of a 6-bit unsigned integer constant"
121	(and (match_code "const_int")
122	(match_test "UNSIGNED_INT6 (~ival)")))
123
124	(define_constraint "CmL"
125	"@internal
126	Two's complement of a 6-bit unsigned integer constant"
127	(and (match_code "const_int")
128	(match_test "UNSIGNED_INT6 (-ival)")))
129
f50bb868 CZ	130	(define_constraint "C16"
	131	"@internal
	132	A 16-bit signed integer constant"
	133	(and (match_code "const_int")
	134	(match_test "SIGNED_INT16 (ival)")))
	135
526b7aee SV	136	(define_constraint "M"
	137	"@internal
	138	A 5-bit unsigned integer constant"
	139	(and (match_code "const_int")
	140	(match_test "UNSIGNED_INT5 (ival)")))
	141
	142	(define_constraint "N"
	143	"@internal
	144	Integer constant 1"
	145	(and (match_code "const_int")
	146	(match_test "IS_ONE (ival)")))
	147
	148	(define_constraint "O"
	149	"@internal
	150	A 7-bit unsigned integer constant"
	151	(and (match_code "const_int")
	152	(match_test "UNSIGNED_INT7 (ival)")))
	153
	154	(define_constraint "P"
	155	"@internal
	156	An 8-bit unsigned integer constant"
	157	(and (match_code "const_int")
	158	(match_test "UNSIGNED_INT8 (ival)")))
	159
	160	(define_constraint "C_0"
	161	"@internal
	162	Zero"
	163	(and (match_code "const_int")
	164	(match_test "ival == 0")))
	165
	166	(define_constraint "Cn0"
	167	"@internal
	168	Negative or zero"
	169	(and (match_code "const_int")
	170	(match_test "ival <= 0")))
	171
	172	(define_constraint "Cca"
	173	"@internal
	174	Conditional or three-address add / sub constant"
	175	(and (match_code "const_int")
c419f71c	176	(match_test "ival == (HOST_WIDE_INT)(HOST_WIDE_INT_M1U << 31)
526b7aee SV	177	\|\| (ival >= -0x1f8 && ival <= 0x1f8
	178	&& ((ival >= 0 ? ival : -ival)
	179	<= 0x3f * (ival & -ival)))")))
	180
	181	; intersection of "O" and "Cca".
	182	(define_constraint "CL2"
	183	"@internal
	184	A 6-bit unsigned integer constant times 2"
	185	(and (match_code "const_int")
	186	(match_test "!(ival & ~126)")))
	187
	188	(define_constraint "CM4"
	189	"@internal
	190	A 5-bit unsigned integer constant times 4"
	191	(and (match_code "const_int")
	192	(match_test "!(ival & ~124)")))
	193
	194	(define_constraint "Csp"
	195	"@internal
	196	A valid stack pointer offset for a short add"
	197	(and (match_code "const_int")
	198	(match_test "!(ival & ~124) \|\| !(-ival & ~124)")))
	199
	200	(define_constraint "C2a"
	201	"@internal
	202	Unconditional two-address add / sub constant"
	203	(and (match_code "const_int")
4e671509	204	(match_test "ival == (HOST_WIDE_INT) (HOST_WIDE_INT_M1U << 31)
526b7aee SV	205	\|\| (ival >= -0x4000 && ival <= 0x4000
	206	&& ((ival >= 0 ? ival : -ival)
	207	<= 0x7ff * (ival & -ival)))")))
	208
	209	(define_constraint "C0p"
	210	"@internal
	211	power of two"
	212	(and (match_code "const_int")
	213	(match_test "IS_POWEROF2_P (ival)")))
	214
	215	(define_constraint "C1p"
	216	"@internal
	217	constant such that x+1 is a power of two, and x != 0"
	218	(and (match_code "const_int")
	219	(match_test "ival && IS_POWEROF2_P (ival + 1)")))
	220
f50bb868 CZ	221	(define_constraint "C3p"
	222	"@internal
	223	constant int used to select xbfu a,b,u6 instruction. The values accepted are 1 and 2."
	224	(and (match_code "const_int")
	225	(match_test "((ival == 1) \|\| (ival == 2))")))
	226
526b7aee SV	227	(define_constraint "Ccp"
	228	"@internal
	229	constant such that ~x (one's Complement) is a power of two"
	230	(and (match_code "const_int")
	231	(match_test "IS_POWEROF2_P (~ival)")))
	232
	233	(define_constraint "Cux"
	234	"@internal
	235	constant such that AND gives an unsigned extension"
	236	(and (match_code "const_int")
	237	(match_test "ival == 0xff \|\| ival == 0xffff")))
	238
	239	(define_constraint "Crr"
	240	"@internal
	241	constant that can be loaded with ror b,u6"
	242	(and (match_code "const_int")
	243	(match_test "(ival & ~0x8000001f) == 0 && !arc_ccfsm_cond_exec_p ()")))
	244
	245	;; Floating-point constraints
	246
	247	(define_constraint "G"
	248	"@internal
	249	A 32-bit constant double value"
	250	(and (match_code "const_double")
	251	(match_test "arc_double_limm_p (op)")))
	252
	253	(define_constraint "H"
	254	"@internal
	255	All const_double values (including 64-bit values)"
	256	(and (match_code "const_double")
	257	(match_test "1")))
	258
	259	;; Memory constraints
	260	(define_memory_constraint "T"
	261	"@internal
	262	A valid memory operand for ARCompact load instructions"
	263	(and (match_code "mem")
	264	(match_test "compact_load_memory_operand (op, VOIDmode)")))
	265
	266	(define_memory_constraint "S"
	267	"@internal
	268	A valid memory operand for ARCompact store instructions"
	269	(and (match_code "mem")
	270	(match_test "compact_store_memory_operand (op, VOIDmode)")))
	271
	272	(define_memory_constraint "Usd"
	273	"@internal
	274	A valid _small-data_ memory operand for ARCompact instructions"
	275	(and (match_code "mem")
	276	(match_test "compact_sda_memory_operand (op, VOIDmode)")))
	277
	278	(define_memory_constraint "Usc"
	279	"@internal
	280	A valid memory operand for storing constants"
	281	(and (match_code "mem")
	282	(match_test "!CONSTANT_P (XEXP (op,0))")
	283	;; ??? the assembler rejects stores of immediates to small data.
	284	(match_test "!compact_sda_memory_operand (op, VOIDmode)")))
	285
	286	(define_memory_constraint "Us<"
	287	"@internal
	288	Stack pre-decrement"
	289	(and (match_code "mem")
	290	(match_test "GET_CODE (XEXP (op, 0)) == PRE_DEC")
291	(match_test "REG_P (XEXP (XEXP (op, 0), 0))")
292	(match_test "REGNO (XEXP (XEXP (op, 0), 0)) == SP_REG")))
293
294	(define_memory_constraint "Us>"
295	"@internal
296	Stack post-increment"
297	(and (match_code "mem")
298	(match_test "GET_CODE (XEXP (op, 0)) == POST_INC")
299	(match_test "REG_P (XEXP (XEXP (op, 0), 0))")
300	(match_test "REGNO (XEXP (XEXP (op, 0), 0)) == SP_REG")))
301
302	;; General constraints
303
304	(define_constraint "Cbr"
305	"Branch destination"
306	(ior (and (match_code "symbol_ref")
307	(match_test "!arc_is_longcall_p (op)"))
308	(match_code "label_ref")))
309
310	(define_constraint "Cbp"
311	"predicable branch/call destination"
312	(ior (and (match_code "symbol_ref")
313	(match_test "arc_is_shortcall_p (op)"))
314	(match_code "label_ref")))
315
316	(define_constraint "Cpc"
317	"pc-relative constant"
318	(match_test "arc_legitimate_pc_offset_p (op)"))
319
320	(define_constraint "Clb"
321	"label"
322	(and (match_code "label_ref")
b32d5189	323	(match_test "arc_text_label (as_a <rtx_insn *> (XEXP (op, 0)))")))
526b7aee SV	324
	325	(define_constraint "Cal"
	326	"constant for arithmetic/logical operations"
	327	(match_test "immediate_operand (op, VOIDmode) && !arc_legitimate_pc_offset_p (op)"))
	328
	329	(define_constraint "C32"
	330	"32 bit constant for arithmetic/logical operations"
	331	(match_test "immediate_operand (op, VOIDmode)
	332	&& !arc_legitimate_pc_offset_p (op)
	333	&& !satisfies_constraint_I (op)"))
	334
	335	; Note that the 'cryptic' register constraints will not make reload use the
	336	; associated class to reload into, but this will not penalize reloading of any
	337	; other operands, or using an alternate part of the same alternative.
	338
	339	; Rcq is different in three important ways from a register class constraint:
	340	; - It does not imply a register class, hence reload will not use it to drive
	341	; reloads.
	342	; - It matches even when there is no register class to describe its accepted
	343	; set; not having such a set again lessens the impact on register allocation.
	344	; - It won't match when the instruction is conditionalized by the ccfsm.
	345	(define_constraint "Rcq"
	346	"@internal
	347	Cryptic q - for short insn generation while not affecting register allocation
	348	Registers usable in ARCompact 16-bit instructions: @code{r0}-@code{r3},
	349	@code{r12}-@code{r15}"
8da140e0	350	(and (match_code "reg")
526b7aee SV	351	(match_test "TARGET_Rcq
526b7aee SV	352	&& !arc_ccfsm_cond_exec_p ()
036def0f	353	&& IN_RANGE (REGNO (op) ^ 4, 4, 11)")))
526b7aee SV	354
	355	; If we need a reload, we generally want to steer reload to use three-address
	356	; alternatives in preference of two-address alternatives, unless the
	357	; three-address alternative introduces a LIMM that is unnecessary for the
	358	; two-address alternative.
	359	(define_constraint "Rcw"
	360	"@internal
	361	Cryptic w - for use in early alternatives with matching constraint"
8da140e0	362	(and (match_code "reg")
526b7aee SV	363	(match_test
	364	"TARGET_Rcw
	365	&& REGNO (op) < FIRST_PSEUDO_REGISTER
	366	&& TEST_HARD_REG_BIT (reg_class_contents[WRITABLE_CORE_REGS],
	367	REGNO (op))")))
	368
	369	(define_constraint "Rcr"
	370	"@internal
	371	Cryptic r - for use in early alternatives with matching constraint"
8da140e0	372	(and (match_code "reg")
526b7aee SV	373	(match_test
	374	"TARGET_Rcw
	375	&& REGNO (op) < FIRST_PSEUDO_REGISTER
	376	&& TEST_HARD_REG_BIT (reg_class_contents[GENERAL_REGS],
	377	REGNO (op))")))
	378
	379	(define_constraint "Rcb"
	380	"@internal
	381	Stack Pointer register @code{r28} - do not reload into its class"
8da140e0	382	(and (match_code "reg")
526b7aee SV	383	(match_test "REGNO (op) == 28")))
	384
	385	(define_constraint "Rck"
	386	"@internal
	387	blink (usful for push_s / pop_s)"
8da140e0	388	(and (match_code "reg")
526b7aee SV	389	(match_test "REGNO (op) == 31")))
	390
	391	(define_constraint "Rs5"
	392	"@internal
	393	sibcall register - only allow one of the five available 16 bit isnsn.
	394	Registers usable in ARCompact 16-bit instructions: @code{r0}-@code{r3},
	395	@code{r12}"
8da140e0	396	(and (match_code "reg")
526b7aee SV	397	(match_test "!arc_ccfsm_cond_exec_p ()")
	398	(ior (match_test "(unsigned) REGNO (op) <= 3")
	399	(match_test "REGNO (op) == 12"))))
	400
	401	(define_constraint "Rcc"
	402	"@internal
	403	Condition Codes"
8da140e0	404	(and (match_code "reg") (match_test "cc_register (op, VOIDmode)")))
526b7aee SV	405
	406
	407	(define_constraint "Q"
	408	"@internal
	409	Integer constant zero"
	410	(and (match_code "const_int")
	411	(match_test "IS_ZERO (ival)")))
f50bb868 CZ	412
	413	(define_constraint "Cm2"
	414	"@internal
	415	A signed 9-bit integer constant."
	416	(and (match_code "const_int")
	417	(match_test "(ival >= -256) && (ival <=255)")))
	418
	419	(define_constraint "C62"
	420	"@internal
	421	An unsigned 6-bit integer constant, up to 62."
	422	(and (match_code "const_int")
	423	(match_test "UNSIGNED_INT6 (ival - 1)")))