[thirdparty/gcc.git] / gcc / config / arc / constraints.md

;; Constraint definitions for Synopsys DesignWare ARC.
;; Copyright (C) 2007-2016 Free Software Foundation, Inc.
;;
;; This file is part of GCC.
;;
;; GCC is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 3, or (at your option)
;; any later version.
;;
;; GCC is distributed in the hope that it will be useful,
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
;; GNU General Public License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3.  If not see
;; <http://www.gnu.org/licenses/>.

;; Register constraints

; Most instructions accept arbitrary core registers for their inputs, even
; if the core register in question cannot be written to, like the multiply
; result registers of ARC600.
; First, define a class for core registers that can be read cheaply.  This
; is most or all core registers for ARC600, but only r0-r31 for ARC700
(define_register_constraint "c" "CHEAP_CORE_REGS"
  "core register @code{r0}-@code{r31}, @code{ap},@code{pcl}")

; All core regs - e.g. for when we must have a way to reload a register.
(define_register_constraint "Rac" "ALL_CORE_REGS"
  "core register @code{r0}-@code{r60}, @code{ap},@code{pcl}")

; Some core registers (.e.g lp_count) aren't general registers because they
; can't be used as the destination of a multi-cycle operation like
; load and/or multiply, yet they are still writable in the sense that
; register-register moves and single-cycle arithmetic (e.g "add", "and",
; but not "mpy") can write to them.
(define_register_constraint "w" "WRITABLE_CORE_REGS"
  "writable core register: @code{r0}-@code{r31}, @code{r60}, nonfixed core register")

(define_register_constraint "W" "MPY_WRITABLE_CORE_REGS"
  "writable core register except @code{LP_COUNT} (@code{r60}): @code{r0}-@code{r31}, nonfixed core register")

(define_register_constraint "l" "LPCOUNT_REG"
  "@internal
   Loop count register @code{r60}")

(define_register_constraint "x" "R0_REGS"
  "@code{R0} register.")

(define_register_constraint "Rgp" "GP_REG"
  "@internal
   Global Pointer register @code{r26}")

(define_register_constraint "f" "FP_REG"
  "@internal
   Frame Pointer register @code{r27}")

(define_register_constraint "b" "SP_REGS"
  "@internal
   Stack Pointer register @code{r28}")

(define_register_constraint "k" "LINK_REGS"
  "@internal
   Link Registers @code{ilink1}:@code{r29}, @code{ilink2}:@code{r30},
   @code{blink}:@code{r31},")

(define_register_constraint "q" "TARGET_Q_CLASS ? ARCOMPACT16_REGS : NO_REGS"
  "Registers usable in ARCompact 16-bit instructions: @code{r0}-@code{r3},
   @code{r12}-@code{r15}")

; NPS400 bitfield instructions require registers from the r0-r3,r12-r15
; range, and thus we need a register class and constraint that works
; independently of size optimization.
(define_register_constraint
 "Rrq" "TARGET_RRQ_CLASS ? ARCOMPACT16_REGS : NO_REGS"
  "Registers usable in NPS400 bitfield instructions: @code{r0}-@code{r3},
   @code{r12}-@code{r15}")

(define_register_constraint "e" "AC16_BASE_REGS"
  "Registers usable as base-regs of memory addresses in ARCompact 16-bit memory
   instructions: @code{r0}-@code{r3}, @code{r12}-@code{r15}, @code{sp}")

(define_register_constraint "D" "DOUBLE_REGS"
  "ARC FPX (dpfp) 64-bit registers. @code{D0}, @code{D1}")

(define_register_constraint "d" "SIMD_DMA_CONFIG_REGS"
  "@internal
   ARC SIMD DMA configuration registers @code{di0}-@code{di7},
   @code{do0}-@code{do7}")

(define_register_constraint "v" "SIMD_VR_REGS"
  "ARC SIMD 128-bit registers @code{VR0}-@code{VR23}")

; We could allow call-saved registers for sibling calls if we restored them
; in the delay slot of the call.  However, that would not allow to adjust the
; stack pointer afterwards, so the call-saved register would have to be
; restored from a call-used register that was just loaded with the value
; before.  So sticking to call-used registers for sibcalls will likely
; generate better code overall.
(define_register_constraint "Rsc" "SIBCALL_REGS"
  "@internal
   Sibling call register")

;; Integer constraints

(define_constraint "I"
  "@internal
   A signed 12-bit integer constant."
  (and (match_code "const_int")
       (match_test "SIGNED_INT12 (ival)")))

(define_constraint "K"
  "@internal
   A 3-bit unsigned integer constant"
  (and (match_code "const_int")
       (match_test "UNSIGNED_INT3 (ival)")))

(define_constraint "L"
  "@internal
   A 6-bit unsigned integer constant"
  (and (match_code "const_int")
       (match_test "UNSIGNED_INT6 (ival)")))

(define_constraint "CnL"
  "@internal
   One's complement of a 6-bit unsigned integer constant"
  (and (match_code "const_int")
       (match_test "UNSIGNED_INT6 (~ival)")))

(define_constraint "CmL"
  "@internal
   Two's complement of a 6-bit unsigned integer constant"
  (and (match_code "const_int")
       (match_test "UNSIGNED_INT6 (-ival)")))

(define_constraint "C16"
  "@internal
   A 16-bit signed integer constant"
  (and (match_code "const_int")
       (match_test "SIGNED_INT16 (ival)")))

(define_constraint "M"
  "@internal
   A 5-bit unsigned integer constant"
  (and (match_code "const_int")
       (match_test "UNSIGNED_INT5 (ival)")))

(define_constraint "N"
  "@internal
   Integer constant 1"
  (and (match_code "const_int")
       (match_test "IS_ONE (ival)")))

(define_constraint "O"
  "@internal
   A 7-bit unsigned integer constant"
  (and (match_code "const_int")
       (match_test "UNSIGNED_INT7 (ival)")))

(define_constraint "P"
  "@internal
   An 8-bit unsigned integer constant"
  (and (match_code "const_int")
       (match_test "UNSIGNED_INT8 (ival)")))

(define_constraint "C_0"
  "@internal
   Zero"
  (and (match_code "const_int")
       (match_test "ival == 0")))

(define_constraint "Cn0"
  "@internal
   Negative or zero"
  (and (match_code "const_int")
       (match_test "ival <= 0")))

(define_constraint "Cca"
  "@internal
   Conditional or three-address add / sub constant"
  (and (match_code "const_int")
       (match_test "ival == (HOST_WIDE_INT)(HOST_WIDE_INT_M1U << 31)
		    || (ival >= -0x1f8 && ival <= 0x1f8
			&& ((ival >= 0 ? ival : -ival)
			    <= 0x3f * (ival & -ival)))")))

; intersection of "O" and "Cca".
(define_constraint "CL2"
  "@internal
   A 6-bit unsigned integer constant times 2"
  (and (match_code "const_int")
       (match_test "!(ival & ~126)")))

(define_constraint "CM4"
  "@internal
   A 5-bit unsigned integer constant times 4"
  (and (match_code "const_int")
       (match_test "!(ival & ~124)")))

(define_constraint "Csp"
  "@internal
   A valid stack pointer offset for a short add"
  (and (match_code "const_int")
       (match_test "!(ival & ~124) || !(-ival & ~124)")))

(define_constraint "C2a"
  "@internal
   Unconditional two-address add / sub constant"
  (and (match_code "const_int")
       (match_test "ival == (HOST_WIDE_INT) (HOST_WIDE_INT_M1U << 31)
		    || (ival >= -0x4000 && ival <= 0x4000
			&& ((ival >= 0 ? ival : -ival)
			    <= 0x7ff * (ival & -ival)))")))

(define_constraint "C0p"
 "@internal
  power of two"
  (and (match_code "const_int")
       (match_test "IS_POWEROF2_P (ival)")))

(define_constraint "C1p"
 "@internal
  constant such that x+1 is a power of two, and x != 0"
  (and (match_code "const_int")
       (match_test "ival && IS_POWEROF2_P (ival + 1)")))

(define_constraint "C3p"
 "@internal
  constant int used to select xbfu a,b,u6 instruction.  The values accepted are 1 and 2."
  (and (match_code "const_int")
       (match_test "((ival == 1) || (ival == 2))")))

(define_constraint "Ccp"
 "@internal
  constant such that ~x (one's Complement) is a power of two"
  (and (match_code "const_int")
       (match_test "IS_POWEROF2_P (~ival)")))

(define_constraint "Cux"
 "@internal
  constant such that AND gives an unsigned extension"
  (and (match_code "const_int")
       (match_test "ival == 0xff || ival == 0xffff")))

(define_constraint "Chs"
 "@internal
  constant for a highpart that can be checked with a shift (asr.f 0,rn,m)"
  (and (match_code "const_int")
       (match_test "IS_POWEROF2_P (-ival)")))

(define_constraint "Clo"
 "@internal
  constant that fits into 16 lower bits, for movl"
  (and (match_code "const_int")
       (match_test "TARGET_NPS_BITOPS")
       (match_test "(ival & ~0xffffU) == 0")))

(define_constraint "Chi"
 "@internal
  constant that fits into 16 higher bits, for movh_i"
  (and (match_code "const_int")
       (match_test "TARGET_NPS_BITOPS")
       (match_test "trunc_int_for_mode (ival >> 16, HImode) << 16 == ival")))

(define_constraint "Cbf"
 "@internal
  a mask for a bit field, for AND using movb_i"
  (and (match_code "const_int")
       (match_test "TARGET_NPS_BITOPS")
       (match_test "IS_POWEROF2_OR_0_P (ival + (ival & -ival))")))

(define_constraint "Cbn"
 "@internal
  a constant integer, valid only if TARGET_NPS_BITOPS is true"
  (and (match_code "const_int")
       (match_test "TARGET_NPS_BITOPS")))

(define_constraint "C18"
 "@internal
  1,2,4 or 8"
  (and (match_code "const_int")
       (match_test "ival == 1 || ival == 2 || ival == 4 || ival == 8")))

(define_constraint "Crr"
 "@internal
  constant that can be loaded with ror b,u6"
  (and (match_code "const_int")
       (match_test "(ival & ~0x8000001f) == 0 && !arc_ccfsm_cond_exec_p ()")))

(define_constraint "Cbi"
 "@internal
  constant that can be loaded with movbi.cl"
  (and (match_code "const_int")
       (match_test "TARGET_NPS_BITOPS")
       (match_test "!ival
		    || ((ival & 0xffffffffUL) >> exact_log2 (ival & -ival)
			<= 0xff)")))

;; Floating-point constraints

(define_constraint "G"
  "@internal
   A 32-bit constant double value"
  (and (match_code "const_double")
       (match_test "arc_double_limm_p (op)")))

(define_constraint "H"
  "@internal
   All const_double values (including 64-bit values)"
  (and (match_code "const_double")
       (match_test "1")))

;; Memory constraints
(define_memory_constraint "T"
  "@internal
   A valid memory operand for ARCompact load instructions"
  (and (match_code "mem")
       (match_test "compact_load_memory_operand (op, VOIDmode)")))

(define_memory_constraint "S"
  "@internal
   A valid memory operand for ARCompact store instructions"
  (and (match_code "mem")
       (match_test "compact_store_memory_operand (op, VOIDmode)")))

(define_memory_constraint "Uex"
  "@internal
   A valid memory operand for limm-free extend instructions"
  (and (match_code "mem")
       (match_test "!cmem_address (XEXP (op, 0), SImode)")
       (not (match_operand 0 "long_immediate_loadstore_operand"))))

; Don't use define_memory_constraint here as the relocation patching
; for small data symbols only works within a ld/st instruction and
; define_memory_constraint may result in the address being calculated
; into a register first.
(define_constraint "Usd"
   "@internal
    A valid _small-data_ memory operand for ARCompact instructions"
   (and (match_code "mem")
        (match_test "compact_sda_memory_operand (op, VOIDmode)")))

(define_memory_constraint "Usc"
  "@internal
   A valid memory operand for storing constants"
  (and (match_code "mem")
       (match_test "!CONSTANT_P (XEXP (op,0))")
;; ??? the assembler rejects stores of immediates to small data.
       (match_test "!compact_sda_memory_operand (op, VOIDmode)")))

(define_constraint "Us<"
  "@internal
   Stack pre-decrement"
  (and (match_code "mem")
       (match_test "GET_CODE (XEXP (op, 0)) == PRE_DEC")
       (match_test "REG_P (XEXP (XEXP (op, 0), 0))")
       (match_test "REGNO (XEXP (XEXP (op, 0), 0)) == SP_REG")))

(define_constraint "Us>"
  "@internal
   Stack post-increment"
  (and (match_code "mem")
       (match_test "GET_CODE (XEXP (op, 0)) == POST_INC")
       (match_test "REG_P (XEXP (XEXP (op, 0), 0))")
       (match_test "REGNO (XEXP (XEXP (op, 0), 0)) == SP_REG")))

(define_constraint "Ucm"
  "@internal
  cmem access"
  (and (match_code "mem")
       (match_test "TARGET_NPS_CMEM && cmem_address (XEXP (op, 0), VOIDmode)")))

;; General constraints

(define_constraint "Cbr"
  "Branch destination"
  (ior (and (match_code "symbol_ref")
	    (match_test "!arc_is_longcall_p (op)"))
       (match_code "label_ref")))

(define_constraint "Cbp"
  "predicable branch/call destination"
  (ior (and (match_code "symbol_ref")
	    (match_test "arc_is_shortcall_p (op)"))
       (match_code "label_ref")))

(define_constraint "Cpc"
  "pc-relative constant"
  (match_test "arc_legitimate_pc_offset_p (op)"))

(define_constraint "Clb"
  "label"
  (and (match_code "label_ref")
       (match_test "arc_text_label (as_a <rtx_insn *> (XEXP (op, 0)))")))

(define_constraint "Cal"
  "constant for arithmetic/logical operations"
  (match_test "immediate_operand (op, VOIDmode) && !arc_legitimate_pc_offset_p (op)"))

(define_constraint "C32"
  "32 bit constant for arithmetic/logical operations"
  (match_test "immediate_operand (op, VOIDmode)
	       && !arc_legitimate_pc_offset_p (op)
	       && !satisfies_constraint_I (op)"))

; Note that the 'cryptic' register constraints will not make reload use the
; associated class to reload into, but this will not penalize reloading of any
; other operands, or using an alternate part of the same alternative.

; Rcq is different in three important ways from a register class constraint:
; - It does not imply a register class, hence reload will not use it to drive
;   reloads.
; - It matches even when there is no register class to describe its accepted
;   set; not having such a set again lessens the impact on register allocation.
; - It won't match when the instruction is conditionalized by the ccfsm.
(define_constraint "Rcq"
  "@internal
   Cryptic q - for short insn generation while not affecting register allocation
   Registers usable in ARCompact 16-bit instructions: @code{r0}-@code{r3},
   @code{r12}-@code{r15}"
  (and (match_code "reg")
       (match_test "TARGET_Rcq
		    && !arc_ccfsm_cond_exec_p ()
		    && IN_RANGE (REGNO (op) ^ 4, 4, 11)")))

; If we need a reload, we generally want to steer reload to use three-address
; alternatives in preference of two-address alternatives, unless the
; three-address alternative introduces a LIMM that is unnecessary for the
; two-address alternative.
(define_constraint "Rcw"
  "@internal
   Cryptic w - for use in early alternatives with matching constraint"
  (and (match_code "reg")
       (match_test
	"TARGET_Rcw
	 && REGNO (op) < FIRST_PSEUDO_REGISTER
	 && TEST_HARD_REG_BIT (reg_class_contents[WRITABLE_CORE_REGS],
			       REGNO (op))")))

(define_constraint "Rcr"
  "@internal
   Cryptic r - for use in early alternatives with matching constraint"
  (and (match_code "reg")
       (match_test
	"TARGET_Rcw
	 && REGNO (op) < FIRST_PSEUDO_REGISTER
	 && TEST_HARD_REG_BIT (reg_class_contents[GENERAL_REGS],
			       REGNO (op))")))

(define_constraint "Rcb"
  "@internal
   Stack Pointer register @code{r28} - do not reload into its class"
  (and (match_code "reg")
       (match_test "REGNO (op) == 28")))

(define_constraint "Rck"
  "@internal
   blink (usful for push_s / pop_s)"
  (and (match_code "reg")
       (match_test "REGNO (op) == 31")))

(define_constraint "Rs5"
  "@internal
   sibcall register - only allow one of the five available 16 bit isnsn.
   Registers usable in ARCompact 16-bit instructions: @code{r0}-@code{r3},
   @code{r12}"
  (and (match_code "reg")
       (match_test "!arc_ccfsm_cond_exec_p ()")
       (ior (match_test "(unsigned) REGNO (op) <= 3")
	    (match_test "REGNO (op) == 12"))))

(define_constraint "Rcc"
  "@internal
  Condition Codes"
  (and (match_code "reg") (match_test "cc_register (op, VOIDmode)")))


(define_constraint "Q"
  "@internal
   Integer constant zero"
  (and (match_code "const_int")
       (match_test "IS_ZERO (ival)")))

(define_constraint "Cm2"
  "@internal
   A signed 9-bit integer constant."
  (and (match_code "const_int")
       (match_test "(ival >= -256) && (ival <=255)")))

(define_constraint "C62"
  "@internal
   An unsigned 6-bit integer constant, up to 62."
  (and (match_code "const_int")
       (match_test "UNSIGNED_INT6 (ival - 1)")))

;; Memory constraint used for atomic ops.
(define_memory_constraint "ATO"
  "A memory with only a base register"
  (match_operand 0 "mem_noofs_operand"))
Commit	Line	Data
526b7aee	1	;; Constraint definitions for Synopsys DesignWare ARC.
818ab71a	2	;; Copyright (C) 2007-2016 Free Software Foundation, Inc.
526b7aee SV	3	;;
	4	;; This file is part of GCC.
	5	;;
	6	;; GCC is free software; you can redistribute it and/or modify
	7	;; it under the terms of the GNU General Public License as published by
	8	;; the Free Software Foundation; either version 3, or (at your option)
	9	;; any later version.
	10	;;
	11	;; GCC is distributed in the hope that it will be useful,
	12	;; but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	;; GNU General Public License for more details.
	15	;;
	16	;; You should have received a copy of the GNU General Public License
	17	;; along with GCC; see the file COPYING3. If not see
	18	;; <http://www.gnu.org/licenses/>.
	19
	20	;; Register constraints
	21
	22	; Most instructions accept arbitrary core registers for their inputs, even
	23	; if the core register in question cannot be written to, like the multiply
fb155425	24	; result registers of ARC600.
526b7aee SV	25	; First, define a class for core registers that can be read cheaply. This
	26	; is most or all core registers for ARC600, but only r0-r31 for ARC700
	27	(define_register_constraint "c" "CHEAP_CORE_REGS"
	28	"core register @code{r0}-@code{r31}, @code{ap},@code{pcl}")
	29
	30	; All core regs - e.g. for when we must have a way to reload a register.
	31	(define_register_constraint "Rac" "ALL_CORE_REGS"
	32	"core register @code{r0}-@code{r60}, @code{ap},@code{pcl}")
	33
	34	; Some core registers (.e.g lp_count) aren't general registers because they
	35	; can't be used as the destination of a multi-cycle operation like
	36	; load and/or multiply, yet they are still writable in the sense that
	37	; register-register moves and single-cycle arithmetic (e.g "add", "and",
	38	; but not "mpy") can write to them.
	39	(define_register_constraint "w" "WRITABLE_CORE_REGS"
	40	"writable core register: @code{r0}-@code{r31}, @code{r60}, nonfixed core register")
	41
	42	(define_register_constraint "W" "MPY_WRITABLE_CORE_REGS"
	43	"writable core register except @code{LP_COUNT} (@code{r60}): @code{r0}-@code{r31}, nonfixed core register")
	44
	45	(define_register_constraint "l" "LPCOUNT_REG"
	46	"@internal
	47	Loop count register @code{r60}")
	48
	49	(define_register_constraint "x" "R0_REGS"
	50	"@code{R0} register.")
	51
	52	(define_register_constraint "Rgp" "GP_REG"
	53	"@internal
	54	Global Pointer register @code{r26}")
	55
	56	(define_register_constraint "f" "FP_REG"
	57	"@internal
	58	Frame Pointer register @code{r27}")
	59
	60	(define_register_constraint "b" "SP_REGS"
	61	"@internal
	62	Stack Pointer register @code{r28}")
	63
	64	(define_register_constraint "k" "LINK_REGS"
	65	"@internal
	66	Link Registers @code{ilink1}:@code{r29}, @code{ilink2}:@code{r30},
	67	@code{blink}:@code{r31},")
	68
ceaaa9fe	69	(define_register_constraint "q" "TARGET_Q_CLASS ? ARCOMPACT16_REGS : NO_REGS"
526b7aee SV	70	"Registers usable in ARCompact 16-bit instructions: @code{r0}-@code{r3},
	71	@code{r12}-@code{r15}")
	72
ceaaa9fe JR	73	; NPS400 bitfield instructions require registers from the r0-r3,r12-r15
	74	; range, and thus we need a register class and constraint that works
	75	; independently of size optimization.
	76	(define_register_constraint
	77	"Rrq" "TARGET_RRQ_CLASS ? ARCOMPACT16_REGS : NO_REGS"
	78	"Registers usable in NPS400 bitfield instructions: @code{r0}-@code{r3},
	79	@code{r12}-@code{r15}")
	80
526b7aee SV	81	(define_register_constraint "e" "AC16_BASE_REGS"
	82	"Registers usable as base-regs of memory addresses in ARCompact 16-bit memory
	83	instructions: @code{r0}-@code{r3}, @code{r12}-@code{r15}, @code{sp}")
	84
	85	(define_register_constraint "D" "DOUBLE_REGS"
	86	"ARC FPX (dpfp) 64-bit registers. @code{D0}, @code{D1}")
	87
	88	(define_register_constraint "d" "SIMD_DMA_CONFIG_REGS"
	89	"@internal
	90	ARC SIMD DMA configuration registers @code{di0}-@code{di7},
	91	@code{do0}-@code{do7}")
	92
	93	(define_register_constraint "v" "SIMD_VR_REGS"
	94	"ARC SIMD 128-bit registers @code{VR0}-@code{VR23}")
	95
	96	; We could allow call-saved registers for sibling calls if we restored them
	97	; in the delay slot of the call. However, that would not allow to adjust the
	98	; stack pointer afterwards, so the call-saved register would have to be
	99	; restored from a call-used register that was just loaded with the value
	100	; before. So sticking to call-used registers for sibcalls will likely
	101	; generate better code overall.
	102	(define_register_constraint "Rsc" "SIBCALL_REGS"
	103	"@internal
	104	Sibling call register")
	105
	106	;; Integer constraints
	107
	108	(define_constraint "I"
	109	"@internal
	110	A signed 12-bit integer constant."
	111	(and (match_code "const_int")
	112	(match_test "SIGNED_INT12 (ival)")))
	113
	114	(define_constraint "K"
	115	"@internal
	116	A 3-bit unsigned integer constant"
	117	(and (match_code "const_int")
	118	(match_test "UNSIGNED_INT3 (ival)")))
	119
	120	(define_constraint "L"
	121	"@internal
	122	A 6-bit unsigned integer constant"
	123	(and (match_code "const_int")
	124	(match_test "UNSIGNED_INT6 (ival)")))
	125
	126	(define_constraint "CnL"
	127	"@internal
	128	One's complement of a 6-bit unsigned integer constant"
	129	(and (match_code "const_int")
	130	(match_test "UNSIGNED_INT6 (~ival)")))
	131
	132	(define_constraint "CmL"
	133	"@internal
	134	Two's complement of a 6-bit unsigned integer constant"
	135	(and (match_code "const_int")
	136	(match_test "UNSIGNED_INT6 (-ival)")))
	137
f50bb868 CZ	138	(define_constraint "C16"
	139	"@internal
	140	A 16-bit signed integer constant"
	141	(and (match_code "const_int")
	142	(match_test "SIGNED_INT16 (ival)")))
	143
526b7aee SV	144	(define_constraint "M"
	145	"@internal
	146	A 5-bit unsigned integer constant"
	147	(and (match_code "const_int")
	148	(match_test "UNSIGNED_INT5 (ival)")))
	149
	150	(define_constraint "N"
	151	"@internal
	152	Integer constant 1"
	153	(and (match_code "const_int")
	154	(match_test "IS_ONE (ival)")))
	155
	156	(define_constraint "O"
	157	"@internal
	158	A 7-bit unsigned integer constant"
	159	(and (match_code "const_int")
	160	(match_test "UNSIGNED_INT7 (ival)")))
	161
	162	(define_constraint "P"
	163	"@internal
	164	An 8-bit unsigned integer constant"
	165	(and (match_code "const_int")
	166	(match_test "UNSIGNED_INT8 (ival)")))
	167
	168	(define_constraint "C_0"
	169	"@internal
	170	Zero"
	171	(and (match_code "const_int")
	172	(match_test "ival == 0")))
	173
	174	(define_constraint "Cn0"
	175	"@internal
	176	Negative or zero"
	177	(and (match_code "const_int")
	178	(match_test "ival <= 0")))
	179
	180	(define_constraint "Cca"
	181	"@internal
	182	Conditional or three-address add / sub constant"
	183	(and (match_code "const_int")
c419f71c	184	(match_test "ival == (HOST_WIDE_INT)(HOST_WIDE_INT_M1U << 31)
526b7aee SV	185	\|\| (ival >= -0x1f8 && ival <= 0x1f8
	186	&& ((ival >= 0 ? ival : -ival)
	187	<= 0x3f * (ival & -ival)))")))
	188
	189	; intersection of "O" and "Cca".
	190	(define_constraint "CL2"
	191	"@internal
	192	A 6-bit unsigned integer constant times 2"
	193	(and (match_code "const_int")
	194	(match_test "!(ival & ~126)")))
	195
	196	(define_constraint "CM4"
	197	"@internal
	198	A 5-bit unsigned integer constant times 4"
	199	(and (match_code "const_int")
	200	(match_test "!(ival & ~124)")))
	201
	202	(define_constraint "Csp"
	203	"@internal
	204	A valid stack pointer offset for a short add"
	205	(and (match_code "const_int")
	206	(match_test "!(ival & ~124) \|\| !(-ival & ~124)")))
	207
	208	(define_constraint "C2a"
	209	"@internal
	210	Unconditional two-address add / sub constant"
	211	(and (match_code "const_int")
4e671509	212	(match_test "ival == (HOST_WIDE_INT) (HOST_WIDE_INT_M1U << 31)
526b7aee SV	213	\|\| (ival >= -0x4000 && ival <= 0x4000
	214	&& ((ival >= 0 ? ival : -ival)
	215	<= 0x7ff * (ival & -ival)))")))
	216
	217	(define_constraint "C0p"
	218	"@internal
	219	power of two"
	220	(and (match_code "const_int")
	221	(match_test "IS_POWEROF2_P (ival)")))
	222
	223	(define_constraint "C1p"
	224	"@internal
	225	constant such that x+1 is a power of two, and x != 0"
	226	(and (match_code "const_int")
	227	(match_test "ival && IS_POWEROF2_P (ival + 1)")))
	228
f50bb868 CZ	229	(define_constraint "C3p"
	230	"@internal
	231	constant int used to select xbfu a,b,u6 instruction. The values accepted are 1 and 2."
	232	(and (match_code "const_int")
	233	(match_test "((ival == 1) \|\| (ival == 2))")))
	234
526b7aee SV	235	(define_constraint "Ccp"
	236	"@internal
	237	constant such that ~x (one's Complement) is a power of two"
	238	(and (match_code "const_int")
	239	(match_test "IS_POWEROF2_P (~ival)")))
	240
	241	(define_constraint "Cux"
	242	"@internal
	243	constant such that AND gives an unsigned extension"
	244	(and (match_code "const_int")
	245	(match_test "ival == 0xff \|\| ival == 0xffff")))
	246
ceaaa9fe JR	247	(define_constraint "Chs"
	248	"@internal
	249	constant for a highpart that can be checked with a shift (asr.f 0,rn,m)"
	250	(and (match_code "const_int")
	251	(match_test "IS_POWEROF2_P (-ival)")))
	252
	253	(define_constraint "Clo"
	254	"@internal
	255	constant that fits into 16 lower bits, for movl"
	256	(and (match_code "const_int")
	257	(match_test "TARGET_NPS_BITOPS")
	258	(match_test "(ival & ~0xffffU) == 0")))
	259
	260	(define_constraint "Chi"
	261	"@internal
	262	constant that fits into 16 higher bits, for movh_i"
	263	(and (match_code "const_int")
	264	(match_test "TARGET_NPS_BITOPS")
	265	(match_test "trunc_int_for_mode (ival >> 16, HImode) << 16 == ival")))
	266
	267	(define_constraint "Cbf"
	268	"@internal
	269	a mask for a bit field, for AND using movb_i"
	270	(and (match_code "const_int")
	271	(match_test "TARGET_NPS_BITOPS")
	272	(match_test "IS_POWEROF2_OR_0_P (ival + (ival & -ival))")))
	273
	274	(define_constraint "Cbn"
	275	"@internal
	276	a constant integer, valid only if TARGET_NPS_BITOPS is true"
	277	(and (match_code "const_int")
	278	(match_test "TARGET_NPS_BITOPS")))
	279
	280	(define_constraint "C18"
	281	"@internal
	282	1,2,4 or 8"
	283	(and (match_code "const_int")
	284	(match_test "ival == 1 \|\| ival == 2 \|\| ival == 4 \|\| ival == 8")))
	285
526b7aee SV	286	(define_constraint "Crr"
	287	"@internal
	288	constant that can be loaded with ror b,u6"
	289	(and (match_code "const_int")
	290	(match_test "(ival & ~0x8000001f) == 0 && !arc_ccfsm_cond_exec_p ()")))
	291
ceaaa9fe JR	292	(define_constraint "Cbi"
	293	"@internal
	294	constant that can be loaded with movbi.cl"
	295	(and (match_code "const_int")
	296	(match_test "TARGET_NPS_BITOPS")
	297	(match_test "!ival
	298	\|\| ((ival & 0xffffffffUL) >> exact_log2 (ival & -ival)
	299	<= 0xff)")))
	300
526b7aee SV	301	;; Floating-point constraints
	302
	303	(define_constraint "G"
	304	"@internal
	305	A 32-bit constant double value"
	306	(and (match_code "const_double")
	307	(match_test "arc_double_limm_p (op)")))
	308
	309	(define_constraint "H"
	310	"@internal
	311	All const_double values (including 64-bit values)"
	312	(and (match_code "const_double")
	313	(match_test "1")))
	314
	315	;; Memory constraints
	316	(define_memory_constraint "T"
	317	"@internal
	318	A valid memory operand for ARCompact load instructions"
	319	(and (match_code "mem")
	320	(match_test "compact_load_memory_operand (op, VOIDmode)")))
	321
	322	(define_memory_constraint "S"
	323	"@internal
	324	A valid memory operand for ARCompact store instructions"
	325	(and (match_code "mem")
	326	(match_test "compact_store_memory_operand (op, VOIDmode)")))
	327
4d03dc2f JR	328	(define_memory_constraint "Uex"
	329	"@internal
	330	A valid memory operand for limm-free extend instructions"
	331	(and (match_code "mem")
	332	(match_test "!cmem_address (XEXP (op, 0), SImode)")
	333	(not (match_operand 0 "long_immediate_loadstore_operand"))))
	334
c20ef9d2 AB	335	; Don't use define_memory_constraint here as the relocation patching
	336	; for small data symbols only works within a ld/st instruction and
	337	; define_memory_constraint may result in the address being calculated
	338	; into a register first.
	339	(define_constraint "Usd"
	340	"@internal
	341	A valid _small-data_ memory operand for ARCompact instructions"
	342	(and (match_code "mem")
	343	(match_test "compact_sda_memory_operand (op, VOIDmode)")))
526b7aee SV	344
	345	(define_memory_constraint "Usc"
	346	"@internal
	347	A valid memory operand for storing constants"
	348	(and (match_code "mem")
	349	(match_test "!CONSTANT_P (XEXP (op,0))")
	350	;; ??? the assembler rejects stores of immediates to small data.
	351	(match_test "!compact_sda_memory_operand (op, VOIDmode)")))
	352
c20ef9d2	353	(define_constraint "Us<"
526b7aee SV	354	"@internal
	355	Stack pre-decrement"
	356	(and (match_code "mem")
	357	(match_test "GET_CODE (XEXP (op, 0)) == PRE_DEC")
	358	(match_test "REG_P (XEXP (XEXP (op, 0), 0))")
	359	(match_test "REGNO (XEXP (XEXP (op, 0), 0)) == SP_REG")))
	360
c20ef9d2	361	(define_constraint "Us>"
526b7aee SV	362	"@internal
	363	Stack post-increment"
	364	(and (match_code "mem")
	365	(match_test "GET_CODE (XEXP (op, 0)) == POST_INC")
	366	(match_test "REG_P (XEXP (XEXP (op, 0), 0))")
	367	(match_test "REGNO (XEXP (XEXP (op, 0), 0)) == SP_REG")))
	368
4d03dc2f JR	369	(define_constraint "Ucm"
	370	"@internal
	371	cmem access"
	372	(and (match_code "mem")
	373	(match_test "TARGET_NPS_CMEM && cmem_address (XEXP (op, 0), VOIDmode)")))
	374
526b7aee SV	375	;; General constraints
	376
	377	(define_constraint "Cbr"
	378	"Branch destination"
	379	(ior (and (match_code "symbol_ref")
	380	(match_test "!arc_is_longcall_p (op)"))
	381	(match_code "label_ref")))
	382
	383	(define_constraint "Cbp"
	384	"predicable branch/call destination"
	385	(ior (and (match_code "symbol_ref")
	386	(match_test "arc_is_shortcall_p (op)"))
	387	(match_code "label_ref")))
	388
	389	(define_constraint "Cpc"
	390	"pc-relative constant"
	391	(match_test "arc_legitimate_pc_offset_p (op)"))
	392
	393	(define_constraint "Clb"
	394	"label"
	395	(and (match_code "label_ref")
b32d5189	396	(match_test "arc_text_label (as_a <rtx_insn *> (XEXP (op, 0)))")))
526b7aee SV	397
	398	(define_constraint "Cal"
	399	"constant for arithmetic/logical operations"
	400	(match_test "immediate_operand (op, VOIDmode) && !arc_legitimate_pc_offset_p (op)"))
	401
	402	(define_constraint "C32"
	403	"32 bit constant for arithmetic/logical operations"
	404	(match_test "immediate_operand (op, VOIDmode)
	405	&& !arc_legitimate_pc_offset_p (op)
	406	&& !satisfies_constraint_I (op)"))
	407
	408	; Note that the 'cryptic' register constraints will not make reload use the
	409	; associated class to reload into, but this will not penalize reloading of any
	410	; other operands, or using an alternate part of the same alternative.
	411
	412	; Rcq is different in three important ways from a register class constraint:
	413	; - It does not imply a register class, hence reload will not use it to drive
	414	; reloads.
	415	; - It matches even when there is no register class to describe its accepted
	416	; set; not having such a set again lessens the impact on register allocation.
	417	; - It won't match when the instruction is conditionalized by the ccfsm.
	418	(define_constraint "Rcq"
	419	"@internal
	420	Cryptic q - for short insn generation while not affecting register allocation
	421	Registers usable in ARCompact 16-bit instructions: @code{r0}-@code{r3},
	422	@code{r12}-@code{r15}"
8da140e0	423	(and (match_code "reg")
526b7aee SV	424	(match_test "TARGET_Rcq
526b7aee SV	425	&& !arc_ccfsm_cond_exec_p ()
036def0f	426	&& IN_RANGE (REGNO (op) ^ 4, 4, 11)")))
526b7aee SV	427
	428	; If we need a reload, we generally want to steer reload to use three-address
	429	; alternatives in preference of two-address alternatives, unless the
	430	; three-address alternative introduces a LIMM that is unnecessary for the
	431	; two-address alternative.
	432	(define_constraint "Rcw"
	433	"@internal
	434	Cryptic w - for use in early alternatives with matching constraint"
8da140e0	435	(and (match_code "reg")
526b7aee SV	436	(match_test
	437	"TARGET_Rcw
	438	&& REGNO (op) < FIRST_PSEUDO_REGISTER
	439	&& TEST_HARD_REG_BIT (reg_class_contents[WRITABLE_CORE_REGS],
	440	REGNO (op))")))
	441
	442	(define_constraint "Rcr"
	443	"@internal
	444	Cryptic r - for use in early alternatives with matching constraint"
8da140e0	445	(and (match_code "reg")
526b7aee SV	446	(match_test
	447	"TARGET_Rcw
	448	&& REGNO (op) < FIRST_PSEUDO_REGISTER
	449	&& TEST_HARD_REG_BIT (reg_class_contents[GENERAL_REGS],
	450	REGNO (op))")))
	451
	452	(define_constraint "Rcb"
	453	"@internal
	454	Stack Pointer register @code{r28} - do not reload into its class"
8da140e0	455	(and (match_code "reg")
526b7aee SV	456	(match_test "REGNO (op) == 28")))
	457
	458	(define_constraint "Rck"
	459	"@internal
	460	blink (usful for push_s / pop_s)"
8da140e0	461	(and (match_code "reg")
526b7aee SV	462	(match_test "REGNO (op) == 31")))
	463
	464	(define_constraint "Rs5"
	465	"@internal
	466	sibcall register - only allow one of the five available 16 bit isnsn.
	467	Registers usable in ARCompact 16-bit instructions: @code{r0}-@code{r3},
	468	@code{r12}"
8da140e0	469	(and (match_code "reg")
526b7aee SV	470	(match_test "!arc_ccfsm_cond_exec_p ()")
	471	(ior (match_test "(unsigned) REGNO (op) <= 3")
	472	(match_test "REGNO (op) == 12"))))
	473
	474	(define_constraint "Rcc"
	475	"@internal
	476	Condition Codes"
8da140e0	477	(and (match_code "reg") (match_test "cc_register (op, VOIDmode)")))
526b7aee SV	478
	479
	480	(define_constraint "Q"
	481	"@internal
	482	Integer constant zero"
	483	(and (match_code "const_int")
	484	(match_test "IS_ZERO (ival)")))
f50bb868 CZ	485
	486	(define_constraint "Cm2"
	487	"@internal
	488	A signed 9-bit integer constant."
	489	(and (match_code "const_int")
	490	(match_test "(ival >= -256) && (ival <=255)")))
	491
	492	(define_constraint "C62"
	493	"@internal
	494	An unsigned 6-bit integer constant, up to 62."
	495	(and (match_code "const_int")
	496	(match_test "UNSIGNED_INT6 (ival - 1)")))
b8a64b7f CZ	497
	498	;; Memory constraint used for atomic ops.
	499	(define_memory_constraint "ATO"
	500	"A memory with only a base register"
	501	(match_operand 0 "mem_noofs_operand"))