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526b7aee | 1 | ;; Predicate definitions for Synopsys DesignWare ARC. |
cbe34bb5 | 2 | ;; Copyright (C) 2007-2017 Free Software Foundation, Inc. |
526b7aee SV |
3 | ;; |
4 | ;; This file is part of GCC. | |
5 | ;; | |
6 | ;; GCC is free software; you can redistribute it and/or modify | |
7 | ;; it under the terms of the GNU General Public License as published by | |
8 | ;; the Free Software Foundation; either version 3, or (at your option) | |
9 | ;; any later version. | |
10 | ;; | |
11 | ;; GCC is distributed in the hope that it will be useful, | |
12 | ;; but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | ;; GNU General Public License for more details. | |
15 | ;; | |
16 | ;; You should have received a copy of the GNU General Public License | |
17 | ;; along with GCC; see the file COPYING3. If not see | |
18 | ;; <http://www.gnu.org/licenses/>. | |
19 | ||
20 | (define_predicate "dest_reg_operand" | |
21 | (match_code "reg,subreg") | |
22 | { | |
23 | rtx op0 = op; | |
24 | ||
25 | if (GET_CODE (op0) == SUBREG) | |
26 | op0 = SUBREG_REG (op0); | |
27 | if (REG_P (op0) && REGNO (op0) < FIRST_PSEUDO_REGISTER | |
28 | && TEST_HARD_REG_BIT (reg_class_contents[ALL_CORE_REGS], | |
29 | REGNO (op0)) | |
30 | && !TEST_HARD_REG_BIT (reg_class_contents[WRITABLE_CORE_REGS], | |
31 | REGNO (op0))) | |
32 | return 0; | |
33 | return register_operand (op, mode); | |
34 | }) | |
35 | ||
36 | (define_predicate "mpy_dest_reg_operand" | |
37 | (match_code "reg,subreg") | |
38 | { | |
39 | rtx op0 = op; | |
40 | ||
41 | if (GET_CODE (op0) == SUBREG) | |
42 | op0 = SUBREG_REG (op0); | |
43 | if (REG_P (op0) && REGNO (op0) < FIRST_PSEUDO_REGISTER | |
44 | && TEST_HARD_REG_BIT (reg_class_contents[ALL_CORE_REGS], | |
45 | REGNO (op0)) | |
46 | /* Make sure the destination register is not LP_COUNT. */ | |
47 | && !TEST_HARD_REG_BIT (reg_class_contents[MPY_WRITABLE_CORE_REGS], | |
48 | REGNO (op0))) | |
49 | return 0; | |
50 | return register_operand (op, mode); | |
51 | }) | |
52 | ||
53 | ||
54 | ;; Returns 1 if OP is a symbol reference. | |
55 | (define_predicate "symbolic_operand" | |
56 | (match_code "symbol_ref, label_ref, const") | |
57 | ) | |
58 | ||
59 | ;; Acceptable arguments to the call insn. | |
60 | (define_predicate "call_address_operand" | |
61 | (ior (match_code "const_int, reg") | |
62 | (match_operand 0 "symbolic_operand") | |
63 | (match_test "CONSTANT_P (op) | |
64 | && arc_legitimate_constant_p (VOIDmode, op)")) | |
65 | ) | |
66 | ||
67 | (define_predicate "call_operand" | |
68 | (and (match_code "mem") | |
69 | (match_test "call_address_operand (XEXP (op, 0), mode)")) | |
70 | ) | |
71 | ||
72 | ;; Return true if OP is a unsigned 6-bit immediate (u6) value. | |
73 | (define_predicate "u6_immediate_operand" | |
74 | (and (match_code "const_int") | |
75 | (match_test "UNSIGNED_INT6 (INTVAL (op))")) | |
76 | ) | |
77 | ||
78 | ;; Return true if OP is a short immediate (shimm) value. | |
79 | (define_predicate "short_immediate_operand" | |
80 | (and (match_code "const_int") | |
81 | (match_test "SMALL_INT (INTVAL (op))")) | |
82 | ) | |
83 | ||
84 | (define_predicate "p2_immediate_operand" | |
85 | (and (match_code "const_int") | |
86 | (match_test "((INTVAL (op) - 1) & INTVAL (op)) == 0") | |
87 | (match_test "INTVAL (op)")) | |
88 | ) | |
89 | ||
90 | ;; Return true if OP will require a long immediate (limm) value. | |
91 | ;; This is currently only used when calculating length attributes. | |
92 | (define_predicate "long_immediate_operand" | |
93 | (match_code "symbol_ref, label_ref, const, const_double, const_int") | |
94 | { | |
95 | switch (GET_CODE (op)) | |
96 | { | |
97 | case SYMBOL_REF : | |
98 | case LABEL_REF : | |
99 | case CONST : | |
100 | return 1; | |
101 | case CONST_INT : | |
102 | return !SIGNED_INT12 (INTVAL (op)); | |
103 | case CONST_DOUBLE : | |
104 | /* These can happen because large unsigned 32 bit constants are | |
105 | represented this way (the multiplication patterns can cause these | |
106 | to be generated). They also occur for SFmode values. */ | |
107 | return 1; | |
108 | default: | |
109 | break; | |
110 | } | |
111 | return 0; | |
112 | } | |
113 | ) | |
114 | ||
115 | ;; Return true if OP is a MEM that when used as a load or store address will | |
116 | ;; require an 8 byte insn. | |
117 | ;; Load and store instructions don't allow the same possibilities but they're | |
118 | ;; similar enough that this one function will do. | |
119 | ;; This is currently only used when calculating length attributes. */ | |
120 | (define_predicate "long_immediate_loadstore_operand" | |
121 | (match_code "mem") | |
122 | { | |
123 | int size = GET_MODE_SIZE (GET_MODE (op)); | |
124 | ||
125 | op = XEXP (op, 0); | |
4d03dc2f JR |
126 | if (TARGET_NPS_CMEM && cmem_address (op, SImode)) |
127 | return 0; | |
526b7aee SV |
128 | switch (GET_CODE (op)) |
129 | { | |
130 | case SYMBOL_REF : | |
131 | case LABEL_REF : | |
132 | case CONST : | |
133 | return 1; | |
134 | case CONST_INT : | |
135 | /* This must be handled as "st c,[limm]". Ditto for load. | |
136 | Technically, the assembler could translate some possibilities to | |
137 | "st c,[limm/2 + limm/2]" if limm/2 will fit in a shimm, but we don't | |
138 | assume that it does. */ | |
139 | return 1; | |
140 | case CONST_DOUBLE : | |
141 | /* These can happen because large unsigned 32 bit constants are | |
142 | represented this way (the multiplication patterns can cause these | |
143 | to be generated). They also occur for SFmode values. */ | |
144 | return 1; | |
145 | case REG : | |
146 | return 0; | |
147 | case PLUS : | |
148 | { | |
149 | rtx x = XEXP (op, 1); | |
150 | ||
ac255185 CZ |
151 | if ((GET_CODE (XEXP (op, 0)) == MULT) |
152 | && REG_P (XEXP (XEXP (op, 0), 0)) | |
153 | && CONSTANT_P (x)) | |
154 | return 1; | |
155 | ||
526b7aee SV |
156 | if (GET_CODE (x) == CONST) |
157 | { | |
158 | x = XEXP (x, 0); | |
159 | if (GET_CODE (x) == PLUS) | |
160 | x = XEXP (x, 0); | |
161 | } | |
162 | if (CONST_INT_P (x)) | |
163 | return (!SMALL_INT (INTVAL (x)) | |
164 | && (size <= 1 || size > 4 | |
165 | || (INTVAL (x) & (size - 1)) != 0 | |
166 | || !SMALL_INT (INTVAL (x) / size))); | |
167 | else if (GET_CODE (x) == SYMBOL_REF) | |
168 | return TARGET_NO_SDATA_SET || !SYMBOL_REF_SMALL_P (x); | |
169 | return 0; | |
170 | } | |
171 | default: | |
172 | break; | |
173 | } | |
174 | return 0; | |
175 | } | |
176 | ) | |
177 | ||
178 | ;; Return true if OP is any of R0-R3,R12-R15 for ARCompact 16-bit | |
179 | ;; instructions | |
180 | (define_predicate "compact_register_operand" | |
181 | (match_code "reg, subreg") | |
182 | { | |
183 | if ((GET_MODE (op) != mode) && (mode != VOIDmode)) | |
184 | return 0; | |
185 | ||
186 | return (GET_CODE (op) == REG) | |
187 | && (REGNO (op) >= FIRST_PSEUDO_REGISTER | |
188 | || COMPACT_GP_REG_P (REGNO (op))) ; | |
189 | } | |
190 | ) | |
191 | ||
0e03cebd CZ |
192 | (define_predicate "compact_hreg_operand" |
193 | (match_code "reg, subreg") | |
194 | { | |
195 | if ((GET_MODE (op) != mode) && (mode != VOIDmode)) | |
196 | return 0; | |
197 | ||
198 | return (GET_CODE (op) == REG) | |
199 | && (REGNO (op) >= FIRST_PSEUDO_REGISTER | |
200 | || (TARGET_V2 && REGNO (op) <= 31 && REGNO (op) != 30) | |
201 | || !TARGET_V2); | |
202 | } | |
203 | ) | |
204 | ||
526b7aee SV |
205 | ;; Return true if OP is an acceptable memory operand for ARCompact |
206 | ;; 16-bit store instructions | |
207 | (define_predicate "compact_store_memory_operand" | |
208 | (match_code "mem") | |
209 | { | |
210 | rtx addr, plus0, plus1; | |
211 | int size, off; | |
212 | ||
213 | if (mode == VOIDmode) | |
214 | mode = GET_MODE (op); | |
215 | ||
216 | /* .di instructions have no 16-bit form. */ | |
217 | if (MEM_VOLATILE_P (op) && !TARGET_VOLATILE_CACHE_SET) | |
218 | return 0; | |
219 | ||
220 | size = GET_MODE_SIZE (mode); | |
221 | ||
222 | /* dword operations really put out 2 instructions, so eliminate them. */ | |
223 | if (size > UNITS_PER_WORD) | |
224 | return 0; | |
225 | ||
226 | /* Decode the address now. */ | |
227 | addr = XEXP (op, 0); | |
228 | switch (GET_CODE (addr)) | |
229 | { | |
230 | case REG: | |
231 | return (REGNO (addr) >= FIRST_PSEUDO_REGISTER | |
232 | || COMPACT_GP_REG_P (REGNO (addr)) | |
233 | || (SP_REG_P (REGNO (addr)) && (size != 2))); | |
234 | /* stw_s does not support SP as a parameter. */ | |
235 | case PLUS: | |
236 | plus0 = XEXP (addr, 0); | |
237 | plus1 = XEXP (addr, 1); | |
238 | ||
239 | if ((GET_CODE (plus0) == REG) | |
240 | && ((REGNO (plus0) >= FIRST_PSEUDO_REGISTER) | |
241 | || COMPACT_GP_REG_P (REGNO (plus0))) | |
242 | && (GET_CODE (plus1) == CONST_INT)) | |
243 | { | |
244 | off = INTVAL (plus1); | |
245 | ||
246 | /* Negative offset is not supported in 16-bit load/store insns. */ | |
247 | if (off < 0) | |
248 | return 0; | |
249 | ||
250 | switch (size) | |
251 | { | |
252 | case 1: | |
253 | return (off < 32); | |
254 | case 2: | |
255 | return ((off < 64) && (off % 2 == 0)); | |
256 | case 4: | |
257 | return ((off < 128) && (off % 4 == 0)); | |
258 | } | |
259 | } | |
260 | ||
261 | if ((GET_CODE (plus0) == REG) | |
262 | && ((REGNO (plus0) >= FIRST_PSEUDO_REGISTER) | |
263 | || SP_REG_P (REGNO (plus0))) | |
264 | && (GET_CODE (plus1) == CONST_INT)) | |
265 | { | |
266 | off = INTVAL (plus1); | |
267 | ||
268 | return ((size != 2) && (off >= 0 && off < 128) && (off % 4 == 0)); | |
269 | } | |
270 | default: | |
271 | break; | |
272 | } | |
273 | return 0; | |
274 | } | |
275 | ) | |
276 | ||
277 | ;; Return true if OP is an acceptable argument for a single word | |
278 | ;; move source. | |
279 | (define_predicate "move_src_operand" | |
280 | (match_code "symbol_ref, label_ref, const, const_int, const_double, reg, subreg, mem") | |
281 | { | |
282 | switch (GET_CODE (op)) | |
283 | { | |
284 | case SYMBOL_REF : | |
28633bbd CZ |
285 | if (SYMBOL_REF_TLS_MODEL (op)) |
286 | return 0; | |
3bbe0b82 | 287 | return 1; |
526b7aee | 288 | case LABEL_REF : |
28633bbd | 289 | return 1; |
526b7aee | 290 | case CONST : |
28633bbd | 291 | return arc_legitimate_constant_p (mode, op); |
526b7aee SV |
292 | case CONST_INT : |
293 | return (LARGE_INT (INTVAL (op))); | |
294 | case CONST_DOUBLE : | |
295 | /* We can handle DImode integer constants in SImode if the value | |
296 | (signed or unsigned) will fit in 32 bits. This is needed because | |
297 | large unsigned 32 bit constants are represented as CONST_DOUBLEs. */ | |
298 | if (mode == SImode) | |
299 | return arc_double_limm_p (op); | |
300 | /* We can handle 32 bit floating point constants. */ | |
301 | if (mode == SFmode) | |
302 | return GET_MODE (op) == SFmode; | |
303 | return 0; | |
304 | case REG : | |
305 | return register_operand (op, mode); | |
306 | case SUBREG : | |
307 | /* (subreg (mem ...) ...) can occur here if the inner part was once a | |
308 | pseudo-reg and is now a stack slot. */ | |
309 | if (GET_CODE (SUBREG_REG (op)) == MEM) | |
310 | return address_operand (XEXP (SUBREG_REG (op), 0), mode); | |
311 | else | |
312 | return register_operand (op, mode); | |
313 | case MEM : | |
314 | return address_operand (XEXP (op, 0), mode); | |
315 | default : | |
316 | return 0; | |
317 | } | |
318 | } | |
319 | ) | |
320 | ||
321 | ;; Return true if OP is an acceptable argument for a double word | |
322 | ;; move source. | |
323 | (define_predicate "move_double_src_operand" | |
324 | (match_code "reg, subreg, mem, const_int, const_double") | |
325 | { | |
326 | switch (GET_CODE (op)) | |
327 | { | |
328 | case REG : | |
329 | return register_operand (op, mode); | |
330 | case SUBREG : | |
331 | /* (subreg (mem ...) ...) can occur here if the inner part was once a | |
332 | pseudo-reg and is now a stack slot. */ | |
333 | if (GET_CODE (SUBREG_REG (op)) == MEM) | |
e5dcff3e | 334 | return address_operand (XEXP (SUBREG_REG (op), 0), mode); |
526b7aee SV |
335 | else |
336 | return register_operand (op, mode); | |
337 | case MEM : | |
338 | return address_operand (XEXP (op, 0), mode); | |
339 | case CONST_INT : | |
340 | case CONST_DOUBLE : | |
341 | return 1; | |
342 | default : | |
343 | return 0; | |
344 | } | |
345 | } | |
346 | ) | |
347 | ||
348 | ;; Return true if OP is an acceptable argument for a move destination. | |
349 | (define_predicate "move_dest_operand" | |
350 | (match_code "reg, subreg, mem") | |
351 | { | |
352 | switch (GET_CODE (op)) | |
353 | { | |
354 | case REG : | |
355 | /* Program Counter register cannot be the target of a move. It is | |
356 | a readonly register. */ | |
357 | if (REGNO (op) == PROGRAM_COUNTER_REGNO) | |
358 | return 0; | |
359 | else if (TARGET_MULMAC_32BY16_SET | |
360 | && (REGNO (op) == 56 || REGNO(op) == 57)) | |
361 | return 0; | |
362 | else if (TARGET_MUL64_SET | |
363 | && (REGNO (op) == 57 || REGNO(op) == 58 || REGNO(op) == 59 )) | |
364 | return 0; | |
365 | else | |
366 | return dest_reg_operand (op, mode); | |
367 | case SUBREG : | |
368 | /* (subreg (mem ...) ...) can occur here if the inner part was once a | |
369 | pseudo-reg and is now a stack slot. */ | |
370 | if (GET_CODE (SUBREG_REG (op)) == MEM) | |
371 | return address_operand (XEXP (SUBREG_REG (op), 0), mode); | |
372 | else | |
373 | return dest_reg_operand (op, mode); | |
374 | case MEM : | |
375 | { | |
376 | rtx addr = XEXP (op, 0); | |
377 | ||
378 | if (GET_CODE (addr) == PLUS | |
379 | && (GET_CODE (XEXP (addr, 0)) == MULT | |
380 | || (!CONST_INT_P (XEXP (addr, 1)) | |
381 | && (TARGET_NO_SDATA_SET | |
382 | || GET_CODE (XEXP (addr, 1)) != SYMBOL_REF | |
383 | || !SYMBOL_REF_SMALL_P (XEXP (addr, 1)))))) | |
384 | return 0; | |
385 | if ((GET_CODE (addr) == PRE_MODIFY || GET_CODE (addr) == POST_MODIFY) | |
386 | && (GET_CODE (XEXP (addr, 1)) != PLUS | |
387 | || !CONST_INT_P (XEXP (XEXP (addr, 1), 1)))) | |
388 | return 0; | |
28633bbd CZ |
389 | /* CONST_INT / CONST_DOUBLE is fine, but the PIC CONST ([..] UNSPEC)) |
390 | constructs are effectively indexed. */ | |
391 | if (flag_pic) | |
392 | { | |
393 | rtx ad0 = addr; | |
394 | while (GET_CODE (ad0) == PLUS) | |
395 | ad0 = XEXP (ad0, 0); | |
396 | if (GET_CODE (ad0) == CONST || GET_CODE (ad0) == UNSPEC) | |
397 | return 0; | |
398 | } | |
526b7aee SV |
399 | return address_operand (addr, mode); |
400 | } | |
401 | default : | |
402 | return 0; | |
403 | } | |
404 | ||
405 | } | |
406 | ) | |
407 | ||
526b7aee SV |
408 | ;; Return true if OP is a non-volatile non-immediate operand. |
409 | ;; Volatile memory refs require a special "cache-bypass" instruction | |
410 | ;; and only the standard movXX patterns are set up to handle them. | |
411 | (define_predicate "nonvol_nonimm_operand" | |
412 | (and (match_code "subreg, reg, mem") | |
413 | (match_test "(GET_CODE (op) != MEM || !MEM_VOLATILE_P (op)) && nonimmediate_operand (op, mode)")) | |
414 | ) | |
415 | ||
416 | ;; Return 1 if OP is a comparison operator valid for the mode of CC. | |
417 | ;; This allows the use of MATCH_OPERATOR to recognize all the branch insns. | |
418 | ||
419 | (define_predicate "proper_comparison_operator" | |
420 | (match_code "eq, ne, le, lt, ge, gt, leu, ltu, geu, gtu, unordered, ordered, uneq, unge, ungt, unle, unlt, ltgt") | |
421 | { | |
422 | enum rtx_code code = GET_CODE (op); | |
423 | ||
424 | if (!COMPARISON_P (op)) | |
425 | return 0; | |
426 | ||
427 | /* After generic flag-setting insns, we can use eq / ne / pl / mi / pnz . | |
428 | There are some creative uses for hi / ls after shifts, but these are | |
429 | hard to understand for the compiler and could be at best the target of | |
430 | a peephole. */ | |
431 | switch (GET_MODE (XEXP (op, 0))) | |
432 | { | |
433 | case CC_ZNmode: | |
434 | return (code == EQ || code == NE || code == GE || code == LT | |
435 | || code == GT); | |
436 | case CC_Zmode: | |
437 | return code == EQ || code == NE; | |
438 | case CC_Cmode: | |
439 | return code == LTU || code == GEU; | |
440 | case CC_FP_GTmode: | |
441 | return code == GT || code == UNLE; | |
442 | case CC_FP_GEmode: | |
443 | return code == GE || code == UNLT; | |
444 | case CC_FP_ORDmode: | |
445 | return code == ORDERED || code == UNORDERED; | |
446 | case CC_FP_UNEQmode: | |
447 | return code == UNEQ || code == LTGT; | |
448 | case CC_FPXmode: | |
449 | return (code == EQ || code == NE || code == UNEQ || code == LTGT | |
450 | || code == ORDERED || code == UNORDERED); | |
451 | ||
8f3304d0 CZ |
452 | case CC_FPUmode: |
453 | return 1; | |
454 | case CC_FPU_UNEQmode: | |
455 | return 1; | |
456 | ||
526b7aee SV |
457 | case CCmode: |
458 | case SImode: /* Used for BRcc. */ | |
459 | return 1; | |
460 | /* From combiner. */ | |
461 | case QImode: case HImode: case DImode: case SFmode: case DFmode: | |
462 | return 0; | |
dfa654c8 CZ |
463 | case VOIDmode: |
464 | return 0; | |
526b7aee SV |
465 | default: |
466 | gcc_unreachable (); | |
467 | } | |
468 | }) | |
469 | ||
470 | (define_predicate "equality_comparison_operator" | |
471 | (match_code "eq, ne")) | |
472 | ||
e389ba30 AB |
473 | (define_predicate "ge_lt_comparison_operator" |
474 | (match_code "ge, lt")) | |
475 | ||
526b7aee SV |
476 | (define_predicate "brcc_nolimm_operator" |
477 | (ior (match_test "REG_P (XEXP (op, 1))") | |
478 | (and (match_code "eq, ne, lt, ge, ltu, geu") | |
4173ddaf | 479 | (match_test "CONST_INT_P (XEXP (op, 1))") |
526b7aee SV |
480 | (match_test "u6_immediate_operand (XEXP (op, 1), SImode)")) |
481 | (and (match_code "le, gt, leu, gtu") | |
4173ddaf | 482 | (match_test "CONST_INT_P (XEXP (op, 1))") |
526b7aee SV |
483 | (match_test "UNSIGNED_INT6 (INTVAL (XEXP (op, 1)) + 1)")))) |
484 | ||
485 | ;; Return TRUE if this is the condition code register, if we aren't given | |
486 | ;; a mode, accept any CCmode register | |
487 | (define_special_predicate "cc_register" | |
488 | (match_code "reg") | |
489 | { | |
490 | if (mode == VOIDmode) | |
491 | { | |
492 | mode = GET_MODE (op); | |
493 | if (GET_MODE_CLASS (mode) != MODE_CC) | |
494 | return FALSE; | |
495 | } | |
496 | ||
497 | if (mode == GET_MODE (op) && GET_CODE (op) == REG && REGNO (op) == CC_REG) | |
498 | return TRUE; | |
499 | ||
500 | return FALSE; | |
501 | }) | |
502 | ||
503 | ;; Return TRUE if this is the condition code register; if we aren't given | |
504 | ;; a mode, accept any CCmode register. If we are given a mode, accept | |
505 | ;; modes that set a subset of flags. | |
506 | (define_special_predicate "cc_set_register" | |
507 | (match_code "reg") | |
508 | { | |
ef4bddc2 | 509 | machine_mode rmode = GET_MODE (op); |
526b7aee SV |
510 | |
511 | if (mode == VOIDmode) | |
512 | { | |
513 | mode = rmode; | |
514 | if (GET_MODE_CLASS (mode) != MODE_CC) | |
515 | return FALSE; | |
516 | } | |
517 | ||
518 | if (REGNO (op) != 61) | |
519 | return FALSE; | |
520 | if (mode == rmode | |
521 | || (mode == CC_ZNmode && rmode == CC_Zmode) | |
522 | || (mode == CCmode && rmode == CC_Zmode) | |
523 | || (mode == CCmode && rmode == CC_ZNmode) | |
524 | || (mode == CCmode && rmode == CC_Cmode)) | |
525 | return TRUE; | |
526 | ||
527 | return FALSE; | |
528 | }) | |
529 | ||
530 | ; Accept CC_REG in modes which provide the flags needed for MODE. */ | |
531 | (define_special_predicate "cc_use_register" | |
532 | (match_code "reg") | |
533 | { | |
534 | if (REGNO (op) != CC_REG) | |
535 | return 0; | |
536 | if (GET_MODE (op) == mode) | |
537 | return 1; | |
538 | switch (mode) | |
539 | { | |
540 | case CC_Zmode: | |
541 | if (GET_MODE (op) == CC_ZNmode) | |
542 | return 1; | |
543 | /* Fall through. */ | |
544 | case CC_ZNmode: case CC_Cmode: | |
545 | return GET_MODE (op) == CCmode; | |
546 | default: | |
547 | gcc_unreachable (); | |
548 | } | |
549 | }) | |
550 | ||
551 | (define_special_predicate "zn_compare_operator" | |
552 | (match_code "compare") | |
553 | { | |
554 | return GET_MODE (op) == CC_ZNmode || GET_MODE (op) == CC_Zmode; | |
555 | }) | |
556 | ||
557 | ;; Return true if OP is a shift operator. | |
558 | (define_predicate "shift_operator" | |
559 | (match_code "ashiftrt, lshiftrt, ashift") | |
560 | ) | |
561 | ||
562 | ;; Return true if OP is a left shift operator that can be implemented in | |
563 | ;; four insn words or less without a barrel shifter or multiplier. | |
564 | (define_predicate "shiftl4_operator" | |
565 | (and (match_code "ashift") | |
566 | (match_test "const_int_operand (XEXP (op, 1), VOIDmode) ") | |
567 | (match_test "UINTVAL (XEXP (op, 1)) <= 9U | |
568 | || INTVAL (XEXP (op, 1)) == 29 | |
569 | || INTVAL (XEXP (op, 1)) == 30 | |
570 | || INTVAL (XEXP (op, 1)) == 31"))) | |
571 | ||
572 | ;; Return true if OP is a right shift operator that can be implemented in | |
573 | ;; four insn words or less without a barrel shifter or multiplier. | |
574 | (define_predicate "shiftr4_operator" | |
575 | (and (match_code "ashiftrt, lshiftrt") | |
576 | (match_test "const_int_operand (XEXP (op, 1), VOIDmode) ") | |
577 | (match_test "UINTVAL (XEXP (op, 1)) <= 4U | |
578 | || INTVAL (XEXP (op, 1)) == 30 | |
579 | || INTVAL (XEXP (op, 1)) == 31"))) | |
580 | ||
581 | ;; Return true if OP is a shift operator that can be implemented in | |
582 | ;; four insn words or less without a barrel shifter or multiplier. | |
583 | (define_predicate "shift4_operator" | |
584 | (ior (match_operand 0 "shiftl4_operator") | |
585 | (match_operand 0 "shiftr4_operator"))) | |
586 | ||
587 | (define_predicate "mult_operator" | |
f50bb868 | 588 | (and (match_code "mult") (match_test "TARGET_MPY")) |
526b7aee SV |
589 | ) |
590 | ||
591 | (define_predicate "commutative_operator" | |
592 | (ior (match_code "plus,ior,xor,and") | |
593 | (match_operand 0 "mult_operator") | |
594 | (and (match_code "ss_plus") | |
595 | (match_test "TARGET_ARC700 || TARGET_EA_SET"))) | |
596 | ) | |
597 | ||
598 | (define_predicate "commutative_operator_sans_mult" | |
599 | (ior (match_code "plus,ior,xor,and") | |
600 | (and (match_code "ss_plus") | |
601 | (match_test "TARGET_ARC700 || TARGET_EA_SET"))) | |
602 | ) | |
603 | ||
604 | (define_predicate "noncommutative_operator" | |
605 | (ior (match_code "minus,ashift,ashiftrt,lshiftrt,rotatert") | |
606 | (and (match_code "ss_minus") | |
607 | (match_test "TARGET_ARC700 || TARGET_EA_SET"))) | |
608 | ) | |
609 | ||
610 | (define_predicate "unary_operator" | |
611 | (ior (match_code "abs,neg,not,sign_extend,zero_extend") | |
612 | (and (ior (match_code "ss_neg") | |
613 | (and (match_code "ss_truncate") | |
614 | (match_test "GET_MODE (XEXP (op, 0)) == HImode"))) | |
615 | (match_test "TARGET_ARC700 || TARGET_EA_SET"))) | |
616 | ) | |
617 | ||
1e466f04 GM |
618 | (define_predicate "_1_2_3_operand" |
619 | (and (match_code "const_int") | |
620 | (match_test "INTVAL (op) == 1 || INTVAL (op) == 2 || INTVAL (op) == 3")) | |
621 | ) | |
622 | ||
526b7aee SV |
623 | (define_predicate "_2_4_8_operand" |
624 | (and (match_code "const_int") | |
625 | (match_test "INTVAL (op) == 2 || INTVAL (op) == 4 || INTVAL (op) == 8")) | |
626 | ) | |
627 | ||
628 | (define_predicate "arc_double_register_operand" | |
629 | (match_code "reg") | |
630 | { | |
631 | if ((GET_MODE (op) != mode) && (mode != VOIDmode)) | |
632 | return 0; | |
633 | ||
634 | return (GET_CODE (op) == REG | |
635 | && (REGNO (op) >= FIRST_PSEUDO_REGISTER | |
636 | || REGNO_REG_CLASS (REGNO (op)) == DOUBLE_REGS)); | |
637 | }) | |
638 | ||
639 | (define_predicate "shouldbe_register_operand" | |
640 | (match_code "reg,subreg,mem") | |
641 | { | |
642 | return ((reload_in_progress || reload_completed) | |
643 | ? general_operand : register_operand) (op, mode); | |
644 | }) | |
645 | ||
646 | (define_predicate "vector_register_operand" | |
647 | (match_code "reg") | |
648 | { | |
649 | if ((GET_MODE (op) != mode) && (mode != VOIDmode)) | |
650 | return 0; | |
651 | ||
652 | return (GET_CODE (op) == REG | |
653 | && (REGNO (op) >= FIRST_PSEUDO_REGISTER | |
654 | || REGNO_REG_CLASS (REGNO (op)) == SIMD_VR_REGS)); | |
655 | }) | |
656 | ||
657 | (define_predicate "vector_register_or_memory_operand" | |
658 | ( ior (match_code "reg") | |
659 | (match_code "mem")) | |
660 | { | |
661 | if ((GET_MODE (op) != mode) && (mode != VOIDmode)) | |
662 | return 0; | |
663 | ||
664 | if ((GET_CODE (op) == MEM) | |
665 | && (mode == V8HImode) | |
666 | && GET_CODE (XEXP (op,0)) == REG) | |
667 | return 1; | |
668 | ||
669 | return (GET_CODE (op) == REG | |
670 | && (REGNO (op) >= FIRST_PSEUDO_REGISTER | |
671 | || REGNO_REG_CLASS (REGNO (op)) == SIMD_VR_REGS)); | |
672 | }) | |
673 | ||
674 | (define_predicate "arc_dpfp_operator" | |
675 | (match_code "plus, mult,minus") | |
676 | ) | |
677 | ||
678 | (define_predicate "arc_simd_dma_register_operand" | |
679 | (match_code "reg") | |
680 | { | |
681 | if ((GET_MODE (op) != mode) && (mode != VOIDmode)) | |
682 | return 0; | |
683 | ||
684 | return (GET_CODE (op) == REG | |
685 | && (REGNO (op) >= FIRST_PSEUDO_REGISTER | |
686 | || REGNO_REG_CLASS (REGNO (op)) == SIMD_DMA_CONFIG_REGS)); | |
687 | }) | |
688 | ||
689 | (define_predicate "acc1_operand" | |
690 | (and (match_code "reg") | |
691 | (match_test "REGNO (op) == (TARGET_BIG_ENDIAN ? 56 : 57)"))) | |
692 | ||
693 | (define_predicate "acc2_operand" | |
694 | (and (match_code "reg") | |
695 | (match_test "REGNO (op) == (TARGET_BIG_ENDIAN ? 57 : 56)"))) | |
696 | ||
697 | (define_predicate "mlo_operand" | |
698 | (and (match_code "reg") | |
699 | (match_test "REGNO (op) == (TARGET_BIG_ENDIAN ? 59 : 58)"))) | |
700 | ||
701 | (define_predicate "mhi_operand" | |
702 | (and (match_code "reg") | |
703 | (match_test "REGNO (op) == (TARGET_BIG_ENDIAN ? 58 : 59)"))) | |
704 | ||
79557bae CZ |
705 | (define_predicate "accl_operand" |
706 | (and (match_code "reg") | |
707 | (match_test "REGNO (op) == (TARGET_BIG_ENDIAN ? 59 : 58)") | |
708 | (match_test "TARGET_V2"))) | |
709 | ||
167ba5b9 JR |
710 | ; Unfortunately, we can not allow a const_int_operand before reload, because |
711 | ; reload needs a non-void mode to guide it how to reload the inside of a | |
712 | ; {sign_}extend. | |
526b7aee | 713 | (define_predicate "extend_operand" |
167ba5b9 JR |
714 | (ior (match_operand 0 "register_operand") |
715 | (and (match_operand 0 "immediate_operand") | |
716 | (ior (not (match_operand 0 "const_int_operand")) | |
717 | (match_test "reload_in_progress || reload_completed"))))) | |
526b7aee SV |
718 | |
719 | (define_predicate "millicode_store_operation" | |
720 | (match_code "parallel") | |
721 | { | |
722 | return arc_check_millicode (op, 0, 0); | |
723 | }) | |
724 | ||
725 | (define_predicate "millicode_load_operation" | |
726 | (match_code "parallel") | |
727 | { | |
728 | return arc_check_millicode (op, 2, 2); | |
729 | }) | |
730 | ||
731 | (define_predicate "millicode_load_clob_operation" | |
732 | (match_code "parallel") | |
733 | { | |
734 | return arc_check_millicode (op, 0, 1); | |
735 | }) | |
736 | ||
737 | (define_special_predicate "immediate_usidi_operand" | |
738 | (if_then_else | |
739 | (match_code "const_int") | |
740 | (match_test "INTVAL (op) >= 0") | |
741 | (and (match_test "const_double_operand (op, mode)") | |
742 | (match_test "CONST_DOUBLE_HIGH (op) == 0")))) | |
f50bb868 CZ |
743 | |
744 | (define_predicate "short_const_int_operand" | |
745 | (and (match_operand 0 "const_int_operand") | |
746 | (match_test "satisfies_constraint_C16 (op)"))) | |
b8a64b7f CZ |
747 | |
748 | (define_predicate "mem_noofs_operand" | |
749 | (and (match_code "mem") | |
750 | (match_code "reg" "0"))) | |
0086bd99 AB |
751 | |
752 | (define_predicate "any_mem_operand" | |
d34a0fdc CZ |
753 | (match_code "mem")) |
754 | ||
755 | ; Special predicate to match even-odd double register pair | |
756 | (define_predicate "even_register_operand" | |
757 | (match_code "reg") | |
758 | { | |
759 | if ((GET_MODE (op) != mode) && (mode != VOIDmode)) | |
760 | return 0; | |
761 | ||
762 | return (REG_P (op) && ((REGNO (op) >= FIRST_PSEUDO_REGISTER) | |
763 | || ((REGNO (op) & 1) == 0))); | |
764 | }) | |
8f3304d0 CZ |
765 | |
766 | (define_predicate "double_register_operand" | |
767 | (ior (match_test "even_register_operand (op, mode)") | |
768 | (match_test "arc_double_register_operand (op, mode)"))) | |
4d03dc2f JR |
769 | |
770 | (define_predicate "cmem_address_0" | |
771 | (and (match_code "symbol_ref") | |
772 | (match_test "SYMBOL_REF_FLAGS (op) & SYMBOL_FLAG_CMEM"))) | |
773 | ||
774 | (define_predicate "cmem_address_1" | |
775 | (and (match_code "plus") | |
776 | (match_test "cmem_address_0 (XEXP (op, 0), SImode)"))) | |
777 | ||
778 | (define_predicate "cmem_address_2" | |
779 | (and (match_code "const") | |
780 | (match_test "cmem_address_1 (XEXP (op, 0), SImode)"))) | |
781 | ||
782 | (define_predicate "cmem_address" | |
783 | (ior (match_operand:SI 0 "cmem_address_0") | |
784 | (match_operand:SI 0 "cmem_address_1") | |
785 | (match_operand:SI 0 "cmem_address_2"))) | |
7132ae19 CZ |
786 | |
787 | (define_predicate "short_unsigned_const_operand" | |
788 | (and (match_code "const_int") | |
789 | (match_test "satisfies_constraint_J16 (op)"))) | |
790 | ||
791 | (define_predicate "arc_short_operand" | |
792 | (ior (match_test "register_operand (op, mode)") | |
793 | (match_test "short_unsigned_const_operand (op, mode)"))) |