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526b7aee | 1 | ;; Predicate definitions for Synopsys DesignWare ARC. |
818ab71a | 2 | ;; Copyright (C) 2007-2016 Free Software Foundation, Inc. |
526b7aee SV |
3 | ;; |
4 | ;; This file is part of GCC. | |
5 | ;; | |
6 | ;; GCC is free software; you can redistribute it and/or modify | |
7 | ;; it under the terms of the GNU General Public License as published by | |
8 | ;; the Free Software Foundation; either version 3, or (at your option) | |
9 | ;; any later version. | |
10 | ;; | |
11 | ;; GCC is distributed in the hope that it will be useful, | |
12 | ;; but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | ;; GNU General Public License for more details. | |
15 | ;; | |
16 | ;; You should have received a copy of the GNU General Public License | |
17 | ;; along with GCC; see the file COPYING3. If not see | |
18 | ;; <http://www.gnu.org/licenses/>. | |
19 | ||
20 | (define_predicate "dest_reg_operand" | |
21 | (match_code "reg,subreg") | |
22 | { | |
23 | rtx op0 = op; | |
24 | ||
25 | if (GET_CODE (op0) == SUBREG) | |
26 | op0 = SUBREG_REG (op0); | |
27 | if (REG_P (op0) && REGNO (op0) < FIRST_PSEUDO_REGISTER | |
28 | && TEST_HARD_REG_BIT (reg_class_contents[ALL_CORE_REGS], | |
29 | REGNO (op0)) | |
30 | && !TEST_HARD_REG_BIT (reg_class_contents[WRITABLE_CORE_REGS], | |
31 | REGNO (op0))) | |
32 | return 0; | |
33 | return register_operand (op, mode); | |
34 | }) | |
35 | ||
36 | (define_predicate "mpy_dest_reg_operand" | |
37 | (match_code "reg,subreg") | |
38 | { | |
39 | rtx op0 = op; | |
40 | ||
41 | if (GET_CODE (op0) == SUBREG) | |
42 | op0 = SUBREG_REG (op0); | |
43 | if (REG_P (op0) && REGNO (op0) < FIRST_PSEUDO_REGISTER | |
44 | && TEST_HARD_REG_BIT (reg_class_contents[ALL_CORE_REGS], | |
45 | REGNO (op0)) | |
46 | /* Make sure the destination register is not LP_COUNT. */ | |
47 | && !TEST_HARD_REG_BIT (reg_class_contents[MPY_WRITABLE_CORE_REGS], | |
48 | REGNO (op0))) | |
49 | return 0; | |
50 | return register_operand (op, mode); | |
51 | }) | |
52 | ||
53 | ||
54 | ;; Returns 1 if OP is a symbol reference. | |
55 | (define_predicate "symbolic_operand" | |
56 | (match_code "symbol_ref, label_ref, const") | |
57 | ) | |
58 | ||
59 | ;; Acceptable arguments to the call insn. | |
60 | (define_predicate "call_address_operand" | |
61 | (ior (match_code "const_int, reg") | |
62 | (match_operand 0 "symbolic_operand") | |
63 | (match_test "CONSTANT_P (op) | |
64 | && arc_legitimate_constant_p (VOIDmode, op)")) | |
65 | ) | |
66 | ||
67 | (define_predicate "call_operand" | |
68 | (and (match_code "mem") | |
69 | (match_test "call_address_operand (XEXP (op, 0), mode)")) | |
70 | ) | |
71 | ||
72 | ;; Return true if OP is a unsigned 6-bit immediate (u6) value. | |
73 | (define_predicate "u6_immediate_operand" | |
74 | (and (match_code "const_int") | |
75 | (match_test "UNSIGNED_INT6 (INTVAL (op))")) | |
76 | ) | |
77 | ||
78 | ;; Return true if OP is a short immediate (shimm) value. | |
79 | (define_predicate "short_immediate_operand" | |
80 | (and (match_code "const_int") | |
81 | (match_test "SMALL_INT (INTVAL (op))")) | |
82 | ) | |
83 | ||
84 | (define_predicate "p2_immediate_operand" | |
85 | (and (match_code "const_int") | |
86 | (match_test "((INTVAL (op) - 1) & INTVAL (op)) == 0") | |
87 | (match_test "INTVAL (op)")) | |
88 | ) | |
89 | ||
90 | ;; Return true if OP will require a long immediate (limm) value. | |
91 | ;; This is currently only used when calculating length attributes. | |
92 | (define_predicate "long_immediate_operand" | |
93 | (match_code "symbol_ref, label_ref, const, const_double, const_int") | |
94 | { | |
95 | switch (GET_CODE (op)) | |
96 | { | |
97 | case SYMBOL_REF : | |
98 | case LABEL_REF : | |
99 | case CONST : | |
100 | return 1; | |
101 | case CONST_INT : | |
102 | return !SIGNED_INT12 (INTVAL (op)); | |
103 | case CONST_DOUBLE : | |
104 | /* These can happen because large unsigned 32 bit constants are | |
105 | represented this way (the multiplication patterns can cause these | |
106 | to be generated). They also occur for SFmode values. */ | |
107 | return 1; | |
108 | default: | |
109 | break; | |
110 | } | |
111 | return 0; | |
112 | } | |
113 | ) | |
114 | ||
115 | ;; Return true if OP is a MEM that when used as a load or store address will | |
116 | ;; require an 8 byte insn. | |
117 | ;; Load and store instructions don't allow the same possibilities but they're | |
118 | ;; similar enough that this one function will do. | |
119 | ;; This is currently only used when calculating length attributes. */ | |
120 | (define_predicate "long_immediate_loadstore_operand" | |
121 | (match_code "mem") | |
122 | { | |
123 | int size = GET_MODE_SIZE (GET_MODE (op)); | |
124 | ||
125 | op = XEXP (op, 0); | |
4d03dc2f JR |
126 | if (TARGET_NPS_CMEM && cmem_address (op, SImode)) |
127 | return 0; | |
526b7aee SV |
128 | switch (GET_CODE (op)) |
129 | { | |
130 | case SYMBOL_REF : | |
131 | case LABEL_REF : | |
132 | case CONST : | |
133 | return 1; | |
134 | case CONST_INT : | |
135 | /* This must be handled as "st c,[limm]". Ditto for load. | |
136 | Technically, the assembler could translate some possibilities to | |
137 | "st c,[limm/2 + limm/2]" if limm/2 will fit in a shimm, but we don't | |
138 | assume that it does. */ | |
139 | return 1; | |
140 | case CONST_DOUBLE : | |
141 | /* These can happen because large unsigned 32 bit constants are | |
142 | represented this way (the multiplication patterns can cause these | |
143 | to be generated). They also occur for SFmode values. */ | |
144 | return 1; | |
145 | case REG : | |
146 | return 0; | |
147 | case PLUS : | |
148 | { | |
149 | rtx x = XEXP (op, 1); | |
150 | ||
151 | if (GET_CODE (x) == CONST) | |
152 | { | |
153 | x = XEXP (x, 0); | |
154 | if (GET_CODE (x) == PLUS) | |
155 | x = XEXP (x, 0); | |
156 | } | |
157 | if (CONST_INT_P (x)) | |
158 | return (!SMALL_INT (INTVAL (x)) | |
159 | && (size <= 1 || size > 4 | |
160 | || (INTVAL (x) & (size - 1)) != 0 | |
161 | || !SMALL_INT (INTVAL (x) / size))); | |
162 | else if (GET_CODE (x) == SYMBOL_REF) | |
163 | return TARGET_NO_SDATA_SET || !SYMBOL_REF_SMALL_P (x); | |
164 | return 0; | |
165 | } | |
166 | default: | |
167 | break; | |
168 | } | |
169 | return 0; | |
170 | } | |
171 | ) | |
172 | ||
173 | ;; Return true if OP is any of R0-R3,R12-R15 for ARCompact 16-bit | |
174 | ;; instructions | |
175 | (define_predicate "compact_register_operand" | |
176 | (match_code "reg, subreg") | |
177 | { | |
178 | if ((GET_MODE (op) != mode) && (mode != VOIDmode)) | |
179 | return 0; | |
180 | ||
181 | return (GET_CODE (op) == REG) | |
182 | && (REGNO (op) >= FIRST_PSEUDO_REGISTER | |
183 | || COMPACT_GP_REG_P (REGNO (op))) ; | |
184 | } | |
185 | ) | |
186 | ||
526b7aee SV |
187 | ;; Return true if OP is an acceptable memory operand for ARCompact |
188 | ;; 16-bit store instructions | |
189 | (define_predicate "compact_store_memory_operand" | |
190 | (match_code "mem") | |
191 | { | |
192 | rtx addr, plus0, plus1; | |
193 | int size, off; | |
194 | ||
195 | if (mode == VOIDmode) | |
196 | mode = GET_MODE (op); | |
197 | ||
198 | /* .di instructions have no 16-bit form. */ | |
199 | if (MEM_VOLATILE_P (op) && !TARGET_VOLATILE_CACHE_SET) | |
200 | return 0; | |
201 | ||
202 | size = GET_MODE_SIZE (mode); | |
203 | ||
204 | /* dword operations really put out 2 instructions, so eliminate them. */ | |
205 | if (size > UNITS_PER_WORD) | |
206 | return 0; | |
207 | ||
208 | /* Decode the address now. */ | |
209 | addr = XEXP (op, 0); | |
210 | switch (GET_CODE (addr)) | |
211 | { | |
212 | case REG: | |
213 | return (REGNO (addr) >= FIRST_PSEUDO_REGISTER | |
214 | || COMPACT_GP_REG_P (REGNO (addr)) | |
215 | || (SP_REG_P (REGNO (addr)) && (size != 2))); | |
216 | /* stw_s does not support SP as a parameter. */ | |
217 | case PLUS: | |
218 | plus0 = XEXP (addr, 0); | |
219 | plus1 = XEXP (addr, 1); | |
220 | ||
221 | if ((GET_CODE (plus0) == REG) | |
222 | && ((REGNO (plus0) >= FIRST_PSEUDO_REGISTER) | |
223 | || COMPACT_GP_REG_P (REGNO (plus0))) | |
224 | && (GET_CODE (plus1) == CONST_INT)) | |
225 | { | |
226 | off = INTVAL (plus1); | |
227 | ||
228 | /* Negative offset is not supported in 16-bit load/store insns. */ | |
229 | if (off < 0) | |
230 | return 0; | |
231 | ||
232 | switch (size) | |
233 | { | |
234 | case 1: | |
235 | return (off < 32); | |
236 | case 2: | |
237 | return ((off < 64) && (off % 2 == 0)); | |
238 | case 4: | |
239 | return ((off < 128) && (off % 4 == 0)); | |
240 | } | |
241 | } | |
242 | ||
243 | if ((GET_CODE (plus0) == REG) | |
244 | && ((REGNO (plus0) >= FIRST_PSEUDO_REGISTER) | |
245 | || SP_REG_P (REGNO (plus0))) | |
246 | && (GET_CODE (plus1) == CONST_INT)) | |
247 | { | |
248 | off = INTVAL (plus1); | |
249 | ||
250 | return ((size != 2) && (off >= 0 && off < 128) && (off % 4 == 0)); | |
251 | } | |
252 | default: | |
253 | break; | |
254 | } | |
255 | return 0; | |
256 | } | |
257 | ) | |
258 | ||
259 | ;; Return true if OP is an acceptable argument for a single word | |
260 | ;; move source. | |
261 | (define_predicate "move_src_operand" | |
262 | (match_code "symbol_ref, label_ref, const, const_int, const_double, reg, subreg, mem") | |
263 | { | |
264 | switch (GET_CODE (op)) | |
265 | { | |
266 | case SYMBOL_REF : | |
28633bbd CZ |
267 | if (SYMBOL_REF_TLS_MODEL (op)) |
268 | return 0; | |
3bbe0b82 | 269 | return 1; |
526b7aee | 270 | case LABEL_REF : |
28633bbd | 271 | return 1; |
526b7aee | 272 | case CONST : |
28633bbd | 273 | return arc_legitimate_constant_p (mode, op); |
526b7aee SV |
274 | case CONST_INT : |
275 | return (LARGE_INT (INTVAL (op))); | |
276 | case CONST_DOUBLE : | |
277 | /* We can handle DImode integer constants in SImode if the value | |
278 | (signed or unsigned) will fit in 32 bits. This is needed because | |
279 | large unsigned 32 bit constants are represented as CONST_DOUBLEs. */ | |
280 | if (mode == SImode) | |
281 | return arc_double_limm_p (op); | |
282 | /* We can handle 32 bit floating point constants. */ | |
283 | if (mode == SFmode) | |
284 | return GET_MODE (op) == SFmode; | |
285 | return 0; | |
286 | case REG : | |
287 | return register_operand (op, mode); | |
288 | case SUBREG : | |
289 | /* (subreg (mem ...) ...) can occur here if the inner part was once a | |
290 | pseudo-reg and is now a stack slot. */ | |
291 | if (GET_CODE (SUBREG_REG (op)) == MEM) | |
292 | return address_operand (XEXP (SUBREG_REG (op), 0), mode); | |
293 | else | |
294 | return register_operand (op, mode); | |
295 | case MEM : | |
296 | return address_operand (XEXP (op, 0), mode); | |
297 | default : | |
298 | return 0; | |
299 | } | |
300 | } | |
301 | ) | |
302 | ||
303 | ;; Return true if OP is an acceptable argument for a double word | |
304 | ;; move source. | |
305 | (define_predicate "move_double_src_operand" | |
306 | (match_code "reg, subreg, mem, const_int, const_double") | |
307 | { | |
308 | switch (GET_CODE (op)) | |
309 | { | |
310 | case REG : | |
311 | return register_operand (op, mode); | |
312 | case SUBREG : | |
313 | /* (subreg (mem ...) ...) can occur here if the inner part was once a | |
314 | pseudo-reg and is now a stack slot. */ | |
315 | if (GET_CODE (SUBREG_REG (op)) == MEM) | |
316 | return move_double_src_operand (SUBREG_REG (op), mode); | |
317 | else | |
318 | return register_operand (op, mode); | |
319 | case MEM : | |
320 | return address_operand (XEXP (op, 0), mode); | |
321 | case CONST_INT : | |
322 | case CONST_DOUBLE : | |
323 | return 1; | |
324 | default : | |
325 | return 0; | |
326 | } | |
327 | } | |
328 | ) | |
329 | ||
330 | ;; Return true if OP is an acceptable argument for a move destination. | |
331 | (define_predicate "move_dest_operand" | |
332 | (match_code "reg, subreg, mem") | |
333 | { | |
334 | switch (GET_CODE (op)) | |
335 | { | |
336 | case REG : | |
337 | /* Program Counter register cannot be the target of a move. It is | |
338 | a readonly register. */ | |
339 | if (REGNO (op) == PROGRAM_COUNTER_REGNO) | |
340 | return 0; | |
341 | else if (TARGET_MULMAC_32BY16_SET | |
342 | && (REGNO (op) == 56 || REGNO(op) == 57)) | |
343 | return 0; | |
344 | else if (TARGET_MUL64_SET | |
345 | && (REGNO (op) == 57 || REGNO(op) == 58 || REGNO(op) == 59 )) | |
346 | return 0; | |
347 | else | |
348 | return dest_reg_operand (op, mode); | |
349 | case SUBREG : | |
350 | /* (subreg (mem ...) ...) can occur here if the inner part was once a | |
351 | pseudo-reg and is now a stack slot. */ | |
352 | if (GET_CODE (SUBREG_REG (op)) == MEM) | |
353 | return address_operand (XEXP (SUBREG_REG (op), 0), mode); | |
354 | else | |
355 | return dest_reg_operand (op, mode); | |
356 | case MEM : | |
357 | { | |
358 | rtx addr = XEXP (op, 0); | |
359 | ||
360 | if (GET_CODE (addr) == PLUS | |
361 | && (GET_CODE (XEXP (addr, 0)) == MULT | |
362 | || (!CONST_INT_P (XEXP (addr, 1)) | |
363 | && (TARGET_NO_SDATA_SET | |
364 | || GET_CODE (XEXP (addr, 1)) != SYMBOL_REF | |
365 | || !SYMBOL_REF_SMALL_P (XEXP (addr, 1)))))) | |
366 | return 0; | |
367 | if ((GET_CODE (addr) == PRE_MODIFY || GET_CODE (addr) == POST_MODIFY) | |
368 | && (GET_CODE (XEXP (addr, 1)) != PLUS | |
369 | || !CONST_INT_P (XEXP (XEXP (addr, 1), 1)))) | |
370 | return 0; | |
28633bbd CZ |
371 | /* CONST_INT / CONST_DOUBLE is fine, but the PIC CONST ([..] UNSPEC)) |
372 | constructs are effectively indexed. */ | |
373 | if (flag_pic) | |
374 | { | |
375 | rtx ad0 = addr; | |
376 | while (GET_CODE (ad0) == PLUS) | |
377 | ad0 = XEXP (ad0, 0); | |
378 | if (GET_CODE (ad0) == CONST || GET_CODE (ad0) == UNSPEC) | |
379 | return 0; | |
380 | } | |
526b7aee SV |
381 | return address_operand (addr, mode); |
382 | } | |
383 | default : | |
384 | return 0; | |
385 | } | |
386 | ||
387 | } | |
388 | ) | |
389 | ||
526b7aee SV |
390 | ;; Return true if OP is a non-volatile non-immediate operand. |
391 | ;; Volatile memory refs require a special "cache-bypass" instruction | |
392 | ;; and only the standard movXX patterns are set up to handle them. | |
393 | (define_predicate "nonvol_nonimm_operand" | |
394 | (and (match_code "subreg, reg, mem") | |
395 | (match_test "(GET_CODE (op) != MEM || !MEM_VOLATILE_P (op)) && nonimmediate_operand (op, mode)")) | |
396 | ) | |
397 | ||
398 | ;; Return 1 if OP is a comparison operator valid for the mode of CC. | |
399 | ;; This allows the use of MATCH_OPERATOR to recognize all the branch insns. | |
400 | ||
401 | (define_predicate "proper_comparison_operator" | |
402 | (match_code "eq, ne, le, lt, ge, gt, leu, ltu, geu, gtu, unordered, ordered, uneq, unge, ungt, unle, unlt, ltgt") | |
403 | { | |
404 | enum rtx_code code = GET_CODE (op); | |
405 | ||
406 | if (!COMPARISON_P (op)) | |
407 | return 0; | |
408 | ||
409 | /* After generic flag-setting insns, we can use eq / ne / pl / mi / pnz . | |
410 | There are some creative uses for hi / ls after shifts, but these are | |
411 | hard to understand for the compiler and could be at best the target of | |
412 | a peephole. */ | |
413 | switch (GET_MODE (XEXP (op, 0))) | |
414 | { | |
415 | case CC_ZNmode: | |
416 | return (code == EQ || code == NE || code == GE || code == LT | |
417 | || code == GT); | |
418 | case CC_Zmode: | |
419 | return code == EQ || code == NE; | |
420 | case CC_Cmode: | |
421 | return code == LTU || code == GEU; | |
422 | case CC_FP_GTmode: | |
423 | return code == GT || code == UNLE; | |
424 | case CC_FP_GEmode: | |
425 | return code == GE || code == UNLT; | |
426 | case CC_FP_ORDmode: | |
427 | return code == ORDERED || code == UNORDERED; | |
428 | case CC_FP_UNEQmode: | |
429 | return code == UNEQ || code == LTGT; | |
430 | case CC_FPXmode: | |
431 | return (code == EQ || code == NE || code == UNEQ || code == LTGT | |
432 | || code == ORDERED || code == UNORDERED); | |
433 | ||
8f3304d0 CZ |
434 | case CC_FPUmode: |
435 | return 1; | |
436 | case CC_FPU_UNEQmode: | |
437 | return 1; | |
438 | ||
526b7aee SV |
439 | case CCmode: |
440 | case SImode: /* Used for BRcc. */ | |
441 | return 1; | |
442 | /* From combiner. */ | |
443 | case QImode: case HImode: case DImode: case SFmode: case DFmode: | |
444 | return 0; | |
dfa654c8 CZ |
445 | case VOIDmode: |
446 | return 0; | |
526b7aee SV |
447 | default: |
448 | gcc_unreachable (); | |
449 | } | |
450 | }) | |
451 | ||
452 | (define_predicate "equality_comparison_operator" | |
453 | (match_code "eq, ne")) | |
454 | ||
e389ba30 AB |
455 | (define_predicate "ge_lt_comparison_operator" |
456 | (match_code "ge, lt")) | |
457 | ||
526b7aee SV |
458 | (define_predicate "brcc_nolimm_operator" |
459 | (ior (match_test "REG_P (XEXP (op, 1))") | |
460 | (and (match_code "eq, ne, lt, ge, ltu, geu") | |
461 | (match_test "u6_immediate_operand (XEXP (op, 1), SImode)")) | |
462 | (and (match_code "le, gt, leu, gtu") | |
463 | (match_test "UNSIGNED_INT6 (INTVAL (XEXP (op, 1)) + 1)")))) | |
464 | ||
465 | ;; Return TRUE if this is the condition code register, if we aren't given | |
466 | ;; a mode, accept any CCmode register | |
467 | (define_special_predicate "cc_register" | |
468 | (match_code "reg") | |
469 | { | |
470 | if (mode == VOIDmode) | |
471 | { | |
472 | mode = GET_MODE (op); | |
473 | if (GET_MODE_CLASS (mode) != MODE_CC) | |
474 | return FALSE; | |
475 | } | |
476 | ||
477 | if (mode == GET_MODE (op) && GET_CODE (op) == REG && REGNO (op) == CC_REG) | |
478 | return TRUE; | |
479 | ||
480 | return FALSE; | |
481 | }) | |
482 | ||
483 | ;; Return TRUE if this is the condition code register; if we aren't given | |
484 | ;; a mode, accept any CCmode register. If we are given a mode, accept | |
485 | ;; modes that set a subset of flags. | |
486 | (define_special_predicate "cc_set_register" | |
487 | (match_code "reg") | |
488 | { | |
ef4bddc2 | 489 | machine_mode rmode = GET_MODE (op); |
526b7aee SV |
490 | |
491 | if (mode == VOIDmode) | |
492 | { | |
493 | mode = rmode; | |
494 | if (GET_MODE_CLASS (mode) != MODE_CC) | |
495 | return FALSE; | |
496 | } | |
497 | ||
498 | if (REGNO (op) != 61) | |
499 | return FALSE; | |
500 | if (mode == rmode | |
501 | || (mode == CC_ZNmode && rmode == CC_Zmode) | |
502 | || (mode == CCmode && rmode == CC_Zmode) | |
503 | || (mode == CCmode && rmode == CC_ZNmode) | |
504 | || (mode == CCmode && rmode == CC_Cmode)) | |
505 | return TRUE; | |
506 | ||
507 | return FALSE; | |
508 | }) | |
509 | ||
510 | ; Accept CC_REG in modes which provide the flags needed for MODE. */ | |
511 | (define_special_predicate "cc_use_register" | |
512 | (match_code "reg") | |
513 | { | |
514 | if (REGNO (op) != CC_REG) | |
515 | return 0; | |
516 | if (GET_MODE (op) == mode) | |
517 | return 1; | |
518 | switch (mode) | |
519 | { | |
520 | case CC_Zmode: | |
521 | if (GET_MODE (op) == CC_ZNmode) | |
522 | return 1; | |
523 | /* Fall through. */ | |
524 | case CC_ZNmode: case CC_Cmode: | |
525 | return GET_MODE (op) == CCmode; | |
526 | default: | |
527 | gcc_unreachable (); | |
528 | } | |
529 | }) | |
530 | ||
531 | (define_special_predicate "zn_compare_operator" | |
532 | (match_code "compare") | |
533 | { | |
534 | return GET_MODE (op) == CC_ZNmode || GET_MODE (op) == CC_Zmode; | |
535 | }) | |
536 | ||
537 | ;; Return true if OP is a shift operator. | |
538 | (define_predicate "shift_operator" | |
539 | (match_code "ashiftrt, lshiftrt, ashift") | |
540 | ) | |
541 | ||
542 | ;; Return true if OP is a left shift operator that can be implemented in | |
543 | ;; four insn words or less without a barrel shifter or multiplier. | |
544 | (define_predicate "shiftl4_operator" | |
545 | (and (match_code "ashift") | |
546 | (match_test "const_int_operand (XEXP (op, 1), VOIDmode) ") | |
547 | (match_test "UINTVAL (XEXP (op, 1)) <= 9U | |
548 | || INTVAL (XEXP (op, 1)) == 29 | |
549 | || INTVAL (XEXP (op, 1)) == 30 | |
550 | || INTVAL (XEXP (op, 1)) == 31"))) | |
551 | ||
552 | ;; Return true if OP is a right shift operator that can be implemented in | |
553 | ;; four insn words or less without a barrel shifter or multiplier. | |
554 | (define_predicate "shiftr4_operator" | |
555 | (and (match_code "ashiftrt, lshiftrt") | |
556 | (match_test "const_int_operand (XEXP (op, 1), VOIDmode) ") | |
557 | (match_test "UINTVAL (XEXP (op, 1)) <= 4U | |
558 | || INTVAL (XEXP (op, 1)) == 30 | |
559 | || INTVAL (XEXP (op, 1)) == 31"))) | |
560 | ||
561 | ;; Return true if OP is a shift operator that can be implemented in | |
562 | ;; four insn words or less without a barrel shifter or multiplier. | |
563 | (define_predicate "shift4_operator" | |
564 | (ior (match_operand 0 "shiftl4_operator") | |
565 | (match_operand 0 "shiftr4_operator"))) | |
566 | ||
567 | (define_predicate "mult_operator" | |
f50bb868 | 568 | (and (match_code "mult") (match_test "TARGET_MPY")) |
526b7aee SV |
569 | ) |
570 | ||
571 | (define_predicate "commutative_operator" | |
572 | (ior (match_code "plus,ior,xor,and") | |
573 | (match_operand 0 "mult_operator") | |
574 | (and (match_code "ss_plus") | |
575 | (match_test "TARGET_ARC700 || TARGET_EA_SET"))) | |
576 | ) | |
577 | ||
578 | (define_predicate "commutative_operator_sans_mult" | |
579 | (ior (match_code "plus,ior,xor,and") | |
580 | (and (match_code "ss_plus") | |
581 | (match_test "TARGET_ARC700 || TARGET_EA_SET"))) | |
582 | ) | |
583 | ||
584 | (define_predicate "noncommutative_operator" | |
585 | (ior (match_code "minus,ashift,ashiftrt,lshiftrt,rotatert") | |
586 | (and (match_code "ss_minus") | |
587 | (match_test "TARGET_ARC700 || TARGET_EA_SET"))) | |
588 | ) | |
589 | ||
590 | (define_predicate "unary_operator" | |
591 | (ior (match_code "abs,neg,not,sign_extend,zero_extend") | |
592 | (and (ior (match_code "ss_neg") | |
593 | (and (match_code "ss_truncate") | |
594 | (match_test "GET_MODE (XEXP (op, 0)) == HImode"))) | |
595 | (match_test "TARGET_ARC700 || TARGET_EA_SET"))) | |
596 | ) | |
597 | ||
598 | (define_predicate "_2_4_8_operand" | |
599 | (and (match_code "const_int") | |
600 | (match_test "INTVAL (op) == 2 || INTVAL (op) == 4 || INTVAL (op) == 8")) | |
601 | ) | |
602 | ||
603 | (define_predicate "arc_double_register_operand" | |
604 | (match_code "reg") | |
605 | { | |
606 | if ((GET_MODE (op) != mode) && (mode != VOIDmode)) | |
607 | return 0; | |
608 | ||
609 | return (GET_CODE (op) == REG | |
610 | && (REGNO (op) >= FIRST_PSEUDO_REGISTER | |
611 | || REGNO_REG_CLASS (REGNO (op)) == DOUBLE_REGS)); | |
612 | }) | |
613 | ||
614 | (define_predicate "shouldbe_register_operand" | |
615 | (match_code "reg,subreg,mem") | |
616 | { | |
617 | return ((reload_in_progress || reload_completed) | |
618 | ? general_operand : register_operand) (op, mode); | |
619 | }) | |
620 | ||
621 | (define_predicate "vector_register_operand" | |
622 | (match_code "reg") | |
623 | { | |
624 | if ((GET_MODE (op) != mode) && (mode != VOIDmode)) | |
625 | return 0; | |
626 | ||
627 | return (GET_CODE (op) == REG | |
628 | && (REGNO (op) >= FIRST_PSEUDO_REGISTER | |
629 | || REGNO_REG_CLASS (REGNO (op)) == SIMD_VR_REGS)); | |
630 | }) | |
631 | ||
632 | (define_predicate "vector_register_or_memory_operand" | |
633 | ( ior (match_code "reg") | |
634 | (match_code "mem")) | |
635 | { | |
636 | if ((GET_MODE (op) != mode) && (mode != VOIDmode)) | |
637 | return 0; | |
638 | ||
639 | if ((GET_CODE (op) == MEM) | |
640 | && (mode == V8HImode) | |
641 | && GET_CODE (XEXP (op,0)) == REG) | |
642 | return 1; | |
643 | ||
644 | return (GET_CODE (op) == REG | |
645 | && (REGNO (op) >= FIRST_PSEUDO_REGISTER | |
646 | || REGNO_REG_CLASS (REGNO (op)) == SIMD_VR_REGS)); | |
647 | }) | |
648 | ||
649 | (define_predicate "arc_dpfp_operator" | |
650 | (match_code "plus, mult,minus") | |
651 | ) | |
652 | ||
653 | (define_predicate "arc_simd_dma_register_operand" | |
654 | (match_code "reg") | |
655 | { | |
656 | if ((GET_MODE (op) != mode) && (mode != VOIDmode)) | |
657 | return 0; | |
658 | ||
659 | return (GET_CODE (op) == REG | |
660 | && (REGNO (op) >= FIRST_PSEUDO_REGISTER | |
661 | || REGNO_REG_CLASS (REGNO (op)) == SIMD_DMA_CONFIG_REGS)); | |
662 | }) | |
663 | ||
664 | (define_predicate "acc1_operand" | |
665 | (and (match_code "reg") | |
666 | (match_test "REGNO (op) == (TARGET_BIG_ENDIAN ? 56 : 57)"))) | |
667 | ||
668 | (define_predicate "acc2_operand" | |
669 | (and (match_code "reg") | |
670 | (match_test "REGNO (op) == (TARGET_BIG_ENDIAN ? 57 : 56)"))) | |
671 | ||
672 | (define_predicate "mlo_operand" | |
673 | (and (match_code "reg") | |
674 | (match_test "REGNO (op) == (TARGET_BIG_ENDIAN ? 59 : 58)"))) | |
675 | ||
676 | (define_predicate "mhi_operand" | |
677 | (and (match_code "reg") | |
678 | (match_test "REGNO (op) == (TARGET_BIG_ENDIAN ? 58 : 59)"))) | |
679 | ||
167ba5b9 JR |
680 | ; Unfortunately, we can not allow a const_int_operand before reload, because |
681 | ; reload needs a non-void mode to guide it how to reload the inside of a | |
682 | ; {sign_}extend. | |
526b7aee | 683 | (define_predicate "extend_operand" |
167ba5b9 JR |
684 | (ior (match_operand 0 "register_operand") |
685 | (and (match_operand 0 "immediate_operand") | |
686 | (ior (not (match_operand 0 "const_int_operand")) | |
687 | (match_test "reload_in_progress || reload_completed"))))) | |
526b7aee SV |
688 | |
689 | (define_predicate "millicode_store_operation" | |
690 | (match_code "parallel") | |
691 | { | |
692 | return arc_check_millicode (op, 0, 0); | |
693 | }) | |
694 | ||
695 | (define_predicate "millicode_load_operation" | |
696 | (match_code "parallel") | |
697 | { | |
698 | return arc_check_millicode (op, 2, 2); | |
699 | }) | |
700 | ||
701 | (define_predicate "millicode_load_clob_operation" | |
702 | (match_code "parallel") | |
703 | { | |
704 | return arc_check_millicode (op, 0, 1); | |
705 | }) | |
706 | ||
707 | (define_special_predicate "immediate_usidi_operand" | |
708 | (if_then_else | |
709 | (match_code "const_int") | |
710 | (match_test "INTVAL (op) >= 0") | |
711 | (and (match_test "const_double_operand (op, mode)") | |
712 | (match_test "CONST_DOUBLE_HIGH (op) == 0")))) | |
f50bb868 CZ |
713 | |
714 | (define_predicate "short_const_int_operand" | |
715 | (and (match_operand 0 "const_int_operand") | |
716 | (match_test "satisfies_constraint_C16 (op)"))) | |
b8a64b7f CZ |
717 | |
718 | (define_predicate "mem_noofs_operand" | |
719 | (and (match_code "mem") | |
720 | (match_code "reg" "0"))) | |
0086bd99 AB |
721 | |
722 | (define_predicate "any_mem_operand" | |
d34a0fdc CZ |
723 | (match_code "mem")) |
724 | ||
725 | ; Special predicate to match even-odd double register pair | |
726 | (define_predicate "even_register_operand" | |
727 | (match_code "reg") | |
728 | { | |
729 | if ((GET_MODE (op) != mode) && (mode != VOIDmode)) | |
730 | return 0; | |
731 | ||
732 | return (REG_P (op) && ((REGNO (op) >= FIRST_PSEUDO_REGISTER) | |
733 | || ((REGNO (op) & 1) == 0))); | |
734 | }) | |
8f3304d0 CZ |
735 | |
736 | (define_predicate "double_register_operand" | |
737 | (ior (match_test "even_register_operand (op, mode)") | |
738 | (match_test "arc_double_register_operand (op, mode)"))) | |
4d03dc2f JR |
739 | |
740 | (define_predicate "cmem_address_0" | |
741 | (and (match_code "symbol_ref") | |
742 | (match_test "SYMBOL_REF_FLAGS (op) & SYMBOL_FLAG_CMEM"))) | |
743 | ||
744 | (define_predicate "cmem_address_1" | |
745 | (and (match_code "plus") | |
746 | (match_test "cmem_address_0 (XEXP (op, 0), SImode)"))) | |
747 | ||
748 | (define_predicate "cmem_address_2" | |
749 | (and (match_code "const") | |
750 | (match_test "cmem_address_1 (XEXP (op, 0), SImode)"))) | |
751 | ||
752 | (define_predicate "cmem_address" | |
753 | (ior (match_operand:SI 0 "cmem_address_0") | |
754 | (match_operand:SI 0 "cmem_address_1") | |
755 | (match_operand:SI 0 "cmem_address_2"))) | |
7132ae19 CZ |
756 | |
757 | (define_predicate "short_unsigned_const_operand" | |
758 | (and (match_code "const_int") | |
759 | (match_test "satisfies_constraint_J16 (op)"))) | |
760 | ||
761 | (define_predicate "arc_short_operand" | |
762 | (ior (match_test "register_operand (op, mode)") | |
763 | (match_test "short_unsigned_const_operand (op, mode)"))) |