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8f67eb82 | 1 | /* Functions and structures shared between arm and aarch64. |
015adf41 | 2 | |
fbd26352 | 3 | Copyright (C) 1991-2019 Free Software Foundation, Inc. |
015adf41 | 4 | Contributed by ARM Ltd. |
5 | ||
6 | This file is part of GCC. | |
7 | ||
8 | GCC is free software; you can redistribute it and/or modify it | |
9 | under the terms of the GNU General Public License as published | |
10 | by the Free Software Foundation; either version 3, or (at your | |
11 | option) any later version. | |
12 | ||
13 | GCC is distributed in the hope that it will be useful, but WITHOUT | |
14 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
15 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
16 | License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with GCC; see the file COPYING3. If not see | |
20 | <http://www.gnu.org/licenses/>. */ | |
21 | ||
22 | ||
23 | #ifndef GCC_AARCH_COMMON_PROTOS_H | |
24 | #define GCC_AARCH_COMMON_PROTOS_H | |
25 | ||
08993ad1 | 26 | extern int aarch_accumulator_forwarding (rtx_insn *, rtx_insn *); |
50fc2d35 | 27 | extern int aarch_crypto_can_dual_issue (rtx_insn *, rtx_insn *); |
d049924d | 28 | extern bool aarch_rev16_p (rtx); |
3754d046 | 29 | extern bool aarch_rev16_shleft_mask_imm_p (rtx, machine_mode); |
30 | extern bool aarch_rev16_shright_mask_imm_p (rtx, machine_mode); | |
50bfed1c | 31 | extern bool aarch_mm_needs_acquire (rtx); |
32 | extern bool aarch_mm_needs_release (rtx); | |
015adf41 | 33 | extern int arm_early_load_addr_dep (rtx, rtx); |
441e8134 | 34 | extern int arm_early_load_addr_dep_ptr (rtx, rtx); |
015adf41 | 35 | extern int arm_early_store_addr_dep (rtx, rtx); |
441e8134 | 36 | extern int arm_early_store_addr_dep_ptr (rtx, rtx); |
015adf41 | 37 | extern int arm_mac_accumulator_is_mul_result (rtx, rtx); |
38 | extern int arm_mac_accumulator_is_result (rtx, rtx); | |
39 | extern int arm_no_early_alu_shift_dep (rtx, rtx); | |
40 | extern int arm_no_early_alu_shift_value_dep (rtx, rtx); | |
41 | extern int arm_no_early_mul_dep (rtx, rtx); | |
42 | extern int arm_no_early_store_addr_dep (rtx, rtx); | |
daac2ec8 | 43 | extern bool arm_rtx_shift_left_p (rtx); |
015adf41 | 44 | |
8f67eb82 | 45 | /* RTX cost table definitions. These are used when tuning for speed rather |
46 | than for size and should reflect the _additional_ cost over the cost | |
47 | of the fastest instruction in the machine, which is COSTS_N_INSNS (1). | |
48 | Therefore it's okay for some costs to be 0. | |
49 | Costs may not have a negative value. */ | |
50 | struct alu_cost_table | |
51 | { | |
52 | const int arith; /* ADD/SUB. */ | |
53 | const int logical; /* AND/ORR/EOR/BIC, etc. */ | |
54 | const int shift; /* Simple shift. */ | |
55 | const int shift_reg; /* Simple shift by reg. */ | |
56 | const int arith_shift; /* Additional when arith also shifts... */ | |
57 | const int arith_shift_reg; /* ... and when the shift is by a reg. */ | |
58 | const int log_shift; /* Additional when logic also shifts... */ | |
59 | const int log_shift_reg; /* ... and when the shift is by a reg. */ | |
cde4685b | 60 | const int extend; /* Zero/sign extension. */ |
61 | const int extend_arith; /* Extend and arith. */ | |
8f67eb82 | 62 | const int bfi; /* Bit-field insert. */ |
63 | const int bfx; /* Bit-field extraction. */ | |
64 | const int clz; /* Count Leading Zeros. */ | |
3ee55116 | 65 | const int rev; /* Reverse bits/bytes. */ |
8f67eb82 | 66 | const int non_exec; /* Extra cost when not executing insn. */ |
67 | const bool non_exec_costs_exec; /* True if non-execution must add the exec | |
68 | cost. */ | |
69 | }; | |
70 | ||
71 | struct mult_cost_table | |
72 | { | |
73 | const int simple; | |
74 | const int flag_setting; /* Additional cost if multiply sets flags. */ | |
75 | const int extend; | |
76 | const int add; | |
77 | const int extend_add; | |
78 | const int idiv; | |
79 | }; | |
80 | ||
81 | /* Calculations of LDM costs are complex. We assume an initial cost | |
82 | (ldm_1st) which will load the number of registers mentioned in | |
83 | ldm_regs_per_insn_1st registers; then each additional | |
84 | ldm_regs_per_insn_subsequent registers cost one more insn. | |
85 | Similarly for STM operations. | |
86 | Therefore the ldm_regs_per_insn_1st/stm_regs_per_insn_1st and | |
87 | ldm_regs_per_insn_subsequent/stm_regs_per_insn_subsequent fields indicate | |
88 | the number of registers loaded/stored and are expressed by a simple integer | |
89 | and not by a COSTS_N_INSNS (N) expression. | |
90 | */ | |
91 | struct mem_cost_table | |
92 | { | |
93 | const int load; | |
94 | const int load_sign_extend; /* Additional to load cost. */ | |
95 | const int ldrd; /* Cost of LDRD. */ | |
96 | const int ldm_1st; | |
97 | const int ldm_regs_per_insn_1st; | |
98 | const int ldm_regs_per_insn_subsequent; | |
99 | const int loadf; /* SFmode. */ | |
100 | const int loadd; /* DFmode. */ | |
101 | const int load_unaligned; /* Extra for unaligned loads. */ | |
102 | const int store; | |
103 | const int strd; | |
104 | const int stm_1st; | |
105 | const int stm_regs_per_insn_1st; | |
106 | const int stm_regs_per_insn_subsequent; | |
107 | const int storef; /* SFmode. */ | |
108 | const int stored; /* DFmode. */ | |
109 | const int store_unaligned; /* Extra for unaligned stores. */ | |
155e90fe | 110 | const int loadv; /* Vector load. */ |
111 | const int storev; /* Vector store. */ | |
8f67eb82 | 112 | }; |
113 | ||
114 | struct fp_cost_table | |
115 | { | |
116 | const int div; | |
117 | const int mult; | |
118 | const int mult_addsub; /* Non-fused. */ | |
119 | const int fma; /* Fused. */ | |
120 | const int addsub; | |
121 | const int fpconst; /* Immediate. */ | |
122 | const int neg; /* NEG and ABS. */ | |
123 | const int compare; | |
124 | const int widen; /* Widen to this size. */ | |
125 | const int narrow; /* Narrow from this size. */ | |
126 | const int toint; | |
127 | const int fromint; | |
128 | const int roundint; /* V8 round to integral, remains FP format. */ | |
129 | }; | |
130 | ||
131 | struct vector_cost_table | |
132 | { | |
133 | const int alu; | |
134 | }; | |
135 | ||
136 | struct cpu_cost_table | |
137 | { | |
138 | const struct alu_cost_table alu; | |
139 | const struct mult_cost_table mult[2]; /* SImode and DImode. */ | |
140 | const struct mem_cost_table ldst; | |
141 | const struct fp_cost_table fp[2]; /* SFmode and DFmode. */ | |
142 | const struct vector_cost_table vect; | |
143 | }; | |
144 | ||
145 | ||
015adf41 | 146 | #endif /* GCC_AARCH_COMMON_PROTOS_H */ |