[thirdparty/gcc.git] / gcc / config / arm / arm-arches.def

/* ARM CPU architectures.
   Copyright (C) 1991-2016 Free Software Foundation, Inc.

   This file is part of GCC.

   GCC is free software; you can redistribute it and/or modify it
   under the terms of the GNU General Public License as published
   by the Free Software Foundation; either version 3, or (at your
   option) any later version.

   GCC is distributed in the hope that it will be useful, but WITHOUT
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
   License for more details.

   You should have received a copy of the GNU General Public License
   along with GCC; see the file COPYING3.  If not see
   <http://www.gnu.org/licenses/>.  */

/* Before using #include to read this file, define a macro:

      ARM_ARCH(NAME, CORE, ARCH, FLAGS)

   The NAME is the name of the architecture, represented as a string
   constant.  The CORE is the identifier for a core representative of
   this architecture.  ARCH is the architecture revision.  FLAGS is
   the set of feature flags implied by the architecture.

   genopt.sh assumes no whitespace up to the first "," in each entry.  */

ARM_ARCH("armv2",   arm2,       2,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2))
ARM_ARCH("armv2a",  arm2,       2,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2))
ARM_ARCH("armv3",   arm6,       3,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3))
ARM_ARCH("armv3m",  arm7m,      3M,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3M))
ARM_ARCH("armv4",   arm7tdmi,   4,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH4))
/* Strictly, FL_MODE26 is a permitted option for v4t, but there are no
   implementations that support it, so we will leave it out for now.  */
ARM_ARCH("armv4t",  arm7tdmi,   4T,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC |             FL_FOR_ARCH4T))
ARM_ARCH("armv5",   arm10tdmi,  5,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC |             FL_FOR_ARCH5))
ARM_ARCH("armv5t",  arm10tdmi,  5T,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC |             FL_FOR_ARCH5T))
ARM_ARCH("armv5e",  arm1026ejs, 5E,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC |             FL_FOR_ARCH5E))
ARM_ARCH("armv5te", arm1026ejs, 5TE,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC |             FL_FOR_ARCH5TE))
ARM_ARCH("armv6",   arm1136js,  6,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC |             FL_FOR_ARCH6))
ARM_ARCH("armv6j",  arm1136js,  6J,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC |             FL_FOR_ARCH6J))
ARM_ARCH("armv6k",  mpcore,	6K,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC |             FL_FOR_ARCH6K))
ARM_ARCH("armv6z",  arm1176jzs, 6Z,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC |             FL_FOR_ARCH6Z))
ARM_ARCH("armv6kz", arm1176jzs, 6KZ,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC |             FL_FOR_ARCH6KZ))
ARM_ARCH("armv6zk", arm1176jzs, 6KZ,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC |             FL_FOR_ARCH6KZ))
ARM_ARCH("armv6t2", arm1156t2s, 6T2,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC |             FL_FOR_ARCH6T2))
ARM_ARCH("armv6-m", cortexm1,	6M,	ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6M))
ARM_ARCH("armv6s-m", cortexm1,	6M,	ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6M))
ARM_ARCH("armv7",   cortexa8,	7,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC |	      FL_FOR_ARCH7))
ARM_ARCH("armv7-a", cortexa8,	7A,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC |	      FL_FOR_ARCH7A))
ARM_ARCH("armv7ve", cortexa8,	7A,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC |	      FL_FOR_ARCH7VE))
ARM_ARCH("armv7-r", cortexr4,	7R,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC |	      FL_FOR_ARCH7R))
ARM_ARCH("armv7-m", cortexm3,	7M,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC |	      FL_FOR_ARCH7M))
ARM_ARCH("armv7e-m", cortexm4,  7EM,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC |	      FL_FOR_ARCH7EM))
ARM_ARCH("armv8-a", cortexa53,  8A,	ARM_FSET_MAKE_CPU1 (FL_CO_PROC |             FL_FOR_ARCH8A))
ARM_ARCH("armv8-a+crc",cortexa53, 8A,   ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_CRC32  | FL_FOR_ARCH8A))
ARM_ARCH("armv8.1-a", cortexa53,  8A,
	  ARM_FSET_MAKE (FL_CO_PROC | FL_CRC32 | FL_FOR_ARCH8A,
			 FL2_FOR_ARCH8_1A))
ARM_ARCH("armv8.1-a+crc",cortexa53, 8A,
	  ARM_FSET_MAKE (FL_CO_PROC | FL_CRC32 | FL_FOR_ARCH8A,
			 FL2_FOR_ARCH8_1A))
ARM_ARCH ("armv8.2-a", cortexa53,  8A,
	  ARM_FSET_MAKE (FL_CO_PROC | FL_CRC32 | FL_FOR_ARCH8A,
			 FL2_FOR_ARCH8_2A))
ARM_ARCH ("armv8.2-a+fp16", cortexa53,  8A,
	  ARM_FSET_MAKE (FL_CO_PROC | FL_CRC32 | FL_FOR_ARCH8A,
			 FL2_FOR_ARCH8_2A | FL2_FP16INST))
ARM_ARCH("armv8-m.base", cortexm23, 8M_BASE,
	  ARM_FSET_MAKE (FL_FOR_ARCH8M_BASE, FL2_CMSE))
ARM_ARCH("armv8-m.main", cortexm7, 8M_MAIN,
	  ARM_FSET_MAKE (FL_CO_PROC | FL_FOR_ARCH8M_MAIN, FL2_CMSE))
ARM_ARCH("armv8-m.main+dsp", cortexm33, 8M_MAIN,
	  ARM_FSET_MAKE (FL_CO_PROC | FL_ARCH7EM | FL_FOR_ARCH8M_MAIN, FL2_CMSE))
ARM_ARCH("iwmmxt",  iwmmxt,     5TE,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT))
ARM_ARCH("iwmmxt2", iwmmxt2,    5TE,	ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT | FL_IWMMXT2))
Commit	Line	Data
ad7be009	1	/* ARM CPU architectures.
818ab71a	2	Copyright (C) 1991-2016 Free Software Foundation, Inc.
ad7be009 JM	3
	4	This file is part of GCC.
	5
	6	GCC is free software; you can redistribute it and/or modify it
	7	under the terms of the GNU General Public License as published
	8	by the Free Software Foundation; either version 3, or (at your
	9	option) any later version.
	10
	11	GCC is distributed in the hope that it will be useful, but WITHOUT
	12	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
	13	or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
	14	License for more details.
	15
	16	You should have received a copy of the GNU General Public License
	17	along with GCC; see the file COPYING3. If not see
	18	<http://www.gnu.org/licenses/>. */
	19
	20	/* Before using #include to read this file, define a macro:
	21
	22	ARM_ARCH(NAME, CORE, ARCH, FLAGS)
	23
	24	The NAME is the name of the architecture, represented as a string
	25	constant. The CORE is the identifier for a core representative of
e656fbc8 MW	26	this architecture. ARCH is the architecture revision. FLAGS is
e656fbc8 MW	27	the set of feature flags implied by the architecture.
ad7be009 JM	28
	29	genopt.sh assumes no whitespace up to the first "," in each entry. */
	30
e656fbc8 MW	31	ARM_ARCH("armv2", arm2, 2, ARM_FSET_MAKE_CPU1 (FL_CO_PROC \| FL_MODE26 \| FL_FOR_ARCH2))
	32	ARM_ARCH("armv2a", arm2, 2, ARM_FSET_MAKE_CPU1 (FL_CO_PROC \| FL_MODE26 \| FL_FOR_ARCH2))
	33	ARM_ARCH("armv3", arm6, 3, ARM_FSET_MAKE_CPU1 (FL_CO_PROC \| FL_MODE26 \| FL_FOR_ARCH3))
	34	ARM_ARCH("armv3m", arm7m, 3M, ARM_FSET_MAKE_CPU1 (FL_CO_PROC \| FL_MODE26 \| FL_FOR_ARCH3M))
	35	ARM_ARCH("armv4", arm7tdmi, 4, ARM_FSET_MAKE_CPU1 (FL_CO_PROC \| FL_MODE26 \| FL_FOR_ARCH4))
ad7be009 JM	36	/* Strictly, FL_MODE26 is a permitted option for v4t, but there are no
ad7be009 JM	37	implementations that support it, so we will leave it out for now. */
e656fbc8 MW	38	ARM_ARCH("armv4t", arm7tdmi, 4T, ARM_FSET_MAKE_CPU1 (FL_CO_PROC \| FL_FOR_ARCH4T))
	39	ARM_ARCH("armv5", arm10tdmi, 5, ARM_FSET_MAKE_CPU1 (FL_CO_PROC \| FL_FOR_ARCH5))
	40	ARM_ARCH("armv5t", arm10tdmi, 5T, ARM_FSET_MAKE_CPU1 (FL_CO_PROC \| FL_FOR_ARCH5T))
	41	ARM_ARCH("armv5e", arm1026ejs, 5E, ARM_FSET_MAKE_CPU1 (FL_CO_PROC \| FL_FOR_ARCH5E))
	42	ARM_ARCH("armv5te", arm1026ejs, 5TE, ARM_FSET_MAKE_CPU1 (FL_CO_PROC \| FL_FOR_ARCH5TE))
	43	ARM_ARCH("armv6", arm1136js, 6, ARM_FSET_MAKE_CPU1 (FL_CO_PROC \| FL_FOR_ARCH6))
	44	ARM_ARCH("armv6j", arm1136js, 6J, ARM_FSET_MAKE_CPU1 (FL_CO_PROC \| FL_FOR_ARCH6J))
	45	ARM_ARCH("armv6k", mpcore, 6K, ARM_FSET_MAKE_CPU1 (FL_CO_PROC \| FL_FOR_ARCH6K))
	46	ARM_ARCH("armv6z", arm1176jzs, 6Z, ARM_FSET_MAKE_CPU1 (FL_CO_PROC \| FL_FOR_ARCH6Z))
	47	ARM_ARCH("armv6kz", arm1176jzs, 6KZ, ARM_FSET_MAKE_CPU1 (FL_CO_PROC \| FL_FOR_ARCH6KZ))
	48	ARM_ARCH("armv6zk", arm1176jzs, 6KZ, ARM_FSET_MAKE_CPU1 (FL_CO_PROC \| FL_FOR_ARCH6KZ))
	49	ARM_ARCH("armv6t2", arm1156t2s, 6T2, ARM_FSET_MAKE_CPU1 (FL_CO_PROC \| FL_FOR_ARCH6T2))
	50	ARM_ARCH("armv6-m", cortexm1, 6M, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6M))
	51	ARM_ARCH("armv6s-m", cortexm1, 6M, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6M))
	52	ARM_ARCH("armv7", cortexa8, 7, ARM_FSET_MAKE_CPU1 (FL_CO_PROC \| FL_FOR_ARCH7))
	53	ARM_ARCH("armv7-a", cortexa8, 7A, ARM_FSET_MAKE_CPU1 (FL_CO_PROC \| FL_FOR_ARCH7A))
	54	ARM_ARCH("armv7ve", cortexa8, 7A, ARM_FSET_MAKE_CPU1 (FL_CO_PROC \| FL_FOR_ARCH7VE))
	55	ARM_ARCH("armv7-r", cortexr4, 7R, ARM_FSET_MAKE_CPU1 (FL_CO_PROC \| FL_FOR_ARCH7R))
	56	ARM_ARCH("armv7-m", cortexm3, 7M, ARM_FSET_MAKE_CPU1 (FL_CO_PROC \| FL_FOR_ARCH7M))
	57	ARM_ARCH("armv7e-m", cortexm4, 7EM, ARM_FSET_MAKE_CPU1 (FL_CO_PROC \| FL_FOR_ARCH7EM))
	58	ARM_ARCH("armv8-a", cortexa53, 8A, ARM_FSET_MAKE_CPU1 (FL_CO_PROC \| FL_FOR_ARCH8A))
	59	ARM_ARCH("armv8-a+crc",cortexa53, 8A, ARM_FSET_MAKE_CPU1 (FL_CO_PROC \| FL_CRC32 \| FL_FOR_ARCH8A))
4e3999a7	60	ARM_ARCH("armv8.1-a", cortexa53, 8A,
4040b89a MW	61	ARM_FSET_MAKE (FL_CO_PROC \| FL_CRC32 \| FL_FOR_ARCH8A,
4040b89a MW	62	FL2_FOR_ARCH8_1A))
4e3999a7	63	ARM_ARCH("armv8.1-a+crc",cortexa53, 8A,
252e03b5 MW	64	ARM_FSET_MAKE (FL_CO_PROC \| FL_CRC32 \| FL_FOR_ARCH8A,
252e03b5 MW	65	FL2_FOR_ARCH8_1A))
4040b89a MW	66	ARM_ARCH ("armv8.2-a", cortexa53, 8A,
	67	ARM_FSET_MAKE (FL_CO_PROC \| FL_CRC32 \| FL_FOR_ARCH8A,
	68	FL2_FOR_ARCH8_2A))
	69	ARM_ARCH ("armv8.2-a+fp16", cortexa53, 8A,
	70	ARM_FSET_MAKE (FL_CO_PROC \| FL_CRC32 \| FL_FOR_ARCH8A,
	71	FL2_FOR_ARCH8_2A \| FL2_FP16INST))
f6b2065f	72	ARM_ARCH("armv8-m.base", cortexm23, 8M_BASE,
de7b5723	73	ARM_FSET_MAKE (FL_FOR_ARCH8M_BASE, FL2_CMSE))
05a437c1	74	ARM_ARCH("armv8-m.main", cortexm7, 8M_MAIN,
de7b5723	75	ARM_FSET_MAKE (FL_CO_PROC \| FL_FOR_ARCH8M_MAIN, FL2_CMSE))
cf16d50f	76	ARM_ARCH("armv8-m.main+dsp", cortexm33, 8M_MAIN,
de7b5723	77	ARM_FSET_MAKE (FL_CO_PROC \| FL_ARCH7EM \| FL_FOR_ARCH8M_MAIN, FL2_CMSE))
e656fbc8 MW	78	ARM_ARCH("iwmmxt", iwmmxt, 5TE, ARM_FSET_MAKE_CPU1 (FL_LDSCHED \| FL_STRONG \| FL_FOR_ARCH5TE \| FL_XSCALE \| FL_IWMMXT))
e656fbc8 MW	79	ARM_ARCH("iwmmxt2", iwmmxt2, 5TE, ARM_FSET_MAKE_CPU1 (FL_LDSCHED \| FL_STRONG \| FL_FOR_ARCH5TE \| FL_XSCALE \| FL_IWMMXT \| FL_IWMMXT2))