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a92ffb3e RE |
1 | /* -*- buffer-read-only: t -*- |
2 | Generated automatically by parsecpu.awk from arm-cpus.in. | |
3 | Do not edit. | |
4 | ||
5 | Copyright (C) 2011-2017 Free Software Foundation, Inc. | |
6 | ||
7 | This file is part of GCC. | |
8 | ||
9 | GCC is free software; you can redistribute it and/or modify | |
10 | it under the terms of the GNU General Public License as | |
11 | published by the Free Software Foundation; either version 3, | |
12 | or (at your option) any later version. | |
13 | ||
14 | GCC is distributed in the hope that it will be useful, | |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public | |
20 | License along with GCC; see the file COPYING3. If not see | |
21 | <http://www.gnu.org/licenses/>. */ | |
22 | ||
050809ed RE |
23 | static const cpu_tune all_tunes[] = |
24 | { | |
25 | { /* arm2. */ | |
26 | TARGET_CPU_arm2, | |
27 | (TF_CO_PROC | TF_NO_MODE32), | |
28 | &arm_slowmul_tune | |
29 | }, | |
30 | { /* arm250. */ | |
31 | TARGET_CPU_arm250, | |
32 | (TF_CO_PROC | TF_NO_MODE32), | |
33 | &arm_slowmul_tune | |
34 | }, | |
35 | { /* arm3. */ | |
36 | TARGET_CPU_arm3, | |
37 | (TF_CO_PROC | TF_NO_MODE32), | |
38 | &arm_slowmul_tune | |
39 | }, | |
40 | { /* arm6. */ | |
41 | TARGET_CPU_arm6, | |
42 | (TF_CO_PROC), | |
43 | &arm_slowmul_tune | |
44 | }, | |
45 | { /* arm60. */ | |
46 | TARGET_CPU_arm60, | |
47 | (TF_CO_PROC), | |
48 | &arm_slowmul_tune | |
49 | }, | |
50 | { /* arm600. */ | |
51 | TARGET_CPU_arm600, | |
52 | (TF_CO_PROC | TF_WBUF), | |
53 | &arm_slowmul_tune | |
54 | }, | |
55 | { /* arm610. */ | |
56 | TARGET_CPU_arm610, | |
57 | (TF_WBUF), | |
58 | &arm_slowmul_tune | |
59 | }, | |
60 | { /* arm620. */ | |
61 | TARGET_CPU_arm620, | |
62 | (TF_CO_PROC | TF_WBUF), | |
63 | &arm_slowmul_tune | |
64 | }, | |
65 | { /* arm7. */ | |
66 | TARGET_CPU_arm7, | |
67 | (TF_CO_PROC), | |
68 | &arm_slowmul_tune | |
69 | }, | |
70 | { /* arm7d. */ | |
71 | TARGET_CPU_arm7d, | |
72 | (TF_CO_PROC), | |
73 | &arm_slowmul_tune | |
74 | }, | |
75 | { /* arm7di. */ | |
76 | TARGET_CPU_arm7di, | |
77 | (TF_CO_PROC), | |
78 | &arm_slowmul_tune | |
79 | }, | |
80 | { /* arm70. */ | |
81 | TARGET_CPU_arm70, | |
82 | (TF_CO_PROC), | |
83 | &arm_slowmul_tune | |
84 | }, | |
85 | { /* arm700. */ | |
86 | TARGET_CPU_arm700, | |
87 | (TF_CO_PROC | TF_WBUF), | |
88 | &arm_slowmul_tune | |
89 | }, | |
90 | { /* arm700i. */ | |
91 | TARGET_CPU_arm700i, | |
92 | (TF_CO_PROC | TF_WBUF), | |
93 | &arm_slowmul_tune | |
94 | }, | |
95 | { /* arm710. */ | |
96 | TARGET_CPU_arm710, | |
97 | (TF_WBUF), | |
98 | &arm_slowmul_tune | |
99 | }, | |
100 | { /* arm720. */ | |
101 | TARGET_CPU_arm720, | |
102 | (TF_WBUF), | |
103 | &arm_slowmul_tune | |
104 | }, | |
105 | { /* arm710c. */ | |
106 | TARGET_CPU_arm710c, | |
107 | (TF_WBUF), | |
108 | &arm_slowmul_tune | |
109 | }, | |
110 | { /* arm7100. */ | |
111 | TARGET_CPU_arm7100, | |
112 | (TF_WBUF), | |
113 | &arm_slowmul_tune | |
114 | }, | |
115 | { /* arm7500. */ | |
116 | TARGET_CPU_arm7500, | |
117 | (TF_WBUF), | |
118 | &arm_slowmul_tune | |
119 | }, | |
120 | { /* arm7500fe. */ | |
121 | TARGET_CPU_arm7500fe, | |
122 | (TF_CO_PROC | TF_WBUF), | |
123 | &arm_slowmul_tune | |
124 | }, | |
125 | { /* arm7m. */ | |
126 | TARGET_CPU_arm7m, | |
127 | (TF_CO_PROC), | |
128 | &arm_fastmul_tune | |
129 | }, | |
130 | { /* arm7dm. */ | |
131 | TARGET_CPU_arm7dm, | |
132 | (TF_CO_PROC), | |
133 | &arm_fastmul_tune | |
134 | }, | |
135 | { /* arm7dmi. */ | |
136 | TARGET_CPU_arm7dmi, | |
137 | (TF_CO_PROC), | |
138 | &arm_fastmul_tune | |
139 | }, | |
140 | { /* arm8. */ | |
141 | TARGET_CPU_arm8, | |
142 | (TF_LDSCHED), | |
143 | &arm_fastmul_tune | |
144 | }, | |
145 | { /* arm810. */ | |
146 | TARGET_CPU_arm810, | |
147 | (TF_LDSCHED), | |
148 | &arm_fastmul_tune | |
149 | }, | |
150 | { /* strongarm. */ | |
151 | TARGET_CPU_strongarm, | |
152 | (TF_LDSCHED | TF_STRONG), | |
153 | &arm_strongarm_tune | |
154 | }, | |
155 | { /* strongarm110. */ | |
156 | TARGET_CPU_strongarm110, | |
157 | (TF_LDSCHED | TF_STRONG), | |
158 | &arm_strongarm_tune | |
159 | }, | |
160 | { /* strongarm1100. */ | |
161 | TARGET_CPU_strongarm1100, | |
162 | (TF_LDSCHED | TF_STRONG), | |
163 | &arm_strongarm_tune | |
164 | }, | |
165 | { /* strongarm1110. */ | |
166 | TARGET_CPU_strongarm1110, | |
167 | (TF_LDSCHED | TF_STRONG), | |
168 | &arm_strongarm_tune | |
169 | }, | |
170 | { /* fa526. */ | |
171 | TARGET_CPU_fa526, | |
172 | (TF_LDSCHED), | |
173 | &arm_fastmul_tune | |
174 | }, | |
175 | { /* fa626. */ | |
176 | TARGET_CPU_fa626, | |
177 | (TF_LDSCHED), | |
178 | &arm_fastmul_tune | |
179 | }, | |
180 | { /* arm7tdmi. */ | |
181 | TARGET_CPU_arm7tdmi, | |
182 | (TF_CO_PROC), | |
183 | &arm_fastmul_tune | |
184 | }, | |
185 | { /* arm7tdmi-s. */ | |
186 | TARGET_CPU_arm7tdmis, | |
187 | (TF_CO_PROC), | |
188 | &arm_fastmul_tune | |
189 | }, | |
190 | { /* arm710t. */ | |
191 | TARGET_CPU_arm710t, | |
192 | (TF_WBUF), | |
193 | &arm_fastmul_tune | |
194 | }, | |
195 | { /* arm720t. */ | |
196 | TARGET_CPU_arm720t, | |
197 | (TF_WBUF), | |
198 | &arm_fastmul_tune | |
199 | }, | |
200 | { /* arm740t. */ | |
201 | TARGET_CPU_arm740t, | |
202 | (TF_WBUF), | |
203 | &arm_fastmul_tune | |
204 | }, | |
205 | { /* arm9. */ | |
206 | TARGET_CPU_arm9, | |
207 | (TF_LDSCHED), | |
208 | &arm_fastmul_tune | |
209 | }, | |
210 | { /* arm9tdmi. */ | |
211 | TARGET_CPU_arm9tdmi, | |
212 | (TF_LDSCHED), | |
213 | &arm_fastmul_tune | |
214 | }, | |
215 | { /* arm920. */ | |
216 | TARGET_CPU_arm920, | |
217 | (TF_LDSCHED), | |
218 | &arm_fastmul_tune | |
219 | }, | |
220 | { /* arm920t. */ | |
221 | TARGET_CPU_arm920t, | |
222 | (TF_LDSCHED), | |
223 | &arm_fastmul_tune | |
224 | }, | |
225 | { /* arm922t. */ | |
226 | TARGET_CPU_arm922t, | |
227 | (TF_LDSCHED), | |
228 | &arm_fastmul_tune | |
229 | }, | |
230 | { /* arm940t. */ | |
231 | TARGET_CPU_arm940t, | |
232 | (TF_LDSCHED), | |
233 | &arm_fastmul_tune | |
234 | }, | |
235 | { /* ep9312. */ | |
236 | TARGET_CPU_ep9312, | |
237 | (TF_LDSCHED), | |
238 | &arm_fastmul_tune | |
239 | }, | |
240 | { /* arm10tdmi. */ | |
241 | TARGET_CPU_arm10tdmi, | |
242 | (TF_LDSCHED), | |
243 | &arm_fastmul_tune | |
244 | }, | |
245 | { /* arm1020t. */ | |
246 | TARGET_CPU_arm1020t, | |
247 | (TF_LDSCHED), | |
248 | &arm_fastmul_tune | |
249 | }, | |
250 | { /* arm9e. */ | |
251 | TARGET_CPU_arm9e, | |
252 | (TF_LDSCHED), | |
253 | &arm_9e_tune | |
254 | }, | |
255 | { /* arm946e-s. */ | |
256 | TARGET_CPU_arm946es, | |
257 | (TF_LDSCHED), | |
258 | &arm_9e_tune | |
259 | }, | |
260 | { /* arm966e-s. */ | |
261 | TARGET_CPU_arm966es, | |
262 | (TF_LDSCHED), | |
263 | &arm_9e_tune | |
264 | }, | |
265 | { /* arm968e-s. */ | |
266 | TARGET_CPU_arm968es, | |
267 | (TF_LDSCHED), | |
268 | &arm_9e_tune | |
269 | }, | |
270 | { /* arm10e. */ | |
271 | TARGET_CPU_arm10e, | |
272 | (TF_LDSCHED), | |
273 | &arm_fastmul_tune | |
274 | }, | |
275 | { /* arm1020e. */ | |
276 | TARGET_CPU_arm1020e, | |
277 | (TF_LDSCHED), | |
278 | &arm_fastmul_tune | |
279 | }, | |
280 | { /* arm1022e. */ | |
281 | TARGET_CPU_arm1022e, | |
282 | (TF_LDSCHED), | |
283 | &arm_fastmul_tune | |
284 | }, | |
285 | { /* xscale. */ | |
286 | TARGET_CPU_xscale, | |
287 | (TF_LDSCHED | TF_XSCALE), | |
288 | &arm_xscale_tune | |
289 | }, | |
290 | { /* iwmmxt. */ | |
291 | TARGET_CPU_iwmmxt, | |
292 | (TF_LDSCHED | TF_XSCALE), | |
293 | &arm_xscale_tune | |
294 | }, | |
295 | { /* iwmmxt2. */ | |
296 | TARGET_CPU_iwmmxt2, | |
297 | (TF_LDSCHED | TF_XSCALE), | |
298 | &arm_xscale_tune | |
299 | }, | |
300 | { /* fa606te. */ | |
301 | TARGET_CPU_fa606te, | |
302 | (TF_LDSCHED), | |
303 | &arm_9e_tune | |
304 | }, | |
305 | { /* fa626te. */ | |
306 | TARGET_CPU_fa626te, | |
307 | (TF_LDSCHED), | |
308 | &arm_9e_tune | |
309 | }, | |
310 | { /* fmp626. */ | |
311 | TARGET_CPU_fmp626, | |
312 | (TF_LDSCHED), | |
313 | &arm_9e_tune | |
314 | }, | |
315 | { /* fa726te. */ | |
316 | TARGET_CPU_fa726te, | |
317 | (TF_LDSCHED), | |
318 | &arm_fa726te_tune | |
319 | }, | |
320 | { /* arm926ej-s. */ | |
321 | TARGET_CPU_arm926ejs, | |
322 | (TF_LDSCHED), | |
a92ffb3e RE |
323 | &arm_9e_tune |
324 | }, | |
050809ed RE |
325 | { /* arm1026ej-s. */ |
326 | TARGET_CPU_arm1026ejs, | |
327 | (TF_LDSCHED), | |
328 | &arm_9e_tune | |
329 | }, | |
330 | { /* arm1136j-s. */ | |
48c0758a | 331 | TARGET_CPU_arm1136js, |
a92ffb3e | 332 | (TF_LDSCHED), |
a92ffb3e RE |
333 | &arm_9e_tune |
334 | }, | |
050809ed | 335 | { /* arm1136jf-s. */ |
48c0758a | 336 | TARGET_CPU_arm1136jfs, |
a92ffb3e | 337 | (TF_LDSCHED), |
a92ffb3e RE |
338 | &arm_9e_tune |
339 | }, | |
050809ed | 340 | { /* arm1176jz-s. */ |
48c0758a | 341 | TARGET_CPU_arm1176jzs, |
a92ffb3e | 342 | (TF_LDSCHED), |
a92ffb3e RE |
343 | &arm_9e_tune |
344 | }, | |
050809ed | 345 | { /* arm1176jzf-s. */ |
48c0758a | 346 | TARGET_CPU_arm1176jzfs, |
a92ffb3e | 347 | (TF_LDSCHED), |
a92ffb3e RE |
348 | &arm_9e_tune |
349 | }, | |
050809ed | 350 | { /* mpcorenovfp. */ |
48c0758a | 351 | TARGET_CPU_mpcorenovfp, |
a92ffb3e | 352 | (TF_LDSCHED), |
a92ffb3e RE |
353 | &arm_9e_tune |
354 | }, | |
050809ed | 355 | { /* mpcore. */ |
48c0758a | 356 | TARGET_CPU_mpcore, |
a92ffb3e | 357 | (TF_LDSCHED), |
a92ffb3e RE |
358 | &arm_9e_tune |
359 | }, | |
050809ed | 360 | { /* arm1156t2-s. */ |
48c0758a | 361 | TARGET_CPU_arm1156t2s, |
a92ffb3e | 362 | (TF_LDSCHED), |
a92ffb3e RE |
363 | &arm_v6t2_tune |
364 | }, | |
050809ed | 365 | { /* arm1156t2f-s. */ |
48c0758a | 366 | TARGET_CPU_arm1156t2fs, |
a92ffb3e | 367 | (TF_LDSCHED), |
a92ffb3e RE |
368 | &arm_v6t2_tune |
369 | }, | |
050809ed | 370 | { /* cortex-m1. */ |
48c0758a | 371 | TARGET_CPU_cortexm1, |
a92ffb3e | 372 | (TF_LDSCHED), |
a92ffb3e RE |
373 | &arm_v6m_tune |
374 | }, | |
050809ed | 375 | { /* cortex-m0. */ |
48c0758a | 376 | TARGET_CPU_cortexm0, |
a92ffb3e | 377 | (TF_LDSCHED), |
a92ffb3e RE |
378 | &arm_v6m_tune |
379 | }, | |
050809ed | 380 | { /* cortex-m0plus. */ |
48c0758a | 381 | TARGET_CPU_cortexm0plus, |
a92ffb3e | 382 | (TF_LDSCHED), |
a92ffb3e RE |
383 | &arm_v6m_tune |
384 | }, | |
050809ed | 385 | { /* cortex-m1.small-multiply. */ |
48c0758a | 386 | TARGET_CPU_cortexm1, |
a92ffb3e | 387 | (TF_LDSCHED | TF_SMALLMUL), |
a92ffb3e RE |
388 | &arm_v6m_tune |
389 | }, | |
050809ed | 390 | { /* cortex-m0.small-multiply. */ |
48c0758a | 391 | TARGET_CPU_cortexm0, |
a92ffb3e | 392 | (TF_LDSCHED | TF_SMALLMUL), |
a92ffb3e RE |
393 | &arm_v6m_tune |
394 | }, | |
050809ed | 395 | { /* cortex-m0plus.small-multiply. */ |
48c0758a | 396 | TARGET_CPU_cortexm0plus, |
a92ffb3e | 397 | (TF_LDSCHED | TF_SMALLMUL), |
a92ffb3e RE |
398 | &arm_v6m_tune |
399 | }, | |
050809ed | 400 | { /* generic-armv7-a. */ |
48c0758a | 401 | TARGET_CPU_genericv7a, |
a92ffb3e | 402 | (TF_LDSCHED), |
a92ffb3e RE |
403 | &arm_cortex_tune |
404 | }, | |
050809ed | 405 | { /* cortex-a5. */ |
48c0758a | 406 | TARGET_CPU_cortexa5, |
a92ffb3e | 407 | (TF_LDSCHED), |
a92ffb3e RE |
408 | &arm_cortex_a5_tune |
409 | }, | |
050809ed | 410 | { /* cortex-a7. */ |
48c0758a | 411 | TARGET_CPU_cortexa7, |
a92ffb3e | 412 | (TF_LDSCHED), |
a92ffb3e RE |
413 | &arm_cortex_a7_tune |
414 | }, | |
050809ed | 415 | { /* cortex-a8. */ |
48c0758a | 416 | TARGET_CPU_cortexa8, |
a92ffb3e | 417 | (TF_LDSCHED), |
a92ffb3e RE |
418 | &arm_cortex_a8_tune |
419 | }, | |
050809ed | 420 | { /* cortex-a9. */ |
48c0758a | 421 | TARGET_CPU_cortexa9, |
a92ffb3e | 422 | (TF_LDSCHED), |
a92ffb3e RE |
423 | &arm_cortex_a9_tune |
424 | }, | |
050809ed | 425 | { /* cortex-a12. */ |
48c0758a | 426 | TARGET_CPU_cortexa17, |
a92ffb3e | 427 | (TF_LDSCHED), |
a92ffb3e RE |
428 | &arm_cortex_a12_tune |
429 | }, | |
050809ed | 430 | { /* cortex-a15. */ |
48c0758a | 431 | TARGET_CPU_cortexa15, |
a92ffb3e | 432 | (TF_LDSCHED), |
a92ffb3e RE |
433 | &arm_cortex_a15_tune |
434 | }, | |
050809ed | 435 | { /* cortex-a17. */ |
48c0758a | 436 | TARGET_CPU_cortexa17, |
a92ffb3e | 437 | (TF_LDSCHED), |
a92ffb3e RE |
438 | &arm_cortex_a12_tune |
439 | }, | |
050809ed | 440 | { /* cortex-r4. */ |
48c0758a | 441 | TARGET_CPU_cortexr4, |
a92ffb3e | 442 | (TF_LDSCHED), |
a92ffb3e RE |
443 | &arm_cortex_tune |
444 | }, | |
050809ed | 445 | { /* cortex-r4f. */ |
48c0758a | 446 | TARGET_CPU_cortexr4f, |
a92ffb3e | 447 | (TF_LDSCHED), |
a92ffb3e RE |
448 | &arm_cortex_tune |
449 | }, | |
050809ed | 450 | { /* cortex-r5. */ |
48c0758a | 451 | TARGET_CPU_cortexr5, |
a92ffb3e | 452 | (TF_LDSCHED), |
a92ffb3e RE |
453 | &arm_cortex_tune |
454 | }, | |
050809ed | 455 | { /* cortex-r7. */ |
48c0758a | 456 | TARGET_CPU_cortexr7, |
a92ffb3e | 457 | (TF_LDSCHED), |
a92ffb3e RE |
458 | &arm_cortex_tune |
459 | }, | |
050809ed | 460 | { /* cortex-r8. */ |
48c0758a | 461 | TARGET_CPU_cortexr7, |
a92ffb3e | 462 | (TF_LDSCHED), |
a92ffb3e RE |
463 | &arm_cortex_tune |
464 | }, | |
050809ed | 465 | { /* cortex-m7. */ |
48c0758a | 466 | TARGET_CPU_cortexm7, |
a92ffb3e | 467 | (TF_LDSCHED), |
a92ffb3e RE |
468 | &arm_cortex_m7_tune |
469 | }, | |
050809ed | 470 | { /* cortex-m4. */ |
48c0758a | 471 | TARGET_CPU_cortexm4, |
a92ffb3e | 472 | (TF_LDSCHED), |
a92ffb3e RE |
473 | &arm_v7m_tune |
474 | }, | |
050809ed | 475 | { /* cortex-m3. */ |
48c0758a | 476 | TARGET_CPU_cortexm3, |
a92ffb3e | 477 | (TF_LDSCHED), |
a92ffb3e RE |
478 | &arm_v7m_tune |
479 | }, | |
050809ed | 480 | { /* marvell-pj4. */ |
48c0758a | 481 | TARGET_CPU_marvell_pj4, |
a92ffb3e | 482 | (TF_LDSCHED), |
a92ffb3e RE |
483 | &arm_marvell_pj4_tune |
484 | }, | |
050809ed | 485 | { /* cortex-a15.cortex-a7. */ |
48c0758a | 486 | TARGET_CPU_cortexa7, |
a92ffb3e | 487 | (TF_LDSCHED), |
a92ffb3e RE |
488 | &arm_cortex_a15_tune |
489 | }, | |
050809ed | 490 | { /* cortex-a17.cortex-a7. */ |
48c0758a | 491 | TARGET_CPU_cortexa7, |
a92ffb3e | 492 | (TF_LDSCHED), |
a92ffb3e RE |
493 | &arm_cortex_a12_tune |
494 | }, | |
050809ed | 495 | { /* cortex-a32. */ |
48c0758a | 496 | TARGET_CPU_cortexa53, |
a92ffb3e | 497 | (TF_LDSCHED), |
a92ffb3e RE |
498 | &arm_cortex_a35_tune |
499 | }, | |
050809ed | 500 | { /* cortex-a35. */ |
48c0758a | 501 | TARGET_CPU_cortexa53, |
a92ffb3e | 502 | (TF_LDSCHED), |
a92ffb3e RE |
503 | &arm_cortex_a35_tune |
504 | }, | |
050809ed | 505 | { /* cortex-a53. */ |
48c0758a | 506 | TARGET_CPU_cortexa53, |
a92ffb3e | 507 | (TF_LDSCHED), |
a92ffb3e RE |
508 | &arm_cortex_a53_tune |
509 | }, | |
050809ed | 510 | { /* cortex-a57. */ |
48c0758a | 511 | TARGET_CPU_cortexa57, |
a92ffb3e | 512 | (TF_LDSCHED), |
a92ffb3e RE |
513 | &arm_cortex_a57_tune |
514 | }, | |
050809ed | 515 | { /* cortex-a72. */ |
48c0758a | 516 | TARGET_CPU_cortexa57, |
a92ffb3e | 517 | (TF_LDSCHED), |
a92ffb3e RE |
518 | &arm_cortex_a57_tune |
519 | }, | |
050809ed | 520 | { /* cortex-a73. */ |
48c0758a | 521 | TARGET_CPU_cortexa57, |
a92ffb3e | 522 | (TF_LDSCHED), |
a92ffb3e RE |
523 | &arm_cortex_a73_tune |
524 | }, | |
050809ed | 525 | { /* exynos-m1. */ |
48c0758a | 526 | TARGET_CPU_exynosm1, |
a92ffb3e | 527 | (TF_LDSCHED), |
a92ffb3e RE |
528 | &arm_exynosm1_tune |
529 | }, | |
050809ed | 530 | { /* xgene1. */ |
48c0758a | 531 | TARGET_CPU_xgene1, |
a92ffb3e | 532 | (TF_LDSCHED), |
a92ffb3e RE |
533 | &arm_xgene1_tune |
534 | }, | |
050809ed | 535 | { /* cortex-a57.cortex-a53. */ |
48c0758a | 536 | TARGET_CPU_cortexa53, |
a92ffb3e | 537 | (TF_LDSCHED), |
a92ffb3e RE |
538 | &arm_cortex_a57_tune |
539 | }, | |
050809ed | 540 | { /* cortex-a72.cortex-a53. */ |
48c0758a | 541 | TARGET_CPU_cortexa53, |
a92ffb3e | 542 | (TF_LDSCHED), |
a92ffb3e RE |
543 | &arm_cortex_a57_tune |
544 | }, | |
050809ed | 545 | { /* cortex-a73.cortex-a35. */ |
48c0758a | 546 | TARGET_CPU_cortexa53, |
a92ffb3e | 547 | (TF_LDSCHED), |
a92ffb3e RE |
548 | &arm_cortex_a73_tune |
549 | }, | |
050809ed | 550 | { /* cortex-a73.cortex-a53. */ |
48c0758a | 551 | TARGET_CPU_cortexa53, |
a92ffb3e | 552 | (TF_LDSCHED), |
a92ffb3e RE |
553 | &arm_cortex_a73_tune |
554 | }, | |
1d79dcb8 JG |
555 | { /* cortex-a55. */ |
556 | TARGET_CPU_cortexa53, | |
557 | (TF_LDSCHED), | |
558 | &arm_cortex_a53_tune | |
559 | }, | |
560 | { /* cortex-a75. */ | |
561 | TARGET_CPU_cortexa57, | |
562 | (TF_LDSCHED), | |
563 | &arm_cortex_a73_tune | |
564 | }, | |
565 | { /* cortex-a75.cortex-a55. */ | |
566 | TARGET_CPU_cortexa53, | |
567 | (TF_LDSCHED), | |
568 | &arm_cortex_a73_tune | |
569 | }, | |
050809ed | 570 | { /* cortex-m23. */ |
48c0758a | 571 | TARGET_CPU_cortexm23, |
a92ffb3e | 572 | (TF_LDSCHED), |
a92ffb3e RE |
573 | &arm_v6m_tune |
574 | }, | |
050809ed | 575 | { /* cortex-m33. */ |
48c0758a | 576 | TARGET_CPU_cortexm33, |
a92ffb3e | 577 | (TF_LDSCHED), |
a92ffb3e RE |
578 | &arm_v7m_tune |
579 | }, | |
050809ed | 580 | {TARGET_CPU_arm_none, 0, NULL} |
250e088b | 581 | }; |