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Make arm_feature_set agree with type of FL_* macros
[thirdparty/gcc.git] / gcc / config / arm / arm-protos.h
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eb3921e8 1/* Prototypes for exported functions defined in arm.c and pe.c
818ab71a 2 Copyright (C) 1999-2016 Free Software Foundation, Inc.
eb3921e8
NC		 3 Contributed by Richard Earnshaw (rearnsha@arm.com)
4 Minor hacks by Nick Clifton (nickc@cygnus.com)
5
4f448245 6 This file is part of GCC.
eb3921e8 7
4f448245
NC		 8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
2f83c7d6 10 the Free Software Foundation; either version 3, or (at your option)
4f448245 11 any later version.
eb3921e8 12
4f448245
NC		 13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
eb3921e8 17
4f448245 18 You should have received a copy of the GNU General Public License
2f83c7d6
NC		 19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
eb3921e8 21
8b97c5f8
ZW		 22#ifndef GCC_ARM_PROTOS_H
23#define GCC_ARM_PROTOS_H
24
677f3fa8 25extern enum unwind_info_type arm_except_unwind_info (struct gcc_options *);
a72d4945 26extern int use_return_insn (int, rtx);
24d5b097 27extern bool use_simple_return_p (void);
bbbbb16a 28extern enum reg_class arm_regno_class (int);
e55ef7f4 29extern void arm_load_pic_register (unsigned long);
e32bac5b 30extern int arm_volatile_func (void);
e32bac5b 31extern void arm_expand_prologue (void);
d461c88a 32extern void arm_expand_epilogue (bool);
258619bb 33extern void arm_declare_function_name (FILE *, const char *, tree);
24d5b097 34extern void thumb2_expand_return (bool);
e32bac5b
RE		 35extern const char *arm_strip_name_encoding (const char *);
36extern void arm_asm_output_labelref (FILE *, const char *);
5b3e6663 37extern void thumb2_asm_output_opcode (FILE *);
e32bac5b 38extern unsigned long arm_current_func_type (void);
b3f8d95d
MM		 39extern HOST_WIDE_INT arm_compute_initial_elimination_offset (unsigned int,
40 unsigned int);
5848830f
PB		 41extern HOST_WIDE_INT thumb_compute_initial_elimination_offset (unsigned int,
42 unsigned int);
2fa330b2 43extern unsigned int arm_dbx_register_number (unsigned int);
617a1b71 44extern void arm_output_fn_unwind (FILE *, bool);
33857df2
JG		 45
46extern rtx arm_expand_builtin (tree exp, rtx target, rtx subtarget
47 ATTRIBUTE_UNUSED, enum machine_mode mode
48 ATTRIBUTE_UNUSED, int ignore ATTRIBUTE_UNUSED);
49extern tree arm_builtin_decl (unsigned code, bool initialize_p
50 ATTRIBUTE_UNUSED);
51extern void arm_init_builtins (void);
52extern void arm_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update);
93c590ee
MC		 53extern rtx arm_simd_vect_par_cnst_half (machine_mode mode, bool high);
54extern bool arm_simd_check_vect_par_cnst_half_p (rtx op, machine_mode mode,
55 bool high);
eb3921e8 56#ifdef RTX_CODE
c8cd4696
MC		 57extern void arm_gen_unlikely_cbranch (enum rtx_code, machine_mode cc_mode,
58 rtx label_ref);
ef4bddc2
RS		 59extern bool arm_vector_mode_supported_p (machine_mode);
60extern bool arm_small_register_classes_for_mode_p (machine_mode);
61extern int arm_hard_regno_mode_ok (unsigned int, machine_mode);
62extern bool arm_modes_tieable_p (machine_mode, machine_mode);
e32bac5b 63extern int const_ok_for_arm (HOST_WIDE_INT);
c2b640a7 64extern int const_ok_for_op (HOST_WIDE_INT, enum rtx_code);
44cd6810 65extern int const_ok_for_dimode_op (HOST_WIDE_INT, enum rtx_code);
ef4bddc2 66extern int arm_split_constant (RTX_CODE, machine_mode, rtx,
a406f566 67 HOST_WIDE_INT, rtx, rtx, int);
e32bac5b 68extern int legitimate_pic_operand_p (rtx);
ef4bddc2 69extern rtx legitimize_pic_address (rtx, machine_mode, rtx);
d3585b76 70extern rtx legitimize_tls_address (rtx, rtx);
ef4bddc2
RS		 71extern bool arm_legitimate_address_p (machine_mode, rtx, bool);
72extern int arm_legitimate_address_outer_p (machine_mode, rtx, RTX_CODE, int);
73extern int thumb_legitimate_offset_p (machine_mode, HOST_WIDE_INT);
ef4bddc2
RS		 74extern int thumb1_legitimate_address_p (machine_mode, rtx, int);
75extern bool ldm_stm_operation_p (rtx, bool, machine_mode mode,
fb40241d 76 bool, bool);
9b66ebb1 77extern int arm_const_double_rtx (rtx);
f1adb0a9 78extern int vfp3_const_double_rtx (rtx);
ef4bddc2
RS		 79extern int neon_immediate_valid_for_move (rtx, machine_mode, rtx *, int *);
80extern int neon_immediate_valid_for_logic (rtx, machine_mode, int, rtx *,
88f77cba 81 int *);
ef4bddc2 82extern int neon_immediate_valid_for_shift (rtx, machine_mode, rtx *,
31a0c825 83 int *, bool);
88f77cba 84extern char *neon_output_logic_immediate (const char *, rtx *,
ef4bddc2 85 machine_mode, int, int);
31a0c825 86extern char *neon_output_shift_immediate (const char *, char, rtx *,
ef4bddc2
RS		 87 machine_mode, int, bool);
88extern void neon_pairwise_reduce (rtx, rtx, machine_mode,
88f77cba 89 rtx (*) (rtx, rtx, rtx));
814a4c3b 90extern rtx neon_make_constant (rtx);
10766209 91extern tree arm_builtin_vectorized_function (unsigned int, tree, tree);
88f77cba 92extern void neon_expand_vector_init (rtx, rtx);
eaa80f64 93extern void neon_lane_bounds (rtx, HOST_WIDE_INT, HOST_WIDE_INT, const_tree);
b617fc71 94extern void neon_const_bounds (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
ef4bddc2 95extern HOST_WIDE_INT neon_element_bits (machine_mode);
ef4bddc2 96extern void neon_emit_pair_result_insn (machine_mode,
88f77cba
JB		 97 rtx (*) (rtx, rtx, rtx, rtx),
98 rtx, rtx, rtx);
99extern void neon_disambiguate_copy (rtx *, rtx *, rtx *, unsigned int);
b440f324 100extern void neon_split_vcombine (rtx op[3]);
ef4bddc2 101extern enum reg_class coproc_secondary_reload_class (machine_mode, rtx,
fe2d934b 102 bool);
d3585b76 103extern bool arm_tls_referenced_p (rtx);
d5b7b3ae 104
fdd695fd 105extern int arm_coproc_mem_operand (rtx, bool);
33255ae3 106extern int neon_vector_mem_operand (rtx, int, bool);
88f77cba 107extern int neon_struct_mem_operand (rtx);
e32bac5b 108
d3585b76 109extern int tls_mentioned_p (rtx);
e32bac5b
RE		 110extern int symbol_mentioned_p (rtx);
111extern int label_mentioned_p (rtx);
112extern RTX_CODE minmax_code (rtx);
5d216c70 113extern bool arm_sat_operator_match (rtx, rtx, int *, bool *);
e32bac5b 114extern int adjacent_mem_locations (rtx, rtx);
37119410
BS		 115extern bool gen_ldm_seq (rtx *, int, bool);
116extern bool gen_stm_seq (rtx *, int);
117extern bool gen_const_stm_seq (rtx *, int);
118extern rtx arm_gen_load_multiple (int *, int, rtx, int, rtx, HOST_WIDE_INT *);
119extern rtx arm_gen_store_multiple (int *, int, rtx, int, rtx, HOST_WIDE_INT *);
56289ed2
SD		 120extern bool offset_ok_for_ldrd_strd (HOST_WIDE_INT);
121extern bool operands_ok_ldrd_strd (rtx, rtx, rtx, HOST_WIDE_INT, bool, bool);
4542a38a 122extern bool gen_operands_ldrd_strd (rtx *, bool, bool, bool);
70128ad9 123extern int arm_gen_movmemqi (rtx *);
798d3d04 124extern bool gen_movmem_ldrd_strd (rtx *);
ef4bddc2
RS		 125extern machine_mode arm_select_cc_mode (RTX_CODE, rtx, rtx);
126extern machine_mode arm_select_dominance_cc_mode (rtx, rtx,
e32bac5b 127 HOST_WIDE_INT);
18f0fe6b 128extern rtx arm_gen_compare_reg (RTX_CODE, rtx, rtx, rtx);
e32bac5b
RE		 129extern rtx arm_gen_return_addr_mask (void);
130extern void arm_reload_in_hi (rtx *);
131extern void arm_reload_out_hi (rtx *);
02231c13 132extern int arm_max_const_double_inline_cost (void);
2075b05d 133extern int arm_const_double_inline_cost (rtx);
b4a58f80 134extern bool arm_const_double_by_parts (rtx);
73160ba9 135extern bool arm_const_double_by_immediates (rtx);
7a32d6c4 136extern void arm_emit_call_insn (rtx, rtx, bool);
e32bac5b 137extern const char *output_call (rtx *);
571191af 138void arm_emit_movpair (rtx, rtx);
e32bac5b 139extern const char *output_mov_long_double_arm_from_arm (rtx *);
3598da80 140extern const char *output_move_double (rtx *, bool, int *count);
88f77cba 141extern const char *output_move_quad (rtx *);
3598da80 142extern int arm_count_output_move_double_insns (rtx *);
5b3e6663 143extern const char *output_move_vfp (rtx *operands);
88f77cba 144extern const char *output_move_neon (rtx *operands);
647d790d
DM		 145extern int arm_attr_length_move_neon (rtx_insn *);
146extern int arm_address_offset_is_imm (rtx_insn *);
e32bac5b
RE		 147extern const char *output_add_immediate (rtx *);
148extern const char *arithmetic_instr (rtx, int);
149extern void output_ascii_pseudo_op (FILE *, const unsigned char *, int);
f79b86a4 150extern const char *output_return_instruction (rtx, bool, bool, bool);
4fb94ef9 151extern const char *output_probe_stack_range (rtx, rtx);
e32bac5b 152extern void arm_poke_function_name (FILE *, const char *);
81e3f921 153extern void arm_final_prescan_insn (rtx_insn *);
e32bac5b 154extern int arm_debugger_arg_offset (int, rtx);
25a65198 155extern bool arm_is_long_call_p (tree);
5a9335ef 156extern int arm_emit_vector_const (FILE *, rtx);
0fd8c3ad 157extern void arm_emit_fp16_const (rtx c);
5a9335ef 158extern const char * arm_output_load_gr (rtx *);
b27832ed 159extern const char *vfp_output_vstmd (rtx *);
3aee1982 160extern void arm_output_multireg_pop (rtx *, bool, rtx, bool, bool);
c9ca9b88 161extern void arm_set_return_address (rtx, rtx);
6555b6bd 162extern int arm_eliminable_register (rtx);
5b3e6663 163extern const char *arm_output_shift(rtx *, int);
8fd03515
XQ		 164extern const char *arm_output_iwmmxt_shift_immediate (const char *, rtx *, bool);
165extern const char *arm_output_iwmmxt_tinsr (rtx *);
029e79eb 166extern unsigned int arm_sync_loop_insns (rtx , rtx *);
0c27e2d8 167extern int arm_attr_length_push_multi(rtx, rtx);
5775d58c 168extern int arm_attr_length_pop_multi(rtx *, bool, bool);
18f0fe6b
RH		 169extern void arm_expand_compare_and_swap (rtx op[]);
170extern void arm_split_compare_and_swap (rtx op[]);
171extern void arm_split_atomic_op (enum rtx_code, rtx, rtx, rtx, rtx, rtx, rtx);
f959607b 172extern rtx arm_load_tp (rtx);
d5b7b3ae
RE		 173
174#if defined TREE_CODE
e32bac5b 175extern void arm_init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, tree);
ef4bddc2
RS		 176extern bool arm_pad_arg_upward (machine_mode, const_tree);
177extern bool arm_pad_reg_upward (machine_mode, tree, int);
d5b7b3ae 178#endif
9f7bf991 179extern int arm_apply_result_size (void);
d5b7b3ae 180
eb3921e8
NC		 181#endif /* RTX_CODE */
182
d5b7b3ae 183/* Thumb functions. */
e32bac5b 184extern void arm_init_expanders (void);
90911ab6 185extern const char *thumb1_unexpanded_epilogue (void);
5b3e6663
PB		 186extern void thumb1_expand_prologue (void);
187extern void thumb1_expand_epilogue (void);
d018b46e 188extern const char *thumb1_output_interwork (void);
e32bac5b 189extern int thumb_shiftable_const (unsigned HOST_WIDE_INT);
cd2b33d0 190#ifdef RTX_CODE
723d95fe 191extern enum arm_cond_code maybe_get_arm_condition_code (rtx);
81e3f921
DM		 192extern void thumb1_final_prescan_insn (rtx_insn *);
193extern void thumb2_final_prescan_insn (rtx_insn *);
e32bac5b
RE		 194extern const char *thumb_load_double_from_address (rtx *);
195extern const char *thumb_output_move_mem_multiple (int, rtx *);
b12a00f1 196extern const char *thumb_call_via_reg (rtx);
70128ad9 197extern void thumb_expand_movmemqi (rtx *);
e32bac5b
RE		 198extern rtx arm_return_addr (int, rtx);
199extern void thumb_reload_out_hi (rtx *);
c9ca9b88 200extern void thumb_set_return_address (rtx, rtx);
907dd0c7
RE		 201extern const char *thumb1_output_casesi (rtx *);
202extern const char *thumb2_output_casesi (rtx *);
d5b7b3ae
RE		 203#endif
204
205/* Defined in pe.c. */
e32bac5b
RE		 206extern int arm_dllexport_name_p (const char *);
207extern int arm_dllimport_name_p (const char *);
d5b7b3ae
RE		 208
209#ifdef TREE_CODE
e32bac5b
RE		 210extern void arm_pe_unique_section (tree, int);
211extern void arm_pe_encode_section_info (tree, rtx, int);
212extern int arm_dllexport_p (tree);
213extern int arm_dllimport_p (tree);
214extern void arm_mark_dllexport (tree);
215extern void arm_mark_dllimport (tree);
d5524d52 216extern bool arm_change_mode_p (tree);
d5b7b3ae 217#endif
8b97c5f8 218
c84f825c
CB		 219extern tree arm_valid_target_attribute_tree (tree, struct gcc_options *,
220 struct gcc_options *);
e32bac5b
RE		 221extern void arm_pr_long_calls (struct cpp_reader *);
222extern void arm_pr_no_long_calls (struct cpp_reader *);
223extern void arm_pr_long_calls_off (struct cpp_reader *);
8b97c5f8 224
3101faab 225extern const char *arm_mangle_type (const_tree);
6276b630 226extern const char *arm_mangle_builtin_type (const_tree);
608063c3 227
795dc4fc
PB		 228extern void arm_order_regs_for_local_alloc (void);
229
b24a2ce5
GY		 230extern int arm_max_conditional_execute ();
231
2597da22
CL		 232/* Vectorizer cost model implementation. */
233struct cpu_vec_costs {
234 const int scalar_stmt_cost; /* Cost of any scalar operation, excluding
235 load and store. */
236 const int scalar_load_cost; /* Cost of scalar load. */
237 const int scalar_store_cost; /* Cost of scalar store. */
238 const int vec_stmt_cost; /* Cost of any vector operation, excluding
239 load, store, vector-to-scalar and
240 scalar-to-vector operation. */
241 const int vec_to_scalar_cost; /* Cost of vect-to-scalar operation. */
242 const int scalar_to_vec_cost; /* Cost of scalar-to-vector operation. */
243 const int vec_align_load_cost; /* Cost of aligned vector load. */
244 const int vec_unalign_load_cost; /* Cost of unaligned vector load. */
245 const int vec_unalign_store_cost; /* Cost of unaligned vector load. */
246 const int vec_store_cost; /* Cost of vector store. */
247 const int cond_taken_branch_cost; /* Cost of taken branch for vectorizer
248 cost model. */
249 const int cond_not_taken_branch_cost;/* Cost of not taken branch for
250 vectorizer cost model. */
251};
252
1b78f575
RE		 253#ifdef RTX_CODE
254/* This needs to be here because we need RTX_CODE and similar. */
255
5bea0c6c
KT		 256struct cpu_cost_table;
257
2301ca74
BC		 258/* Dump function ARM_PRINT_TUNE_INFO should be updated whenever this
259 structure is modified. */
260
1b78f575
RE		 261struct tune_params
262{
5bea0c6c 263 const struct cpu_cost_table *insn_extra_cost;
b505225b 264 bool (*sched_adjust_cost) (rtx_insn *, int, rtx_insn *, int *);
52c266ba
RE		 265 int (*branch_cost) (bool, bool);
266 /* Vectorizer costs. */
267 const struct cpu_vec_costs* vec_costs;
1b78f575 268 int constant_limit;
b24a2ce5 269 /* Maximum number of instructions to conditionalise. */
16868d84 270 int max_insns_skipped;
52c266ba
RE		 271 /* Maximum number of instructions to inline calls to memset. */
272 int max_insns_inline_memset;
273 /* Issue rate of the processor. */
274 unsigned int issue_rate;
275 /* Explicit prefetch data. */
276 struct
277 {
278 int num_slots;
279 int l1_cache_size;
280 int l1_cache_line_size;
281 } prefetch;
282 enum {PREF_CONST_POOL_FALSE, PREF_CONST_POOL_TRUE}
283 prefer_constant_pool: 1;
ab3dfff7 284 /* Prefer STRD/LDRD instructions over PUSH/POP/LDM/STM. */
52c266ba 285 enum {PREF_LDRD_FALSE, PREF_LDRD_TRUE} prefer_ldrd_strd: 1;
a51fb17f
BC		 286 /* The preference for non short cirtcuit operation when optimizing for
287 performance. The first element covers Thumb state and the second one
288 is for ARM state. */
ffa7068e
JG		 289 enum log_op_non_short_circuit {LOG_OP_NON_SHORT_CIRCUIT_FALSE,
290 LOG_OP_NON_SHORT_CIRCUIT_TRUE};
291 log_op_non_short_circuit logical_op_non_short_circuit_thumb: 1;
292 log_op_non_short_circuit logical_op_non_short_circuit_arm: 1;
46fbb3eb 293 /* Prefer 32-bit encoding instead of flag-setting 16-bit encoding. */
52c266ba
RE		 294 enum {DISPARAGE_FLAGS_NEITHER, DISPARAGE_FLAGS_PARTIAL, DISPARAGE_FLAGS_ALL}
295 disparage_flag_setting_t16_encodings: 2;
296 enum {PREF_NEON_64_FALSE, PREF_NEON_64_TRUE} prefer_neon_for_64bits: 1;
ad421159 297 /* Prefer to inline string operations like memset by using Neon. */
52c266ba
RE		 298 enum {PREF_NEON_STRINGOPS_FALSE, PREF_NEON_STRINGOPS_TRUE}
299 string_ops_prefer_neon: 1;
fe0b29c7 300 /* Bitfield encoding the fusible pairs of instructions. Use FUSE_OPS
52c266ba
RE		 301 in an initializer if multiple fusion operations are supported on a
302 target. */
303 enum fuse_ops
304 {
305 FUSE_NOTHING = 0,
066c14c9
WD		 306 FUSE_MOVW_MOVT = 1 << 0,
307 FUSE_AES_AESMC = 1 << 1
308 } fusible_ops: 2;
340c7904 309 /* Depth of scheduling queue to check for L2 autoprefetcher. */
52c266ba
RE		 310 enum {SCHED_AUTOPREF_OFF, SCHED_AUTOPREF_RANK, SCHED_AUTOPREF_FULL}
311 sched_autopref: 2;
1b78f575
RE		 312};
313
52c266ba
RE		 314/* Smash multiple fusion operations into a type that can be used for an
315 initializer. */
316#define FUSE_OPS(x) ((tune_params::fuse_ops) (x))
317
1b78f575 318extern const struct tune_params *current_tune;
7f3d8f56 319extern int vfp3_const_double_for_fract_bits (rtx);
c75d51aa
RL		 320/* return power of two from operand, otherwise 0. */
321extern int vfp3_const_double_for_bits (rtx);
99aea943
AS		 322
323extern void arm_emit_coreregs_64bit_shift (enum rtx_code, rtx, rtx, rtx, rtx,
324 rtx);
39fa4aec 325extern bool arm_fusion_enabled_p (tune_params::fuse_ops);
6ce43645 326extern bool arm_valid_symbolic_address_p (rtx);
95ffee1f 327extern bool arm_validize_comparison (rtx *, rtx *, rtx *);
1b78f575
RE		 328#endif /* RTX_CODE */
329
ad421159 330extern bool arm_gen_setmem (rtx *);
b440f324
RH		 331extern void arm_expand_vec_perm (rtx target, rtx op0, rtx op1, rtx sel);
332extern bool arm_expand_vec_perm_const (rtx target, rtx op0, rtx op1, rtx sel);
333
ef4bddc2 334extern bool arm_autoinc_modes_ok_p (machine_mode, enum arm_auto_incmodes);
8875e939 335
34dd397b
SB		 336extern void arm_emit_eabi_attribute (const char *, int, int);
337
d5524d52 338extern void arm_reset_previous_fndecl (void);
eeb085f3 339extern void save_restore_target_globals (tree);
d5524d52 340
b848e289
JG		 341/* Defined in gcc/common/config/arm-common.c. */
342extern const char *arm_rewrite_selected_cpu (const char *name);
343
7049e4eb
CB		 344/* Defined in gcc/common/config/arm-c.c. */
345extern void arm_lang_object_attributes_init (void);
c84f825c 346extern void arm_register_target_pragmas (void);
7049e4eb
CB		 347extern void arm_cpu_cpp_builtins (struct cpp_reader *);
348
aed773a2
CB		 349extern bool arm_is_constant_pool_ref (rtx);
350
a27d8d80
JG		 351/* Flags used to identify the presence of processor capabilities. */
352
353/* Bit values used to identify processor capabilities. */
05237cf8
TP		 354#define FL_NONE (0U) /* No flags. */
355#define FL_ANY (0xffffffffU) /* All flags. */
356#define FL_CO_PROC (1U << 0) /* Has external co-processor bus. */
357#define FL_ARCH3M (1U << 1) /* Extended multiply. */
358#define FL_MODE26 (1U << 2) /* 26-bit mode support. */
359#define FL_MODE32 (1U << 3) /* 32-bit mode support. */
360#define FL_ARCH4 (1U << 4) /* Architecture rel 4. */
361#define FL_ARCH5 (1U << 5) /* Architecture rel 5. */
362#define FL_THUMB (1U << 6) /* Thumb aware. */
363#define FL_LDSCHED (1U << 7) /* Load scheduling necessary. */
364#define FL_STRONG (1U << 8) /* StrongARM. */
365#define FL_ARCH5E (1U << 9) /* DSP extensions to v5. */
366#define FL_XSCALE (1U << 10) /* XScale. */
367/* spare (1U << 11) */
368#define FL_ARCH6 (1U << 12) /* Architecture rel 6. Adds
369 media instructions. */
370#define FL_VFPV2 (1U << 13) /* Vector Floating Point V2. */
371#define FL_WBUF (1U << 14) /* Schedule for write buffer ops.
372 Note: ARM6 & 7 derivatives only. */
373#define FL_ARCH6K (1U << 15) /* Architecture rel 6 K extensions. */
374#define FL_THUMB2 (1U << 16) /* Thumb-2. */
375#define FL_NOTM (1U << 17) /* Instructions not present in the 'M'
376 profile. */
377#define FL_THUMB_DIV (1U << 18) /* Hardware divide (Thumb mode). */
378#define FL_VFPV3 (1U << 19) /* Vector Floating Point V3. */
379#define FL_NEON (1U << 20) /* Neon instructions. */
380#define FL_ARCH7EM (1U << 21) /* Instructions present in the ARMv7E-M
381 architecture. */
382#define FL_ARCH7 (1U << 22) /* Architecture 7. */
383#define FL_ARM_DIV (1U << 23) /* Hardware divide (ARM mode). */
384#define FL_ARCH8 (1U << 24) /* Architecture 8. */
385#define FL_CRC32 (1U << 25) /* ARMv8 CRC32 instructions. */
386#define FL_SMALLMUL (1U << 26) /* Small multiply supported. */
387#define FL_NO_VOLATILE_CE (1U << 27) /* No volatile memory in IT block. */
388
389#define FL_IWMMXT (1U << 29) /* XScale v2 or "Intel Wireless MMX
390 technology". */
391#define FL_IWMMXT2 (1U << 30) /* "Intel Wireless MMX2
392 technology". */
393#define FL_ARCH6KZ (1U << 31) /* ARMv6KZ architecture. */
394
395#define FL2_ARCH8_1 (1U << 0) /* Architecture 8.1. */
396#define FL2_ARCH8_2 (1U << 1) /* Architecture 8.2. */
397#define FL2_FP16INST (1U << 2) /* FP16 Instructions for ARMv8.2 and
398 later. */
252e03b5 399
a27d8d80
JG		 400/* Flags that only effect tuning, not available instructions. */
401#define FL_TUNE (FL_WBUF | FL_VFPV2 | FL_STRONG | FL_LDSCHED \
402 | FL_CO_PROC)
403
3129a320
TP		 404#define FL_FOR_ARCH2 FL_NOTM
405#define FL_FOR_ARCH3 (FL_FOR_ARCH2 | FL_MODE32)
406#define FL_FOR_ARCH3M (FL_FOR_ARCH3 | FL_ARCH3M)
407#define FL_FOR_ARCH4 (FL_FOR_ARCH3M | FL_ARCH4)
408#define FL_FOR_ARCH4T (FL_FOR_ARCH4 | FL_THUMB)
409#define FL_FOR_ARCH5 (FL_FOR_ARCH4 | FL_ARCH5)
410#define FL_FOR_ARCH5T (FL_FOR_ARCH5 | FL_THUMB)
411#define FL_FOR_ARCH5E (FL_FOR_ARCH5 | FL_ARCH5E)
412#define FL_FOR_ARCH5TE (FL_FOR_ARCH5E | FL_THUMB)
413#define FL_FOR_ARCH5TEJ FL_FOR_ARCH5TE
414#define FL_FOR_ARCH6 (FL_FOR_ARCH5TE | FL_ARCH6)
415#define FL_FOR_ARCH6J FL_FOR_ARCH6
416#define FL_FOR_ARCH6K (FL_FOR_ARCH6 | FL_ARCH6K)
417#define FL_FOR_ARCH6Z FL_FOR_ARCH6
418#define FL_FOR_ARCH6ZK FL_FOR_ARCH6K
419#define FL_FOR_ARCH6KZ (FL_FOR_ARCH6K | FL_ARCH6KZ)
420#define FL_FOR_ARCH6T2 (FL_FOR_ARCH6 | FL_THUMB2)
421#define FL_FOR_ARCH6M (FL_FOR_ARCH6 & ~FL_NOTM)
422#define FL_FOR_ARCH7 ((FL_FOR_ARCH6T2 & ~FL_NOTM) | FL_ARCH7)
423#define FL_FOR_ARCH7A (FL_FOR_ARCH7 | FL_NOTM | FL_ARCH6K)
424#define FL_FOR_ARCH7VE (FL_FOR_ARCH7A | FL_THUMB_DIV | FL_ARM_DIV)
425#define FL_FOR_ARCH7R (FL_FOR_ARCH7A | FL_THUMB_DIV)
426#define FL_FOR_ARCH7M (FL_FOR_ARCH7 | FL_THUMB_DIV)
427#define FL_FOR_ARCH7EM (FL_FOR_ARCH7M | FL_ARCH7EM)
428#define FL_FOR_ARCH8A (FL_FOR_ARCH7VE | FL_ARCH8)
252e03b5 429#define FL2_FOR_ARCH8_1A FL2_ARCH8_1
4040b89a 430#define FL2_FOR_ARCH8_2A (FL2_FOR_ARCH8_1A | FL2_ARCH8_2)
05a437c1
TP		 431#define FL_FOR_ARCH8M_BASE (FL_FOR_ARCH6M | FL_ARCH8 | FL_THUMB_DIV)
432#define FL_FOR_ARCH8M_MAIN (FL_FOR_ARCH7M | FL_ARCH8)
a27d8d80 433
427388a4
MW		 434/* There are too many feature bits to fit in a single word so the set of cpu and
435 fpu capabilities is a structure. A feature set is created and manipulated
436 with the ARM_FSET macros. */
437
438typedef struct
439{
05237cf8 440 unsigned cpu[2];
427388a4
MW		 441} arm_feature_set;
442
443
444/* Initialize a feature set. */
445
446#define ARM_FSET_MAKE(CPU1,CPU2) { { (CPU1), (CPU2) } }
447
448#define ARM_FSET_MAKE_CPU1(CPU1) ARM_FSET_MAKE ((CPU1), (FL_NONE))
449#define ARM_FSET_MAKE_CPU2(CPU2) ARM_FSET_MAKE ((FL_NONE), (CPU2))
450
451/* Accessors. */
452
453#define ARM_FSET_CPU1(S) ((S).cpu[0])
454#define ARM_FSET_CPU2(S) ((S).cpu[1])
455
456/* Useful combinations. */
457
458#define ARM_FSET_EMPTY ARM_FSET_MAKE (FL_NONE, FL_NONE)
459#define ARM_FSET_ANY ARM_FSET_MAKE (FL_ANY, FL_ANY)
460
461/* Tests for a specific CPU feature. */
462
463#define ARM_FSET_HAS_CPU1(A, F) \
464 (((A).cpu[0] & ((unsigned long)(F))) == ((unsigned long)(F)))
465#define ARM_FSET_HAS_CPU2(A, F) \
466 (((A).cpu[1] & ((unsigned long)(F))) == ((unsigned long)(F)))
467#define ARM_FSET_HAS_CPU(A, F1, F2) \
468 (ARM_FSET_HAS_CPU1 ((A), (F1)) && ARM_FSET_HAS_CPU2 ((A), (F2)))
469
470/* Add a feature to a feature set. */
471
472#define ARM_FSET_ADD_CPU1(DST, F) \
473 do { \
474 (DST).cpu[0] |= (F); \
475 } while (0)
476
477#define ARM_FSET_ADD_CPU2(DST, F) \
478 do { \
479 (DST).cpu[1] |= (F); \
480 } while (0)
481
482/* Remove a feature from a feature set. */
483
484#define ARM_FSET_DEL_CPU1(DST, F) \
485 do { \
486 (DST).cpu[0] &= ~(F); \
487 } while (0)
488
489#define ARM_FSET_DEL_CPU2(DST, F) \
490 do { \
491 (DST).cpu[1] &= ~(F); \
492 } while (0)
493
494/* Union of feature sets. */
495
496#define ARM_FSET_UNION(DST,F1,F2) \
497 do { \
498 (DST).cpu[0] = (F1).cpu[0] | (F2).cpu[0]; \
499 (DST).cpu[1] = (F1).cpu[1] | (F2).cpu[1]; \
500 } while (0)
501
502/* Intersection of feature sets. */
503
504#define ARM_FSET_INTER(DST,F1,F2) \
505 do { \
506 (DST).cpu[0] = (F1).cpu[0] & (F2).cpu[0]; \
507 (DST).cpu[1] = (F1).cpu[1] & (F2).cpu[1]; \
508 } while (0)
509
510/* Exclusive disjunction. */
511
512#define ARM_FSET_XOR(DST,F1,F2) \
513 do { \
514 (DST).cpu[0] = (F1).cpu[0] ^ (F2).cpu[0]; \
515 (DST).cpu[1] = (F1).cpu[1] ^ (F2).cpu[1]; \
516 } while (0)
517
518/* Difference of feature sets: F1 excluding the elements of F2. */
519
520#define ARM_FSET_EXCLUDE(DST,F1,F2) \
521 do { \
522 (DST).cpu[0] = (F1).cpu[0] & ~(F2).cpu[0]; \
523 (DST).cpu[1] = (F1).cpu[1] & ~(F2).cpu[1]; \
524 } while (0)
525
526/* Test for an empty feature set. */
527
528#define ARM_FSET_IS_EMPTY(A) \
529 (!((A).cpu[0]) && !((A).cpu[1]))
530
531/* Tests whether the cpu features of A are a subset of B. */
532
533#define ARM_FSET_CPU_SUBSET(A,B) \
534 ((((A).cpu[0] & (B).cpu[0]) == (A).cpu[0]) \
535 && (((A).cpu[1] & (B).cpu[1]) == (A).cpu[1]))
536
a27d8d80
JG		 537/* The bits in this mask specify which
538 instructions we are allowed to generate. */
a1c54ebf 539extern arm_feature_set insn_flags;
a27d8d80
JG		 540
541/* The bits in this mask specify which instruction scheduling options should
542 be used. */
a1c54ebf 543extern arm_feature_set tune_flags;
a27d8d80
JG		 544
545/* Nonzero if this chip supports the ARM Architecture 3M extensions. */
546extern int arm_arch3m;
547
548/* Nonzero if this chip supports the ARM Architecture 4 extensions. */
549extern int arm_arch4;
550
551/* Nonzero if this chip supports the ARM Architecture 4t extensions. */
552extern int arm_arch4t;
553
554/* Nonzero if this chip supports the ARM Architecture 5 extensions. */
555extern int arm_arch5;
556
557/* Nonzero if this chip supports the ARM Architecture 5E extensions. */
558extern int arm_arch5e;
559
560/* Nonzero if this chip supports the ARM Architecture 6 extensions. */
561extern int arm_arch6;
562
563/* Nonzero if this chip supports the ARM 6K extensions. */
564extern int arm_arch6k;
565
39c12541
MW		 566/* Nonzero if this chip supports the ARM 6KZ extensions. */
567extern int arm_arch6kz;
568
a27d8d80
JG		 569/* Nonzero if instructions present in ARMv6-M can be used. */
570extern int arm_arch6m;
571
572/* Nonzero if this chip supports the ARM 7 extensions. */
573extern int arm_arch7;
574
575/* Nonzero if instructions not present in the 'M' profile can be used. */
576extern int arm_arch_notm;
577
578/* Nonzero if instructions present in ARMv7E-M can be used. */
579extern int arm_arch7em;
580
581/* Nonzero if instructions present in ARMv8 can be used. */
582extern int arm_arch8;
583
584/* Nonzero if this chip can benefit from load scheduling. */
585extern int arm_ld_sched;
586
587/* Nonzero if this chip is a StrongARM. */
588extern int arm_tune_strongarm;
589
590/* Nonzero if this chip supports Intel Wireless MMX technology. */
591extern int arm_arch_iwmmxt;
592
593/* Nonzero if this chip supports Intel Wireless MMX2 technology. */
594extern int arm_arch_iwmmxt2;
595
596/* Nonzero if this chip is an XScale. */
597extern int arm_arch_xscale;
598
599/* Nonzero if tuning for XScale */
600extern int arm_tune_xscale;
601
602/* Nonzero if we want to tune for stores that access the write-buffer.
603 This typically means an ARM6 or ARM7 with MMU or MPU. */
604extern int arm_tune_wbuf;
605
606/* Nonzero if tuning for Cortex-A9. */
607extern int arm_tune_cortex_a9;
608
a27d8d80
JG		 609/* Nonzero if we should define __THUMB_INTERWORK__ in the
610 preprocessor.
611 XXX This is a bit of a hack, it's intended to help work around
612 problems in GLD which doesn't understand that armv5t code is
613 interworking clean. */
614extern int arm_cpp_interwork;
615
52545641
TP		 616/* Nonzero if chip supports Thumb 1. */
617extern int arm_arch_thumb1;
618
a27d8d80
JG		 619/* Nonzero if chip supports Thumb 2. */
620extern int arm_arch_thumb2;
621
622/* Nonzero if chip supports integer division instruction. */
623extern int arm_arch_arm_hwdiv;
624extern int arm_arch_thumb_hwdiv;
625
afe006ad
TG		 626/* Nonzero if chip disallows volatile memory access in IT block. */
627extern int arm_arch_no_volatile_ce;
628
a27d8d80
JG		 629/* Nonzero if we should use Neon to handle 64-bits operations rather
630 than core registers. */
631extern int prefer_neon_for_64bits;
632
633
634
88657302 635#endif /* ! GCC_ARM_PROTOS_H */
Mirror of https://gcc.gnu.org/git/gcc.git