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e53b6e56 | 1 | /* Prototypes for exported functions defined in arm.cc and pe.c |
aeee4812 | 2 | Copyright (C) 1999-2023 Free Software Foundation, Inc. |
eb3921e8 NC |
3 | Contributed by Richard Earnshaw (rearnsha@arm.com) |
4 | Minor hacks by Nick Clifton (nickc@cygnus.com) | |
5 | ||
4f448245 | 6 | This file is part of GCC. |
eb3921e8 | 7 | |
4f448245 NC |
8 | GCC is free software; you can redistribute it and/or modify |
9 | it under the terms of the GNU General Public License as published by | |
2f83c7d6 | 10 | the Free Software Foundation; either version 3, or (at your option) |
4f448245 | 11 | any later version. |
eb3921e8 | 12 | |
4f448245 NC |
13 | GCC is distributed in the hope that it will be useful, |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
eb3921e8 | 17 | |
4f448245 | 18 | You should have received a copy of the GNU General Public License |
2f83c7d6 NC |
19 | along with GCC; see the file COPYING3. If not see |
20 | <http://www.gnu.org/licenses/>. */ | |
eb3921e8 | 21 | |
8b97c5f8 ZW |
22 | #ifndef GCC_ARM_PROTOS_H |
23 | #define GCC_ARM_PROTOS_H | |
24 | ||
851966d6 | 25 | #include "sbitmap.h" |
70e73d3c | 26 | |
db6b9a9d AC |
27 | rtl_opt_pass *make_pass_insert_bti (gcc::context *ctxt); |
28 | ||
677f3fa8 | 29 | extern enum unwind_info_type arm_except_unwind_info (struct gcc_options *); |
a72d4945 | 30 | extern int use_return_insn (int, rtx); |
24d5b097 | 31 | extern bool use_simple_return_p (void); |
bbbbb16a | 32 | extern enum reg_class arm_regno_class (int); |
cf16f980 KT |
33 | extern bool arm_check_builtin_call (location_t , vec<location_t> , tree, |
34 | tree, unsigned int, tree *); | |
89d75572 | 35 | extern void arm_load_pic_register (unsigned long, rtx); |
e32bac5b | 36 | extern int arm_volatile_func (void); |
e32bac5b | 37 | extern void arm_expand_prologue (void); |
d461c88a | 38 | extern void arm_expand_epilogue (bool); |
258619bb | 39 | extern void arm_declare_function_name (FILE *, const char *, tree); |
9ad1f699 | 40 | extern void arm_asm_declare_function_name (FILE *, const char *, tree); |
24d5b097 | 41 | extern void thumb2_expand_return (bool); |
e32bac5b RE |
42 | extern const char *arm_strip_name_encoding (const char *); |
43 | extern void arm_asm_output_labelref (FILE *, const char *); | |
5b3e6663 | 44 | extern void thumb2_asm_output_opcode (FILE *); |
e32bac5b | 45 | extern unsigned long arm_current_func_type (void); |
b3f8d95d MM |
46 | extern HOST_WIDE_INT arm_compute_initial_elimination_offset (unsigned int, |
47 | unsigned int); | |
5848830f PB |
48 | extern HOST_WIDE_INT thumb_compute_initial_elimination_offset (unsigned int, |
49 | unsigned int); | |
ca60bd93 | 50 | extern unsigned int arm_debugger_regno (unsigned int); |
617a1b71 | 51 | extern void arm_output_fn_unwind (FILE *, bool); |
33857df2 JG |
52 | |
53 | extern rtx arm_expand_builtin (tree exp, rtx target, rtx subtarget | |
b8506a8a | 54 | ATTRIBUTE_UNUSED, machine_mode mode |
33857df2 JG |
55 | ATTRIBUTE_UNUSED, int ignore ATTRIBUTE_UNUSED); |
56 | extern tree arm_builtin_decl (unsigned code, bool initialize_p | |
57 | ATTRIBUTE_UNUSED); | |
58 | extern void arm_init_builtins (void); | |
59 | extern void arm_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update); | |
93c590ee MC |
60 | extern rtx arm_simd_vect_par_cnst_half (machine_mode mode, bool high); |
61 | extern bool arm_simd_check_vect_par_cnst_half_p (rtx op, machine_mode mode, | |
62 | bool high); | |
ebdb6f23 | 63 | extern void arm_emit_speculation_barrier_function (void); |
0406dccd | 64 | extern void arm_decompose_di_binop (rtx, rtx, rtx *, rtx *, rtx *, rtx *); |
cf16f980 | 65 | extern bool arm_q_bit_access (void); |
16155ccf | 66 | extern bool arm_ge_bits_access (void); |
d2ed233c | 67 | extern bool arm_target_insn_ok_for_lob (rtx); |
ebdb6f23 | 68 | |
eb3921e8 | 69 | #ifdef RTX_CODE |
d91524d5 SP |
70 | enum reg_class |
71 | arm_mode_base_reg_class (machine_mode); | |
c8cd4696 MC |
72 | extern void arm_gen_unlikely_cbranch (enum rtx_code, machine_mode cc_mode, |
73 | rtx label_ref); | |
ef4bddc2 RS |
74 | extern bool arm_vector_mode_supported_p (machine_mode); |
75 | extern bool arm_small_register_classes_for_mode_p (machine_mode); | |
e32bac5b | 76 | extern int const_ok_for_arm (HOST_WIDE_INT); |
c2b640a7 | 77 | extern int const_ok_for_op (HOST_WIDE_INT, enum rtx_code); |
44cd6810 | 78 | extern int const_ok_for_dimode_op (HOST_WIDE_INT, enum rtx_code); |
011f5e92 | 79 | extern void thumb1_gen_const_int_rtl (rtx, HOST_WIDE_INT); |
c7f49e05 | 80 | extern void thumb1_gen_const_int_print (rtx, HOST_WIDE_INT); |
ef4bddc2 | 81 | extern int arm_split_constant (RTX_CODE, machine_mode, rtx, |
a406f566 | 82 | HOST_WIDE_INT, rtx, rtx, int); |
e32bac5b | 83 | extern int legitimate_pic_operand_p (rtx); |
89d75572 | 84 | extern rtx legitimize_pic_address (rtx, machine_mode, rtx, rtx, bool); |
d3585b76 | 85 | extern rtx legitimize_tls_address (rtx, rtx); |
ef4bddc2 RS |
86 | extern bool arm_legitimate_address_p (machine_mode, rtx, bool); |
87 | extern int arm_legitimate_address_outer_p (machine_mode, rtx, RTX_CODE, int); | |
88 | extern int thumb_legitimate_offset_p (machine_mode, HOST_WIDE_INT); | |
ef4bddc2 RS |
89 | extern int thumb1_legitimate_address_p (machine_mode, rtx, int); |
90 | extern bool ldm_stm_operation_p (rtx, bool, machine_mode mode, | |
fb40241d | 91 | bool, bool); |
0b1c7b27 | 92 | extern bool clear_operation_p (rtx, bool); |
9b66ebb1 | 93 | extern int arm_const_double_rtx (rtx); |
f1adb0a9 | 94 | extern int vfp3_const_double_rtx (rtx); |
63c8f7d6 | 95 | extern int simd_immediate_valid_for_move (rtx, machine_mode, rtx *, int *); |
ef4bddc2 | 96 | extern int neon_immediate_valid_for_logic (rtx, machine_mode, int, rtx *, |
88f77cba | 97 | int *); |
ef4bddc2 | 98 | extern int neon_immediate_valid_for_shift (rtx, machine_mode, rtx *, |
31a0c825 | 99 | int *, bool); |
88f77cba | 100 | extern char *neon_output_logic_immediate (const char *, rtx *, |
ef4bddc2 | 101 | machine_mode, int, int); |
31a0c825 | 102 | extern char *neon_output_shift_immediate (const char *, char, rtx *, |
ef4bddc2 RS |
103 | machine_mode, int, bool); |
104 | extern void neon_pairwise_reduce (rtx, rtx, machine_mode, | |
88f77cba | 105 | rtx (*) (rtx, rtx, rtx)); |
91224cf6 | 106 | extern rtx mve_bool_vec_to_const (rtx const_vec); |
150a829a | 107 | extern rtx neon_make_constant (rtx, bool generate = true); |
88f77cba | 108 | extern void neon_expand_vector_init (rtx, rtx); |
eaa80f64 | 109 | extern void neon_lane_bounds (rtx, HOST_WIDE_INT, HOST_WIDE_INT, const_tree); |
d57daa0c | 110 | extern void arm_const_bounds (rtx, HOST_WIDE_INT, HOST_WIDE_INT); |
ef4bddc2 | 111 | extern HOST_WIDE_INT neon_element_bits (machine_mode); |
ef4bddc2 | 112 | extern void neon_emit_pair_result_insn (machine_mode, |
88f77cba JB |
113 | rtx (*) (rtx, rtx, rtx, rtx), |
114 | rtx, rtx, rtx); | |
115 | extern void neon_disambiguate_copy (rtx *, rtx *, rtx *, unsigned int); | |
b440f324 | 116 | extern void neon_split_vcombine (rtx op[3]); |
ef4bddc2 | 117 | extern enum reg_class coproc_secondary_reload_class (machine_mode, rtx, |
fe2d934b | 118 | bool); |
d3585b76 | 119 | extern bool arm_tls_referenced_p (rtx); |
d5b7b3ae | 120 | |
fdd695fd | 121 | extern int arm_coproc_mem_operand (rtx, bool); |
9f6abd2d JR |
122 | extern int arm_coproc_mem_operand_no_writeback (rtx); |
123 | extern int arm_coproc_mem_operand_wb (rtx, int); | |
33255ae3 | 124 | extern int neon_vector_mem_operand (rtx, int, bool); |
d91524d5 | 125 | extern int mve_vector_mem_operand (machine_mode, rtx, bool); |
88f77cba | 126 | extern int neon_struct_mem_operand (rtx); |
4269a656 | 127 | extern int mve_struct_mem_operand (rtx); |
e32bac5b | 128 | |
ee8045e5 | 129 | extern rtx *neon_vcmla_lane_prepare_operands (rtx *); |
c2b7062d | 130 | |
d3585b76 | 131 | extern int tls_mentioned_p (rtx); |
e32bac5b RE |
132 | extern int symbol_mentioned_p (rtx); |
133 | extern int label_mentioned_p (rtx); | |
134 | extern RTX_CODE minmax_code (rtx); | |
5d216c70 | 135 | extern bool arm_sat_operator_match (rtx, rtx, int *, bool *); |
e32bac5b | 136 | extern int adjacent_mem_locations (rtx, rtx); |
37119410 BS |
137 | extern bool gen_ldm_seq (rtx *, int, bool); |
138 | extern bool gen_stm_seq (rtx *, int); | |
139 | extern bool gen_const_stm_seq (rtx *, int); | |
140 | extern rtx arm_gen_load_multiple (int *, int, rtx, int, rtx, HOST_WIDE_INT *); | |
141 | extern rtx arm_gen_store_multiple (int *, int, rtx, int, rtx, HOST_WIDE_INT *); | |
56289ed2 SD |
142 | extern bool offset_ok_for_ldrd_strd (HOST_WIDE_INT); |
143 | extern bool operands_ok_ldrd_strd (rtx, rtx, rtx, HOST_WIDE_INT, bool, bool); | |
4542a38a | 144 | extern bool gen_operands_ldrd_strd (rtx *, bool, bool, bool); |
c272bbda | 145 | extern bool valid_operands_ldrd_strd (rtx *, bool); |
76715c32 AS |
146 | extern int arm_gen_cpymemqi (rtx *); |
147 | extern bool gen_cpymem_ldrd_strd (rtx *); | |
ef4bddc2 RS |
148 | extern machine_mode arm_select_cc_mode (RTX_CODE, rtx, rtx); |
149 | extern machine_mode arm_select_dominance_cc_mode (rtx, rtx, | |
e32bac5b | 150 | HOST_WIDE_INT); |
18f0fe6b | 151 | extern rtx arm_gen_compare_reg (RTX_CODE, rtx, rtx, rtx); |
e32bac5b RE |
152 | extern rtx arm_gen_return_addr_mask (void); |
153 | extern void arm_reload_in_hi (rtx *); | |
154 | extern void arm_reload_out_hi (rtx *); | |
02231c13 | 155 | extern int arm_max_const_double_inline_cost (void); |
2075b05d | 156 | extern int arm_const_double_inline_cost (rtx); |
b4a58f80 | 157 | extern bool arm_const_double_by_parts (rtx); |
73160ba9 | 158 | extern bool arm_const_double_by_immediates (rtx); |
8b63716e | 159 | extern rtx arm_load_function_descriptor (rtx funcdesc); |
7a32d6c4 | 160 | extern void arm_emit_call_insn (rtx, rtx, bool); |
c92e08e3 | 161 | bool detect_cmse_nonsecure_call (tree); |
e32bac5b | 162 | extern const char *output_call (rtx *); |
571191af | 163 | void arm_emit_movpair (rtx, rtx); |
e32bac5b | 164 | extern const char *output_mov_long_double_arm_from_arm (rtx *); |
3598da80 | 165 | extern const char *output_move_double (rtx *, bool, int *count); |
88f77cba | 166 | extern const char *output_move_quad (rtx *); |
3598da80 | 167 | extern int arm_count_output_move_double_insns (rtx *); |
c272bbda | 168 | extern int arm_count_ldrdstrd_insns (rtx *, bool); |
5b3e6663 | 169 | extern const char *output_move_vfp (rtx *operands); |
88f77cba | 170 | extern const char *output_move_neon (rtx *operands); |
647d790d DM |
171 | extern int arm_attr_length_move_neon (rtx_insn *); |
172 | extern int arm_address_offset_is_imm (rtx_insn *); | |
e32bac5b RE |
173 | extern const char *output_add_immediate (rtx *); |
174 | extern const char *arithmetic_instr (rtx, int); | |
175 | extern void output_ascii_pseudo_op (FILE *, const unsigned char *, int); | |
f79b86a4 | 176 | extern const char *output_return_instruction (rtx, bool, bool, bool); |
4fb94ef9 | 177 | extern const char *output_probe_stack_range (rtx, rtx); |
e32bac5b | 178 | extern void arm_poke_function_name (FILE *, const char *); |
81e3f921 | 179 | extern void arm_final_prescan_insn (rtx_insn *); |
e32bac5b | 180 | extern int arm_debugger_arg_offset (int, rtx); |
25a65198 | 181 | extern bool arm_is_long_call_p (tree); |
5a9335ef | 182 | extern int arm_emit_vector_const (FILE *, rtx); |
0fd8c3ad | 183 | extern void arm_emit_fp16_const (rtx c); |
5a9335ef | 184 | extern const char * arm_output_load_gr (rtx *); |
b27832ed | 185 | extern const char *vfp_output_vstmd (rtx *); |
3aee1982 | 186 | extern void arm_output_multireg_pop (rtx *, bool, rtx, bool, bool); |
c9ca9b88 | 187 | extern void arm_set_return_address (rtx, rtx); |
6555b6bd | 188 | extern int arm_eliminable_register (rtx); |
5b3e6663 | 189 | extern const char *arm_output_shift(rtx *, int); |
8fd03515 XQ |
190 | extern const char *arm_output_iwmmxt_shift_immediate (const char *, rtx *, bool); |
191 | extern const char *arm_output_iwmmxt_tinsr (rtx *); | |
029e79eb | 192 | extern unsigned int arm_sync_loop_insns (rtx , rtx *); |
0c27e2d8 | 193 | extern int arm_attr_length_push_multi(rtx, rtx); |
5775d58c | 194 | extern int arm_attr_length_pop_multi(rtx *, bool, bool); |
18f0fe6b RH |
195 | extern void arm_expand_compare_and_swap (rtx op[]); |
196 | extern void arm_split_compare_and_swap (rtx op[]); | |
197 | extern void arm_split_atomic_op (enum rtx_code, rtx, rtx, rtx, rtx, rtx, rtx); | |
f959607b | 198 | extern rtx arm_load_tp (rtx); |
d57daa0c | 199 | extern bool arm_coproc_builtin_available (enum unspecv); |
3811581f | 200 | extern bool arm_coproc_ldc_stc_legitimate_address (rtx); |
9d7a84b9 AB |
201 | extern rtx arm_stack_protect_tls_canary_mem (bool); |
202 | ||
d5b7b3ae RE |
203 | |
204 | #if defined TREE_CODE | |
e32bac5b | 205 | extern void arm_init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, tree); |
ef4bddc2 | 206 | extern bool arm_pad_reg_upward (machine_mode, tree, int); |
d5b7b3ae | 207 | #endif |
9f7bf991 | 208 | extern int arm_apply_result_size (void); |
df0e57c2 | 209 | extern opt_machine_mode arm_get_mask_mode (machine_mode mode); |
d5b7b3ae | 210 | |
eb3921e8 NC |
211 | #endif /* RTX_CODE */ |
212 | ||
9d7c64fa CL |
213 | /* It's convenient to divide the built-in function codes into groups, |
214 | rather than having everything in a single enum. This type enumerates | |
215 | those groups. */ | |
216 | enum arm_builtin_class | |
217 | { | |
218 | ARM_BUILTIN_GENERAL | |
219 | }; | |
220 | ||
221 | /* Built-in function codes are structured so that the low | |
222 | ARM_BUILTIN_SHIFT bits contain the arm_builtin_class | |
223 | and the upper bits contain a group-specific subcode. */ | |
224 | const unsigned int ARM_BUILTIN_SHIFT = 1; | |
225 | ||
226 | /* Mask that selects the arm part of a function code. */ | |
227 | const unsigned int ARM_BUILTIN_CLASS = (1 << ARM_BUILTIN_SHIFT) - 1; | |
228 | ||
9c1ce17b MS |
229 | /* MVE functions. */ |
230 | namespace arm_mve { | |
231 | void handle_arm_mve_types_h (); | |
232 | } | |
233 | ||
d5b7b3ae | 234 | /* Thumb functions. */ |
e32bac5b | 235 | extern void arm_init_expanders (void); |
90911ab6 | 236 | extern const char *thumb1_unexpanded_epilogue (void); |
5b3e6663 PB |
237 | extern void thumb1_expand_prologue (void); |
238 | extern void thumb1_expand_epilogue (void); | |
d018b46e | 239 | extern const char *thumb1_output_interwork (void); |
e32bac5b | 240 | extern int thumb_shiftable_const (unsigned HOST_WIDE_INT); |
cd2b33d0 | 241 | #ifdef RTX_CODE |
723d95fe | 242 | extern enum arm_cond_code maybe_get_arm_condition_code (rtx); |
81e3f921 DM |
243 | extern void thumb1_final_prescan_insn (rtx_insn *); |
244 | extern void thumb2_final_prescan_insn (rtx_insn *); | |
e32bac5b RE |
245 | extern const char *thumb_load_double_from_address (rtx *); |
246 | extern const char *thumb_output_move_mem_multiple (int, rtx *); | |
b12a00f1 | 247 | extern const char *thumb_call_via_reg (rtx); |
76715c32 | 248 | extern void thumb_expand_cpymemqi (rtx *); |
e32bac5b RE |
249 | extern rtx arm_return_addr (int, rtx); |
250 | extern void thumb_reload_out_hi (rtx *); | |
c9ca9b88 | 251 | extern void thumb_set_return_address (rtx, rtx); |
907dd0c7 RE |
252 | extern const char *thumb1_output_casesi (rtx *); |
253 | extern const char *thumb2_output_casesi (rtx *); | |
d5b7b3ae RE |
254 | #endif |
255 | ||
256 | /* Defined in pe.c. */ | |
e32bac5b RE |
257 | extern int arm_dllexport_name_p (const char *); |
258 | extern int arm_dllimport_name_p (const char *); | |
d5b7b3ae RE |
259 | |
260 | #ifdef TREE_CODE | |
e32bac5b RE |
261 | extern void arm_pe_unique_section (tree, int); |
262 | extern void arm_pe_encode_section_info (tree, rtx, int); | |
263 | extern int arm_dllexport_p (tree); | |
264 | extern int arm_dllimport_p (tree); | |
265 | extern void arm_mark_dllexport (tree); | |
266 | extern void arm_mark_dllimport (tree); | |
d5524d52 | 267 | extern bool arm_change_mode_p (tree); |
d5b7b3ae | 268 | #endif |
8b97c5f8 | 269 | |
c84f825c CB |
270 | extern tree arm_valid_target_attribute_tree (tree, struct gcc_options *, |
271 | struct gcc_options *); | |
851966d6 | 272 | extern void arm_configure_build_target (struct arm_build_target *, |
262e75d2 | 273 | struct cl_target_option *, bool); |
008a11cc TC |
274 | extern void arm_option_reconfigure_globals (void); |
275 | extern void arm_options_perform_arch_sanity_checks (void); | |
e32bac5b RE |
276 | extern void arm_pr_long_calls (struct cpp_reader *); |
277 | extern void arm_pr_no_long_calls (struct cpp_reader *); | |
278 | extern void arm_pr_long_calls_off (struct cpp_reader *); | |
8b97c5f8 | 279 | |
3101faab | 280 | extern const char *arm_mangle_type (const_tree); |
6276b630 | 281 | extern const char *arm_mangle_builtin_type (const_tree); |
608063c3 | 282 | |
795dc4fc PB |
283 | extern void arm_order_regs_for_local_alloc (void); |
284 | ||
b24a2ce5 GY |
285 | extern int arm_max_conditional_execute (); |
286 | ||
2597da22 CL |
287 | /* Vectorizer cost model implementation. */ |
288 | struct cpu_vec_costs { | |
289 | const int scalar_stmt_cost; /* Cost of any scalar operation, excluding | |
290 | load and store. */ | |
291 | const int scalar_load_cost; /* Cost of scalar load. */ | |
292 | const int scalar_store_cost; /* Cost of scalar store. */ | |
293 | const int vec_stmt_cost; /* Cost of any vector operation, excluding | |
294 | load, store, vector-to-scalar and | |
295 | scalar-to-vector operation. */ | |
296 | const int vec_to_scalar_cost; /* Cost of vect-to-scalar operation. */ | |
297 | const int scalar_to_vec_cost; /* Cost of scalar-to-vector operation. */ | |
298 | const int vec_align_load_cost; /* Cost of aligned vector load. */ | |
299 | const int vec_unalign_load_cost; /* Cost of unaligned vector load. */ | |
300 | const int vec_unalign_store_cost; /* Cost of unaligned vector load. */ | |
301 | const int vec_store_cost; /* Cost of vector store. */ | |
302 | const int cond_taken_branch_cost; /* Cost of taken branch for vectorizer | |
303 | cost model. */ | |
304 | const int cond_not_taken_branch_cost;/* Cost of not taken branch for | |
305 | vectorizer cost model. */ | |
306 | }; | |
307 | ||
1b78f575 RE |
308 | #ifdef RTX_CODE |
309 | /* This needs to be here because we need RTX_CODE and similar. */ | |
310 | ||
5bea0c6c KT |
311 | struct cpu_cost_table; |
312 | ||
612ea540 CB |
313 | /* Addressing mode operations. Used to index tables in struct |
314 | addr_mode_cost_table. */ | |
315 | enum arm_addr_mode_op | |
316 | { | |
317 | AMO_DEFAULT, | |
318 | AMO_NO_WB, /* Offset with no writeback. */ | |
319 | AMO_WB, /* Offset with writeback. */ | |
320 | AMO_MAX /* For array size. */ | |
321 | }; | |
322 | ||
323 | /* Table of additional costs in units of COSTS_N_INSNS() when using | |
324 | addressing modes for each access type. */ | |
325 | struct addr_mode_cost_table | |
326 | { | |
327 | const int integer[AMO_MAX]; | |
328 | const int fp[AMO_MAX]; | |
329 | const int vector[AMO_MAX]; | |
330 | }; | |
331 | ||
2301ca74 BC |
332 | /* Dump function ARM_PRINT_TUNE_INFO should be updated whenever this |
333 | structure is modified. */ | |
334 | ||
1b78f575 RE |
335 | struct tune_params |
336 | { | |
5bea0c6c | 337 | const struct cpu_cost_table *insn_extra_cost; |
612ea540 | 338 | const struct addr_mode_cost_table *addr_mode_costs; |
b505225b | 339 | bool (*sched_adjust_cost) (rtx_insn *, int, rtx_insn *, int *); |
52c266ba RE |
340 | int (*branch_cost) (bool, bool); |
341 | /* Vectorizer costs. */ | |
342 | const struct cpu_vec_costs* vec_costs; | |
1b78f575 | 343 | int constant_limit; |
b24a2ce5 | 344 | /* Maximum number of instructions to conditionalise. */ |
16868d84 | 345 | int max_insns_skipped; |
52c266ba RE |
346 | /* Maximum number of instructions to inline calls to memset. */ |
347 | int max_insns_inline_memset; | |
348 | /* Issue rate of the processor. */ | |
349 | unsigned int issue_rate; | |
350 | /* Explicit prefetch data. */ | |
351 | struct | |
352 | { | |
353 | int num_slots; | |
354 | int l1_cache_size; | |
355 | int l1_cache_line_size; | |
356 | } prefetch; | |
357 | enum {PREF_CONST_POOL_FALSE, PREF_CONST_POOL_TRUE} | |
358 | prefer_constant_pool: 1; | |
ab3dfff7 | 359 | /* Prefer STRD/LDRD instructions over PUSH/POP/LDM/STM. */ |
52c266ba | 360 | enum {PREF_LDRD_FALSE, PREF_LDRD_TRUE} prefer_ldrd_strd: 1; |
a51fb17f BC |
361 | /* The preference for non short cirtcuit operation when optimizing for |
362 | performance. The first element covers Thumb state and the second one | |
363 | is for ARM state. */ | |
ffa7068e JG |
364 | enum log_op_non_short_circuit {LOG_OP_NON_SHORT_CIRCUIT_FALSE, |
365 | LOG_OP_NON_SHORT_CIRCUIT_TRUE}; | |
366 | log_op_non_short_circuit logical_op_non_short_circuit_thumb: 1; | |
367 | log_op_non_short_circuit logical_op_non_short_circuit_arm: 1; | |
46fbb3eb | 368 | /* Prefer 32-bit encoding instead of flag-setting 16-bit encoding. */ |
52c266ba RE |
369 | enum {DISPARAGE_FLAGS_NEITHER, DISPARAGE_FLAGS_PARTIAL, DISPARAGE_FLAGS_ALL} |
370 | disparage_flag_setting_t16_encodings: 2; | |
ad421159 | 371 | /* Prefer to inline string operations like memset by using Neon. */ |
52c266ba RE |
372 | enum {PREF_NEON_STRINGOPS_FALSE, PREF_NEON_STRINGOPS_TRUE} |
373 | string_ops_prefer_neon: 1; | |
fe0b29c7 | 374 | /* Bitfield encoding the fusible pairs of instructions. Use FUSE_OPS |
52c266ba RE |
375 | in an initializer if multiple fusion operations are supported on a |
376 | target. */ | |
377 | enum fuse_ops | |
378 | { | |
379 | FUSE_NOTHING = 0, | |
066c14c9 WD |
380 | FUSE_MOVW_MOVT = 1 << 0, |
381 | FUSE_AES_AESMC = 1 << 1 | |
382 | } fusible_ops: 2; | |
340c7904 | 383 | /* Depth of scheduling queue to check for L2 autoprefetcher. */ |
52c266ba RE |
384 | enum {SCHED_AUTOPREF_OFF, SCHED_AUTOPREF_RANK, SCHED_AUTOPREF_FULL} |
385 | sched_autopref: 2; | |
1b78f575 RE |
386 | }; |
387 | ||
52c266ba RE |
388 | /* Smash multiple fusion operations into a type that can be used for an |
389 | initializer. */ | |
390 | #define FUSE_OPS(x) ((tune_params::fuse_ops) (x)) | |
391 | ||
1b78f575 | 392 | extern const struct tune_params *current_tune; |
7f3d8f56 | 393 | extern int vfp3_const_double_for_fract_bits (rtx); |
c75d51aa RL |
394 | /* return power of two from operand, otherwise 0. */ |
395 | extern int vfp3_const_double_for_bits (rtx); | |
99aea943 AS |
396 | |
397 | extern void arm_emit_coreregs_64bit_shift (enum rtx_code, rtx, rtx, rtx, rtx, | |
398 | rtx); | |
39fa4aec | 399 | extern bool arm_fusion_enabled_p (tune_params::fuse_ops); |
651460b4 | 400 | extern bool arm_current_function_pac_enabled_p (void); |
6ce43645 | 401 | extern bool arm_valid_symbolic_address_p (rtx); |
95ffee1f | 402 | extern bool arm_validize_comparison (rtx *, rtx *, rtx *); |
df0e57c2 | 403 | extern bool arm_expand_vector_compare (rtx, rtx_code, rtx, rtx, bool); |
1b78f575 RE |
404 | #endif /* RTX_CODE */ |
405 | ||
ad421159 | 406 | extern bool arm_gen_setmem (rtx *); |
c2978b34 | 407 | extern void arm_expand_vcond (rtx *, machine_mode); |
b440f324 | 408 | extern void arm_expand_vec_perm (rtx target, rtx op0, rtx op1, rtx sel); |
b440f324 | 409 | |
ef4bddc2 | 410 | extern bool arm_autoinc_modes_ok_p (machine_mode, enum arm_auto_incmodes); |
8875e939 | 411 | |
34dd397b SB |
412 | extern void arm_emit_eabi_attribute (const char *, int, int); |
413 | ||
d5524d52 | 414 | extern void arm_reset_previous_fndecl (void); |
eeb085f3 | 415 | extern void save_restore_target_globals (tree); |
d5524d52 | 416 | |
e53b6e56 | 417 | /* Defined in gcc/common/config/arm-common.cc. */ |
b848e289 JG |
418 | extern const char *arm_rewrite_selected_cpu (const char *name); |
419 | ||
e53b6e56 | 420 | /* Defined in gcc/common/config/arm-c.cc. */ |
7049e4eb | 421 | extern void arm_lang_object_attributes_init (void); |
c84f825c | 422 | extern void arm_register_target_pragmas (void); |
7049e4eb CB |
423 | extern void arm_cpu_cpp_builtins (struct cpp_reader *); |
424 | ||
aed773a2 CB |
425 | extern bool arm_is_constant_pool_ref (rtx); |
426 | ||
a27d8d80 JG |
427 | /* The bits in this mask specify which instruction scheduling options should |
428 | be used. */ | |
643a5717 | 429 | extern unsigned int tune_flags; |
a27d8d80 | 430 | |
a27d8d80 JG |
431 | /* Nonzero if this chip supports the ARM Architecture 4 extensions. */ |
432 | extern int arm_arch4; | |
433 | ||
434 | /* Nonzero if this chip supports the ARM Architecture 4t extensions. */ | |
435 | extern int arm_arch4t; | |
436 | ||
c3f808d3 KT |
437 | /* Nonzero if this chip supports the ARM Architecture 5t extensions. */ |
438 | extern int arm_arch5t; | |
a27d8d80 | 439 | |
c3f808d3 KT |
440 | /* Nonzero if this chip supports the ARM Architecture 5te extensions. */ |
441 | extern int arm_arch5te; | |
a27d8d80 JG |
442 | |
443 | /* Nonzero if this chip supports the ARM Architecture 6 extensions. */ | |
444 | extern int arm_arch6; | |
445 | ||
446 | /* Nonzero if this chip supports the ARM 6K extensions. */ | |
447 | extern int arm_arch6k; | |
448 | ||
39c12541 MW |
449 | /* Nonzero if this chip supports the ARM 6KZ extensions. */ |
450 | extern int arm_arch6kz; | |
451 | ||
a27d8d80 JG |
452 | /* Nonzero if instructions present in ARMv6-M can be used. */ |
453 | extern int arm_arch6m; | |
454 | ||
455 | /* Nonzero if this chip supports the ARM 7 extensions. */ | |
456 | extern int arm_arch7; | |
457 | ||
bf634d1c TP |
458 | /* Nonzero if this chip supports the Large Physical Address Extension. */ |
459 | extern int arm_arch_lpae; | |
6c466c7c | 460 | |
a27d8d80 JG |
461 | /* Nonzero if instructions not present in the 'M' profile can be used. */ |
462 | extern int arm_arch_notm; | |
463 | ||
464 | /* Nonzero if instructions present in ARMv7E-M can be used. */ | |
465 | extern int arm_arch7em; | |
466 | ||
467 | /* Nonzero if instructions present in ARMv8 can be used. */ | |
468 | extern int arm_arch8; | |
469 | ||
470 | /* Nonzero if this chip can benefit from load scheduling. */ | |
471 | extern int arm_ld_sched; | |
472 | ||
473 | /* Nonzero if this chip is a StrongARM. */ | |
474 | extern int arm_tune_strongarm; | |
475 | ||
476 | /* Nonzero if this chip supports Intel Wireless MMX technology. */ | |
477 | extern int arm_arch_iwmmxt; | |
478 | ||
479 | /* Nonzero if this chip supports Intel Wireless MMX2 technology. */ | |
480 | extern int arm_arch_iwmmxt2; | |
481 | ||
482 | /* Nonzero if this chip is an XScale. */ | |
483 | extern int arm_arch_xscale; | |
484 | ||
485 | /* Nonzero if tuning for XScale */ | |
486 | extern int arm_tune_xscale; | |
487 | ||
488 | /* Nonzero if we want to tune for stores that access the write-buffer. | |
489 | This typically means an ARM6 or ARM7 with MMU or MPU. */ | |
490 | extern int arm_tune_wbuf; | |
491 | ||
492 | /* Nonzero if tuning for Cortex-A9. */ | |
493 | extern int arm_tune_cortex_a9; | |
494 | ||
a27d8d80 JG |
495 | /* Nonzero if we should define __THUMB_INTERWORK__ in the |
496 | preprocessor. | |
497 | XXX This is a bit of a hack, it's intended to help work around | |
498 | problems in GLD which doesn't understand that armv5t code is | |
499 | interworking clean. */ | |
500 | extern int arm_cpp_interwork; | |
501 | ||
52545641 TP |
502 | /* Nonzero if chip supports Thumb 1. */ |
503 | extern int arm_arch_thumb1; | |
504 | ||
a27d8d80 JG |
505 | /* Nonzero if chip supports Thumb 2. */ |
506 | extern int arm_arch_thumb2; | |
507 | ||
508 | /* Nonzero if chip supports integer division instruction. */ | |
509 | extern int arm_arch_arm_hwdiv; | |
510 | extern int arm_arch_thumb_hwdiv; | |
511 | ||
afe006ad TG |
512 | /* Nonzero if chip disallows volatile memory access in IT block. */ |
513 | extern int arm_arch_no_volatile_ce; | |
514 | ||
8341f8c4 RE |
515 | /* Structure defining the current overall architectural target and tuning. */ |
516 | struct arm_build_target | |
517 | { | |
518 | /* Name of the target CPU, if known, or NULL if the target CPU was not | |
519 | specified by the user (and inferred from the -march option). */ | |
520 | const char *core_name; | |
521 | /* Name of the target ARCH. NULL if there is a selected CPU. */ | |
522 | const char *arch_name; | |
523 | /* Preprocessor substring (never NULL). */ | |
524 | const char *arch_pp_name; | |
8341f8c4 RE |
525 | /* The base architecture value. */ |
526 | enum base_architecture base_arch; | |
8afb5358 RE |
527 | /* The profile letter for the architecture, upper case by convention. */ |
528 | char profile; | |
8341f8c4 RE |
529 | /* Bitmap encapsulating the isa_bits for the target environment. */ |
530 | sbitmap isa; | |
531 | /* Flags used for tuning. Long term, these move into tune_params. */ | |
532 | unsigned int tune_flags; | |
533 | /* Tables with more detailed tuning information. */ | |
534 | const struct tune_params *tune; | |
535 | /* CPU identifier for the tuning target. */ | |
536 | enum processor_type tune_core; | |
537 | }; | |
538 | ||
539 | extern struct arm_build_target arm_active_target; | |
a27d8d80 | 540 | |
d4f680c6 RE |
541 | /* Table entry for a CPU alias. */ |
542 | struct cpu_alias | |
543 | { | |
544 | /* The alias name. */ | |
545 | const char *const name; | |
546 | /* True if the name should be displayed in help text listing cpu names. */ | |
547 | bool visible; | |
548 | }; | |
549 | ||
550 | /* Table entry for an architectural feature extension. */ | |
050809ed RE |
551 | struct cpu_arch_extension |
552 | { | |
357e1023 | 553 | /* Feature name. */ |
050809ed | 554 | const char *const name; |
357e1023 | 555 | /* True if the option is negative (removes extensions). */ |
050809ed | 556 | bool remove; |
357e1023 RE |
557 | /* True if the option is an alias for another option with identical effect; |
558 | the option will be ignored for canonicalization. */ | |
559 | bool alias; | |
560 | /* The modifier bits. */ | |
050809ed RE |
561 | const enum isa_feature isa_bits[isa_num_bits]; |
562 | }; | |
563 | ||
d4f680c6 | 564 | /* Common elements of both CPU and architectural options. */ |
050809ed RE |
565 | struct cpu_arch_option |
566 | { | |
567 | /* Name for this option. */ | |
568 | const char *name; | |
569 | /* List of feature extensions permitted. */ | |
570 | const struct cpu_arch_extension *extensions; | |
571 | /* Standard feature bits. */ | |
572 | enum isa_feature isa_bits[isa_num_bits]; | |
573 | }; | |
574 | ||
d4f680c6 | 575 | /* Table entry for an architecture entry. */ |
050809ed RE |
576 | struct arch_option |
577 | { | |
578 | /* Common option fields. */ | |
579 | cpu_arch_option common; | |
580 | /* Short string for this architecture. */ | |
581 | const char *arch; | |
582 | /* Base architecture, from which this specific architecture is derived. */ | |
583 | enum base_architecture base_arch; | |
8afb5358 RE |
584 | /* The profile letter for the architecture, upper case by convention. */ |
585 | const char profile; | |
050809ed RE |
586 | /* Default tune target (in the absence of any more specific data). */ |
587 | enum processor_type tune_id; | |
588 | }; | |
589 | ||
d4f680c6 | 590 | /* Table entry for a CPU entry. */ |
050809ed RE |
591 | struct cpu_option |
592 | { | |
593 | /* Common option fields. */ | |
594 | cpu_arch_option common; | |
d4f680c6 RE |
595 | /* List of aliases for this CPU. */ |
596 | const struct cpu_alias *aliases; | |
050809ed RE |
597 | /* Architecture upon which this CPU is based. */ |
598 | enum arch_type arch; | |
599 | }; | |
a27d8d80 | 600 | |
435d1272 RE |
601 | extern const arch_option all_architectures[]; |
602 | extern const cpu_option all_cores[]; | |
603 | ||
d8dadbc9 | 604 | |
435d1272 | 605 | const cpu_option *arm_parse_cpu_option_name (const cpu_option *, const char *, |
a4017ff7 | 606 | const char *, bool = true); |
435d1272 | 607 | const arch_option *arm_parse_arch_option_name (const arch_option *, |
a4017ff7 | 608 | const char *, const char *, bool = true); |
435d1272 RE |
609 | void arm_parse_option_features (sbitmap, const cpu_arch_option *, |
610 | const char *); | |
611 | ||
612 | void arm_initialize_isa (sbitmap, const enum isa_feature *); | |
613 | ||
44f77a6d SMW |
614 | const char * arm_gen_far_branch (rtx *, int, const char * , const char *); |
615 | ||
f2170a37 | 616 | bool arm_mve_immediate_check(rtx, machine_mode, bool); |
88657302 | 617 | #endif /* ! GCC_ARM_PROTOS_H */ |