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eb3921e8 1/* Prototypes for exported functions defined in arm.c and pe.c
818ab71a 2 Copyright (C) 1999-2016 Free Software Foundation, Inc.
eb3921e8
NC		 3 Contributed by Richard Earnshaw (rearnsha@arm.com)
4 Minor hacks by Nick Clifton (nickc@cygnus.com)
5
4f448245 6 This file is part of GCC.
eb3921e8 7
4f448245
NC		 8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
2f83c7d6 10 the Free Software Foundation; either version 3, or (at your option)
4f448245 11 any later version.
eb3921e8 12
4f448245
NC		 13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
eb3921e8 17
4f448245 18 You should have received a copy of the GNU General Public License
2f83c7d6
NC		 19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
eb3921e8 21
8b97c5f8
ZW		 22#ifndef GCC_ARM_PROTOS_H
23#define GCC_ARM_PROTOS_H
24
677f3fa8 25extern enum unwind_info_type arm_except_unwind_info (struct gcc_options *);
a72d4945 26extern int use_return_insn (int, rtx);
24d5b097 27extern bool use_simple_return_p (void);
bbbbb16a 28extern enum reg_class arm_regno_class (int);
e55ef7f4 29extern void arm_load_pic_register (unsigned long);
e32bac5b 30extern int arm_volatile_func (void);
e32bac5b 31extern void arm_expand_prologue (void);
d461c88a 32extern void arm_expand_epilogue (bool);
258619bb 33extern void arm_declare_function_name (FILE *, const char *, tree);
24d5b097 34extern void thumb2_expand_return (bool);
e32bac5b
RE		 35extern const char *arm_strip_name_encoding (const char *);
36extern void arm_asm_output_labelref (FILE *, const char *);
5b3e6663 37extern void thumb2_asm_output_opcode (FILE *);
e32bac5b 38extern unsigned long arm_current_func_type (void);
b3f8d95d
MM		 39extern HOST_WIDE_INT arm_compute_initial_elimination_offset (unsigned int,
40 unsigned int);
5848830f
PB		 41extern HOST_WIDE_INT thumb_compute_initial_elimination_offset (unsigned int,
42 unsigned int);
2fa330b2 43extern unsigned int arm_dbx_register_number (unsigned int);
617a1b71 44extern void arm_output_fn_unwind (FILE *, bool);
33857df2
JG		 45
46extern rtx arm_expand_builtin (tree exp, rtx target, rtx subtarget
47 ATTRIBUTE_UNUSED, enum machine_mode mode
48 ATTRIBUTE_UNUSED, int ignore ATTRIBUTE_UNUSED);
49extern tree arm_builtin_decl (unsigned code, bool initialize_p
50 ATTRIBUTE_UNUSED);
51extern void arm_init_builtins (void);
52extern void arm_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update);
93c590ee
MC		 53extern rtx arm_simd_vect_par_cnst_half (machine_mode mode, bool high);
54extern bool arm_simd_check_vect_par_cnst_half_p (rtx op, machine_mode mode,
55 bool high);
eb3921e8 56#ifdef RTX_CODE
ef4bddc2
RS		 57extern bool arm_vector_mode_supported_p (machine_mode);
58extern bool arm_small_register_classes_for_mode_p (machine_mode);
59extern int arm_hard_regno_mode_ok (unsigned int, machine_mode);
60extern bool arm_modes_tieable_p (machine_mode, machine_mode);
e32bac5b 61extern int const_ok_for_arm (HOST_WIDE_INT);
c2b640a7 62extern int const_ok_for_op (HOST_WIDE_INT, enum rtx_code);
44cd6810 63extern int const_ok_for_dimode_op (HOST_WIDE_INT, enum rtx_code);
ef4bddc2 64extern int arm_split_constant (RTX_CODE, machine_mode, rtx,
a406f566 65 HOST_WIDE_INT, rtx, rtx, int);
e32bac5b 66extern int legitimate_pic_operand_p (rtx);
ef4bddc2 67extern rtx legitimize_pic_address (rtx, machine_mode, rtx);
d3585b76 68extern rtx legitimize_tls_address (rtx, rtx);
ef4bddc2
RS		 69extern bool arm_legitimate_address_p (machine_mode, rtx, bool);
70extern int arm_legitimate_address_outer_p (machine_mode, rtx, RTX_CODE, int);
71extern int thumb_legitimate_offset_p (machine_mode, HOST_WIDE_INT);
ef4bddc2
RS		 72extern int thumb1_legitimate_address_p (machine_mode, rtx, int);
73extern bool ldm_stm_operation_p (rtx, bool, machine_mode mode,
fb40241d 74 bool, bool);
9b66ebb1 75extern int arm_const_double_rtx (rtx);
f1adb0a9 76extern int vfp3_const_double_rtx (rtx);
ef4bddc2
RS		 77extern int neon_immediate_valid_for_move (rtx, machine_mode, rtx *, int *);
78extern int neon_immediate_valid_for_logic (rtx, machine_mode, int, rtx *,
88f77cba 79 int *);
ef4bddc2 80extern int neon_immediate_valid_for_shift (rtx, machine_mode, rtx *,
31a0c825 81 int *, bool);
88f77cba 82extern char *neon_output_logic_immediate (const char *, rtx *,
ef4bddc2 83 machine_mode, int, int);
31a0c825 84extern char *neon_output_shift_immediate (const char *, char, rtx *,
ef4bddc2
RS		 85 machine_mode, int, bool);
86extern void neon_pairwise_reduce (rtx, rtx, machine_mode,
88f77cba 87 rtx (*) (rtx, rtx, rtx));
814a4c3b 88extern rtx neon_make_constant (rtx);
10766209 89extern tree arm_builtin_vectorized_function (unsigned int, tree, tree);
88f77cba 90extern void neon_expand_vector_init (rtx, rtx);
eaa80f64 91extern void neon_lane_bounds (rtx, HOST_WIDE_INT, HOST_WIDE_INT, const_tree);
b617fc71 92extern void neon_const_bounds (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
ef4bddc2 93extern HOST_WIDE_INT neon_element_bits (machine_mode);
ef4bddc2 94extern void neon_emit_pair_result_insn (machine_mode,
88f77cba
JB		 95 rtx (*) (rtx, rtx, rtx, rtx),
96 rtx, rtx, rtx);
97extern void neon_disambiguate_copy (rtx *, rtx *, rtx *, unsigned int);
b440f324 98extern void neon_split_vcombine (rtx op[3]);
ef4bddc2 99extern enum reg_class coproc_secondary_reload_class (machine_mode, rtx,
fe2d934b 100 bool);
d3585b76 101extern bool arm_tls_referenced_p (rtx);
d5b7b3ae 102
fdd695fd 103extern int arm_coproc_mem_operand (rtx, bool);
33255ae3 104extern int neon_vector_mem_operand (rtx, int, bool);
88f77cba 105extern int neon_struct_mem_operand (rtx);
e32bac5b 106
d3585b76 107extern int tls_mentioned_p (rtx);
e32bac5b
RE		 108extern int symbol_mentioned_p (rtx);
109extern int label_mentioned_p (rtx);
110extern RTX_CODE minmax_code (rtx);
5d216c70 111extern bool arm_sat_operator_match (rtx, rtx, int *, bool *);
e32bac5b 112extern int adjacent_mem_locations (rtx, rtx);
37119410
BS		 113extern bool gen_ldm_seq (rtx *, int, bool);
114extern bool gen_stm_seq (rtx *, int);
115extern bool gen_const_stm_seq (rtx *, int);
116extern rtx arm_gen_load_multiple (int *, int, rtx, int, rtx, HOST_WIDE_INT *);
117extern rtx arm_gen_store_multiple (int *, int, rtx, int, rtx, HOST_WIDE_INT *);
56289ed2
SD		 118extern bool offset_ok_for_ldrd_strd (HOST_WIDE_INT);
119extern bool operands_ok_ldrd_strd (rtx, rtx, rtx, HOST_WIDE_INT, bool, bool);
4542a38a 120extern bool gen_operands_ldrd_strd (rtx *, bool, bool, bool);
70128ad9 121extern int arm_gen_movmemqi (rtx *);
798d3d04 122extern bool gen_movmem_ldrd_strd (rtx *);
ef4bddc2
RS		 123extern machine_mode arm_select_cc_mode (RTX_CODE, rtx, rtx);
124extern machine_mode arm_select_dominance_cc_mode (rtx, rtx,
e32bac5b 125 HOST_WIDE_INT);
18f0fe6b 126extern rtx arm_gen_compare_reg (RTX_CODE, rtx, rtx, rtx);
e32bac5b
RE		 127extern rtx arm_gen_return_addr_mask (void);
128extern void arm_reload_in_hi (rtx *);
129extern void arm_reload_out_hi (rtx *);
02231c13 130extern int arm_max_const_double_inline_cost (void);
2075b05d 131extern int arm_const_double_inline_cost (rtx);
b4a58f80 132extern bool arm_const_double_by_parts (rtx);
73160ba9 133extern bool arm_const_double_by_immediates (rtx);
7a32d6c4 134extern void arm_emit_call_insn (rtx, rtx, bool);
e32bac5b 135extern const char *output_call (rtx *);
571191af 136void arm_emit_movpair (rtx, rtx);
e32bac5b 137extern const char *output_mov_long_double_arm_from_arm (rtx *);
3598da80 138extern const char *output_move_double (rtx *, bool, int *count);
88f77cba 139extern const char *output_move_quad (rtx *);
3598da80 140extern int arm_count_output_move_double_insns (rtx *);
5b3e6663 141extern const char *output_move_vfp (rtx *operands);
88f77cba 142extern const char *output_move_neon (rtx *operands);
647d790d
DM		 143extern int arm_attr_length_move_neon (rtx_insn *);
144extern int arm_address_offset_is_imm (rtx_insn *);
e32bac5b
RE		 145extern const char *output_add_immediate (rtx *);
146extern const char *arithmetic_instr (rtx, int);
147extern void output_ascii_pseudo_op (FILE *, const unsigned char *, int);
f79b86a4 148extern const char *output_return_instruction (rtx, bool, bool, bool);
4fb94ef9 149extern const char *output_probe_stack_range (rtx, rtx);
e32bac5b 150extern void arm_poke_function_name (FILE *, const char *);
81e3f921 151extern void arm_final_prescan_insn (rtx_insn *);
e32bac5b 152extern int arm_debugger_arg_offset (int, rtx);
25a65198 153extern bool arm_is_long_call_p (tree);
5a9335ef 154extern int arm_emit_vector_const (FILE *, rtx);
0fd8c3ad 155extern void arm_emit_fp16_const (rtx c);
5a9335ef 156extern const char * arm_output_load_gr (rtx *);
b27832ed 157extern const char *vfp_output_vstmd (rtx *);
3aee1982 158extern void arm_output_multireg_pop (rtx *, bool, rtx, bool, bool);
c9ca9b88 159extern void arm_set_return_address (rtx, rtx);
6555b6bd 160extern int arm_eliminable_register (rtx);
5b3e6663 161extern const char *arm_output_shift(rtx *, int);
8fd03515
XQ		 162extern const char *arm_output_iwmmxt_shift_immediate (const char *, rtx *, bool);
163extern const char *arm_output_iwmmxt_tinsr (rtx *);
029e79eb 164extern unsigned int arm_sync_loop_insns (rtx , rtx *);
0c27e2d8 165extern int arm_attr_length_push_multi(rtx, rtx);
18f0fe6b
RH		 166extern void arm_expand_compare_and_swap (rtx op[]);
167extern void arm_split_compare_and_swap (rtx op[]);
168extern void arm_split_atomic_op (enum rtx_code, rtx, rtx, rtx, rtx, rtx, rtx);
f959607b 169extern rtx arm_load_tp (rtx);
d5b7b3ae
RE		 170
171#if defined TREE_CODE
e32bac5b 172extern void arm_init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, tree);
ef4bddc2
RS		 173extern bool arm_pad_arg_upward (machine_mode, const_tree);
174extern bool arm_pad_reg_upward (machine_mode, tree, int);
d5b7b3ae 175#endif
9f7bf991 176extern int arm_apply_result_size (void);
d5b7b3ae 177
eb3921e8
NC		 178#endif /* RTX_CODE */
179
d5b7b3ae 180/* Thumb functions. */
e32bac5b 181extern void arm_init_expanders (void);
90911ab6 182extern const char *thumb1_unexpanded_epilogue (void);
5b3e6663
PB		 183extern void thumb1_expand_prologue (void);
184extern void thumb1_expand_epilogue (void);
d018b46e 185extern const char *thumb1_output_interwork (void);
e32bac5b 186extern int thumb_shiftable_const (unsigned HOST_WIDE_INT);
cd2b33d0 187#ifdef RTX_CODE
723d95fe 188extern enum arm_cond_code maybe_get_arm_condition_code (rtx);
81e3f921
DM		 189extern void thumb1_final_prescan_insn (rtx_insn *);
190extern void thumb2_final_prescan_insn (rtx_insn *);
e32bac5b
RE		 191extern const char *thumb_load_double_from_address (rtx *);
192extern const char *thumb_output_move_mem_multiple (int, rtx *);
b12a00f1 193extern const char *thumb_call_via_reg (rtx);
70128ad9 194extern void thumb_expand_movmemqi (rtx *);
e32bac5b
RE		 195extern rtx arm_return_addr (int, rtx);
196extern void thumb_reload_out_hi (rtx *);
197extern void thumb_reload_in_hi (rtx *);
c9ca9b88 198extern void thumb_set_return_address (rtx, rtx);
907dd0c7
RE		 199extern const char *thumb1_output_casesi (rtx *);
200extern const char *thumb2_output_casesi (rtx *);
d5b7b3ae
RE		 201#endif
202
203/* Defined in pe.c. */
e32bac5b
RE		 204extern int arm_dllexport_name_p (const char *);
205extern int arm_dllimport_name_p (const char *);
d5b7b3ae
RE		 206
207#ifdef TREE_CODE
e32bac5b
RE		 208extern void arm_pe_unique_section (tree, int);
209extern void arm_pe_encode_section_info (tree, rtx, int);
210extern int arm_dllexport_p (tree);
211extern int arm_dllimport_p (tree);
212extern void arm_mark_dllexport (tree);
213extern void arm_mark_dllimport (tree);
d5524d52 214extern bool arm_change_mode_p (tree);
d5b7b3ae 215#endif
8b97c5f8 216
c84f825c
CB		 217extern tree arm_valid_target_attribute_tree (tree, struct gcc_options *,
218 struct gcc_options *);
e32bac5b
RE		 219extern void arm_pr_long_calls (struct cpp_reader *);
220extern void arm_pr_no_long_calls (struct cpp_reader *);
221extern void arm_pr_long_calls_off (struct cpp_reader *);
8b97c5f8 222
3101faab 223extern const char *arm_mangle_type (const_tree);
6276b630 224extern const char *arm_mangle_builtin_type (const_tree);
608063c3 225
795dc4fc
PB		 226extern void arm_order_regs_for_local_alloc (void);
227
b24a2ce5
GY		 228extern int arm_max_conditional_execute ();
229
2597da22
CL		 230/* Vectorizer cost model implementation. */
231struct cpu_vec_costs {
232 const int scalar_stmt_cost; /* Cost of any scalar operation, excluding
233 load and store. */
234 const int scalar_load_cost; /* Cost of scalar load. */
235 const int scalar_store_cost; /* Cost of scalar store. */
236 const int vec_stmt_cost; /* Cost of any vector operation, excluding
237 load, store, vector-to-scalar and
238 scalar-to-vector operation. */
239 const int vec_to_scalar_cost; /* Cost of vect-to-scalar operation. */
240 const int scalar_to_vec_cost; /* Cost of scalar-to-vector operation. */
241 const int vec_align_load_cost; /* Cost of aligned vector load. */
242 const int vec_unalign_load_cost; /* Cost of unaligned vector load. */
243 const int vec_unalign_store_cost; /* Cost of unaligned vector load. */
244 const int vec_store_cost; /* Cost of vector store. */
245 const int cond_taken_branch_cost; /* Cost of taken branch for vectorizer
246 cost model. */
247 const int cond_not_taken_branch_cost;/* Cost of not taken branch for
248 vectorizer cost model. */
249};
250
1b78f575
RE		 251#ifdef RTX_CODE
252/* This needs to be here because we need RTX_CODE and similar. */
253
5bea0c6c
KT		 254struct cpu_cost_table;
255
2301ca74
BC		 256/* Dump function ARM_PRINT_TUNE_INFO should be updated whenever this
257 structure is modified. */
258
1b78f575
RE		 259struct tune_params
260{
261 bool (*rtx_costs) (rtx, RTX_CODE, RTX_CODE, int *, bool);
5bea0c6c 262 const struct cpu_cost_table *insn_extra_cost;
647d790d 263 bool (*sched_adjust_cost) (rtx_insn *, rtx, rtx_insn *, int *);
52c266ba
RE		 264 int (*branch_cost) (bool, bool);
265 /* Vectorizer costs. */
266 const struct cpu_vec_costs* vec_costs;
1b78f575 267 int constant_limit;
b24a2ce5 268 /* Maximum number of instructions to conditionalise. */
16868d84 269 int max_insns_skipped;
52c266ba
RE		 270 /* Maximum number of instructions to inline calls to memset. */
271 int max_insns_inline_memset;
272 /* Issue rate of the processor. */
273 unsigned int issue_rate;
274 /* Explicit prefetch data. */
275 struct
276 {
277 int num_slots;
278 int l1_cache_size;
279 int l1_cache_line_size;
280 } prefetch;
281 enum {PREF_CONST_POOL_FALSE, PREF_CONST_POOL_TRUE}
282 prefer_constant_pool: 1;
ab3dfff7 283 /* Prefer STRD/LDRD instructions over PUSH/POP/LDM/STM. */
52c266ba 284 enum {PREF_LDRD_FALSE, PREF_LDRD_TRUE} prefer_ldrd_strd: 1;
a51fb17f
BC		 285 /* The preference for non short cirtcuit operation when optimizing for
286 performance. The first element covers Thumb state and the second one
287 is for ARM state. */
ffa7068e
JG		 288 enum log_op_non_short_circuit {LOG_OP_NON_SHORT_CIRCUIT_FALSE,
289 LOG_OP_NON_SHORT_CIRCUIT_TRUE};
290 log_op_non_short_circuit logical_op_non_short_circuit_thumb: 1;
291 log_op_non_short_circuit logical_op_non_short_circuit_arm: 1;
46fbb3eb 292 /* Prefer 32-bit encoding instead of flag-setting 16-bit encoding. */
52c266ba
RE		 293 enum {DISPARAGE_FLAGS_NEITHER, DISPARAGE_FLAGS_PARTIAL, DISPARAGE_FLAGS_ALL}
294 disparage_flag_setting_t16_encodings: 2;
295 enum {PREF_NEON_64_FALSE, PREF_NEON_64_TRUE} prefer_neon_for_64bits: 1;
ad421159 296 /* Prefer to inline string operations like memset by using Neon. */
52c266ba
RE		 297 enum {PREF_NEON_STRINGOPS_FALSE, PREF_NEON_STRINGOPS_TRUE}
298 string_ops_prefer_neon: 1;
fe0b29c7 299 /* Bitfield encoding the fusible pairs of instructions. Use FUSE_OPS
52c266ba
RE		 300 in an initializer if multiple fusion operations are supported on a
301 target. */
302 enum fuse_ops
303 {
304 FUSE_NOTHING = 0,
066c14c9
WD		 305 FUSE_MOVW_MOVT = 1 << 0,
306 FUSE_AES_AESMC = 1 << 1
307 } fusible_ops: 2;
340c7904 308 /* Depth of scheduling queue to check for L2 autoprefetcher. */
52c266ba
RE		 309 enum {SCHED_AUTOPREF_OFF, SCHED_AUTOPREF_RANK, SCHED_AUTOPREF_FULL}
310 sched_autopref: 2;
1b78f575
RE		 311};
312
52c266ba
RE		 313/* Smash multiple fusion operations into a type that can be used for an
314 initializer. */
315#define FUSE_OPS(x) ((tune_params::fuse_ops) (x))
316
1b78f575 317extern const struct tune_params *current_tune;
7f3d8f56 318extern int vfp3_const_double_for_fract_bits (rtx);
c75d51aa
RL		 319/* return power of two from operand, otherwise 0. */
320extern int vfp3_const_double_for_bits (rtx);
99aea943
AS		 321
322extern void arm_emit_coreregs_64bit_shift (enum rtx_code, rtx, rtx, rtx, rtx,
323 rtx);
39fa4aec 324extern bool arm_fusion_enabled_p (tune_params::fuse_ops);
6ce43645 325extern bool arm_valid_symbolic_address_p (rtx);
95ffee1f 326extern bool arm_validize_comparison (rtx *, rtx *, rtx *);
1b78f575
RE		 327#endif /* RTX_CODE */
328
ad421159 329extern bool arm_gen_setmem (rtx *);
b440f324
RH		 330extern void arm_expand_vec_perm (rtx target, rtx op0, rtx op1, rtx sel);
331extern bool arm_expand_vec_perm_const (rtx target, rtx op0, rtx op1, rtx sel);
332
ef4bddc2 333extern bool arm_autoinc_modes_ok_p (machine_mode, enum arm_auto_incmodes);
8875e939 334
34dd397b
SB		 335extern void arm_emit_eabi_attribute (const char *, int, int);
336
d5524d52 337extern void arm_reset_previous_fndecl (void);
eeb085f3 338extern void save_restore_target_globals (tree);
d5524d52 339
b848e289
JG		 340/* Defined in gcc/common/config/arm-common.c. */
341extern const char *arm_rewrite_selected_cpu (const char *name);
342
7049e4eb
CB		 343/* Defined in gcc/common/config/arm-c.c. */
344extern void arm_lang_object_attributes_init (void);
c84f825c 345extern void arm_register_target_pragmas (void);
7049e4eb
CB		 346extern void arm_cpu_cpp_builtins (struct cpp_reader *);
347
aed773a2
CB		 348extern bool arm_is_constant_pool_ref (rtx);
349
a27d8d80
JG		 350/* Flags used to identify the presence of processor capabilities. */
351
352/* Bit values used to identify processor capabilities. */
427388a4
MW		 353#define FL_NONE (0) /* No flags. */
354#define FL_ANY (0xffffffff) /* All flags. */
a27d8d80
JG		 355#define FL_CO_PROC (1 << 0) /* Has external co-processor bus */
356#define FL_ARCH3M (1 << 1) /* Extended multiply */
357#define FL_MODE26 (1 << 2) /* 26-bit mode support */
358#define FL_MODE32 (1 << 3) /* 32-bit mode support */
359#define FL_ARCH4 (1 << 4) /* Architecture rel 4 */
360#define FL_ARCH5 (1 << 5) /* Architecture rel 5 */
361#define FL_THUMB (1 << 6) /* Thumb aware */
362#define FL_LDSCHED (1 << 7) /* Load scheduling necessary */
363#define FL_STRONG (1 << 8) /* StrongARM */
364#define FL_ARCH5E (1 << 9) /* DSP extensions to v5 */
365#define FL_XSCALE (1 << 10) /* XScale */
366/* spare (1 << 11) */
367#define FL_ARCH6 (1 << 12) /* Architecture rel 6. Adds
368 media instructions. */
369#define FL_VFPV2 (1 << 13) /* Vector Floating Point V2. */
370#define FL_WBUF (1 << 14) /* Schedule for write buffer ops.
371 Note: ARM6 & 7 derivatives only. */
372#define FL_ARCH6K (1 << 15) /* Architecture rel 6 K extensions. */
373#define FL_THUMB2 (1 << 16) /* Thumb-2. */
374#define FL_NOTM (1 << 17) /* Instructions not present in the 'M'
375 profile. */
376#define FL_THUMB_DIV (1 << 18) /* Hardware divide (Thumb mode). */
377#define FL_VFPV3 (1 << 19) /* Vector Floating Point V3. */
378#define FL_NEON (1 << 20) /* Neon instructions. */
379#define FL_ARCH7EM (1 << 21) /* Instructions present in the ARMv7E-M
380 architecture. */
381#define FL_ARCH7 (1 << 22) /* Architecture 7. */
382#define FL_ARM_DIV (1 << 23) /* Hardware divide (ARM mode). */
383#define FL_ARCH8 (1 << 24) /* Architecture 8. */
384#define FL_CRC32 (1 << 25) /* ARMv8 CRC32 instructions. */
385
386#define FL_SMALLMUL (1 << 26) /* Small multiply supported. */
afe006ad 387#define FL_NO_VOLATILE_CE (1 << 27) /* No volatile memory in IT block. */
a27d8d80
JG		 388
389#define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */
390#define FL_IWMMXT2 (1 << 30) /* "Intel Wireless MMX2 technology". */
39c12541 391#define FL_ARCH6KZ (1 << 31) /* ARMv6KZ architecture. */
a27d8d80 392
252e03b5
MW		 393#define FL2_ARCH8_1 (1 << 0) /* Architecture 8.1. */
394
a27d8d80
JG		 395/* Flags that only effect tuning, not available instructions. */
396#define FL_TUNE (FL_WBUF | FL_VFPV2 | FL_STRONG | FL_LDSCHED \
397 | FL_CO_PROC)
398
399#define FL_FOR_ARCH2 FL_NOTM
400#define FL_FOR_ARCH3 (FL_FOR_ARCH2 | FL_MODE32)
401#define FL_FOR_ARCH3M (FL_FOR_ARCH3 | FL_ARCH3M)
402#define FL_FOR_ARCH4 (FL_FOR_ARCH3M | FL_ARCH4)
403#define FL_FOR_ARCH4T (FL_FOR_ARCH4 | FL_THUMB)
404#define FL_FOR_ARCH5 (FL_FOR_ARCH4 | FL_ARCH5)
405#define FL_FOR_ARCH5T (FL_FOR_ARCH5 | FL_THUMB)
406#define FL_FOR_ARCH5E (FL_FOR_ARCH5 | FL_ARCH5E)
407#define FL_FOR_ARCH5TE (FL_FOR_ARCH5E | FL_THUMB)
408#define FL_FOR_ARCH5TEJ FL_FOR_ARCH5TE
409#define FL_FOR_ARCH6 (FL_FOR_ARCH5TE | FL_ARCH6)
410#define FL_FOR_ARCH6J FL_FOR_ARCH6
411#define FL_FOR_ARCH6K (FL_FOR_ARCH6 | FL_ARCH6K)
412#define FL_FOR_ARCH6Z FL_FOR_ARCH6
39c12541 413#define FL_FOR_ARCH6KZ (FL_FOR_ARCH6K | FL_ARCH6KZ)
a27d8d80
JG		 414#define FL_FOR_ARCH6T2 (FL_FOR_ARCH6 | FL_THUMB2)
415#define FL_FOR_ARCH6M (FL_FOR_ARCH6 & ~FL_NOTM)
416#define FL_FOR_ARCH7 ((FL_FOR_ARCH6T2 & ~FL_NOTM) | FL_ARCH7)
417#define FL_FOR_ARCH7A (FL_FOR_ARCH7 | FL_NOTM | FL_ARCH6K)
418#define FL_FOR_ARCH7VE (FL_FOR_ARCH7A | FL_THUMB_DIV | FL_ARM_DIV)
419#define FL_FOR_ARCH7R (FL_FOR_ARCH7A | FL_THUMB_DIV)
420#define FL_FOR_ARCH7M (FL_FOR_ARCH7 | FL_THUMB_DIV)
421#define FL_FOR_ARCH7EM (FL_FOR_ARCH7M | FL_ARCH7EM)
422#define FL_FOR_ARCH8A (FL_FOR_ARCH7VE | FL_ARCH8)
252e03b5 423#define FL2_FOR_ARCH8_1A FL2_ARCH8_1
a27d8d80 424
427388a4
MW		 425/* There are too many feature bits to fit in a single word so the set of cpu and
426 fpu capabilities is a structure. A feature set is created and manipulated
427 with the ARM_FSET macros. */
428
429typedef struct
430{
431 unsigned long cpu[2];
432} arm_feature_set;
433
434
435/* Initialize a feature set. */
436
437#define ARM_FSET_MAKE(CPU1,CPU2) { { (CPU1), (CPU2) } }
438
439#define ARM_FSET_MAKE_CPU1(CPU1) ARM_FSET_MAKE ((CPU1), (FL_NONE))
440#define ARM_FSET_MAKE_CPU2(CPU2) ARM_FSET_MAKE ((FL_NONE), (CPU2))
441
442/* Accessors. */
443
444#define ARM_FSET_CPU1(S) ((S).cpu[0])
445#define ARM_FSET_CPU2(S) ((S).cpu[1])
446
447/* Useful combinations. */
448
449#define ARM_FSET_EMPTY ARM_FSET_MAKE (FL_NONE, FL_NONE)
450#define ARM_FSET_ANY ARM_FSET_MAKE (FL_ANY, FL_ANY)
451
452/* Tests for a specific CPU feature. */
453
454#define ARM_FSET_HAS_CPU1(A, F) \
455 (((A).cpu[0] & ((unsigned long)(F))) == ((unsigned long)(F)))
456#define ARM_FSET_HAS_CPU2(A, F) \
457 (((A).cpu[1] & ((unsigned long)(F))) == ((unsigned long)(F)))
458#define ARM_FSET_HAS_CPU(A, F1, F2) \
459 (ARM_FSET_HAS_CPU1 ((A), (F1)) && ARM_FSET_HAS_CPU2 ((A), (F2)))
460
461/* Add a feature to a feature set. */
462
463#define ARM_FSET_ADD_CPU1(DST, F) \
464 do { \
465 (DST).cpu[0] |= (F); \
466 } while (0)
467
468#define ARM_FSET_ADD_CPU2(DST, F) \
469 do { \
470 (DST).cpu[1] |= (F); \
471 } while (0)
472
473/* Remove a feature from a feature set. */
474
475#define ARM_FSET_DEL_CPU1(DST, F) \
476 do { \
477 (DST).cpu[0] &= ~(F); \
478 } while (0)
479
480#define ARM_FSET_DEL_CPU2(DST, F) \
481 do { \
482 (DST).cpu[1] &= ~(F); \
483 } while (0)
484
485/* Union of feature sets. */
486
487#define ARM_FSET_UNION(DST,F1,F2) \
488 do { \
489 (DST).cpu[0] = (F1).cpu[0] | (F2).cpu[0]; \
490 (DST).cpu[1] = (F1).cpu[1] | (F2).cpu[1]; \
491 } while (0)
492
493/* Intersection of feature sets. */
494
495#define ARM_FSET_INTER(DST,F1,F2) \
496 do { \
497 (DST).cpu[0] = (F1).cpu[0] & (F2).cpu[0]; \
498 (DST).cpu[1] = (F1).cpu[1] & (F2).cpu[1]; \
499 } while (0)
500
501/* Exclusive disjunction. */
502
503#define ARM_FSET_XOR(DST,F1,F2) \
504 do { \
505 (DST).cpu[0] = (F1).cpu[0] ^ (F2).cpu[0]; \
506 (DST).cpu[1] = (F1).cpu[1] ^ (F2).cpu[1]; \
507 } while (0)
508
509/* Difference of feature sets: F1 excluding the elements of F2. */
510
511#define ARM_FSET_EXCLUDE(DST,F1,F2) \
512 do { \
513 (DST).cpu[0] = (F1).cpu[0] & ~(F2).cpu[0]; \
514 (DST).cpu[1] = (F1).cpu[1] & ~(F2).cpu[1]; \
515 } while (0)
516
517/* Test for an empty feature set. */
518
519#define ARM_FSET_IS_EMPTY(A) \
520 (!((A).cpu[0]) && !((A).cpu[1]))
521
522/* Tests whether the cpu features of A are a subset of B. */
523
524#define ARM_FSET_CPU_SUBSET(A,B) \
525 ((((A).cpu[0] & (B).cpu[0]) == (A).cpu[0]) \
526 && (((A).cpu[1] & (B).cpu[1]) == (A).cpu[1]))
527
a27d8d80
JG		 528/* The bits in this mask specify which
529 instructions we are allowed to generate. */
a1c54ebf 530extern arm_feature_set insn_flags;
a27d8d80
JG		 531
532/* The bits in this mask specify which instruction scheduling options should
533 be used. */
a1c54ebf 534extern arm_feature_set tune_flags;
a27d8d80
JG		 535
536/* Nonzero if this chip supports the ARM Architecture 3M extensions. */
537extern int arm_arch3m;
538
539/* Nonzero if this chip supports the ARM Architecture 4 extensions. */
540extern int arm_arch4;
541
542/* Nonzero if this chip supports the ARM Architecture 4t extensions. */
543extern int arm_arch4t;
544
545/* Nonzero if this chip supports the ARM Architecture 5 extensions. */
546extern int arm_arch5;
547
548/* Nonzero if this chip supports the ARM Architecture 5E extensions. */
549extern int arm_arch5e;
550
551/* Nonzero if this chip supports the ARM Architecture 6 extensions. */
552extern int arm_arch6;
553
554/* Nonzero if this chip supports the ARM 6K extensions. */
555extern int arm_arch6k;
556
39c12541
MW		 557/* Nonzero if this chip supports the ARM 6KZ extensions. */
558extern int arm_arch6kz;
559
a27d8d80
JG		 560/* Nonzero if instructions present in ARMv6-M can be used. */
561extern int arm_arch6m;
562
563/* Nonzero if this chip supports the ARM 7 extensions. */
564extern int arm_arch7;
565
566/* Nonzero if instructions not present in the 'M' profile can be used. */
567extern int arm_arch_notm;
568
569/* Nonzero if instructions present in ARMv7E-M can be used. */
570extern int arm_arch7em;
571
572/* Nonzero if instructions present in ARMv8 can be used. */
573extern int arm_arch8;
574
575/* Nonzero if this chip can benefit from load scheduling. */
576extern int arm_ld_sched;
577
578/* Nonzero if this chip is a StrongARM. */
579extern int arm_tune_strongarm;
580
581/* Nonzero if this chip supports Intel Wireless MMX technology. */
582extern int arm_arch_iwmmxt;
583
584/* Nonzero if this chip supports Intel Wireless MMX2 technology. */
585extern int arm_arch_iwmmxt2;
586
587/* Nonzero if this chip is an XScale. */
588extern int arm_arch_xscale;
589
590/* Nonzero if tuning for XScale */
591extern int arm_tune_xscale;
592
593/* Nonzero if we want to tune for stores that access the write-buffer.
594 This typically means an ARM6 or ARM7 with MMU or MPU. */
595extern int arm_tune_wbuf;
596
597/* Nonzero if tuning for Cortex-A9. */
598extern int arm_tune_cortex_a9;
599
a27d8d80
JG		 600/* Nonzero if we should define __THUMB_INTERWORK__ in the
601 preprocessor.
602 XXX This is a bit of a hack, it's intended to help work around
603 problems in GLD which doesn't understand that armv5t code is
604 interworking clean. */
605extern int arm_cpp_interwork;
606
52545641
TP		 607/* Nonzero if chip supports Thumb 1. */
608extern int arm_arch_thumb1;
609
a27d8d80
JG		 610/* Nonzero if chip supports Thumb 2. */
611extern int arm_arch_thumb2;
612
613/* Nonzero if chip supports integer division instruction. */
614extern int arm_arch_arm_hwdiv;
615extern int arm_arch_thumb_hwdiv;
616
afe006ad
TG		 617/* Nonzero if chip disallows volatile memory access in IT block. */
618extern int arm_arch_no_volatile_ce;
619
a27d8d80
JG		 620/* Nonzero if we should use Neon to handle 64-bits operations rather
621 than core registers. */
622extern int prefer_neon_for_64bits;
623
624
625
88657302 626#endif /* ! GCC_ARM_PROTOS_H */
Mirror of https://gcc.gnu.org/git/gcc.git