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[Patch ARM Refactor Builtins 2/8] Move Processor flags to arm-protos.h
[thirdparty/gcc.git] / gcc / config / arm / arm-protos.h
CommitLineData
eb3921e8 1/* Prototypes for exported functions defined in arm.c and pe.c
23a5b65a 2 Copyright (C) 1999-2014 Free Software Foundation, Inc.
eb3921e8
NC		 3 Contributed by Richard Earnshaw (rearnsha@arm.com)
4 Minor hacks by Nick Clifton (nickc@cygnus.com)
5
4f448245 6 This file is part of GCC.
eb3921e8 7
4f448245
NC		 8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
2f83c7d6 10 the Free Software Foundation; either version 3, or (at your option)
4f448245 11 any later version.
eb3921e8 12
4f448245
NC		 13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
eb3921e8 17
4f448245 18 You should have received a copy of the GNU General Public License
2f83c7d6
NC		 19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
eb3921e8 21
8b97c5f8
ZW		 22#ifndef GCC_ARM_PROTOS_H
23#define GCC_ARM_PROTOS_H
24
677f3fa8 25extern enum unwind_info_type arm_except_unwind_info (struct gcc_options *);
a72d4945 26extern int use_return_insn (int, rtx);
24d5b097 27extern bool use_simple_return_p (void);
bbbbb16a 28extern enum reg_class arm_regno_class (int);
e55ef7f4 29extern void arm_load_pic_register (unsigned long);
e32bac5b 30extern int arm_volatile_func (void);
e32bac5b 31extern void arm_expand_prologue (void);
d461c88a 32extern void arm_expand_epilogue (bool);
24d5b097 33extern void thumb2_expand_return (bool);
e32bac5b
RE		 34extern const char *arm_strip_name_encoding (const char *);
35extern void arm_asm_output_labelref (FILE *, const char *);
5b3e6663 36extern void thumb2_asm_output_opcode (FILE *);
e32bac5b 37extern unsigned long arm_current_func_type (void);
b3f8d95d
MM		 38extern HOST_WIDE_INT arm_compute_initial_elimination_offset (unsigned int,
39 unsigned int);
5848830f
PB		 40extern HOST_WIDE_INT thumb_compute_initial_elimination_offset (unsigned int,
41 unsigned int);
2fa330b2 42extern unsigned int arm_dbx_register_number (unsigned int);
617a1b71
PB		 43extern void arm_output_fn_unwind (FILE *, bool);
44
eb3921e8 45
eb3921e8 46#ifdef RTX_CODE
ef4bddc2
RS		 47extern bool arm_vector_mode_supported_p (machine_mode);
48extern bool arm_small_register_classes_for_mode_p (machine_mode);
49extern int arm_hard_regno_mode_ok (unsigned int, machine_mode);
50extern bool arm_modes_tieable_p (machine_mode, machine_mode);
e32bac5b 51extern int const_ok_for_arm (HOST_WIDE_INT);
c2b640a7 52extern int const_ok_for_op (HOST_WIDE_INT, enum rtx_code);
44cd6810 53extern int const_ok_for_dimode_op (HOST_WIDE_INT, enum rtx_code);
ef4bddc2 54extern int arm_split_constant (RTX_CODE, machine_mode, rtx,
a406f566 55 HOST_WIDE_INT, rtx, rtx, int);
e32bac5b 56extern int legitimate_pic_operand_p (rtx);
ef4bddc2 57extern rtx legitimize_pic_address (rtx, machine_mode, rtx);
d3585b76 58extern rtx legitimize_tls_address (rtx, rtx);
ef4bddc2
RS		 59extern bool arm_legitimate_address_p (machine_mode, rtx, bool);
60extern int arm_legitimate_address_outer_p (machine_mode, rtx, RTX_CODE, int);
61extern int thumb_legitimate_offset_p (machine_mode, HOST_WIDE_INT);
62extern bool arm_legitimize_reload_address (rtx *, machine_mode, int, int,
0cd98787 63 int);
ef4bddc2 64extern rtx thumb_legitimize_reload_address (rtx *, machine_mode, int, int,
a132dad6 65 int);
ef4bddc2
RS		 66extern int thumb1_legitimate_address_p (machine_mode, rtx, int);
67extern bool ldm_stm_operation_p (rtx, bool, machine_mode mode,
fb40241d 68 bool, bool);
9b66ebb1 69extern int arm_const_double_rtx (rtx);
f1adb0a9 70extern int vfp3_const_double_rtx (rtx);
ef4bddc2
RS		 71extern int neon_immediate_valid_for_move (rtx, machine_mode, rtx *, int *);
72extern int neon_immediate_valid_for_logic (rtx, machine_mode, int, rtx *,
88f77cba 73 int *);
ef4bddc2 74extern int neon_immediate_valid_for_shift (rtx, machine_mode, rtx *,
31a0c825 75 int *, bool);
88f77cba 76extern char *neon_output_logic_immediate (const char *, rtx *,
ef4bddc2 77 machine_mode, int, int);
31a0c825 78extern char *neon_output_shift_immediate (const char *, char, rtx *,
ef4bddc2
RS		 79 machine_mode, int, bool);
80extern void neon_pairwise_reduce (rtx, rtx, machine_mode,
88f77cba 81 rtx (*) (rtx, rtx, rtx));
814a4c3b 82extern rtx neon_make_constant (rtx);
dfa3f8d0 83extern tree arm_builtin_vectorized_function (tree, tree, tree);
88f77cba 84extern void neon_expand_vector_init (rtx, rtx);
b617fc71
JB		 85extern void neon_lane_bounds (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
86extern void neon_const_bounds (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
ef4bddc2 87extern HOST_WIDE_INT neon_element_bits (machine_mode);
88f77cba 88extern void neon_reinterpret (rtx, rtx);
ef4bddc2 89extern void neon_emit_pair_result_insn (machine_mode,
88f77cba
JB		 90 rtx (*) (rtx, rtx, rtx, rtx),
91 rtx, rtx, rtx);
92extern void neon_disambiguate_copy (rtx *, rtx *, rtx *, unsigned int);
b440f324 93extern void neon_split_vcombine (rtx op[3]);
ef4bddc2 94extern enum reg_class coproc_secondary_reload_class (machine_mode, rtx,
fe2d934b 95 bool);
d3585b76 96extern bool arm_tls_referenced_p (rtx);
d5b7b3ae 97
fdd695fd 98extern int arm_coproc_mem_operand (rtx, bool);
33255ae3 99extern int neon_vector_mem_operand (rtx, int, bool);
88f77cba 100extern int neon_struct_mem_operand (rtx);
e32bac5b 101
d3585b76 102extern int tls_mentioned_p (rtx);
e32bac5b
RE		 103extern int symbol_mentioned_p (rtx);
104extern int label_mentioned_p (rtx);
105extern RTX_CODE minmax_code (rtx);
5d216c70 106extern bool arm_sat_operator_match (rtx, rtx, int *, bool *);
e32bac5b 107extern int adjacent_mem_locations (rtx, rtx);
37119410
BS		 108extern bool gen_ldm_seq (rtx *, int, bool);
109extern bool gen_stm_seq (rtx *, int);
110extern bool gen_const_stm_seq (rtx *, int);
111extern rtx arm_gen_load_multiple (int *, int, rtx, int, rtx, HOST_WIDE_INT *);
112extern rtx arm_gen_store_multiple (int *, int, rtx, int, rtx, HOST_WIDE_INT *);
56289ed2
SD		 113extern bool offset_ok_for_ldrd_strd (HOST_WIDE_INT);
114extern bool operands_ok_ldrd_strd (rtx, rtx, rtx, HOST_WIDE_INT, bool, bool);
4542a38a 115extern bool gen_operands_ldrd_strd (rtx *, bool, bool, bool);
70128ad9 116extern int arm_gen_movmemqi (rtx *);
798d3d04 117extern bool gen_movmem_ldrd_strd (rtx *);
ef4bddc2
RS		 118extern machine_mode arm_select_cc_mode (RTX_CODE, rtx, rtx);
119extern machine_mode arm_select_dominance_cc_mode (rtx, rtx,
e32bac5b 120 HOST_WIDE_INT);
18f0fe6b 121extern rtx arm_gen_compare_reg (RTX_CODE, rtx, rtx, rtx);
e32bac5b
RE		 122extern rtx arm_gen_return_addr_mask (void);
123extern void arm_reload_in_hi (rtx *);
124extern void arm_reload_out_hi (rtx *);
02231c13 125extern int arm_max_const_double_inline_cost (void);
2075b05d 126extern int arm_const_double_inline_cost (rtx);
b4a58f80 127extern bool arm_const_double_by_parts (rtx);
73160ba9 128extern bool arm_const_double_by_immediates (rtx);
7a32d6c4 129extern void arm_emit_call_insn (rtx, rtx, bool);
e32bac5b
RE		 130extern const char *output_call (rtx *);
131extern const char *output_call_mem (rtx *);
571191af 132void arm_emit_movpair (rtx, rtx);
e32bac5b 133extern const char *output_mov_long_double_arm_from_arm (rtx *);
3598da80 134extern const char *output_move_double (rtx *, bool, int *count);
88f77cba 135extern const char *output_move_quad (rtx *);
3598da80 136extern int arm_count_output_move_double_insns (rtx *);
5b3e6663 137extern const char *output_move_vfp (rtx *operands);
88f77cba 138extern const char *output_move_neon (rtx *operands);
647d790d
DM		 139extern int arm_attr_length_move_neon (rtx_insn *);
140extern int arm_address_offset_is_imm (rtx_insn *);
e32bac5b
RE		 141extern const char *output_add_immediate (rtx *);
142extern const char *arithmetic_instr (rtx, int);
143extern void output_ascii_pseudo_op (FILE *, const unsigned char *, int);
f79b86a4 144extern const char *output_return_instruction (rtx, bool, bool, bool);
e32bac5b 145extern void arm_poke_function_name (FILE *, const char *);
81e3f921 146extern void arm_final_prescan_insn (rtx_insn *);
e32bac5b 147extern int arm_debugger_arg_offset (int, rtx);
25a65198 148extern bool arm_is_long_call_p (tree);
5a9335ef 149extern int arm_emit_vector_const (FILE *, rtx);
0fd8c3ad 150extern void arm_emit_fp16_const (rtx c);
5a9335ef 151extern const char * arm_output_load_gr (rtx *);
b27832ed 152extern const char *vfp_output_vstmd (rtx *);
3aee1982 153extern void arm_output_multireg_pop (rtx *, bool, rtx, bool, bool);
c9ca9b88 154extern void arm_set_return_address (rtx, rtx);
6555b6bd 155extern int arm_eliminable_register (rtx);
5b3e6663 156extern const char *arm_output_shift(rtx *, int);
8fd03515
XQ		 157extern const char *arm_output_iwmmxt_shift_immediate (const char *, rtx *, bool);
158extern const char *arm_output_iwmmxt_tinsr (rtx *);
029e79eb 159extern unsigned int arm_sync_loop_insns (rtx , rtx *);
0c27e2d8 160extern int arm_attr_length_push_multi(rtx, rtx);
18f0fe6b
RH		 161extern void arm_expand_compare_and_swap (rtx op[]);
162extern void arm_split_compare_and_swap (rtx op[]);
163extern void arm_split_atomic_op (enum rtx_code, rtx, rtx, rtx, rtx, rtx, rtx);
f959607b 164extern rtx arm_load_tp (rtx);
d5b7b3ae
RE		 165
166#if defined TREE_CODE
e32bac5b 167extern void arm_init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, tree);
ef4bddc2
RS		 168extern bool arm_pad_arg_upward (machine_mode, const_tree);
169extern bool arm_pad_reg_upward (machine_mode, tree, int);
d5b7b3ae 170#endif
9f7bf991 171extern int arm_apply_result_size (void);
d5b7b3ae 172
eb3921e8
NC		 173#endif /* RTX_CODE */
174
d5b7b3ae 175/* Thumb functions. */
e32bac5b 176extern void arm_init_expanders (void);
90911ab6 177extern const char *thumb1_unexpanded_epilogue (void);
5b3e6663
PB		 178extern void thumb1_expand_prologue (void);
179extern void thumb1_expand_epilogue (void);
d018b46e 180extern const char *thumb1_output_interwork (void);
d5b7b3ae 181#ifdef TREE_CODE
e32bac5b 182extern int is_called_in_ARM_mode (tree);
d5b7b3ae 183#endif
e32bac5b 184extern int thumb_shiftable_const (unsigned HOST_WIDE_INT);
cd2b33d0 185#ifdef RTX_CODE
723d95fe 186extern enum arm_cond_code maybe_get_arm_condition_code (rtx);
81e3f921
DM		 187extern void thumb1_final_prescan_insn (rtx_insn *);
188extern void thumb2_final_prescan_insn (rtx_insn *);
e32bac5b
RE		 189extern const char *thumb_load_double_from_address (rtx *);
190extern const char *thumb_output_move_mem_multiple (int, rtx *);
b12a00f1 191extern const char *thumb_call_via_reg (rtx);
70128ad9 192extern void thumb_expand_movmemqi (rtx *);
e32bac5b
RE		 193extern rtx arm_return_addr (int, rtx);
194extern void thumb_reload_out_hi (rtx *);
195extern void thumb_reload_in_hi (rtx *);
c9ca9b88 196extern void thumb_set_return_address (rtx, rtx);
907dd0c7
RE		 197extern const char *thumb1_output_casesi (rtx *);
198extern const char *thumb2_output_casesi (rtx *);
d5b7b3ae
RE		 199#endif
200
201/* Defined in pe.c. */
e32bac5b
RE		 202extern int arm_dllexport_name_p (const char *);
203extern int arm_dllimport_name_p (const char *);
d5b7b3ae
RE		 204
205#ifdef TREE_CODE
e32bac5b
RE		 206extern void arm_pe_unique_section (tree, int);
207extern void arm_pe_encode_section_info (tree, rtx, int);
208extern int arm_dllexport_p (tree);
209extern int arm_dllimport_p (tree);
210extern void arm_mark_dllexport (tree);
211extern void arm_mark_dllimport (tree);
d5b7b3ae 212#endif
8b97c5f8 213
e32bac5b
RE		 214extern void arm_pr_long_calls (struct cpp_reader *);
215extern void arm_pr_no_long_calls (struct cpp_reader *);
216extern void arm_pr_long_calls_off (struct cpp_reader *);
8b97c5f8 217
b76c3c4b
PB		 218extern void arm_lang_object_attributes_init(void);
219
3101faab 220extern const char *arm_mangle_type (const_tree);
608063c3 221
795dc4fc
PB		 222extern void arm_order_regs_for_local_alloc (void);
223
b24a2ce5
GY		 224extern int arm_max_conditional_execute ();
225
2597da22
CL		 226/* Vectorizer cost model implementation. */
227struct cpu_vec_costs {
228 const int scalar_stmt_cost; /* Cost of any scalar operation, excluding
229 load and store. */
230 const int scalar_load_cost; /* Cost of scalar load. */
231 const int scalar_store_cost; /* Cost of scalar store. */
232 const int vec_stmt_cost; /* Cost of any vector operation, excluding
233 load, store, vector-to-scalar and
234 scalar-to-vector operation. */
235 const int vec_to_scalar_cost; /* Cost of vect-to-scalar operation. */
236 const int scalar_to_vec_cost; /* Cost of scalar-to-vector operation. */
237 const int vec_align_load_cost; /* Cost of aligned vector load. */
238 const int vec_unalign_load_cost; /* Cost of unaligned vector load. */
239 const int vec_unalign_store_cost; /* Cost of unaligned vector load. */
240 const int vec_store_cost; /* Cost of vector store. */
241 const int cond_taken_branch_cost; /* Cost of taken branch for vectorizer
242 cost model. */
243 const int cond_not_taken_branch_cost;/* Cost of not taken branch for
244 vectorizer cost model. */
245};
246
1b78f575
RE		 247#ifdef RTX_CODE
248/* This needs to be here because we need RTX_CODE and similar. */
249
5bea0c6c
KT		 250struct cpu_cost_table;
251
1b78f575
RE		 252struct tune_params
253{
254 bool (*rtx_costs) (rtx, RTX_CODE, RTX_CODE, int *, bool);
5bea0c6c 255 const struct cpu_cost_table *insn_extra_cost;
647d790d 256 bool (*sched_adjust_cost) (rtx_insn *, rtx, rtx_insn *, int *);
1b78f575 257 int constant_limit;
b24a2ce5 258 /* Maximum number of instructions to conditionalise. */
16868d84 259 int max_insns_skipped;
911de8a3
IB		 260 int num_prefetch_slots;
261 int l1_cache_size;
262 int l1_cache_line_size;
7ec70105 263 bool prefer_constant_pool;
153668ec 264 int (*branch_cost) (bool, bool);
ab3dfff7
SD		 265 /* Prefer STRD/LDRD instructions over PUSH/POP/LDM/STM. */
266 bool prefer_ldrd_strd;
a51fb17f
BC		 267 /* The preference for non short cirtcuit operation when optimizing for
268 performance. The first element covers Thumb state and the second one
269 is for ARM state. */
270 bool logical_op_non_short_circuit[2];
2597da22
CL		 271 /* Vectorizer costs. */
272 const struct cpu_vec_costs* vec_costs;
65074f54
CL		 273 /* Prefer Neon for 64-bit bitops. */
274 bool prefer_neon_for_64bits;
46fbb3eb
IB		 275 /* Prefer 32-bit encoding instead of flag-setting 16-bit encoding. */
276 bool disparage_flag_setting_t16_encodings;
277 /* Prefer 32-bit encoding instead of 16-bit encoding where subset of flags
278 would be set. */
279 bool disparage_partial_flag_setting_t16_encodings;
ad421159
BC		 280 /* Prefer to inline string operations like memset by using Neon. */
281 bool string_ops_prefer_neon;
282 /* Maximum number of instructions to inline calls to memset. */
283 int max_insns_inline_memset;
1b78f575
RE		 284};
285
286extern const struct tune_params *current_tune;
7f3d8f56 287extern int vfp3_const_double_for_fract_bits (rtx);
c75d51aa
RL		 288/* return power of two from operand, otherwise 0. */
289extern int vfp3_const_double_for_bits (rtx);
99aea943
AS		 290
291extern void arm_emit_coreregs_64bit_shift (enum rtx_code, rtx, rtx, rtx, rtx,
292 rtx);
95ffee1f 293extern bool arm_validize_comparison (rtx *, rtx *, rtx *);
1b78f575
RE		 294#endif /* RTX_CODE */
295
ad421159 296extern bool arm_gen_setmem (rtx *);
b440f324
RH		 297extern void arm_expand_vec_perm (rtx target, rtx op0, rtx op1, rtx sel);
298extern bool arm_expand_vec_perm_const (rtx target, rtx op0, rtx op1, rtx sel);
299
ef4bddc2 300extern bool arm_autoinc_modes_ok_p (machine_mode, enum arm_auto_incmodes);
8875e939 301
34dd397b
SB		 302extern void arm_emit_eabi_attribute (const char *, int, int);
303
b848e289
JG		 304/* Defined in gcc/common/config/arm-common.c. */
305extern const char *arm_rewrite_selected_cpu (const char *name);
306
aed773a2
CB		 307extern bool arm_is_constant_pool_ref (rtx);
308
a27d8d80
JG		 309/* Flags used to identify the presence of processor capabilities. */
310
311/* Bit values used to identify processor capabilities. */
312#define FL_CO_PROC (1 << 0) /* Has external co-processor bus */
313#define FL_ARCH3M (1 << 1) /* Extended multiply */
314#define FL_MODE26 (1 << 2) /* 26-bit mode support */
315#define FL_MODE32 (1 << 3) /* 32-bit mode support */
316#define FL_ARCH4 (1 << 4) /* Architecture rel 4 */
317#define FL_ARCH5 (1 << 5) /* Architecture rel 5 */
318#define FL_THUMB (1 << 6) /* Thumb aware */
319#define FL_LDSCHED (1 << 7) /* Load scheduling necessary */
320#define FL_STRONG (1 << 8) /* StrongARM */
321#define FL_ARCH5E (1 << 9) /* DSP extensions to v5 */
322#define FL_XSCALE (1 << 10) /* XScale */
323/* spare (1 << 11) */
324#define FL_ARCH6 (1 << 12) /* Architecture rel 6. Adds
325 media instructions. */
326#define FL_VFPV2 (1 << 13) /* Vector Floating Point V2. */
327#define FL_WBUF (1 << 14) /* Schedule for write buffer ops.
328 Note: ARM6 & 7 derivatives only. */
329#define FL_ARCH6K (1 << 15) /* Architecture rel 6 K extensions. */
330#define FL_THUMB2 (1 << 16) /* Thumb-2. */
331#define FL_NOTM (1 << 17) /* Instructions not present in the 'M'
332 profile. */
333#define FL_THUMB_DIV (1 << 18) /* Hardware divide (Thumb mode). */
334#define FL_VFPV3 (1 << 19) /* Vector Floating Point V3. */
335#define FL_NEON (1 << 20) /* Neon instructions. */
336#define FL_ARCH7EM (1 << 21) /* Instructions present in the ARMv7E-M
337 architecture. */
338#define FL_ARCH7 (1 << 22) /* Architecture 7. */
339#define FL_ARM_DIV (1 << 23) /* Hardware divide (ARM mode). */
340#define FL_ARCH8 (1 << 24) /* Architecture 8. */
341#define FL_CRC32 (1 << 25) /* ARMv8 CRC32 instructions. */
342
343#define FL_SMALLMUL (1 << 26) /* Small multiply supported. */
344
345#define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */
346#define FL_IWMMXT2 (1 << 30) /* "Intel Wireless MMX2 technology". */
347
348/* Flags that only effect tuning, not available instructions. */
349#define FL_TUNE (FL_WBUF | FL_VFPV2 | FL_STRONG | FL_LDSCHED \
350 | FL_CO_PROC)
351
352#define FL_FOR_ARCH2 FL_NOTM
353#define FL_FOR_ARCH3 (FL_FOR_ARCH2 | FL_MODE32)
354#define FL_FOR_ARCH3M (FL_FOR_ARCH3 | FL_ARCH3M)
355#define FL_FOR_ARCH4 (FL_FOR_ARCH3M | FL_ARCH4)
356#define FL_FOR_ARCH4T (FL_FOR_ARCH4 | FL_THUMB)
357#define FL_FOR_ARCH5 (FL_FOR_ARCH4 | FL_ARCH5)
358#define FL_FOR_ARCH5T (FL_FOR_ARCH5 | FL_THUMB)
359#define FL_FOR_ARCH5E (FL_FOR_ARCH5 | FL_ARCH5E)
360#define FL_FOR_ARCH5TE (FL_FOR_ARCH5E | FL_THUMB)
361#define FL_FOR_ARCH5TEJ FL_FOR_ARCH5TE
362#define FL_FOR_ARCH6 (FL_FOR_ARCH5TE | FL_ARCH6)
363#define FL_FOR_ARCH6J FL_FOR_ARCH6
364#define FL_FOR_ARCH6K (FL_FOR_ARCH6 | FL_ARCH6K)
365#define FL_FOR_ARCH6Z FL_FOR_ARCH6
366#define FL_FOR_ARCH6ZK FL_FOR_ARCH6K
367#define FL_FOR_ARCH6T2 (FL_FOR_ARCH6 | FL_THUMB2)
368#define FL_FOR_ARCH6M (FL_FOR_ARCH6 & ~FL_NOTM)
369#define FL_FOR_ARCH7 ((FL_FOR_ARCH6T2 & ~FL_NOTM) | FL_ARCH7)
370#define FL_FOR_ARCH7A (FL_FOR_ARCH7 | FL_NOTM | FL_ARCH6K)
371#define FL_FOR_ARCH7VE (FL_FOR_ARCH7A | FL_THUMB_DIV | FL_ARM_DIV)
372#define FL_FOR_ARCH7R (FL_FOR_ARCH7A | FL_THUMB_DIV)
373#define FL_FOR_ARCH7M (FL_FOR_ARCH7 | FL_THUMB_DIV)
374#define FL_FOR_ARCH7EM (FL_FOR_ARCH7M | FL_ARCH7EM)
375#define FL_FOR_ARCH8A (FL_FOR_ARCH7VE | FL_ARCH8)
376
377/* The bits in this mask specify which
378 instructions we are allowed to generate. */
379extern unsigned long insn_flags;
380
381/* The bits in this mask specify which instruction scheduling options should
382 be used. */
383extern unsigned long tune_flags;
384
385/* Nonzero if this chip supports the ARM Architecture 3M extensions. */
386extern int arm_arch3m;
387
388/* Nonzero if this chip supports the ARM Architecture 4 extensions. */
389extern int arm_arch4;
390
391/* Nonzero if this chip supports the ARM Architecture 4t extensions. */
392extern int arm_arch4t;
393
394/* Nonzero if this chip supports the ARM Architecture 5 extensions. */
395extern int arm_arch5;
396
397/* Nonzero if this chip supports the ARM Architecture 5E extensions. */
398extern int arm_arch5e;
399
400/* Nonzero if this chip supports the ARM Architecture 6 extensions. */
401extern int arm_arch6;
402
403/* Nonzero if this chip supports the ARM 6K extensions. */
404extern int arm_arch6k;
405
406/* Nonzero if instructions present in ARMv6-M can be used. */
407extern int arm_arch6m;
408
409/* Nonzero if this chip supports the ARM 7 extensions. */
410extern int arm_arch7;
411
412/* Nonzero if instructions not present in the 'M' profile can be used. */
413extern int arm_arch_notm;
414
415/* Nonzero if instructions present in ARMv7E-M can be used. */
416extern int arm_arch7em;
417
418/* Nonzero if instructions present in ARMv8 can be used. */
419extern int arm_arch8;
420
421/* Nonzero if this chip can benefit from load scheduling. */
422extern int arm_ld_sched;
423
424/* Nonzero if this chip is a StrongARM. */
425extern int arm_tune_strongarm;
426
427/* Nonzero if this chip supports Intel Wireless MMX technology. */
428extern int arm_arch_iwmmxt;
429
430/* Nonzero if this chip supports Intel Wireless MMX2 technology. */
431extern int arm_arch_iwmmxt2;
432
433/* Nonzero if this chip is an XScale. */
434extern int arm_arch_xscale;
435
436/* Nonzero if tuning for XScale */
437extern int arm_tune_xscale;
438
439/* Nonzero if we want to tune for stores that access the write-buffer.
440 This typically means an ARM6 or ARM7 with MMU or MPU. */
441extern int arm_tune_wbuf;
442
443/* Nonzero if tuning for Cortex-A9. */
444extern int arm_tune_cortex_a9;
445
446/* Nonzero if generating Thumb instructions. */
447extern int thumb_code;
448
449/* Nonzero if generating Thumb-1 instructions. */
450extern int thumb1_code;
451
452/* Nonzero if we should define __THUMB_INTERWORK__ in the
453 preprocessor.
454 XXX This is a bit of a hack, it's intended to help work around
455 problems in GLD which doesn't understand that armv5t code is
456 interworking clean. */
457extern int arm_cpp_interwork;
458
459/* Nonzero if chip supports Thumb 2. */
460extern int arm_arch_thumb2;
461
462/* Nonzero if chip supports integer division instruction. */
463extern int arm_arch_arm_hwdiv;
464extern int arm_arch_thumb_hwdiv;
465
466/* Nonzero if we should use Neon to handle 64-bits operations rather
467 than core registers. */
468extern int prefer_neon_for_64bits;
469
470
471
88657302 472#endif /* ! GCC_ARM_PROTOS_H */
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