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[Patch ARM Refactor Builtins 6/8] Add some tests for "poly" mangling
[thirdparty/gcc.git] / gcc / config / arm / arm-protos.h
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eb3921e8 1/* Prototypes for exported functions defined in arm.c and pe.c
23a5b65a 2 Copyright (C) 1999-2014 Free Software Foundation, Inc.
eb3921e8
NC		 3 Contributed by Richard Earnshaw (rearnsha@arm.com)
4 Minor hacks by Nick Clifton (nickc@cygnus.com)
5
4f448245 6 This file is part of GCC.
eb3921e8 7
4f448245
NC		 8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
2f83c7d6 10 the Free Software Foundation; either version 3, or (at your option)
4f448245 11 any later version.
eb3921e8 12
4f448245
NC		 13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
eb3921e8 17
4f448245 18 You should have received a copy of the GNU General Public License
2f83c7d6
NC		 19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
eb3921e8 21
8b97c5f8
ZW		 22#ifndef GCC_ARM_PROTOS_H
23#define GCC_ARM_PROTOS_H
24
677f3fa8 25extern enum unwind_info_type arm_except_unwind_info (struct gcc_options *);
a72d4945 26extern int use_return_insn (int, rtx);
24d5b097 27extern bool use_simple_return_p (void);
bbbbb16a 28extern enum reg_class arm_regno_class (int);
e55ef7f4 29extern void arm_load_pic_register (unsigned long);
e32bac5b 30extern int arm_volatile_func (void);
e32bac5b 31extern void arm_expand_prologue (void);
d461c88a 32extern void arm_expand_epilogue (bool);
24d5b097 33extern void thumb2_expand_return (bool);
e32bac5b
RE		 34extern const char *arm_strip_name_encoding (const char *);
35extern void arm_asm_output_labelref (FILE *, const char *);
5b3e6663 36extern void thumb2_asm_output_opcode (FILE *);
e32bac5b 37extern unsigned long arm_current_func_type (void);
b3f8d95d
MM		 38extern HOST_WIDE_INT arm_compute_initial_elimination_offset (unsigned int,
39 unsigned int);
5848830f
PB		 40extern HOST_WIDE_INT thumb_compute_initial_elimination_offset (unsigned int,
41 unsigned int);
2fa330b2 42extern unsigned int arm_dbx_register_number (unsigned int);
617a1b71 43extern void arm_output_fn_unwind (FILE *, bool);
33857df2
JG		 44
45extern rtx arm_expand_builtin (tree exp, rtx target, rtx subtarget
46 ATTRIBUTE_UNUSED, enum machine_mode mode
47 ATTRIBUTE_UNUSED, int ignore ATTRIBUTE_UNUSED);
48extern tree arm_builtin_decl (unsigned code, bool initialize_p
49 ATTRIBUTE_UNUSED);
50extern void arm_init_builtins (void);
51extern void arm_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update);
eb3921e8 52
eb3921e8 53#ifdef RTX_CODE
ef4bddc2
RS		 54extern bool arm_vector_mode_supported_p (machine_mode);
55extern bool arm_small_register_classes_for_mode_p (machine_mode);
56extern int arm_hard_regno_mode_ok (unsigned int, machine_mode);
57extern bool arm_modes_tieable_p (machine_mode, machine_mode);
e32bac5b 58extern int const_ok_for_arm (HOST_WIDE_INT);
c2b640a7 59extern int const_ok_for_op (HOST_WIDE_INT, enum rtx_code);
44cd6810 60extern int const_ok_for_dimode_op (HOST_WIDE_INT, enum rtx_code);
ef4bddc2 61extern int arm_split_constant (RTX_CODE, machine_mode, rtx,
a406f566 62 HOST_WIDE_INT, rtx, rtx, int);
e32bac5b 63extern int legitimate_pic_operand_p (rtx);
ef4bddc2 64extern rtx legitimize_pic_address (rtx, machine_mode, rtx);
d3585b76 65extern rtx legitimize_tls_address (rtx, rtx);
ef4bddc2
RS		 66extern bool arm_legitimate_address_p (machine_mode, rtx, bool);
67extern int arm_legitimate_address_outer_p (machine_mode, rtx, RTX_CODE, int);
68extern int thumb_legitimate_offset_p (machine_mode, HOST_WIDE_INT);
69extern bool arm_legitimize_reload_address (rtx *, machine_mode, int, int,
0cd98787 70 int);
ef4bddc2 71extern rtx thumb_legitimize_reload_address (rtx *, machine_mode, int, int,
a132dad6 72 int);
ef4bddc2
RS		 73extern int thumb1_legitimate_address_p (machine_mode, rtx, int);
74extern bool ldm_stm_operation_p (rtx, bool, machine_mode mode,
fb40241d 75 bool, bool);
9b66ebb1 76extern int arm_const_double_rtx (rtx);
f1adb0a9 77extern int vfp3_const_double_rtx (rtx);
ef4bddc2
RS		 78extern int neon_immediate_valid_for_move (rtx, machine_mode, rtx *, int *);
79extern int neon_immediate_valid_for_logic (rtx, machine_mode, int, rtx *,
88f77cba 80 int *);
ef4bddc2 81extern int neon_immediate_valid_for_shift (rtx, machine_mode, rtx *,
31a0c825 82 int *, bool);
88f77cba 83extern char *neon_output_logic_immediate (const char *, rtx *,
ef4bddc2 84 machine_mode, int, int);
31a0c825 85extern char *neon_output_shift_immediate (const char *, char, rtx *,
ef4bddc2
RS		 86 machine_mode, int, bool);
87extern void neon_pairwise_reduce (rtx, rtx, machine_mode,
88f77cba 88 rtx (*) (rtx, rtx, rtx));
814a4c3b 89extern rtx neon_make_constant (rtx);
dfa3f8d0 90extern tree arm_builtin_vectorized_function (tree, tree, tree);
88f77cba 91extern void neon_expand_vector_init (rtx, rtx);
b617fc71
JB		 92extern void neon_lane_bounds (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
93extern void neon_const_bounds (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
ef4bddc2 94extern HOST_WIDE_INT neon_element_bits (machine_mode);
88f77cba 95extern void neon_reinterpret (rtx, rtx);
ef4bddc2 96extern void neon_emit_pair_result_insn (machine_mode,
88f77cba
JB		 97 rtx (*) (rtx, rtx, rtx, rtx),
98 rtx, rtx, rtx);
99extern void neon_disambiguate_copy (rtx *, rtx *, rtx *, unsigned int);
b440f324 100extern void neon_split_vcombine (rtx op[3]);
ef4bddc2 101extern enum reg_class coproc_secondary_reload_class (machine_mode, rtx,
fe2d934b 102 bool);
d3585b76 103extern bool arm_tls_referenced_p (rtx);
d5b7b3ae 104
fdd695fd 105extern int arm_coproc_mem_operand (rtx, bool);
33255ae3 106extern int neon_vector_mem_operand (rtx, int, bool);
88f77cba 107extern int neon_struct_mem_operand (rtx);
e32bac5b 108
d3585b76 109extern int tls_mentioned_p (rtx);
e32bac5b
RE		 110extern int symbol_mentioned_p (rtx);
111extern int label_mentioned_p (rtx);
112extern RTX_CODE minmax_code (rtx);
5d216c70 113extern bool arm_sat_operator_match (rtx, rtx, int *, bool *);
e32bac5b 114extern int adjacent_mem_locations (rtx, rtx);
37119410
BS		 115extern bool gen_ldm_seq (rtx *, int, bool);
116extern bool gen_stm_seq (rtx *, int);
117extern bool gen_const_stm_seq (rtx *, int);
118extern rtx arm_gen_load_multiple (int *, int, rtx, int, rtx, HOST_WIDE_INT *);
119extern rtx arm_gen_store_multiple (int *, int, rtx, int, rtx, HOST_WIDE_INT *);
56289ed2
SD		 120extern bool offset_ok_for_ldrd_strd (HOST_WIDE_INT);
121extern bool operands_ok_ldrd_strd (rtx, rtx, rtx, HOST_WIDE_INT, bool, bool);
4542a38a 122extern bool gen_operands_ldrd_strd (rtx *, bool, bool, bool);
70128ad9 123extern int arm_gen_movmemqi (rtx *);
798d3d04 124extern bool gen_movmem_ldrd_strd (rtx *);
ef4bddc2
RS		 125extern machine_mode arm_select_cc_mode (RTX_CODE, rtx, rtx);
126extern machine_mode arm_select_dominance_cc_mode (rtx, rtx,
e32bac5b 127 HOST_WIDE_INT);
18f0fe6b 128extern rtx arm_gen_compare_reg (RTX_CODE, rtx, rtx, rtx);
e32bac5b
RE		 129extern rtx arm_gen_return_addr_mask (void);
130extern void arm_reload_in_hi (rtx *);
131extern void arm_reload_out_hi (rtx *);
02231c13 132extern int arm_max_const_double_inline_cost (void);
2075b05d 133extern int arm_const_double_inline_cost (rtx);
b4a58f80 134extern bool arm_const_double_by_parts (rtx);
73160ba9 135extern bool arm_const_double_by_immediates (rtx);
7a32d6c4 136extern void arm_emit_call_insn (rtx, rtx, bool);
e32bac5b
RE		 137extern const char *output_call (rtx *);
138extern const char *output_call_mem (rtx *);
571191af 139void arm_emit_movpair (rtx, rtx);
e32bac5b 140extern const char *output_mov_long_double_arm_from_arm (rtx *);
3598da80 141extern const char *output_move_double (rtx *, bool, int *count);
88f77cba 142extern const char *output_move_quad (rtx *);
3598da80 143extern int arm_count_output_move_double_insns (rtx *);
5b3e6663 144extern const char *output_move_vfp (rtx *operands);
88f77cba 145extern const char *output_move_neon (rtx *operands);
647d790d
DM		 146extern int arm_attr_length_move_neon (rtx_insn *);
147extern int arm_address_offset_is_imm (rtx_insn *);
e32bac5b
RE		 148extern const char *output_add_immediate (rtx *);
149extern const char *arithmetic_instr (rtx, int);
150extern void output_ascii_pseudo_op (FILE *, const unsigned char *, int);
f79b86a4 151extern const char *output_return_instruction (rtx, bool, bool, bool);
e32bac5b 152extern void arm_poke_function_name (FILE *, const char *);
81e3f921 153extern void arm_final_prescan_insn (rtx_insn *);
e32bac5b 154extern int arm_debugger_arg_offset (int, rtx);
25a65198 155extern bool arm_is_long_call_p (tree);
5a9335ef 156extern int arm_emit_vector_const (FILE *, rtx);
0fd8c3ad 157extern void arm_emit_fp16_const (rtx c);
5a9335ef 158extern const char * arm_output_load_gr (rtx *);
b27832ed 159extern const char *vfp_output_vstmd (rtx *);
3aee1982 160extern void arm_output_multireg_pop (rtx *, bool, rtx, bool, bool);
c9ca9b88 161extern void arm_set_return_address (rtx, rtx);
6555b6bd 162extern int arm_eliminable_register (rtx);
5b3e6663 163extern const char *arm_output_shift(rtx *, int);
8fd03515
XQ		 164extern const char *arm_output_iwmmxt_shift_immediate (const char *, rtx *, bool);
165extern const char *arm_output_iwmmxt_tinsr (rtx *);
029e79eb 166extern unsigned int arm_sync_loop_insns (rtx , rtx *);
0c27e2d8 167extern int arm_attr_length_push_multi(rtx, rtx);
18f0fe6b
RH		 168extern void arm_expand_compare_and_swap (rtx op[]);
169extern void arm_split_compare_and_swap (rtx op[]);
170extern void arm_split_atomic_op (enum rtx_code, rtx, rtx, rtx, rtx, rtx, rtx);
f959607b 171extern rtx arm_load_tp (rtx);
d5b7b3ae
RE		 172
173#if defined TREE_CODE
e32bac5b 174extern void arm_init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, tree);
ef4bddc2
RS		 175extern bool arm_pad_arg_upward (machine_mode, const_tree);
176extern bool arm_pad_reg_upward (machine_mode, tree, int);
d5b7b3ae 177#endif
9f7bf991 178extern int arm_apply_result_size (void);
d5b7b3ae 179
eb3921e8
NC		 180#endif /* RTX_CODE */
181
d5b7b3ae 182/* Thumb functions. */
e32bac5b 183extern void arm_init_expanders (void);
90911ab6 184extern const char *thumb1_unexpanded_epilogue (void);
5b3e6663
PB		 185extern void thumb1_expand_prologue (void);
186extern void thumb1_expand_epilogue (void);
d018b46e 187extern const char *thumb1_output_interwork (void);
d5b7b3ae 188#ifdef TREE_CODE
e32bac5b 189extern int is_called_in_ARM_mode (tree);
d5b7b3ae 190#endif
e32bac5b 191extern int thumb_shiftable_const (unsigned HOST_WIDE_INT);
cd2b33d0 192#ifdef RTX_CODE
723d95fe 193extern enum arm_cond_code maybe_get_arm_condition_code (rtx);
81e3f921
DM		 194extern void thumb1_final_prescan_insn (rtx_insn *);
195extern void thumb2_final_prescan_insn (rtx_insn *);
e32bac5b
RE		 196extern const char *thumb_load_double_from_address (rtx *);
197extern const char *thumb_output_move_mem_multiple (int, rtx *);
b12a00f1 198extern const char *thumb_call_via_reg (rtx);
70128ad9 199extern void thumb_expand_movmemqi (rtx *);
e32bac5b
RE		 200extern rtx arm_return_addr (int, rtx);
201extern void thumb_reload_out_hi (rtx *);
202extern void thumb_reload_in_hi (rtx *);
c9ca9b88 203extern void thumb_set_return_address (rtx, rtx);
907dd0c7
RE		 204extern const char *thumb1_output_casesi (rtx *);
205extern const char *thumb2_output_casesi (rtx *);
d5b7b3ae
RE		 206#endif
207
208/* Defined in pe.c. */
e32bac5b
RE		 209extern int arm_dllexport_name_p (const char *);
210extern int arm_dllimport_name_p (const char *);
d5b7b3ae
RE		 211
212#ifdef TREE_CODE
e32bac5b
RE		 213extern void arm_pe_unique_section (tree, int);
214extern void arm_pe_encode_section_info (tree, rtx, int);
215extern int arm_dllexport_p (tree);
216extern int arm_dllimport_p (tree);
217extern void arm_mark_dllexport (tree);
218extern void arm_mark_dllimport (tree);
d5b7b3ae 219#endif
8b97c5f8 220
e32bac5b
RE		 221extern void arm_pr_long_calls (struct cpp_reader *);
222extern void arm_pr_no_long_calls (struct cpp_reader *);
223extern void arm_pr_long_calls_off (struct cpp_reader *);
8b97c5f8 224
b76c3c4b
PB		 225extern void arm_lang_object_attributes_init(void);
226
3101faab 227extern const char *arm_mangle_type (const_tree);
608063c3 228
795dc4fc
PB		 229extern void arm_order_regs_for_local_alloc (void);
230
b24a2ce5
GY		 231extern int arm_max_conditional_execute ();
232
2597da22
CL		 233/* Vectorizer cost model implementation. */
234struct cpu_vec_costs {
235 const int scalar_stmt_cost; /* Cost of any scalar operation, excluding
236 load and store. */
237 const int scalar_load_cost; /* Cost of scalar load. */
238 const int scalar_store_cost; /* Cost of scalar store. */
239 const int vec_stmt_cost; /* Cost of any vector operation, excluding
240 load, store, vector-to-scalar and
241 scalar-to-vector operation. */
242 const int vec_to_scalar_cost; /* Cost of vect-to-scalar operation. */
243 const int scalar_to_vec_cost; /* Cost of scalar-to-vector operation. */
244 const int vec_align_load_cost; /* Cost of aligned vector load. */
245 const int vec_unalign_load_cost; /* Cost of unaligned vector load. */
246 const int vec_unalign_store_cost; /* Cost of unaligned vector load. */
247 const int vec_store_cost; /* Cost of vector store. */
248 const int cond_taken_branch_cost; /* Cost of taken branch for vectorizer
249 cost model. */
250 const int cond_not_taken_branch_cost;/* Cost of not taken branch for
251 vectorizer cost model. */
252};
253
1b78f575
RE		 254#ifdef RTX_CODE
255/* This needs to be here because we need RTX_CODE and similar. */
256
5bea0c6c
KT		 257struct cpu_cost_table;
258
1b78f575
RE		 259struct tune_params
260{
261 bool (*rtx_costs) (rtx, RTX_CODE, RTX_CODE, int *, bool);
5bea0c6c 262 const struct cpu_cost_table *insn_extra_cost;
647d790d 263 bool (*sched_adjust_cost) (rtx_insn *, rtx, rtx_insn *, int *);
1b78f575 264 int constant_limit;
b24a2ce5 265 /* Maximum number of instructions to conditionalise. */
16868d84 266 int max_insns_skipped;
911de8a3
IB		 267 int num_prefetch_slots;
268 int l1_cache_size;
269 int l1_cache_line_size;
7ec70105 270 bool prefer_constant_pool;
153668ec 271 int (*branch_cost) (bool, bool);
ab3dfff7
SD		 272 /* Prefer STRD/LDRD instructions over PUSH/POP/LDM/STM. */
273 bool prefer_ldrd_strd;
a51fb17f
BC		 274 /* The preference for non short cirtcuit operation when optimizing for
275 performance. The first element covers Thumb state and the second one
276 is for ARM state. */
277 bool logical_op_non_short_circuit[2];
2597da22
CL		 278 /* Vectorizer costs. */
279 const struct cpu_vec_costs* vec_costs;
65074f54
CL		 280 /* Prefer Neon for 64-bit bitops. */
281 bool prefer_neon_for_64bits;
46fbb3eb
IB		 282 /* Prefer 32-bit encoding instead of flag-setting 16-bit encoding. */
283 bool disparage_flag_setting_t16_encodings;
284 /* Prefer 32-bit encoding instead of 16-bit encoding where subset of flags
285 would be set. */
286 bool disparage_partial_flag_setting_t16_encodings;
ad421159
BC		 287 /* Prefer to inline string operations like memset by using Neon. */
288 bool string_ops_prefer_neon;
289 /* Maximum number of instructions to inline calls to memset. */
290 int max_insns_inline_memset;
1b78f575
RE		 291};
292
293extern const struct tune_params *current_tune;
7f3d8f56 294extern int vfp3_const_double_for_fract_bits (rtx);
c75d51aa
RL		 295/* return power of two from operand, otherwise 0. */
296extern int vfp3_const_double_for_bits (rtx);
99aea943
AS		 297
298extern void arm_emit_coreregs_64bit_shift (enum rtx_code, rtx, rtx, rtx, rtx,
299 rtx);
95ffee1f 300extern bool arm_validize_comparison (rtx *, rtx *, rtx *);
1b78f575
RE		 301#endif /* RTX_CODE */
302
ad421159 303extern bool arm_gen_setmem (rtx *);
b440f324
RH		 304extern void arm_expand_vec_perm (rtx target, rtx op0, rtx op1, rtx sel);
305extern bool arm_expand_vec_perm_const (rtx target, rtx op0, rtx op1, rtx sel);
306
ef4bddc2 307extern bool arm_autoinc_modes_ok_p (machine_mode, enum arm_auto_incmodes);
8875e939 308
34dd397b
SB		 309extern void arm_emit_eabi_attribute (const char *, int, int);
310
b848e289
JG		 311/* Defined in gcc/common/config/arm-common.c. */
312extern const char *arm_rewrite_selected_cpu (const char *name);
313
aed773a2
CB		 314extern bool arm_is_constant_pool_ref (rtx);
315
a27d8d80
JG		 316/* Flags used to identify the presence of processor capabilities. */
317
318/* Bit values used to identify processor capabilities. */
319#define FL_CO_PROC (1 << 0) /* Has external co-processor bus */
320#define FL_ARCH3M (1 << 1) /* Extended multiply */
321#define FL_MODE26 (1 << 2) /* 26-bit mode support */
322#define FL_MODE32 (1 << 3) /* 32-bit mode support */
323#define FL_ARCH4 (1 << 4) /* Architecture rel 4 */
324#define FL_ARCH5 (1 << 5) /* Architecture rel 5 */
325#define FL_THUMB (1 << 6) /* Thumb aware */
326#define FL_LDSCHED (1 << 7) /* Load scheduling necessary */
327#define FL_STRONG (1 << 8) /* StrongARM */
328#define FL_ARCH5E (1 << 9) /* DSP extensions to v5 */
329#define FL_XSCALE (1 << 10) /* XScale */
330/* spare (1 << 11) */
331#define FL_ARCH6 (1 << 12) /* Architecture rel 6. Adds
332 media instructions. */
333#define FL_VFPV2 (1 << 13) /* Vector Floating Point V2. */
334#define FL_WBUF (1 << 14) /* Schedule for write buffer ops.
335 Note: ARM6 & 7 derivatives only. */
336#define FL_ARCH6K (1 << 15) /* Architecture rel 6 K extensions. */
337#define FL_THUMB2 (1 << 16) /* Thumb-2. */
338#define FL_NOTM (1 << 17) /* Instructions not present in the 'M'
339 profile. */
340#define FL_THUMB_DIV (1 << 18) /* Hardware divide (Thumb mode). */
341#define FL_VFPV3 (1 << 19) /* Vector Floating Point V3. */
342#define FL_NEON (1 << 20) /* Neon instructions. */
343#define FL_ARCH7EM (1 << 21) /* Instructions present in the ARMv7E-M
344 architecture. */
345#define FL_ARCH7 (1 << 22) /* Architecture 7. */
346#define FL_ARM_DIV (1 << 23) /* Hardware divide (ARM mode). */
347#define FL_ARCH8 (1 << 24) /* Architecture 8. */
348#define FL_CRC32 (1 << 25) /* ARMv8 CRC32 instructions. */
349
350#define FL_SMALLMUL (1 << 26) /* Small multiply supported. */
351
352#define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */
353#define FL_IWMMXT2 (1 << 30) /* "Intel Wireless MMX2 technology". */
354
355/* Flags that only effect tuning, not available instructions. */
356#define FL_TUNE (FL_WBUF | FL_VFPV2 | FL_STRONG | FL_LDSCHED \
357 | FL_CO_PROC)
358
359#define FL_FOR_ARCH2 FL_NOTM
360#define FL_FOR_ARCH3 (FL_FOR_ARCH2 | FL_MODE32)
361#define FL_FOR_ARCH3M (FL_FOR_ARCH3 | FL_ARCH3M)
362#define FL_FOR_ARCH4 (FL_FOR_ARCH3M | FL_ARCH4)
363#define FL_FOR_ARCH4T (FL_FOR_ARCH4 | FL_THUMB)
364#define FL_FOR_ARCH5 (FL_FOR_ARCH4 | FL_ARCH5)
365#define FL_FOR_ARCH5T (FL_FOR_ARCH5 | FL_THUMB)
366#define FL_FOR_ARCH5E (FL_FOR_ARCH5 | FL_ARCH5E)
367#define FL_FOR_ARCH5TE (FL_FOR_ARCH5E | FL_THUMB)
368#define FL_FOR_ARCH5TEJ FL_FOR_ARCH5TE
369#define FL_FOR_ARCH6 (FL_FOR_ARCH5TE | FL_ARCH6)
370#define FL_FOR_ARCH6J FL_FOR_ARCH6
371#define FL_FOR_ARCH6K (FL_FOR_ARCH6 | FL_ARCH6K)
372#define FL_FOR_ARCH6Z FL_FOR_ARCH6
373#define FL_FOR_ARCH6ZK FL_FOR_ARCH6K
374#define FL_FOR_ARCH6T2 (FL_FOR_ARCH6 | FL_THUMB2)
375#define FL_FOR_ARCH6M (FL_FOR_ARCH6 & ~FL_NOTM)
376#define FL_FOR_ARCH7 ((FL_FOR_ARCH6T2 & ~FL_NOTM) | FL_ARCH7)
377#define FL_FOR_ARCH7A (FL_FOR_ARCH7 | FL_NOTM | FL_ARCH6K)
378#define FL_FOR_ARCH7VE (FL_FOR_ARCH7A | FL_THUMB_DIV | FL_ARM_DIV)
379#define FL_FOR_ARCH7R (FL_FOR_ARCH7A | FL_THUMB_DIV)
380#define FL_FOR_ARCH7M (FL_FOR_ARCH7 | FL_THUMB_DIV)
381#define FL_FOR_ARCH7EM (FL_FOR_ARCH7M | FL_ARCH7EM)
382#define FL_FOR_ARCH8A (FL_FOR_ARCH7VE | FL_ARCH8)
383
384/* The bits in this mask specify which
385 instructions we are allowed to generate. */
386extern unsigned long insn_flags;
387
388/* The bits in this mask specify which instruction scheduling options should
389 be used. */
390extern unsigned long tune_flags;
391
392/* Nonzero if this chip supports the ARM Architecture 3M extensions. */
393extern int arm_arch3m;
394
395/* Nonzero if this chip supports the ARM Architecture 4 extensions. */
396extern int arm_arch4;
397
398/* Nonzero if this chip supports the ARM Architecture 4t extensions. */
399extern int arm_arch4t;
400
401/* Nonzero if this chip supports the ARM Architecture 5 extensions. */
402extern int arm_arch5;
403
404/* Nonzero if this chip supports the ARM Architecture 5E extensions. */
405extern int arm_arch5e;
406
407/* Nonzero if this chip supports the ARM Architecture 6 extensions. */
408extern int arm_arch6;
409
410/* Nonzero if this chip supports the ARM 6K extensions. */
411extern int arm_arch6k;
412
413/* Nonzero if instructions present in ARMv6-M can be used. */
414extern int arm_arch6m;
415
416/* Nonzero if this chip supports the ARM 7 extensions. */
417extern int arm_arch7;
418
419/* Nonzero if instructions not present in the 'M' profile can be used. */
420extern int arm_arch_notm;
421
422/* Nonzero if instructions present in ARMv7E-M can be used. */
423extern int arm_arch7em;
424
425/* Nonzero if instructions present in ARMv8 can be used. */
426extern int arm_arch8;
427
428/* Nonzero if this chip can benefit from load scheduling. */
429extern int arm_ld_sched;
430
431/* Nonzero if this chip is a StrongARM. */
432extern int arm_tune_strongarm;
433
434/* Nonzero if this chip supports Intel Wireless MMX technology. */
435extern int arm_arch_iwmmxt;
436
437/* Nonzero if this chip supports Intel Wireless MMX2 technology. */
438extern int arm_arch_iwmmxt2;
439
440/* Nonzero if this chip is an XScale. */
441extern int arm_arch_xscale;
442
443/* Nonzero if tuning for XScale */
444extern int arm_tune_xscale;
445
446/* Nonzero if we want to tune for stores that access the write-buffer.
447 This typically means an ARM6 or ARM7 with MMU or MPU. */
448extern int arm_tune_wbuf;
449
450/* Nonzero if tuning for Cortex-A9. */
451extern int arm_tune_cortex_a9;
452
453/* Nonzero if generating Thumb instructions. */
454extern int thumb_code;
455
456/* Nonzero if generating Thumb-1 instructions. */
457extern int thumb1_code;
458
459/* Nonzero if we should define __THUMB_INTERWORK__ in the
460 preprocessor.
461 XXX This is a bit of a hack, it's intended to help work around
462 problems in GLD which doesn't understand that armv5t code is
463 interworking clean. */
464extern int arm_cpp_interwork;
465
466/* Nonzero if chip supports Thumb 2. */
467extern int arm_arch_thumb2;
468
469/* Nonzero if chip supports integer division instruction. */
470extern int arm_arch_arm_hwdiv;
471extern int arm_arch_thumb_hwdiv;
472
473/* Nonzero if we should use Neon to handle 64-bits operations rather
474 than core registers. */
475extern int prefer_neon_for_64bits;
476
477
478
88657302 479#endif /* ! GCC_ARM_PROTOS_H */
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