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[thirdparty/gcc.git] / gcc / config / arm / arm-protos.h
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eb3921e8 1/* Prototypes for exported functions defined in arm.c and pe.c
5624e564 2 Copyright (C) 1999-2015 Free Software Foundation, Inc.
eb3921e8
NC		 3 Contributed by Richard Earnshaw (rearnsha@arm.com)
4 Minor hacks by Nick Clifton (nickc@cygnus.com)
5
4f448245 6 This file is part of GCC.
eb3921e8 7
4f448245
NC		 8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
2f83c7d6 10 the Free Software Foundation; either version 3, or (at your option)
4f448245 11 any later version.
eb3921e8 12
4f448245
NC		 13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
eb3921e8 17
4f448245 18 You should have received a copy of the GNU General Public License
2f83c7d6
NC		 19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
eb3921e8 21
8b97c5f8
ZW		 22#ifndef GCC_ARM_PROTOS_H
23#define GCC_ARM_PROTOS_H
24
677f3fa8 25extern enum unwind_info_type arm_except_unwind_info (struct gcc_options *);
a72d4945 26extern int use_return_insn (int, rtx);
24d5b097 27extern bool use_simple_return_p (void);
bbbbb16a 28extern enum reg_class arm_regno_class (int);
e55ef7f4 29extern void arm_load_pic_register (unsigned long);
e32bac5b 30extern int arm_volatile_func (void);
e32bac5b 31extern void arm_expand_prologue (void);
d461c88a 32extern void arm_expand_epilogue (bool);
258619bb 33extern void arm_declare_function_name (FILE *, const char *, tree);
24d5b097 34extern void thumb2_expand_return (bool);
e32bac5b
RE		 35extern const char *arm_strip_name_encoding (const char *);
36extern void arm_asm_output_labelref (FILE *, const char *);
5b3e6663 37extern void thumb2_asm_output_opcode (FILE *);
e32bac5b 38extern unsigned long arm_current_func_type (void);
b3f8d95d
MM		 39extern HOST_WIDE_INT arm_compute_initial_elimination_offset (unsigned int,
40 unsigned int);
5848830f
PB		 41extern HOST_WIDE_INT thumb_compute_initial_elimination_offset (unsigned int,
42 unsigned int);
2fa330b2 43extern unsigned int arm_dbx_register_number (unsigned int);
617a1b71 44extern void arm_output_fn_unwind (FILE *, bool);
33857df2
JG		 45
46extern rtx arm_expand_builtin (tree exp, rtx target, rtx subtarget
47 ATTRIBUTE_UNUSED, enum machine_mode mode
48 ATTRIBUTE_UNUSED, int ignore ATTRIBUTE_UNUSED);
49extern tree arm_builtin_decl (unsigned code, bool initialize_p
50 ATTRIBUTE_UNUSED);
51extern void arm_init_builtins (void);
52extern void arm_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update);
eb3921e8 53
eb3921e8 54#ifdef RTX_CODE
ef4bddc2
RS		 55extern bool arm_vector_mode_supported_p (machine_mode);
56extern bool arm_small_register_classes_for_mode_p (machine_mode);
57extern int arm_hard_regno_mode_ok (unsigned int, machine_mode);
58extern bool arm_modes_tieable_p (machine_mode, machine_mode);
e32bac5b 59extern int const_ok_for_arm (HOST_WIDE_INT);
c2b640a7 60extern int const_ok_for_op (HOST_WIDE_INT, enum rtx_code);
44cd6810 61extern int const_ok_for_dimode_op (HOST_WIDE_INT, enum rtx_code);
ef4bddc2 62extern int arm_split_constant (RTX_CODE, machine_mode, rtx,
a406f566 63 HOST_WIDE_INT, rtx, rtx, int);
e32bac5b 64extern int legitimate_pic_operand_p (rtx);
ef4bddc2 65extern rtx legitimize_pic_address (rtx, machine_mode, rtx);
d3585b76 66extern rtx legitimize_tls_address (rtx, rtx);
ef4bddc2
RS		 67extern bool arm_legitimate_address_p (machine_mode, rtx, bool);
68extern int arm_legitimate_address_outer_p (machine_mode, rtx, RTX_CODE, int);
69extern int thumb_legitimate_offset_p (machine_mode, HOST_WIDE_INT);
ef4bddc2
RS		 70extern int thumb1_legitimate_address_p (machine_mode, rtx, int);
71extern bool ldm_stm_operation_p (rtx, bool, machine_mode mode,
fb40241d 72 bool, bool);
9b66ebb1 73extern int arm_const_double_rtx (rtx);
f1adb0a9 74extern int vfp3_const_double_rtx (rtx);
ef4bddc2
RS		 75extern int neon_immediate_valid_for_move (rtx, machine_mode, rtx *, int *);
76extern int neon_immediate_valid_for_logic (rtx, machine_mode, int, rtx *,
88f77cba 77 int *);
ef4bddc2 78extern int neon_immediate_valid_for_shift (rtx, machine_mode, rtx *,
31a0c825 79 int *, bool);
88f77cba 80extern char *neon_output_logic_immediate (const char *, rtx *,
ef4bddc2 81 machine_mode, int, int);
31a0c825 82extern char *neon_output_shift_immediate (const char *, char, rtx *,
ef4bddc2
RS		 83 machine_mode, int, bool);
84extern void neon_pairwise_reduce (rtx, rtx, machine_mode,
88f77cba 85 rtx (*) (rtx, rtx, rtx));
814a4c3b 86extern rtx neon_make_constant (rtx);
dfa3f8d0 87extern tree arm_builtin_vectorized_function (tree, tree, tree);
88f77cba 88extern void neon_expand_vector_init (rtx, rtx);
b617fc71
JB		 89extern void neon_lane_bounds (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
90extern void neon_const_bounds (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
ef4bddc2 91extern HOST_WIDE_INT neon_element_bits (machine_mode);
88f77cba 92extern void neon_reinterpret (rtx, rtx);
ef4bddc2 93extern void neon_emit_pair_result_insn (machine_mode,
88f77cba
JB		 94 rtx (*) (rtx, rtx, rtx, rtx),
95 rtx, rtx, rtx);
96extern void neon_disambiguate_copy (rtx *, rtx *, rtx *, unsigned int);
b440f324 97extern void neon_split_vcombine (rtx op[3]);
ef4bddc2 98extern enum reg_class coproc_secondary_reload_class (machine_mode, rtx,
fe2d934b 99 bool);
d3585b76 100extern bool arm_tls_referenced_p (rtx);
d5b7b3ae 101
fdd695fd 102extern int arm_coproc_mem_operand (rtx, bool);
33255ae3 103extern int neon_vector_mem_operand (rtx, int, bool);
88f77cba 104extern int neon_struct_mem_operand (rtx);
e32bac5b 105
d3585b76 106extern int tls_mentioned_p (rtx);
e32bac5b
RE		 107extern int symbol_mentioned_p (rtx);
108extern int label_mentioned_p (rtx);
109extern RTX_CODE minmax_code (rtx);
5d216c70 110extern bool arm_sat_operator_match (rtx, rtx, int *, bool *);
e32bac5b 111extern int adjacent_mem_locations (rtx, rtx);
37119410
BS		 112extern bool gen_ldm_seq (rtx *, int, bool);
113extern bool gen_stm_seq (rtx *, int);
114extern bool gen_const_stm_seq (rtx *, int);
115extern rtx arm_gen_load_multiple (int *, int, rtx, int, rtx, HOST_WIDE_INT *);
116extern rtx arm_gen_store_multiple (int *, int, rtx, int, rtx, HOST_WIDE_INT *);
56289ed2
SD		 117extern bool offset_ok_for_ldrd_strd (HOST_WIDE_INT);
118extern bool operands_ok_ldrd_strd (rtx, rtx, rtx, HOST_WIDE_INT, bool, bool);
4542a38a 119extern bool gen_operands_ldrd_strd (rtx *, bool, bool, bool);
70128ad9 120extern int arm_gen_movmemqi (rtx *);
798d3d04 121extern bool gen_movmem_ldrd_strd (rtx *);
ef4bddc2
RS		 122extern machine_mode arm_select_cc_mode (RTX_CODE, rtx, rtx);
123extern machine_mode arm_select_dominance_cc_mode (rtx, rtx,
e32bac5b 124 HOST_WIDE_INT);
18f0fe6b 125extern rtx arm_gen_compare_reg (RTX_CODE, rtx, rtx, rtx);
e32bac5b
RE		 126extern rtx arm_gen_return_addr_mask (void);
127extern void arm_reload_in_hi (rtx *);
128extern void arm_reload_out_hi (rtx *);
02231c13 129extern int arm_max_const_double_inline_cost (void);
2075b05d 130extern int arm_const_double_inline_cost (rtx);
b4a58f80 131extern bool arm_const_double_by_parts (rtx);
73160ba9 132extern bool arm_const_double_by_immediates (rtx);
7a32d6c4 133extern void arm_emit_call_insn (rtx, rtx, bool);
e32bac5b
RE		 134extern const char *output_call (rtx *);
135extern const char *output_call_mem (rtx *);
571191af 136void arm_emit_movpair (rtx, rtx);
e32bac5b 137extern const char *output_mov_long_double_arm_from_arm (rtx *);
3598da80 138extern const char *output_move_double (rtx *, bool, int *count);
88f77cba 139extern const char *output_move_quad (rtx *);
3598da80 140extern int arm_count_output_move_double_insns (rtx *);
5b3e6663 141extern const char *output_move_vfp (rtx *operands);
88f77cba 142extern const char *output_move_neon (rtx *operands);
647d790d
DM		 143extern int arm_attr_length_move_neon (rtx_insn *);
144extern int arm_address_offset_is_imm (rtx_insn *);
e32bac5b
RE		 145extern const char *output_add_immediate (rtx *);
146extern const char *arithmetic_instr (rtx, int);
147extern void output_ascii_pseudo_op (FILE *, const unsigned char *, int);
f79b86a4 148extern const char *output_return_instruction (rtx, bool, bool, bool);
e32bac5b 149extern void arm_poke_function_name (FILE *, const char *);
81e3f921 150extern void arm_final_prescan_insn (rtx_insn *);
e32bac5b 151extern int arm_debugger_arg_offset (int, rtx);
25a65198 152extern bool arm_is_long_call_p (tree);
5a9335ef 153extern int arm_emit_vector_const (FILE *, rtx);
0fd8c3ad 154extern void arm_emit_fp16_const (rtx c);
5a9335ef 155extern const char * arm_output_load_gr (rtx *);
b27832ed 156extern const char *vfp_output_vstmd (rtx *);
3aee1982 157extern void arm_output_multireg_pop (rtx *, bool, rtx, bool, bool);
c9ca9b88 158extern void arm_set_return_address (rtx, rtx);
6555b6bd 159extern int arm_eliminable_register (rtx);
5b3e6663 160extern const char *arm_output_shift(rtx *, int);
8fd03515
XQ		 161extern const char *arm_output_iwmmxt_shift_immediate (const char *, rtx *, bool);
162extern const char *arm_output_iwmmxt_tinsr (rtx *);
029e79eb 163extern unsigned int arm_sync_loop_insns (rtx , rtx *);
0c27e2d8 164extern int arm_attr_length_push_multi(rtx, rtx);
18f0fe6b
RH		 165extern void arm_expand_compare_and_swap (rtx op[]);
166extern void arm_split_compare_and_swap (rtx op[]);
167extern void arm_split_atomic_op (enum rtx_code, rtx, rtx, rtx, rtx, rtx, rtx);
f959607b 168extern rtx arm_load_tp (rtx);
d5b7b3ae
RE		 169
170#if defined TREE_CODE
e32bac5b 171extern void arm_init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, tree);
ef4bddc2
RS		 172extern bool arm_pad_arg_upward (machine_mode, const_tree);
173extern bool arm_pad_reg_upward (machine_mode, tree, int);
d5b7b3ae 174#endif
9f7bf991 175extern int arm_apply_result_size (void);
d5b7b3ae 176
eb3921e8
NC		 177#endif /* RTX_CODE */
178
d5b7b3ae 179/* Thumb functions. */
e32bac5b 180extern void arm_init_expanders (void);
90911ab6 181extern const char *thumb1_unexpanded_epilogue (void);
5b3e6663
PB		 182extern void thumb1_expand_prologue (void);
183extern void thumb1_expand_epilogue (void);
d018b46e 184extern const char *thumb1_output_interwork (void);
e32bac5b 185extern int thumb_shiftable_const (unsigned HOST_WIDE_INT);
cd2b33d0 186#ifdef RTX_CODE
723d95fe 187extern enum arm_cond_code maybe_get_arm_condition_code (rtx);
81e3f921
DM		 188extern void thumb1_final_prescan_insn (rtx_insn *);
189extern void thumb2_final_prescan_insn (rtx_insn *);
e32bac5b
RE		 190extern const char *thumb_load_double_from_address (rtx *);
191extern const char *thumb_output_move_mem_multiple (int, rtx *);
b12a00f1 192extern const char *thumb_call_via_reg (rtx);
70128ad9 193extern void thumb_expand_movmemqi (rtx *);
e32bac5b
RE		 194extern rtx arm_return_addr (int, rtx);
195extern void thumb_reload_out_hi (rtx *);
196extern void thumb_reload_in_hi (rtx *);
c9ca9b88 197extern void thumb_set_return_address (rtx, rtx);
907dd0c7
RE		 198extern const char *thumb1_output_casesi (rtx *);
199extern const char *thumb2_output_casesi (rtx *);
d5b7b3ae
RE		 200#endif
201
202/* Defined in pe.c. */
e32bac5b
RE		 203extern int arm_dllexport_name_p (const char *);
204extern int arm_dllimport_name_p (const char *);
d5b7b3ae
RE		 205
206#ifdef TREE_CODE
e32bac5b
RE		 207extern void arm_pe_unique_section (tree, int);
208extern void arm_pe_encode_section_info (tree, rtx, int);
209extern int arm_dllexport_p (tree);
210extern int arm_dllimport_p (tree);
211extern void arm_mark_dllexport (tree);
212extern void arm_mark_dllimport (tree);
d5524d52 213extern bool arm_change_mode_p (tree);
d5b7b3ae 214#endif
8b97c5f8 215
c84f825c
CB		 216extern tree arm_valid_target_attribute_tree (tree, struct gcc_options *,
217 struct gcc_options *);
e32bac5b
RE		 218extern void arm_pr_long_calls (struct cpp_reader *);
219extern void arm_pr_no_long_calls (struct cpp_reader *);
220extern void arm_pr_long_calls_off (struct cpp_reader *);
8b97c5f8 221
3101faab 222extern const char *arm_mangle_type (const_tree);
6276b630 223extern const char *arm_mangle_builtin_type (const_tree);
608063c3 224
795dc4fc
PB		 225extern void arm_order_regs_for_local_alloc (void);
226
b24a2ce5
GY		 227extern int arm_max_conditional_execute ();
228
2597da22
CL		 229/* Vectorizer cost model implementation. */
230struct cpu_vec_costs {
231 const int scalar_stmt_cost; /* Cost of any scalar operation, excluding
232 load and store. */
233 const int scalar_load_cost; /* Cost of scalar load. */
234 const int scalar_store_cost; /* Cost of scalar store. */
235 const int vec_stmt_cost; /* Cost of any vector operation, excluding
236 load, store, vector-to-scalar and
237 scalar-to-vector operation. */
238 const int vec_to_scalar_cost; /* Cost of vect-to-scalar operation. */
239 const int scalar_to_vec_cost; /* Cost of scalar-to-vector operation. */
240 const int vec_align_load_cost; /* Cost of aligned vector load. */
241 const int vec_unalign_load_cost; /* Cost of unaligned vector load. */
242 const int vec_unalign_store_cost; /* Cost of unaligned vector load. */
243 const int vec_store_cost; /* Cost of vector store. */
244 const int cond_taken_branch_cost; /* Cost of taken branch for vectorizer
245 cost model. */
246 const int cond_not_taken_branch_cost;/* Cost of not taken branch for
247 vectorizer cost model. */
248};
249
1b78f575
RE		 250#ifdef RTX_CODE
251/* This needs to be here because we need RTX_CODE and similar. */
252
5bea0c6c
KT		 253struct cpu_cost_table;
254
2301ca74
BC		 255/* Dump function ARM_PRINT_TUNE_INFO should be updated whenever this
256 structure is modified. */
257
1b78f575
RE		 258struct tune_params
259{
260 bool (*rtx_costs) (rtx, RTX_CODE, RTX_CODE, int *, bool);
5bea0c6c 261 const struct cpu_cost_table *insn_extra_cost;
647d790d 262 bool (*sched_adjust_cost) (rtx_insn *, rtx, rtx_insn *, int *);
52c266ba
RE		 263 int (*branch_cost) (bool, bool);
264 /* Vectorizer costs. */
265 const struct cpu_vec_costs* vec_costs;
1b78f575 266 int constant_limit;
b24a2ce5 267 /* Maximum number of instructions to conditionalise. */
16868d84 268 int max_insns_skipped;
52c266ba
RE		 269 /* Maximum number of instructions to inline calls to memset. */
270 int max_insns_inline_memset;
271 /* Issue rate of the processor. */
272 unsigned int issue_rate;
273 /* Explicit prefetch data. */
274 struct
275 {
276 int num_slots;
277 int l1_cache_size;
278 int l1_cache_line_size;
279 } prefetch;
280 enum {PREF_CONST_POOL_FALSE, PREF_CONST_POOL_TRUE}
281 prefer_constant_pool: 1;
ab3dfff7 282 /* Prefer STRD/LDRD instructions over PUSH/POP/LDM/STM. */
52c266ba 283 enum {PREF_LDRD_FALSE, PREF_LDRD_TRUE} prefer_ldrd_strd: 1;
a51fb17f
BC		 284 /* The preference for non short cirtcuit operation when optimizing for
285 performance. The first element covers Thumb state and the second one
286 is for ARM state. */
ffa7068e
JG		 287 enum log_op_non_short_circuit {LOG_OP_NON_SHORT_CIRCUIT_FALSE,
288 LOG_OP_NON_SHORT_CIRCUIT_TRUE};
289 log_op_non_short_circuit logical_op_non_short_circuit_thumb: 1;
290 log_op_non_short_circuit logical_op_non_short_circuit_arm: 1;
46fbb3eb 291 /* Prefer 32-bit encoding instead of flag-setting 16-bit encoding. */
52c266ba
RE		 292 enum {DISPARAGE_FLAGS_NEITHER, DISPARAGE_FLAGS_PARTIAL, DISPARAGE_FLAGS_ALL}
293 disparage_flag_setting_t16_encodings: 2;
294 enum {PREF_NEON_64_FALSE, PREF_NEON_64_TRUE} prefer_neon_for_64bits: 1;
ad421159 295 /* Prefer to inline string operations like memset by using Neon. */
52c266ba
RE		 296 enum {PREF_NEON_STRINGOPS_FALSE, PREF_NEON_STRINGOPS_TRUE}
297 string_ops_prefer_neon: 1;
fe0b29c7 298 /* Bitfield encoding the fusible pairs of instructions. Use FUSE_OPS
52c266ba
RE		 299 in an initializer if multiple fusion operations are supported on a
300 target. */
301 enum fuse_ops
302 {
303 FUSE_NOTHING = 0,
304 FUSE_MOVW_MOVT = 1 << 0
fe0b29c7 305 } fusible_ops: 1;
340c7904 306 /* Depth of scheduling queue to check for L2 autoprefetcher. */
52c266ba
RE		 307 enum {SCHED_AUTOPREF_OFF, SCHED_AUTOPREF_RANK, SCHED_AUTOPREF_FULL}
308 sched_autopref: 2;
1b78f575
RE		 309};
310
52c266ba
RE		 311/* Smash multiple fusion operations into a type that can be used for an
312 initializer. */
313#define FUSE_OPS(x) ((tune_params::fuse_ops) (x))
314
1b78f575 315extern const struct tune_params *current_tune;
7f3d8f56 316extern int vfp3_const_double_for_fract_bits (rtx);
c75d51aa
RL		 317/* return power of two from operand, otherwise 0. */
318extern int vfp3_const_double_for_bits (rtx);
99aea943
AS		 319
320extern void arm_emit_coreregs_64bit_shift (enum rtx_code, rtx, rtx, rtx, rtx,
321 rtx);
95ffee1f 322extern bool arm_validize_comparison (rtx *, rtx *, rtx *);
1b78f575
RE		 323#endif /* RTX_CODE */
324
ad421159 325extern bool arm_gen_setmem (rtx *);
b440f324
RH		 326extern void arm_expand_vec_perm (rtx target, rtx op0, rtx op1, rtx sel);
327extern bool arm_expand_vec_perm_const (rtx target, rtx op0, rtx op1, rtx sel);
328
ef4bddc2 329extern bool arm_autoinc_modes_ok_p (machine_mode, enum arm_auto_incmodes);
8875e939 330
34dd397b
SB		 331extern void arm_emit_eabi_attribute (const char *, int, int);
332
d5524d52
CB		 333extern void arm_reset_previous_fndecl (void);
334
b848e289
JG		 335/* Defined in gcc/common/config/arm-common.c. */
336extern const char *arm_rewrite_selected_cpu (const char *name);
337
7049e4eb
CB		 338/* Defined in gcc/common/config/arm-c.c. */
339extern void arm_lang_object_attributes_init (void);
c84f825c 340extern void arm_register_target_pragmas (void);
7049e4eb 341extern void arm_cpu_cpp_builtins (struct cpp_reader *);
c84f825c 342extern void arm_cpu_builtins (struct cpp_reader *, int);
7049e4eb 343
aed773a2
CB		 344extern bool arm_is_constant_pool_ref (rtx);
345
a27d8d80
JG		 346/* Flags used to identify the presence of processor capabilities. */
347
348/* Bit values used to identify processor capabilities. */
349#define FL_CO_PROC (1 << 0) /* Has external co-processor bus */
350#define FL_ARCH3M (1 << 1) /* Extended multiply */
351#define FL_MODE26 (1 << 2) /* 26-bit mode support */
352#define FL_MODE32 (1 << 3) /* 32-bit mode support */
353#define FL_ARCH4 (1 << 4) /* Architecture rel 4 */
354#define FL_ARCH5 (1 << 5) /* Architecture rel 5 */
355#define FL_THUMB (1 << 6) /* Thumb aware */
356#define FL_LDSCHED (1 << 7) /* Load scheduling necessary */
357#define FL_STRONG (1 << 8) /* StrongARM */
358#define FL_ARCH5E (1 << 9) /* DSP extensions to v5 */
359#define FL_XSCALE (1 << 10) /* XScale */
360/* spare (1 << 11) */
361#define FL_ARCH6 (1 << 12) /* Architecture rel 6. Adds
362 media instructions. */
363#define FL_VFPV2 (1 << 13) /* Vector Floating Point V2. */
364#define FL_WBUF (1 << 14) /* Schedule for write buffer ops.
365 Note: ARM6 & 7 derivatives only. */
366#define FL_ARCH6K (1 << 15) /* Architecture rel 6 K extensions. */
367#define FL_THUMB2 (1 << 16) /* Thumb-2. */
368#define FL_NOTM (1 << 17) /* Instructions not present in the 'M'
369 profile. */
370#define FL_THUMB_DIV (1 << 18) /* Hardware divide (Thumb mode). */
371#define FL_VFPV3 (1 << 19) /* Vector Floating Point V3. */
372#define FL_NEON (1 << 20) /* Neon instructions. */
373#define FL_ARCH7EM (1 << 21) /* Instructions present in the ARMv7E-M
374 architecture. */
375#define FL_ARCH7 (1 << 22) /* Architecture 7. */
376#define FL_ARM_DIV (1 << 23) /* Hardware divide (ARM mode). */
377#define FL_ARCH8 (1 << 24) /* Architecture 8. */
378#define FL_CRC32 (1 << 25) /* ARMv8 CRC32 instructions. */
379
380#define FL_SMALLMUL (1 << 26) /* Small multiply supported. */
afe006ad 381#define FL_NO_VOLATILE_CE (1 << 27) /* No volatile memory in IT block. */
a27d8d80
JG		 382
383#define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */
384#define FL_IWMMXT2 (1 << 30) /* "Intel Wireless MMX2 technology". */
39c12541 385#define FL_ARCH6KZ (1 << 31) /* ARMv6KZ architecture. */
a27d8d80
JG		 386
387/* Flags that only effect tuning, not available instructions. */
388#define FL_TUNE (FL_WBUF | FL_VFPV2 | FL_STRONG | FL_LDSCHED \
389 | FL_CO_PROC)
390
391#define FL_FOR_ARCH2 FL_NOTM
392#define FL_FOR_ARCH3 (FL_FOR_ARCH2 | FL_MODE32)
393#define FL_FOR_ARCH3M (FL_FOR_ARCH3 | FL_ARCH3M)
394#define FL_FOR_ARCH4 (FL_FOR_ARCH3M | FL_ARCH4)
395#define FL_FOR_ARCH4T (FL_FOR_ARCH4 | FL_THUMB)
396#define FL_FOR_ARCH5 (FL_FOR_ARCH4 | FL_ARCH5)
397#define FL_FOR_ARCH5T (FL_FOR_ARCH5 | FL_THUMB)
398#define FL_FOR_ARCH5E (FL_FOR_ARCH5 | FL_ARCH5E)
399#define FL_FOR_ARCH5TE (FL_FOR_ARCH5E | FL_THUMB)
400#define FL_FOR_ARCH5TEJ FL_FOR_ARCH5TE
401#define FL_FOR_ARCH6 (FL_FOR_ARCH5TE | FL_ARCH6)
402#define FL_FOR_ARCH6J FL_FOR_ARCH6
403#define FL_FOR_ARCH6K (FL_FOR_ARCH6 | FL_ARCH6K)
404#define FL_FOR_ARCH6Z FL_FOR_ARCH6
39c12541 405#define FL_FOR_ARCH6KZ (FL_FOR_ARCH6K | FL_ARCH6KZ)
a27d8d80
JG		 406#define FL_FOR_ARCH6T2 (FL_FOR_ARCH6 | FL_THUMB2)
407#define FL_FOR_ARCH6M (FL_FOR_ARCH6 & ~FL_NOTM)
408#define FL_FOR_ARCH7 ((FL_FOR_ARCH6T2 & ~FL_NOTM) | FL_ARCH7)
409#define FL_FOR_ARCH7A (FL_FOR_ARCH7 | FL_NOTM | FL_ARCH6K)
410#define FL_FOR_ARCH7VE (FL_FOR_ARCH7A | FL_THUMB_DIV | FL_ARM_DIV)
411#define FL_FOR_ARCH7R (FL_FOR_ARCH7A | FL_THUMB_DIV)
412#define FL_FOR_ARCH7M (FL_FOR_ARCH7 | FL_THUMB_DIV)
413#define FL_FOR_ARCH7EM (FL_FOR_ARCH7M | FL_ARCH7EM)
414#define FL_FOR_ARCH8A (FL_FOR_ARCH7VE | FL_ARCH8)
415
416/* The bits in this mask specify which
417 instructions we are allowed to generate. */
418extern unsigned long insn_flags;
419
420/* The bits in this mask specify which instruction scheduling options should
421 be used. */
422extern unsigned long tune_flags;
423
424/* Nonzero if this chip supports the ARM Architecture 3M extensions. */
425extern int arm_arch3m;
426
427/* Nonzero if this chip supports the ARM Architecture 4 extensions. */
428extern int arm_arch4;
429
430/* Nonzero if this chip supports the ARM Architecture 4t extensions. */
431extern int arm_arch4t;
432
433/* Nonzero if this chip supports the ARM Architecture 5 extensions. */
434extern int arm_arch5;
435
436/* Nonzero if this chip supports the ARM Architecture 5E extensions. */
437extern int arm_arch5e;
438
439/* Nonzero if this chip supports the ARM Architecture 6 extensions. */
440extern int arm_arch6;
441
442/* Nonzero if this chip supports the ARM 6K extensions. */
443extern int arm_arch6k;
444
39c12541
MW		 445/* Nonzero if this chip supports the ARM 6KZ extensions. */
446extern int arm_arch6kz;
447
a27d8d80
JG		 448/* Nonzero if instructions present in ARMv6-M can be used. */
449extern int arm_arch6m;
450
451/* Nonzero if this chip supports the ARM 7 extensions. */
452extern int arm_arch7;
453
454/* Nonzero if instructions not present in the 'M' profile can be used. */
455extern int arm_arch_notm;
456
457/* Nonzero if instructions present in ARMv7E-M can be used. */
458extern int arm_arch7em;
459
460/* Nonzero if instructions present in ARMv8 can be used. */
461extern int arm_arch8;
462
463/* Nonzero if this chip can benefit from load scheduling. */
464extern int arm_ld_sched;
465
466/* Nonzero if this chip is a StrongARM. */
467extern int arm_tune_strongarm;
468
469/* Nonzero if this chip supports Intel Wireless MMX technology. */
470extern int arm_arch_iwmmxt;
471
472/* Nonzero if this chip supports Intel Wireless MMX2 technology. */
473extern int arm_arch_iwmmxt2;
474
475/* Nonzero if this chip is an XScale. */
476extern int arm_arch_xscale;
477
478/* Nonzero if tuning for XScale */
479extern int arm_tune_xscale;
480
481/* Nonzero if we want to tune for stores that access the write-buffer.
482 This typically means an ARM6 or ARM7 with MMU or MPU. */
483extern int arm_tune_wbuf;
484
485/* Nonzero if tuning for Cortex-A9. */
486extern int arm_tune_cortex_a9;
487
a27d8d80
JG		 488/* Nonzero if we should define __THUMB_INTERWORK__ in the
489 preprocessor.
490 XXX This is a bit of a hack, it's intended to help work around
491 problems in GLD which doesn't understand that armv5t code is
492 interworking clean. */
493extern int arm_cpp_interwork;
494
495/* Nonzero if chip supports Thumb 2. */
496extern int arm_arch_thumb2;
497
498/* Nonzero if chip supports integer division instruction. */
499extern int arm_arch_arm_hwdiv;
500extern int arm_arch_thumb_hwdiv;
501
afe006ad
TG		 502/* Nonzero if chip disallows volatile memory access in IT block. */
503extern int arm_arch_no_volatile_ce;
504
a27d8d80
JG		 505/* Nonzero if we should use Neon to handle 64-bits operations rather
506 than core registers. */
507extern int prefer_neon_for_64bits;
508
509
510
88657302 511#endif /* ! GCC_ARM_PROTOS_H */
Mirror of https://gcc.gnu.org/git/gcc.git