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eb3921e8 | 1 | /* Prototypes for exported functions defined in arm.c and pe.c |
cbe34bb5 | 2 | Copyright (C) 1999-2017 Free Software Foundation, Inc. |
eb3921e8 NC |
3 | Contributed by Richard Earnshaw (rearnsha@arm.com) |
4 | Minor hacks by Nick Clifton (nickc@cygnus.com) | |
5 | ||
4f448245 | 6 | This file is part of GCC. |
eb3921e8 | 7 | |
4f448245 NC |
8 | GCC is free software; you can redistribute it and/or modify |
9 | it under the terms of the GNU General Public License as published by | |
2f83c7d6 | 10 | the Free Software Foundation; either version 3, or (at your option) |
4f448245 | 11 | any later version. |
eb3921e8 | 12 | |
4f448245 NC |
13 | GCC is distributed in the hope that it will be useful, |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
eb3921e8 | 17 | |
4f448245 | 18 | You should have received a copy of the GNU General Public License |
2f83c7d6 NC |
19 | along with GCC; see the file COPYING3. If not see |
20 | <http://www.gnu.org/licenses/>. */ | |
eb3921e8 | 21 | |
8b97c5f8 ZW |
22 | #ifndef GCC_ARM_PROTOS_H |
23 | #define GCC_ARM_PROTOS_H | |
24 | ||
851966d6 | 25 | #include "sbitmap.h" |
70e73d3c | 26 | |
677f3fa8 | 27 | extern enum unwind_info_type arm_except_unwind_info (struct gcc_options *); |
a72d4945 | 28 | extern int use_return_insn (int, rtx); |
24d5b097 | 29 | extern bool use_simple_return_p (void); |
bbbbb16a | 30 | extern enum reg_class arm_regno_class (int); |
e55ef7f4 | 31 | extern void arm_load_pic_register (unsigned long); |
e32bac5b | 32 | extern int arm_volatile_func (void); |
e32bac5b | 33 | extern void arm_expand_prologue (void); |
d461c88a | 34 | extern void arm_expand_epilogue (bool); |
258619bb | 35 | extern void arm_declare_function_name (FILE *, const char *, tree); |
9ad1f699 | 36 | extern void arm_asm_declare_function_name (FILE *, const char *, tree); |
24d5b097 | 37 | extern void thumb2_expand_return (bool); |
e32bac5b RE |
38 | extern const char *arm_strip_name_encoding (const char *); |
39 | extern void arm_asm_output_labelref (FILE *, const char *); | |
5b3e6663 | 40 | extern void thumb2_asm_output_opcode (FILE *); |
e32bac5b | 41 | extern unsigned long arm_current_func_type (void); |
b3f8d95d MM |
42 | extern HOST_WIDE_INT arm_compute_initial_elimination_offset (unsigned int, |
43 | unsigned int); | |
5848830f PB |
44 | extern HOST_WIDE_INT thumb_compute_initial_elimination_offset (unsigned int, |
45 | unsigned int); | |
2fa330b2 | 46 | extern unsigned int arm_dbx_register_number (unsigned int); |
617a1b71 | 47 | extern void arm_output_fn_unwind (FILE *, bool); |
33857df2 JG |
48 | |
49 | extern rtx arm_expand_builtin (tree exp, rtx target, rtx subtarget | |
50 | ATTRIBUTE_UNUSED, enum machine_mode mode | |
51 | ATTRIBUTE_UNUSED, int ignore ATTRIBUTE_UNUSED); | |
52 | extern tree arm_builtin_decl (unsigned code, bool initialize_p | |
53 | ATTRIBUTE_UNUSED); | |
54 | extern void arm_init_builtins (void); | |
55 | extern void arm_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update); | |
93c590ee MC |
56 | extern rtx arm_simd_vect_par_cnst_half (machine_mode mode, bool high); |
57 | extern bool arm_simd_check_vect_par_cnst_half_p (rtx op, machine_mode mode, | |
58 | bool high); | |
eb3921e8 | 59 | #ifdef RTX_CODE |
c8cd4696 MC |
60 | extern void arm_gen_unlikely_cbranch (enum rtx_code, machine_mode cc_mode, |
61 | rtx label_ref); | |
ef4bddc2 RS |
62 | extern bool arm_vector_mode_supported_p (machine_mode); |
63 | extern bool arm_small_register_classes_for_mode_p (machine_mode); | |
64 | extern int arm_hard_regno_mode_ok (unsigned int, machine_mode); | |
65 | extern bool arm_modes_tieable_p (machine_mode, machine_mode); | |
e32bac5b | 66 | extern int const_ok_for_arm (HOST_WIDE_INT); |
c2b640a7 | 67 | extern int const_ok_for_op (HOST_WIDE_INT, enum rtx_code); |
44cd6810 | 68 | extern int const_ok_for_dimode_op (HOST_WIDE_INT, enum rtx_code); |
ef4bddc2 | 69 | extern int arm_split_constant (RTX_CODE, machine_mode, rtx, |
a406f566 | 70 | HOST_WIDE_INT, rtx, rtx, int); |
e32bac5b | 71 | extern int legitimate_pic_operand_p (rtx); |
ef4bddc2 | 72 | extern rtx legitimize_pic_address (rtx, machine_mode, rtx); |
d3585b76 | 73 | extern rtx legitimize_tls_address (rtx, rtx); |
ef4bddc2 RS |
74 | extern bool arm_legitimate_address_p (machine_mode, rtx, bool); |
75 | extern int arm_legitimate_address_outer_p (machine_mode, rtx, RTX_CODE, int); | |
76 | extern int thumb_legitimate_offset_p (machine_mode, HOST_WIDE_INT); | |
ef4bddc2 RS |
77 | extern int thumb1_legitimate_address_p (machine_mode, rtx, int); |
78 | extern bool ldm_stm_operation_p (rtx, bool, machine_mode mode, | |
fb40241d | 79 | bool, bool); |
9b66ebb1 | 80 | extern int arm_const_double_rtx (rtx); |
f1adb0a9 | 81 | extern int vfp3_const_double_rtx (rtx); |
ef4bddc2 RS |
82 | extern int neon_immediate_valid_for_move (rtx, machine_mode, rtx *, int *); |
83 | extern int neon_immediate_valid_for_logic (rtx, machine_mode, int, rtx *, | |
88f77cba | 84 | int *); |
ef4bddc2 | 85 | extern int neon_immediate_valid_for_shift (rtx, machine_mode, rtx *, |
31a0c825 | 86 | int *, bool); |
88f77cba | 87 | extern char *neon_output_logic_immediate (const char *, rtx *, |
ef4bddc2 | 88 | machine_mode, int, int); |
31a0c825 | 89 | extern char *neon_output_shift_immediate (const char *, char, rtx *, |
ef4bddc2 RS |
90 | machine_mode, int, bool); |
91 | extern void neon_pairwise_reduce (rtx, rtx, machine_mode, | |
88f77cba | 92 | rtx (*) (rtx, rtx, rtx)); |
814a4c3b | 93 | extern rtx neon_make_constant (rtx); |
10766209 | 94 | extern tree arm_builtin_vectorized_function (unsigned int, tree, tree); |
88f77cba | 95 | extern void neon_expand_vector_init (rtx, rtx); |
eaa80f64 | 96 | extern void neon_lane_bounds (rtx, HOST_WIDE_INT, HOST_WIDE_INT, const_tree); |
d57daa0c | 97 | extern void arm_const_bounds (rtx, HOST_WIDE_INT, HOST_WIDE_INT); |
ef4bddc2 | 98 | extern HOST_WIDE_INT neon_element_bits (machine_mode); |
ef4bddc2 | 99 | extern void neon_emit_pair_result_insn (machine_mode, |
88f77cba JB |
100 | rtx (*) (rtx, rtx, rtx, rtx), |
101 | rtx, rtx, rtx); | |
102 | extern void neon_disambiguate_copy (rtx *, rtx *, rtx *, unsigned int); | |
b440f324 | 103 | extern void neon_split_vcombine (rtx op[3]); |
ef4bddc2 | 104 | extern enum reg_class coproc_secondary_reload_class (machine_mode, rtx, |
fe2d934b | 105 | bool); |
d3585b76 | 106 | extern bool arm_tls_referenced_p (rtx); |
d5b7b3ae | 107 | |
fdd695fd | 108 | extern int arm_coproc_mem_operand (rtx, bool); |
33255ae3 | 109 | extern int neon_vector_mem_operand (rtx, int, bool); |
88f77cba | 110 | extern int neon_struct_mem_operand (rtx); |
e32bac5b | 111 | |
d3585b76 | 112 | extern int tls_mentioned_p (rtx); |
e32bac5b RE |
113 | extern int symbol_mentioned_p (rtx); |
114 | extern int label_mentioned_p (rtx); | |
115 | extern RTX_CODE minmax_code (rtx); | |
5d216c70 | 116 | extern bool arm_sat_operator_match (rtx, rtx, int *, bool *); |
e32bac5b | 117 | extern int adjacent_mem_locations (rtx, rtx); |
37119410 BS |
118 | extern bool gen_ldm_seq (rtx *, int, bool); |
119 | extern bool gen_stm_seq (rtx *, int); | |
120 | extern bool gen_const_stm_seq (rtx *, int); | |
121 | extern rtx arm_gen_load_multiple (int *, int, rtx, int, rtx, HOST_WIDE_INT *); | |
122 | extern rtx arm_gen_store_multiple (int *, int, rtx, int, rtx, HOST_WIDE_INT *); | |
56289ed2 SD |
123 | extern bool offset_ok_for_ldrd_strd (HOST_WIDE_INT); |
124 | extern bool operands_ok_ldrd_strd (rtx, rtx, rtx, HOST_WIDE_INT, bool, bool); | |
4542a38a | 125 | extern bool gen_operands_ldrd_strd (rtx *, bool, bool, bool); |
70128ad9 | 126 | extern int arm_gen_movmemqi (rtx *); |
798d3d04 | 127 | extern bool gen_movmem_ldrd_strd (rtx *); |
ef4bddc2 RS |
128 | extern machine_mode arm_select_cc_mode (RTX_CODE, rtx, rtx); |
129 | extern machine_mode arm_select_dominance_cc_mode (rtx, rtx, | |
e32bac5b | 130 | HOST_WIDE_INT); |
18f0fe6b | 131 | extern rtx arm_gen_compare_reg (RTX_CODE, rtx, rtx, rtx); |
e32bac5b RE |
132 | extern rtx arm_gen_return_addr_mask (void); |
133 | extern void arm_reload_in_hi (rtx *); | |
134 | extern void arm_reload_out_hi (rtx *); | |
02231c13 | 135 | extern int arm_max_const_double_inline_cost (void); |
2075b05d | 136 | extern int arm_const_double_inline_cost (rtx); |
b4a58f80 | 137 | extern bool arm_const_double_by_parts (rtx); |
73160ba9 | 138 | extern bool arm_const_double_by_immediates (rtx); |
7a32d6c4 | 139 | extern void arm_emit_call_insn (rtx, rtx, bool); |
c92e08e3 | 140 | bool detect_cmse_nonsecure_call (tree); |
e32bac5b | 141 | extern const char *output_call (rtx *); |
571191af | 142 | void arm_emit_movpair (rtx, rtx); |
e32bac5b | 143 | extern const char *output_mov_long_double_arm_from_arm (rtx *); |
3598da80 | 144 | extern const char *output_move_double (rtx *, bool, int *count); |
88f77cba | 145 | extern const char *output_move_quad (rtx *); |
3598da80 | 146 | extern int arm_count_output_move_double_insns (rtx *); |
5b3e6663 | 147 | extern const char *output_move_vfp (rtx *operands); |
88f77cba | 148 | extern const char *output_move_neon (rtx *operands); |
647d790d DM |
149 | extern int arm_attr_length_move_neon (rtx_insn *); |
150 | extern int arm_address_offset_is_imm (rtx_insn *); | |
e32bac5b RE |
151 | extern const char *output_add_immediate (rtx *); |
152 | extern const char *arithmetic_instr (rtx, int); | |
153 | extern void output_ascii_pseudo_op (FILE *, const unsigned char *, int); | |
f79b86a4 | 154 | extern const char *output_return_instruction (rtx, bool, bool, bool); |
4fb94ef9 | 155 | extern const char *output_probe_stack_range (rtx, rtx); |
e32bac5b | 156 | extern void arm_poke_function_name (FILE *, const char *); |
81e3f921 | 157 | extern void arm_final_prescan_insn (rtx_insn *); |
e32bac5b | 158 | extern int arm_debugger_arg_offset (int, rtx); |
25a65198 | 159 | extern bool arm_is_long_call_p (tree); |
5a9335ef | 160 | extern int arm_emit_vector_const (FILE *, rtx); |
0fd8c3ad | 161 | extern void arm_emit_fp16_const (rtx c); |
5a9335ef | 162 | extern const char * arm_output_load_gr (rtx *); |
b27832ed | 163 | extern const char *vfp_output_vstmd (rtx *); |
3aee1982 | 164 | extern void arm_output_multireg_pop (rtx *, bool, rtx, bool, bool); |
c9ca9b88 | 165 | extern void arm_set_return_address (rtx, rtx); |
6555b6bd | 166 | extern int arm_eliminable_register (rtx); |
5b3e6663 | 167 | extern const char *arm_output_shift(rtx *, int); |
8fd03515 XQ |
168 | extern const char *arm_output_iwmmxt_shift_immediate (const char *, rtx *, bool); |
169 | extern const char *arm_output_iwmmxt_tinsr (rtx *); | |
029e79eb | 170 | extern unsigned int arm_sync_loop_insns (rtx , rtx *); |
0c27e2d8 | 171 | extern int arm_attr_length_push_multi(rtx, rtx); |
5775d58c | 172 | extern int arm_attr_length_pop_multi(rtx *, bool, bool); |
18f0fe6b RH |
173 | extern void arm_expand_compare_and_swap (rtx op[]); |
174 | extern void arm_split_compare_and_swap (rtx op[]); | |
175 | extern void arm_split_atomic_op (enum rtx_code, rtx, rtx, rtx, rtx, rtx, rtx); | |
f959607b | 176 | extern rtx arm_load_tp (rtx); |
d57daa0c | 177 | extern bool arm_coproc_builtin_available (enum unspecv); |
3811581f | 178 | extern bool arm_coproc_ldc_stc_legitimate_address (rtx); |
d5b7b3ae RE |
179 | |
180 | #if defined TREE_CODE | |
e32bac5b | 181 | extern void arm_init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, tree); |
ef4bddc2 RS |
182 | extern bool arm_pad_arg_upward (machine_mode, const_tree); |
183 | extern bool arm_pad_reg_upward (machine_mode, tree, int); | |
d5b7b3ae | 184 | #endif |
9f7bf991 | 185 | extern int arm_apply_result_size (void); |
d5b7b3ae | 186 | |
eb3921e8 NC |
187 | #endif /* RTX_CODE */ |
188 | ||
d5b7b3ae | 189 | /* Thumb functions. */ |
e32bac5b | 190 | extern void arm_init_expanders (void); |
90911ab6 | 191 | extern const char *thumb1_unexpanded_epilogue (void); |
5b3e6663 PB |
192 | extern void thumb1_expand_prologue (void); |
193 | extern void thumb1_expand_epilogue (void); | |
d018b46e | 194 | extern const char *thumb1_output_interwork (void); |
e32bac5b | 195 | extern int thumb_shiftable_const (unsigned HOST_WIDE_INT); |
cd2b33d0 | 196 | #ifdef RTX_CODE |
723d95fe | 197 | extern enum arm_cond_code maybe_get_arm_condition_code (rtx); |
81e3f921 DM |
198 | extern void thumb1_final_prescan_insn (rtx_insn *); |
199 | extern void thumb2_final_prescan_insn (rtx_insn *); | |
e32bac5b RE |
200 | extern const char *thumb_load_double_from_address (rtx *); |
201 | extern const char *thumb_output_move_mem_multiple (int, rtx *); | |
b12a00f1 | 202 | extern const char *thumb_call_via_reg (rtx); |
70128ad9 | 203 | extern void thumb_expand_movmemqi (rtx *); |
e32bac5b RE |
204 | extern rtx arm_return_addr (int, rtx); |
205 | extern void thumb_reload_out_hi (rtx *); | |
c9ca9b88 | 206 | extern void thumb_set_return_address (rtx, rtx); |
907dd0c7 RE |
207 | extern const char *thumb1_output_casesi (rtx *); |
208 | extern const char *thumb2_output_casesi (rtx *); | |
d5b7b3ae RE |
209 | #endif |
210 | ||
211 | /* Defined in pe.c. */ | |
e32bac5b RE |
212 | extern int arm_dllexport_name_p (const char *); |
213 | extern int arm_dllimport_name_p (const char *); | |
d5b7b3ae RE |
214 | |
215 | #ifdef TREE_CODE | |
e32bac5b RE |
216 | extern void arm_pe_unique_section (tree, int); |
217 | extern void arm_pe_encode_section_info (tree, rtx, int); | |
218 | extern int arm_dllexport_p (tree); | |
219 | extern int arm_dllimport_p (tree); | |
220 | extern void arm_mark_dllexport (tree); | |
221 | extern void arm_mark_dllimport (tree); | |
d5524d52 | 222 | extern bool arm_change_mode_p (tree); |
d5b7b3ae | 223 | #endif |
8b97c5f8 | 224 | |
c84f825c CB |
225 | extern tree arm_valid_target_attribute_tree (tree, struct gcc_options *, |
226 | struct gcc_options *); | |
851966d6 | 227 | extern void arm_configure_build_target (struct arm_build_target *, |
a53613c4 | 228 | struct cl_target_option *, |
851966d6 | 229 | struct gcc_options *, bool); |
e32bac5b RE |
230 | extern void arm_pr_long_calls (struct cpp_reader *); |
231 | extern void arm_pr_no_long_calls (struct cpp_reader *); | |
232 | extern void arm_pr_long_calls_off (struct cpp_reader *); | |
8b97c5f8 | 233 | |
3101faab | 234 | extern const char *arm_mangle_type (const_tree); |
6276b630 | 235 | extern const char *arm_mangle_builtin_type (const_tree); |
608063c3 | 236 | |
795dc4fc PB |
237 | extern void arm_order_regs_for_local_alloc (void); |
238 | ||
b24a2ce5 GY |
239 | extern int arm_max_conditional_execute (); |
240 | ||
2597da22 CL |
241 | /* Vectorizer cost model implementation. */ |
242 | struct cpu_vec_costs { | |
243 | const int scalar_stmt_cost; /* Cost of any scalar operation, excluding | |
244 | load and store. */ | |
245 | const int scalar_load_cost; /* Cost of scalar load. */ | |
246 | const int scalar_store_cost; /* Cost of scalar store. */ | |
247 | const int vec_stmt_cost; /* Cost of any vector operation, excluding | |
248 | load, store, vector-to-scalar and | |
249 | scalar-to-vector operation. */ | |
250 | const int vec_to_scalar_cost; /* Cost of vect-to-scalar operation. */ | |
251 | const int scalar_to_vec_cost; /* Cost of scalar-to-vector operation. */ | |
252 | const int vec_align_load_cost; /* Cost of aligned vector load. */ | |
253 | const int vec_unalign_load_cost; /* Cost of unaligned vector load. */ | |
254 | const int vec_unalign_store_cost; /* Cost of unaligned vector load. */ | |
255 | const int vec_store_cost; /* Cost of vector store. */ | |
256 | const int cond_taken_branch_cost; /* Cost of taken branch for vectorizer | |
257 | cost model. */ | |
258 | const int cond_not_taken_branch_cost;/* Cost of not taken branch for | |
259 | vectorizer cost model. */ | |
260 | }; | |
261 | ||
1b78f575 RE |
262 | #ifdef RTX_CODE |
263 | /* This needs to be here because we need RTX_CODE and similar. */ | |
264 | ||
5bea0c6c KT |
265 | struct cpu_cost_table; |
266 | ||
2301ca74 BC |
267 | /* Dump function ARM_PRINT_TUNE_INFO should be updated whenever this |
268 | structure is modified. */ | |
269 | ||
1b78f575 RE |
270 | struct tune_params |
271 | { | |
5bea0c6c | 272 | const struct cpu_cost_table *insn_extra_cost; |
b505225b | 273 | bool (*sched_adjust_cost) (rtx_insn *, int, rtx_insn *, int *); |
52c266ba RE |
274 | int (*branch_cost) (bool, bool); |
275 | /* Vectorizer costs. */ | |
276 | const struct cpu_vec_costs* vec_costs; | |
1b78f575 | 277 | int constant_limit; |
b24a2ce5 | 278 | /* Maximum number of instructions to conditionalise. */ |
16868d84 | 279 | int max_insns_skipped; |
52c266ba RE |
280 | /* Maximum number of instructions to inline calls to memset. */ |
281 | int max_insns_inline_memset; | |
282 | /* Issue rate of the processor. */ | |
283 | unsigned int issue_rate; | |
284 | /* Explicit prefetch data. */ | |
285 | struct | |
286 | { | |
287 | int num_slots; | |
288 | int l1_cache_size; | |
289 | int l1_cache_line_size; | |
290 | } prefetch; | |
291 | enum {PREF_CONST_POOL_FALSE, PREF_CONST_POOL_TRUE} | |
292 | prefer_constant_pool: 1; | |
ab3dfff7 | 293 | /* Prefer STRD/LDRD instructions over PUSH/POP/LDM/STM. */ |
52c266ba | 294 | enum {PREF_LDRD_FALSE, PREF_LDRD_TRUE} prefer_ldrd_strd: 1; |
a51fb17f BC |
295 | /* The preference for non short cirtcuit operation when optimizing for |
296 | performance. The first element covers Thumb state and the second one | |
297 | is for ARM state. */ | |
ffa7068e JG |
298 | enum log_op_non_short_circuit {LOG_OP_NON_SHORT_CIRCUIT_FALSE, |
299 | LOG_OP_NON_SHORT_CIRCUIT_TRUE}; | |
300 | log_op_non_short_circuit logical_op_non_short_circuit_thumb: 1; | |
301 | log_op_non_short_circuit logical_op_non_short_circuit_arm: 1; | |
46fbb3eb | 302 | /* Prefer 32-bit encoding instead of flag-setting 16-bit encoding. */ |
52c266ba RE |
303 | enum {DISPARAGE_FLAGS_NEITHER, DISPARAGE_FLAGS_PARTIAL, DISPARAGE_FLAGS_ALL} |
304 | disparage_flag_setting_t16_encodings: 2; | |
305 | enum {PREF_NEON_64_FALSE, PREF_NEON_64_TRUE} prefer_neon_for_64bits: 1; | |
ad421159 | 306 | /* Prefer to inline string operations like memset by using Neon. */ |
52c266ba RE |
307 | enum {PREF_NEON_STRINGOPS_FALSE, PREF_NEON_STRINGOPS_TRUE} |
308 | string_ops_prefer_neon: 1; | |
fe0b29c7 | 309 | /* Bitfield encoding the fusible pairs of instructions. Use FUSE_OPS |
52c266ba RE |
310 | in an initializer if multiple fusion operations are supported on a |
311 | target. */ | |
312 | enum fuse_ops | |
313 | { | |
314 | FUSE_NOTHING = 0, | |
066c14c9 WD |
315 | FUSE_MOVW_MOVT = 1 << 0, |
316 | FUSE_AES_AESMC = 1 << 1 | |
317 | } fusible_ops: 2; | |
340c7904 | 318 | /* Depth of scheduling queue to check for L2 autoprefetcher. */ |
52c266ba RE |
319 | enum {SCHED_AUTOPREF_OFF, SCHED_AUTOPREF_RANK, SCHED_AUTOPREF_FULL} |
320 | sched_autopref: 2; | |
1b78f575 RE |
321 | }; |
322 | ||
52c266ba RE |
323 | /* Smash multiple fusion operations into a type that can be used for an |
324 | initializer. */ | |
325 | #define FUSE_OPS(x) ((tune_params::fuse_ops) (x)) | |
326 | ||
1b78f575 | 327 | extern const struct tune_params *current_tune; |
7f3d8f56 | 328 | extern int vfp3_const_double_for_fract_bits (rtx); |
c75d51aa RL |
329 | /* return power of two from operand, otherwise 0. */ |
330 | extern int vfp3_const_double_for_bits (rtx); | |
99aea943 AS |
331 | |
332 | extern void arm_emit_coreregs_64bit_shift (enum rtx_code, rtx, rtx, rtx, rtx, | |
333 | rtx); | |
39fa4aec | 334 | extern bool arm_fusion_enabled_p (tune_params::fuse_ops); |
6ce43645 | 335 | extern bool arm_valid_symbolic_address_p (rtx); |
95ffee1f | 336 | extern bool arm_validize_comparison (rtx *, rtx *, rtx *); |
1b78f575 RE |
337 | #endif /* RTX_CODE */ |
338 | ||
ad421159 | 339 | extern bool arm_gen_setmem (rtx *); |
b440f324 RH |
340 | extern void arm_expand_vec_perm (rtx target, rtx op0, rtx op1, rtx sel); |
341 | extern bool arm_expand_vec_perm_const (rtx target, rtx op0, rtx op1, rtx sel); | |
342 | ||
ef4bddc2 | 343 | extern bool arm_autoinc_modes_ok_p (machine_mode, enum arm_auto_incmodes); |
8875e939 | 344 | |
34dd397b SB |
345 | extern void arm_emit_eabi_attribute (const char *, int, int); |
346 | ||
d5524d52 | 347 | extern void arm_reset_previous_fndecl (void); |
eeb085f3 | 348 | extern void save_restore_target_globals (tree); |
d5524d52 | 349 | |
b848e289 JG |
350 | /* Defined in gcc/common/config/arm-common.c. */ |
351 | extern const char *arm_rewrite_selected_cpu (const char *name); | |
352 | ||
7049e4eb CB |
353 | /* Defined in gcc/common/config/arm-c.c. */ |
354 | extern void arm_lang_object_attributes_init (void); | |
c84f825c | 355 | extern void arm_register_target_pragmas (void); |
7049e4eb CB |
356 | extern void arm_cpu_cpp_builtins (struct cpp_reader *); |
357 | ||
aed773a2 CB |
358 | extern bool arm_is_constant_pool_ref (rtx); |
359 | ||
a27d8d80 JG |
360 | /* The bits in this mask specify which instruction scheduling options should |
361 | be used. */ | |
643a5717 | 362 | extern unsigned int tune_flags; |
a27d8d80 JG |
363 | |
364 | /* Nonzero if this chip supports the ARM Architecture 3M extensions. */ | |
365 | extern int arm_arch3m; | |
366 | ||
367 | /* Nonzero if this chip supports the ARM Architecture 4 extensions. */ | |
368 | extern int arm_arch4; | |
369 | ||
370 | /* Nonzero if this chip supports the ARM Architecture 4t extensions. */ | |
371 | extern int arm_arch4t; | |
372 | ||
373 | /* Nonzero if this chip supports the ARM Architecture 5 extensions. */ | |
374 | extern int arm_arch5; | |
375 | ||
376 | /* Nonzero if this chip supports the ARM Architecture 5E extensions. */ | |
377 | extern int arm_arch5e; | |
378 | ||
379 | /* Nonzero if this chip supports the ARM Architecture 6 extensions. */ | |
380 | extern int arm_arch6; | |
381 | ||
382 | /* Nonzero if this chip supports the ARM 6K extensions. */ | |
383 | extern int arm_arch6k; | |
384 | ||
39c12541 MW |
385 | /* Nonzero if this chip supports the ARM 6KZ extensions. */ |
386 | extern int arm_arch6kz; | |
387 | ||
a27d8d80 JG |
388 | /* Nonzero if instructions present in ARMv6-M can be used. */ |
389 | extern int arm_arch6m; | |
390 | ||
391 | /* Nonzero if this chip supports the ARM 7 extensions. */ | |
392 | extern int arm_arch7; | |
393 | ||
6c466c7c RE |
394 | /* Nonzero if this chip supports the ARM 7ve extensions. */ |
395 | extern int arm_arch7ve; | |
396 | ||
a27d8d80 JG |
397 | /* Nonzero if instructions not present in the 'M' profile can be used. */ |
398 | extern int arm_arch_notm; | |
399 | ||
400 | /* Nonzero if instructions present in ARMv7E-M can be used. */ | |
401 | extern int arm_arch7em; | |
402 | ||
403 | /* Nonzero if instructions present in ARMv8 can be used. */ | |
404 | extern int arm_arch8; | |
405 | ||
406 | /* Nonzero if this chip can benefit from load scheduling. */ | |
407 | extern int arm_ld_sched; | |
408 | ||
409 | /* Nonzero if this chip is a StrongARM. */ | |
410 | extern int arm_tune_strongarm; | |
411 | ||
412 | /* Nonzero if this chip supports Intel Wireless MMX technology. */ | |
413 | extern int arm_arch_iwmmxt; | |
414 | ||
415 | /* Nonzero if this chip supports Intel Wireless MMX2 technology. */ | |
416 | extern int arm_arch_iwmmxt2; | |
417 | ||
418 | /* Nonzero if this chip is an XScale. */ | |
419 | extern int arm_arch_xscale; | |
420 | ||
421 | /* Nonzero if tuning for XScale */ | |
422 | extern int arm_tune_xscale; | |
423 | ||
424 | /* Nonzero if we want to tune for stores that access the write-buffer. | |
425 | This typically means an ARM6 or ARM7 with MMU or MPU. */ | |
426 | extern int arm_tune_wbuf; | |
427 | ||
428 | /* Nonzero if tuning for Cortex-A9. */ | |
429 | extern int arm_tune_cortex_a9; | |
430 | ||
a27d8d80 JG |
431 | /* Nonzero if we should define __THUMB_INTERWORK__ in the |
432 | preprocessor. | |
433 | XXX This is a bit of a hack, it's intended to help work around | |
434 | problems in GLD which doesn't understand that armv5t code is | |
435 | interworking clean. */ | |
436 | extern int arm_cpp_interwork; | |
437 | ||
52545641 TP |
438 | /* Nonzero if chip supports Thumb 1. */ |
439 | extern int arm_arch_thumb1; | |
440 | ||
a27d8d80 JG |
441 | /* Nonzero if chip supports Thumb 2. */ |
442 | extern int arm_arch_thumb2; | |
443 | ||
444 | /* Nonzero if chip supports integer division instruction. */ | |
445 | extern int arm_arch_arm_hwdiv; | |
446 | extern int arm_arch_thumb_hwdiv; | |
447 | ||
afe006ad TG |
448 | /* Nonzero if chip disallows volatile memory access in IT block. */ |
449 | extern int arm_arch_no_volatile_ce; | |
450 | ||
a27d8d80 JG |
451 | /* Nonzero if we should use Neon to handle 64-bits operations rather |
452 | than core registers. */ | |
453 | extern int prefer_neon_for_64bits; | |
454 | ||
8341f8c4 RE |
455 | /* Structure defining the current overall architectural target and tuning. */ |
456 | struct arm_build_target | |
457 | { | |
458 | /* Name of the target CPU, if known, or NULL if the target CPU was not | |
459 | specified by the user (and inferred from the -march option). */ | |
460 | const char *core_name; | |
461 | /* Name of the target ARCH. NULL if there is a selected CPU. */ | |
462 | const char *arch_name; | |
463 | /* Preprocessor substring (never NULL). */ | |
464 | const char *arch_pp_name; | |
465 | /* CPU identifier for the core we're compiling for (architecturally). */ | |
466 | enum processor_type arch_core; | |
467 | /* The base architecture value. */ | |
468 | enum base_architecture base_arch; | |
469 | /* Bitmap encapsulating the isa_bits for the target environment. */ | |
470 | sbitmap isa; | |
471 | /* Flags used for tuning. Long term, these move into tune_params. */ | |
472 | unsigned int tune_flags; | |
473 | /* Tables with more detailed tuning information. */ | |
474 | const struct tune_params *tune; | |
475 | /* CPU identifier for the tuning target. */ | |
476 | enum processor_type tune_core; | |
477 | }; | |
478 | ||
479 | extern struct arm_build_target arm_active_target; | |
a27d8d80 JG |
480 | |
481 | ||
88657302 | 482 | #endif /* ! GCC_ARM_PROTOS_H */ |