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b36ba79f | 1 | /* Output routines for GCC for ARM. |
f954388e | 2 | Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, |
147a0bcf | 3 | 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011 |
b3a796bc | 4 | Free Software Foundation, Inc. |
cce8749e | 5 | Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl) |
956d6950 | 6 | and Martin Simmons (@harleqn.co.uk). |
b36ba79f | 7 | More major hacks by Richard Earnshaw (rearnsha@arm.com). |
cce8749e | 8 | |
4f448245 | 9 | This file is part of GCC. |
cce8749e | 10 | |
4f448245 NC |
11 | GCC is free software; you can redistribute it and/or modify it |
12 | under the terms of the GNU General Public License as published | |
2f83c7d6 | 13 | by the Free Software Foundation; either version 3, or (at your |
4f448245 | 14 | option) any later version. |
cce8749e | 15 | |
4f448245 NC |
16 | GCC is distributed in the hope that it will be useful, but WITHOUT |
17 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
18 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
19 | License for more details. | |
cce8749e | 20 | |
4f448245 | 21 | You should have received a copy of the GNU General Public License |
2f83c7d6 NC |
22 | along with GCC; see the file COPYING3. If not see |
23 | <http://www.gnu.org/licenses/>. */ | |
f676971a | 24 | |
56636818 | 25 | #include "config.h" |
43cffd11 | 26 | #include "system.h" |
4977bab6 ZW |
27 | #include "coretypes.h" |
28 | #include "tm.h" | |
cce8749e | 29 | #include "rtl.h" |
d5b7b3ae | 30 | #include "tree.h" |
c7319d87 | 31 | #include "obstack.h" |
cce8749e CH |
32 | #include "regs.h" |
33 | #include "hard-reg-set.h" | |
cce8749e CH |
34 | #include "insn-config.h" |
35 | #include "conditions.h" | |
cce8749e CH |
36 | #include "output.h" |
37 | #include "insn-attr.h" | |
38 | #include "flags.h" | |
af48348a | 39 | #include "reload.h" |
49ad7cfa | 40 | #include "function.h" |
bee06f3d | 41 | #include "expr.h" |
e78d8e51 | 42 | #include "optabs.h" |
718f9c0f | 43 | #include "diagnostic-core.h" |
aec3cfba | 44 | #include "recog.h" |
390b17c2 | 45 | #include "cgraph.h" |
92a432f4 | 46 | #include "ggc.h" |
d5b7b3ae | 47 | #include "except.h" |
39dabefd | 48 | #include "c-family/c-pragma.h" /* ??? */ |
7b8b8ade | 49 | #include "integrate.h" |
c27ba912 | 50 | #include "tm_p.h" |
672a6f42 NB |
51 | #include "target.h" |
52 | #include "target-def.h" | |
980e61bb | 53 | #include "debug.h" |
6e34d3a3 | 54 | #include "langhooks.h" |
6fb5fa3c | 55 | #include "df.h" |
0fd8c3ad | 56 | #include "intl.h" |
353a58f7 | 57 | #include "libfuncs.h" |
ec3728ad | 58 | #include "params.h" |
96e45421 | 59 | #include "opts.h" |
cce8749e | 60 | |
d5b7b3ae RE |
61 | /* Forward definitions of types. */ |
62 | typedef struct minipool_node Mnode; | |
63 | typedef struct minipool_fixup Mfix; | |
64 | ||
b76c3c4b PB |
65 | void (*arm_lang_output_object_attributes_hook)(void); |
66 | ||
d5b7b3ae | 67 | /* Forward function declarations. */ |
c2ed6cf8 | 68 | static bool arm_needs_doubleword_align (enum machine_mode, const_tree); |
35596784 | 69 | static int arm_compute_static_chain_stack_bytes (void); |
5848830f | 70 | static arm_stack_offsets *arm_get_frame_offsets (void); |
e32bac5b | 71 | static void arm_add_gc_roots (void); |
a406f566 MM |
72 | static int arm_gen_constant (enum rtx_code, enum machine_mode, rtx, |
73 | HOST_WIDE_INT, rtx, rtx, int, int); | |
e32bac5b RE |
74 | static unsigned bit_count (unsigned long); |
75 | static int arm_address_register_rtx_p (rtx, int); | |
1e1ab407 | 76 | static int arm_legitimate_index_p (enum machine_mode, rtx, RTX_CODE, int); |
5b3e6663 PB |
77 | static int thumb2_legitimate_index_p (enum machine_mode, rtx, int); |
78 | static int thumb1_base_register_rtx_p (rtx, enum machine_mode, int); | |
506d7b68 PB |
79 | static rtx arm_legitimize_address (rtx, rtx, enum machine_mode); |
80 | static rtx thumb_legitimize_address (rtx, rtx, enum machine_mode); | |
5b3e6663 | 81 | inline static int thumb1_index_register_rtx_p (rtx, int); |
c6c3dba9 | 82 | static bool arm_legitimate_address_p (enum machine_mode, rtx, bool); |
5848830f | 83 | static int thumb_far_jump_used_p (void); |
57934c39 | 84 | static bool thumb_force_lr_save (void); |
e32bac5b | 85 | static int const_ok_for_op (HOST_WIDE_INT, enum rtx_code); |
e32bac5b | 86 | static rtx emit_sfm (int, int); |
466e4b7a | 87 | static unsigned arm_size_return_regs (void); |
e32bac5b | 88 | static bool arm_assemble_integer (rtx, unsigned int, int); |
944442bb NF |
89 | static void arm_print_operand (FILE *, rtx, int); |
90 | static void arm_print_operand_address (FILE *, rtx); | |
91 | static bool arm_print_operand_punct_valid_p (unsigned char code); | |
e32bac5b RE |
92 | static const char *fp_const_from_val (REAL_VALUE_TYPE *); |
93 | static arm_cc get_arm_condition_code (rtx); | |
e32bac5b RE |
94 | static HOST_WIDE_INT int_log2 (HOST_WIDE_INT); |
95 | static rtx is_jump_table (rtx); | |
96 | static const char *output_multi_immediate (rtx *, const char *, const char *, | |
97 | int, HOST_WIDE_INT); | |
e32bac5b RE |
98 | static const char *shift_op (rtx, HOST_WIDE_INT *); |
99 | static struct machine_function *arm_init_machine_status (void); | |
c9ca9b88 | 100 | static void thumb_exit (FILE *, int); |
e32bac5b RE |
101 | static rtx is_jump_table (rtx); |
102 | static HOST_WIDE_INT get_jump_table_size (rtx); | |
103 | static Mnode *move_minipool_fix_forward_ref (Mnode *, Mnode *, HOST_WIDE_INT); | |
104 | static Mnode *add_minipool_forward_ref (Mfix *); | |
105 | static Mnode *move_minipool_fix_backward_ref (Mnode *, Mnode *, HOST_WIDE_INT); | |
106 | static Mnode *add_minipool_backward_ref (Mfix *); | |
107 | static void assign_minipool_offsets (Mfix *); | |
108 | static void arm_print_value (FILE *, rtx); | |
109 | static void dump_minipool (rtx); | |
110 | static int arm_barrier_cost (rtx); | |
111 | static Mfix *create_fix_barrier (Mfix *, HOST_WIDE_INT); | |
112 | static void push_minipool_barrier (rtx, HOST_WIDE_INT); | |
113 | static void push_minipool_fix (rtx, HOST_WIDE_INT, rtx *, enum machine_mode, | |
114 | rtx); | |
115 | static void arm_reorg (void); | |
116 | static bool note_invalid_constants (rtx, HOST_WIDE_INT, int); | |
e32bac5b RE |
117 | static unsigned long arm_compute_save_reg0_reg12_mask (void); |
118 | static unsigned long arm_compute_save_reg_mask (void); | |
119 | static unsigned long arm_isr_value (tree); | |
120 | static unsigned long arm_compute_func_type (void); | |
121 | static tree arm_handle_fndecl_attribute (tree *, tree, tree, int, bool *); | |
390b17c2 | 122 | static tree arm_handle_pcs_attribute (tree *, tree, tree, int, bool *); |
e32bac5b | 123 | static tree arm_handle_isr_attribute (tree *, tree, tree, int, bool *); |
7bff66a7 | 124 | #if TARGET_DLLIMPORT_DECL_ATTRIBUTES |
04fb56d5 | 125 | static tree arm_handle_notshared_attribute (tree *, tree, tree, int, bool *); |
7bff66a7 | 126 | #endif |
e32bac5b RE |
127 | static void arm_output_function_epilogue (FILE *, HOST_WIDE_INT); |
128 | static void arm_output_function_prologue (FILE *, HOST_WIDE_INT); | |
5b3e6663 | 129 | static void thumb1_output_function_prologue (FILE *, HOST_WIDE_INT); |
3101faab | 130 | static int arm_comp_type_attributes (const_tree, const_tree); |
e32bac5b RE |
131 | static void arm_set_default_type_attributes (tree); |
132 | static int arm_adjust_cost (rtx, rtx, rtx, int); | |
e32bac5b RE |
133 | static int count_insns_for_constant (HOST_WIDE_INT, int); |
134 | static int arm_get_strip_length (int); | |
135 | static bool arm_function_ok_for_sibcall (tree, tree); | |
390b17c2 RE |
136 | static enum machine_mode arm_promote_function_mode (const_tree, |
137 | enum machine_mode, int *, | |
138 | const_tree, int); | |
139 | static bool arm_return_in_memory (const_tree, const_tree); | |
140 | static rtx arm_function_value (const_tree, const_tree, bool); | |
7fc6a96b | 141 | static rtx arm_libcall_value (enum machine_mode, const_rtx); |
390b17c2 | 142 | |
e32bac5b RE |
143 | static void arm_internal_label (FILE *, const char *, unsigned long); |
144 | static void arm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, | |
145 | tree); | |
2929029c | 146 | static bool arm_have_conditional_execution (void); |
d5a0a47b RE |
147 | static bool arm_rtx_costs_1 (rtx, enum rtx_code, int*, bool); |
148 | static bool arm_size_rtx_costs (rtx, enum rtx_code, enum rtx_code, int *); | |
149 | static bool arm_slowmul_rtx_costs (rtx, enum rtx_code, enum rtx_code, int *, bool); | |
150 | static bool arm_fastmul_rtx_costs (rtx, enum rtx_code, enum rtx_code, int *, bool); | |
151 | static bool arm_xscale_rtx_costs (rtx, enum rtx_code, enum rtx_code, int *, bool); | |
152 | static bool arm_9e_rtx_costs (rtx, enum rtx_code, enum rtx_code, int *, bool); | |
f40751dd JH |
153 | static bool arm_rtx_costs (rtx, int, int, int *, bool); |
154 | static int arm_address_cost (rtx, bool); | |
e32bac5b RE |
155 | static bool arm_memory_load_p (rtx); |
156 | static bool arm_cirrus_insn_p (rtx); | |
157 | static void cirrus_reorg (rtx); | |
5a9335ef | 158 | static void arm_init_builtins (void); |
5a9335ef NC |
159 | static void arm_init_iwmmxt_builtins (void); |
160 | static rtx safe_vector_operand (rtx, enum machine_mode); | |
161 | static rtx arm_expand_binop_builtin (enum insn_code, tree, rtx); | |
162 | static rtx arm_expand_unop_builtin (enum insn_code, tree, rtx, int); | |
163 | static rtx arm_expand_builtin (tree, rtx, rtx, enum machine_mode, int); | |
a406f566 | 164 | static void emit_constant_insn (rtx cond, rtx pattern); |
d66437c5 | 165 | static rtx emit_set_insn (rtx, rtx); |
78a52f11 RH |
166 | static int arm_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode, |
167 | tree, bool); | |
9c6a2bee NF |
168 | static rtx arm_function_arg (CUMULATIVE_ARGS *, enum machine_mode, |
169 | const_tree, bool); | |
170 | static void arm_function_arg_advance (CUMULATIVE_ARGS *, enum machine_mode, | |
171 | const_tree, bool); | |
c2ed6cf8 | 172 | static unsigned int arm_function_arg_boundary (enum machine_mode, const_tree); |
390b17c2 RE |
173 | static rtx aapcs_allocate_return_reg (enum machine_mode, const_tree, |
174 | const_tree); | |
175 | static int aapcs_select_return_coproc (const_tree, const_tree); | |
5a9335ef | 176 | |
7abc66b1 | 177 | #ifdef OBJECT_FORMAT_ELF |
9403b7f7 RS |
178 | static void arm_elf_asm_constructor (rtx, int) ATTRIBUTE_UNUSED; |
179 | static void arm_elf_asm_destructor (rtx, int) ATTRIBUTE_UNUSED; | |
7abc66b1 | 180 | #endif |
fb49053f | 181 | #ifndef ARM_PE |
e32bac5b | 182 | static void arm_encode_section_info (tree, rtx, int); |
fb49053f | 183 | #endif |
b12a00f1 RE |
184 | |
185 | static void arm_file_end (void); | |
6c6aa1af | 186 | static void arm_file_start (void); |
b12a00f1 | 187 | |
1cc9f5f5 KH |
188 | static void arm_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode, |
189 | tree, int *, int); | |
8cd5a4e0 | 190 | static bool arm_pass_by_reference (CUMULATIVE_ARGS *, |
586de218 KG |
191 | enum machine_mode, const_tree, bool); |
192 | static bool arm_promote_prototypes (const_tree); | |
6b045785 | 193 | static bool arm_default_short_enums (void); |
13c1cd82 | 194 | static bool arm_align_anon_bitfield (void); |
586de218 KG |
195 | static bool arm_return_in_msb (const_tree); |
196 | static bool arm_must_pass_in_stack (enum machine_mode, const_tree); | |
23668cf7 | 197 | static bool arm_return_in_memory (const_tree, const_tree); |
f0a0390e | 198 | #if ARM_UNWIND_INFO |
617a1b71 PB |
199 | static void arm_unwind_emit (FILE *, rtx); |
200 | static bool arm_output_ttype (rtx); | |
a68b5e52 RH |
201 | static void arm_asm_emit_except_personality (rtx); |
202 | static void arm_asm_init_sections (void); | |
617a1b71 | 203 | #endif |
d5fabb58 | 204 | static enum unwind_info_type arm_except_unwind_info (struct gcc_options *); |
5b3e6663 | 205 | static void arm_dwarf_handle_frame_unspec (const char *, rtx, int); |
854b8a40 | 206 | static rtx arm_dwarf_register_span (rtx); |
c237e94a | 207 | |
4185ae53 PB |
208 | static tree arm_cxx_guard_type (void); |
209 | static bool arm_cxx_guard_mask_bit (void); | |
46e995e0 PB |
210 | static tree arm_get_cookie_size (tree); |
211 | static bool arm_cookie_has_size (void); | |
44d10c10 | 212 | static bool arm_cxx_cdtor_returns_this (void); |
505970fc | 213 | static bool arm_cxx_key_method_may_be_inline (void); |
1e731102 MM |
214 | static void arm_cxx_determine_class_data_visibility (tree); |
215 | static bool arm_cxx_class_data_always_comdat (void); | |
9f62c3e3 | 216 | static bool arm_cxx_use_aeabi_atexit (void); |
b3f8d95d | 217 | static void arm_init_libfuncs (void); |
07d8efe3 MM |
218 | static tree arm_build_builtin_va_list (void); |
219 | static void arm_expand_builtin_va_start (tree, rtx); | |
ae46a823 | 220 | static tree arm_gimplify_va_arg_expr (tree, tree, gimple_seq *, gimple_seq *); |
c5387660 | 221 | static void arm_option_override (void); |
96e45421 JM |
222 | static bool arm_handle_option (struct gcc_options *, struct gcc_options *, |
223 | const struct cl_decoded_option *, location_t); | |
67e6ba46 | 224 | static void arm_target_help (void); |
273a2526 | 225 | static unsigned HOST_WIDE_INT arm_shift_truncation_mask (enum machine_mode); |
d3585b76 DJ |
226 | static bool arm_cannot_copy_insn_p (rtx); |
227 | static bool arm_tls_symbol_p (rtx x); | |
bd4dc3cd | 228 | static int arm_issue_rate (void); |
afcc986d | 229 | static void arm_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED; |
ffda8a0d | 230 | static bool arm_output_addr_const_extra (FILE *, rtx); |
007e61c2 | 231 | static bool arm_allocate_stack_slots_for_args (void); |
0fd8c3ad SL |
232 | static const char *arm_invalid_parameter_type (const_tree t); |
233 | static const char *arm_invalid_return_type (const_tree t); | |
234 | static tree arm_promoted_type (const_tree t); | |
235 | static tree arm_convert_to_type (tree type, tree expr); | |
bdc4827b | 236 | static bool arm_scalar_mode_supported_p (enum machine_mode); |
b52b1749 | 237 | static bool arm_frame_pointer_required (void); |
7b5cbb57 | 238 | static bool arm_can_eliminate (const int, const int); |
0ef9304b RH |
239 | static void arm_asm_trampoline_template (FILE *); |
240 | static void arm_trampoline_init (rtx, tree, rtx); | |
241 | static rtx arm_trampoline_adjust_address (rtx); | |
85c9bcd4 | 242 | static rtx arm_pic_static_addr (rtx orig, rtx reg); |
b0c13111 RR |
243 | static bool cortex_a9_sched_adjust_cost (rtx, rtx, rtx, int *); |
244 | static bool xscale_sched_adjust_cost (rtx, rtx, rtx, int *); | |
c02a5ccb | 245 | static bool fa726te_sched_adjust_cost (rtx, rtx, rtx, int *); |
cc4b5170 | 246 | static enum machine_mode arm_preferred_simd_mode (enum machine_mode); |
d163e655 | 247 | static bool arm_class_likely_spilled_p (reg_class_t); |
c452684d JB |
248 | static bool arm_vector_alignment_reachable (const_tree type, bool is_packed); |
249 | static bool arm_builtin_support_vector_misalignment (enum machine_mode mode, | |
250 | const_tree type, | |
251 | int misalignment, | |
252 | bool is_packed); | |
5efd84c5 | 253 | static void arm_conditional_register_usage (void); |
6d3fbe2f | 254 | static reg_class_t arm_preferred_rename_class (reg_class_t rclass); |
b52b1749 | 255 | |
5a82ecd9 ILT |
256 | \f |
257 | /* Table of machine attributes. */ | |
258 | static const struct attribute_spec arm_attribute_table[] = | |
259 | { | |
62d784f7 KT |
260 | /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler, |
261 | affects_type_identity } */ | |
5a82ecd9 ILT |
262 | /* Function calls made to this symbol must be done indirectly, because |
263 | it may lie outside of the 26 bit addressing range of a normal function | |
264 | call. */ | |
62d784f7 | 265 | { "long_call", 0, 0, false, true, true, NULL, false }, |
5a82ecd9 ILT |
266 | /* Whereas these functions are always known to reside within the 26 bit |
267 | addressing range. */ | |
62d784f7 | 268 | { "short_call", 0, 0, false, true, true, NULL, false }, |
390b17c2 | 269 | /* Specify the procedure call conventions for a function. */ |
62d784f7 KT |
270 | { "pcs", 1, 1, false, true, true, arm_handle_pcs_attribute, |
271 | false }, | |
5a82ecd9 | 272 | /* Interrupt Service Routines have special prologue and epilogue requirements. */ |
62d784f7 KT |
273 | { "isr", 0, 1, false, false, false, arm_handle_isr_attribute, |
274 | false }, | |
275 | { "interrupt", 0, 1, false, false, false, arm_handle_isr_attribute, | |
276 | false }, | |
277 | { "naked", 0, 0, true, false, false, arm_handle_fndecl_attribute, | |
278 | false }, | |
5a82ecd9 ILT |
279 | #ifdef ARM_PE |
280 | /* ARM/PE has three new attributes: | |
281 | interfacearm - ? | |
282 | dllexport - for exporting a function/variable that will live in a dll | |
283 | dllimport - for importing a function/variable from a dll | |
d3585b76 | 284 | |
5a82ecd9 ILT |
285 | Microsoft allows multiple declspecs in one __declspec, separating |
286 | them with spaces. We do NOT support this. Instead, use __declspec | |
287 | multiple times. | |
288 | */ | |
62d784f7 KT |
289 | { "dllimport", 0, 0, true, false, false, NULL, false }, |
290 | { "dllexport", 0, 0, true, false, false, NULL, false }, | |
291 | { "interfacearm", 0, 0, true, false, false, arm_handle_fndecl_attribute, | |
292 | false }, | |
5a82ecd9 | 293 | #elif TARGET_DLLIMPORT_DECL_ATTRIBUTES |
62d784f7 KT |
294 | { "dllimport", 0, 0, false, false, false, handle_dll_attribute, false }, |
295 | { "dllexport", 0, 0, false, false, false, handle_dll_attribute, false }, | |
296 | { "notshared", 0, 0, false, true, false, arm_handle_notshared_attribute, | |
297 | false }, | |
5a82ecd9 | 298 | #endif |
62d784f7 | 299 | { NULL, 0, 0, false, false, false, NULL, false } |
5a82ecd9 | 300 | }; |
3020190e JM |
301 | |
302 | /* Set default optimization options. */ | |
303 | static const struct default_options arm_option_optimization_table[] = | |
304 | { | |
305 | /* Enable section anchors by default at -O1 or higher. */ | |
306 | { OPT_LEVELS_1_PLUS, OPT_fsection_anchors, NULL, 1 }, | |
307 | { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 }, | |
308 | { OPT_LEVELS_NONE, 0, NULL, 0 } | |
309 | }; | |
672a6f42 NB |
310 | \f |
311 | /* Initialize the GCC target structure. */ | |
b2ca3702 | 312 | #if TARGET_DLLIMPORT_DECL_ATTRIBUTES |
1d6e90ac | 313 | #undef TARGET_MERGE_DECL_ATTRIBUTES |
672a6f42 NB |
314 | #define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes |
315 | #endif | |
f3bb6135 | 316 | |
506d7b68 PB |
317 | #undef TARGET_LEGITIMIZE_ADDRESS |
318 | #define TARGET_LEGITIMIZE_ADDRESS arm_legitimize_address | |
319 | ||
1d6e90ac | 320 | #undef TARGET_ATTRIBUTE_TABLE |
91d231cb | 321 | #define TARGET_ATTRIBUTE_TABLE arm_attribute_table |
672a6f42 | 322 | |
6c6aa1af PB |
323 | #undef TARGET_ASM_FILE_START |
324 | #define TARGET_ASM_FILE_START arm_file_start | |
b12a00f1 RE |
325 | #undef TARGET_ASM_FILE_END |
326 | #define TARGET_ASM_FILE_END arm_file_end | |
327 | ||
1d6e90ac | 328 | #undef TARGET_ASM_ALIGNED_SI_OP |
301d03af | 329 | #define TARGET_ASM_ALIGNED_SI_OP NULL |
1d6e90ac | 330 | #undef TARGET_ASM_INTEGER |
301d03af | 331 | #define TARGET_ASM_INTEGER arm_assemble_integer |
301d03af | 332 | |
944442bb NF |
333 | #undef TARGET_PRINT_OPERAND |
334 | #define TARGET_PRINT_OPERAND arm_print_operand | |
335 | #undef TARGET_PRINT_OPERAND_ADDRESS | |
336 | #define TARGET_PRINT_OPERAND_ADDRESS arm_print_operand_address | |
337 | #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P | |
338 | #define TARGET_PRINT_OPERAND_PUNCT_VALID_P arm_print_operand_punct_valid_p | |
339 | ||
ffda8a0d AS |
340 | #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA |
341 | #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA arm_output_addr_const_extra | |
342 | ||
1d6e90ac | 343 | #undef TARGET_ASM_FUNCTION_PROLOGUE |
08c148a8 NB |
344 | #define TARGET_ASM_FUNCTION_PROLOGUE arm_output_function_prologue |
345 | ||
1d6e90ac | 346 | #undef TARGET_ASM_FUNCTION_EPILOGUE |
08c148a8 NB |
347 | #define TARGET_ASM_FUNCTION_EPILOGUE arm_output_function_epilogue |
348 | ||
c54c7322 RS |
349 | #undef TARGET_DEFAULT_TARGET_FLAGS |
350 | #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | MASK_SCHED_PROLOG) | |
351 | #undef TARGET_HANDLE_OPTION | |
352 | #define TARGET_HANDLE_OPTION arm_handle_option | |
67e6ba46 NC |
353 | #undef TARGET_HELP |
354 | #define TARGET_HELP arm_target_help | |
c5387660 JM |
355 | #undef TARGET_OPTION_OVERRIDE |
356 | #define TARGET_OPTION_OVERRIDE arm_option_override | |
3020190e JM |
357 | #undef TARGET_OPTION_OPTIMIZATION_TABLE |
358 | #define TARGET_OPTION_OPTIMIZATION_TABLE arm_option_optimization_table | |
c54c7322 | 359 | |
1d6e90ac | 360 | #undef TARGET_COMP_TYPE_ATTRIBUTES |
8d8e52be JM |
361 | #define TARGET_COMP_TYPE_ATTRIBUTES arm_comp_type_attributes |
362 | ||
1d6e90ac | 363 | #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES |
8d8e52be JM |
364 | #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES arm_set_default_type_attributes |
365 | ||
1d6e90ac | 366 | #undef TARGET_SCHED_ADJUST_COST |
c237e94a ZW |
367 | #define TARGET_SCHED_ADJUST_COST arm_adjust_cost |
368 | ||
fb49053f RH |
369 | #undef TARGET_ENCODE_SECTION_INFO |
370 | #ifdef ARM_PE | |
371 | #define TARGET_ENCODE_SECTION_INFO arm_pe_encode_section_info | |
372 | #else | |
373 | #define TARGET_ENCODE_SECTION_INFO arm_encode_section_info | |
374 | #endif | |
375 | ||
5a9335ef | 376 | #undef TARGET_STRIP_NAME_ENCODING |
772c5265 RH |
377 | #define TARGET_STRIP_NAME_ENCODING arm_strip_name_encoding |
378 | ||
5a9335ef | 379 | #undef TARGET_ASM_INTERNAL_LABEL |
4977bab6 ZW |
380 | #define TARGET_ASM_INTERNAL_LABEL arm_internal_label |
381 | ||
5a9335ef | 382 | #undef TARGET_FUNCTION_OK_FOR_SIBCALL |
4977bab6 ZW |
383 | #define TARGET_FUNCTION_OK_FOR_SIBCALL arm_function_ok_for_sibcall |
384 | ||
390b17c2 RE |
385 | #undef TARGET_FUNCTION_VALUE |
386 | #define TARGET_FUNCTION_VALUE arm_function_value | |
387 | ||
388 | #undef TARGET_LIBCALL_VALUE | |
389 | #define TARGET_LIBCALL_VALUE arm_libcall_value | |
390 | ||
5a9335ef | 391 | #undef TARGET_ASM_OUTPUT_MI_THUNK |
c590b625 | 392 | #define TARGET_ASM_OUTPUT_MI_THUNK arm_output_mi_thunk |
5a9335ef | 393 | #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK |
3961e8fe | 394 | #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall |
c590b625 | 395 | |
5a9335ef | 396 | #undef TARGET_RTX_COSTS |
f40751dd | 397 | #define TARGET_RTX_COSTS arm_rtx_costs |
5a9335ef | 398 | #undef TARGET_ADDRESS_COST |
dcefdf67 | 399 | #define TARGET_ADDRESS_COST arm_address_cost |
3c50106f | 400 | |
273a2526 RS |
401 | #undef TARGET_SHIFT_TRUNCATION_MASK |
402 | #define TARGET_SHIFT_TRUNCATION_MASK arm_shift_truncation_mask | |
f676971a EC |
403 | #undef TARGET_VECTOR_MODE_SUPPORTED_P |
404 | #define TARGET_VECTOR_MODE_SUPPORTED_P arm_vector_mode_supported_p | |
cc4b5170 RG |
405 | #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE |
406 | #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE arm_preferred_simd_mode | |
f676971a | 407 | |
5a9335ef | 408 | #undef TARGET_MACHINE_DEPENDENT_REORG |
18dbd950 RS |
409 | #define TARGET_MACHINE_DEPENDENT_REORG arm_reorg |
410 | ||
5a9335ef NC |
411 | #undef TARGET_INIT_BUILTINS |
412 | #define TARGET_INIT_BUILTINS arm_init_builtins | |
413 | #undef TARGET_EXPAND_BUILTIN | |
414 | #define TARGET_EXPAND_BUILTIN arm_expand_builtin | |
415 | ||
b3f8d95d MM |
416 | #undef TARGET_INIT_LIBFUNCS |
417 | #define TARGET_INIT_LIBFUNCS arm_init_libfuncs | |
418 | ||
cde0f3fd PB |
419 | #undef TARGET_PROMOTE_FUNCTION_MODE |
420 | #define TARGET_PROMOTE_FUNCTION_MODE arm_promote_function_mode | |
f9ba5949 | 421 | #undef TARGET_PROMOTE_PROTOTYPES |
70301b45 | 422 | #define TARGET_PROMOTE_PROTOTYPES arm_promote_prototypes |
8cd5a4e0 RH |
423 | #undef TARGET_PASS_BY_REFERENCE |
424 | #define TARGET_PASS_BY_REFERENCE arm_pass_by_reference | |
78a52f11 RH |
425 | #undef TARGET_ARG_PARTIAL_BYTES |
426 | #define TARGET_ARG_PARTIAL_BYTES arm_arg_partial_bytes | |
9c6a2bee NF |
427 | #undef TARGET_FUNCTION_ARG |
428 | #define TARGET_FUNCTION_ARG arm_function_arg | |
429 | #undef TARGET_FUNCTION_ARG_ADVANCE | |
430 | #define TARGET_FUNCTION_ARG_ADVANCE arm_function_arg_advance | |
c2ed6cf8 NF |
431 | #undef TARGET_FUNCTION_ARG_BOUNDARY |
432 | #define TARGET_FUNCTION_ARG_BOUNDARY arm_function_arg_boundary | |
f9ba5949 | 433 | |
1cc9f5f5 KH |
434 | #undef TARGET_SETUP_INCOMING_VARARGS |
435 | #define TARGET_SETUP_INCOMING_VARARGS arm_setup_incoming_varargs | |
436 | ||
007e61c2 PB |
437 | #undef TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS |
438 | #define TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS arm_allocate_stack_slots_for_args | |
439 | ||
0ef9304b RH |
440 | #undef TARGET_ASM_TRAMPOLINE_TEMPLATE |
441 | #define TARGET_ASM_TRAMPOLINE_TEMPLATE arm_asm_trampoline_template | |
442 | #undef TARGET_TRAMPOLINE_INIT | |
443 | #define TARGET_TRAMPOLINE_INIT arm_trampoline_init | |
444 | #undef TARGET_TRAMPOLINE_ADJUST_ADDRESS | |
445 | #define TARGET_TRAMPOLINE_ADJUST_ADDRESS arm_trampoline_adjust_address | |
446 | ||
6b045785 PB |
447 | #undef TARGET_DEFAULT_SHORT_ENUMS |
448 | #define TARGET_DEFAULT_SHORT_ENUMS arm_default_short_enums | |
449 | ||
13c1cd82 PB |
450 | #undef TARGET_ALIGN_ANON_BITFIELD |
451 | #define TARGET_ALIGN_ANON_BITFIELD arm_align_anon_bitfield | |
452 | ||
c2a64439 PB |
453 | #undef TARGET_NARROW_VOLATILE_BITFIELD |
454 | #define TARGET_NARROW_VOLATILE_BITFIELD hook_bool_void_false | |
455 | ||
4185ae53 PB |
456 | #undef TARGET_CXX_GUARD_TYPE |
457 | #define TARGET_CXX_GUARD_TYPE arm_cxx_guard_type | |
458 | ||
459 | #undef TARGET_CXX_GUARD_MASK_BIT | |
460 | #define TARGET_CXX_GUARD_MASK_BIT arm_cxx_guard_mask_bit | |
461 | ||
46e995e0 PB |
462 | #undef TARGET_CXX_GET_COOKIE_SIZE |
463 | #define TARGET_CXX_GET_COOKIE_SIZE arm_get_cookie_size | |
464 | ||
465 | #undef TARGET_CXX_COOKIE_HAS_SIZE | |
466 | #define TARGET_CXX_COOKIE_HAS_SIZE arm_cookie_has_size | |
467 | ||
44d10c10 PB |
468 | #undef TARGET_CXX_CDTOR_RETURNS_THIS |
469 | #define TARGET_CXX_CDTOR_RETURNS_THIS arm_cxx_cdtor_returns_this | |
470 | ||
505970fc MM |
471 | #undef TARGET_CXX_KEY_METHOD_MAY_BE_INLINE |
472 | #define TARGET_CXX_KEY_METHOD_MAY_BE_INLINE arm_cxx_key_method_may_be_inline | |
473 | ||
9f62c3e3 PB |
474 | #undef TARGET_CXX_USE_AEABI_ATEXIT |
475 | #define TARGET_CXX_USE_AEABI_ATEXIT arm_cxx_use_aeabi_atexit | |
476 | ||
1e731102 MM |
477 | #undef TARGET_CXX_DETERMINE_CLASS_DATA_VISIBILITY |
478 | #define TARGET_CXX_DETERMINE_CLASS_DATA_VISIBILITY \ | |
479 | arm_cxx_determine_class_data_visibility | |
480 | ||
481 | #undef TARGET_CXX_CLASS_DATA_ALWAYS_COMDAT | |
482 | #define TARGET_CXX_CLASS_DATA_ALWAYS_COMDAT arm_cxx_class_data_always_comdat | |
505970fc | 483 | |
866af8a9 JB |
484 | #undef TARGET_RETURN_IN_MSB |
485 | #define TARGET_RETURN_IN_MSB arm_return_in_msb | |
486 | ||
23668cf7 CLT |
487 | #undef TARGET_RETURN_IN_MEMORY |
488 | #define TARGET_RETURN_IN_MEMORY arm_return_in_memory | |
489 | ||
866af8a9 JB |
490 | #undef TARGET_MUST_PASS_IN_STACK |
491 | #define TARGET_MUST_PASS_IN_STACK arm_must_pass_in_stack | |
492 | ||
f0a0390e | 493 | #if ARM_UNWIND_INFO |
38f8b050 JR |
494 | #undef TARGET_ASM_UNWIND_EMIT |
495 | #define TARGET_ASM_UNWIND_EMIT arm_unwind_emit | |
617a1b71 PB |
496 | |
497 | /* EABI unwinding tables use a different format for the typeinfo tables. */ | |
498 | #undef TARGET_ASM_TTYPE | |
499 | #define TARGET_ASM_TTYPE arm_output_ttype | |
500 | ||
501 | #undef TARGET_ARM_EABI_UNWINDER | |
502 | #define TARGET_ARM_EABI_UNWINDER true | |
a68b5e52 RH |
503 | |
504 | #undef TARGET_ASM_EMIT_EXCEPT_PERSONALITY | |
505 | #define TARGET_ASM_EMIT_EXCEPT_PERSONALITY arm_asm_emit_except_personality | |
506 | ||
507 | #undef TARGET_ASM_INIT_SECTIONS | |
508 | #define TARGET_ASM_INIT_SECTIONS arm_asm_init_sections | |
f0a0390e RH |
509 | #endif /* ARM_UNWIND_INFO */ |
510 | ||
511 | #undef TARGET_EXCEPT_UNWIND_INFO | |
512 | #define TARGET_EXCEPT_UNWIND_INFO arm_except_unwind_info | |
617a1b71 | 513 | |
5b3e6663 PB |
514 | #undef TARGET_DWARF_HANDLE_FRAME_UNSPEC |
515 | #define TARGET_DWARF_HANDLE_FRAME_UNSPEC arm_dwarf_handle_frame_unspec | |
516 | ||
854b8a40 JB |
517 | #undef TARGET_DWARF_REGISTER_SPAN |
518 | #define TARGET_DWARF_REGISTER_SPAN arm_dwarf_register_span | |
519 | ||
d3585b76 DJ |
520 | #undef TARGET_CANNOT_COPY_INSN_P |
521 | #define TARGET_CANNOT_COPY_INSN_P arm_cannot_copy_insn_p | |
522 | ||
523 | #ifdef HAVE_AS_TLS | |
524 | #undef TARGET_HAVE_TLS | |
525 | #define TARGET_HAVE_TLS true | |
526 | #endif | |
527 | ||
2929029c WG |
528 | #undef TARGET_HAVE_CONDITIONAL_EXECUTION |
529 | #define TARGET_HAVE_CONDITIONAL_EXECUTION arm_have_conditional_execution | |
530 | ||
d3585b76 | 531 | #undef TARGET_CANNOT_FORCE_CONST_MEM |
8426b956 | 532 | #define TARGET_CANNOT_FORCE_CONST_MEM arm_cannot_force_const_mem |
d3585b76 | 533 | |
f67358da PB |
534 | #undef TARGET_MAX_ANCHOR_OFFSET |
535 | #define TARGET_MAX_ANCHOR_OFFSET 4095 | |
536 | ||
537 | /* The minimum is set such that the total size of the block | |
538 | for a particular anchor is -4088 + 1 + 4095 bytes, which is | |
539 | divisible by eight, ensuring natural spacing of anchors. */ | |
540 | #undef TARGET_MIN_ANCHOR_OFFSET | |
541 | #define TARGET_MIN_ANCHOR_OFFSET -4088 | |
542 | ||
bd4dc3cd PB |
543 | #undef TARGET_SCHED_ISSUE_RATE |
544 | #define TARGET_SCHED_ISSUE_RATE arm_issue_rate | |
545 | ||
608063c3 JB |
546 | #undef TARGET_MANGLE_TYPE |
547 | #define TARGET_MANGLE_TYPE arm_mangle_type | |
548 | ||
07d8efe3 MM |
549 | #undef TARGET_BUILD_BUILTIN_VA_LIST |
550 | #define TARGET_BUILD_BUILTIN_VA_LIST arm_build_builtin_va_list | |
551 | #undef TARGET_EXPAND_BUILTIN_VA_START | |
552 | #define TARGET_EXPAND_BUILTIN_VA_START arm_expand_builtin_va_start | |
553 | #undef TARGET_GIMPLIFY_VA_ARG_EXPR | |
554 | #define TARGET_GIMPLIFY_VA_ARG_EXPR arm_gimplify_va_arg_expr | |
555 | ||
afcc986d JM |
556 | #ifdef HAVE_AS_TLS |
557 | #undef TARGET_ASM_OUTPUT_DWARF_DTPREL | |
558 | #define TARGET_ASM_OUTPUT_DWARF_DTPREL arm_output_dwarf_dtprel | |
559 | #endif | |
560 | ||
c6c3dba9 PB |
561 | #undef TARGET_LEGITIMATE_ADDRESS_P |
562 | #define TARGET_LEGITIMATE_ADDRESS_P arm_legitimate_address_p | |
563 | ||
0fd8c3ad SL |
564 | #undef TARGET_INVALID_PARAMETER_TYPE |
565 | #define TARGET_INVALID_PARAMETER_TYPE arm_invalid_parameter_type | |
566 | ||
567 | #undef TARGET_INVALID_RETURN_TYPE | |
568 | #define TARGET_INVALID_RETURN_TYPE arm_invalid_return_type | |
569 | ||
570 | #undef TARGET_PROMOTED_TYPE | |
571 | #define TARGET_PROMOTED_TYPE arm_promoted_type | |
572 | ||
573 | #undef TARGET_CONVERT_TO_TYPE | |
574 | #define TARGET_CONVERT_TO_TYPE arm_convert_to_type | |
575 | ||
bdc4827b SL |
576 | #undef TARGET_SCALAR_MODE_SUPPORTED_P |
577 | #define TARGET_SCALAR_MODE_SUPPORTED_P arm_scalar_mode_supported_p | |
578 | ||
b52b1749 AS |
579 | #undef TARGET_FRAME_POINTER_REQUIRED |
580 | #define TARGET_FRAME_POINTER_REQUIRED arm_frame_pointer_required | |
581 | ||
7b5cbb57 AS |
582 | #undef TARGET_CAN_ELIMINATE |
583 | #define TARGET_CAN_ELIMINATE arm_can_eliminate | |
584 | ||
5efd84c5 NF |
585 | #undef TARGET_CONDITIONAL_REGISTER_USAGE |
586 | #define TARGET_CONDITIONAL_REGISTER_USAGE arm_conditional_register_usage | |
587 | ||
d163e655 AS |
588 | #undef TARGET_CLASS_LIKELY_SPILLED_P |
589 | #define TARGET_CLASS_LIKELY_SPILLED_P arm_class_likely_spilled_p | |
590 | ||
c452684d JB |
591 | #undef TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE |
592 | #define TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE \ | |
593 | arm_vector_alignment_reachable | |
594 | ||
595 | #undef TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT | |
596 | #define TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT \ | |
597 | arm_builtin_support_vector_misalignment | |
598 | ||
74e32076 YQ |
599 | #undef TARGET_PREFERRED_RENAME_CLASS |
600 | #define TARGET_PREFERRED_RENAME_CLASS \ | |
601 | arm_preferred_rename_class | |
602 | ||
f6897b10 | 603 | struct gcc_target targetm = TARGET_INITIALIZER; |
672a6f42 | 604 | \f |
c7319d87 RE |
605 | /* Obstack for minipool constant handling. */ |
606 | static struct obstack minipool_obstack; | |
1d6e90ac | 607 | static char * minipool_startobj; |
c7319d87 | 608 | |
1d6e90ac NC |
609 | /* The maximum number of insns skipped which |
610 | will be conditionalised if possible. */ | |
c27ba912 DM |
611 | static int max_insns_skipped = 5; |
612 | ||
613 | extern FILE * asm_out_file; | |
614 | ||
6354dc9b | 615 | /* True if we are currently building a constant table. */ |
13bd191d PB |
616 | int making_const_table; |
617 | ||
9b66ebb1 PB |
618 | /* The processor for which instructions should be scheduled. */ |
619 | enum processor_type arm_tune = arm_none; | |
620 | ||
1b78f575 RE |
621 | /* The current tuning set. */ |
622 | const struct tune_params *current_tune; | |
623 | ||
9b66ebb1 | 624 | /* Which floating point hardware to schedule for. */ |
d79f3032 PB |
625 | int arm_fpu_attr; |
626 | ||
627 | /* Which floating popint hardware to use. */ | |
628 | const struct arm_fpu_desc *arm_fpu_desc; | |
9b66ebb1 PB |
629 | |
630 | /* Whether to use floating point hardware. */ | |
631 | enum float_abi_type arm_float_abi; | |
632 | ||
0fd8c3ad SL |
633 | /* Which __fp16 format to use. */ |
634 | enum arm_fp16_format_type arm_fp16_format; | |
635 | ||
5848830f PB |
636 | /* Which ABI to use. */ |
637 | enum arm_abi_type arm_abi; | |
638 | ||
d3585b76 DJ |
639 | /* Which thread pointer model to use. */ |
640 | enum arm_tp_type target_thread_pointer = TP_AUTO; | |
641 | ||
b355a481 | 642 | /* Used to parse -mstructure_size_boundary command line option. */ |
723ae7c1 | 643 | int arm_structure_size_boundary = DEFAULT_STRUCTURE_SIZE_BOUNDARY; |
b355a481 | 644 | |
b12a00f1 | 645 | /* Used for Thumb call_via trampolines. */ |
57ecec57 | 646 | rtx thumb_call_via_label[14]; |
b12a00f1 RE |
647 | static int thumb_call_reg_needed; |
648 | ||
aec3cfba | 649 | /* Bit values used to identify processor capabilities. */ |
62b10bbc | 650 | #define FL_CO_PROC (1 << 0) /* Has external co-processor bus */ |
9b66ebb1 | 651 | #define FL_ARCH3M (1 << 1) /* Extended multiply */ |
62b10bbc NC |
652 | #define FL_MODE26 (1 << 2) /* 26-bit mode support */ |
653 | #define FL_MODE32 (1 << 3) /* 32-bit mode support */ | |
654 | #define FL_ARCH4 (1 << 4) /* Architecture rel 4 */ | |
655 | #define FL_ARCH5 (1 << 5) /* Architecture rel 5 */ | |
656 | #define FL_THUMB (1 << 6) /* Thumb aware */ | |
657 | #define FL_LDSCHED (1 << 7) /* Load scheduling necessary */ | |
658 | #define FL_STRONG (1 << 8) /* StrongARM */ | |
6bc82793 | 659 | #define FL_ARCH5E (1 << 9) /* DSP extensions to v5 */ |
d19fb8e3 | 660 | #define FL_XSCALE (1 << 10) /* XScale */ |
9b6b54e2 | 661 | #define FL_CIRRUS (1 << 11) /* Cirrus/DSP. */ |
9b66ebb1 | 662 | #define FL_ARCH6 (1 << 12) /* Architecture rel 6. Adds |
81f9037c MM |
663 | media instructions. */ |
664 | #define FL_VFPV2 (1 << 13) /* Vector Floating Point V2. */ | |
abac3b49 RE |
665 | #define FL_WBUF (1 << 14) /* Schedule for write buffer ops. |
666 | Note: ARM6 & 7 derivatives only. */ | |
d3585b76 | 667 | #define FL_ARCH6K (1 << 15) /* Architecture rel 6 K extensions. */ |
5b3e6663 PB |
668 | #define FL_THUMB2 (1 << 16) /* Thumb-2. */ |
669 | #define FL_NOTM (1 << 17) /* Instructions not present in the 'M' | |
670 | profile. */ | |
7a085dce | 671 | #define FL_DIV (1 << 18) /* Hardware divide. */ |
f1adb0a9 | 672 | #define FL_VFPV3 (1 << 19) /* Vector Floating Point V3. */ |
88f77cba | 673 | #define FL_NEON (1 << 20) /* Neon instructions. */ |
60bd3528 PB |
674 | #define FL_ARCH7EM (1 << 21) /* Instructions present in the ARMv7E-M |
675 | architecture. */ | |
029e79eb | 676 | #define FL_ARCH7 (1 << 22) /* Architecture 7. */ |
aec3cfba | 677 | |
9b66ebb1 PB |
678 | #define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */ |
679 | ||
12a0a4d4 PB |
680 | /* Flags that only effect tuning, not available instructions. */ |
681 | #define FL_TUNE (FL_WBUF | FL_VFPV2 | FL_STRONG | FL_LDSCHED \ | |
682 | | FL_CO_PROC) | |
683 | ||
5b3e6663 PB |
684 | #define FL_FOR_ARCH2 FL_NOTM |
685 | #define FL_FOR_ARCH3 (FL_FOR_ARCH2 | FL_MODE32) | |
78011587 PB |
686 | #define FL_FOR_ARCH3M (FL_FOR_ARCH3 | FL_ARCH3M) |
687 | #define FL_FOR_ARCH4 (FL_FOR_ARCH3M | FL_ARCH4) | |
688 | #define FL_FOR_ARCH4T (FL_FOR_ARCH4 | FL_THUMB) | |
689 | #define FL_FOR_ARCH5 (FL_FOR_ARCH4 | FL_ARCH5) | |
690 | #define FL_FOR_ARCH5T (FL_FOR_ARCH5 | FL_THUMB) | |
691 | #define FL_FOR_ARCH5E (FL_FOR_ARCH5 | FL_ARCH5E) | |
692 | #define FL_FOR_ARCH5TE (FL_FOR_ARCH5E | FL_THUMB) | |
693 | #define FL_FOR_ARCH5TEJ FL_FOR_ARCH5TE | |
694 | #define FL_FOR_ARCH6 (FL_FOR_ARCH5TE | FL_ARCH6) | |
695 | #define FL_FOR_ARCH6J FL_FOR_ARCH6 | |
d3585b76 | 696 | #define FL_FOR_ARCH6K (FL_FOR_ARCH6 | FL_ARCH6K) |
fa91adc6 | 697 | #define FL_FOR_ARCH6Z FL_FOR_ARCH6 |
d3585b76 | 698 | #define FL_FOR_ARCH6ZK FL_FOR_ARCH6K |
5b3e6663 | 699 | #define FL_FOR_ARCH6T2 (FL_FOR_ARCH6 | FL_THUMB2) |
bf98ec6c | 700 | #define FL_FOR_ARCH6M (FL_FOR_ARCH6 & ~FL_NOTM) |
029e79eb | 701 | #define FL_FOR_ARCH7 ((FL_FOR_ARCH6T2 & ~FL_NOTM) | FL_ARCH7) |
87d05b44 | 702 | #define FL_FOR_ARCH7A (FL_FOR_ARCH7 | FL_NOTM | FL_ARCH6K) |
5b3e6663 PB |
703 | #define FL_FOR_ARCH7R (FL_FOR_ARCH7A | FL_DIV) |
704 | #define FL_FOR_ARCH7M (FL_FOR_ARCH7 | FL_DIV) | |
60bd3528 | 705 | #define FL_FOR_ARCH7EM (FL_FOR_ARCH7M | FL_ARCH7EM) |
78011587 | 706 | |
1d6e90ac NC |
707 | /* The bits in this mask specify which |
708 | instructions we are allowed to generate. */ | |
0977774b | 709 | static unsigned long insn_flags = 0; |
d5b7b3ae | 710 | |
aec3cfba | 711 | /* The bits in this mask specify which instruction scheduling options should |
9b66ebb1 | 712 | be used. */ |
0977774b | 713 | static unsigned long tune_flags = 0; |
aec3cfba NC |
714 | |
715 | /* The following are used in the arm.md file as equivalents to bits | |
716 | in the above two flag variables. */ | |
717 | ||
9b66ebb1 PB |
718 | /* Nonzero if this chip supports the ARM Architecture 3M extensions. */ |
719 | int arm_arch3m = 0; | |
2b835d68 | 720 | |
6354dc9b | 721 | /* Nonzero if this chip supports the ARM Architecture 4 extensions. */ |
2b835d68 RE |
722 | int arm_arch4 = 0; |
723 | ||
68d560d4 RE |
724 | /* Nonzero if this chip supports the ARM Architecture 4t extensions. */ |
725 | int arm_arch4t = 0; | |
726 | ||
6354dc9b | 727 | /* Nonzero if this chip supports the ARM Architecture 5 extensions. */ |
62b10bbc NC |
728 | int arm_arch5 = 0; |
729 | ||
b15bca31 RE |
730 | /* Nonzero if this chip supports the ARM Architecture 5E extensions. */ |
731 | int arm_arch5e = 0; | |
732 | ||
9b66ebb1 PB |
733 | /* Nonzero if this chip supports the ARM Architecture 6 extensions. */ |
734 | int arm_arch6 = 0; | |
735 | ||
d3585b76 DJ |
736 | /* Nonzero if this chip supports the ARM 6K extensions. */ |
737 | int arm_arch6k = 0; | |
738 | ||
029e79eb MS |
739 | /* Nonzero if this chip supports the ARM 7 extensions. */ |
740 | int arm_arch7 = 0; | |
741 | ||
5b3e6663 PB |
742 | /* Nonzero if instructions not present in the 'M' profile can be used. */ |
743 | int arm_arch_notm = 0; | |
744 | ||
60bd3528 PB |
745 | /* Nonzero if instructions present in ARMv7E-M can be used. */ |
746 | int arm_arch7em = 0; | |
747 | ||
aec3cfba | 748 | /* Nonzero if this chip can benefit from load scheduling. */ |
f5a1b0d2 NC |
749 | int arm_ld_sched = 0; |
750 | ||
751 | /* Nonzero if this chip is a StrongARM. */ | |
abac3b49 | 752 | int arm_tune_strongarm = 0; |
f5a1b0d2 | 753 | |
78011587 PB |
754 | /* Nonzero if this chip is a Cirrus variant. */ |
755 | int arm_arch_cirrus = 0; | |
756 | ||
5a9335ef NC |
757 | /* Nonzero if this chip supports Intel Wireless MMX technology. */ |
758 | int arm_arch_iwmmxt = 0; | |
759 | ||
d19fb8e3 | 760 | /* Nonzero if this chip is an XScale. */ |
4b3c2e48 PB |
761 | int arm_arch_xscale = 0; |
762 | ||
763 | /* Nonzero if tuning for XScale */ | |
764 | int arm_tune_xscale = 0; | |
d19fb8e3 | 765 | |
e0b92319 | 766 | /* Nonzero if we want to tune for stores that access the write-buffer. |
c5d34bb2 | 767 | This typically means an ARM6 or ARM7 with MMU or MPU. */ |
abac3b49 | 768 | int arm_tune_wbuf = 0; |
b111229a | 769 | |
7612f14d PB |
770 | /* Nonzero if tuning for Cortex-A9. */ |
771 | int arm_tune_cortex_a9 = 0; | |
772 | ||
0616531f RE |
773 | /* Nonzero if generating Thumb instructions. */ |
774 | int thumb_code = 0; | |
775 | ||
906668bb BS |
776 | /* Nonzero if generating Thumb-1 instructions. */ |
777 | int thumb1_code = 0; | |
778 | ||
2ad4dcf9 | 779 | /* Nonzero if we should define __THUMB_INTERWORK__ in the |
f676971a | 780 | preprocessor. |
2ad4dcf9 RE |
781 | XXX This is a bit of a hack, it's intended to help work around |
782 | problems in GLD which doesn't understand that armv5t code is | |
783 | interworking clean. */ | |
784 | int arm_cpp_interwork = 0; | |
785 | ||
5b3e6663 PB |
786 | /* Nonzero if chip supports Thumb 2. */ |
787 | int arm_arch_thumb2; | |
788 | ||
789 | /* Nonzero if chip supports integer division instruction. */ | |
790 | int arm_arch_hwdiv; | |
791 | ||
944442bb NF |
792 | /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, |
793 | we must report the mode of the memory reference from | |
794 | TARGET_PRINT_OPERAND to TARGET_PRINT_OPERAND_ADDRESS. */ | |
f3bb6135 | 795 | enum machine_mode output_memory_reference_mode; |
cce8749e | 796 | |
32de079a | 797 | /* The register number to be used for the PIC offset register. */ |
020a4035 | 798 | unsigned arm_pic_register = INVALID_REGNUM; |
32de079a | 799 | |
aec3cfba NC |
800 | /* Set to 1 after arm_reorg has started. Reset to start at the start of |
801 | the next function. */ | |
4b632bf1 RE |
802 | static int after_arm_reorg = 0; |
803 | ||
12ffc7d5 | 804 | enum arm_pcs arm_pcs_default; |
390b17c2 | 805 | |
cce8749e CH |
806 | /* For an explanation of these variables, see final_prescan_insn below. */ |
807 | int arm_ccfsm_state; | |
5b3e6663 | 808 | /* arm_current_cc is also used for Thumb-2 cond_exec blocks. */ |
84ed5e79 | 809 | enum arm_cond_code arm_current_cc; |
906668bb | 810 | |
cce8749e CH |
811 | rtx arm_target_insn; |
812 | int arm_target_label; | |
5b3e6663 PB |
813 | /* The number of conditionally executed insns, including the current insn. */ |
814 | int arm_condexec_count = 0; | |
815 | /* A bitmask specifying the patterns for the IT block. | |
816 | Zero means do not output an IT block before this insn. */ | |
817 | int arm_condexec_mask = 0; | |
818 | /* The number of bits used in arm_condexec_mask. */ | |
819 | int arm_condexec_masklen = 0; | |
9997d19d RE |
820 | |
821 | /* The condition codes of the ARM, and the inverse function. */ | |
1d6e90ac | 822 | static const char * const arm_condition_codes[] = |
9997d19d RE |
823 | { |
824 | "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc", | |
825 | "hi", "ls", "ge", "lt", "gt", "le", "al", "nv" | |
826 | }; | |
827 | ||
37119410 BS |
828 | /* The register numbers in sequence, for passing to arm_gen_load_multiple. */ |
829 | int arm_regs_in_sequence[] = | |
830 | { | |
831 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 | |
832 | }; | |
833 | ||
5b3e6663 | 834 | #define ARM_LSL_NAME (TARGET_UNIFIED_ASM ? "lsl" : "asl") |
f5a1b0d2 | 835 | #define streq(string1, string2) (strcmp (string1, string2) == 0) |
5b3e6663 PB |
836 | |
837 | #define THUMB2_WORK_REGS (0xff & ~( (1 << THUMB_HARD_FRAME_POINTER_REGNUM) \ | |
838 | | (1 << SP_REGNUM) | (1 << PC_REGNUM) \ | |
839 | | (1 << PIC_OFFSET_TABLE_REGNUM))) | |
2b835d68 | 840 | \f |
6354dc9b | 841 | /* Initialization code. */ |
2b835d68 | 842 | |
2b835d68 RE |
843 | struct processors |
844 | { | |
8b60264b | 845 | const char *const name; |
9b66ebb1 | 846 | enum processor_type core; |
78011587 | 847 | const char *arch; |
0977774b | 848 | const unsigned long flags; |
1b78f575 RE |
849 | const struct tune_params *const tune; |
850 | }; | |
851 | ||
911de8a3 IB |
852 | |
853 | #define ARM_PREFETCH_NOT_BENEFICIAL 0, -1, -1 | |
854 | #define ARM_PREFETCH_BENEFICIAL(prefetch_slots,l1_size,l1_line_size) \ | |
855 | prefetch_slots, \ | |
856 | l1_size, \ | |
857 | l1_line_size | |
858 | ||
1b78f575 RE |
859 | const struct tune_params arm_slowmul_tune = |
860 | { | |
861 | arm_slowmul_rtx_costs, | |
b0c13111 | 862 | NULL, |
911de8a3 IB |
863 | 3, |
864 | ARM_PREFETCH_NOT_BENEFICIAL | |
1b78f575 RE |
865 | }; |
866 | ||
867 | const struct tune_params arm_fastmul_tune = | |
868 | { | |
869 | arm_fastmul_rtx_costs, | |
b0c13111 | 870 | NULL, |
911de8a3 IB |
871 | 1, |
872 | ARM_PREFETCH_NOT_BENEFICIAL | |
1b78f575 RE |
873 | }; |
874 | ||
875 | const struct tune_params arm_xscale_tune = | |
876 | { | |
877 | arm_xscale_rtx_costs, | |
b0c13111 | 878 | xscale_sched_adjust_cost, |
911de8a3 IB |
879 | 2, |
880 | ARM_PREFETCH_NOT_BENEFICIAL | |
1b78f575 RE |
881 | }; |
882 | ||
883 | const struct tune_params arm_9e_tune = | |
884 | { | |
885 | arm_9e_rtx_costs, | |
b0c13111 | 886 | NULL, |
911de8a3 IB |
887 | 1, |
888 | ARM_PREFETCH_NOT_BENEFICIAL | |
2b835d68 RE |
889 | }; |
890 | ||
b0c13111 RR |
891 | const struct tune_params arm_cortex_a9_tune = |
892 | { | |
893 | arm_9e_rtx_costs, | |
894 | cortex_a9_sched_adjust_cost, | |
911de8a3 IB |
895 | 1, |
896 | ARM_PREFETCH_BENEFICIAL(4,32,32) | |
b0c13111 RR |
897 | }; |
898 | ||
c02a5ccb SL |
899 | const struct tune_params arm_fa726te_tune = |
900 | { | |
901 | arm_9e_rtx_costs, | |
902 | fa726te_sched_adjust_cost, | |
903 | 1, | |
904 | ARM_PREFETCH_NOT_BENEFICIAL | |
905 | }; | |
906 | ||
b0c13111 | 907 | |
2b835d68 RE |
908 | /* Not all of these give usefully different compilation alternatives, |
909 | but there is no simple way of generalizing them. */ | |
8b60264b | 910 | static const struct processors all_cores[] = |
f5a1b0d2 NC |
911 | { |
912 | /* ARM Cores */ | |
d98a72fd | 913 | #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \ |
12a0a4d4 | 914 | {NAME, IDENT, #ARCH, FLAGS | FL_FOR_ARCH##ARCH, &arm_##COSTS##_tune}, |
9b66ebb1 PB |
915 | #include "arm-cores.def" |
916 | #undef ARM_CORE | |
78011587 | 917 | {NULL, arm_none, NULL, 0, NULL} |
f5a1b0d2 NC |
918 | }; |
919 | ||
8b60264b | 920 | static const struct processors all_architectures[] = |
2b835d68 | 921 | { |
f5a1b0d2 | 922 | /* ARM Architectures */ |
1b78f575 | 923 | /* We don't specify tuning costs here as it will be figured out |
9b66ebb1 | 924 | from the core. */ |
f676971a | 925 | |
78011587 PB |
926 | {"armv2", arm2, "2", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2, NULL}, |
927 | {"armv2a", arm2, "2", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2, NULL}, | |
928 | {"armv3", arm6, "3", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3, NULL}, | |
929 | {"armv3m", arm7m, "3M", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3M, NULL}, | |
930 | {"armv4", arm7tdmi, "4", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH4, NULL}, | |
b111229a RE |
931 | /* Strictly, FL_MODE26 is a permitted option for v4t, but there are no |
932 | implementations that support it, so we will leave it out for now. */ | |
78011587 PB |
933 | {"armv4t", arm7tdmi, "4T", FL_CO_PROC | FL_FOR_ARCH4T, NULL}, |
934 | {"armv5", arm10tdmi, "5", FL_CO_PROC | FL_FOR_ARCH5, NULL}, | |
935 | {"armv5t", arm10tdmi, "5T", FL_CO_PROC | FL_FOR_ARCH5T, NULL}, | |
936 | {"armv5e", arm1026ejs, "5E", FL_CO_PROC | FL_FOR_ARCH5E, NULL}, | |
937 | {"armv5te", arm1026ejs, "5TE", FL_CO_PROC | FL_FOR_ARCH5TE, NULL}, | |
938 | {"armv6", arm1136js, "6", FL_CO_PROC | FL_FOR_ARCH6, NULL}, | |
939 | {"armv6j", arm1136js, "6J", FL_CO_PROC | FL_FOR_ARCH6J, NULL}, | |
fa91adc6 PB |
940 | {"armv6k", mpcore, "6K", FL_CO_PROC | FL_FOR_ARCH6K, NULL}, |
941 | {"armv6z", arm1176jzs, "6Z", FL_CO_PROC | FL_FOR_ARCH6Z, NULL}, | |
942 | {"armv6zk", arm1176jzs, "6ZK", FL_CO_PROC | FL_FOR_ARCH6ZK, NULL}, | |
5b3e6663 | 943 | {"armv6t2", arm1156t2s, "6T2", FL_CO_PROC | FL_FOR_ARCH6T2, NULL}, |
bf98ec6c | 944 | {"armv6-m", cortexm1, "6M", FL_FOR_ARCH6M, NULL}, |
5b3e6663 PB |
945 | {"armv7", cortexa8, "7", FL_CO_PROC | FL_FOR_ARCH7, NULL}, |
946 | {"armv7-a", cortexa8, "7A", FL_CO_PROC | FL_FOR_ARCH7A, NULL}, | |
947 | {"armv7-r", cortexr4, "7R", FL_CO_PROC | FL_FOR_ARCH7R, NULL}, | |
948 | {"armv7-m", cortexm3, "7M", FL_CO_PROC | FL_FOR_ARCH7M, NULL}, | |
f6e47b26 | 949 | {"armv7e-m", cortexm4, "7EM", FL_CO_PROC | FL_FOR_ARCH7EM, NULL}, |
78011587 PB |
950 | {"ep9312", ep9312, "4T", FL_LDSCHED | FL_CIRRUS | FL_FOR_ARCH4, NULL}, |
951 | {"iwmmxt", iwmmxt, "5TE", FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT , NULL}, | |
442dc742 | 952 | {"iwmmxt2", iwmmxt2, "5TE", FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT , NULL}, |
78011587 | 953 | {NULL, arm_none, NULL, 0 , NULL} |
f5a1b0d2 NC |
954 | }; |
955 | ||
f5a1b0d2 | 956 | |
12a0a4d4 PB |
957 | /* These are populated as commandline arguments are processed, or NULL |
958 | if not specified. */ | |
959 | static const struct processors *arm_selected_arch; | |
960 | static const struct processors *arm_selected_cpu; | |
961 | static const struct processors *arm_selected_tune; | |
78011587 | 962 | |
afc0a4ba | 963 | /* The name of the preprocessor macro to define for this architecture. */ |
78011587 PB |
964 | |
965 | char arm_arch_name[] = "__ARM_ARCH_0UNK__"; | |
966 | ||
56f42830 | 967 | /* Available values for -mfpu=. */ |
9b66ebb1 | 968 | |
d79f3032 PB |
969 | static const struct arm_fpu_desc all_fpus[] = |
970 | { | |
70dd156a RN |
971 | {"fpa", ARM_FP_MODEL_FPA, 0, VFP_NONE, false, false}, |
972 | {"fpe2", ARM_FP_MODEL_FPA, 2, VFP_NONE, false, false}, | |
973 | {"fpe3", ARM_FP_MODEL_FPA, 3, VFP_NONE, false, false}, | |
974 | {"maverick", ARM_FP_MODEL_MAVERICK, 0, VFP_NONE, false, false}, | |
d79f3032 PB |
975 | {"vfp", ARM_FP_MODEL_VFP, 2, VFP_REG_D16, false, false}, |
976 | {"vfpv3", ARM_FP_MODEL_VFP, 3, VFP_REG_D32, false, false}, | |
e0dc3601 | 977 | {"vfpv3-fp16", ARM_FP_MODEL_VFP, 3, VFP_REG_D32, false, true}, |
d79f3032 | 978 | {"vfpv3-d16", ARM_FP_MODEL_VFP, 3, VFP_REG_D16, false, false}, |
e0dc3601 PB |
979 | {"vfpv3-d16-fp16", ARM_FP_MODEL_VFP, 3, VFP_REG_D16, false, true}, |
980 | {"vfpv3xd", ARM_FP_MODEL_VFP, 3, VFP_REG_SINGLE, false, false}, | |
981 | {"vfpv3xd-fp16", ARM_FP_MODEL_VFP, 3, VFP_REG_SINGLE, false, true}, | |
d79f3032 PB |
982 | {"neon", ARM_FP_MODEL_VFP, 3, VFP_REG_D32, true , false}, |
983 | {"neon-fp16", ARM_FP_MODEL_VFP, 3, VFP_REG_D32, true , true }, | |
6ed126e6 PB |
984 | {"vfpv4", ARM_FP_MODEL_VFP, 4, VFP_REG_D32, false, true}, |
985 | {"vfpv4-d16", ARM_FP_MODEL_VFP, 4, VFP_REG_D16, false, true}, | |
1abed66b | 986 | {"fpv4-sp-d16", ARM_FP_MODEL_VFP, 4, VFP_REG_SINGLE, false, true}, |
6ed126e6 | 987 | {"neon-vfpv4", ARM_FP_MODEL_VFP, 4, VFP_REG_D32, true, true}, |
d79f3032 PB |
988 | /* Compatibility aliases. */ |
989 | {"vfp3", ARM_FP_MODEL_VFP, 3, VFP_REG_D32, false, false}, | |
9b66ebb1 PB |
990 | }; |
991 | ||
992 | ||
993 | struct float_abi | |
994 | { | |
995 | const char * name; | |
996 | enum float_abi_type abi_type; | |
997 | }; | |
998 | ||
999 | ||
1000 | /* Available values for -mfloat-abi=. */ | |
1001 | ||
1002 | static const struct float_abi all_float_abis[] = | |
1003 | { | |
1004 | {"soft", ARM_FLOAT_ABI_SOFT}, | |
1005 | {"softfp", ARM_FLOAT_ABI_SOFTFP}, | |
1006 | {"hard", ARM_FLOAT_ABI_HARD} | |
1007 | }; | |
1008 | ||
1009 | ||
0fd8c3ad SL |
1010 | struct fp16_format |
1011 | { | |
1012 | const char *name; | |
1013 | enum arm_fp16_format_type fp16_format_type; | |
1014 | }; | |
1015 | ||
1016 | ||
1017 | /* Available values for -mfp16-format=. */ | |
1018 | ||
1019 | static const struct fp16_format all_fp16_formats[] = | |
1020 | { | |
1021 | {"none", ARM_FP16_FORMAT_NONE}, | |
1022 | {"ieee", ARM_FP16_FORMAT_IEEE}, | |
1023 | {"alternative", ARM_FP16_FORMAT_ALTERNATIVE} | |
1024 | }; | |
1025 | ||
1026 | ||
5848830f PB |
1027 | struct abi_name |
1028 | { | |
1029 | const char *name; | |
1030 | enum arm_abi_type abi_type; | |
1031 | }; | |
1032 | ||
1033 | ||
1034 | /* Available values for -mabi=. */ | |
1035 | ||
1036 | static const struct abi_name arm_all_abis[] = | |
1037 | { | |
1038 | {"apcs-gnu", ARM_ABI_APCS}, | |
1039 | {"atpcs", ARM_ABI_ATPCS}, | |
1040 | {"aapcs", ARM_ABI_AAPCS}, | |
077fc835 KH |
1041 | {"iwmmxt", ARM_ABI_IWMMXT}, |
1042 | {"aapcs-linux", ARM_ABI_AAPCS_LINUX} | |
5848830f PB |
1043 | }; |
1044 | ||
d3585b76 DJ |
1045 | /* Supported TLS relocations. */ |
1046 | ||
1047 | enum tls_reloc { | |
1048 | TLS_GD32, | |
1049 | TLS_LDM32, | |
1050 | TLS_LDO32, | |
1051 | TLS_IE32, | |
1052 | TLS_LE32 | |
1053 | }; | |
1054 | ||
1b78f575 RE |
1055 | /* The maximum number of insns to be used when loading a constant. */ |
1056 | inline static int | |
1057 | arm_constant_limit (bool size_p) | |
1058 | { | |
1059 | return size_p ? 1 : current_tune->constant_limit; | |
1060 | } | |
1061 | ||
d66437c5 RE |
1062 | /* Emit an insn that's a simple single-set. Both the operands must be known |
1063 | to be valid. */ | |
1064 | inline static rtx | |
1065 | emit_set_insn (rtx x, rtx y) | |
1066 | { | |
1067 | return emit_insn (gen_rtx_SET (VOIDmode, x, y)); | |
1068 | } | |
1069 | ||
0977774b JT |
1070 | /* Return the number of bits set in VALUE. */ |
1071 | static unsigned | |
e32bac5b | 1072 | bit_count (unsigned long value) |
aec3cfba | 1073 | { |
d5b7b3ae | 1074 | unsigned long count = 0; |
f676971a | 1075 | |
aec3cfba NC |
1076 | while (value) |
1077 | { | |
0977774b JT |
1078 | count++; |
1079 | value &= value - 1; /* Clear the least-significant set bit. */ | |
aec3cfba NC |
1080 | } |
1081 | ||
1082 | return count; | |
1083 | } | |
1084 | ||
c112cf2b | 1085 | /* Set up library functions unique to ARM. */ |
b3f8d95d MM |
1086 | |
1087 | static void | |
1088 | arm_init_libfuncs (void) | |
1089 | { | |
1090 | /* There are no special library functions unless we are using the | |
1091 | ARM BPABI. */ | |
1092 | if (!TARGET_BPABI) | |
1093 | return; | |
1094 | ||
1095 | /* The functions below are described in Section 4 of the "Run-Time | |
1096 | ABI for the ARM architecture", Version 1.0. */ | |
1097 | ||
1098 | /* Double-precision floating-point arithmetic. Table 2. */ | |
1099 | set_optab_libfunc (add_optab, DFmode, "__aeabi_dadd"); | |
1100 | set_optab_libfunc (sdiv_optab, DFmode, "__aeabi_ddiv"); | |
1101 | set_optab_libfunc (smul_optab, DFmode, "__aeabi_dmul"); | |
1102 | set_optab_libfunc (neg_optab, DFmode, "__aeabi_dneg"); | |
1103 | set_optab_libfunc (sub_optab, DFmode, "__aeabi_dsub"); | |
1104 | ||
c112cf2b | 1105 | /* Double-precision comparisons. Table 3. */ |
b3f8d95d MM |
1106 | set_optab_libfunc (eq_optab, DFmode, "__aeabi_dcmpeq"); |
1107 | set_optab_libfunc (ne_optab, DFmode, NULL); | |
1108 | set_optab_libfunc (lt_optab, DFmode, "__aeabi_dcmplt"); | |
1109 | set_optab_libfunc (le_optab, DFmode, "__aeabi_dcmple"); | |
1110 | set_optab_libfunc (ge_optab, DFmode, "__aeabi_dcmpge"); | |
1111 | set_optab_libfunc (gt_optab, DFmode, "__aeabi_dcmpgt"); | |
1112 | set_optab_libfunc (unord_optab, DFmode, "__aeabi_dcmpun"); | |
1113 | ||
1114 | /* Single-precision floating-point arithmetic. Table 4. */ | |
1115 | set_optab_libfunc (add_optab, SFmode, "__aeabi_fadd"); | |
1116 | set_optab_libfunc (sdiv_optab, SFmode, "__aeabi_fdiv"); | |
1117 | set_optab_libfunc (smul_optab, SFmode, "__aeabi_fmul"); | |
1118 | set_optab_libfunc (neg_optab, SFmode, "__aeabi_fneg"); | |
1119 | set_optab_libfunc (sub_optab, SFmode, "__aeabi_fsub"); | |
f676971a | 1120 | |
c112cf2b | 1121 | /* Single-precision comparisons. Table 5. */ |
b3f8d95d MM |
1122 | set_optab_libfunc (eq_optab, SFmode, "__aeabi_fcmpeq"); |
1123 | set_optab_libfunc (ne_optab, SFmode, NULL); | |
1124 | set_optab_libfunc (lt_optab, SFmode, "__aeabi_fcmplt"); | |
1125 | set_optab_libfunc (le_optab, SFmode, "__aeabi_fcmple"); | |
1126 | set_optab_libfunc (ge_optab, SFmode, "__aeabi_fcmpge"); | |
1127 | set_optab_libfunc (gt_optab, SFmode, "__aeabi_fcmpgt"); | |
1128 | set_optab_libfunc (unord_optab, SFmode, "__aeabi_fcmpun"); | |
1129 | ||
1130 | /* Floating-point to integer conversions. Table 6. */ | |
1131 | set_conv_libfunc (sfix_optab, SImode, DFmode, "__aeabi_d2iz"); | |
1132 | set_conv_libfunc (ufix_optab, SImode, DFmode, "__aeabi_d2uiz"); | |
1133 | set_conv_libfunc (sfix_optab, DImode, DFmode, "__aeabi_d2lz"); | |
1134 | set_conv_libfunc (ufix_optab, DImode, DFmode, "__aeabi_d2ulz"); | |
1135 | set_conv_libfunc (sfix_optab, SImode, SFmode, "__aeabi_f2iz"); | |
1136 | set_conv_libfunc (ufix_optab, SImode, SFmode, "__aeabi_f2uiz"); | |
1137 | set_conv_libfunc (sfix_optab, DImode, SFmode, "__aeabi_f2lz"); | |
1138 | set_conv_libfunc (ufix_optab, DImode, SFmode, "__aeabi_f2ulz"); | |
1139 | ||
1140 | /* Conversions between floating types. Table 7. */ | |
1141 | set_conv_libfunc (trunc_optab, SFmode, DFmode, "__aeabi_d2f"); | |
1142 | set_conv_libfunc (sext_optab, DFmode, SFmode, "__aeabi_f2d"); | |
1143 | ||
c112cf2b | 1144 | /* Integer to floating-point conversions. Table 8. */ |
b3f8d95d MM |
1145 | set_conv_libfunc (sfloat_optab, DFmode, SImode, "__aeabi_i2d"); |
1146 | set_conv_libfunc (ufloat_optab, DFmode, SImode, "__aeabi_ui2d"); | |
1147 | set_conv_libfunc (sfloat_optab, DFmode, DImode, "__aeabi_l2d"); | |
1148 | set_conv_libfunc (ufloat_optab, DFmode, DImode, "__aeabi_ul2d"); | |
1149 | set_conv_libfunc (sfloat_optab, SFmode, SImode, "__aeabi_i2f"); | |
1150 | set_conv_libfunc (ufloat_optab, SFmode, SImode, "__aeabi_ui2f"); | |
1151 | set_conv_libfunc (sfloat_optab, SFmode, DImode, "__aeabi_l2f"); | |
1152 | set_conv_libfunc (ufloat_optab, SFmode, DImode, "__aeabi_ul2f"); | |
1153 | ||
1154 | /* Long long. Table 9. */ | |
1155 | set_optab_libfunc (smul_optab, DImode, "__aeabi_lmul"); | |
1156 | set_optab_libfunc (sdivmod_optab, DImode, "__aeabi_ldivmod"); | |
1157 | set_optab_libfunc (udivmod_optab, DImode, "__aeabi_uldivmod"); | |
1158 | set_optab_libfunc (ashl_optab, DImode, "__aeabi_llsl"); | |
1159 | set_optab_libfunc (lshr_optab, DImode, "__aeabi_llsr"); | |
1160 | set_optab_libfunc (ashr_optab, DImode, "__aeabi_lasr"); | |
1161 | set_optab_libfunc (cmp_optab, DImode, "__aeabi_lcmp"); | |
1162 | set_optab_libfunc (ucmp_optab, DImode, "__aeabi_ulcmp"); | |
1163 | ||
1164 | /* Integer (32/32->32) division. \S 4.3.1. */ | |
1165 | set_optab_libfunc (sdivmod_optab, SImode, "__aeabi_idivmod"); | |
1166 | set_optab_libfunc (udivmod_optab, SImode, "__aeabi_uidivmod"); | |
1167 | ||
1168 | /* The divmod functions are designed so that they can be used for | |
1169 | plain division, even though they return both the quotient and the | |
1170 | remainder. The quotient is returned in the usual location (i.e., | |
1171 | r0 for SImode, {r0, r1} for DImode), just as would be expected | |
1172 | for an ordinary division routine. Because the AAPCS calling | |
1173 | conventions specify that all of { r0, r1, r2, r3 } are | |
1174 | callee-saved registers, there is no need to tell the compiler | |
1175 | explicitly that those registers are clobbered by these | |
1176 | routines. */ | |
1177 | set_optab_libfunc (sdiv_optab, DImode, "__aeabi_ldivmod"); | |
1178 | set_optab_libfunc (udiv_optab, DImode, "__aeabi_uldivmod"); | |
e993ba8f DJ |
1179 | |
1180 | /* For SImode division the ABI provides div-without-mod routines, | |
1181 | which are faster. */ | |
1182 | set_optab_libfunc (sdiv_optab, SImode, "__aeabi_idiv"); | |
1183 | set_optab_libfunc (udiv_optab, SImode, "__aeabi_uidiv"); | |
01c19d47 PB |
1184 | |
1185 | /* We don't have mod libcalls. Fortunately gcc knows how to use the | |
1186 | divmod libcalls instead. */ | |
1187 | set_optab_libfunc (smod_optab, DImode, NULL); | |
1188 | set_optab_libfunc (umod_optab, DImode, NULL); | |
1189 | set_optab_libfunc (smod_optab, SImode, NULL); | |
1190 | set_optab_libfunc (umod_optab, SImode, NULL); | |
0fd8c3ad SL |
1191 | |
1192 | /* Half-precision float operations. The compiler handles all operations | |
1193 | with NULL libfuncs by converting the SFmode. */ | |
1194 | switch (arm_fp16_format) | |
1195 | { | |
1196 | case ARM_FP16_FORMAT_IEEE: | |
1197 | case ARM_FP16_FORMAT_ALTERNATIVE: | |
1198 | ||
1199 | /* Conversions. */ | |
1200 | set_conv_libfunc (trunc_optab, HFmode, SFmode, | |
1201 | (arm_fp16_format == ARM_FP16_FORMAT_IEEE | |
1202 | ? "__gnu_f2h_ieee" | |
1203 | : "__gnu_f2h_alternative")); | |
1204 | set_conv_libfunc (sext_optab, SFmode, HFmode, | |
1205 | (arm_fp16_format == ARM_FP16_FORMAT_IEEE | |
1206 | ? "__gnu_h2f_ieee" | |
1207 | : "__gnu_h2f_alternative")); | |
1208 | ||
1209 | /* Arithmetic. */ | |
1210 | set_optab_libfunc (add_optab, HFmode, NULL); | |
1211 | set_optab_libfunc (sdiv_optab, HFmode, NULL); | |
1212 | set_optab_libfunc (smul_optab, HFmode, NULL); | |
1213 | set_optab_libfunc (neg_optab, HFmode, NULL); | |
1214 | set_optab_libfunc (sub_optab, HFmode, NULL); | |
1215 | ||
1216 | /* Comparisons. */ | |
1217 | set_optab_libfunc (eq_optab, HFmode, NULL); | |
1218 | set_optab_libfunc (ne_optab, HFmode, NULL); | |
1219 | set_optab_libfunc (lt_optab, HFmode, NULL); | |
1220 | set_optab_libfunc (le_optab, HFmode, NULL); | |
1221 | set_optab_libfunc (ge_optab, HFmode, NULL); | |
1222 | set_optab_libfunc (gt_optab, HFmode, NULL); | |
1223 | set_optab_libfunc (unord_optab, HFmode, NULL); | |
1224 | break; | |
1225 | ||
1226 | default: | |
1227 | break; | |
1228 | } | |
353a58f7 AH |
1229 | |
1230 | if (TARGET_AAPCS_BASED) | |
1231 | synchronize_libfunc = init_one_libfunc ("__sync_synchronize"); | |
b3f8d95d MM |
1232 | } |
1233 | ||
07d8efe3 MM |
1234 | /* On AAPCS systems, this is the "struct __va_list". */ |
1235 | static GTY(()) tree va_list_type; | |
1236 | ||
1237 | /* Return the type to use as __builtin_va_list. */ | |
1238 | static tree | |
1239 | arm_build_builtin_va_list (void) | |
1240 | { | |
1241 | tree va_list_name; | |
1242 | tree ap_field; | |
1243 | ||
1244 | if (!TARGET_AAPCS_BASED) | |
1245 | return std_build_builtin_va_list (); | |
1246 | ||
1247 | /* AAPCS \S 7.1.4 requires that va_list be a typedef for a type | |
1248 | defined as: | |
1249 | ||
1250 | struct __va_list | |
1251 | { | |
1252 | void *__ap; | |
1253 | }; | |
1254 | ||
1255 | The C Library ABI further reinforces this definition in \S | |
1256 | 4.1. | |
1257 | ||
1258 | We must follow this definition exactly. The structure tag | |
1259 | name is visible in C++ mangled names, and thus forms a part | |
1260 | of the ABI. The field name may be used by people who | |
1261 | #include <stdarg.h>. */ | |
1262 | /* Create the type. */ | |
1263 | va_list_type = lang_hooks.types.make_type (RECORD_TYPE); | |
1264 | /* Give it the required name. */ | |
4c4bde29 AH |
1265 | va_list_name = build_decl (BUILTINS_LOCATION, |
1266 | TYPE_DECL, | |
07d8efe3 MM |
1267 | get_identifier ("__va_list"), |
1268 | va_list_type); | |
1269 | DECL_ARTIFICIAL (va_list_name) = 1; | |
1270 | TYPE_NAME (va_list_type) = va_list_name; | |
56f01f0b | 1271 | TYPE_STUB_DECL (va_list_type) = va_list_name; |
07d8efe3 | 1272 | /* Create the __ap field. */ |
4c4bde29 AH |
1273 | ap_field = build_decl (BUILTINS_LOCATION, |
1274 | FIELD_DECL, | |
07d8efe3 MM |
1275 | get_identifier ("__ap"), |
1276 | ptr_type_node); | |
1277 | DECL_ARTIFICIAL (ap_field) = 1; | |
1278 | DECL_FIELD_CONTEXT (ap_field) = va_list_type; | |
1279 | TYPE_FIELDS (va_list_type) = ap_field; | |
1280 | /* Compute its layout. */ | |
1281 | layout_type (va_list_type); | |
1282 | ||
1283 | return va_list_type; | |
1284 | } | |
1285 | ||
1286 | /* Return an expression of type "void *" pointing to the next | |
1287 | available argument in a variable-argument list. VALIST is the | |
1288 | user-level va_list object, of type __builtin_va_list. */ | |
1289 | static tree | |
1290 | arm_extract_valist_ptr (tree valist) | |
1291 | { | |
1292 | if (TREE_TYPE (valist) == error_mark_node) | |
1293 | return error_mark_node; | |
1294 | ||
1295 | /* On an AAPCS target, the pointer is stored within "struct | |
1296 | va_list". */ | |
1297 | if (TARGET_AAPCS_BASED) | |
1298 | { | |
1299 | tree ap_field = TYPE_FIELDS (TREE_TYPE (valist)); | |
1300 | valist = build3 (COMPONENT_REF, TREE_TYPE (ap_field), | |
1301 | valist, ap_field, NULL_TREE); | |
1302 | } | |
1303 | ||
1304 | return valist; | |
1305 | } | |
1306 | ||
1307 | /* Implement TARGET_EXPAND_BUILTIN_VA_START. */ | |
1308 | static void | |
1309 | arm_expand_builtin_va_start (tree valist, rtx nextarg) | |
1310 | { | |
1311 | valist = arm_extract_valist_ptr (valist); | |
1312 | std_expand_builtin_va_start (valist, nextarg); | |
1313 | } | |
1314 | ||
1315 | /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */ | |
1316 | static tree | |
ae46a823 JM |
1317 | arm_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p, |
1318 | gimple_seq *post_p) | |
07d8efe3 MM |
1319 | { |
1320 | valist = arm_extract_valist_ptr (valist); | |
1321 | return std_gimplify_va_arg_expr (valist, type, pre_p, post_p); | |
1322 | } | |
1323 | ||
12a0a4d4 PB |
1324 | /* Lookup NAME in SEL. */ |
1325 | ||
1326 | static const struct processors * | |
1327 | arm_find_cpu (const char *name, const struct processors *sel, const char *desc) | |
1328 | { | |
1329 | if (!(name && *name)) | |
1330 | return NULL; | |
1331 | ||
1332 | for (; sel->name != NULL; sel++) | |
1333 | { | |
1334 | if (streq (name, sel->name)) | |
1335 | return sel; | |
1336 | } | |
1337 | ||
1338 | error ("bad value (%s) for %s switch", name, desc); | |
1339 | return NULL; | |
1340 | } | |
1341 | ||
c54c7322 RS |
1342 | /* Implement TARGET_HANDLE_OPTION. */ |
1343 | ||
1344 | static bool | |
96e45421 JM |
1345 | arm_handle_option (struct gcc_options *opts, struct gcc_options *opts_set, |
1346 | const struct cl_decoded_option *decoded, | |
1347 | location_t loc ATTRIBUTE_UNUSED) | |
c54c7322 | 1348 | { |
96e45421 JM |
1349 | size_t code = decoded->opt_index; |
1350 | const char *arg = decoded->arg; | |
1351 | ||
1352 | gcc_assert (opts == &global_options); | |
1353 | gcc_assert (opts_set == &global_options_set); | |
1354 | ||
c54c7322 RS |
1355 | switch (code) |
1356 | { | |
c54c7322 | 1357 | case OPT_march_: |
12a0a4d4 | 1358 | arm_selected_arch = arm_find_cpu(arg, all_architectures, "-march"); |
c54c7322 RS |
1359 | return true; |
1360 | ||
1361 | case OPT_mcpu_: | |
12a0a4d4 | 1362 | arm_selected_cpu = arm_find_cpu(arg, all_cores, "-mcpu"); |
c54c7322 RS |
1363 | return true; |
1364 | ||
c54c7322 RS |
1365 | case OPT_mhard_float: |
1366 | target_float_abi_name = "hard"; | |
1367 | return true; | |
1368 | ||
c54c7322 RS |
1369 | case OPT_msoft_float: |
1370 | target_float_abi_name = "soft"; | |
1371 | return true; | |
1372 | ||
c54c7322 | 1373 | case OPT_mtune_: |
12a0a4d4 | 1374 | arm_selected_tune = arm_find_cpu(arg, all_cores, "-mtune"); |
c54c7322 RS |
1375 | return true; |
1376 | ||
1377 | default: | |
1378 | return true; | |
1379 | } | |
1380 | } | |
1381 | ||
67e6ba46 NC |
1382 | static void |
1383 | arm_target_help (void) | |
1384 | { | |
1385 | int i; | |
1386 | static int columns = 0; | |
1387 | int remaining; | |
1388 | ||
1389 | /* If we have not done so already, obtain the desired maximum width of | |
1390 | the output. Note - this is a duplication of the code at the start of | |
1391 | gcc/opts.c:print_specific_help() - the two copies should probably be | |
1392 | replaced by a single function. */ | |
1393 | if (columns == 0) | |
1394 | { | |
1395 | const char *p; | |
1396 | ||
71f3e391 | 1397 | p = getenv ("COLUMNS"); |
67e6ba46 NC |
1398 | if (p != NULL) |
1399 | { | |
1400 | int value = atoi (p); | |
1401 | ||
1402 | if (value > 0) | |
1403 | columns = value; | |
1404 | } | |
1405 | ||
1406 | if (columns == 0) | |
1407 | /* Use a reasonable default. */ | |
1408 | columns = 80; | |
1409 | } | |
1410 | ||
1411 | printf (" Known ARM CPUs (for use with the -mcpu= and -mtune= options):\n"); | |
1412 | ||
1413 | /* The - 2 is because we know that the last entry in the array is NULL. */ | |
1414 | i = ARRAY_SIZE (all_cores) - 2; | |
1415 | gcc_assert (i > 0); | |
1416 | printf (" %s", all_cores[i].name); | |
1417 | remaining = columns - (strlen (all_cores[i].name) + 4); | |
1418 | gcc_assert (remaining >= 0); | |
1419 | ||
1420 | while (i--) | |
1421 | { | |
1422 | int len = strlen (all_cores[i].name); | |
1423 | ||
1424 | if (remaining > len + 2) | |
1425 | { | |
1426 | printf (", %s", all_cores[i].name); | |
1427 | remaining -= len + 2; | |
1428 | } | |
1429 | else | |
1430 | { | |
1431 | if (remaining > 0) | |
1432 | printf (","); | |
1433 | printf ("\n %s", all_cores[i].name); | |
1434 | remaining = columns - (len + 4); | |
1435 | } | |
1436 | } | |
1437 | ||
1438 | printf ("\n\n Known ARM architectures (for use with the -march= option):\n"); | |
1439 | ||
1440 | i = ARRAY_SIZE (all_architectures) - 2; | |
1441 | gcc_assert (i > 0); | |
1442 | ||
1443 | printf (" %s", all_architectures[i].name); | |
1444 | remaining = columns - (strlen (all_architectures[i].name) + 4); | |
1445 | gcc_assert (remaining >= 0); | |
1446 | ||
1447 | while (i--) | |
1448 | { | |
1449 | int len = strlen (all_architectures[i].name); | |
1450 | ||
1451 | if (remaining > len + 2) | |
1452 | { | |
1453 | printf (", %s", all_architectures[i].name); | |
1454 | remaining -= len + 2; | |
1455 | } | |
1456 | else | |
1457 | { | |
1458 | if (remaining > 0) | |
1459 | printf (","); | |
1460 | printf ("\n %s", all_architectures[i].name); | |
1461 | remaining = columns - (len + 4); | |
1462 | } | |
1463 | } | |
1464 | printf ("\n"); | |
1465 | ||
1466 | } | |
1467 | ||
c5387660 JM |
1468 | /* Fix up any incompatible options that the user has specified. */ |
1469 | static void | |
1470 | arm_option_override (void) | |
2b835d68 | 1471 | { |
ed4c4348 | 1472 | unsigned i; |
9b66ebb1 | 1473 | |
c5387660 JM |
1474 | #ifdef SUBTARGET_OVERRIDE_OPTIONS |
1475 | SUBTARGET_OVERRIDE_OPTIONS; | |
1476 | #endif | |
1477 | ||
12a0a4d4 | 1478 | if (arm_selected_arch) |
bd9c7e23 | 1479 | { |
12a0a4d4 PB |
1480 | if (arm_selected_cpu) |
1481 | { | |
1482 | /* Check for conflict between mcpu and march. */ | |
1483 | if ((arm_selected_cpu->flags ^ arm_selected_arch->flags) & ~FL_TUNE) | |
1484 | { | |
1485 | warning (0, "switch -mcpu=%s conflicts with -march=%s switch", | |
1486 | arm_selected_cpu->name, arm_selected_arch->name); | |
1487 | /* -march wins for code generation. | |
1488 | -mcpu wins for default tuning. */ | |
1489 | if (!arm_selected_tune) | |
1490 | arm_selected_tune = arm_selected_cpu; | |
1491 | ||
1492 | arm_selected_cpu = arm_selected_arch; | |
1493 | } | |
1494 | else | |
1495 | /* -mcpu wins. */ | |
1496 | arm_selected_arch = NULL; | |
1497 | } | |
1498 | else | |
1499 | /* Pick a CPU based on the architecture. */ | |
1500 | arm_selected_cpu = arm_selected_arch; | |
bd9c7e23 | 1501 | } |
f676971a | 1502 | |
f5a1b0d2 | 1503 | /* If the user did not specify a processor, choose one for them. */ |
12a0a4d4 | 1504 | if (!arm_selected_cpu) |
f5a1b0d2 | 1505 | { |
8b60264b | 1506 | const struct processors * sel; |
aec3cfba | 1507 | unsigned int sought; |
aec3cfba | 1508 | |
12a0a4d4 PB |
1509 | arm_selected_cpu = &all_cores[TARGET_CPU_DEFAULT]; |
1510 | if (!arm_selected_cpu->name) | |
78011587 PB |
1511 | { |
1512 | #ifdef SUBTARGET_CPU_DEFAULT | |
1513 | /* Use the subtarget default CPU if none was specified by | |
1514 | configure. */ | |
12a0a4d4 | 1515 | arm_selected_cpu = &all_cores[SUBTARGET_CPU_DEFAULT]; |
78011587 PB |
1516 | #endif |
1517 | /* Default to ARM6. */ | |
fe7645b9 | 1518 | if (!arm_selected_cpu->name) |
12a0a4d4 | 1519 | arm_selected_cpu = &all_cores[arm6]; |
78011587 | 1520 | } |
aec3cfba | 1521 | |
12a0a4d4 | 1522 | sel = arm_selected_cpu; |
aec3cfba | 1523 | insn_flags = sel->flags; |
9b66ebb1 | 1524 | |
aec3cfba NC |
1525 | /* Now check to see if the user has specified some command line |
1526 | switch that require certain abilities from the cpu. */ | |
1527 | sought = 0; | |
f676971a | 1528 | |
d5b7b3ae | 1529 | if (TARGET_INTERWORK || TARGET_THUMB) |
f5a1b0d2 | 1530 | { |
aec3cfba | 1531 | sought |= (FL_THUMB | FL_MODE32); |
f676971a | 1532 | |
d5b7b3ae | 1533 | /* There are no ARM processors that support both APCS-26 and |
aec3cfba NC |
1534 | interworking. Therefore we force FL_MODE26 to be removed |
1535 | from insn_flags here (if it was set), so that the search | |
1536 | below will always be able to find a compatible processor. */ | |
5895f793 | 1537 | insn_flags &= ~FL_MODE26; |
f5a1b0d2 | 1538 | } |
f676971a | 1539 | |
aec3cfba | 1540 | if (sought != 0 && ((sought & insn_flags) != sought)) |
f5a1b0d2 | 1541 | { |
aec3cfba NC |
1542 | /* Try to locate a CPU type that supports all of the abilities |
1543 | of the default CPU, plus the extra abilities requested by | |
1544 | the user. */ | |
5895f793 | 1545 | for (sel = all_cores; sel->name != NULL; sel++) |
aec3cfba | 1546 | if ((sel->flags & sought) == (sought | insn_flags)) |
f5a1b0d2 NC |
1547 | break; |
1548 | ||
1549 | if (sel->name == NULL) | |
aec3cfba | 1550 | { |
0977774b | 1551 | unsigned current_bit_count = 0; |
8b60264b | 1552 | const struct processors * best_fit = NULL; |
f676971a | 1553 | |
aec3cfba NC |
1554 | /* Ideally we would like to issue an error message here |
1555 | saying that it was not possible to find a CPU compatible | |
1556 | with the default CPU, but which also supports the command | |
1557 | line options specified by the programmer, and so they | |
1558 | ought to use the -mcpu=<name> command line option to | |
1559 | override the default CPU type. | |
1560 | ||
61f0ccff RE |
1561 | If we cannot find a cpu that has both the |
1562 | characteristics of the default cpu and the given | |
1563 | command line options we scan the array again looking | |
1564 | for a best match. */ | |
5895f793 | 1565 | for (sel = all_cores; sel->name != NULL; sel++) |
aec3cfba NC |
1566 | if ((sel->flags & sought) == sought) |
1567 | { | |
0977774b | 1568 | unsigned count; |
aec3cfba NC |
1569 | |
1570 | count = bit_count (sel->flags & insn_flags); | |
1571 | ||
1572 | if (count >= current_bit_count) | |
1573 | { | |
1574 | best_fit = sel; | |
1575 | current_bit_count = count; | |
1576 | } | |
1577 | } | |
f5a1b0d2 | 1578 | |
e6d29d15 NS |
1579 | gcc_assert (best_fit); |
1580 | sel = best_fit; | |
aec3cfba NC |
1581 | } |
1582 | ||
12a0a4d4 | 1583 | arm_selected_cpu = sel; |
f5a1b0d2 NC |
1584 | } |
1585 | } | |
f676971a | 1586 | |
12a0a4d4 PB |
1587 | gcc_assert (arm_selected_cpu); |
1588 | /* The selected cpu may be an architecture, so lookup tuning by core ID. */ | |
1589 | if (!arm_selected_tune) | |
1590 | arm_selected_tune = &all_cores[arm_selected_cpu->core]; | |
1591 | ||
1592 | sprintf (arm_arch_name, "__ARM_ARCH_%s__", arm_selected_cpu->arch); | |
1593 | insn_flags = arm_selected_cpu->flags; | |
f676971a | 1594 | |
12a0a4d4 PB |
1595 | arm_tune = arm_selected_tune->core; |
1596 | tune_flags = arm_selected_tune->flags; | |
1597 | current_tune = arm_selected_tune->tune; | |
e26053d1 | 1598 | |
0fd8c3ad SL |
1599 | if (target_fp16_format_name) |
1600 | { | |
1601 | for (i = 0; i < ARRAY_SIZE (all_fp16_formats); i++) | |
1602 | { | |
1603 | if (streq (all_fp16_formats[i].name, target_fp16_format_name)) | |
1604 | { | |
1605 | arm_fp16_format = all_fp16_formats[i].fp16_format_type; | |
1606 | break; | |
1607 | } | |
1608 | } | |
1609 | if (i == ARRAY_SIZE (all_fp16_formats)) | |
1610 | error ("invalid __fp16 format option: -mfp16-format=%s", | |
1611 | target_fp16_format_name); | |
1612 | } | |
1613 | else | |
1614 | arm_fp16_format = ARM_FP16_FORMAT_NONE; | |
1615 | ||
26272ba2 PB |
1616 | if (target_abi_name) |
1617 | { | |
1618 | for (i = 0; i < ARRAY_SIZE (arm_all_abis); i++) | |
1619 | { | |
1620 | if (streq (arm_all_abis[i].name, target_abi_name)) | |
1621 | { | |
1622 | arm_abi = arm_all_abis[i].abi_type; | |
1623 | break; | |
1624 | } | |
1625 | } | |
1626 | if (i == ARRAY_SIZE (arm_all_abis)) | |
1627 | error ("invalid ABI option: -mabi=%s", target_abi_name); | |
1628 | } | |
1629 | else | |
1630 | arm_abi = ARM_DEFAULT_ABI; | |
1631 | ||
f5a1b0d2 NC |
1632 | /* Make sure that the processor choice does not conflict with any of the |
1633 | other command line choices. */ | |
5b3e6663 PB |
1634 | if (TARGET_ARM && !(insn_flags & FL_NOTM)) |
1635 | error ("target CPU does not support ARM mode"); | |
1636 | ||
26272ba2 PB |
1637 | /* BPABI targets use linker tricks to allow interworking on cores |
1638 | without thumb support. */ | |
1639 | if (TARGET_INTERWORK && !((insn_flags & FL_THUMB) || TARGET_BPABI)) | |
f5a1b0d2 | 1640 | { |
d4ee4d25 | 1641 | warning (0, "target CPU does not support interworking" ); |
c54c7322 | 1642 | target_flags &= ~MASK_INTERWORK; |
f5a1b0d2 | 1643 | } |
f676971a | 1644 | |
d5b7b3ae RE |
1645 | if (TARGET_THUMB && !(insn_flags & FL_THUMB)) |
1646 | { | |
d4ee4d25 | 1647 | warning (0, "target CPU does not support THUMB instructions"); |
c54c7322 | 1648 | target_flags &= ~MASK_THUMB; |
d5b7b3ae RE |
1649 | } |
1650 | ||
1651 | if (TARGET_APCS_FRAME && TARGET_THUMB) | |
1652 | { | |
d4ee4d25 | 1653 | /* warning (0, "ignoring -mapcs-frame because -mthumb was used"); */ |
c54c7322 | 1654 | target_flags &= ~MASK_APCS_FRAME; |
d5b7b3ae | 1655 | } |
d19fb8e3 | 1656 | |
da8ce8be RE |
1657 | /* Callee super interworking implies thumb interworking. Adding |
1658 | this to the flags here simplifies the logic elsewhere. */ | |
1659 | if (TARGET_THUMB && TARGET_CALLEE_INTERWORKING) | |
4546a2ef | 1660 | target_flags |= MASK_INTERWORK; |
da8ce8be | 1661 | |
d5b7b3ae RE |
1662 | /* TARGET_BACKTRACE calls leaf_function_p, which causes a crash if done |
1663 | from here where no function is being compiled currently. */ | |
c54c7322 | 1664 | if ((TARGET_TPCS_FRAME || TARGET_TPCS_LEAF_FRAME) && TARGET_ARM) |
d4ee4d25 | 1665 | warning (0, "enabling backtrace support is only meaningful when compiling for the Thumb"); |
d5b7b3ae RE |
1666 | |
1667 | if (TARGET_ARM && TARGET_CALLEE_INTERWORKING) | |
d4ee4d25 | 1668 | warning (0, "enabling callee interworking support is only meaningful when compiling for the Thumb"); |
d5b7b3ae | 1669 | |
5895f793 | 1670 | if (TARGET_APCS_STACK && !TARGET_APCS_FRAME) |
f5a1b0d2 | 1671 | { |
d4ee4d25 | 1672 | warning (0, "-mapcs-stack-check incompatible with -mno-apcs-frame"); |
c54c7322 | 1673 | target_flags |= MASK_APCS_FRAME; |
f5a1b0d2 | 1674 | } |
f676971a | 1675 | |
2b835d68 | 1676 | if (TARGET_POKE_FUNCTION_NAME) |
c54c7322 | 1677 | target_flags |= MASK_APCS_FRAME; |
f676971a | 1678 | |
2b835d68 | 1679 | if (TARGET_APCS_REENT && flag_pic) |
400500c4 | 1680 | error ("-fpic and -mapcs-reent are incompatible"); |
f676971a | 1681 | |
2b835d68 | 1682 | if (TARGET_APCS_REENT) |
d4ee4d25 | 1683 | warning (0, "APCS reentrant code not supported. Ignored"); |
f676971a | 1684 | |
d5b7b3ae RE |
1685 | /* If this target is normally configured to use APCS frames, warn if they |
1686 | are turned off and debugging is turned on. */ | |
1687 | if (TARGET_ARM | |
1688 | && write_symbols != NO_DEBUG | |
5895f793 | 1689 | && !TARGET_APCS_FRAME |
c54c7322 | 1690 | && (TARGET_DEFAULT & MASK_APCS_FRAME)) |
d4ee4d25 | 1691 | warning (0, "-g with -mno-apcs-frame may not give sensible debugging"); |
f676971a | 1692 | |
2b835d68 | 1693 | if (TARGET_APCS_FLOAT) |
d4ee4d25 | 1694 | warning (0, "passing floating point arguments in fp regs not yet supported"); |
f676971a | 1695 | |
4912a07c | 1696 | /* Initialize boolean versions of the flags, for use in the arm.md file. */ |
9b66ebb1 PB |
1697 | arm_arch3m = (insn_flags & FL_ARCH3M) != 0; |
1698 | arm_arch4 = (insn_flags & FL_ARCH4) != 0; | |
68d560d4 | 1699 | arm_arch4t = arm_arch4 & ((insn_flags & FL_THUMB) != 0); |
9b66ebb1 PB |
1700 | arm_arch5 = (insn_flags & FL_ARCH5) != 0; |
1701 | arm_arch5e = (insn_flags & FL_ARCH5E) != 0; | |
1702 | arm_arch6 = (insn_flags & FL_ARCH6) != 0; | |
d3585b76 | 1703 | arm_arch6k = (insn_flags & FL_ARCH6K) != 0; |
5b3e6663 | 1704 | arm_arch_notm = (insn_flags & FL_NOTM) != 0; |
029e79eb | 1705 | arm_arch7 = (insn_flags & FL_ARCH7) != 0; |
60bd3528 | 1706 | arm_arch7em = (insn_flags & FL_ARCH7EM) != 0; |
5b3e6663 | 1707 | arm_arch_thumb2 = (insn_flags & FL_THUMB2) != 0; |
9b66ebb1 | 1708 | arm_arch_xscale = (insn_flags & FL_XSCALE) != 0; |
78011587 | 1709 | arm_arch_cirrus = (insn_flags & FL_CIRRUS) != 0; |
9b66ebb1 PB |
1710 | |
1711 | arm_ld_sched = (tune_flags & FL_LDSCHED) != 0; | |
abac3b49 | 1712 | arm_tune_strongarm = (tune_flags & FL_STRONG) != 0; |
906668bb BS |
1713 | thumb_code = TARGET_ARM == 0; |
1714 | thumb1_code = TARGET_THUMB1 != 0; | |
abac3b49 | 1715 | arm_tune_wbuf = (tune_flags & FL_WBUF) != 0; |
9b66ebb1 PB |
1716 | arm_tune_xscale = (tune_flags & FL_XSCALE) != 0; |
1717 | arm_arch_iwmmxt = (insn_flags & FL_IWMMXT) != 0; | |
5b3e6663 | 1718 | arm_arch_hwdiv = (insn_flags & FL_DIV) != 0; |
7612f14d | 1719 | arm_tune_cortex_a9 = (arm_tune == cortexa9) != 0; |
5a9335ef | 1720 | |
f67358da PB |
1721 | /* If we are not using the default (ARM mode) section anchor offset |
1722 | ranges, then set the correct ranges now. */ | |
1723 | if (TARGET_THUMB1) | |
1724 | { | |
1725 | /* Thumb-1 LDR instructions cannot have negative offsets. | |
1726 | Permissible positive offset ranges are 5-bit (for byte loads), | |
1727 | 6-bit (for halfword loads), or 7-bit (for word loads). | |
1728 | Empirical results suggest a 7-bit anchor range gives the best | |
1729 | overall code size. */ | |
1730 | targetm.min_anchor_offset = 0; | |
1731 | targetm.max_anchor_offset = 127; | |
1732 | } | |
1733 | else if (TARGET_THUMB2) | |
1734 | { | |
1735 | /* The minimum is set such that the total size of the block | |
1736 | for a particular anchor is 248 + 1 + 4095 bytes, which is | |
1737 | divisible by eight, ensuring natural spacing of anchors. */ | |
1738 | targetm.min_anchor_offset = -248; | |
1739 | targetm.max_anchor_offset = 4095; | |
1740 | } | |
1741 | ||
68d560d4 RE |
1742 | /* V5 code we generate is completely interworking capable, so we turn off |
1743 | TARGET_INTERWORK here to avoid many tests later on. */ | |
2ad4dcf9 RE |
1744 | |
1745 | /* XXX However, we must pass the right pre-processor defines to CPP | |
1746 | or GLD can get confused. This is a hack. */ | |
1747 | if (TARGET_INTERWORK) | |
1748 | arm_cpp_interwork = 1; | |
1749 | ||
68d560d4 | 1750 | if (arm_arch5) |
c54c7322 | 1751 | target_flags &= ~MASK_INTERWORK; |
68d560d4 | 1752 | |
5848830f PB |
1753 | if (TARGET_IWMMXT && !ARM_DOUBLEWORD_ALIGN) |
1754 | error ("iwmmxt requires an AAPCS compatible ABI for proper operation"); | |
1755 | ||
1756 | if (TARGET_IWMMXT_ABI && !TARGET_IWMMXT) | |
1757 | error ("iwmmxt abi requires an iwmmxt capable cpu"); | |
6f7ebcbb | 1758 | |
9b66ebb1 | 1759 | if (target_fpu_name == NULL && target_fpe_name != NULL) |
9b6b54e2 | 1760 | { |
9b66ebb1 PB |
1761 | if (streq (target_fpe_name, "2")) |
1762 | target_fpu_name = "fpe2"; | |
1763 | else if (streq (target_fpe_name, "3")) | |
1764 | target_fpu_name = "fpe3"; | |
1765 | else | |
1766 | error ("invalid floating point emulation option: -mfpe=%s", | |
1767 | target_fpe_name); | |
1768 | } | |
d79f3032 PB |
1769 | |
1770 | if (target_fpu_name == NULL) | |
2b835d68 | 1771 | { |
9b66ebb1 | 1772 | #ifdef FPUTYPE_DEFAULT |
d79f3032 | 1773 | target_fpu_name = FPUTYPE_DEFAULT; |
9b66ebb1 | 1774 | #else |
78011587 | 1775 | if (arm_arch_cirrus) |
d79f3032 | 1776 | target_fpu_name = "maverick"; |
9b66ebb1 | 1777 | else |
d79f3032 | 1778 | target_fpu_name = "fpe2"; |
9b66ebb1 | 1779 | #endif |
d79f3032 PB |
1780 | } |
1781 | ||
1782 | arm_fpu_desc = NULL; | |
1783 | for (i = 0; i < ARRAY_SIZE (all_fpus); i++) | |
1784 | { | |
1785 | if (streq (all_fpus[i].name, target_fpu_name)) | |
1786 | { | |
1787 | arm_fpu_desc = &all_fpus[i]; | |
1788 | break; | |
1789 | } | |
1790 | } | |
b761dbe6 | 1791 | |
d79f3032 | 1792 | if (!arm_fpu_desc) |
b761dbe6 RE |
1793 | { |
1794 | error ("invalid floating point option: -mfpu=%s", target_fpu_name); | |
1795 | return; | |
1796 | } | |
d79f3032 PB |
1797 | |
1798 | switch (arm_fpu_desc->model) | |
1799 | { | |
1800 | case ARM_FP_MODEL_FPA: | |
1801 | if (arm_fpu_desc->rev == 2) | |
1802 | arm_fpu_attr = FPU_FPE2; | |
1803 | else if (arm_fpu_desc->rev == 3) | |
1804 | arm_fpu_attr = FPU_FPE3; | |
2b835d68 | 1805 | else |
d79f3032 PB |
1806 | arm_fpu_attr = FPU_FPA; |
1807 | break; | |
1808 | ||
1809 | case ARM_FP_MODEL_MAVERICK: | |
1810 | arm_fpu_attr = FPU_MAVERICK; | |
1811 | break; | |
1812 | ||
1813 | case ARM_FP_MODEL_VFP: | |
1814 | arm_fpu_attr = FPU_VFP; | |
1815 | break; | |
1816 | ||
1817 | default: | |
1818 | gcc_unreachable(); | |
9b66ebb1 PB |
1819 | } |
1820 | ||
1821 | if (target_float_abi_name != NULL) | |
1822 | { | |
1823 | /* The user specified a FP ABI. */ | |
1824 | for (i = 0; i < ARRAY_SIZE (all_float_abis); i++) | |
1825 | { | |
1826 | if (streq (all_float_abis[i].name, target_float_abi_name)) | |
1827 | { | |
1828 | arm_float_abi = all_float_abis[i].abi_type; | |
1829 | break; | |
1830 | } | |
1831 | } | |
1832 | if (i == ARRAY_SIZE (all_float_abis)) | |
1833 | error ("invalid floating point abi: -mfloat-abi=%s", | |
1834 | target_float_abi_name); | |
2b835d68 | 1835 | } |
3d8532aa PB |
1836 | else |
1837 | arm_float_abi = TARGET_DEFAULT_FLOAT_ABI; | |
9b66ebb1 | 1838 | |
0c48a567 | 1839 | if (TARGET_AAPCS_BASED |
d79f3032 | 1840 | && (arm_fpu_desc->model == ARM_FP_MODEL_FPA)) |
0c48a567 RR |
1841 | error ("FPA is unsupported in the AAPCS"); |
1842 | ||
3ce14752 | 1843 | if (TARGET_AAPCS_BASED) |
9df5bfe4 RR |
1844 | { |
1845 | if (TARGET_CALLER_INTERWORKING) | |
1846 | error ("AAPCS does not support -mcaller-super-interworking"); | |
1847 | else | |
1848 | if (TARGET_CALLEE_INTERWORKING) | |
1849 | error ("AAPCS does not support -mcallee-super-interworking"); | |
1850 | } | |
3ce14752 | 1851 | |
87b24aaf PB |
1852 | /* FPA and iWMMXt are incompatible because the insn encodings overlap. |
1853 | VFP and iWMMXt can theoretically coexist, but it's unlikely such silicon | |
1854 | will ever exist. GCC makes no attempt to support this combination. */ | |
1855 | if (TARGET_IWMMXT && !TARGET_SOFT_FLOAT) | |
1856 | sorry ("iWMMXt and hardware floating point"); | |
1857 | ||
5b3e6663 PB |
1858 | /* ??? iWMMXt insn patterns need auditing for Thumb-2. */ |
1859 | if (TARGET_THUMB2 && TARGET_IWMMXT) | |
1860 | sorry ("Thumb-2 iWMMXt"); | |
1861 | ||
0fd8c3ad SL |
1862 | /* __fp16 support currently assumes the core has ldrh. */ |
1863 | if (!arm_arch4 && arm_fp16_format != ARM_FP16_FORMAT_NONE) | |
1864 | sorry ("__fp16 and no ldrh"); | |
1865 | ||
9b66ebb1 PB |
1866 | /* If soft-float is specified then don't use FPU. */ |
1867 | if (TARGET_SOFT_FLOAT) | |
d79f3032 | 1868 | arm_fpu_attr = FPU_NONE; |
f676971a | 1869 | |
390b17c2 RE |
1870 | if (TARGET_AAPCS_BASED) |
1871 | { | |
1872 | if (arm_abi == ARM_ABI_IWMMXT) | |
1873 | arm_pcs_default = ARM_PCS_AAPCS_IWMMXT; | |
1874 | else if (arm_float_abi == ARM_FLOAT_ABI_HARD | |
1875 | && TARGET_HARD_FLOAT | |
1876 | && TARGET_VFP) | |
1877 | arm_pcs_default = ARM_PCS_AAPCS_VFP; | |
1878 | else | |
1879 | arm_pcs_default = ARM_PCS_AAPCS; | |
1880 | } | |
1881 | else | |
1882 | { | |
1883 | if (arm_float_abi == ARM_FLOAT_ABI_HARD && TARGET_VFP) | |
1884 | sorry ("-mfloat-abi=hard and VFP"); | |
1885 | ||
1886 | if (arm_abi == ARM_ABI_APCS) | |
1887 | arm_pcs_default = ARM_PCS_APCS; | |
1888 | else | |
1889 | arm_pcs_default = ARM_PCS_ATPCS; | |
1890 | } | |
1891 | ||
f5a1b0d2 NC |
1892 | /* For arm2/3 there is no need to do any scheduling if there is only |
1893 | a floating point emulator, or we are doing software floating-point. */ | |
9b66ebb1 | 1894 | if ((TARGET_SOFT_FLOAT |
d79f3032 | 1895 | || (TARGET_FPA && arm_fpu_desc->rev)) |
ed0e6530 | 1896 | && (tune_flags & FL_MODE32) == 0) |
f5a1b0d2 | 1897 | flag_schedule_insns = flag_schedule_insns_after_reload = 0; |
f676971a | 1898 | |
d3585b76 DJ |
1899 | if (target_thread_switch) |
1900 | { | |
1901 | if (strcmp (target_thread_switch, "soft") == 0) | |
1902 | target_thread_pointer = TP_SOFT; | |
1903 | else if (strcmp (target_thread_switch, "auto") == 0) | |
1904 | target_thread_pointer = TP_AUTO; | |
1905 | else if (strcmp (target_thread_switch, "cp15") == 0) | |
1906 | target_thread_pointer = TP_CP15; | |
1907 | else | |
1908 | error ("invalid thread pointer option: -mtp=%s", target_thread_switch); | |
1909 | } | |
1910 | ||
1911 | /* Use the cp15 method if it is available. */ | |
1912 | if (target_thread_pointer == TP_AUTO) | |
1913 | { | |
87d05b44 | 1914 | if (arm_arch6k && !TARGET_THUMB1) |
d3585b76 DJ |
1915 | target_thread_pointer = TP_CP15; |
1916 | else | |
1917 | target_thread_pointer = TP_SOFT; | |
1918 | } | |
1919 | ||
5b3e6663 PB |
1920 | if (TARGET_HARD_TP && TARGET_THUMB1) |
1921 | error ("can not use -mtp=cp15 with 16-bit Thumb"); | |
d3585b76 | 1922 | |
5848830f | 1923 | /* Override the default structure alignment for AAPCS ABI. */ |
077fc835 | 1924 | if (TARGET_AAPCS_BASED) |
5848830f PB |
1925 | arm_structure_size_boundary = 8; |
1926 | ||
b355a481 NC |
1927 | if (structure_size_string != NULL) |
1928 | { | |
1929 | int size = strtol (structure_size_string, NULL, 0); | |
5848830f PB |
1930 | |
1931 | if (size == 8 || size == 32 | |
1932 | || (ARM_DOUBLEWORD_ALIGN && size == 64)) | |
b355a481 NC |
1933 | arm_structure_size_boundary = size; |
1934 | else | |
d4ee4d25 | 1935 | warning (0, "structure size boundary can only be set to %s", |
5848830f | 1936 | ARM_DOUBLEWORD_ALIGN ? "8, 32 or 64": "8 or 32"); |
b355a481 | 1937 | } |
ed0e6530 | 1938 | |
9403b7f7 RS |
1939 | if (!TARGET_ARM && TARGET_VXWORKS_RTP && flag_pic) |
1940 | { | |
1941 | error ("RTP PIC is incompatible with Thumb"); | |
1942 | flag_pic = 0; | |
1943 | } | |
1944 | ||
c147eacb PB |
1945 | /* If stack checking is disabled, we can use r10 as the PIC register, |
1946 | which keeps r9 available. The EABI specifies r9 as the PIC register. */ | |
1947 | if (flag_pic && TARGET_SINGLE_PIC_BASE) | |
9403b7f7 RS |
1948 | { |
1949 | if (TARGET_VXWORKS_RTP) | |
1950 | warning (0, "RTP PIC is incompatible with -msingle-pic-base"); | |
1951 | arm_pic_register = (TARGET_APCS_STACK || TARGET_AAPCS_BASED) ? 9 : 10; | |
1952 | } | |
1953 | ||
1954 | if (flag_pic && TARGET_VXWORKS_RTP) | |
1955 | arm_pic_register = 9; | |
c147eacb | 1956 | |
ed0e6530 PB |
1957 | if (arm_pic_register_string != NULL) |
1958 | { | |
5b43fed1 | 1959 | int pic_register = decode_reg_name (arm_pic_register_string); |
e26053d1 | 1960 | |
5895f793 | 1961 | if (!flag_pic) |
d4ee4d25 | 1962 | warning (0, "-mpic-register= is useless without -fpic"); |
ed0e6530 | 1963 | |
ed0e6530 | 1964 | /* Prevent the user from choosing an obviously stupid PIC register. */ |
5b43fed1 RH |
1965 | else if (pic_register < 0 || call_used_regs[pic_register] |
1966 | || pic_register == HARD_FRAME_POINTER_REGNUM | |
1967 | || pic_register == STACK_POINTER_REGNUM | |
9403b7f7 RS |
1968 | || pic_register >= PC_REGNUM |
1969 | || (TARGET_VXWORKS_RTP | |
1970 | && (unsigned int) pic_register != arm_pic_register)) | |
c725bd79 | 1971 | error ("unable to use '%s' for PIC register", arm_pic_register_string); |
ed0e6530 PB |
1972 | else |
1973 | arm_pic_register = pic_register; | |
1974 | } | |
d5b7b3ae | 1975 | |
5fd42423 PB |
1976 | /* Enable -mfix-cortex-m3-ldrd by default for Cortex-M3 cores. */ |
1977 | if (fix_cm3_ldrd == 2) | |
1978 | { | |
12a0a4d4 | 1979 | if (arm_selected_cpu->core == cortexm3) |
5fd42423 PB |
1980 | fix_cm3_ldrd = 1; |
1981 | else | |
1982 | fix_cm3_ldrd = 0; | |
1983 | } | |
1984 | ||
4aef21c8 | 1985 | if (TARGET_THUMB1 && flag_schedule_insns) |
d5b7b3ae RE |
1986 | { |
1987 | /* Don't warn since it's on by default in -O2. */ | |
1988 | flag_schedule_insns = 0; | |
1989 | } | |
1990 | ||
f5a1b0d2 | 1991 | if (optimize_size) |
be03ccc9 | 1992 | { |
be03ccc9 | 1993 | /* If optimizing for size, bump the number of instructions that we |
d6b4baa4 | 1994 | are prepared to conditionally execute (even on a StrongARM). */ |
be03ccc9 NP |
1995 | max_insns_skipped = 6; |
1996 | } | |
1997 | else | |
1998 | { | |
be03ccc9 NP |
1999 | /* StrongARM has early execution of branches, so a sequence |
2000 | that is worth skipping is shorter. */ | |
abac3b49 | 2001 | if (arm_tune_strongarm) |
be03ccc9 NP |
2002 | max_insns_skipped = 3; |
2003 | } | |
92a432f4 | 2004 | |
70041f8a RE |
2005 | /* Hot/Cold partitioning is not currently supported, since we can't |
2006 | handle literal pool placement in that case. */ | |
2007 | if (flag_reorder_blocks_and_partition) | |
2008 | { | |
2009 | inform (input_location, | |
2010 | "-freorder-blocks-and-partition not supported on this architecture"); | |
2011 | flag_reorder_blocks_and_partition = 0; | |
2012 | flag_reorder_blocks = 1; | |
2013 | } | |
2014 | ||
128dc8e2 | 2015 | if (flag_pic) |
ec3728ad MK |
2016 | /* Hoisting PIC address calculations more aggressively provides a small, |
2017 | but measurable, size reduction for PIC code. Therefore, we decrease | |
2018 | the bar for unrestricted expression hoisting to the cost of PIC address | |
2019 | calculation, which is 2 instructions. */ | |
48476d13 JM |
2020 | maybe_set_param_value (PARAM_GCSE_UNRESTRICTED_COST, 2, |
2021 | global_options.x_param_values, | |
2022 | global_options_set.x_param_values); | |
ec3728ad | 2023 | |
f5c88dbf JZ |
2024 | /* ARM EABI defaults to strict volatile bitfields. */ |
2025 | if (TARGET_AAPCS_BASED && flag_strict_volatile_bitfields < 0) | |
2026 | flag_strict_volatile_bitfields = 1; | |
2027 | ||
911de8a3 IB |
2028 | /* Enable sw prefetching at -O3 for CPUS that have prefetch, and we have deemed |
2029 | it beneficial (signified by setting num_prefetch_slots to 1 or more.) */ | |
2030 | if (flag_prefetch_loop_arrays < 0 | |
2031 | && HAVE_prefetch | |
2032 | && optimize >= 3 | |
2033 | && current_tune->num_prefetch_slots > 0) | |
2034 | flag_prefetch_loop_arrays = 1; | |
2035 | ||
2036 | /* Set up parameters to be used in prefetching algorithm. Do not override the | |
2037 | defaults unless we are tuning for a core we have researched values for. */ | |
2038 | if (current_tune->num_prefetch_slots > 0) | |
2039 | maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES, | |
2040 | current_tune->num_prefetch_slots, | |
2041 | global_options.x_param_values, | |
2042 | global_options_set.x_param_values); | |
2043 | if (current_tune->l1_cache_line_size >= 0) | |
2044 | maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE, | |
2045 | current_tune->l1_cache_line_size, | |
2046 | global_options.x_param_values, | |
2047 | global_options_set.x_param_values); | |
2048 | if (current_tune->l1_cache_size >= 0) | |
2049 | maybe_set_param_value (PARAM_L1_CACHE_SIZE, | |
2050 | current_tune->l1_cache_size, | |
2051 | global_options.x_param_values, | |
2052 | global_options_set.x_param_values); | |
2053 | ||
92a432f4 RE |
2054 | /* Register global variables with the garbage collector. */ |
2055 | arm_add_gc_roots (); | |
2056 | } | |
2057 | ||
2058 | static void | |
e32bac5b | 2059 | arm_add_gc_roots (void) |
92a432f4 | 2060 | { |
c7319d87 RE |
2061 | gcc_obstack_init(&minipool_obstack); |
2062 | minipool_startobj = (char *) obstack_alloc (&minipool_obstack, 0); | |
2b835d68 | 2063 | } |
cce8749e | 2064 | \f |
6d3d9133 NC |
2065 | /* A table of known ARM exception types. |
2066 | For use with the interrupt function attribute. */ | |
2067 | ||
2068 | typedef struct | |
2069 | { | |
8b60264b KG |
2070 | const char *const arg; |
2071 | const unsigned long return_value; | |
6d3d9133 NC |
2072 | } |
2073 | isr_attribute_arg; | |
2074 | ||
8b60264b | 2075 | static const isr_attribute_arg isr_attribute_args [] = |
6d3d9133 NC |
2076 | { |
2077 | { "IRQ", ARM_FT_ISR }, | |
2078 | { "irq", ARM_FT_ISR }, | |
2079 | { "FIQ", ARM_FT_FIQ }, | |
2080 | { "fiq", ARM_FT_FIQ }, | |
2081 | { "ABORT", ARM_FT_ISR }, | |
2082 | { "abort", ARM_FT_ISR }, | |
2083 | { "ABORT", ARM_FT_ISR }, | |
2084 | { "abort", ARM_FT_ISR }, | |
2085 | { "UNDEF", ARM_FT_EXCEPTION }, | |
2086 | { "undef", ARM_FT_EXCEPTION }, | |
2087 | { "SWI", ARM_FT_EXCEPTION }, | |
2088 | { "swi", ARM_FT_EXCEPTION }, | |
2089 | { NULL, ARM_FT_NORMAL } | |
2090 | }; | |
2091 | ||
2092 | /* Returns the (interrupt) function type of the current | |
2093 | function, or ARM_FT_UNKNOWN if the type cannot be determined. */ | |
2094 | ||
2095 | static unsigned long | |
e32bac5b | 2096 | arm_isr_value (tree argument) |
6d3d9133 | 2097 | { |
8b60264b | 2098 | const isr_attribute_arg * ptr; |
1d6e90ac | 2099 | const char * arg; |
6d3d9133 | 2100 | |
5b3e6663 PB |
2101 | if (!arm_arch_notm) |
2102 | return ARM_FT_NORMAL | ARM_FT_STACKALIGN; | |
2103 | ||
6d3d9133 NC |
2104 | /* No argument - default to IRQ. */ |
2105 | if (argument == NULL_TREE) | |
2106 | return ARM_FT_ISR; | |
2107 | ||
2108 | /* Get the value of the argument. */ | |
2109 | if (TREE_VALUE (argument) == NULL_TREE | |
2110 | || TREE_CODE (TREE_VALUE (argument)) != STRING_CST) | |
2111 | return ARM_FT_UNKNOWN; | |
2112 | ||
2113 | arg = TREE_STRING_POINTER (TREE_VALUE (argument)); | |
2114 | ||
2115 | /* Check it against the list of known arguments. */ | |
5a9335ef | 2116 | for (ptr = isr_attribute_args; ptr->arg != NULL; ptr++) |
1d6e90ac NC |
2117 | if (streq (arg, ptr->arg)) |
2118 | return ptr->return_value; | |
6d3d9133 | 2119 | |
05713b80 | 2120 | /* An unrecognized interrupt type. */ |
6d3d9133 NC |
2121 | return ARM_FT_UNKNOWN; |
2122 | } | |
2123 | ||
2124 | /* Computes the type of the current function. */ | |
2125 | ||
2126 | static unsigned long | |
e32bac5b | 2127 | arm_compute_func_type (void) |
6d3d9133 NC |
2128 | { |
2129 | unsigned long type = ARM_FT_UNKNOWN; | |
2130 | tree a; | |
2131 | tree attr; | |
f676971a | 2132 | |
e6d29d15 | 2133 | gcc_assert (TREE_CODE (current_function_decl) == FUNCTION_DECL); |
6d3d9133 NC |
2134 | |
2135 | /* Decide if the current function is volatile. Such functions | |
2136 | never return, and many memory cycles can be saved by not storing | |
2137 | register values that will never be needed again. This optimization | |
2138 | was added to speed up context switching in a kernel application. */ | |
2139 | if (optimize > 0 | |
cf1955dc PB |
2140 | && (TREE_NOTHROW (current_function_decl) |
2141 | || !(flag_unwind_tables | |
d5fabb58 JM |
2142 | || (flag_exceptions |
2143 | && arm_except_unwind_info (&global_options) != UI_SJLJ))) | |
6d3d9133 NC |
2144 | && TREE_THIS_VOLATILE (current_function_decl)) |
2145 | type |= ARM_FT_VOLATILE; | |
f676971a | 2146 | |
6de9cd9a | 2147 | if (cfun->static_chain_decl != NULL) |
6d3d9133 NC |
2148 | type |= ARM_FT_NESTED; |
2149 | ||
91d231cb | 2150 | attr = DECL_ATTRIBUTES (current_function_decl); |
f676971a | 2151 | |
6d3d9133 NC |
2152 | a = lookup_attribute ("naked", attr); |
2153 | if (a != NULL_TREE) | |
2154 | type |= ARM_FT_NAKED; | |
2155 | ||
c9ca9b88 PB |
2156 | a = lookup_attribute ("isr", attr); |
2157 | if (a == NULL_TREE) | |
2158 | a = lookup_attribute ("interrupt", attr); | |
f676971a | 2159 | |
c9ca9b88 PB |
2160 | if (a == NULL_TREE) |
2161 | type |= TARGET_INTERWORK ? ARM_FT_INTERWORKED : ARM_FT_NORMAL; | |
6d3d9133 | 2162 | else |
c9ca9b88 | 2163 | type |= arm_isr_value (TREE_VALUE (a)); |
f676971a | 2164 | |
6d3d9133 NC |
2165 | return type; |
2166 | } | |
2167 | ||
2168 | /* Returns the type of the current function. */ | |
2169 | ||
2170 | unsigned long | |
e32bac5b | 2171 | arm_current_func_type (void) |
6d3d9133 NC |
2172 | { |
2173 | if (ARM_FUNC_TYPE (cfun->machine->func_type) == ARM_FT_UNKNOWN) | |
2174 | cfun->machine->func_type = arm_compute_func_type (); | |
2175 | ||
2176 | return cfun->machine->func_type; | |
2177 | } | |
007e61c2 PB |
2178 | |
2179 | bool | |
2180 | arm_allocate_stack_slots_for_args (void) | |
2181 | { | |
2182 | /* Naked functions should not allocate stack slots for arguments. */ | |
2183 | return !IS_NAKED (arm_current_func_type ()); | |
2184 | } | |
2185 | ||
0ef9304b RH |
2186 | \f |
2187 | /* Output assembler code for a block containing the constant parts | |
2188 | of a trampoline, leaving space for the variable parts. | |
2189 | ||
2190 | On the ARM, (if r8 is the static chain regnum, and remembering that | |
2191 | referencing pc adds an offset of 8) the trampoline looks like: | |
2192 | ldr r8, [pc, #0] | |
2193 | ldr pc, [pc] | |
2194 | .word static chain value | |
2195 | .word function's address | |
2196 | XXX FIXME: When the trampoline returns, r8 will be clobbered. */ | |
2197 | ||
2198 | static void | |
2199 | arm_asm_trampoline_template (FILE *f) | |
2200 | { | |
2201 | if (TARGET_ARM) | |
2202 | { | |
2203 | asm_fprintf (f, "\tldr\t%r, [%r, #0]\n", STATIC_CHAIN_REGNUM, PC_REGNUM); | |
2204 | asm_fprintf (f, "\tldr\t%r, [%r, #0]\n", PC_REGNUM, PC_REGNUM); | |
2205 | } | |
2206 | else if (TARGET_THUMB2) | |
2207 | { | |
2208 | /* The Thumb-2 trampoline is similar to the arm implementation. | |
2209 | Unlike 16-bit Thumb, we enter the stub in thumb mode. */ | |
2210 | asm_fprintf (f, "\tldr.w\t%r, [%r, #4]\n", | |
2211 | STATIC_CHAIN_REGNUM, PC_REGNUM); | |
2212 | asm_fprintf (f, "\tldr.w\t%r, [%r, #4]\n", PC_REGNUM, PC_REGNUM); | |
2213 | } | |
2214 | else | |
2215 | { | |
2216 | ASM_OUTPUT_ALIGN (f, 2); | |
2217 | fprintf (f, "\t.code\t16\n"); | |
2218 | fprintf (f, ".Ltrampoline_start:\n"); | |
2219 | asm_fprintf (f, "\tpush\t{r0, r1}\n"); | |
2220 | asm_fprintf (f, "\tldr\tr0, [%r, #8]\n", PC_REGNUM); | |
2221 | asm_fprintf (f, "\tmov\t%r, r0\n", STATIC_CHAIN_REGNUM); | |
2222 | asm_fprintf (f, "\tldr\tr0, [%r, #8]\n", PC_REGNUM); | |
2223 | asm_fprintf (f, "\tstr\tr0, [%r, #4]\n", SP_REGNUM); | |
2224 | asm_fprintf (f, "\tpop\t{r0, %r}\n", PC_REGNUM); | |
2225 | } | |
2226 | assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); | |
2227 | assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); | |
2228 | } | |
2229 | ||
2230 | /* Emit RTL insns to initialize the variable parts of a trampoline. */ | |
2231 | ||
2232 | static void | |
2233 | arm_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value) | |
2234 | { | |
2235 | rtx fnaddr, mem, a_tramp; | |
2236 | ||
2237 | emit_block_move (m_tramp, assemble_trampoline_template (), | |
2238 | GEN_INT (TRAMPOLINE_SIZE), BLOCK_OP_NORMAL); | |
2239 | ||
2240 | mem = adjust_address (m_tramp, SImode, TARGET_32BIT ? 8 : 12); | |
2241 | emit_move_insn (mem, chain_value); | |
2242 | ||
2243 | mem = adjust_address (m_tramp, SImode, TARGET_32BIT ? 12 : 16); | |
2244 | fnaddr = XEXP (DECL_RTL (fndecl), 0); | |
2245 | emit_move_insn (mem, fnaddr); | |
2246 | ||
2247 | a_tramp = XEXP (m_tramp, 0); | |
2248 | emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__clear_cache"), | |
2249 | LCT_NORMAL, VOIDmode, 2, a_tramp, Pmode, | |
2250 | plus_constant (a_tramp, TRAMPOLINE_SIZE), Pmode); | |
2251 | } | |
2252 | ||
2253 | /* Thumb trampolines should be entered in thumb mode, so set | |
2254 | the bottom bit of the address. */ | |
2255 | ||
2256 | static rtx | |
2257 | arm_trampoline_adjust_address (rtx addr) | |
2258 | { | |
2259 | if (TARGET_THUMB) | |
2260 | addr = expand_simple_binop (Pmode, IOR, addr, const1_rtx, | |
2261 | NULL, 0, OPTAB_LIB_WIDEN); | |
2262 | return addr; | |
2263 | } | |
6d3d9133 | 2264 | \f |
f676971a | 2265 | /* Return 1 if it is possible to return using a single instruction. |
a72d4945 RE |
2266 | If SIBLING is non-null, this is a test for a return before a sibling |
2267 | call. SIBLING is the call insn, so we can examine its register usage. */ | |
6d3d9133 | 2268 | |
ff9940b0 | 2269 | int |
a72d4945 | 2270 | use_return_insn (int iscond, rtx sibling) |
ff9940b0 RE |
2271 | { |
2272 | int regno; | |
9b598fa0 | 2273 | unsigned int func_type; |
d5db54a1 | 2274 | unsigned long saved_int_regs; |
a72d4945 | 2275 | unsigned HOST_WIDE_INT stack_adjust; |
5848830f | 2276 | arm_stack_offsets *offsets; |
ff9940b0 | 2277 | |
d5b7b3ae | 2278 | /* Never use a return instruction before reload has run. */ |
6d3d9133 NC |
2279 | if (!reload_completed) |
2280 | return 0; | |
efc2515b | 2281 | |
9b598fa0 RE |
2282 | func_type = arm_current_func_type (); |
2283 | ||
5b3e6663 | 2284 | /* Naked, volatile and stack alignment functions need special |
3a7731fd | 2285 | consideration. */ |
5b3e6663 | 2286 | if (func_type & (ARM_FT_VOLATILE | ARM_FT_NAKED | ARM_FT_STACKALIGN)) |
6d3d9133 | 2287 | return 0; |
06bea5aa | 2288 | |
a15908a4 PB |
2289 | /* So do interrupt functions that use the frame pointer and Thumb |
2290 | interrupt functions. */ | |
2291 | if (IS_INTERRUPT (func_type) && (frame_pointer_needed || TARGET_THUMB)) | |
06bea5aa | 2292 | return 0; |
a72d4945 | 2293 | |
5848830f PB |
2294 | offsets = arm_get_frame_offsets (); |
2295 | stack_adjust = offsets->outgoing_args - offsets->saved_regs; | |
a72d4945 | 2296 | |
6d3d9133 | 2297 | /* As do variadic functions. */ |
38173d38 | 2298 | if (crtl->args.pretend_args_size |
3cb66fd7 | 2299 | || cfun->machine->uses_anonymous_args |
699a4925 | 2300 | /* Or if the function calls __builtin_eh_return () */ |
e3b5732b | 2301 | || crtl->calls_eh_return |
699a4925 | 2302 | /* Or if the function calls alloca */ |
e3b5732b | 2303 | || cfun->calls_alloca |
a72d4945 RE |
2304 | /* Or if there is a stack adjustment. However, if the stack pointer |
2305 | is saved on the stack, we can use a pre-incrementing stack load. */ | |
ec6237e4 PB |
2306 | || !(stack_adjust == 0 || (TARGET_APCS_FRAME && frame_pointer_needed |
2307 | && stack_adjust == 4))) | |
ff9940b0 RE |
2308 | return 0; |
2309 | ||
954954d1 | 2310 | saved_int_regs = offsets->saved_regs_mask; |
d5db54a1 | 2311 | |
a72d4945 RE |
2312 | /* Unfortunately, the insn |
2313 | ||
2314 | ldmib sp, {..., sp, ...} | |
2315 | ||
2316 | triggers a bug on most SA-110 based devices, such that the stack | |
2317 | pointer won't be correctly restored if the instruction takes a | |
839a4992 | 2318 | page fault. We work around this problem by popping r3 along with |
a72d4945 | 2319 | the other registers, since that is never slower than executing |
f676971a | 2320 | another instruction. |
a72d4945 RE |
2321 | |
2322 | We test for !arm_arch5 here, because code for any architecture | |
2323 | less than this could potentially be run on one of the buggy | |
2324 | chips. */ | |
5b3e6663 | 2325 | if (stack_adjust == 4 && !arm_arch5 && TARGET_ARM) |
a72d4945 RE |
2326 | { |
2327 | /* Validate that r3 is a call-clobbered register (always true in | |
d6b4baa4 | 2328 | the default abi) ... */ |
a72d4945 RE |
2329 | if (!call_used_regs[3]) |
2330 | return 0; | |
2331 | ||
4f5dfed0 JC |
2332 | /* ... that it isn't being used for a return value ... */ |
2333 | if (arm_size_return_regs () >= (4 * UNITS_PER_WORD)) | |
2334 | return 0; | |
2335 | ||
2336 | /* ... or for a tail-call argument ... */ | |
a72d4945 RE |
2337 | if (sibling) |
2338 | { | |
e6d29d15 | 2339 | gcc_assert (GET_CODE (sibling) == CALL_INSN); |
a72d4945 RE |
2340 | |
2341 | if (find_regno_fusage (sibling, USE, 3)) | |
2342 | return 0; | |
2343 | } | |
2344 | ||
2345 | /* ... and that there are no call-saved registers in r0-r2 | |
2346 | (always true in the default ABI). */ | |
2347 | if (saved_int_regs & 0x7) | |
2348 | return 0; | |
2349 | } | |
2350 | ||
b111229a | 2351 | /* Can't be done if interworking with Thumb, and any registers have been |
d5db54a1 | 2352 | stacked. */ |
a15908a4 | 2353 | if (TARGET_INTERWORK && saved_int_regs != 0 && !IS_INTERRUPT(func_type)) |
b36ba79f | 2354 | return 0; |
d5db54a1 RE |
2355 | |
2356 | /* On StrongARM, conditional returns are expensive if they aren't | |
2357 | taken and multiple registers have been stacked. */ | |
abac3b49 | 2358 | if (iscond && arm_tune_strongarm) |
6ed30148 | 2359 | { |
f676971a | 2360 | /* Conditional return when just the LR is stored is a simple |
d5db54a1 RE |
2361 | conditional-load instruction, that's not expensive. */ |
2362 | if (saved_int_regs != 0 && saved_int_regs != (1 << LR_REGNUM)) | |
2363 | return 0; | |
6ed30148 | 2364 | |
020a4035 RE |
2365 | if (flag_pic |
2366 | && arm_pic_register != INVALID_REGNUM | |
6fb5fa3c | 2367 | && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM)) |
b111229a | 2368 | return 0; |
6ed30148 | 2369 | } |
d5db54a1 RE |
2370 | |
2371 | /* If there are saved registers but the LR isn't saved, then we need | |
2372 | two instructions for the return. */ | |
2373 | if (saved_int_regs && !(saved_int_regs & (1 << LR_REGNUM))) | |
2374 | return 0; | |
2375 | ||
3b684012 | 2376 | /* Can't be done if any of the FPA regs are pushed, |
6d3d9133 | 2377 | since this also requires an insn. */ |
9b66ebb1 PB |
2378 | if (TARGET_HARD_FLOAT && TARGET_FPA) |
2379 | for (regno = FIRST_FPA_REGNUM; regno <= LAST_FPA_REGNUM; regno++) | |
6fb5fa3c | 2380 | if (df_regs_ever_live_p (regno) && !call_used_regs[regno]) |
9b66ebb1 PB |
2381 | return 0; |
2382 | ||
2383 | /* Likewise VFP regs. */ | |
2384 | if (TARGET_HARD_FLOAT && TARGET_VFP) | |
2385 | for (regno = FIRST_VFP_REGNUM; regno <= LAST_VFP_REGNUM; regno++) | |
6fb5fa3c | 2386 | if (df_regs_ever_live_p (regno) && !call_used_regs[regno]) |
d5b7b3ae | 2387 | return 0; |
ff9940b0 | 2388 | |
5a9335ef NC |
2389 | if (TARGET_REALLY_IWMMXT) |
2390 | for (regno = FIRST_IWMMXT_REGNUM; regno <= LAST_IWMMXT_REGNUM; regno++) | |
6fb5fa3c | 2391 | if (df_regs_ever_live_p (regno) && ! call_used_regs[regno]) |
5a9335ef NC |
2392 | return 0; |
2393 | ||
ff9940b0 RE |
2394 | return 1; |
2395 | } | |
2396 | ||
cce8749e CH |
2397 | /* Return TRUE if int I is a valid immediate ARM constant. */ |
2398 | ||
2399 | int | |
e32bac5b | 2400 | const_ok_for_arm (HOST_WIDE_INT i) |
cce8749e | 2401 | { |
4642ccb1 | 2402 | int lowbit; |
e0b92319 | 2403 | |
f676971a | 2404 | /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must |
56636818 | 2405 | be all zero, or all one. */ |
30cf4896 KG |
2406 | if ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff) != 0 |
2407 | && ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff) | |
2408 | != ((~(unsigned HOST_WIDE_INT) 0) | |
2409 | & ~(unsigned HOST_WIDE_INT) 0xffffffff))) | |
56636818 | 2410 | return FALSE; |
f676971a | 2411 | |
4642ccb1 | 2412 | i &= (unsigned HOST_WIDE_INT) 0xffffffff; |
e0b92319 | 2413 | |
4642ccb1 RE |
2414 | /* Fast return for 0 and small values. We must do this for zero, since |
2415 | the code below can't handle that one case. */ | |
2416 | if ((i & ~(unsigned HOST_WIDE_INT) 0xff) == 0) | |
e2c671ba RE |
2417 | return TRUE; |
2418 | ||
5b3e6663 PB |
2419 | /* Get the number of trailing zeros. */ |
2420 | lowbit = ffs((int) i) - 1; | |
2421 | ||
2422 | /* Only even shifts are allowed in ARM mode so round down to the | |
2423 | nearest even number. */ | |
2424 | if (TARGET_ARM) | |
2425 | lowbit &= ~1; | |
4642ccb1 RE |
2426 | |
2427 | if ((i & ~(((unsigned HOST_WIDE_INT) 0xff) << lowbit)) == 0) | |
2428 | return TRUE; | |
5b3e6663 PB |
2429 | |
2430 | if (TARGET_ARM) | |
2431 | { | |
2432 | /* Allow rotated constants in ARM mode. */ | |
2433 | if (lowbit <= 4 | |
4642ccb1 RE |
2434 | && ((i & ~0xc000003f) == 0 |
2435 | || (i & ~0xf000000f) == 0 | |
2436 | || (i & ~0xfc000003) == 0)) | |
5b3e6663 PB |
2437 | return TRUE; |
2438 | } | |
2439 | else | |
2440 | { | |
2441 | HOST_WIDE_INT v; | |
2442 | ||
d724c8f0 | 2443 | /* Allow repeated patterns 0x00XY00XY or 0xXYXYXYXY. */ |
5b3e6663 PB |
2444 | v = i & 0xff; |
2445 | v |= v << 16; | |
2446 | if (i == v || i == (v | (v << 8))) | |
2447 | return TRUE; | |
d724c8f0 AS |
2448 | |
2449 | /* Allow repeated pattern 0xXY00XY00. */ | |
2450 | v = i & 0xff00; | |
2451 | v |= v << 16; | |
2452 | if (i == v) | |
2453 | return TRUE; | |
5b3e6663 | 2454 | } |
cce8749e | 2455 | |
f3bb6135 RE |
2456 | return FALSE; |
2457 | } | |
cce8749e | 2458 | |
6354dc9b | 2459 | /* Return true if I is a valid constant for the operation CODE. */ |
74bbc178 | 2460 | static int |
e32bac5b | 2461 | const_ok_for_op (HOST_WIDE_INT i, enum rtx_code code) |
e2c671ba RE |
2462 | { |
2463 | if (const_ok_for_arm (i)) | |
2464 | return 1; | |
2465 | ||
2466 | switch (code) | |
2467 | { | |
2468 | case PLUS: | |
d5a0a47b RE |
2469 | case COMPARE: |
2470 | case EQ: | |
2471 | case NE: | |
2472 | case GT: | |
2473 | case LE: | |
2474 | case LT: | |
2475 | case GE: | |
2476 | case GEU: | |
2477 | case LTU: | |
2478 | case GTU: | |
2479 | case LEU: | |
2480 | case UNORDERED: | |
2481 | case ORDERED: | |
2482 | case UNEQ: | |
2483 | case UNGE: | |
2484 | case UNLT: | |
2485 | case UNGT: | |
2486 | case UNLE: | |
e2c671ba RE |
2487 | return const_ok_for_arm (ARM_SIGN_EXTEND (-i)); |
2488 | ||
2489 | case MINUS: /* Should only occur with (MINUS I reg) => rsb */ | |
2490 | case XOR: | |
a7994a57 RR |
2491 | return 0; |
2492 | ||
e2c671ba | 2493 | case IOR: |
a7994a57 RR |
2494 | if (TARGET_THUMB2) |
2495 | return const_ok_for_arm (ARM_SIGN_EXTEND (~i)); | |
e2c671ba RE |
2496 | return 0; |
2497 | ||
2498 | case AND: | |
2499 | return const_ok_for_arm (ARM_SIGN_EXTEND (~i)); | |
2500 | ||
2501 | default: | |
e6d29d15 | 2502 | gcc_unreachable (); |
e2c671ba RE |
2503 | } |
2504 | } | |
2505 | ||
2506 | /* Emit a sequence of insns to handle a large constant. | |
2507 | CODE is the code of the operation required, it can be any of SET, PLUS, | |
2508 | IOR, AND, XOR, MINUS; | |
2509 | MODE is the mode in which the operation is being performed; | |
2510 | VAL is the integer to operate on; | |
2511 | SOURCE is the other operand (a register, or a null-pointer for SET); | |
2512 | SUBTARGETS means it is safe to create scratch registers if that will | |
2b835d68 RE |
2513 | either produce a simpler sequence, or we will want to cse the values. |
2514 | Return value is the number of insns emitted. */ | |
e2c671ba | 2515 | |
5b3e6663 | 2516 | /* ??? Tweak this for thumb2. */ |
e2c671ba | 2517 | int |
a406f566 | 2518 | arm_split_constant (enum rtx_code code, enum machine_mode mode, rtx insn, |
e32bac5b | 2519 | HOST_WIDE_INT val, rtx target, rtx source, int subtargets) |
2b835d68 | 2520 | { |
a406f566 MM |
2521 | rtx cond; |
2522 | ||
2523 | if (insn && GET_CODE (PATTERN (insn)) == COND_EXEC) | |
2524 | cond = COND_EXEC_TEST (PATTERN (insn)); | |
2525 | else | |
2526 | cond = NULL_RTX; | |
2527 | ||
2b835d68 RE |
2528 | if (subtargets || code == SET |
2529 | || (GET_CODE (target) == REG && GET_CODE (source) == REG | |
2530 | && REGNO (target) != REGNO (source))) | |
2531 | { | |
4b632bf1 | 2532 | /* After arm_reorg has been called, we can't fix up expensive |
05713b80 | 2533 | constants by pushing them into memory so we must synthesize |
4b632bf1 RE |
2534 | them in-line, regardless of the cost. This is only likely to |
2535 | be more costly on chips that have load delay slots and we are | |
2536 | compiling without running the scheduler (so no splitting | |
aec3cfba NC |
2537 | occurred before the final instruction emission). |
2538 | ||
2539 | Ref: gcc -O1 -mcpu=strongarm gcc.c-torture/compile/980506-2.c | |
aec3cfba | 2540 | */ |
5895f793 | 2541 | if (!after_arm_reorg |
a406f566 | 2542 | && !cond |
f676971a | 2543 | && (arm_gen_constant (code, mode, NULL_RTX, val, target, source, |
a406f566 | 2544 | 1, 0) |
1b78f575 RE |
2545 | > (arm_constant_limit (optimize_function_for_size_p (cfun)) |
2546 | + (code != SET)))) | |
2b835d68 RE |
2547 | { |
2548 | if (code == SET) | |
2549 | { | |
2550 | /* Currently SET is the only monadic value for CODE, all | |
2551 | the rest are diadic. */ | |
571191af PB |
2552 | if (TARGET_USE_MOVT) |
2553 | arm_emit_movpair (target, GEN_INT (val)); | |
2554 | else | |
2555 | emit_set_insn (target, GEN_INT (val)); | |
2556 | ||
2b835d68 RE |
2557 | return 1; |
2558 | } | |
2559 | else | |
2560 | { | |
2561 | rtx temp = subtargets ? gen_reg_rtx (mode) : target; | |
2562 | ||
571191af PB |
2563 | if (TARGET_USE_MOVT) |
2564 | arm_emit_movpair (temp, GEN_INT (val)); | |
2565 | else | |
2566 | emit_set_insn (temp, GEN_INT (val)); | |
2567 | ||
2b835d68 RE |
2568 | /* For MINUS, the value is subtracted from, since we never |
2569 | have subtraction of a constant. */ | |
2570 | if (code == MINUS) | |
d66437c5 | 2571 | emit_set_insn (target, gen_rtx_MINUS (mode, temp, source)); |
2b835d68 | 2572 | else |
d66437c5 RE |
2573 | emit_set_insn (target, |
2574 | gen_rtx_fmt_ee (code, mode, source, temp)); | |
2b835d68 RE |
2575 | return 2; |
2576 | } | |
2577 | } | |
2578 | } | |
2579 | ||
f676971a | 2580 | return arm_gen_constant (code, mode, cond, val, target, source, subtargets, |
a406f566 | 2581 | 1); |
2b835d68 RE |
2582 | } |
2583 | ||
162e4591 RE |
2584 | /* Return the number of instructions required to synthesize the given |
2585 | constant, if we start emitting them from bit-position I. */ | |
ceebdb09 | 2586 | static int |
e32bac5b | 2587 | count_insns_for_constant (HOST_WIDE_INT remainder, int i) |
ceebdb09 PB |
2588 | { |
2589 | HOST_WIDE_INT temp1; | |
162e4591 | 2590 | int step_size = TARGET_ARM ? 2 : 1; |
ceebdb09 | 2591 | int num_insns = 0; |
162e4591 RE |
2592 | |
2593 | gcc_assert (TARGET_ARM || i == 0); | |
2594 | ||
ceebdb09 PB |
2595 | do |
2596 | { | |
2597 | int end; | |
f676971a | 2598 | |
ceebdb09 PB |
2599 | if (i <= 0) |
2600 | i += 32; | |
162e4591 | 2601 | if (remainder & (((1 << step_size) - 1) << (i - step_size))) |
ceebdb09 PB |
2602 | { |
2603 | end = i - 8; | |
2604 | if (end < 0) | |
2605 | end += 32; | |
2606 | temp1 = remainder & ((0x0ff << end) | |
2607 | | ((i < end) ? (0xff >> (32 - end)) : 0)); | |
2608 | remainder &= ~temp1; | |
2609 | num_insns++; | |
162e4591 | 2610 | i -= 8 - step_size; |
ceebdb09 | 2611 | } |
162e4591 | 2612 | i -= step_size; |
ceebdb09 PB |
2613 | } while (remainder); |
2614 | return num_insns; | |
2615 | } | |
2616 | ||
162e4591 | 2617 | static int |
90e77553 | 2618 | find_best_start (unsigned HOST_WIDE_INT remainder) |
162e4591 RE |
2619 | { |
2620 | int best_consecutive_zeros = 0; | |
2621 | int i; | |
2622 | int best_start = 0; | |
2623 | ||
2624 | /* If we aren't targetting ARM, the best place to start is always at | |
2625 | the bottom. */ | |
2626 | if (! TARGET_ARM) | |
2627 | return 0; | |
2628 | ||
2629 | for (i = 0; i < 32; i += 2) | |
2630 | { | |
2631 | int consecutive_zeros = 0; | |
2632 | ||
2633 | if (!(remainder & (3 << i))) | |
2634 | { | |
2635 | while ((i < 32) && !(remainder & (3 << i))) | |
2636 | { | |
2637 | consecutive_zeros += 2; | |
2638 | i += 2; | |
2639 | } | |
2640 | if (consecutive_zeros > best_consecutive_zeros) | |
2641 | { | |
2642 | best_consecutive_zeros = consecutive_zeros; | |
2643 | best_start = i - consecutive_zeros; | |
2644 | } | |
2645 | i -= 2; | |
2646 | } | |
2647 | } | |
2648 | ||
2649 | /* So long as it won't require any more insns to do so, it's | |
2650 | desirable to emit a small constant (in bits 0...9) in the last | |
2651 | insn. This way there is more chance that it can be combined with | |
2652 | a later addressing insn to form a pre-indexed load or store | |
2653 | operation. Consider: | |
2654 | ||
2655 | *((volatile int *)0xe0000100) = 1; | |
2656 | *((volatile int *)0xe0000110) = 2; | |
2657 | ||
2658 | We want this to wind up as: | |
2659 | ||
2660 | mov rA, #0xe0000000 | |
2661 | mov rB, #1 | |
2662 | str rB, [rA, #0x100] | |
2663 | mov rB, #2 | |
2664 | str rB, [rA, #0x110] | |
2665 | ||
2666 | rather than having to synthesize both large constants from scratch. | |
2667 | ||
2668 | Therefore, we calculate how many insns would be required to emit | |
2669 | the constant starting from `best_start', and also starting from | |
2670 | zero (i.e. with bit 31 first to be output). If `best_start' doesn't | |
2671 | yield a shorter sequence, we may as well use zero. */ | |
2672 | if (best_start != 0 | |
2673 | && ((((unsigned HOST_WIDE_INT) 1) << best_start) < remainder) | |
2674 | && (count_insns_for_constant (remainder, 0) <= | |
2675 | count_insns_for_constant (remainder, best_start))) | |
2676 | best_start = 0; | |
2677 | ||
2678 | return best_start; | |
2679 | } | |
2680 | ||
a406f566 MM |
2681 | /* Emit an instruction with the indicated PATTERN. If COND is |
2682 | non-NULL, conditionalize the execution of the instruction on COND | |
2683 | being true. */ | |
2684 | ||
2685 | static void | |
2686 | emit_constant_insn (rtx cond, rtx pattern) | |
2687 | { | |
2688 | if (cond) | |
2689 | pattern = gen_rtx_COND_EXEC (VOIDmode, copy_rtx (cond), pattern); | |
2690 | emit_insn (pattern); | |
2691 | } | |
2692 | ||
2b835d68 RE |
2693 | /* As above, but extra parameter GENERATE which, if clear, suppresses |
2694 | RTL generation. */ | |
5b3e6663 | 2695 | /* ??? This needs more work for thumb2. */ |
1d6e90ac | 2696 | |
d5b7b3ae | 2697 | static int |
a406f566 | 2698 | arm_gen_constant (enum rtx_code code, enum machine_mode mode, rtx cond, |
e32bac5b RE |
2699 | HOST_WIDE_INT val, rtx target, rtx source, int subtargets, |
2700 | int generate) | |
e2c671ba | 2701 | { |
e2c671ba RE |
2702 | int can_invert = 0; |
2703 | int can_negate = 0; | |
162e4591 | 2704 | int final_invert = 0; |
e2c671ba | 2705 | int can_negate_initial = 0; |
e2c671ba RE |
2706 | int i; |
2707 | int num_bits_set = 0; | |
2708 | int set_sign_bit_copies = 0; | |
2709 | int clear_sign_bit_copies = 0; | |
2710 | int clear_zero_bit_copies = 0; | |
2711 | int set_zero_bit_copies = 0; | |
2712 | int insns = 0; | |
e2c671ba | 2713 | unsigned HOST_WIDE_INT temp1, temp2; |
30cf4896 | 2714 | unsigned HOST_WIDE_INT remainder = val & 0xffffffff; |
162e4591 | 2715 | int step_size = TARGET_ARM ? 2 : 1; |
e2c671ba | 2716 | |
d5b7b3ae | 2717 | /* Find out which operations are safe for a given CODE. Also do a quick |
e2c671ba RE |
2718 | check for degenerate cases; these can occur when DImode operations |
2719 | are split. */ | |
2720 | switch (code) | |
2721 | { | |
2722 | case SET: | |
2723 | can_invert = 1; | |
e2c671ba RE |
2724 | can_negate = 1; |
2725 | break; | |
2726 | ||
2727 | case PLUS: | |
2728 | can_negate = 1; | |
2729 | can_negate_initial = 1; | |
2730 | break; | |
2731 | ||
2732 | case IOR: | |
30cf4896 | 2733 | if (remainder == 0xffffffff) |
e2c671ba | 2734 | { |
2b835d68 | 2735 | if (generate) |
a406f566 MM |
2736 | emit_constant_insn (cond, |
2737 | gen_rtx_SET (VOIDmode, target, | |
2738 | GEN_INT (ARM_SIGN_EXTEND (val)))); | |
e2c671ba RE |
2739 | return 1; |
2740 | } | |
a7994a57 | 2741 | |
e2c671ba RE |
2742 | if (remainder == 0) |
2743 | { | |
2744 | if (reload_completed && rtx_equal_p (target, source)) | |
2745 | return 0; | |
a7994a57 | 2746 | |
2b835d68 | 2747 | if (generate) |
a406f566 MM |
2748 | emit_constant_insn (cond, |
2749 | gen_rtx_SET (VOIDmode, target, source)); | |
e2c671ba RE |
2750 | return 1; |
2751 | } | |
a7994a57 RR |
2752 | |
2753 | if (TARGET_THUMB2) | |
2754 | can_invert = 1; | |
e2c671ba RE |
2755 | break; |
2756 | ||
2757 | case AND: | |
2758 | if (remainder == 0) | |
2759 | { | |
2b835d68 | 2760 | if (generate) |
a406f566 MM |
2761 | emit_constant_insn (cond, |
2762 | gen_rtx_SET (VOIDmode, target, const0_rtx)); | |
e2c671ba RE |
2763 | return 1; |
2764 | } | |
30cf4896 | 2765 | if (remainder == 0xffffffff) |
e2c671ba RE |
2766 | { |
2767 | if (reload_completed && rtx_equal_p (target, source)) | |
2768 | return 0; | |
2b835d68 | 2769 | if (generate) |
a406f566 MM |
2770 | emit_constant_insn (cond, |
2771 | gen_rtx_SET (VOIDmode, target, source)); | |
e2c671ba RE |
2772 | return 1; |
2773 | } | |
2774 | can_invert = 1; | |
2775 | break; | |
2776 | ||
2777 | case XOR: | |
2778 | if (remainder == 0) | |
2779 | { | |
2780 | if (reload_completed && rtx_equal_p (target, source)) | |
2781 | return 0; | |
2b835d68 | 2782 | if (generate) |
a406f566 MM |
2783 | emit_constant_insn (cond, |
2784 | gen_rtx_SET (VOIDmode, target, source)); | |
e2c671ba RE |
2785 | return 1; |
2786 | } | |
e0b92319 | 2787 | |
162e4591 RE |
2788 | if (remainder == 0xffffffff) |
2789 | { | |
2790 | if (generate) | |
2791 | emit_constant_insn (cond, | |
2792 | gen_rtx_SET (VOIDmode, target, | |
2793 | gen_rtx_NOT (mode, source))); | |
2794 | return 1; | |
2795 | } | |
2796 | break; | |
e2c671ba RE |
2797 | |
2798 | case MINUS: | |
2799 | /* We treat MINUS as (val - source), since (source - val) is always | |
2800 | passed as (source + (-val)). */ | |
2801 | if (remainder == 0) | |
2802 | { | |
2b835d68 | 2803 | if (generate) |
a406f566 MM |
2804 | emit_constant_insn (cond, |
2805 | gen_rtx_SET (VOIDmode, target, | |
2806 | gen_rtx_NEG (mode, source))); | |
e2c671ba RE |
2807 | return 1; |
2808 | } | |
2809 | if (const_ok_for_arm (val)) | |
2810 | { | |
2b835d68 | 2811 | if (generate) |
a406f566 | 2812 | emit_constant_insn (cond, |
f676971a | 2813 | gen_rtx_SET (VOIDmode, target, |
a406f566 MM |
2814 | gen_rtx_MINUS (mode, GEN_INT (val), |
2815 | source))); | |
e2c671ba RE |
2816 | return 1; |
2817 | } | |
2818 | can_negate = 1; | |
2819 | ||
2820 | break; | |
2821 | ||
2822 | default: | |
e6d29d15 | 2823 | gcc_unreachable (); |
e2c671ba RE |
2824 | } |
2825 | ||
6354dc9b | 2826 | /* If we can do it in one insn get out quickly. */ |
e2c671ba RE |
2827 | if (const_ok_for_arm (val) |
2828 | || (can_negate_initial && const_ok_for_arm (-val)) | |
2829 | || (can_invert && const_ok_for_arm (~val))) | |
2830 | { | |
2b835d68 | 2831 | if (generate) |
a406f566 MM |
2832 | emit_constant_insn (cond, |
2833 | gen_rtx_SET (VOIDmode, target, | |
f676971a | 2834 | (source |
a406f566 MM |
2835 | ? gen_rtx_fmt_ee (code, mode, source, |
2836 | GEN_INT (val)) | |
2837 | : GEN_INT (val)))); | |
e2c671ba RE |
2838 | return 1; |
2839 | } | |
2840 | ||
e2c671ba | 2841 | /* Calculate a few attributes that may be useful for specific |
6354dc9b | 2842 | optimizations. */ |
a7994a57 | 2843 | /* Count number of leading zeros. */ |
e2c671ba RE |
2844 | for (i = 31; i >= 0; i--) |
2845 | { | |
2846 | if ((remainder & (1 << i)) == 0) | |
2847 | clear_sign_bit_copies++; | |
2848 | else | |
2849 | break; | |
2850 | } | |
2851 | ||
a7994a57 | 2852 | /* Count number of leading 1's. */ |
e2c671ba RE |
2853 | for (i = 31; i >= 0; i--) |
2854 | { | |
2855 | if ((remainder & (1 << i)) != 0) | |
2856 | set_sign_bit_copies++; | |
2857 | else | |
2858 | break; | |
2859 | } | |
2860 | ||
a7994a57 | 2861 | /* Count number of trailing zero's. */ |
e2c671ba RE |
2862 | for (i = 0; i <= 31; i++) |
2863 | { | |
2864 | if ((remainder & (1 << i)) == 0) | |
2865 | clear_zero_bit_copies++; | |
2866 | else | |
2867 | break; | |
2868 | } | |
2869 | ||
a7994a57 | 2870 | /* Count number of trailing 1's. */ |
e2c671ba RE |
2871 | for (i = 0; i <= 31; i++) |
2872 | { | |
2873 | if ((remainder & (1 << i)) != 0) | |
2874 | set_zero_bit_copies++; | |
2875 | else | |
2876 | break; | |
2877 | } | |
2878 | ||
2879 | switch (code) | |
2880 | { | |
2881 | case SET: | |
5b3e6663 PB |
2882 | /* See if we can use movw. */ |
2883 | if (arm_arch_thumb2 && (remainder & 0xffff0000) == 0) | |
2884 | { | |
2885 | if (generate) | |
2886 | emit_constant_insn (cond, gen_rtx_SET (VOIDmode, target, | |
2887 | GEN_INT (val))); | |
2888 | return 1; | |
2889 | } | |
2890 | ||
e2c671ba RE |
2891 | /* See if we can do this by sign_extending a constant that is known |
2892 | to be negative. This is a good, way of doing it, since the shift | |
2893 | may well merge into a subsequent insn. */ | |
2894 | if (set_sign_bit_copies > 1) | |
2895 | { | |
2896 | if (const_ok_for_arm | |
f676971a | 2897 | (temp1 = ARM_SIGN_EXTEND (remainder |
e2c671ba RE |
2898 | << (set_sign_bit_copies - 1)))) |
2899 | { | |
2b835d68 RE |
2900 | if (generate) |
2901 | { | |
d499463f | 2902 | rtx new_src = subtargets ? gen_reg_rtx (mode) : target; |
a406f566 | 2903 | emit_constant_insn (cond, |
f676971a | 2904 | gen_rtx_SET (VOIDmode, new_src, |
a406f566 MM |
2905 | GEN_INT (temp1))); |
2906 | emit_constant_insn (cond, | |
f676971a | 2907 | gen_ashrsi3 (target, new_src, |
a406f566 | 2908 | GEN_INT (set_sign_bit_copies - 1))); |
2b835d68 | 2909 | } |
e2c671ba RE |
2910 | return 2; |
2911 | } | |
2912 | /* For an inverted constant, we will need to set the low bits, | |
2913 | these will be shifted out of harm's way. */ | |
2914 | temp1 |= (1 << (set_sign_bit_copies - 1)) - 1; | |
2915 | if (const_ok_for_arm (~temp1)) | |
2916 | { | |
2b835d68 RE |
2917 | if (generate) |
2918 | { | |
d499463f | 2919 | rtx new_src = subtargets ? gen_reg_rtx (mode) : target; |
a406f566 MM |
2920 | emit_constant_insn (cond, |
2921 | gen_rtx_SET (VOIDmode, new_src, | |
2922 | GEN_INT (temp1))); | |
2923 | emit_constant_insn (cond, | |
f676971a | 2924 | gen_ashrsi3 (target, new_src, |
a406f566 | 2925 | GEN_INT (set_sign_bit_copies - 1))); |
2b835d68 | 2926 | } |
e2c671ba RE |
2927 | return 2; |
2928 | } | |
2929 | } | |
2930 | ||
c87e6352 RE |
2931 | /* See if we can calculate the value as the difference between two |
2932 | valid immediates. */ | |
2933 | if (clear_sign_bit_copies + clear_zero_bit_copies <= 16) | |
2934 | { | |
2935 | int topshift = clear_sign_bit_copies & ~1; | |
2936 | ||
fa2c88a0 RE |
2937 | temp1 = ARM_SIGN_EXTEND ((remainder + (0x00800000 >> topshift)) |
2938 | & (0xff000000 >> topshift)); | |
c87e6352 RE |
2939 | |
2940 | /* If temp1 is zero, then that means the 9 most significant | |
2941 | bits of remainder were 1 and we've caused it to overflow. | |
2942 | When topshift is 0 we don't need to do anything since we | |
2943 | can borrow from 'bit 32'. */ | |
2944 | if (temp1 == 0 && topshift != 0) | |
2945 | temp1 = 0x80000000 >> (topshift - 1); | |
2946 | ||
fa2c88a0 | 2947 | temp2 = ARM_SIGN_EXTEND (temp1 - remainder); |
e0b92319 | 2948 | |
c87e6352 RE |
2949 | if (const_ok_for_arm (temp2)) |
2950 | { | |
2951 | if (generate) | |
2952 | { | |
2953 | rtx new_src = subtargets ? gen_reg_rtx (mode) : target; | |
2954 | emit_constant_insn (cond, | |
2955 | gen_rtx_SET (VOIDmode, new_src, | |
2956 | GEN_INT (temp1))); | |
2957 | emit_constant_insn (cond, | |
2958 | gen_addsi3 (target, new_src, | |
2959 | GEN_INT (-temp2))); | |
2960 | } | |
2961 | ||
2962 | return 2; | |
2963 | } | |
2964 | } | |
2965 | ||
e2c671ba RE |
2966 | /* See if we can generate this by setting the bottom (or the top) |
2967 | 16 bits, and then shifting these into the other half of the | |
2968 | word. We only look for the simplest cases, to do more would cost | |
2969 | too much. Be careful, however, not to generate this when the | |
2970 | alternative would take fewer insns. */ | |
30cf4896 | 2971 | if (val & 0xffff0000) |
e2c671ba | 2972 | { |
30cf4896 | 2973 | temp1 = remainder & 0xffff0000; |
e2c671ba RE |
2974 | temp2 = remainder & 0x0000ffff; |
2975 | ||
6354dc9b | 2976 | /* Overlaps outside this range are best done using other methods. */ |
e2c671ba RE |
2977 | for (i = 9; i < 24; i++) |
2978 | { | |
30cf4896 | 2979 | if ((((temp2 | (temp2 << i)) & 0xffffffff) == remainder) |
5895f793 | 2980 | && !const_ok_for_arm (temp2)) |
e2c671ba | 2981 | { |
d499463f RE |
2982 | rtx new_src = (subtargets |
2983 | ? (generate ? gen_reg_rtx (mode) : NULL_RTX) | |
2984 | : target); | |
a406f566 | 2985 | insns = arm_gen_constant (code, mode, cond, temp2, new_src, |
2b835d68 | 2986 | source, subtargets, generate); |
e2c671ba | 2987 | source = new_src; |
2b835d68 | 2988 | if (generate) |
f676971a | 2989 | emit_constant_insn |
a406f566 MM |
2990 | (cond, |
2991 | gen_rtx_SET | |
2992 | (VOIDmode, target, | |
2993 | gen_rtx_IOR (mode, | |
2994 | gen_rtx_ASHIFT (mode, source, | |
2995 | GEN_INT (i)), | |
2996 | source))); | |
e2c671ba RE |
2997 | return insns + 1; |
2998 | } | |
2999 | } | |
3000 | ||
6354dc9b | 3001 | /* Don't duplicate cases already considered. */ |
e2c671ba RE |
3002 | for (i = 17; i < 24; i++) |
3003 | { | |
3004 | if (((temp1 | (temp1 >> i)) == remainder) | |
5895f793 | 3005 | && !const_ok_for_arm (temp1)) |
e2c671ba | 3006 | { |
d499463f RE |
3007 | rtx new_src = (subtargets |
3008 | ? (generate ? gen_reg_rtx (mode) : NULL_RTX) | |
3009 | : target); | |
a406f566 | 3010 | insns = arm_gen_constant (code, mode, cond, temp1, new_src, |
2b835d68 | 3011 | source, subtargets, generate); |
e2c671ba | 3012 | source = new_src; |
2b835d68 | 3013 | if (generate) |
a406f566 MM |
3014 | emit_constant_insn |
3015 | (cond, | |
3016 | gen_rtx_SET (VOIDmode, target, | |
43cffd11 RE |
3017 | gen_rtx_IOR |
3018 | (mode, | |
3019 | gen_rtx_LSHIFTRT (mode, source, | |
3020 | GEN_INT (i)), | |
3021 | source))); | |
e2c671ba RE |
3022 | return insns + 1; |
3023 | } | |
3024 | } | |
3025 | } | |
3026 | break; | |
3027 | ||
3028 | case IOR: | |
3029 | case XOR: | |
7b64da89 RE |
3030 | /* If we have IOR or XOR, and the constant can be loaded in a |
3031 | single instruction, and we can find a temporary to put it in, | |
e2c671ba RE |
3032 | then this can be done in two instructions instead of 3-4. */ |
3033 | if (subtargets | |
d499463f | 3034 | /* TARGET can't be NULL if SUBTARGETS is 0 */ |
5895f793 | 3035 | || (reload_completed && !reg_mentioned_p (target, source))) |
e2c671ba | 3036 | { |
5895f793 | 3037 | if (const_ok_for_arm (ARM_SIGN_EXTEND (~val))) |
e2c671ba | 3038 | { |
2b835d68 RE |
3039 | if (generate) |
3040 | { | |
3041 | rtx sub = subtargets ? gen_reg_rtx (mode) : target; | |
e2c671ba | 3042 | |
a406f566 | 3043 | emit_constant_insn (cond, |
f676971a | 3044 | gen_rtx_SET (VOIDmode, sub, |
a406f566 MM |
3045 | GEN_INT (val))); |
3046 | emit_constant_insn (cond, | |
f676971a | 3047 | gen_rtx_SET (VOIDmode, target, |
a406f566 MM |
3048 | gen_rtx_fmt_ee (code, mode, |
3049 | source, sub))); | |
2b835d68 | 3050 | } |
e2c671ba RE |
3051 | return 2; |
3052 | } | |
3053 | } | |
3054 | ||
3055 | if (code == XOR) | |
3056 | break; | |
3057 | ||
a7994a57 RR |
3058 | /* Convert. |
3059 | x = y | constant ( which is composed of set_sign_bit_copies of leading 1s | |
3060 | and the remainder 0s for e.g. 0xfff00000) | |
3061 | x = ~(~(y ashift set_sign_bit_copies) lshiftrt set_sign_bit_copies) | |
3062 | ||
3063 | This can be done in 2 instructions by using shifts with mov or mvn. | |
3064 | e.g. for | |
3065 | x = x | 0xfff00000; | |
3066 | we generate. | |
3067 | mvn r0, r0, asl #12 | |
3068 | mvn r0, r0, lsr #12 */ | |
e2c671ba RE |
3069 | if (set_sign_bit_copies > 8 |
3070 | && (val & (-1 << (32 - set_sign_bit_copies))) == val) | |
3071 | { | |
2b835d68 RE |
3072 | if (generate) |
3073 | { | |
3074 | rtx sub = subtargets ? gen_reg_rtx (mode) : target; | |
3075 | rtx shift = GEN_INT (set_sign_bit_copies); | |
3076 | ||
f676971a | 3077 | emit_constant_insn |
a406f566 MM |
3078 | (cond, |
3079 | gen_rtx_SET (VOIDmode, sub, | |
f676971a | 3080 | gen_rtx_NOT (mode, |
a406f566 | 3081 | gen_rtx_ASHIFT (mode, |
f676971a | 3082 | source, |
a406f566 | 3083 | shift)))); |
f676971a | 3084 | emit_constant_insn |
a406f566 MM |
3085 | (cond, |
3086 | gen_rtx_SET (VOIDmode, target, | |
3087 | gen_rtx_NOT (mode, | |
3088 | gen_rtx_LSHIFTRT (mode, sub, | |
3089 | shift)))); | |
2b835d68 | 3090 | } |
e2c671ba RE |
3091 | return 2; |
3092 | } | |
3093 | ||
a7994a57 RR |
3094 | /* Convert |
3095 | x = y | constant (which has set_zero_bit_copies number of trailing ones). | |
3096 | to | |
3097 | x = ~((~y lshiftrt set_zero_bit_copies) ashift set_zero_bit_copies). | |
3098 | ||
3099 | For eg. r0 = r0 | 0xfff | |
3100 | mvn r0, r0, lsr #12 | |
3101 | mvn r0, r0, asl #12 | |
3102 | ||
3103 | */ | |
e2c671ba RE |
3104 | if (set_zero_bit_copies > 8 |
3105 | && (remainder & ((1 << set_zero_bit_copies) - 1)) == remainder) | |
3106 | { | |
2b835d68 RE |
3107 | if (generate) |
3108 | { | |
3109 | rtx sub = subtargets ? gen_reg_rtx (mode) : target; | |
3110 | rtx shift = GEN_INT (set_zero_bit_copies); | |
3111 | ||
a406f566 MM |
3112 | emit_constant_insn |
3113 | (cond, | |
3114 | gen_rtx_SET (VOIDmode, sub, | |
3115 | gen_rtx_NOT (mode, | |
3116 | gen_rtx_LSHIFTRT (mode, | |
3117 | source, | |
3118 | shift)))); | |
f676971a | 3119 | emit_constant_insn |
a406f566 MM |
3120 | (cond, |
3121 | gen_rtx_SET (VOIDmode, target, | |
3122 | gen_rtx_NOT (mode, | |
3123 | gen_rtx_ASHIFT (mode, sub, | |
3124 | shift)))); | |
2b835d68 | 3125 | } |
e2c671ba RE |
3126 | return 2; |
3127 | } | |
3128 | ||
a7994a57 RR |
3129 | /* This will never be reached for Thumb2 because orn is a valid |
3130 | instruction. This is for Thumb1 and the ARM 32 bit cases. | |
3131 | ||
3132 | x = y | constant (such that ~constant is a valid constant) | |
3133 | Transform this to | |
3134 | x = ~(~y & ~constant). | |
3135 | */ | |
5895f793 | 3136 | if (const_ok_for_arm (temp1 = ARM_SIGN_EXTEND (~val))) |
e2c671ba | 3137 | { |
2b835d68 RE |
3138 | if (generate) |
3139 | { | |
3140 | rtx sub = subtargets ? gen_reg_rtx (mode) : target; | |
a406f566 MM |
3141 | emit_constant_insn (cond, |
3142 | gen_rtx_SET (VOIDmode, sub, | |
3143 | gen_rtx_NOT (mode, source))); | |
2b835d68 RE |
3144 | source = sub; |
3145 | if (subtargets) | |
3146 | sub = gen_reg_rtx (mode); | |
a406f566 MM |
3147 | emit_constant_insn (cond, |
3148 | gen_rtx_SET (VOIDmode, sub, | |
f676971a | 3149 | gen_rtx_AND (mode, source, |
a406f566 MM |
3150 | GEN_INT (temp1)))); |
3151 | emit_constant_insn (cond, | |
3152 | gen_rtx_SET (VOIDmode, target, | |
3153 | gen_rtx_NOT (mode, sub))); | |
2b835d68 | 3154 | } |
e2c671ba RE |
3155 | return 3; |
3156 | } | |
3157 | break; | |
3158 | ||
3159 | case AND: | |
3160 | /* See if two shifts will do 2 or more insn's worth of work. */ | |
3161 | if (clear_sign_bit_copies >= 16 && clear_sign_bit_copies < 24) | |
3162 | { | |
30cf4896 | 3163 | HOST_WIDE_INT shift_mask = ((0xffffffff |
e2c671ba | 3164 | << (32 - clear_sign_bit_copies)) |
30cf4896 | 3165 | & 0xffffffff); |
e2c671ba | 3166 | |
30cf4896 | 3167 | if ((remainder | shift_mask) != 0xffffffff) |
e2c671ba | 3168 | { |
2b835d68 RE |
3169 | if (generate) |
3170 | { | |
d499463f | 3171 | rtx new_src = subtargets ? gen_reg_rtx (mode) : target; |
f676971a | 3172 | insns = arm_gen_constant (AND, mode, cond, |
a406f566 | 3173 | remainder | shift_mask, |
d499463f RE |
3174 | new_src, source, subtargets, 1); |
3175 | source = new_src; | |
2b835d68 RE |
3176 | } |
3177 | else | |
d499463f RE |
3178 | { |
3179 | rtx targ = subtargets ? NULL_RTX : target; | |
a406f566 MM |
3180 | insns = arm_gen_constant (AND, mode, cond, |
3181 | remainder | shift_mask, | |
d499463f RE |
3182 | targ, source, subtargets, 0); |
3183 | } | |
2b835d68 RE |
3184 | } |
3185 | ||
3186 | if (generate) | |
3187 | { | |
d499463f RE |
3188 | rtx new_src = subtargets ? gen_reg_rtx (mode) : target; |
3189 | rtx shift = GEN_INT (clear_sign_bit_copies); | |
3190 | ||
3191 | emit_insn (gen_ashlsi3 (new_src, source, shift)); | |
3192 | emit_insn (gen_lshrsi3 (target, new_src, shift)); | |
e2c671ba RE |
3193 | } |
3194 | ||
e2c671ba RE |
3195 | return insns + 2; |
3196 | } | |
3197 | ||
3198 | if (clear_zero_bit_copies >= 16 && clear_zero_bit_copies < 24) | |
3199 | { | |
3200 | HOST_WIDE_INT shift_mask = (1 << clear_zero_bit_copies) - 1; | |
f676971a | 3201 | |
30cf4896 | 3202 | if ((remainder | shift_mask) != 0xffffffff) |
e2c671ba | 3203 | { |
2b835d68 RE |
3204 | if (generate) |
3205 | { | |
d499463f RE |
3206 | rtx new_src = subtargets ? gen_reg_rtx (mode) : target; |
3207 | ||
a406f566 MM |
3208 | insns = arm_gen_constant (AND, mode, cond, |
3209 | remainder | shift_mask, | |
d499463f RE |
3210 | new_src, source, subtargets, 1); |
3211 | source = new_src; | |
2b835d68 RE |
3212 | } |
3213 | else | |
d499463f RE |
3214 | { |
3215 | rtx targ = subtargets ? NULL_RTX : target; | |
3216 | ||
a406f566 MM |
3217 | insns = arm_gen_constant (AND, mode, cond, |
3218 | remainder | shift_mask, | |
d499463f RE |
3219 | targ, source, subtargets, 0); |
3220 | } | |
2b835d68 RE |
3221 | } |
3222 | ||
3223 | if (generate) | |
3224 | { | |
d499463f RE |
3225 | rtx new_src = subtargets ? gen_reg_rtx (mode) : target; |
3226 | rtx shift = GEN_INT (clear_zero_bit_copies); | |
3227 | ||
3228 | emit_insn (gen_lshrsi3 (new_src, source, shift)); | |
3229 | emit_insn (gen_ashlsi3 (target, new_src, shift)); | |
e2c671ba RE |
3230 | } |
3231 | ||
e2c671ba RE |
3232 | return insns + 2; |
3233 | } | |
3234 | ||
3235 | break; | |
3236 | ||
3237 | default: | |
3238 | break; | |
3239 | } | |
3240 | ||
3241 | for (i = 0; i < 32; i++) | |
3242 | if (remainder & (1 << i)) | |
3243 | num_bits_set++; | |
3244 | ||
a7994a57 RR |
3245 | if ((code == AND) |
3246 | || (code != IOR && can_invert && num_bits_set > 16)) | |
162e4591 | 3247 | remainder ^= 0xffffffff; |
e2c671ba | 3248 | else if (code == PLUS && num_bits_set > 16) |
30cf4896 | 3249 | remainder = (-remainder) & 0xffffffff; |
162e4591 RE |
3250 | |
3251 | /* For XOR, if more than half the bits are set and there's a sequence | |
3252 | of more than 8 consecutive ones in the pattern then we can XOR by the | |
3253 | inverted constant and then invert the final result; this may save an | |
3254 | instruction and might also lead to the final mvn being merged with | |
3255 | some other operation. */ | |
3256 | else if (code == XOR && num_bits_set > 16 | |
3257 | && (count_insns_for_constant (remainder ^ 0xffffffff, | |
3258 | find_best_start | |
3259 | (remainder ^ 0xffffffff)) | |
3260 | < count_insns_for_constant (remainder, | |
3261 | find_best_start (remainder)))) | |
3262 | { | |
3263 | remainder ^= 0xffffffff; | |
3264 | final_invert = 1; | |
3265 | } | |
e2c671ba RE |
3266 | else |
3267 | { | |
3268 | can_invert = 0; | |
3269 | can_negate = 0; | |
3270 | } | |
3271 | ||
3272 | /* Now try and find a way of doing the job in either two or three | |
3273 | instructions. | |
3274 | We start by looking for the largest block of zeros that are aligned on | |
3275 | a 2-bit boundary, we then fill up the temps, wrapping around to the | |
3276 | top of the word when we drop off the bottom. | |
5b3e6663 PB |
3277 | In the worst case this code should produce no more than four insns. |
3278 | Thumb-2 constants are shifted, not rotated, so the MSB is always the | |
3279 | best place to start. */ | |
3280 | ||
3281 | /* ??? Use thumb2 replicated constants when the high and low halfwords are | |
3282 | the same. */ | |
e2c671ba | 3283 | { |
ceebdb09 | 3284 | /* Now start emitting the insns. */ |
162e4591 | 3285 | i = find_best_start (remainder); |
e2c671ba RE |
3286 | do |
3287 | { | |
3288 | int end; | |
3289 | ||
3290 | if (i <= 0) | |
3291 | i += 32; | |
3292 | if (remainder & (3 << (i - 2))) | |
3293 | { | |
3294 | end = i - 8; | |
3295 | if (end < 0) | |
3296 | end += 32; | |
3297 | temp1 = remainder & ((0x0ff << end) | |
3298 | | ((i < end) ? (0xff >> (32 - end)) : 0)); | |
3299 | remainder &= ~temp1; | |
3300 | ||
d499463f | 3301 | if (generate) |
e2c671ba | 3302 | { |
9503f3d1 RH |
3303 | rtx new_src, temp1_rtx; |
3304 | ||
3305 | if (code == SET || code == MINUS) | |
3306 | { | |
3307 | new_src = (subtargets ? gen_reg_rtx (mode) : target); | |
96ae8197 | 3308 | if (can_invert && code != MINUS) |
9503f3d1 RH |
3309 | temp1 = ~temp1; |
3310 | } | |
3311 | else | |
3312 | { | |
162e4591 | 3313 | if ((final_invert || remainder) && subtargets) |
9503f3d1 | 3314 | new_src = gen_reg_rtx (mode); |
96ae8197 NC |
3315 | else |
3316 | new_src = target; | |
9503f3d1 RH |
3317 | if (can_invert) |
3318 | temp1 = ~temp1; | |
3319 | else if (can_negate) | |
3320 | temp1 = -temp1; | |
3321 | } | |
3322 | ||
3323 | temp1 = trunc_int_for_mode (temp1, mode); | |
3324 | temp1_rtx = GEN_INT (temp1); | |
d499463f RE |
3325 | |
3326 | if (code == SET) | |
9503f3d1 | 3327 | ; |
d499463f | 3328 | else if (code == MINUS) |
9503f3d1 | 3329 | temp1_rtx = gen_rtx_MINUS (mode, temp1_rtx, source); |
d499463f | 3330 | else |
9503f3d1 RH |
3331 | temp1_rtx = gen_rtx_fmt_ee (code, mode, source, temp1_rtx); |
3332 | ||
a406f566 | 3333 | emit_constant_insn (cond, |
f676971a | 3334 | gen_rtx_SET (VOIDmode, new_src, |
a406f566 | 3335 | temp1_rtx)); |
d499463f | 3336 | source = new_src; |
e2c671ba RE |
3337 | } |
3338 | ||
d499463f RE |
3339 | if (code == SET) |
3340 | { | |
3341 | can_invert = 0; | |
3342 | code = PLUS; | |
3343 | } | |
3344 | else if (code == MINUS) | |
3345 | code = PLUS; | |
3346 | ||
e2c671ba | 3347 | insns++; |
162e4591 | 3348 | i -= 8 - step_size; |
e2c671ba | 3349 | } |
7a085dce | 3350 | /* Arm allows rotates by a multiple of two. Thumb-2 allows arbitrary |
5b3e6663 | 3351 | shifts. */ |
162e4591 | 3352 | i -= step_size; |
1d6e90ac NC |
3353 | } |
3354 | while (remainder); | |
e2c671ba | 3355 | } |
1d6e90ac | 3356 | |
162e4591 RE |
3357 | if (final_invert) |
3358 | { | |
3359 | if (generate) | |
3360 | emit_constant_insn (cond, gen_rtx_SET (VOIDmode, target, | |
3361 | gen_rtx_NOT (mode, source))); | |
3362 | insns++; | |
3363 | } | |
3364 | ||
e2c671ba RE |
3365 | return insns; |
3366 | } | |
3367 | ||
bd9c7e23 RE |
3368 | /* Canonicalize a comparison so that we are more likely to recognize it. |
3369 | This can be done for a few constant compares, where we can make the | |
3370 | immediate value easier to load. */ | |
1d6e90ac | 3371 | |
bd9c7e23 | 3372 | enum rtx_code |
73160ba9 | 3373 | arm_canonicalize_comparison (enum rtx_code code, rtx *op0, rtx *op1) |
bd9c7e23 | 3374 | { |
73160ba9 DJ |
3375 | enum machine_mode mode; |
3376 | unsigned HOST_WIDE_INT i, maxval; | |
3377 | ||
3378 | mode = GET_MODE (*op0); | |
3379 | if (mode == VOIDmode) | |
3380 | mode = GET_MODE (*op1); | |
3381 | ||
a14b88bb | 3382 | maxval = (((unsigned HOST_WIDE_INT) 1) << (GET_MODE_BITSIZE(mode) - 1)) - 1; |
bd9c7e23 | 3383 | |
73160ba9 DJ |
3384 | /* For DImode, we have GE/LT/GEU/LTU comparisons. In ARM mode |
3385 | we can also use cmp/cmpeq for GTU/LEU. GT/LE must be either | |
3386 | reversed or (for constant OP1) adjusted to GE/LT. Similarly | |
3387 | for GTU/LEU in Thumb mode. */ | |
3388 | if (mode == DImode) | |
3389 | { | |
3390 | rtx tem; | |
3391 | ||
3392 | /* To keep things simple, always use the Cirrus cfcmp64 if it is | |
3393 | available. */ | |
3394 | if (TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK) | |
3395 | return code; | |
3396 | ||
3397 | if (code == GT || code == LE | |
3398 | || (!TARGET_ARM && (code == GTU || code == LEU))) | |
3399 | { | |
3400 | /* Missing comparison. First try to use an available | |
3401 | comparison. */ | |
3402 | if (GET_CODE (*op1) == CONST_INT) | |
3403 | { | |
3404 | i = INTVAL (*op1); | |
3405 | switch (code) | |
3406 | { | |
3407 | case GT: | |
3408 | case LE: | |
3409 | if (i != maxval | |
3410 | && arm_const_double_by_immediates (GEN_INT (i + 1))) | |
3411 | { | |
3412 | *op1 = GEN_INT (i + 1); | |
3413 | return code == GT ? GE : LT; | |
3414 | } | |
3415 | break; | |
3416 | case GTU: | |
3417 | case LEU: | |
3418 | if (i != ~((unsigned HOST_WIDE_INT) 0) | |
3419 | && arm_const_double_by_immediates (GEN_INT (i + 1))) | |
3420 | { | |
3421 | *op1 = GEN_INT (i + 1); | |
3422 | return code == GTU ? GEU : LTU; | |
3423 | } | |
3424 | break; | |
3425 | default: | |
3426 | gcc_unreachable (); | |
3427 | } | |
3428 | } | |
3429 | ||
3430 | /* If that did not work, reverse the condition. */ | |
3431 | tem = *op0; | |
3432 | *op0 = *op1; | |
3433 | *op1 = tem; | |
3434 | return swap_condition (code); | |
3435 | } | |
3436 | ||
3437 | return code; | |
3438 | } | |
3439 | ||
3440 | /* Comparisons smaller than DImode. Only adjust comparisons against | |
3441 | an out-of-range constant. */ | |
3442 | if (GET_CODE (*op1) != CONST_INT | |
3443 | || const_ok_for_arm (INTVAL (*op1)) | |
3444 | || const_ok_for_arm (- INTVAL (*op1))) | |
3445 | return code; | |
3446 | ||
3447 | i = INTVAL (*op1); | |
3448 | ||
bd9c7e23 RE |
3449 | switch (code) |
3450 | { | |
3451 | case EQ: | |
3452 | case NE: | |
3453 | return code; | |
3454 | ||
3455 | case GT: | |
3456 | case LE: | |
a14b88bb | 3457 | if (i != maxval |
5895f793 | 3458 | && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1)))) |
bd9c7e23 | 3459 | { |
5895f793 | 3460 | *op1 = GEN_INT (i + 1); |
bd9c7e23 RE |
3461 | return code == GT ? GE : LT; |
3462 | } | |
3463 | break; | |
3464 | ||
3465 | case GE: | |
3466 | case LT: | |
a14b88bb | 3467 | if (i != ~maxval |
5895f793 | 3468 | && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1)))) |
bd9c7e23 | 3469 | { |
5895f793 | 3470 | *op1 = GEN_INT (i - 1); |
bd9c7e23 RE |
3471 | return code == GE ? GT : LE; |
3472 | } | |
3473 | break; | |
3474 | ||
3475 | case GTU: | |
3476 | case LEU: | |
30cf4896 | 3477 | if (i != ~((unsigned HOST_WIDE_INT) 0) |
5895f793 | 3478 | && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1)))) |
bd9c7e23 RE |
3479 | { |
3480 | *op1 = GEN_INT (i + 1); | |
3481 | return code == GTU ? GEU : LTU; | |
3482 | } | |
3483 | break; | |
3484 | ||
3485 | case GEU: | |
3486 | case LTU: | |
3487 | if (i != 0 | |
5895f793 | 3488 | && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1)))) |
bd9c7e23 RE |
3489 | { |
3490 | *op1 = GEN_INT (i - 1); | |
3491 | return code == GEU ? GTU : LEU; | |
3492 | } | |
3493 | break; | |
3494 | ||
3495 | default: | |
e6d29d15 | 3496 | gcc_unreachable (); |
bd9c7e23 RE |
3497 | } |
3498 | ||
3499 | return code; | |
3500 | } | |
bd9c7e23 | 3501 | |
d4453b7a PB |
3502 | |
3503 | /* Define how to find the value returned by a function. */ | |
3504 | ||
390b17c2 RE |
3505 | static rtx |
3506 | arm_function_value(const_tree type, const_tree func, | |
3507 | bool outgoing ATTRIBUTE_UNUSED) | |
d4453b7a PB |
3508 | { |
3509 | enum machine_mode mode; | |
3510 | int unsignedp ATTRIBUTE_UNUSED; | |
3511 | rtx r ATTRIBUTE_UNUSED; | |
3512 | ||
d4453b7a | 3513 | mode = TYPE_MODE (type); |
390b17c2 RE |
3514 | |
3515 | if (TARGET_AAPCS_BASED) | |
3516 | return aapcs_allocate_return_reg (mode, type, func); | |
3517 | ||
d4453b7a PB |
3518 | /* Promote integer types. */ |
3519 | if (INTEGRAL_TYPE_P (type)) | |
cde0f3fd | 3520 | mode = arm_promote_function_mode (type, mode, &unsignedp, func, 1); |
866af8a9 JB |
3521 | |
3522 | /* Promotes small structs returned in a register to full-word size | |
3523 | for big-endian AAPCS. */ | |
3524 | if (arm_return_in_msb (type)) | |
3525 | { | |
3526 | HOST_WIDE_INT size = int_size_in_bytes (type); | |
3527 | if (size % UNITS_PER_WORD != 0) | |
3528 | { | |
3529 | size += UNITS_PER_WORD - size % UNITS_PER_WORD; | |
3530 | mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0); | |
3531 | } | |
3532 | } | |
e0b92319 | 3533 | |
390b17c2 RE |
3534 | return LIBCALL_VALUE (mode); |
3535 | } | |
3536 | ||
3537 | static int | |
3538 | libcall_eq (const void *p1, const void *p2) | |
3539 | { | |
3540 | return rtx_equal_p ((const_rtx) p1, (const_rtx) p2); | |
3541 | } | |
3542 | ||
3543 | static hashval_t | |
3544 | libcall_hash (const void *p1) | |
3545 | { | |
3546 | return hash_rtx ((const_rtx) p1, VOIDmode, NULL, NULL, FALSE); | |
3547 | } | |
3548 | ||
3549 | static void | |
3550 | add_libcall (htab_t htab, rtx libcall) | |
3551 | { | |
3552 | *htab_find_slot (htab, libcall, INSERT) = libcall; | |
3553 | } | |
3554 | ||
3555 | static bool | |
7fc6a96b | 3556 | arm_libcall_uses_aapcs_base (const_rtx libcall) |
390b17c2 RE |
3557 | { |
3558 | static bool init_done = false; | |
3559 | static htab_t libcall_htab; | |
3560 | ||
3561 | if (!init_done) | |
3562 | { | |
3563 | init_done = true; | |
3564 | ||
3565 | libcall_htab = htab_create (31, libcall_hash, libcall_eq, | |
3566 | NULL); | |
3567 | add_libcall (libcall_htab, | |
3568 | convert_optab_libfunc (sfloat_optab, SFmode, SImode)); | |
3569 | add_libcall (libcall_htab, | |
3570 | convert_optab_libfunc (sfloat_optab, DFmode, SImode)); | |
3571 | add_libcall (libcall_htab, | |
3572 | convert_optab_libfunc (sfloat_optab, SFmode, DImode)); | |
3573 | add_libcall (libcall_htab, | |
3574 | convert_optab_libfunc (sfloat_optab, DFmode, DImode)); | |
3575 | ||
3576 | add_libcall (libcall_htab, | |
3577 | convert_optab_libfunc (ufloat_optab, SFmode, SImode)); | |
3578 | add_libcall (libcall_htab, | |
3579 | convert_optab_libfunc (ufloat_optab, DFmode, SImode)); | |
3580 | add_libcall (libcall_htab, | |
3581 | convert_optab_libfunc (ufloat_optab, SFmode, DImode)); | |
3582 | add_libcall (libcall_htab, | |
3583 | convert_optab_libfunc (ufloat_optab, DFmode, DImode)); | |
3584 | ||
3585 | add_libcall (libcall_htab, | |
3586 | convert_optab_libfunc (sext_optab, SFmode, HFmode)); | |
3587 | add_libcall (libcall_htab, | |
3588 | convert_optab_libfunc (trunc_optab, HFmode, SFmode)); | |
3589 | add_libcall (libcall_htab, | |
3590 | convert_optab_libfunc (sfix_optab, DImode, DFmode)); | |
3591 | add_libcall (libcall_htab, | |
3592 | convert_optab_libfunc (ufix_optab, DImode, DFmode)); | |
3593 | add_libcall (libcall_htab, | |
3594 | convert_optab_libfunc (sfix_optab, DImode, SFmode)); | |
3595 | add_libcall (libcall_htab, | |
3596 | convert_optab_libfunc (ufix_optab, DImode, SFmode)); | |
3597 | } | |
3598 | ||
3599 | return libcall && htab_find (libcall_htab, libcall) != NULL; | |
3600 | } | |
3601 | ||
3602 | rtx | |
7fc6a96b | 3603 | arm_libcall_value (enum machine_mode mode, const_rtx libcall) |
390b17c2 RE |
3604 | { |
3605 | if (TARGET_AAPCS_BASED && arm_pcs_default != ARM_PCS_AAPCS | |
3606 | && GET_MODE_CLASS (mode) == MODE_FLOAT) | |
3607 | { | |
3608 | /* The following libcalls return their result in integer registers, | |
3609 | even though they return a floating point value. */ | |
3610 | if (arm_libcall_uses_aapcs_base (libcall)) | |
3611 | return gen_rtx_REG (mode, ARG_REGISTER(1)); | |
3612 | ||
3613 | } | |
3614 | ||
3615 | return LIBCALL_VALUE (mode); | |
d4453b7a PB |
3616 | } |
3617 | ||
e0b92319 | 3618 | /* Determine the amount of memory needed to store the possible return |
9f7bf991 RE |
3619 | registers of an untyped call. */ |
3620 | int | |
3621 | arm_apply_result_size (void) | |
3622 | { | |
3623 | int size = 16; | |
3624 | ||
390b17c2 | 3625 | if (TARGET_32BIT) |
9f7bf991 RE |
3626 | { |
3627 | if (TARGET_HARD_FLOAT_ABI) | |
3628 | { | |
390b17c2 RE |
3629 | if (TARGET_VFP) |
3630 | size += 32; | |
9f7bf991 RE |
3631 | if (TARGET_FPA) |
3632 | size += 12; | |
3633 | if (TARGET_MAVERICK) | |
3634 | size += 8; | |
3635 | } | |
3636 | if (TARGET_IWMMXT_ABI) | |
3637 | size += 8; | |
3638 | } | |
3639 | ||
3640 | return size; | |
3641 | } | |
d4453b7a | 3642 | |
390b17c2 RE |
3643 | /* Decide whether TYPE should be returned in memory (true) |
3644 | or in a register (false). FNTYPE is the type of the function making | |
3645 | the call. */ | |
23668cf7 | 3646 | static bool |
390b17c2 | 3647 | arm_return_in_memory (const_tree type, const_tree fntype) |
2b835d68 | 3648 | { |
dc0ba55a JT |
3649 | HOST_WIDE_INT size; |
3650 | ||
390b17c2 RE |
3651 | size = int_size_in_bytes (type); /* Negative if not fixed size. */ |
3652 | ||
3653 | if (TARGET_AAPCS_BASED) | |
3654 | { | |
3655 | /* Simple, non-aggregate types (ie not including vectors and | |
3656 | complex) are always returned in a register (or registers). | |
3657 | We don't care about which register here, so we can short-cut | |
3658 | some of the detail. */ | |
3659 | if (!AGGREGATE_TYPE_P (type) | |
3660 | && TREE_CODE (type) != VECTOR_TYPE | |
3661 | && TREE_CODE (type) != COMPLEX_TYPE) | |
3662 | return false; | |
3663 | ||
3664 | /* Any return value that is no larger than one word can be | |
3665 | returned in r0. */ | |
3666 | if (((unsigned HOST_WIDE_INT) size) <= UNITS_PER_WORD) | |
3667 | return false; | |
3668 | ||
3669 | /* Check any available co-processors to see if they accept the | |
3670 | type as a register candidate (VFP, for example, can return | |
3671 | some aggregates in consecutive registers). These aren't | |
3672 | available if the call is variadic. */ | |
3673 | if (aapcs_select_return_coproc (type, fntype) >= 0) | |
3674 | return false; | |
3675 | ||
3676 | /* Vector values should be returned using ARM registers, not | |
3677 | memory (unless they're over 16 bytes, which will break since | |
3678 | we only have four call-clobbered registers to play with). */ | |
3679 | if (TREE_CODE (type) == VECTOR_TYPE) | |
3680 | return (size < 0 || size > (4 * UNITS_PER_WORD)); | |
3681 | ||
3682 | /* The rest go in memory. */ | |
3683 | return true; | |
3684 | } | |
88f77cba | 3685 | |
88f77cba JB |
3686 | if (TREE_CODE (type) == VECTOR_TYPE) |
3687 | return (size < 0 || size > (4 * UNITS_PER_WORD)); | |
3688 | ||
3dd7ab65 | 3689 | if (!AGGREGATE_TYPE_P (type) && |
390b17c2 RE |
3690 | (TREE_CODE (type) != VECTOR_TYPE)) |
3691 | /* All simple types are returned in registers. */ | |
3692 | return false; | |
dc0ba55a | 3693 | |
5848830f | 3694 | if (arm_abi != ARM_ABI_APCS) |
dc0ba55a | 3695 | { |
5848830f | 3696 | /* ATPCS and later return aggregate types in memory only if they are |
dc0ba55a JT |
3697 | larger than a word (or are variable size). */ |
3698 | return (size < 0 || size > UNITS_PER_WORD); | |
3699 | } | |
f676971a | 3700 | |
6bc82793 | 3701 | /* For the arm-wince targets we choose to be compatible with Microsoft's |
d5b7b3ae RE |
3702 | ARM and Thumb compilers, which always return aggregates in memory. */ |
3703 | #ifndef ARM_WINCE | |
e529bd42 NC |
3704 | /* All structures/unions bigger than one word are returned in memory. |
3705 | Also catch the case where int_size_in_bytes returns -1. In this case | |
6bc82793 | 3706 | the aggregate is either huge or of variable size, and in either case |
e529bd42 | 3707 | we will want to return it via memory and not in a register. */ |
dc0ba55a | 3708 | if (size < 0 || size > UNITS_PER_WORD) |
390b17c2 | 3709 | return true; |
f676971a | 3710 | |
d7d01975 | 3711 | if (TREE_CODE (type) == RECORD_TYPE) |
2b835d68 RE |
3712 | { |
3713 | tree field; | |
3714 | ||
3a2ea258 RE |
3715 | /* For a struct the APCS says that we only return in a register |
3716 | if the type is 'integer like' and every addressable element | |
3717 | has an offset of zero. For practical purposes this means | |
3718 | that the structure can have at most one non bit-field element | |
3719 | and that this element must be the first one in the structure. */ | |
f676971a | 3720 | |
f5a1b0d2 NC |
3721 | /* Find the first field, ignoring non FIELD_DECL things which will |
3722 | have been created by C++. */ | |
3723 | for (field = TYPE_FIELDS (type); | |
3724 | field && TREE_CODE (field) != FIELD_DECL; | |
910ad8de | 3725 | field = DECL_CHAIN (field)) |
f5a1b0d2 | 3726 | continue; |
f676971a | 3727 | |
f5a1b0d2 | 3728 | if (field == NULL) |
390b17c2 | 3729 | return false; /* An empty structure. Allowed by an extension to ANSI C. */ |
f5a1b0d2 | 3730 | |
d5b7b3ae RE |
3731 | /* Check that the first field is valid for returning in a register. */ |
3732 | ||
3733 | /* ... Floats are not allowed */ | |
9e291dbe | 3734 | if (FLOAT_TYPE_P (TREE_TYPE (field))) |
390b17c2 | 3735 | return true; |
3a2ea258 | 3736 | |
d5b7b3ae RE |
3737 | /* ... Aggregates that are not themselves valid for returning in |
3738 | a register are not allowed. */ | |
81464b2c | 3739 | if (arm_return_in_memory (TREE_TYPE (field), NULL_TREE)) |
390b17c2 | 3740 | return true; |
6f7ebcbb | 3741 | |
3a2ea258 RE |
3742 | /* Now check the remaining fields, if any. Only bitfields are allowed, |
3743 | since they are not addressable. */ | |
910ad8de | 3744 | for (field = DECL_CHAIN (field); |
f5a1b0d2 | 3745 | field; |
910ad8de | 3746 | field = DECL_CHAIN (field)) |
f5a1b0d2 NC |
3747 | { |
3748 | if (TREE_CODE (field) != FIELD_DECL) | |
3749 | continue; | |
f676971a | 3750 | |
5895f793 | 3751 | if (!DECL_BIT_FIELD_TYPE (field)) |
390b17c2 | 3752 | return true; |
f5a1b0d2 | 3753 | } |
2b835d68 | 3754 | |
390b17c2 | 3755 | return false; |
2b835d68 | 3756 | } |
f676971a | 3757 | |
d7d01975 | 3758 | if (TREE_CODE (type) == UNION_TYPE) |
2b835d68 RE |
3759 | { |
3760 | tree field; | |
3761 | ||
3762 | /* Unions can be returned in registers if every element is | |
3763 | integral, or can be returned in an integer register. */ | |
f5a1b0d2 NC |
3764 | for (field = TYPE_FIELDS (type); |
3765 | field; | |
910ad8de | 3766 | field = DECL_CHAIN (field)) |
2b835d68 | 3767 | { |
f5a1b0d2 NC |
3768 | if (TREE_CODE (field) != FIELD_DECL) |
3769 | continue; | |
3770 | ||
6cc8c0b3 | 3771 | if (FLOAT_TYPE_P (TREE_TYPE (field))) |
390b17c2 | 3772 | return true; |
f676971a | 3773 | |
81464b2c | 3774 | if (arm_return_in_memory (TREE_TYPE (field), NULL_TREE)) |
390b17c2 | 3775 | return true; |
2b835d68 | 3776 | } |
f676971a | 3777 | |
390b17c2 | 3778 | return false; |
2b835d68 | 3779 | } |
f676971a EC |
3780 | #endif /* not ARM_WINCE */ |
3781 | ||
d5b7b3ae | 3782 | /* Return all other types in memory. */ |
390b17c2 | 3783 | return true; |
2b835d68 RE |
3784 | } |
3785 | ||
d6b4baa4 | 3786 | /* Indicate whether or not words of a double are in big-endian order. */ |
3717da94 JT |
3787 | |
3788 | int | |
e32bac5b | 3789 | arm_float_words_big_endian (void) |
3717da94 | 3790 | { |
9b66ebb1 | 3791 | if (TARGET_MAVERICK) |
9b6b54e2 | 3792 | return 0; |
3717da94 JT |
3793 | |
3794 | /* For FPA, float words are always big-endian. For VFP, floats words | |
3795 | follow the memory system mode. */ | |
3796 | ||
9b66ebb1 | 3797 | if (TARGET_FPA) |
3717da94 | 3798 | { |
3717da94 JT |
3799 | return 1; |
3800 | } | |
3801 | ||
3802 | if (TARGET_VFP) | |
3803 | return (TARGET_BIG_END ? 1 : 0); | |
3804 | ||
3805 | return 1; | |
3806 | } | |
3807 | ||
390b17c2 RE |
3808 | const struct pcs_attribute_arg |
3809 | { | |
3810 | const char *arg; | |
3811 | enum arm_pcs value; | |
3812 | } pcs_attribute_args[] = | |
3813 | { | |
3814 | {"aapcs", ARM_PCS_AAPCS}, | |
3815 | {"aapcs-vfp", ARM_PCS_AAPCS_VFP}, | |
0f1a24df RE |
3816 | #if 0 |
3817 | /* We could recognize these, but changes would be needed elsewhere | |
3818 | * to implement them. */ | |
390b17c2 RE |
3819 | {"aapcs-iwmmxt", ARM_PCS_AAPCS_IWMMXT}, |
3820 | {"atpcs", ARM_PCS_ATPCS}, | |
3821 | {"apcs", ARM_PCS_APCS}, | |
0f1a24df | 3822 | #endif |
390b17c2 RE |
3823 | {NULL, ARM_PCS_UNKNOWN} |
3824 | }; | |
3825 | ||
3826 | static enum arm_pcs | |
3827 | arm_pcs_from_attribute (tree attr) | |
3828 | { | |
3829 | const struct pcs_attribute_arg *ptr; | |
3830 | const char *arg; | |
3831 | ||
3832 | /* Get the value of the argument. */ | |
3833 | if (TREE_VALUE (attr) == NULL_TREE | |
3834 | || TREE_CODE (TREE_VALUE (attr)) != STRING_CST) | |
3835 | return ARM_PCS_UNKNOWN; | |
3836 | ||
3837 | arg = TREE_STRING_POINTER (TREE_VALUE (attr)); | |
3838 | ||
3839 | /* Check it against the list of known arguments. */ | |
3840 | for (ptr = pcs_attribute_args; ptr->arg != NULL; ptr++) | |
3841 | if (streq (arg, ptr->arg)) | |
3842 | return ptr->value; | |
3843 | ||
3844 | /* An unrecognized interrupt type. */ | |
3845 | return ARM_PCS_UNKNOWN; | |
3846 | } | |
3847 | ||
3848 | /* Get the PCS variant to use for this call. TYPE is the function's type | |
3849 | specification, DECL is the specific declartion. DECL may be null if | |
3850 | the call could be indirect or if this is a library call. */ | |
3851 | static enum arm_pcs | |
3852 | arm_get_pcs_model (const_tree type, const_tree decl) | |
3853 | { | |
3854 | bool user_convention = false; | |
3855 | enum arm_pcs user_pcs = arm_pcs_default; | |
3856 | tree attr; | |
3857 | ||
3858 | gcc_assert (type); | |
3859 | ||
3860 | attr = lookup_attribute ("pcs", TYPE_ATTRIBUTES (type)); | |
3861 | if (attr) | |
3862 | { | |
3863 | user_pcs = arm_pcs_from_attribute (TREE_VALUE (attr)); | |
3864 | user_convention = true; | |
3865 | } | |
3866 | ||
3867 | if (TARGET_AAPCS_BASED) | |
3868 | { | |
3869 | /* Detect varargs functions. These always use the base rules | |
3870 | (no argument is ever a candidate for a co-processor | |
3871 | register). */ | |
f38958e8 | 3872 | bool base_rules = stdarg_p (type); |
390b17c2 RE |
3873 | |
3874 | if (user_convention) | |
3875 | { | |
3876 | if (user_pcs > ARM_PCS_AAPCS_LOCAL) | |
d8a07487 | 3877 | sorry ("non-AAPCS derived PCS variant"); |
390b17c2 | 3878 | else if (base_rules && user_pcs != ARM_PCS_AAPCS) |
d8a07487 | 3879 | error ("variadic functions must use the base AAPCS variant"); |
390b17c2 RE |
3880 | } |
3881 | ||
3882 | if (base_rules) | |
3883 | return ARM_PCS_AAPCS; | |
3884 | else if (user_convention) | |
3885 | return user_pcs; | |
3886 | else if (decl && flag_unit_at_a_time) | |
3887 | { | |
3888 | /* Local functions never leak outside this compilation unit, | |
3889 | so we are free to use whatever conventions are | |
3890 | appropriate. */ | |
3891 | /* FIXME: remove CONST_CAST_TREE when cgraph is constified. */ | |
3892 | struct cgraph_local_info *i = cgraph_local_info (CONST_CAST_TREE(decl)); | |
3893 | if (i && i->local) | |
3894 | return ARM_PCS_AAPCS_LOCAL; | |
3895 | } | |
3896 | } | |
3897 | else if (user_convention && user_pcs != arm_pcs_default) | |
3898 | sorry ("PCS variant"); | |
3899 | ||
3900 | /* For everything else we use the target's default. */ | |
3901 | return arm_pcs_default; | |
3902 | } | |
3903 | ||
3904 | ||
3905 | static void | |
3906 | aapcs_vfp_cum_init (CUMULATIVE_ARGS *pcum ATTRIBUTE_UNUSED, | |
3907 | const_tree fntype ATTRIBUTE_UNUSED, | |
3908 | rtx libcall ATTRIBUTE_UNUSED, | |
3909 | const_tree fndecl ATTRIBUTE_UNUSED) | |
3910 | { | |
3911 | /* Record the unallocated VFP registers. */ | |
3912 | pcum->aapcs_vfp_regs_free = (1 << NUM_VFP_ARG_REGS) - 1; | |
3913 | pcum->aapcs_vfp_reg_alloc = 0; | |
3914 | } | |
3915 | ||
3916 | /* Walk down the type tree of TYPE counting consecutive base elements. | |
3917 | If *MODEP is VOIDmode, then set it to the first valid floating point | |
3918 | type. If a non-floating point type is found, or if a floating point | |
3919 | type that doesn't match a non-VOIDmode *MODEP is found, then return -1, | |
3920 | otherwise return the count in the sub-tree. */ | |
3921 | static int | |
3922 | aapcs_vfp_sub_candidate (const_tree type, enum machine_mode *modep) | |
3923 | { | |
3924 | enum machine_mode mode; | |
3925 | HOST_WIDE_INT size; | |
3926 | ||
3927 | switch (TREE_CODE (type)) | |
3928 | { | |
3929 | case REAL_TYPE: | |
3930 | mode = TYPE_MODE (type); | |
3931 | if (mode != DFmode && mode != SFmode) | |
3932 | return -1; | |
3933 | ||
3934 | if (*modep == VOIDmode) | |
3935 | *modep = mode; | |
3936 | ||
3937 | if (*modep == mode) | |
3938 | return 1; | |
3939 | ||
3940 | break; | |
3941 | ||
3942 | case COMPLEX_TYPE: | |
3943 | mode = TYPE_MODE (TREE_TYPE (type)); | |
3944 | if (mode != DFmode && mode != SFmode) | |
3945 | return -1; | |
3946 | ||
3947 | if (*modep == VOIDmode) | |
3948 | *modep = mode; | |
3949 | ||
3950 | if (*modep == mode) | |
3951 | return 2; | |
3952 | ||
3953 | break; | |
3954 | ||
3955 | case VECTOR_TYPE: | |
3956 | /* Use V2SImode and V4SImode as representatives of all 64-bit | |
3957 | and 128-bit vector types, whether or not those modes are | |
3958 | supported with the present options. */ | |
3959 | size = int_size_in_bytes (type); | |
3960 | switch (size) | |
3961 | { | |
3962 | case 8: | |
3963 | mode = V2SImode; | |
3964 | break; | |
3965 | case 16: | |
3966 | mode = V4SImode; | |
3967 | break; | |
3968 | default: | |
3969 | return -1; | |
3970 | } | |
3971 | ||
3972 | if (*modep == VOIDmode) | |
3973 | *modep = mode; | |
3974 | ||
3975 | /* Vector modes are considered to be opaque: two vectors are | |
3976 | equivalent for the purposes of being homogeneous aggregates | |
3977 | if they are the same size. */ | |
3978 | if (*modep == mode) | |
3979 | return 1; | |
3980 | ||
3981 | break; | |
3982 | ||
3983 | case ARRAY_TYPE: | |
3984 | { | |
3985 | int count; | |
3986 | tree index = TYPE_DOMAIN (type); | |
3987 | ||
3988 | /* Can't handle incomplete types. */ | |
3989 | if (!COMPLETE_TYPE_P(type)) | |
3990 | return -1; | |
3991 | ||
3992 | count = aapcs_vfp_sub_candidate (TREE_TYPE (type), modep); | |
3993 | if (count == -1 | |
3994 | || !index | |
3995 | || !TYPE_MAX_VALUE (index) | |
3996 | || !host_integerp (TYPE_MAX_VALUE (index), 1) | |
3997 | || !TYPE_MIN_VALUE (index) | |
3998 | || !host_integerp (TYPE_MIN_VALUE (index), 1) | |
3999 | || count < 0) | |
4000 | return -1; | |
4001 | ||
4002 | count *= (1 + tree_low_cst (TYPE_MAX_VALUE (index), 1) | |
4003 | - tree_low_cst (TYPE_MIN_VALUE (index), 1)); | |
4004 | ||
4005 | /* There must be no padding. */ | |
4006 | if (!host_integerp (TYPE_SIZE (type), 1) | |
4007 | || (tree_low_cst (TYPE_SIZE (type), 1) | |
4008 | != count * GET_MODE_BITSIZE (*modep))) | |
4009 | return -1; | |
4010 | ||
4011 | return count; | |
4012 | } | |
4013 | ||
4014 | case RECORD_TYPE: | |
4015 | { | |
4016 | int count = 0; | |
4017 | int sub_count; | |
4018 | tree field; | |
4019 | ||
4020 | /* Can't handle incomplete types. */ | |
4021 | if (!COMPLETE_TYPE_P(type)) | |
4022 | return -1; | |
4023 | ||
910ad8de | 4024 | for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field)) |
390b17c2 RE |
4025 | { |
4026 | if (TREE_CODE (field) != FIELD_DECL) | |
4027 | continue; | |
4028 | ||
4029 | sub_count = aapcs_vfp_sub_candidate (TREE_TYPE (field), modep); | |
4030 | if (sub_count < 0) | |
4031 | return -1; | |
4032 | count += sub_count; | |
4033 | } | |
4034 | ||
4035 | /* There must be no padding. */ | |
4036 | if (!host_integerp (TYPE_SIZE (type), 1) | |
4037 | || (tree_low_cst (TYPE_SIZE (type), 1) | |
4038 | != count * GET_MODE_BITSIZE (*modep))) | |
4039 | return -1; | |
4040 | ||
4041 | return count; | |
4042 | } | |
4043 | ||
4044 | case UNION_TYPE: | |
4045 | case QUAL_UNION_TYPE: | |
4046 | { | |
4047 | /* These aren't very interesting except in a degenerate case. */ | |
4048 | int count = 0; | |
4049 | int sub_count; | |
4050 | tree field; | |
4051 | ||
4052 | /* Can't handle incomplete types. */ | |
4053 | if (!COMPLETE_TYPE_P(type)) | |
4054 | return -1; | |
4055 | ||
910ad8de | 4056 | for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field)) |
390b17c2 RE |
4057 | { |
4058 | if (TREE_CODE (field) != FIELD_DECL) | |
4059 | continue; | |
4060 | ||
4061 | sub_count = aapcs_vfp_sub_candidate (TREE_TYPE (field), modep); | |
4062 | if (sub_count < 0) | |
4063 | return -1; | |
4064 | count = count > sub_count ? count : sub_count; | |
4065 | } | |
4066 | ||
4067 | /* There must be no padding. */ | |
4068 | if (!host_integerp (TYPE_SIZE (type), 1) | |
4069 | || (tree_low_cst (TYPE_SIZE (type), 1) | |
4070 | != count * GET_MODE_BITSIZE (*modep))) | |
4071 | return -1; | |
4072 | ||
4073 | return count; | |
4074 | } | |
4075 | ||
4076 | default: | |
4077 | break; | |
4078 | } | |
4079 | ||
4080 | return -1; | |
4081 | } | |
4082 | ||
e0dc3601 | 4083 | /* Return true if PCS_VARIANT should use VFP registers. */ |
390b17c2 | 4084 | static bool |
e0dc3601 | 4085 | use_vfp_abi (enum arm_pcs pcs_variant, bool is_double) |
390b17c2 | 4086 | { |
e0dc3601 | 4087 | if (pcs_variant == ARM_PCS_AAPCS_VFP) |
50416c61 PB |
4088 | { |
4089 | static bool seen_thumb1_vfp = false; | |
4090 | ||
4091 | if (TARGET_THUMB1 && !seen_thumb1_vfp) | |
4092 | { | |
4093 | sorry ("Thumb-1 hard-float VFP ABI"); | |
4094 | /* sorry() is not immediately fatal, so only display this once. */ | |
4095 | seen_thumb1_vfp = true; | |
4096 | } | |
4097 | ||
4098 | return true; | |
4099 | } | |
e0dc3601 PB |
4100 | |
4101 | if (pcs_variant != ARM_PCS_AAPCS_LOCAL) | |
4102 | return false; | |
4103 | ||
4104 | return (TARGET_32BIT && TARGET_VFP && TARGET_HARD_FLOAT && | |
4105 | (TARGET_VFP_DOUBLE || !is_double)); | |
4106 | } | |
4107 | ||
4108 | static bool | |
4109 | aapcs_vfp_is_call_or_return_candidate (enum arm_pcs pcs_variant, | |
4110 | enum machine_mode mode, const_tree type, | |
70dd156a | 4111 | enum machine_mode *base_mode, int *count) |
e0dc3601 PB |
4112 | { |
4113 | enum machine_mode new_mode = VOIDmode; | |
4114 | ||
390b17c2 RE |
4115 | if (GET_MODE_CLASS (mode) == MODE_FLOAT |
4116 | || GET_MODE_CLASS (mode) == MODE_VECTOR_INT | |
4117 | || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT) | |
4118 | { | |
4119 | *count = 1; | |
e0dc3601 | 4120 | new_mode = mode; |
390b17c2 RE |
4121 | } |
4122 | else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT) | |
4123 | { | |
4124 | *count = 2; | |
e0dc3601 | 4125 | new_mode = (mode == DCmode ? DFmode : SFmode); |
390b17c2 RE |
4126 | } |
4127 | else if (type && (mode == BLKmode || TREE_CODE (type) == VECTOR_TYPE)) | |
4128 | { | |
e0dc3601 | 4129 | int ag_count = aapcs_vfp_sub_candidate (type, &new_mode); |
390b17c2 RE |
4130 | |
4131 | if (ag_count > 0 && ag_count <= 4) | |
e0dc3601 PB |
4132 | *count = ag_count; |
4133 | else | |
4134 | return false; | |
390b17c2 | 4135 | } |
e0dc3601 PB |
4136 | else |
4137 | return false; | |
4138 | ||
4139 | ||
4140 | if (!use_vfp_abi (pcs_variant, ARM_NUM_REGS (new_mode) > 1)) | |
4141 | return false; | |
4142 | ||
4143 | *base_mode = new_mode; | |
4144 | return true; | |
390b17c2 RE |
4145 | } |
4146 | ||
4147 | static bool | |
4148 | aapcs_vfp_is_return_candidate (enum arm_pcs pcs_variant, | |
4149 | enum machine_mode mode, const_tree type) | |
4150 | { | |
4151 | int count ATTRIBUTE_UNUSED; | |
46107b99 | 4152 | enum machine_mode ag_mode ATTRIBUTE_UNUSED; |
390b17c2 | 4153 | |
e0dc3601 | 4154 | if (!use_vfp_abi (pcs_variant, false)) |
390b17c2 | 4155 | return false; |
e0dc3601 PB |
4156 | return aapcs_vfp_is_call_or_return_candidate (pcs_variant, mode, type, |
4157 | &ag_mode, &count); | |
390b17c2 RE |
4158 | } |
4159 | ||
4160 | static bool | |
4161 | aapcs_vfp_is_call_candidate (CUMULATIVE_ARGS *pcum, enum machine_mode mode, | |
4162 | const_tree type) | |
4163 | { | |
e0dc3601 | 4164 | if (!use_vfp_abi (pcum->pcs_variant, false)) |
390b17c2 | 4165 | return false; |
e0dc3601 PB |
4166 | |
4167 | return aapcs_vfp_is_call_or_return_candidate (pcum->pcs_variant, mode, type, | |
390b17c2 RE |
4168 | &pcum->aapcs_vfp_rmode, |
4169 | &pcum->aapcs_vfp_rcount); | |
4170 | } | |
4171 | ||
4172 | static bool | |
4173 | aapcs_vfp_allocate (CUMULATIVE_ARGS *pcum, enum machine_mode mode, | |
4174 | const_tree type ATTRIBUTE_UNUSED) | |
4175 | { | |
4176 | int shift = GET_MODE_SIZE (pcum->aapcs_vfp_rmode) / GET_MODE_SIZE (SFmode); | |
4177 | unsigned mask = (1 << (shift * pcum->aapcs_vfp_rcount)) - 1; | |
4178 | int regno; | |
4179 | ||
4180 | for (regno = 0; regno < NUM_VFP_ARG_REGS; regno += shift) | |
4181 | if (((pcum->aapcs_vfp_regs_free >> regno) & mask) == mask) | |
4182 | { | |
4183 | pcum->aapcs_vfp_reg_alloc = mask << regno; | |
4184 | if (mode == BLKmode || (mode == TImode && !TARGET_NEON)) | |
4185 | { | |
4186 | int i; | |
4187 | int rcount = pcum->aapcs_vfp_rcount; | |
4188 | int rshift = shift; | |
4189 | enum machine_mode rmode = pcum->aapcs_vfp_rmode; | |
4190 | rtx par; | |
4191 | if (!TARGET_NEON) | |
4192 | { | |
4193 | /* Avoid using unsupported vector modes. */ | |
4194 | if (rmode == V2SImode) | |
4195 | rmode = DImode; | |
4196 | else if (rmode == V4SImode) | |
4197 | { | |
4198 | rmode = DImode; | |
4199 | rcount *= 2; | |
4200 | rshift /= 2; | |
4201 | } | |
4202 | } | |
4203 | par = gen_rtx_PARALLEL (mode, rtvec_alloc (rcount)); | |
4204 | for (i = 0; i < rcount; i++) | |
4205 | { | |
4206 | rtx tmp = gen_rtx_REG (rmode, | |
4207 | FIRST_VFP_REGNUM + regno + i * rshift); | |
4208 | tmp = gen_rtx_EXPR_LIST | |
4209 | (VOIDmode, tmp, | |
4210 | GEN_INT (i * GET_MODE_SIZE (rmode))); | |
4211 | XVECEXP (par, 0, i) = tmp; | |
4212 | } | |
4213 | ||
4214 | pcum->aapcs_reg = par; | |
4215 | } | |
4216 | else | |
4217 | pcum->aapcs_reg = gen_rtx_REG (mode, FIRST_VFP_REGNUM + regno); | |
4218 | return true; | |
4219 | } | |
4220 | return false; | |
4221 | } | |
4222 | ||
4223 | static rtx | |
4224 | aapcs_vfp_allocate_return_reg (enum arm_pcs pcs_variant ATTRIBUTE_UNUSED, | |
4225 | enum machine_mode mode, | |
4226 | const_tree type ATTRIBUTE_UNUSED) | |
4227 | { | |
e0dc3601 | 4228 | if (!use_vfp_abi (pcs_variant, false)) |
390b17c2 | 4229 | return false; |
e0dc3601 | 4230 | |
390b17c2 RE |
4231 | if (mode == BLKmode || (mode == TImode && !TARGET_NEON)) |
4232 | { | |
4233 | int count; | |
46107b99 | 4234 | enum machine_mode ag_mode; |
390b17c2 RE |
4235 | int i; |
4236 | rtx par; | |
4237 | int shift; | |
4238 | ||
e0dc3601 PB |
4239 | aapcs_vfp_is_call_or_return_candidate (pcs_variant, mode, type, |
4240 | &ag_mode, &count); | |
390b17c2 RE |
4241 | |
4242 | if (!TARGET_NEON) | |
4243 | { | |
4244 | if (ag_mode == V2SImode) | |
4245 | ag_mode = DImode; | |
4246 | else if (ag_mode == V4SImode) | |
4247 | { | |
4248 | ag_mode = DImode; | |
4249 | count *= 2; | |
4250 | } | |
4251 | } | |
4252 | shift = GET_MODE_SIZE(ag_mode) / GET_MODE_SIZE(SFmode); | |
4253 | par = gen_rtx_PARALLEL (mode, rtvec_alloc (count)); | |
4254 | for (i = 0; i < count; i++) | |
4255 | { | |
4256 | rtx tmp = gen_rtx_REG (ag_mode, FIRST_VFP_REGNUM + i * shift); | |
4257 | tmp = gen_rtx_EXPR_LIST (VOIDmode, tmp, | |
4258 | GEN_INT (i * GET_MODE_SIZE (ag_mode))); | |
4259 | XVECEXP (par, 0, i) = tmp; | |
4260 | } | |
4261 | ||
4262 | return par; | |
4263 | } | |
4264 | ||
4265 | return gen_rtx_REG (mode, FIRST_VFP_REGNUM); | |
4266 | } | |
4267 | ||
4268 | static void | |
4269 | aapcs_vfp_advance (CUMULATIVE_ARGS *pcum ATTRIBUTE_UNUSED, | |
4270 | enum machine_mode mode ATTRIBUTE_UNUSED, | |
4271 | const_tree type ATTRIBUTE_UNUSED) | |
4272 | { | |
4273 | pcum->aapcs_vfp_regs_free &= ~pcum->aapcs_vfp_reg_alloc; | |
4274 | pcum->aapcs_vfp_reg_alloc = 0; | |
4275 | return; | |
4276 | } | |
4277 | ||
4278 | #define AAPCS_CP(X) \ | |
4279 | { \ | |
4280 | aapcs_ ## X ## _cum_init, \ | |
4281 | aapcs_ ## X ## _is_call_candidate, \ | |
4282 | aapcs_ ## X ## _allocate, \ | |
4283 | aapcs_ ## X ## _is_return_candidate, \ | |
4284 | aapcs_ ## X ## _allocate_return_reg, \ | |
4285 | aapcs_ ## X ## _advance \ | |
4286 | } | |
4287 | ||
4288 | /* Table of co-processors that can be used to pass arguments in | |
4289 | registers. Idealy no arugment should be a candidate for more than | |
4290 | one co-processor table entry, but the table is processed in order | |
4291 | and stops after the first match. If that entry then fails to put | |
4292 | the argument into a co-processor register, the argument will go on | |
4293 | the stack. */ | |
4294 | static struct | |
4295 | { | |
4296 | /* Initialize co-processor related state in CUMULATIVE_ARGS structure. */ | |
4297 | void (*cum_init) (CUMULATIVE_ARGS *, const_tree, rtx, const_tree); | |
4298 | ||
4299 | /* Return true if an argument of mode MODE (or type TYPE if MODE is | |
4300 | BLKmode) is a candidate for this co-processor's registers; this | |
4301 | function should ignore any position-dependent state in | |
4302 | CUMULATIVE_ARGS and only use call-type dependent information. */ | |
4303 | bool (*is_call_candidate) (CUMULATIVE_ARGS *, enum machine_mode, const_tree); | |
4304 | ||
4305 | /* Return true if the argument does get a co-processor register; it | |
4306 | should set aapcs_reg to an RTX of the register allocated as is | |
4307 | required for a return from FUNCTION_ARG. */ | |
4308 | bool (*allocate) (CUMULATIVE_ARGS *, enum machine_mode, const_tree); | |
4309 | ||
4310 | /* Return true if a result of mode MODE (or type TYPE if MODE is | |
4311 | BLKmode) is can be returned in this co-processor's registers. */ | |
4312 | bool (*is_return_candidate) (enum arm_pcs, enum machine_mode, const_tree); | |
4313 | ||
4314 | /* Allocate and return an RTX element to hold the return type of a | |
4315 | call, this routine must not fail and will only be called if | |
4316 | is_return_candidate returned true with the same parameters. */ | |
4317 | rtx (*allocate_return_reg) (enum arm_pcs, enum machine_mode, const_tree); | |
4318 | ||
4319 | /* Finish processing this argument and prepare to start processing | |
4320 | the next one. */ | |
4321 | void (*advance) (CUMULATIVE_ARGS *, enum machine_mode, const_tree); | |
4322 | } aapcs_cp_arg_layout[ARM_NUM_COPROC_SLOTS] = | |
4323 | { | |
4324 | AAPCS_CP(vfp) | |
4325 | }; | |
4326 | ||
4327 | #undef AAPCS_CP | |
4328 | ||
4329 | static int | |
4330 | aapcs_select_call_coproc (CUMULATIVE_ARGS *pcum, enum machine_mode mode, | |
9c6a2bee | 4331 | const_tree type) |
390b17c2 RE |
4332 | { |
4333 | int i; | |
4334 | ||
4335 | for (i = 0; i < ARM_NUM_COPROC_SLOTS; i++) | |
4336 | if (aapcs_cp_arg_layout[i].is_call_candidate (pcum, mode, type)) | |
4337 | return i; | |
4338 | ||
4339 | return -1; | |
4340 | } | |
4341 | ||
4342 | static int | |
4343 | aapcs_select_return_coproc (const_tree type, const_tree fntype) | |
4344 | { | |
4345 | /* We aren't passed a decl, so we can't check that a call is local. | |
4346 | However, it isn't clear that that would be a win anyway, since it | |
4347 | might limit some tail-calling opportunities. */ | |
4348 | enum arm_pcs pcs_variant; | |
4349 | ||
4350 | if (fntype) | |
4351 | { | |
4352 | const_tree fndecl = NULL_TREE; | |
4353 | ||
4354 | if (TREE_CODE (fntype) == FUNCTION_DECL) | |
4355 | { | |
4356 | fndecl = fntype; | |
4357 | fntype = TREE_TYPE (fntype); | |
4358 | } | |
4359 | ||
4360 | pcs_variant = arm_get_pcs_model (fntype, fndecl); | |
4361 | } | |
4362 | else | |
4363 | pcs_variant = arm_pcs_default; | |
4364 | ||
4365 | if (pcs_variant != ARM_PCS_AAPCS) | |
4366 | { | |
4367 | int i; | |
4368 | ||
4369 | for (i = 0; i < ARM_NUM_COPROC_SLOTS; i++) | |
4370 | if (aapcs_cp_arg_layout[i].is_return_candidate (pcs_variant, | |
4371 | TYPE_MODE (type), | |
4372 | type)) | |
4373 | return i; | |
4374 | } | |
4375 | return -1; | |
4376 | } | |
4377 | ||
4378 | static rtx | |
4379 | aapcs_allocate_return_reg (enum machine_mode mode, const_tree type, | |
4380 | const_tree fntype) | |
4381 | { | |
4382 | /* We aren't passed a decl, so we can't check that a call is local. | |
4383 | However, it isn't clear that that would be a win anyway, since it | |
4384 | might limit some tail-calling opportunities. */ | |
4385 | enum arm_pcs pcs_variant; | |
4386 | int unsignedp ATTRIBUTE_UNUSED; | |
4387 | ||
4388 | if (fntype) | |
4389 | { | |
4390 | const_tree fndecl = NULL_TREE; | |
4391 | ||
4392 | if (TREE_CODE (fntype) == FUNCTION_DECL) | |
4393 | { | |
4394 | fndecl = fntype; | |
4395 | fntype = TREE_TYPE (fntype); | |
4396 | } | |
4397 | ||
4398 | pcs_variant = arm_get_pcs_model (fntype, fndecl); | |
4399 | } | |
4400 | else | |
4401 | pcs_variant = arm_pcs_default; | |
4402 | ||
4403 | /* Promote integer types. */ | |
4404 | if (type && INTEGRAL_TYPE_P (type)) | |
4405 | mode = arm_promote_function_mode (type, mode, &unsignedp, fntype, 1); | |
4406 | ||
4407 | if (pcs_variant != ARM_PCS_AAPCS) | |
4408 | { | |
4409 | int i; | |
4410 | ||
4411 | for (i = 0; i < ARM_NUM_COPROC_SLOTS; i++) | |
4412 | if (aapcs_cp_arg_layout[i].is_return_candidate (pcs_variant, mode, | |
4413 | type)) | |
4414 | return aapcs_cp_arg_layout[i].allocate_return_reg (pcs_variant, | |
4415 | mode, type); | |
4416 | } | |
4417 | ||
4418 | /* Promotes small structs returned in a register to full-word size | |
4419 | for big-endian AAPCS. */ | |
4420 | if (type && arm_return_in_msb (type)) | |
4421 | { | |
4422 | HOST_WIDE_INT size = int_size_in_bytes (type); | |
4423 | if (size % UNITS_PER_WORD != 0) | |
4424 | { | |
4425 | size += UNITS_PER_WORD - size % UNITS_PER_WORD; | |
4426 | mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0); | |
4427 | } | |
4428 | } | |
4429 | ||
4430 | return gen_rtx_REG (mode, R0_REGNUM); | |
4431 | } | |
4432 | ||
4433 | rtx | |
4434 | aapcs_libcall_value (enum machine_mode mode) | |
4435 | { | |
4436 | return aapcs_allocate_return_reg (mode, NULL_TREE, NULL_TREE); | |
4437 | } | |
4438 | ||
4439 | /* Lay out a function argument using the AAPCS rules. The rule | |
4440 | numbers referred to here are those in the AAPCS. */ | |
4441 | static void | |
4442 | aapcs_layout_arg (CUMULATIVE_ARGS *pcum, enum machine_mode mode, | |
9c6a2bee | 4443 | const_tree type, bool named) |
390b17c2 RE |
4444 | { |
4445 | int nregs, nregs2; | |
4446 | int ncrn; | |
4447 | ||
4448 | /* We only need to do this once per argument. */ | |
4449 | if (pcum->aapcs_arg_processed) | |
4450 | return; | |
4451 | ||
4452 | pcum->aapcs_arg_processed = true; | |
4453 | ||
4454 | /* Special case: if named is false then we are handling an incoming | |
4455 | anonymous argument which is on the stack. */ | |
4456 | if (!named) | |
4457 | return; | |
4458 | ||
4459 | /* Is this a potential co-processor register candidate? */ | |
4460 | if (pcum->pcs_variant != ARM_PCS_AAPCS) | |
4461 | { | |
4462 | int slot = aapcs_select_call_coproc (pcum, mode, type); | |
4463 | pcum->aapcs_cprc_slot = slot; | |
4464 | ||
4465 | /* We don't have to apply any of the rules from part B of the | |
4466 | preparation phase, these are handled elsewhere in the | |
4467 | compiler. */ | |
4468 | ||
4469 | if (slot >= 0) | |
4470 | { | |
4471 | /* A Co-processor register candidate goes either in its own | |
4472 | class of registers or on the stack. */ | |
4473 | if (!pcum->aapcs_cprc_failed[slot]) | |
4474 | { | |
4475 | /* C1.cp - Try to allocate the argument to co-processor | |
4476 | registers. */ | |
4477 | if (aapcs_cp_arg_layout[slot].allocate (pcum, mode, type)) | |
4478 | return; | |
4479 | ||
4480 | /* C2.cp - Put the argument on the stack and note that we | |
4481 | can't assign any more candidates in this slot. We also | |
4482 | need to note that we have allocated stack space, so that | |
4483 | we won't later try to split a non-cprc candidate between | |
4484 | core registers and the stack. */ | |
4485 | pcum->aapcs_cprc_failed[slot] = true; | |
4486 | pcum->can_split = false; | |
4487 | } | |
4488 | ||
4489 | /* We didn't get a register, so this argument goes on the | |
4490 | stack. */ | |
4491 | gcc_assert (pcum->can_split == false); | |
4492 | return; | |
4493 | } | |
4494 | } | |
4495 | ||
4496 | /* C3 - For double-word aligned arguments, round the NCRN up to the | |
4497 | next even number. */ | |
4498 | ncrn = pcum->aapcs_ncrn; | |
4499 | if ((ncrn & 1) && arm_needs_doubleword_align (mode, type)) | |
4500 | ncrn++; | |
4501 | ||
4502 | nregs = ARM_NUM_REGS2(mode, type); | |
4503 | ||
4504 | /* Sigh, this test should really assert that nregs > 0, but a GCC | |
4505 | extension allows empty structs and then gives them empty size; it | |
4506 | then allows such a structure to be passed by value. For some of | |
4507 | the code below we have to pretend that such an argument has | |
4508 | non-zero size so that we 'locate' it correctly either in | |
4509 | registers or on the stack. */ | |
4510 | gcc_assert (nregs >= 0); | |
4511 | ||
4512 | nregs2 = nregs ? nregs : 1; | |
4513 | ||
4514 | /* C4 - Argument fits entirely in core registers. */ | |
4515 | if (ncrn + nregs2 <= NUM_ARG_REGS) | |
4516 | { | |
4517 | pcum->aapcs_reg = gen_rtx_REG (mode, ncrn); | |
4518 | pcum->aapcs_next_ncrn = ncrn + nregs; | |
4519 | return; | |
4520 | } | |
4521 | ||
4522 | /* C5 - Some core registers left and there are no arguments already | |
4523 | on the stack: split this argument between the remaining core | |
4524 | registers and the stack. */ | |
4525 | if (ncrn < NUM_ARG_REGS && pcum->can_split) | |
4526 | { | |
4527 | pcum->aapcs_reg = gen_rtx_REG (mode, ncrn); | |
4528 | pcum->aapcs_next_ncrn = NUM_ARG_REGS; | |
4529 | pcum->aapcs_partial = (NUM_ARG_REGS - ncrn) * UNITS_PER_WORD; | |
4530 | return; | |
4531 | } | |
4532 | ||
4533 | /* C6 - NCRN is set to 4. */ | |
4534 | pcum->aapcs_next_ncrn = NUM_ARG_REGS; | |
4535 | ||
4536 | /* C7,C8 - arugment goes on the stack. We have nothing to do here. */ | |
4537 | return; | |
4538 | } | |
4539 | ||
82e9d970 PB |
4540 | /* Initialize a variable CUM of type CUMULATIVE_ARGS |
4541 | for a call to a function whose data type is FNTYPE. | |
4542 | For a library call, FNTYPE is NULL. */ | |
4543 | void | |
f676971a | 4544 | arm_init_cumulative_args (CUMULATIVE_ARGS *pcum, tree fntype, |
390b17c2 | 4545 | rtx libname, |
e32bac5b | 4546 | tree fndecl ATTRIBUTE_UNUSED) |
82e9d970 | 4547 | { |
390b17c2 RE |
4548 | /* Long call handling. */ |
4549 | if (fntype) | |
4550 | pcum->pcs_variant = arm_get_pcs_model (fntype, fndecl); | |
4551 | else | |
4552 | pcum->pcs_variant = arm_pcs_default; | |
4553 | ||
4554 | if (pcum->pcs_variant <= ARM_PCS_AAPCS_LOCAL) | |
4555 | { | |
4556 | if (arm_libcall_uses_aapcs_base (libname)) | |
4557 | pcum->pcs_variant = ARM_PCS_AAPCS; | |
4558 | ||
4559 | pcum->aapcs_ncrn = pcum->aapcs_next_ncrn = 0; | |
4560 | pcum->aapcs_reg = NULL_RTX; | |
4561 | pcum->aapcs_partial = 0; | |
4562 | pcum->aapcs_arg_processed = false; | |
4563 | pcum->aapcs_cprc_slot = -1; | |
4564 | pcum->can_split = true; | |
4565 | ||
4566 | if (pcum->pcs_variant != ARM_PCS_AAPCS) | |
4567 | { | |
4568 | int i; | |
4569 | ||
4570 | for (i = 0; i < ARM_NUM_COPROC_SLOTS; i++) | |
4571 | { | |
4572 | pcum->aapcs_cprc_failed[i] = false; | |
4573 | aapcs_cp_arg_layout[i].cum_init (pcum, fntype, libname, fndecl); | |
4574 | } | |
4575 | } | |
4576 | return; | |
4577 | } | |
4578 | ||
4579 | /* Legacy ABIs */ | |
4580 | ||
82e9d970 | 4581 | /* On the ARM, the offset starts at 0. */ |
29e339b9 | 4582 | pcum->nregs = 0; |
5a9335ef | 4583 | pcum->iwmmxt_nregs = 0; |
5848830f | 4584 | pcum->can_split = true; |
f676971a | 4585 | |
5a9335ef NC |
4586 | /* Varargs vectors are treated the same as long long. |
4587 | named_count avoids having to change the way arm handles 'named' */ | |
4588 | pcum->named_count = 0; | |
4589 | pcum->nargs = 0; | |
4590 | ||
4591 | if (TARGET_REALLY_IWMMXT && fntype) | |
4592 | { | |
4593 | tree fn_arg; | |
4594 | ||
4595 | for (fn_arg = TYPE_ARG_TYPES (fntype); | |
4596 | fn_arg; | |
4597 | fn_arg = TREE_CHAIN (fn_arg)) | |
4598 | pcum->named_count += 1; | |
4599 | ||
4600 | if (! pcum->named_count) | |
4601 | pcum->named_count = INT_MAX; | |
4602 | } | |
82e9d970 PB |
4603 | } |
4604 | ||
5848830f PB |
4605 | |
4606 | /* Return true if mode/type need doubleword alignment. */ | |
c2ed6cf8 | 4607 | static bool |
9c6a2bee | 4608 | arm_needs_doubleword_align (enum machine_mode mode, const_tree type) |
5848830f | 4609 | { |
65a939f7 PB |
4610 | return (GET_MODE_ALIGNMENT (mode) > PARM_BOUNDARY |
4611 | || (type && TYPE_ALIGN (type) > PARM_BOUNDARY)); | |
5848830f PB |
4612 | } |
4613 | ||
4614 | ||
82e9d970 PB |
4615 | /* Determine where to put an argument to a function. |
4616 | Value is zero to push the argument on the stack, | |
4617 | or a hard register in which to store the argument. | |
4618 | ||
4619 | MODE is the argument's machine mode. | |
4620 | TYPE is the data type of the argument (as a tree). | |
4621 | This is null for libcalls where that information may | |
4622 | not be available. | |
4623 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
4624 | the preceding args and about the function being called. | |
4625 | NAMED is nonzero if this argument is a named parameter | |
9c6a2bee | 4626 | (otherwise it is an extra parameter matching an ellipsis). |
1d6e90ac | 4627 | |
9c6a2bee NF |
4628 | On the ARM, normally the first 16 bytes are passed in registers r0-r3; all |
4629 | other arguments are passed on the stack. If (NAMED == 0) (which happens | |
4630 | only in assign_parms, since TARGET_SETUP_INCOMING_VARARGS is | |
4631 | defined), say it is passed in the stack (function_prologue will | |
4632 | indeed make it pass in the stack if necessary). */ | |
4633 | ||
4634 | static rtx | |
e32bac5b | 4635 | arm_function_arg (CUMULATIVE_ARGS *pcum, enum machine_mode mode, |
9c6a2bee | 4636 | const_tree type, bool named) |
82e9d970 | 4637 | { |
5848830f PB |
4638 | int nregs; |
4639 | ||
390b17c2 RE |
4640 | /* Handle the special case quickly. Pick an arbitrary value for op2 of |
4641 | a call insn (op3 of a call_value insn). */ | |
4642 | if (mode == VOIDmode) | |
4643 | return const0_rtx; | |
4644 | ||
4645 | if (pcum->pcs_variant <= ARM_PCS_AAPCS_LOCAL) | |
4646 | { | |
4647 | aapcs_layout_arg (pcum, mode, type, named); | |
4648 | return pcum->aapcs_reg; | |
4649 | } | |
4650 | ||
5848830f PB |
4651 | /* Varargs vectors are treated the same as long long. |
4652 | named_count avoids having to change the way arm handles 'named' */ | |
4653 | if (TARGET_IWMMXT_ABI | |
f676971a | 4654 | && arm_vector_mode_supported_p (mode) |
5848830f | 4655 | && pcum->named_count > pcum->nargs + 1) |
5a9335ef | 4656 | { |
5848830f PB |
4657 | if (pcum->iwmmxt_nregs <= 9) |
4658 | return gen_rtx_REG (mode, pcum->iwmmxt_nregs + FIRST_IWMMXT_REGNUM); | |
4659 | else | |
5a9335ef | 4660 | { |
5848830f PB |
4661 | pcum->can_split = false; |
4662 | return NULL_RTX; | |
5a9335ef | 4663 | } |
5a9335ef NC |
4664 | } |
4665 | ||
5848830f PB |
4666 | /* Put doubleword aligned quantities in even register pairs. */ |
4667 | if (pcum->nregs & 1 | |
4668 | && ARM_DOUBLEWORD_ALIGN | |
4669 | && arm_needs_doubleword_align (mode, type)) | |
4670 | pcum->nregs++; | |
4671 | ||
666c27b9 | 4672 | /* Only allow splitting an arg between regs and memory if all preceding |
5848830f PB |
4673 | args were allocated to regs. For args passed by reference we only count |
4674 | the reference pointer. */ | |
4675 | if (pcum->can_split) | |
4676 | nregs = 1; | |
4677 | else | |
4678 | nregs = ARM_NUM_REGS2 (mode, type); | |
4679 | ||
4680 | if (!named || pcum->nregs + nregs > NUM_ARG_REGS) | |
82e9d970 | 4681 | return NULL_RTX; |
f676971a | 4682 | |
82e9d970 PB |
4683 | return gen_rtx_REG (mode, pcum->nregs); |
4684 | } | |
1741620c | 4685 | |
c2ed6cf8 NF |
4686 | static unsigned int |
4687 | arm_function_arg_boundary (enum machine_mode mode, const_tree type) | |
4688 | { | |
4689 | return (ARM_DOUBLEWORD_ALIGN && arm_needs_doubleword_align (mode, type) | |
4690 | ? DOUBLEWORD_ALIGNMENT | |
4691 | : PARM_BOUNDARY); | |
4692 | } | |
4693 | ||
78a52f11 RH |
4694 | static int |
4695 | arm_arg_partial_bytes (CUMULATIVE_ARGS *pcum, enum machine_mode mode, | |
390b17c2 | 4696 | tree type, bool named) |
78a52f11 RH |
4697 | { |
4698 | int nregs = pcum->nregs; | |
4699 | ||
390b17c2 RE |
4700 | if (pcum->pcs_variant <= ARM_PCS_AAPCS_LOCAL) |
4701 | { | |
4702 | aapcs_layout_arg (pcum, mode, type, named); | |
4703 | return pcum->aapcs_partial; | |
4704 | } | |
4705 | ||
88f77cba | 4706 | if (TARGET_IWMMXT_ABI && arm_vector_mode_supported_p (mode)) |
78a52f11 RH |
4707 | return 0; |
4708 | ||
4709 | if (NUM_ARG_REGS > nregs | |
4710 | && (NUM_ARG_REGS < nregs + ARM_NUM_REGS2 (mode, type)) | |
4711 | && pcum->can_split) | |
4712 | return (NUM_ARG_REGS - nregs) * UNITS_PER_WORD; | |
4713 | ||
4714 | return 0; | |
4715 | } | |
4716 | ||
9c6a2bee NF |
4717 | /* Update the data in PCUM to advance over an argument |
4718 | of mode MODE and data type TYPE. | |
4719 | (TYPE is null for libcalls where that information may not be available.) */ | |
4720 | ||
4721 | static void | |
390b17c2 | 4722 | arm_function_arg_advance (CUMULATIVE_ARGS *pcum, enum machine_mode mode, |
9c6a2bee | 4723 | const_tree type, bool named) |
390b17c2 RE |
4724 | { |
4725 | if (pcum->pcs_variant <= ARM_PCS_AAPCS_LOCAL) | |
4726 | { | |
4727 | aapcs_layout_arg (pcum, mode, type, named); | |
4728 | ||
4729 | if (pcum->aapcs_cprc_slot >= 0) | |
4730 | { | |
4731 | aapcs_cp_arg_layout[pcum->aapcs_cprc_slot].advance (pcum, mode, | |
4732 | type); | |
4733 | pcum->aapcs_cprc_slot = -1; | |
4734 | } | |
4735 | ||
4736 | /* Generic stuff. */ | |
4737 | pcum->aapcs_arg_processed = false; | |
4738 | pcum->aapcs_ncrn = pcum->aapcs_next_ncrn; | |
4739 | pcum->aapcs_reg = NULL_RTX; | |
4740 | pcum->aapcs_partial = 0; | |
4741 | } | |
4742 | else | |
4743 | { | |
4744 | pcum->nargs += 1; | |
4745 | if (arm_vector_mode_supported_p (mode) | |
4746 | && pcum->named_count > pcum->nargs | |
4747 | && TARGET_IWMMXT_ABI) | |
4748 | pcum->iwmmxt_nregs += 1; | |
4749 | else | |
4750 | pcum->nregs += ARM_NUM_REGS2 (mode, type); | |
4751 | } | |
4752 | } | |
4753 | ||
1741620c JD |
4754 | /* Variable sized types are passed by reference. This is a GCC |
4755 | extension to the ARM ABI. */ | |
4756 | ||
8cd5a4e0 RH |
4757 | static bool |
4758 | arm_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED, | |
4759 | enum machine_mode mode ATTRIBUTE_UNUSED, | |
586de218 | 4760 | const_tree type, bool named ATTRIBUTE_UNUSED) |
1741620c JD |
4761 | { |
4762 | return type && TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST; | |
4763 | } | |
82e9d970 | 4764 | \f |
c27ba912 DM |
4765 | /* Encode the current state of the #pragma [no_]long_calls. */ |
4766 | typedef enum | |
82e9d970 | 4767 | { |
6fc0bb99 | 4768 | OFF, /* No #pragma [no_]long_calls is in effect. */ |
c27ba912 DM |
4769 | LONG, /* #pragma long_calls is in effect. */ |
4770 | SHORT /* #pragma no_long_calls is in effect. */ | |
4771 | } arm_pragma_enum; | |
82e9d970 | 4772 | |
c27ba912 | 4773 | static arm_pragma_enum arm_pragma_long_calls = OFF; |
82e9d970 | 4774 | |
8b97c5f8 | 4775 | void |
e32bac5b | 4776 | arm_pr_long_calls (struct cpp_reader * pfile ATTRIBUTE_UNUSED) |
82e9d970 | 4777 | { |
8b97c5f8 ZW |
4778 | arm_pragma_long_calls = LONG; |
4779 | } | |
4780 | ||
4781 | void | |
e32bac5b | 4782 | arm_pr_no_long_calls (struct cpp_reader * pfile ATTRIBUTE_UNUSED) |
8b97c5f8 ZW |
4783 | { |
4784 | arm_pragma_long_calls = SHORT; | |
4785 | } | |
4786 | ||
4787 | void | |
e32bac5b | 4788 | arm_pr_long_calls_off (struct cpp_reader * pfile ATTRIBUTE_UNUSED) |
8b97c5f8 ZW |
4789 | { |
4790 | arm_pragma_long_calls = OFF; | |
82e9d970 PB |
4791 | } |
4792 | \f | |
91d231cb JM |
4793 | /* Handle an attribute requiring a FUNCTION_DECL; |
4794 | arguments as in struct attribute_spec.handler. */ | |
4795 | static tree | |
e32bac5b RE |
4796 | arm_handle_fndecl_attribute (tree *node, tree name, tree args ATTRIBUTE_UNUSED, |
4797 | int flags ATTRIBUTE_UNUSED, bool *no_add_attrs) | |
91d231cb JM |
4798 | { |
4799 | if (TREE_CODE (*node) != FUNCTION_DECL) | |
4800 | { | |
29d08eba JM |
4801 | warning (OPT_Wattributes, "%qE attribute only applies to functions", |
4802 | name); | |
91d231cb JM |
4803 | *no_add_attrs = true; |
4804 | } | |
4805 | ||
4806 | return NULL_TREE; | |
4807 | } | |
4808 | ||
4809 | /* Handle an "interrupt" or "isr" attribute; | |
4810 | arguments as in struct attribute_spec.handler. */ | |
4811 | static tree | |
e32bac5b RE |
4812 | arm_handle_isr_attribute (tree *node, tree name, tree args, int flags, |
4813 | bool *no_add_attrs) | |
91d231cb JM |
4814 | { |
4815 | if (DECL_P (*node)) | |
4816 | { | |
4817 | if (TREE_CODE (*node) != FUNCTION_DECL) | |
4818 | { | |
29d08eba JM |
4819 | warning (OPT_Wattributes, "%qE attribute only applies to functions", |
4820 | name); | |
91d231cb JM |
4821 | *no_add_attrs = true; |
4822 | } | |
4823 | /* FIXME: the argument if any is checked for type attributes; | |
4824 | should it be checked for decl ones? */ | |
4825 | } | |
4826 | else | |
4827 | { | |
4828 | if (TREE_CODE (*node) == FUNCTION_TYPE | |
4829 | || TREE_CODE (*node) == METHOD_TYPE) | |
4830 | { | |
4831 | if (arm_isr_value (args) == ARM_FT_UNKNOWN) | |
4832 | { | |
29d08eba JM |
4833 | warning (OPT_Wattributes, "%qE attribute ignored", |
4834 | name); | |
91d231cb JM |
4835 | *no_add_attrs = true; |
4836 | } | |
4837 | } | |
4838 | else if (TREE_CODE (*node) == POINTER_TYPE | |
4839 | && (TREE_CODE (TREE_TYPE (*node)) == FUNCTION_TYPE | |
4840 | || TREE_CODE (TREE_TYPE (*node)) == METHOD_TYPE) | |
4841 | && arm_isr_value (args) != ARM_FT_UNKNOWN) | |
4842 | { | |
8dd16ecc | 4843 | *node = build_variant_type_copy (*node); |
1d6e90ac NC |
4844 | TREE_TYPE (*node) = build_type_attribute_variant |
4845 | (TREE_TYPE (*node), | |
4846 | tree_cons (name, args, TYPE_ATTRIBUTES (TREE_TYPE (*node)))); | |
91d231cb JM |
4847 | *no_add_attrs = true; |
4848 | } | |
4849 | else | |
4850 | { | |
4851 | /* Possibly pass this attribute on from the type to a decl. */ | |
4852 | if (flags & ((int) ATTR_FLAG_DECL_NEXT | |
4853 | | (int) ATTR_FLAG_FUNCTION_NEXT | |
4854 | | (int) ATTR_FLAG_ARRAY_NEXT)) | |
4855 | { | |
4856 | *no_add_attrs = true; | |
4857 | return tree_cons (name, args, NULL_TREE); | |
4858 | } | |
4859 | else | |
4860 | { | |
29d08eba JM |
4861 | warning (OPT_Wattributes, "%qE attribute ignored", |
4862 | name); | |
91d231cb JM |
4863 | } |
4864 | } | |
4865 | } | |
4866 | ||
4867 | return NULL_TREE; | |
82e9d970 PB |
4868 | } |
4869 | ||
390b17c2 RE |
4870 | /* Handle a "pcs" attribute; arguments as in struct |
4871 | attribute_spec.handler. */ | |
4872 | static tree | |
4873 | arm_handle_pcs_attribute (tree *node ATTRIBUTE_UNUSED, tree name, tree args, | |
4874 | int flags ATTRIBUTE_UNUSED, bool *no_add_attrs) | |
4875 | { | |
4876 | if (arm_pcs_from_attribute (args) == ARM_PCS_UNKNOWN) | |
4877 | { | |
a9717079 | 4878 | warning (OPT_Wattributes, "%qE attribute ignored", name); |
390b17c2 RE |
4879 | *no_add_attrs = true; |
4880 | } | |
4881 | return NULL_TREE; | |
4882 | } | |
4883 | ||
7bff66a7 | 4884 | #if TARGET_DLLIMPORT_DECL_ATTRIBUTES |
04fb56d5 MM |
4885 | /* Handle the "notshared" attribute. This attribute is another way of |
4886 | requesting hidden visibility. ARM's compiler supports | |
4887 | "__declspec(notshared)"; we support the same thing via an | |
4888 | attribute. */ | |
4889 | ||
4890 | static tree | |
e0b92319 NC |
4891 | arm_handle_notshared_attribute (tree *node, |
4892 | tree name ATTRIBUTE_UNUSED, | |
4893 | tree args ATTRIBUTE_UNUSED, | |
4894 | int flags ATTRIBUTE_UNUSED, | |
04fb56d5 MM |
4895 | bool *no_add_attrs) |
4896 | { | |
4897 | tree decl = TYPE_NAME (*node); | |
4898 | ||
4899 | if (decl) | |
4900 | { | |
4901 | DECL_VISIBILITY (decl) = VISIBILITY_HIDDEN; | |
4902 | DECL_VISIBILITY_SPECIFIED (decl) = 1; | |
4903 | *no_add_attrs = false; | |
4904 | } | |
4905 | return NULL_TREE; | |
4906 | } | |
7bff66a7 | 4907 | #endif |
04fb56d5 | 4908 | |
82e9d970 PB |
4909 | /* Return 0 if the attributes for two types are incompatible, 1 if they |
4910 | are compatible, and 2 if they are nearly compatible (which causes a | |
4911 | warning to be generated). */ | |
8d8e52be | 4912 | static int |
3101faab | 4913 | arm_comp_type_attributes (const_tree type1, const_tree type2) |
82e9d970 | 4914 | { |
1cb8d58a | 4915 | int l1, l2, s1, s2; |
f676971a | 4916 | |
82e9d970 PB |
4917 | /* Check for mismatch of non-default calling convention. */ |
4918 | if (TREE_CODE (type1) != FUNCTION_TYPE) | |
4919 | return 1; | |
4920 | ||
4921 | /* Check for mismatched call attributes. */ | |
1cb8d58a NC |
4922 | l1 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type1)) != NULL; |
4923 | l2 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type2)) != NULL; | |
4924 | s1 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type1)) != NULL; | |
4925 | s2 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type2)) != NULL; | |
bd7fc26f NC |
4926 | |
4927 | /* Only bother to check if an attribute is defined. */ | |
4928 | if (l1 | l2 | s1 | s2) | |
4929 | { | |
4930 | /* If one type has an attribute, the other must have the same attribute. */ | |
1cb8d58a | 4931 | if ((l1 != l2) || (s1 != s2)) |
bd7fc26f | 4932 | return 0; |
82e9d970 | 4933 | |
bd7fc26f NC |
4934 | /* Disallow mixed attributes. */ |
4935 | if ((l1 & s2) || (l2 & s1)) | |
4936 | return 0; | |
4937 | } | |
f676971a | 4938 | |
6d3d9133 NC |
4939 | /* Check for mismatched ISR attribute. */ |
4940 | l1 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type1)) != NULL; | |
4941 | if (! l1) | |
4942 | l1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type1)) != NULL; | |
4943 | l2 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type2)) != NULL; | |
4944 | if (! l2) | |
4945 | l1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type2)) != NULL; | |
4946 | if (l1 != l2) | |
4947 | return 0; | |
4948 | ||
bd7fc26f | 4949 | return 1; |
82e9d970 PB |
4950 | } |
4951 | ||
c27ba912 DM |
4952 | /* Assigns default attributes to newly defined type. This is used to |
4953 | set short_call/long_call attributes for function types of | |
4954 | functions defined inside corresponding #pragma scopes. */ | |
8d8e52be | 4955 | static void |
e32bac5b | 4956 | arm_set_default_type_attributes (tree type) |
c27ba912 DM |
4957 | { |
4958 | /* Add __attribute__ ((long_call)) to all functions, when | |
4959 | inside #pragma long_calls or __attribute__ ((short_call)), | |
4960 | when inside #pragma no_long_calls. */ | |
4961 | if (TREE_CODE (type) == FUNCTION_TYPE || TREE_CODE (type) == METHOD_TYPE) | |
4962 | { | |
4963 | tree type_attr_list, attr_name; | |
4964 | type_attr_list = TYPE_ATTRIBUTES (type); | |
4965 | ||
4966 | if (arm_pragma_long_calls == LONG) | |
4967 | attr_name = get_identifier ("long_call"); | |
4968 | else if (arm_pragma_long_calls == SHORT) | |
4969 | attr_name = get_identifier ("short_call"); | |
4970 | else | |
4971 | return; | |
4972 | ||
4973 | type_attr_list = tree_cons (attr_name, NULL_TREE, type_attr_list); | |
4974 | TYPE_ATTRIBUTES (type) = type_attr_list; | |
4975 | } | |
4976 | } | |
4977 | \f | |
25a65198 RS |
4978 | /* Return true if DECL is known to be linked into section SECTION. */ |
4979 | ||
4980 | static bool | |
4981 | arm_function_in_section_p (tree decl, section *section) | |
c27ba912 | 4982 | { |
25a65198 RS |
4983 | /* We can only be certain about functions defined in the same |
4984 | compilation unit. */ | |
4985 | if (!TREE_STATIC (decl)) | |
4986 | return false; | |
c27ba912 | 4987 | |
25a65198 RS |
4988 | /* Make sure that SYMBOL always binds to the definition in this |
4989 | compilation unit. */ | |
4990 | if (!targetm.binds_local_p (decl)) | |
4991 | return false; | |
c27ba912 | 4992 | |
25a65198 RS |
4993 | /* If DECL_SECTION_NAME is set, assume it is trustworthy. */ |
4994 | if (!DECL_SECTION_NAME (decl)) | |
4995 | { | |
25a65198 RS |
4996 | /* Make sure that we will not create a unique section for DECL. */ |
4997 | if (flag_function_sections || DECL_ONE_ONLY (decl)) | |
4998 | return false; | |
4999 | } | |
5000 | ||
5001 | return function_section (decl) == section; | |
c27ba912 DM |
5002 | } |
5003 | ||
a50aa827 | 5004 | /* Return nonzero if a 32-bit "long_call" should be generated for |
25a65198 RS |
5005 | a call from the current function to DECL. We generate a long_call |
5006 | if the function: | |
c27ba912 DM |
5007 | |
5008 | a. has an __attribute__((long call)) | |
5009 | or b. is within the scope of a #pragma long_calls | |
5010 | or c. the -mlong-calls command line switch has been specified | |
5011 | ||
5012 | However we do not generate a long call if the function: | |
f676971a | 5013 | |
c27ba912 DM |
5014 | d. has an __attribute__ ((short_call)) |
5015 | or e. is inside the scope of a #pragma no_long_calls | |
25a65198 | 5016 | or f. is defined in the same section as the current function. */ |
c27ba912 | 5017 | |
25a65198 RS |
5018 | bool |
5019 | arm_is_long_call_p (tree decl) | |
5020 | { | |
5021 | tree attrs; | |
c27ba912 | 5022 | |
25a65198 RS |
5023 | if (!decl) |
5024 | return TARGET_LONG_CALLS; | |
c27ba912 | 5025 | |
25a65198 RS |
5026 | attrs = TYPE_ATTRIBUTES (TREE_TYPE (decl)); |
5027 | if (lookup_attribute ("short_call", attrs)) | |
5028 | return false; | |
c27ba912 | 5029 | |
25a65198 RS |
5030 | /* For "f", be conservative, and only cater for cases in which the |
5031 | whole of the current function is placed in the same section. */ | |
5032 | if (!flag_reorder_blocks_and_partition | |
b3a796bc | 5033 | && TREE_CODE (decl) == FUNCTION_DECL |
25a65198 RS |
5034 | && arm_function_in_section_p (decl, current_function_section ())) |
5035 | return false; | |
a77655b1 | 5036 | |
25a65198 RS |
5037 | if (lookup_attribute ("long_call", attrs)) |
5038 | return true; | |
f676971a | 5039 | |
25a65198 | 5040 | return TARGET_LONG_CALLS; |
c27ba912 | 5041 | } |
f99fce0c | 5042 | |
825dda42 | 5043 | /* Return nonzero if it is ok to make a tail-call to DECL. */ |
4977bab6 | 5044 | static bool |
390b17c2 | 5045 | arm_function_ok_for_sibcall (tree decl, tree exp) |
f99fce0c | 5046 | { |
5b3e6663 | 5047 | unsigned long func_type; |
f99fce0c | 5048 | |
5a9335ef NC |
5049 | if (cfun->machine->sibcall_blocked) |
5050 | return false; | |
5051 | ||
f99fce0c | 5052 | /* Never tailcall something for which we have no decl, or if we |
7c19c715 JB |
5053 | are generating code for Thumb-1. */ |
5054 | if (decl == NULL || TARGET_THUMB1) | |
4977bab6 | 5055 | return false; |
f99fce0c | 5056 | |
9403b7f7 RS |
5057 | /* The PIC register is live on entry to VxWorks PLT entries, so we |
5058 | must make the call before restoring the PIC register. */ | |
5059 | if (TARGET_VXWORKS_RTP && flag_pic && !targetm.binds_local_p (decl)) | |
5060 | return false; | |
5061 | ||
f99fce0c | 5062 | /* Cannot tail-call to long calls, since these are out of range of |
25a65198 RS |
5063 | a branch instruction. */ |
5064 | if (arm_is_long_call_p (decl)) | |
4977bab6 | 5065 | return false; |
f99fce0c RE |
5066 | |
5067 | /* If we are interworking and the function is not declared static | |
f676971a | 5068 | then we can't tail-call it unless we know that it exists in this |
f99fce0c | 5069 | compilation unit (since it might be a Thumb routine). */ |
5895f793 | 5070 | if (TARGET_INTERWORK && TREE_PUBLIC (decl) && !TREE_ASM_WRITTEN (decl)) |
4977bab6 | 5071 | return false; |
f99fce0c | 5072 | |
5b3e6663 | 5073 | func_type = arm_current_func_type (); |
6d3d9133 | 5074 | /* Never tailcall from an ISR routine - it needs a special exit sequence. */ |
5b3e6663 PB |
5075 | if (IS_INTERRUPT (func_type)) |
5076 | return false; | |
5077 | ||
390b17c2 RE |
5078 | if (!VOID_TYPE_P (TREE_TYPE (DECL_RESULT (cfun->decl)))) |
5079 | { | |
5080 | /* Check that the return value locations are the same. For | |
5081 | example that we aren't returning a value from the sibling in | |
5082 | a VFP register but then need to transfer it to a core | |
5083 | register. */ | |
5084 | rtx a, b; | |
5085 | ||
5086 | a = arm_function_value (TREE_TYPE (exp), decl, false); | |
5087 | b = arm_function_value (TREE_TYPE (DECL_RESULT (cfun->decl)), | |
5088 | cfun->decl, false); | |
5089 | if (!rtx_equal_p (a, b)) | |
5090 | return false; | |
5091 | } | |
5092 | ||
5b3e6663 PB |
5093 | /* Never tailcall if function may be called with a misaligned SP. */ |
5094 | if (IS_STACKALIGN (func_type)) | |
4977bab6 | 5095 | return false; |
6d3d9133 | 5096 | |
f99fce0c | 5097 | /* Everything else is ok. */ |
4977bab6 | 5098 | return true; |
f99fce0c RE |
5099 | } |
5100 | ||
82e9d970 | 5101 | \f |
6b990f6b RE |
5102 | /* Addressing mode support functions. */ |
5103 | ||
0b4be7de | 5104 | /* Return nonzero if X is a legitimate immediate operand when compiling |
020a4035 | 5105 | for PIC. We know that X satisfies CONSTANT_P and flag_pic is true. */ |
32de079a | 5106 | int |
e32bac5b | 5107 | legitimate_pic_operand_p (rtx x) |
32de079a | 5108 | { |
020a4035 RE |
5109 | if (GET_CODE (x) == SYMBOL_REF |
5110 | || (GET_CODE (x) == CONST | |
5111 | && GET_CODE (XEXP (x, 0)) == PLUS | |
5112 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF)) | |
32de079a RE |
5113 | return 0; |
5114 | ||
5115 | return 1; | |
5116 | } | |
5117 | ||
9403b7f7 RS |
5118 | /* Record that the current function needs a PIC register. Initialize |
5119 | cfun->machine->pic_reg if we have not already done so. */ | |
5120 | ||
5121 | static void | |
5122 | require_pic_register (void) | |
5123 | { | |
5124 | /* A lot of the logic here is made obscure by the fact that this | |
5125 | routine gets called as part of the rtx cost estimation process. | |
5126 | We don't want those calls to affect any assumptions about the real | |
5127 | function; and further, we can't call entry_of_function() until we | |
5128 | start the real expansion process. */ | |
e3b5732b | 5129 | if (!crtl->uses_pic_offset_table) |
9403b7f7 | 5130 | { |
b3a13419 | 5131 | gcc_assert (can_create_pseudo_p ()); |
9403b7f7 RS |
5132 | if (arm_pic_register != INVALID_REGNUM) |
5133 | { | |
6d2538f5 JB |
5134 | if (!cfun->machine->pic_reg) |
5135 | cfun->machine->pic_reg = gen_rtx_REG (Pmode, arm_pic_register); | |
9403b7f7 RS |
5136 | |
5137 | /* Play games to avoid marking the function as needing pic | |
5138 | if we are being called as part of the cost-estimation | |
5139 | process. */ | |
04ef80ce | 5140 | if (current_ir_type () != IR_GIMPLE || currently_expanding_to_rtl) |
e3b5732b | 5141 | crtl->uses_pic_offset_table = 1; |
9403b7f7 RS |
5142 | } |
5143 | else | |
5144 | { | |
cb227aa9 | 5145 | rtx seq, insn; |
9403b7f7 | 5146 | |
6d2538f5 JB |
5147 | if (!cfun->machine->pic_reg) |
5148 | cfun->machine->pic_reg = gen_reg_rtx (Pmode); | |
9403b7f7 RS |
5149 | |
5150 | /* Play games to avoid marking the function as needing pic | |
5151 | if we are being called as part of the cost-estimation | |
5152 | process. */ | |
04ef80ce | 5153 | if (current_ir_type () != IR_GIMPLE || currently_expanding_to_rtl) |
9403b7f7 | 5154 | { |
e3b5732b | 5155 | crtl->uses_pic_offset_table = 1; |
9403b7f7 RS |
5156 | start_sequence (); |
5157 | ||
5158 | arm_load_pic_register (0UL); | |
5159 | ||
5160 | seq = get_insns (); | |
5161 | end_sequence (); | |
cb227aa9 UW |
5162 | |
5163 | for (insn = seq; insn; insn = NEXT_INSN (insn)) | |
5164 | if (INSN_P (insn)) | |
5165 | INSN_LOCATOR (insn) = prologue_locator; | |
5166 | ||
af618949 MM |
5167 | /* We can be called during expansion of PHI nodes, where |
5168 | we can't yet emit instructions directly in the final | |
5169 | insn stream. Queue the insns on the entry edge, they will | |
5170 | be committed after everything else is expanded. */ | |
5171 | insert_insn_on_edge (seq, single_succ_edge (ENTRY_BLOCK_PTR)); | |
9403b7f7 RS |
5172 | } |
5173 | } | |
5174 | } | |
5175 | } | |
5176 | ||
32de079a | 5177 | rtx |
e32bac5b | 5178 | legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg) |
32de079a | 5179 | { |
a3c48721 RE |
5180 | if (GET_CODE (orig) == SYMBOL_REF |
5181 | || GET_CODE (orig) == LABEL_REF) | |
32de079a | 5182 | { |
32de079a | 5183 | rtx insn; |
020a4035 | 5184 | |
32de079a RE |
5185 | if (reg == 0) |
5186 | { | |
b3a13419 | 5187 | gcc_assert (can_create_pseudo_p ()); |
e6d29d15 | 5188 | reg = gen_reg_rtx (Pmode); |
32de079a | 5189 | } |
32de079a | 5190 | |
9403b7f7 RS |
5191 | /* VxWorks does not impose a fixed gap between segments; the run-time |
5192 | gap can be different from the object-file gap. We therefore can't | |
5193 | use GOTOFF unless we are absolutely sure that the symbol is in the | |
5194 | same segment as the GOT. Unfortunately, the flexibility of linker | |
5195 | scripts means that we can't be sure of that in general, so assume | |
5196 | that GOTOFF is never valid on VxWorks. */ | |
14f583b8 | 5197 | if ((GET_CODE (orig) == LABEL_REF |
f676971a | 5198 | || (GET_CODE (orig) == SYMBOL_REF && |
94428622 | 5199 | SYMBOL_REF_LOCAL_P (orig))) |
9403b7f7 RS |
5200 | && NEED_GOT_RELOC |
5201 | && !TARGET_VXWORKS_RTP) | |
85c9bcd4 | 5202 | insn = arm_pic_static_addr (orig, reg); |
a3c48721 RE |
5203 | else |
5204 | { | |
d37c3c62 MK |
5205 | rtx pat; |
5206 | rtx mem; | |
5207 | ||
85c9bcd4 WG |
5208 | /* If this function doesn't have a pic register, create one now. */ |
5209 | require_pic_register (); | |
5210 | ||
d37c3c62 | 5211 | pat = gen_calculate_pic_address (reg, cfun->machine->pic_reg, orig); |
85c9bcd4 | 5212 | |
d37c3c62 MK |
5213 | /* Make the MEM as close to a constant as possible. */ |
5214 | mem = SET_SRC (pat); | |
5215 | gcc_assert (MEM_P (mem) && !MEM_VOLATILE_P (mem)); | |
5216 | MEM_READONLY_P (mem) = 1; | |
5217 | MEM_NOTRAP_P (mem) = 1; | |
5218 | ||
5219 | insn = emit_insn (pat); | |
a3c48721 RE |
5220 | } |
5221 | ||
32de079a RE |
5222 | /* Put a REG_EQUAL note on this insn, so that it can be optimized |
5223 | by loop. */ | |
bd94cb6e SB |
5224 | set_unique_reg_note (insn, REG_EQUAL, orig); |
5225 | ||
32de079a RE |
5226 | return reg; |
5227 | } | |
5228 | else if (GET_CODE (orig) == CONST) | |
5229 | { | |
5230 | rtx base, offset; | |
5231 | ||
5232 | if (GET_CODE (XEXP (orig, 0)) == PLUS | |
020a4035 | 5233 | && XEXP (XEXP (orig, 0), 0) == cfun->machine->pic_reg) |
32de079a RE |
5234 | return orig; |
5235 | ||
f67358da | 5236 | /* Handle the case where we have: const (UNSPEC_TLS). */ |
d3585b76 DJ |
5237 | if (GET_CODE (XEXP (orig, 0)) == UNSPEC |
5238 | && XINT (XEXP (orig, 0), 1) == UNSPEC_TLS) | |
5239 | return orig; | |
5240 | ||
f67358da PB |
5241 | /* Handle the case where we have: |
5242 | const (plus (UNSPEC_TLS) (ADDEND)). The ADDEND must be a | |
5243 | CONST_INT. */ | |
5244 | if (GET_CODE (XEXP (orig, 0)) == PLUS | |
5245 | && GET_CODE (XEXP (XEXP (orig, 0), 0)) == UNSPEC | |
5246 | && XINT (XEXP (XEXP (orig, 0), 0), 1) == UNSPEC_TLS) | |
5247 | { | |
5248 | gcc_assert (GET_CODE (XEXP (XEXP (orig, 0), 1)) == CONST_INT); | |
5249 | return orig; | |
5250 | } | |
5251 | ||
32de079a RE |
5252 | if (reg == 0) |
5253 | { | |
b3a13419 | 5254 | gcc_assert (can_create_pseudo_p ()); |
e6d29d15 | 5255 | reg = gen_reg_rtx (Pmode); |
32de079a RE |
5256 | } |
5257 | ||
e6d29d15 | 5258 | gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS); |
e0b92319 | 5259 | |
e6d29d15 NS |
5260 | base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg); |
5261 | offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode, | |
5262 | base == reg ? 0 : reg); | |
32de079a RE |
5263 | |
5264 | if (GET_CODE (offset) == CONST_INT) | |
5265 | { | |
5266 | /* The base register doesn't really matter, we only want to | |
5267 | test the index for the appropriate mode. */ | |
1e1ab407 | 5268 | if (!arm_legitimate_index_p (mode, offset, SET, 0)) |
6b990f6b | 5269 | { |
b3a13419 | 5270 | gcc_assert (can_create_pseudo_p ()); |
e6d29d15 | 5271 | offset = force_reg (Pmode, offset); |
6b990f6b | 5272 | } |
32de079a | 5273 | |
32de079a | 5274 | if (GET_CODE (offset) == CONST_INT) |
ed8908e7 | 5275 | return plus_constant (base, INTVAL (offset)); |
32de079a RE |
5276 | } |
5277 | ||
5278 | if (GET_MODE_SIZE (mode) > 4 | |
5279 | && (GET_MODE_CLASS (mode) == MODE_INT | |
5280 | || TARGET_SOFT_FLOAT)) | |
5281 | { | |
5282 | emit_insn (gen_addsi3 (reg, base, offset)); | |
5283 | return reg; | |
5284 | } | |
5285 | ||
43cffd11 | 5286 | return gen_rtx_PLUS (Pmode, base, offset); |
32de079a | 5287 | } |
32de079a RE |
5288 | |
5289 | return orig; | |
5290 | } | |
5291 | ||
57934c39 | 5292 | |
5b3e6663 | 5293 | /* Find a spare register to use during the prolog of a function. */ |
57934c39 PB |
5294 | |
5295 | static int | |
b279b20a | 5296 | thumb_find_work_register (unsigned long pushed_regs_mask) |
57934c39 PB |
5297 | { |
5298 | int reg; | |
5299 | ||
b279b20a NC |
5300 | /* Check the argument registers first as these are call-used. The |
5301 | register allocation order means that sometimes r3 might be used | |
5302 | but earlier argument registers might not, so check them all. */ | |
5303 | for (reg = LAST_ARG_REGNUM; reg >= 0; reg --) | |
6fb5fa3c | 5304 | if (!df_regs_ever_live_p (reg)) |
b279b20a NC |
5305 | return reg; |
5306 | ||
5307 | /* Before going on to check the call-saved registers we can try a couple | |
5308 | more ways of deducing that r3 is available. The first is when we are | |
5309 | pushing anonymous arguments onto the stack and we have less than 4 | |
5310 | registers worth of fixed arguments(*). In this case r3 will be part of | |
5311 | the variable argument list and so we can be sure that it will be | |
5312 | pushed right at the start of the function. Hence it will be available | |
5313 | for the rest of the prologue. | |
38173d38 | 5314 | (*): ie crtl->args.pretend_args_size is greater than 0. */ |
b279b20a | 5315 | if (cfun->machine->uses_anonymous_args |
38173d38 | 5316 | && crtl->args.pretend_args_size > 0) |
57934c39 PB |
5317 | return LAST_ARG_REGNUM; |
5318 | ||
b279b20a NC |
5319 | /* The other case is when we have fixed arguments but less than 4 registers |
5320 | worth. In this case r3 might be used in the body of the function, but | |
5321 | it is not being used to convey an argument into the function. In theory | |
38173d38 | 5322 | we could just check crtl->args.size to see how many bytes are |
b279b20a NC |
5323 | being passed in argument registers, but it seems that it is unreliable. |
5324 | Sometimes it will have the value 0 when in fact arguments are being | |
5325 | passed. (See testcase execute/20021111-1.c for an example). So we also | |
5326 | check the args_info.nregs field as well. The problem with this field is | |
5327 | that it makes no allowances for arguments that are passed to the | |
5328 | function but which are not used. Hence we could miss an opportunity | |
5329 | when a function has an unused argument in r3. But it is better to be | |
5330 | safe than to be sorry. */ | |
5331 | if (! cfun->machine->uses_anonymous_args | |
38173d38 JH |
5332 | && crtl->args.size >= 0 |
5333 | && crtl->args.size <= (LAST_ARG_REGNUM * UNITS_PER_WORD) | |
f6d2671e | 5334 | && crtl->args.info.nregs < 4) |
b279b20a | 5335 | return LAST_ARG_REGNUM; |
e0b92319 | 5336 | |
b279b20a NC |
5337 | /* Otherwise look for a call-saved register that is going to be pushed. */ |
5338 | for (reg = LAST_LO_REGNUM; reg > LAST_ARG_REGNUM; reg --) | |
5339 | if (pushed_regs_mask & (1 << reg)) | |
57934c39 PB |
5340 | return reg; |
5341 | ||
5b3e6663 PB |
5342 | if (TARGET_THUMB2) |
5343 | { | |
5344 | /* Thumb-2 can use high regs. */ | |
5345 | for (reg = FIRST_HI_REGNUM; reg < 15; reg ++) | |
5346 | if (pushed_regs_mask & (1 << reg)) | |
5347 | return reg; | |
5348 | } | |
b279b20a NC |
5349 | /* Something went wrong - thumb_compute_save_reg_mask() |
5350 | should have arranged for a suitable register to be pushed. */ | |
e6d29d15 | 5351 | gcc_unreachable (); |
57934c39 PB |
5352 | } |
5353 | ||
f16fe45f | 5354 | static GTY(()) int pic_labelno; |
876f13b0 | 5355 | |
fe013435 PB |
5356 | /* Generate code to load the PIC register. In thumb mode SCRATCH is a |
5357 | low register. */ | |
876f13b0 | 5358 | |
32de079a | 5359 | void |
e55ef7f4 | 5360 | arm_load_pic_register (unsigned long saved_regs ATTRIBUTE_UNUSED) |
32de079a | 5361 | { |
f9bd1a89 | 5362 | rtx l1, labelno, pic_tmp, pic_rtx, pic_reg; |
32de079a | 5363 | |
e3b5732b | 5364 | if (crtl->uses_pic_offset_table == 0 || TARGET_SINGLE_PIC_BASE) |
32de079a RE |
5365 | return; |
5366 | ||
e6d29d15 | 5367 | gcc_assert (flag_pic); |
32de079a | 5368 | |
9403b7f7 RS |
5369 | pic_reg = cfun->machine->pic_reg; |
5370 | if (TARGET_VXWORKS_RTP) | |
5371 | { | |
5372 | pic_rtx = gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_BASE); | |
5373 | pic_rtx = gen_rtx_CONST (Pmode, pic_rtx); | |
87d05b44 | 5374 | emit_insn (gen_pic_load_addr_32bit (pic_reg, pic_rtx)); |
43cffd11 | 5375 | |
9403b7f7 | 5376 | emit_insn (gen_rtx_SET (Pmode, pic_reg, gen_rtx_MEM (Pmode, pic_reg))); |
f676971a | 5377 | |
9403b7f7 RS |
5378 | pic_tmp = gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_INDEX); |
5379 | emit_insn (gen_pic_offset_arm (pic_reg, pic_reg, pic_tmp)); | |
4bec9f7d | 5380 | } |
9403b7f7 | 5381 | else |
5b3e6663 | 5382 | { |
9403b7f7 RS |
5383 | /* We use an UNSPEC rather than a LABEL_REF because this label |
5384 | never appears in the code stream. */ | |
5385 | ||
5386 | labelno = GEN_INT (pic_labelno++); | |
5387 | l1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, labelno), UNSPEC_PIC_LABEL); | |
5388 | l1 = gen_rtx_CONST (VOIDmode, l1); | |
5389 | ||
9403b7f7 RS |
5390 | /* On the ARM the PC register contains 'dot + 8' at the time of the |
5391 | addition, on the Thumb it is 'dot + 4'. */ | |
f9bd1a89 RS |
5392 | pic_rtx = plus_constant (l1, TARGET_ARM ? 8 : 4); |
5393 | pic_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, pic_rtx), | |
5394 | UNSPEC_GOTSYM_OFF); | |
9403b7f7 RS |
5395 | pic_rtx = gen_rtx_CONST (Pmode, pic_rtx); |
5396 | ||
87d05b44 | 5397 | if (TARGET_32BIT) |
9403b7f7 | 5398 | { |
87d05b44 RE |
5399 | emit_insn (gen_pic_load_addr_32bit (pic_reg, pic_rtx)); |
5400 | if (TARGET_ARM) | |
5401 | emit_insn (gen_pic_add_dot_plus_eight (pic_reg, pic_reg, labelno)); | |
9403b7f7 | 5402 | else |
87d05b44 | 5403 | emit_insn (gen_pic_add_dot_plus_four (pic_reg, pic_reg, labelno)); |
9403b7f7 RS |
5404 | } |
5405 | else /* TARGET_THUMB1 */ | |
876f13b0 | 5406 | { |
9403b7f7 RS |
5407 | if (arm_pic_register != INVALID_REGNUM |
5408 | && REGNO (pic_reg) > LAST_LO_REGNUM) | |
5409 | { | |
5410 | /* We will have pushed the pic register, so we should always be | |
5411 | able to find a work register. */ | |
5412 | pic_tmp = gen_rtx_REG (SImode, | |
5413 | thumb_find_work_register (saved_regs)); | |
5414 | emit_insn (gen_pic_load_addr_thumb1 (pic_tmp, pic_rtx)); | |
5415 | emit_insn (gen_movsi (pic_offset_table_rtx, pic_tmp)); | |
5416 | } | |
5417 | else | |
5418 | emit_insn (gen_pic_load_addr_thumb1 (pic_reg, pic_rtx)); | |
5419 | emit_insn (gen_pic_add_dot_plus_four (pic_reg, pic_reg, labelno)); | |
876f13b0 | 5420 | } |
4bec9f7d | 5421 | } |
32de079a | 5422 | |
32de079a RE |
5423 | /* Need to emit this whether or not we obey regdecls, |
5424 | since setjmp/longjmp can cause life info to screw up. */ | |
c41c1387 | 5425 | emit_use (pic_reg); |
32de079a RE |
5426 | } |
5427 | ||
85c9bcd4 WG |
5428 | /* Generate code to load the address of a static var when flag_pic is set. */ |
5429 | static rtx | |
5430 | arm_pic_static_addr (rtx orig, rtx reg) | |
5431 | { | |
5432 | rtx l1, labelno, offset_rtx, insn; | |
5433 | ||
5434 | gcc_assert (flag_pic); | |
5435 | ||
5436 | /* We use an UNSPEC rather than a LABEL_REF because this label | |
5437 | never appears in the code stream. */ | |
5438 | labelno = GEN_INT (pic_labelno++); | |
5439 | l1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, labelno), UNSPEC_PIC_LABEL); | |
5440 | l1 = gen_rtx_CONST (VOIDmode, l1); | |
5441 | ||
5442 | /* On the ARM the PC register contains 'dot + 8' at the time of the | |
5443 | addition, on the Thumb it is 'dot + 4'. */ | |
5444 | offset_rtx = plus_constant (l1, TARGET_ARM ? 8 : 4); | |
5445 | offset_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, orig, offset_rtx), | |
5446 | UNSPEC_SYMBOL_OFFSET); | |
5447 | offset_rtx = gen_rtx_CONST (Pmode, offset_rtx); | |
5448 | ||
5449 | if (TARGET_32BIT) | |
5450 | { | |
5451 | emit_insn (gen_pic_load_addr_32bit (reg, offset_rtx)); | |
5452 | if (TARGET_ARM) | |
5453 | insn = emit_insn (gen_pic_add_dot_plus_eight (reg, reg, labelno)); | |
5454 | else | |
5455 | insn = emit_insn (gen_pic_add_dot_plus_four (reg, reg, labelno)); | |
5456 | } | |
5457 | else /* TARGET_THUMB1 */ | |
5458 | { | |
5459 | emit_insn (gen_pic_load_addr_thumb1 (reg, offset_rtx)); | |
5460 | insn = emit_insn (gen_pic_add_dot_plus_four (reg, reg, labelno)); | |
5461 | } | |
5462 | ||
5463 | return insn; | |
5464 | } | |
876f13b0 | 5465 | |
6b990f6b RE |
5466 | /* Return nonzero if X is valid as an ARM state addressing register. */ |
5467 | static int | |
e32bac5b | 5468 | arm_address_register_rtx_p (rtx x, int strict_p) |
6b990f6b RE |
5469 | { |
5470 | int regno; | |
5471 | ||
5472 | if (GET_CODE (x) != REG) | |
5473 | return 0; | |
5474 | ||
5475 | regno = REGNO (x); | |
5476 | ||
5477 | if (strict_p) | |
5478 | return ARM_REGNO_OK_FOR_BASE_P (regno); | |
5479 | ||
5480 | return (regno <= LAST_ARM_REGNUM | |
5481 | || regno >= FIRST_PSEUDO_REGISTER | |
5482 | || regno == FRAME_POINTER_REGNUM | |
5483 | || regno == ARG_POINTER_REGNUM); | |
5484 | } | |
5485 | ||
d3585b76 DJ |
5486 | /* Return TRUE if this rtx is the difference of a symbol and a label, |
5487 | and will reduce to a PC-relative relocation in the object file. | |
5488 | Expressions like this can be left alone when generating PIC, rather | |
5489 | than forced through the GOT. */ | |
5490 | static int | |
5491 | pcrel_constant_p (rtx x) | |
5492 | { | |
5493 | if (GET_CODE (x) == MINUS) | |
5494 | return symbol_mentioned_p (XEXP (x, 0)) && label_mentioned_p (XEXP (x, 1)); | |
5495 | ||
5496 | return FALSE; | |
5497 | } | |
5498 | ||
d37c3c62 MK |
5499 | /* Return true if X will surely end up in an index register after next |
5500 | splitting pass. */ | |
5501 | static bool | |
5502 | will_be_in_index_register (const_rtx x) | |
5503 | { | |
5504 | /* arm.md: calculate_pic_address will split this into a register. */ | |
5505 | return GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_PIC_SYM; | |
5506 | } | |
5507 | ||
6b990f6b RE |
5508 | /* Return nonzero if X is a valid ARM state address operand. */ |
5509 | int | |
c6c3dba9 PB |
5510 | arm_legitimate_address_outer_p (enum machine_mode mode, rtx x, RTX_CODE outer, |
5511 | int strict_p) | |
6b990f6b | 5512 | { |
fdd695fd PB |
5513 | bool use_ldrd; |
5514 | enum rtx_code code = GET_CODE (x); | |
f676971a | 5515 | |
6b990f6b RE |
5516 | if (arm_address_register_rtx_p (x, strict_p)) |
5517 | return 1; | |
5518 | ||
fdd695fd PB |
5519 | use_ldrd = (TARGET_LDRD |
5520 | && (mode == DImode | |
5521 | || (mode == DFmode && (TARGET_SOFT_FLOAT || TARGET_VFP)))); | |
5522 | ||
5523 | if (code == POST_INC || code == PRE_DEC | |
5524 | || ((code == PRE_INC || code == POST_DEC) | |
5525 | && (use_ldrd || GET_MODE_SIZE (mode) <= 4))) | |
6b990f6b RE |
5526 | return arm_address_register_rtx_p (XEXP (x, 0), strict_p); |
5527 | ||
fdd695fd | 5528 | else if ((code == POST_MODIFY || code == PRE_MODIFY) |
6b990f6b RE |
5529 | && arm_address_register_rtx_p (XEXP (x, 0), strict_p) |
5530 | && GET_CODE (XEXP (x, 1)) == PLUS | |
386d3a16 | 5531 | && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0))) |
fdd695fd PB |
5532 | { |
5533 | rtx addend = XEXP (XEXP (x, 1), 1); | |
5534 | ||
112cdef5 | 5535 | /* Don't allow ldrd post increment by register because it's hard |
fdd695fd PB |
5536 | to fixup invalid register choices. */ |
5537 | if (use_ldrd | |
5538 | && GET_CODE (x) == POST_MODIFY | |
5539 | && GET_CODE (addend) == REG) | |
5540 | return 0; | |
5541 | ||
5542 | return ((use_ldrd || GET_MODE_SIZE (mode) <= 4) | |
5543 | && arm_legitimate_index_p (mode, addend, outer, strict_p)); | |
5544 | } | |
6b990f6b RE |
5545 | |
5546 | /* After reload constants split into minipools will have addresses | |
5547 | from a LABEL_REF. */ | |
0bfb39ef | 5548 | else if (reload_completed |
fdd695fd PB |
5549 | && (code == LABEL_REF |
5550 | || (code == CONST | |
6b990f6b RE |
5551 | && GET_CODE (XEXP (x, 0)) == PLUS |
5552 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF | |
5553 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT))) | |
5554 | return 1; | |
5555 | ||
88f77cba | 5556 | else if (mode == TImode || (TARGET_NEON && VALID_NEON_STRUCT_MODE (mode))) |
6b990f6b RE |
5557 | return 0; |
5558 | ||
fdd695fd | 5559 | else if (code == PLUS) |
6b990f6b RE |
5560 | { |
5561 | rtx xop0 = XEXP (x, 0); | |
5562 | rtx xop1 = XEXP (x, 1); | |
5563 | ||
5564 | return ((arm_address_register_rtx_p (xop0, strict_p) | |
d37c3c62 MK |
5565 | && ((GET_CODE(xop1) == CONST_INT |
5566 | && arm_legitimate_index_p (mode, xop1, outer, strict_p)) | |
5567 | || (!strict_p && will_be_in_index_register (xop1)))) | |
6b990f6b | 5568 | || (arm_address_register_rtx_p (xop1, strict_p) |
1e1ab407 | 5569 | && arm_legitimate_index_p (mode, xop0, outer, strict_p))); |
6b990f6b RE |
5570 | } |
5571 | ||
5572 | #if 0 | |
5573 | /* Reload currently can't handle MINUS, so disable this for now */ | |
5574 | else if (GET_CODE (x) == MINUS) | |
5575 | { | |
5576 | rtx xop0 = XEXP (x, 0); | |
5577 | rtx xop1 = XEXP (x, 1); | |
5578 | ||
5579 | return (arm_address_register_rtx_p (xop0, strict_p) | |
1e1ab407 | 5580 | && arm_legitimate_index_p (mode, xop1, outer, strict_p)); |
6b990f6b RE |
5581 | } |
5582 | #endif | |
5583 | ||
5584 | else if (GET_MODE_CLASS (mode) != MODE_FLOAT | |
fdd695fd | 5585 | && code == SYMBOL_REF |
6b990f6b RE |
5586 | && CONSTANT_POOL_ADDRESS_P (x) |
5587 | && ! (flag_pic | |
d3585b76 DJ |
5588 | && symbol_mentioned_p (get_pool_constant (x)) |
5589 | && ! pcrel_constant_p (get_pool_constant (x)))) | |
6b990f6b RE |
5590 | return 1; |
5591 | ||
6b990f6b RE |
5592 | return 0; |
5593 | } | |
5594 | ||
5b3e6663 | 5595 | /* Return nonzero if X is a valid Thumb-2 address operand. */ |
c6c3dba9 | 5596 | static int |
5b3e6663 PB |
5597 | thumb2_legitimate_address_p (enum machine_mode mode, rtx x, int strict_p) |
5598 | { | |
5599 | bool use_ldrd; | |
5600 | enum rtx_code code = GET_CODE (x); | |
5601 | ||
5602 | if (arm_address_register_rtx_p (x, strict_p)) | |
5603 | return 1; | |
5604 | ||
5605 | use_ldrd = (TARGET_LDRD | |
5606 | && (mode == DImode | |
5607 | || (mode == DFmode && (TARGET_SOFT_FLOAT || TARGET_VFP)))); | |
5608 | ||
5609 | if (code == POST_INC || code == PRE_DEC | |
5610 | || ((code == PRE_INC || code == POST_DEC) | |
5611 | && (use_ldrd || GET_MODE_SIZE (mode) <= 4))) | |
5612 | return arm_address_register_rtx_p (XEXP (x, 0), strict_p); | |
5613 | ||
5614 | else if ((code == POST_MODIFY || code == PRE_MODIFY) | |
5615 | && arm_address_register_rtx_p (XEXP (x, 0), strict_p) | |
5616 | && GET_CODE (XEXP (x, 1)) == PLUS | |
5617 | && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0))) | |
5618 | { | |
5619 | /* Thumb-2 only has autoincrement by constant. */ | |
5620 | rtx addend = XEXP (XEXP (x, 1), 1); | |
5621 | HOST_WIDE_INT offset; | |
5622 | ||
5623 | if (GET_CODE (addend) != CONST_INT) | |
5624 | return 0; | |
5625 | ||
5626 | offset = INTVAL(addend); | |
5627 | if (GET_MODE_SIZE (mode) <= 4) | |
5628 | return (offset > -256 && offset < 256); | |
5629 | ||
5630 | return (use_ldrd && offset > -1024 && offset < 1024 | |
5631 | && (offset & 3) == 0); | |
5632 | } | |
5633 | ||
5634 | /* After reload constants split into minipools will have addresses | |
5635 | from a LABEL_REF. */ | |
5636 | else if (reload_completed | |
5637 | && (code == LABEL_REF | |
5638 | || (code == CONST | |
5639 | && GET_CODE (XEXP (x, 0)) == PLUS | |
5640 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF | |
5641 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT))) | |
5642 | return 1; | |
5643 | ||
88f77cba | 5644 | else if (mode == TImode || (TARGET_NEON && VALID_NEON_STRUCT_MODE (mode))) |
5b3e6663 PB |
5645 | return 0; |
5646 | ||
5647 | else if (code == PLUS) | |
5648 | { | |
5649 | rtx xop0 = XEXP (x, 0); | |
5650 | rtx xop1 = XEXP (x, 1); | |
5651 | ||
5652 | return ((arm_address_register_rtx_p (xop0, strict_p) | |
d37c3c62 MK |
5653 | && (thumb2_legitimate_index_p (mode, xop1, strict_p) |
5654 | || (!strict_p && will_be_in_index_register (xop1)))) | |
5b3e6663 PB |
5655 | || (arm_address_register_rtx_p (xop1, strict_p) |
5656 | && thumb2_legitimate_index_p (mode, xop0, strict_p))); | |
5657 | } | |
5658 | ||
5659 | else if (GET_MODE_CLASS (mode) != MODE_FLOAT | |
5660 | && code == SYMBOL_REF | |
5661 | && CONSTANT_POOL_ADDRESS_P (x) | |
5662 | && ! (flag_pic | |
5663 | && symbol_mentioned_p (get_pool_constant (x)) | |
5664 | && ! pcrel_constant_p (get_pool_constant (x)))) | |
5665 | return 1; | |
5666 | ||
5667 | return 0; | |
5668 | } | |
5669 | ||
6b990f6b RE |
5670 | /* Return nonzero if INDEX is valid for an address index operand in |
5671 | ARM state. */ | |
5672 | static int | |
1e1ab407 RE |
5673 | arm_legitimate_index_p (enum machine_mode mode, rtx index, RTX_CODE outer, |
5674 | int strict_p) | |
6b990f6b RE |
5675 | { |
5676 | HOST_WIDE_INT range; | |
5677 | enum rtx_code code = GET_CODE (index); | |
5678 | ||
778ebdd9 PB |
5679 | /* Standard coprocessor addressing modes. */ |
5680 | if (TARGET_HARD_FLOAT | |
f3fb6590 CLT |
5681 | && (TARGET_VFP || TARGET_FPA || TARGET_MAVERICK) |
5682 | && (mode == SFmode || mode == DFmode | |
778ebdd9 | 5683 | || (TARGET_MAVERICK && mode == DImode))) |
6b990f6b RE |
5684 | return (code == CONST_INT && INTVAL (index) < 1024 |
5685 | && INTVAL (index) > -1024 | |
5686 | && (INTVAL (index) & 3) == 0); | |
5687 | ||
49460951 NF |
5688 | /* For quad modes, we restrict the constant offset to be slightly less |
5689 | than what the instruction format permits. We do this because for | |
5690 | quad mode moves, we will actually decompose them into two separate | |
5691 | double-mode reads or writes. INDEX must therefore be a valid | |
5692 | (double-mode) offset and so should INDEX+8. */ | |
5693 | if (TARGET_NEON && VALID_NEON_QREG_MODE (mode)) | |
88f77cba JB |
5694 | return (code == CONST_INT |
5695 | && INTVAL (index) < 1016 | |
5696 | && INTVAL (index) > -1024 | |
5697 | && (INTVAL (index) & 3) == 0); | |
5698 | ||
49460951 NF |
5699 | /* We have no such constraint on double mode offsets, so we permit the |
5700 | full range of the instruction format. */ | |
5701 | if (TARGET_NEON && VALID_NEON_DREG_MODE (mode)) | |
5702 | return (code == CONST_INT | |
5703 | && INTVAL (index) < 1024 | |
5704 | && INTVAL (index) > -1024 | |
5705 | && (INTVAL (index) & 3) == 0); | |
5706 | ||
5a9335ef NC |
5707 | if (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode)) |
5708 | return (code == CONST_INT | |
3657dc3e PB |
5709 | && INTVAL (index) < 1024 |
5710 | && INTVAL (index) > -1024 | |
5711 | && (INTVAL (index) & 3) == 0); | |
5a9335ef | 5712 | |
fdd695fd PB |
5713 | if (arm_address_register_rtx_p (index, strict_p) |
5714 | && (GET_MODE_SIZE (mode) <= 4)) | |
5715 | return 1; | |
5716 | ||
5717 | if (mode == DImode || mode == DFmode) | |
5718 | { | |
5719 | if (code == CONST_INT) | |
5720 | { | |
5721 | HOST_WIDE_INT val = INTVAL (index); | |
5722 | ||
5723 | if (TARGET_LDRD) | |
5724 | return val > -256 && val < 256; | |
5725 | else | |
f372c932 | 5726 | return val > -4096 && val < 4092; |
fdd695fd PB |
5727 | } |
5728 | ||
5729 | return TARGET_LDRD && arm_address_register_rtx_p (index, strict_p); | |
5730 | } | |
5731 | ||
6b990f6b | 5732 | if (GET_MODE_SIZE (mode) <= 4 |
1e1ab407 RE |
5733 | && ! (arm_arch4 |
5734 | && (mode == HImode | |
0fd8c3ad | 5735 | || mode == HFmode |
1e1ab407 | 5736 | || (mode == QImode && outer == SIGN_EXTEND)))) |
6b990f6b | 5737 | { |
1e1ab407 RE |
5738 | if (code == MULT) |
5739 | { | |
5740 | rtx xiop0 = XEXP (index, 0); | |
5741 | rtx xiop1 = XEXP (index, 1); | |
5742 | ||
5743 | return ((arm_address_register_rtx_p (xiop0, strict_p) | |
5744 | && power_of_two_operand (xiop1, SImode)) | |
5745 | || (arm_address_register_rtx_p (xiop1, strict_p) | |
5746 | && power_of_two_operand (xiop0, SImode))); | |
5747 | } | |
5748 | else if (code == LSHIFTRT || code == ASHIFTRT | |
5749 | || code == ASHIFT || code == ROTATERT) | |
5750 | { | |
5751 | rtx op = XEXP (index, 1); | |
6b990f6b | 5752 | |
1e1ab407 RE |
5753 | return (arm_address_register_rtx_p (XEXP (index, 0), strict_p) |
5754 | && GET_CODE (op) == CONST_INT | |
5755 | && INTVAL (op) > 0 | |
5756 | && INTVAL (op) <= 31); | |
5757 | } | |
6b990f6b RE |
5758 | } |
5759 | ||
1e1ab407 RE |
5760 | /* For ARM v4 we may be doing a sign-extend operation during the |
5761 | load. */ | |
e1471c91 | 5762 | if (arm_arch4) |
1e1ab407 | 5763 | { |
0fd8c3ad SL |
5764 | if (mode == HImode |
5765 | || mode == HFmode | |
5766 | || (outer == SIGN_EXTEND && mode == QImode)) | |
1e1ab407 RE |
5767 | range = 256; |
5768 | else | |
5769 | range = 4096; | |
5770 | } | |
e1471c91 | 5771 | else |
0fd8c3ad | 5772 | range = (mode == HImode || mode == HFmode) ? 4095 : 4096; |
6b990f6b RE |
5773 | |
5774 | return (code == CONST_INT | |
5775 | && INTVAL (index) < range | |
5776 | && INTVAL (index) > -range); | |
76a318e9 RE |
5777 | } |
5778 | ||
5b3e6663 PB |
5779 | /* Return true if OP is a valid index scaling factor for Thumb-2 address |
5780 | index operand. i.e. 1, 2, 4 or 8. */ | |
5781 | static bool | |
5782 | thumb2_index_mul_operand (rtx op) | |
5783 | { | |
5784 | HOST_WIDE_INT val; | |
5785 | ||
5786 | if (GET_CODE(op) != CONST_INT) | |
5787 | return false; | |
5788 | ||
5789 | val = INTVAL(op); | |
5790 | return (val == 1 || val == 2 || val == 4 || val == 8); | |
5791 | } | |
5792 | ||
5793 | /* Return nonzero if INDEX is a valid Thumb-2 address index operand. */ | |
5794 | static int | |
5795 | thumb2_legitimate_index_p (enum machine_mode mode, rtx index, int strict_p) | |
5796 | { | |
5797 | enum rtx_code code = GET_CODE (index); | |
5798 | ||
5799 | /* ??? Combine arm and thumb2 coprocessor addressing modes. */ | |
5800 | /* Standard coprocessor addressing modes. */ | |
5801 | if (TARGET_HARD_FLOAT | |
f3fb6590 CLT |
5802 | && (TARGET_VFP || TARGET_FPA || TARGET_MAVERICK) |
5803 | && (mode == SFmode || mode == DFmode | |
5b3e6663 PB |
5804 | || (TARGET_MAVERICK && mode == DImode))) |
5805 | return (code == CONST_INT && INTVAL (index) < 1024 | |
bff99262 CLT |
5806 | /* Thumb-2 allows only > -256 index range for it's core register |
5807 | load/stores. Since we allow SF/DF in core registers, we have | |
5808 | to use the intersection between -256~4096 (core) and -1024~1024 | |
5809 | (coprocessor). */ | |
5810 | && INTVAL (index) > -256 | |
5b3e6663 PB |
5811 | && (INTVAL (index) & 3) == 0); |
5812 | ||
5813 | if (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode)) | |
fe2d934b PB |
5814 | { |
5815 | /* For DImode assume values will usually live in core regs | |
5816 | and only allow LDRD addressing modes. */ | |
5817 | if (!TARGET_LDRD || mode != DImode) | |
5818 | return (code == CONST_INT | |
5819 | && INTVAL (index) < 1024 | |
5820 | && INTVAL (index) > -1024 | |
5821 | && (INTVAL (index) & 3) == 0); | |
5822 | } | |
5b3e6663 | 5823 | |
49460951 NF |
5824 | /* For quad modes, we restrict the constant offset to be slightly less |
5825 | than what the instruction format permits. We do this because for | |
5826 | quad mode moves, we will actually decompose them into two separate | |
5827 | double-mode reads or writes. INDEX must therefore be a valid | |
5828 | (double-mode) offset and so should INDEX+8. */ | |
5829 | if (TARGET_NEON && VALID_NEON_QREG_MODE (mode)) | |
88f77cba JB |
5830 | return (code == CONST_INT |
5831 | && INTVAL (index) < 1016 | |
5832 | && INTVAL (index) > -1024 | |
5833 | && (INTVAL (index) & 3) == 0); | |
5834 | ||
49460951 NF |
5835 | /* We have no such constraint on double mode offsets, so we permit the |
5836 | full range of the instruction format. */ | |
5837 | if (TARGET_NEON && VALID_NEON_DREG_MODE (mode)) | |
5838 | return (code == CONST_INT | |
5839 | && INTVAL (index) < 1024 | |
5840 | && INTVAL (index) > -1024 | |
5841 | && (INTVAL (index) & 3) == 0); | |
5842 | ||
5b3e6663 PB |
5843 | if (arm_address_register_rtx_p (index, strict_p) |
5844 | && (GET_MODE_SIZE (mode) <= 4)) | |
5845 | return 1; | |
5846 | ||
5847 | if (mode == DImode || mode == DFmode) | |
5848 | { | |
e07e020b RR |
5849 | if (code == CONST_INT) |
5850 | { | |
5851 | HOST_WIDE_INT val = INTVAL (index); | |
5852 | /* ??? Can we assume ldrd for thumb2? */ | |
5853 | /* Thumb-2 ldrd only has reg+const addressing modes. */ | |
5854 | /* ldrd supports offsets of +-1020. | |
5855 | However the ldr fallback does not. */ | |
5856 | return val > -256 && val < 256 && (val & 3) == 0; | |
5857 | } | |
5858 | else | |
5b3e6663 | 5859 | return 0; |
5b3e6663 PB |
5860 | } |
5861 | ||
5862 | if (code == MULT) | |
5863 | { | |
5864 | rtx xiop0 = XEXP (index, 0); | |
5865 | rtx xiop1 = XEXP (index, 1); | |
5866 | ||
5867 | return ((arm_address_register_rtx_p (xiop0, strict_p) | |
5868 | && thumb2_index_mul_operand (xiop1)) | |
5869 | || (arm_address_register_rtx_p (xiop1, strict_p) | |
5870 | && thumb2_index_mul_operand (xiop0))); | |
5871 | } | |
5872 | else if (code == ASHIFT) | |
5873 | { | |
5874 | rtx op = XEXP (index, 1); | |
5875 | ||
5876 | return (arm_address_register_rtx_p (XEXP (index, 0), strict_p) | |
5877 | && GET_CODE (op) == CONST_INT | |
5878 | && INTVAL (op) > 0 | |
5879 | && INTVAL (op) <= 3); | |
5880 | } | |
5881 | ||
5882 | return (code == CONST_INT | |
5883 | && INTVAL (index) < 4096 | |
5884 | && INTVAL (index) > -256); | |
5885 | } | |
5886 | ||
5887 | /* Return nonzero if X is valid as a 16-bit Thumb state base register. */ | |
76a318e9 | 5888 | static int |
5b3e6663 | 5889 | thumb1_base_register_rtx_p (rtx x, enum machine_mode mode, int strict_p) |
76a318e9 RE |
5890 | { |
5891 | int regno; | |
5892 | ||
5893 | if (GET_CODE (x) != REG) | |
5894 | return 0; | |
5895 | ||
5896 | regno = REGNO (x); | |
5897 | ||
5898 | if (strict_p) | |
5b3e6663 | 5899 | return THUMB1_REGNO_MODE_OK_FOR_BASE_P (regno, mode); |
76a318e9 RE |
5900 | |
5901 | return (regno <= LAST_LO_REGNUM | |
07e58265 | 5902 | || regno > LAST_VIRTUAL_REGISTER |
76a318e9 RE |
5903 | || regno == FRAME_POINTER_REGNUM |
5904 | || (GET_MODE_SIZE (mode) >= 4 | |
5905 | && (regno == STACK_POINTER_REGNUM | |
edf7cee8 | 5906 | || regno >= FIRST_PSEUDO_REGISTER |
76a318e9 RE |
5907 | || x == hard_frame_pointer_rtx |
5908 | || x == arg_pointer_rtx))); | |
5909 | } | |
5910 | ||
5911 | /* Return nonzero if x is a legitimate index register. This is the case | |
5912 | for any base register that can access a QImode object. */ | |
5913 | inline static int | |
5b3e6663 | 5914 | thumb1_index_register_rtx_p (rtx x, int strict_p) |
76a318e9 | 5915 | { |
5b3e6663 | 5916 | return thumb1_base_register_rtx_p (x, QImode, strict_p); |
76a318e9 RE |
5917 | } |
5918 | ||
5b3e6663 | 5919 | /* Return nonzero if x is a legitimate 16-bit Thumb-state address. |
f676971a | 5920 | |
76a318e9 RE |
5921 | The AP may be eliminated to either the SP or the FP, so we use the |
5922 | least common denominator, e.g. SImode, and offsets from 0 to 64. | |
5923 | ||
5924 | ??? Verify whether the above is the right approach. | |
5925 | ||
5926 | ??? Also, the FP may be eliminated to the SP, so perhaps that | |
5927 | needs special handling also. | |
5928 | ||
5929 | ??? Look at how the mips16 port solves this problem. It probably uses | |
5930 | better ways to solve some of these problems. | |
5931 | ||
5932 | Although it is not incorrect, we don't accept QImode and HImode | |
5933 | addresses based on the frame pointer or arg pointer until the | |
5934 | reload pass starts. This is so that eliminating such addresses | |
5935 | into stack based ones won't produce impossible code. */ | |
c6c3dba9 | 5936 | static int |
5b3e6663 | 5937 | thumb1_legitimate_address_p (enum machine_mode mode, rtx x, int strict_p) |
76a318e9 RE |
5938 | { |
5939 | /* ??? Not clear if this is right. Experiment. */ | |
5940 | if (GET_MODE_SIZE (mode) < 4 | |
5941 | && !(reload_in_progress || reload_completed) | |
5942 | && (reg_mentioned_p (frame_pointer_rtx, x) | |
5943 | || reg_mentioned_p (arg_pointer_rtx, x) | |
5944 | || reg_mentioned_p (virtual_incoming_args_rtx, x) | |
5945 | || reg_mentioned_p (virtual_outgoing_args_rtx, x) | |
5946 | || reg_mentioned_p (virtual_stack_dynamic_rtx, x) | |
5947 | || reg_mentioned_p (virtual_stack_vars_rtx, x))) | |
5948 | return 0; | |
5949 | ||
5950 | /* Accept any base register. SP only in SImode or larger. */ | |
5b3e6663 | 5951 | else if (thumb1_base_register_rtx_p (x, mode, strict_p)) |
76a318e9 RE |
5952 | return 1; |
5953 | ||
18dbd950 | 5954 | /* This is PC relative data before arm_reorg runs. */ |
76a318e9 RE |
5955 | else if (GET_MODE_SIZE (mode) >= 4 && CONSTANT_P (x) |
5956 | && GET_CODE (x) == SYMBOL_REF | |
020a4035 | 5957 | && CONSTANT_POOL_ADDRESS_P (x) && !flag_pic) |
76a318e9 RE |
5958 | return 1; |
5959 | ||
18dbd950 | 5960 | /* This is PC relative data after arm_reorg runs. */ |
0fd8c3ad SL |
5961 | else if ((GET_MODE_SIZE (mode) >= 4 || mode == HFmode) |
5962 | && reload_completed | |
76a318e9 RE |
5963 | && (GET_CODE (x) == LABEL_REF |
5964 | || (GET_CODE (x) == CONST | |
5965 | && GET_CODE (XEXP (x, 0)) == PLUS | |
5966 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF | |
5967 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT))) | |
5968 | return 1; | |
5969 | ||
5970 | /* Post-inc indexing only supported for SImode and larger. */ | |
5971 | else if (GET_CODE (x) == POST_INC && GET_MODE_SIZE (mode) >= 4 | |
5b3e6663 | 5972 | && thumb1_index_register_rtx_p (XEXP (x, 0), strict_p)) |
76a318e9 RE |
5973 | return 1; |
5974 | ||
5975 | else if (GET_CODE (x) == PLUS) | |
5976 | { | |
5977 | /* REG+REG address can be any two index registers. */ | |
5978 | /* We disallow FRAME+REG addressing since we know that FRAME | |
5979 | will be replaced with STACK, and SP relative addressing only | |
5980 | permits SP+OFFSET. */ | |
5981 | if (GET_MODE_SIZE (mode) <= 4 | |
5982 | && XEXP (x, 0) != frame_pointer_rtx | |
5983 | && XEXP (x, 1) != frame_pointer_rtx | |
5b3e6663 | 5984 | && thumb1_index_register_rtx_p (XEXP (x, 0), strict_p) |
d37c3c62 MK |
5985 | && (thumb1_index_register_rtx_p (XEXP (x, 1), strict_p) |
5986 | || (!strict_p && will_be_in_index_register (XEXP (x, 1))))) | |
76a318e9 RE |
5987 | return 1; |
5988 | ||
5989 | /* REG+const has 5-7 bit offset for non-SP registers. */ | |
5b3e6663 | 5990 | else if ((thumb1_index_register_rtx_p (XEXP (x, 0), strict_p) |
76a318e9 RE |
5991 | || XEXP (x, 0) == arg_pointer_rtx) |
5992 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
5993 | && thumb_legitimate_offset_p (mode, INTVAL (XEXP (x, 1)))) | |
5994 | return 1; | |
5995 | ||
a50aa827 | 5996 | /* REG+const has 10-bit offset for SP, but only SImode and |
76a318e9 RE |
5997 | larger is supported. */ |
5998 | /* ??? Should probably check for DI/DFmode overflow here | |
5999 | just like GO_IF_LEGITIMATE_OFFSET does. */ | |
6000 | else if (GET_CODE (XEXP (x, 0)) == REG | |
6001 | && REGNO (XEXP (x, 0)) == STACK_POINTER_REGNUM | |
6002 | && GET_MODE_SIZE (mode) >= 4 | |
6003 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
6004 | && INTVAL (XEXP (x, 1)) >= 0 | |
6005 | && INTVAL (XEXP (x, 1)) + GET_MODE_SIZE (mode) <= 1024 | |
6006 | && (INTVAL (XEXP (x, 1)) & 3) == 0) | |
6007 | return 1; | |
6008 | ||
6009 | else if (GET_CODE (XEXP (x, 0)) == REG | |
c5289e45 RE |
6010 | && (REGNO (XEXP (x, 0)) == FRAME_POINTER_REGNUM |
6011 | || REGNO (XEXP (x, 0)) == ARG_POINTER_REGNUM | |
6012 | || (REGNO (XEXP (x, 0)) >= FIRST_VIRTUAL_REGISTER | |
32990d5b JJ |
6013 | && REGNO (XEXP (x, 0)) |
6014 | <= LAST_VIRTUAL_POINTER_REGISTER)) | |
76a318e9 RE |
6015 | && GET_MODE_SIZE (mode) >= 4 |
6016 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
6017 | && (INTVAL (XEXP (x, 1)) & 3) == 0) | |
6018 | return 1; | |
6019 | } | |
6020 | ||
6021 | else if (GET_MODE_CLASS (mode) != MODE_FLOAT | |
f954388e | 6022 | && GET_MODE_SIZE (mode) == 4 |
76a318e9 RE |
6023 | && GET_CODE (x) == SYMBOL_REF |
6024 | && CONSTANT_POOL_ADDRESS_P (x) | |
d3585b76 DJ |
6025 | && ! (flag_pic |
6026 | && symbol_mentioned_p (get_pool_constant (x)) | |
6027 | && ! pcrel_constant_p (get_pool_constant (x)))) | |
76a318e9 RE |
6028 | return 1; |
6029 | ||
6030 | return 0; | |
6031 | } | |
6032 | ||
6033 | /* Return nonzero if VAL can be used as an offset in a Thumb-state address | |
6034 | instruction of mode MODE. */ | |
6035 | int | |
e32bac5b | 6036 | thumb_legitimate_offset_p (enum machine_mode mode, HOST_WIDE_INT val) |
76a318e9 RE |
6037 | { |
6038 | switch (GET_MODE_SIZE (mode)) | |
6039 | { | |
6040 | case 1: | |
6041 | return val >= 0 && val < 32; | |
6042 | ||
6043 | case 2: | |
6044 | return val >= 0 && val < 64 && (val & 1) == 0; | |
6045 | ||
6046 | default: | |
6047 | return (val >= 0 | |
6048 | && (val + GET_MODE_SIZE (mode)) <= 128 | |
6049 | && (val & 3) == 0); | |
6050 | } | |
6051 | } | |
6052 | ||
c6c3dba9 PB |
6053 | bool |
6054 | arm_legitimate_address_p (enum machine_mode mode, rtx x, bool strict_p) | |
6055 | { | |
6056 | if (TARGET_ARM) | |
6057 | return arm_legitimate_address_outer_p (mode, x, SET, strict_p); | |
6058 | else if (TARGET_THUMB2) | |
6059 | return thumb2_legitimate_address_p (mode, x, strict_p); | |
6060 | else /* if (TARGET_THUMB1) */ | |
6061 | return thumb1_legitimate_address_p (mode, x, strict_p); | |
6062 | } | |
6063 | ||
d3585b76 DJ |
6064 | /* Build the SYMBOL_REF for __tls_get_addr. */ |
6065 | ||
6066 | static GTY(()) rtx tls_get_addr_libfunc; | |
6067 | ||
6068 | static rtx | |
6069 | get_tls_get_addr (void) | |
6070 | { | |
6071 | if (!tls_get_addr_libfunc) | |
6072 | tls_get_addr_libfunc = init_one_libfunc ("__tls_get_addr"); | |
6073 | return tls_get_addr_libfunc; | |
6074 | } | |
6075 | ||
6076 | static rtx | |
6077 | arm_load_tp (rtx target) | |
6078 | { | |
6079 | if (!target) | |
6080 | target = gen_reg_rtx (SImode); | |
6081 | ||
6082 | if (TARGET_HARD_TP) | |
6083 | { | |
6084 | /* Can return in any reg. */ | |
6085 | emit_insn (gen_load_tp_hard (target)); | |
6086 | } | |
6087 | else | |
6088 | { | |
6089 | /* Always returned in r0. Immediately copy the result into a pseudo, | |
6090 | otherwise other uses of r0 (e.g. setting up function arguments) may | |
6091 | clobber the value. */ | |
6092 | ||
6093 | rtx tmp; | |
6094 | ||
6095 | emit_insn (gen_load_tp_soft ()); | |
6096 | ||
6097 | tmp = gen_rtx_REG (SImode, 0); | |
6098 | emit_move_insn (target, tmp); | |
6099 | } | |
6100 | return target; | |
6101 | } | |
6102 | ||
6103 | static rtx | |
6104 | load_tls_operand (rtx x, rtx reg) | |
6105 | { | |
6106 | rtx tmp; | |
6107 | ||
6108 | if (reg == NULL_RTX) | |
6109 | reg = gen_reg_rtx (SImode); | |
6110 | ||
6111 | tmp = gen_rtx_CONST (SImode, x); | |
6112 | ||
6113 | emit_move_insn (reg, tmp); | |
6114 | ||
6115 | return reg; | |
6116 | } | |
6117 | ||
6118 | static rtx | |
6119 | arm_call_tls_get_addr (rtx x, rtx reg, rtx *valuep, int reloc) | |
6120 | { | |
f16fe45f | 6121 | rtx insns, label, labelno, sum; |
d3585b76 DJ |
6122 | |
6123 | start_sequence (); | |
6124 | ||
f16fe45f DJ |
6125 | labelno = GEN_INT (pic_labelno++); |
6126 | label = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, labelno), UNSPEC_PIC_LABEL); | |
6127 | label = gen_rtx_CONST (VOIDmode, label); | |
6128 | ||
d3585b76 | 6129 | sum = gen_rtx_UNSPEC (Pmode, |
f16fe45f | 6130 | gen_rtvec (4, x, GEN_INT (reloc), label, |
d3585b76 DJ |
6131 | GEN_INT (TARGET_ARM ? 8 : 4)), |
6132 | UNSPEC_TLS); | |
6133 | reg = load_tls_operand (sum, reg); | |
6134 | ||
6135 | if (TARGET_ARM) | |
f16fe45f | 6136 | emit_insn (gen_pic_add_dot_plus_eight (reg, reg, labelno)); |
5b3e6663 | 6137 | else if (TARGET_THUMB2) |
87d05b44 | 6138 | emit_insn (gen_pic_add_dot_plus_four (reg, reg, labelno)); |
5b3e6663 | 6139 | else /* TARGET_THUMB1 */ |
f16fe45f | 6140 | emit_insn (gen_pic_add_dot_plus_four (reg, reg, labelno)); |
d3585b76 DJ |
6141 | |
6142 | *valuep = emit_library_call_value (get_tls_get_addr (), NULL_RTX, LCT_PURE, /* LCT_CONST? */ | |
6143 | Pmode, 1, reg, Pmode); | |
6144 | ||
6145 | insns = get_insns (); | |
6146 | end_sequence (); | |
6147 | ||
6148 | return insns; | |
6149 | } | |
6150 | ||
6151 | rtx | |
6152 | legitimize_tls_address (rtx x, rtx reg) | |
6153 | { | |
f16fe45f | 6154 | rtx dest, tp, label, labelno, sum, insns, ret, eqv, addend; |
d3585b76 DJ |
6155 | unsigned int model = SYMBOL_REF_TLS_MODEL (x); |
6156 | ||
6157 | switch (model) | |
6158 | { | |
6159 | case TLS_MODEL_GLOBAL_DYNAMIC: | |
6160 | insns = arm_call_tls_get_addr (x, reg, &ret, TLS_GD32); | |
6161 | dest = gen_reg_rtx (Pmode); | |
6162 | emit_libcall_block (insns, dest, ret, x); | |
6163 | return dest; | |
6164 | ||
6165 | case TLS_MODEL_LOCAL_DYNAMIC: | |
6166 | insns = arm_call_tls_get_addr (x, reg, &ret, TLS_LDM32); | |
6167 | ||
6168 | /* Attach a unique REG_EQUIV, to allow the RTL optimizers to | |
6169 | share the LDM result with other LD model accesses. */ | |
6170 | eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const1_rtx), | |
6171 | UNSPEC_TLS); | |
6172 | dest = gen_reg_rtx (Pmode); | |
e66e1c68 | 6173 | emit_libcall_block (insns, dest, ret, eqv); |
d3585b76 DJ |
6174 | |
6175 | /* Load the addend. */ | |
6176 | addend = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, x, GEN_INT (TLS_LDO32)), | |
6177 | UNSPEC_TLS); | |
6178 | addend = force_reg (SImode, gen_rtx_CONST (SImode, addend)); | |
6179 | return gen_rtx_PLUS (Pmode, dest, addend); | |
6180 | ||
6181 | case TLS_MODEL_INITIAL_EXEC: | |
f16fe45f DJ |
6182 | labelno = GEN_INT (pic_labelno++); |
6183 | label = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, labelno), UNSPEC_PIC_LABEL); | |
6184 | label = gen_rtx_CONST (VOIDmode, label); | |
d3585b76 | 6185 | sum = gen_rtx_UNSPEC (Pmode, |
f16fe45f | 6186 | gen_rtvec (4, x, GEN_INT (TLS_IE32), label, |
d3585b76 DJ |
6187 | GEN_INT (TARGET_ARM ? 8 : 4)), |
6188 | UNSPEC_TLS); | |
6189 | reg = load_tls_operand (sum, reg); | |
6190 | ||
6191 | if (TARGET_ARM) | |
f16fe45f | 6192 | emit_insn (gen_tls_load_dot_plus_eight (reg, reg, labelno)); |
5b3e6663 | 6193 | else if (TARGET_THUMB2) |
2e5505a4 | 6194 | emit_insn (gen_tls_load_dot_plus_four (reg, NULL, reg, labelno)); |
d3585b76 DJ |
6195 | else |
6196 | { | |
f16fe45f | 6197 | emit_insn (gen_pic_add_dot_plus_four (reg, reg, labelno)); |
d3585b76 DJ |
6198 | emit_move_insn (reg, gen_const_mem (SImode, reg)); |
6199 | } | |
6200 | ||
6201 | tp = arm_load_tp (NULL_RTX); | |
6202 | ||
6203 | return gen_rtx_PLUS (Pmode, tp, reg); | |
6204 | ||
6205 | case TLS_MODEL_LOCAL_EXEC: | |
6206 | tp = arm_load_tp (NULL_RTX); | |
6207 | ||
6208 | reg = gen_rtx_UNSPEC (Pmode, | |
6209 | gen_rtvec (2, x, GEN_INT (TLS_LE32)), | |
6210 | UNSPEC_TLS); | |
6211 | reg = force_reg (SImode, gen_rtx_CONST (SImode, reg)); | |
6212 | ||
6213 | return gen_rtx_PLUS (Pmode, tp, reg); | |
6214 | ||
6215 | default: | |
6216 | abort (); | |
6217 | } | |
6218 | } | |
6219 | ||
ccf4d512 RE |
6220 | /* Try machine-dependent ways of modifying an illegitimate address |
6221 | to be legitimate. If we find one, return the new, valid address. */ | |
ccf4d512 | 6222 | rtx |
e32bac5b | 6223 | arm_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode) |
ccf4d512 | 6224 | { |
506d7b68 PB |
6225 | if (!TARGET_ARM) |
6226 | { | |
6227 | /* TODO: legitimize_address for Thumb2. */ | |
6228 | if (TARGET_THUMB2) | |
6229 | return x; | |
6230 | return thumb_legitimize_address (x, orig_x, mode); | |
6231 | } | |
6232 | ||
d3585b76 DJ |
6233 | if (arm_tls_symbol_p (x)) |
6234 | return legitimize_tls_address (x, NULL_RTX); | |
6235 | ||
ccf4d512 RE |
6236 | if (GET_CODE (x) == PLUS) |
6237 | { | |
6238 | rtx xop0 = XEXP (x, 0); | |
6239 | rtx xop1 = XEXP (x, 1); | |
6240 | ||
6241 | if (CONSTANT_P (xop0) && !symbol_mentioned_p (xop0)) | |
6242 | xop0 = force_reg (SImode, xop0); | |
6243 | ||
6244 | if (CONSTANT_P (xop1) && !symbol_mentioned_p (xop1)) | |
6245 | xop1 = force_reg (SImode, xop1); | |
6246 | ||
6247 | if (ARM_BASE_REGISTER_RTX_P (xop0) | |
6248 | && GET_CODE (xop1) == CONST_INT) | |
6249 | { | |
6250 | HOST_WIDE_INT n, low_n; | |
6251 | rtx base_reg, val; | |
6252 | n = INTVAL (xop1); | |
6253 | ||
9b66ebb1 PB |
6254 | /* VFP addressing modes actually allow greater offsets, but for |
6255 | now we just stick with the lowest common denominator. */ | |
6256 | if (mode == DImode | |
6257 | || ((TARGET_SOFT_FLOAT || TARGET_VFP) && mode == DFmode)) | |
ccf4d512 RE |
6258 | { |
6259 | low_n = n & 0x0f; | |
6260 | n &= ~0x0f; | |
6261 | if (low_n > 4) | |
6262 | { | |
6263 | n += 16; | |
6264 | low_n -= 16; | |
6265 | } | |
6266 | } | |
6267 | else | |
6268 | { | |
6269 | low_n = ((mode) == TImode ? 0 | |
6270 | : n >= 0 ? (n & 0xfff) : -((-n) & 0xfff)); | |
6271 | n -= low_n; | |
6272 | } | |
6273 | ||
6274 | base_reg = gen_reg_rtx (SImode); | |
d66437c5 | 6275 | val = force_operand (plus_constant (xop0, n), NULL_RTX); |
ccf4d512 | 6276 | emit_move_insn (base_reg, val); |
d66437c5 | 6277 | x = plus_constant (base_reg, low_n); |
ccf4d512 RE |
6278 | } |
6279 | else if (xop0 != XEXP (x, 0) || xop1 != XEXP (x, 1)) | |
6280 | x = gen_rtx_PLUS (SImode, xop0, xop1); | |
6281 | } | |
6282 | ||
6283 | /* XXX We don't allow MINUS any more -- see comment in | |
c6c3dba9 | 6284 | arm_legitimate_address_outer_p (). */ |
ccf4d512 RE |
6285 | else if (GET_CODE (x) == MINUS) |
6286 | { | |
6287 | rtx xop0 = XEXP (x, 0); | |
6288 | rtx xop1 = XEXP (x, 1); | |
6289 | ||
6290 | if (CONSTANT_P (xop0)) | |
6291 | xop0 = force_reg (SImode, xop0); | |
6292 | ||
6293 | if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1)) | |
6294 | xop1 = force_reg (SImode, xop1); | |
6295 | ||
6296 | if (xop0 != XEXP (x, 0) || xop1 != XEXP (x, 1)) | |
6297 | x = gen_rtx_MINUS (SImode, xop0, xop1); | |
6298 | } | |
6299 | ||
86805759 NP |
6300 | /* Make sure to take full advantage of the pre-indexed addressing mode |
6301 | with absolute addresses which often allows for the base register to | |
6302 | be factorized for multiple adjacent memory references, and it might | |
6303 | even allows for the mini pool to be avoided entirely. */ | |
6304 | else if (GET_CODE (x) == CONST_INT && optimize > 0) | |
6305 | { | |
6306 | unsigned int bits; | |
6307 | HOST_WIDE_INT mask, base, index; | |
6308 | rtx base_reg; | |
6309 | ||
a50aa827 KH |
6310 | /* ldr and ldrb can use a 12-bit index, ldrsb and the rest can only |
6311 | use a 8-bit index. So let's use a 12-bit index for SImode only and | |
86805759 NP |
6312 | hope that arm_gen_constant will enable ldrb to use more bits. */ |
6313 | bits = (mode == SImode) ? 12 : 8; | |
6314 | mask = (1 << bits) - 1; | |
6315 | base = INTVAL (x) & ~mask; | |
6316 | index = INTVAL (x) & mask; | |
b107d743 | 6317 | if (bit_count (base & 0xffffffff) > (32 - bits)/2) |
86805759 NP |
6318 | { |
6319 | /* It'll most probably be more efficient to generate the base | |
6320 | with more bits set and use a negative index instead. */ | |
6321 | base |= mask; | |
6322 | index -= mask; | |
6323 | } | |
6324 | base_reg = force_reg (SImode, GEN_INT (base)); | |
d66437c5 | 6325 | x = plus_constant (base_reg, index); |
86805759 NP |
6326 | } |
6327 | ||
ccf4d512 RE |
6328 | if (flag_pic) |
6329 | { | |
6330 | /* We need to find and carefully transform any SYMBOL and LABEL | |
6331 | references; so go back to the original address expression. */ | |
6332 | rtx new_x = legitimize_pic_address (orig_x, mode, NULL_RTX); | |
6333 | ||
6334 | if (new_x != orig_x) | |
6335 | x = new_x; | |
6336 | } | |
6337 | ||
6338 | return x; | |
6339 | } | |
6340 | ||
6f5b4f3e RE |
6341 | |
6342 | /* Try machine-dependent ways of modifying an illegitimate Thumb address | |
6343 | to be legitimate. If we find one, return the new, valid address. */ | |
6344 | rtx | |
6345 | thumb_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode) | |
6346 | { | |
d3585b76 DJ |
6347 | if (arm_tls_symbol_p (x)) |
6348 | return legitimize_tls_address (x, NULL_RTX); | |
6349 | ||
6f5b4f3e RE |
6350 | if (GET_CODE (x) == PLUS |
6351 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
6352 | && (INTVAL (XEXP (x, 1)) >= 32 * GET_MODE_SIZE (mode) | |
6353 | || INTVAL (XEXP (x, 1)) < 0)) | |
6354 | { | |
6355 | rtx xop0 = XEXP (x, 0); | |
6356 | rtx xop1 = XEXP (x, 1); | |
6357 | HOST_WIDE_INT offset = INTVAL (xop1); | |
6358 | ||
6359 | /* Try and fold the offset into a biasing of the base register and | |
6360 | then offsetting that. Don't do this when optimizing for space | |
6361 | since it can cause too many CSEs. */ | |
6362 | if (optimize_size && offset >= 0 | |
6363 | && offset < 256 + 31 * GET_MODE_SIZE (mode)) | |
6364 | { | |
6365 | HOST_WIDE_INT delta; | |
6366 | ||
6367 | if (offset >= 256) | |
6368 | delta = offset - (256 - GET_MODE_SIZE (mode)); | |
6369 | else if (offset < 32 * GET_MODE_SIZE (mode) + 8) | |
6370 | delta = 31 * GET_MODE_SIZE (mode); | |
6371 | else | |
6372 | delta = offset & (~31 * GET_MODE_SIZE (mode)); | |
6373 | ||
6374 | xop0 = force_operand (plus_constant (xop0, offset - delta), | |
6375 | NULL_RTX); | |
6376 | x = plus_constant (xop0, delta); | |
6377 | } | |
6378 | else if (offset < 0 && offset > -256) | |
6379 | /* Small negative offsets are best done with a subtract before the | |
6380 | dereference, forcing these into a register normally takes two | |
6381 | instructions. */ | |
6382 | x = force_operand (x, NULL_RTX); | |
6383 | else | |
6384 | { | |
6385 | /* For the remaining cases, force the constant into a register. */ | |
6386 | xop1 = force_reg (SImode, xop1); | |
6387 | x = gen_rtx_PLUS (SImode, xop0, xop1); | |
6388 | } | |
6389 | } | |
6390 | else if (GET_CODE (x) == PLUS | |
6391 | && s_register_operand (XEXP (x, 1), SImode) | |
6392 | && !s_register_operand (XEXP (x, 0), SImode)) | |
6393 | { | |
6394 | rtx xop0 = force_operand (XEXP (x, 0), NULL_RTX); | |
6395 | ||
6396 | x = gen_rtx_PLUS (SImode, xop0, XEXP (x, 1)); | |
6397 | } | |
6398 | ||
6399 | if (flag_pic) | |
6400 | { | |
6401 | /* We need to find and carefully transform any SYMBOL and LABEL | |
6402 | references; so go back to the original address expression. */ | |
6403 | rtx new_x = legitimize_pic_address (orig_x, mode, NULL_RTX); | |
6404 | ||
6405 | if (new_x != orig_x) | |
6406 | x = new_x; | |
6407 | } | |
6408 | ||
6409 | return x; | |
6410 | } | |
6411 | ||
0cd98787 JZ |
6412 | bool |
6413 | arm_legitimize_reload_address (rtx *p, | |
6414 | enum machine_mode mode, | |
6415 | int opnum, int type, | |
6416 | int ind_levels ATTRIBUTE_UNUSED) | |
6417 | { | |
6418 | if (GET_CODE (*p) == PLUS | |
6419 | && GET_CODE (XEXP (*p, 0)) == REG | |
6420 | && ARM_REGNO_OK_FOR_BASE_P (REGNO (XEXP (*p, 0))) | |
6421 | && GET_CODE (XEXP (*p, 1)) == CONST_INT) | |
6422 | { | |
6423 | HOST_WIDE_INT val = INTVAL (XEXP (*p, 1)); | |
6424 | HOST_WIDE_INT low, high; | |
6425 | ||
6426 | if (mode == DImode || (mode == DFmode && TARGET_SOFT_FLOAT)) | |
6427 | low = ((val & 0xf) ^ 0x8) - 0x8; | |
6428 | else if (TARGET_MAVERICK && TARGET_HARD_FLOAT) | |
6429 | /* Need to be careful, -256 is not a valid offset. */ | |
6430 | low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); | |
6431 | else if (mode == SImode | |
6432 | || (mode == SFmode && TARGET_SOFT_FLOAT) | |
6433 | || ((mode == HImode || mode == QImode) && ! arm_arch4)) | |
6434 | /* Need to be careful, -4096 is not a valid offset. */ | |
6435 | low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff); | |
6436 | else if ((mode == HImode || mode == QImode) && arm_arch4) | |
6437 | /* Need to be careful, -256 is not a valid offset. */ | |
6438 | low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); | |
6439 | else if (GET_MODE_CLASS (mode) == MODE_FLOAT | |
6440 | && TARGET_HARD_FLOAT && TARGET_FPA) | |
6441 | /* Need to be careful, -1024 is not a valid offset. */ | |
6442 | low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); | |
6443 | else | |
6444 | return false; | |
6445 | ||
6446 | high = ((((val - low) & (unsigned HOST_WIDE_INT) 0xffffffff) | |
6447 | ^ (unsigned HOST_WIDE_INT) 0x80000000) | |
6448 | - (unsigned HOST_WIDE_INT) 0x80000000); | |
6449 | /* Check for overflow or zero */ | |
6450 | if (low == 0 || high == 0 || (high + low != val)) | |
6451 | return false; | |
6452 | ||
6453 | /* Reload the high part into a base reg; leave the low part | |
6454 | in the mem. */ | |
6455 | *p = gen_rtx_PLUS (GET_MODE (*p), | |
6456 | gen_rtx_PLUS (GET_MODE (*p), XEXP (*p, 0), | |
6457 | GEN_INT (high)), | |
6458 | GEN_INT (low)); | |
6459 | push_reload (XEXP (*p, 0), NULL_RTX, &XEXP (*p, 0), NULL, | |
6460 | MODE_BASE_REG_CLASS (mode), GET_MODE (*p), | |
6461 | VOIDmode, 0, 0, opnum, (enum reload_type) type); | |
6462 | return true; | |
6463 | } | |
6464 | ||
6465 | return false; | |
6466 | } | |
6467 | ||
a132dad6 | 6468 | rtx |
e0b92319 NC |
6469 | thumb_legitimize_reload_address (rtx *x_p, |
6470 | enum machine_mode mode, | |
6471 | int opnum, int type, | |
6472 | int ind_levels ATTRIBUTE_UNUSED) | |
a132dad6 RE |
6473 | { |
6474 | rtx x = *x_p; | |
e0b92319 | 6475 | |
a132dad6 RE |
6476 | if (GET_CODE (x) == PLUS |
6477 | && GET_MODE_SIZE (mode) < 4 | |
6478 | && REG_P (XEXP (x, 0)) | |
6479 | && XEXP (x, 0) == stack_pointer_rtx | |
6480 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
6481 | && !thumb_legitimate_offset_p (mode, INTVAL (XEXP (x, 1)))) | |
6482 | { | |
6483 | rtx orig_x = x; | |
6484 | ||
6485 | x = copy_rtx (x); | |
6486 | push_reload (orig_x, NULL_RTX, x_p, NULL, MODE_BASE_REG_CLASS (mode), | |
bbbbb16a | 6487 | Pmode, VOIDmode, 0, 0, opnum, (enum reload_type) type); |
a132dad6 RE |
6488 | return x; |
6489 | } | |
6490 | ||
6491 | /* If both registers are hi-regs, then it's better to reload the | |
6492 | entire expression rather than each register individually. That | |
6493 | only requires one reload register rather than two. */ | |
6494 | if (GET_CODE (x) == PLUS | |
6495 | && REG_P (XEXP (x, 0)) | |
6496 | && REG_P (XEXP (x, 1)) | |
6497 | && !REG_MODE_OK_FOR_REG_BASE_P (XEXP (x, 0), mode) | |
6498 | && !REG_MODE_OK_FOR_REG_BASE_P (XEXP (x, 1), mode)) | |
6499 | { | |
6500 | rtx orig_x = x; | |
6501 | ||
6502 | x = copy_rtx (x); | |
6503 | push_reload (orig_x, NULL_RTX, x_p, NULL, MODE_BASE_REG_CLASS (mode), | |
bbbbb16a | 6504 | Pmode, VOIDmode, 0, 0, opnum, (enum reload_type) type); |
a132dad6 RE |
6505 | return x; |
6506 | } | |
6507 | ||
6508 | return NULL; | |
6509 | } | |
d3585b76 DJ |
6510 | |
6511 | /* Test for various thread-local symbols. */ | |
6512 | ||
6513 | /* Return TRUE if X is a thread-local symbol. */ | |
6514 | ||
6515 | static bool | |
6516 | arm_tls_symbol_p (rtx x) | |
6517 | { | |
6518 | if (! TARGET_HAVE_TLS) | |
6519 | return false; | |
6520 | ||
6521 | if (GET_CODE (x) != SYMBOL_REF) | |
6522 | return false; | |
6523 | ||
6524 | return SYMBOL_REF_TLS_MODEL (x) != 0; | |
6525 | } | |
6526 | ||
6527 | /* Helper for arm_tls_referenced_p. */ | |
6528 | ||
6529 | static int | |
6530 | arm_tls_operand_p_1 (rtx *x, void *data ATTRIBUTE_UNUSED) | |
6531 | { | |
6532 | if (GET_CODE (*x) == SYMBOL_REF) | |
6533 | return SYMBOL_REF_TLS_MODEL (*x) != 0; | |
6534 | ||
6535 | /* Don't recurse into UNSPEC_TLS looking for TLS symbols; these are | |
6536 | TLS offsets, not real symbol references. */ | |
6537 | if (GET_CODE (*x) == UNSPEC | |
6538 | && XINT (*x, 1) == UNSPEC_TLS) | |
6539 | return -1; | |
6540 | ||
6541 | return 0; | |
6542 | } | |
6543 | ||
6544 | /* Return TRUE if X contains any TLS symbol references. */ | |
6545 | ||
6546 | bool | |
6547 | arm_tls_referenced_p (rtx x) | |
6548 | { | |
6549 | if (! TARGET_HAVE_TLS) | |
6550 | return false; | |
6551 | ||
6552 | return for_each_rtx (&x, arm_tls_operand_p_1, NULL); | |
6553 | } | |
8426b956 RS |
6554 | |
6555 | /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */ | |
6556 | ||
6557 | bool | |
6558 | arm_cannot_force_const_mem (rtx x) | |
6559 | { | |
6560 | rtx base, offset; | |
6561 | ||
6562 | if (ARM_OFFSETS_MUST_BE_WITHIN_SECTIONS_P) | |
6563 | { | |
6564 | split_const (x, &base, &offset); | |
6565 | if (GET_CODE (base) == SYMBOL_REF | |
6566 | && !offset_within_block_p (base, INTVAL (offset))) | |
6567 | return true; | |
6568 | } | |
6569 | return arm_tls_referenced_p (x); | |
6570 | } | |
6b990f6b | 6571 | \f |
e2c671ba RE |
6572 | #define REG_OR_SUBREG_REG(X) \ |
6573 | (GET_CODE (X) == REG \ | |
6574 | || (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG)) | |
6575 | ||
6576 | #define REG_OR_SUBREG_RTX(X) \ | |
6577 | (GET_CODE (X) == REG ? (X) : SUBREG_REG (X)) | |
6578 | ||
3c50106f | 6579 | static inline int |
5b3e6663 | 6580 | thumb1_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer) |
e2c671ba RE |
6581 | { |
6582 | enum machine_mode mode = GET_MODE (x); | |
e4c6a07a | 6583 | int total; |
e2c671ba | 6584 | |
9b66ebb1 | 6585 | switch (code) |
d5b7b3ae | 6586 | { |
9b66ebb1 PB |
6587 | case ASHIFT: |
6588 | case ASHIFTRT: | |
6589 | case LSHIFTRT: | |
f676971a | 6590 | case ROTATERT: |
9b66ebb1 PB |
6591 | case PLUS: |
6592 | case MINUS: | |
6593 | case COMPARE: | |
6594 | case NEG: | |
f676971a | 6595 | case NOT: |
9b66ebb1 | 6596 | return COSTS_N_INSNS (1); |
f676971a EC |
6597 | |
6598 | case MULT: | |
6599 | if (GET_CODE (XEXP (x, 1)) == CONST_INT) | |
6600 | { | |
6601 | int cycles = 0; | |
9b66ebb1 | 6602 | unsigned HOST_WIDE_INT i = INTVAL (XEXP (x, 1)); |
f676971a EC |
6603 | |
6604 | while (i) | |
6605 | { | |
6606 | i >>= 2; | |
6607 | cycles++; | |
6608 | } | |
6609 | return COSTS_N_INSNS (2) + cycles; | |
9b66ebb1 PB |
6610 | } |
6611 | return COSTS_N_INSNS (1) + 16; | |
f676971a EC |
6612 | |
6613 | case SET: | |
6614 | return (COSTS_N_INSNS (1) | |
6615 | + 4 * ((GET_CODE (SET_SRC (x)) == MEM) | |
9b66ebb1 | 6616 | + GET_CODE (SET_DEST (x)) == MEM)); |
f676971a EC |
6617 | |
6618 | case CONST_INT: | |
6619 | if (outer == SET) | |
6620 | { | |
6621 | if ((unsigned HOST_WIDE_INT) INTVAL (x) < 256) | |
6622 | return 0; | |
6623 | if (thumb_shiftable_const (INTVAL (x))) | |
6624 | return COSTS_N_INSNS (2); | |
6625 | return COSTS_N_INSNS (3); | |
6626 | } | |
9b66ebb1 | 6627 | else if ((outer == PLUS || outer == COMPARE) |
f676971a | 6628 | && INTVAL (x) < 256 && INTVAL (x) > -256) |
9b66ebb1 | 6629 | return 0; |
582021ba | 6630 | else if ((outer == IOR || outer == XOR || outer == AND) |
9b66ebb1 PB |
6631 | && INTVAL (x) < 256 && INTVAL (x) >= -256) |
6632 | return COSTS_N_INSNS (1); | |
c99102b8 BS |
6633 | else if (outer == AND) |
6634 | { | |
6635 | int i; | |
6636 | /* This duplicates the tests in the andsi3 expander. */ | |
6637 | for (i = 9; i <= 31; i++) | |
6638 | if ((((HOST_WIDE_INT) 1) << i) - 1 == INTVAL (x) | |
6639 | || (((HOST_WIDE_INT) 1) << i) - 1 == ~INTVAL (x)) | |
6640 | return COSTS_N_INSNS (2); | |
6641 | } | |
f676971a EC |
6642 | else if (outer == ASHIFT || outer == ASHIFTRT |
6643 | || outer == LSHIFTRT) | |
6644 | return 0; | |
9b66ebb1 | 6645 | return COSTS_N_INSNS (2); |
f676971a EC |
6646 | |
6647 | case CONST: | |
6648 | case CONST_DOUBLE: | |
6649 | case LABEL_REF: | |
6650 | case SYMBOL_REF: | |
9b66ebb1 | 6651 | return COSTS_N_INSNS (3); |
f676971a | 6652 | |
9b66ebb1 PB |
6653 | case UDIV: |
6654 | case UMOD: | |
6655 | case DIV: | |
6656 | case MOD: | |
6657 | return 100; | |
d5b7b3ae | 6658 | |
9b66ebb1 PB |
6659 | case TRUNCATE: |
6660 | return 99; | |
d5b7b3ae | 6661 | |
9b66ebb1 PB |
6662 | case AND: |
6663 | case XOR: | |
f676971a | 6664 | case IOR: |
ff482c8d | 6665 | /* XXX guess. */ |
9b66ebb1 | 6666 | return 8; |
d5b7b3ae | 6667 | |
9b66ebb1 PB |
6668 | case MEM: |
6669 | /* XXX another guess. */ | |
6670 | /* Memory costs quite a lot for the first word, but subsequent words | |
6671 | load at the equivalent of a single insn each. */ | |
6672 | return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD) | |
6673 | + ((GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x)) | |
6674 | ? 4 : 0)); | |
6675 | ||
6676 | case IF_THEN_ELSE: | |
ff482c8d | 6677 | /* XXX a guess. */ |
9b66ebb1 PB |
6678 | if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC) |
6679 | return 14; | |
6680 | return 2; | |
6681 | ||
e4c6a07a | 6682 | case SIGN_EXTEND: |
9b66ebb1 | 6683 | case ZERO_EXTEND: |
e4c6a07a BS |
6684 | total = mode == DImode ? COSTS_N_INSNS (1) : 0; |
6685 | total += thumb1_rtx_costs (XEXP (x, 0), GET_CODE (XEXP (x, 0)), code); | |
f676971a | 6686 | |
e4c6a07a BS |
6687 | if (mode == SImode) |
6688 | return total; | |
f676971a | 6689 | |
e4c6a07a BS |
6690 | if (arm_arch6) |
6691 | return total + COSTS_N_INSNS (1); | |
f676971a | 6692 | |
e4c6a07a BS |
6693 | /* Assume a two-shift sequence. Increase the cost slightly so |
6694 | we prefer actual shifts over an extend operation. */ | |
6695 | return total + 1 + COSTS_N_INSNS (2); | |
f676971a | 6696 | |
9b66ebb1 PB |
6697 | default: |
6698 | return 99; | |
d5b7b3ae | 6699 | } |
9b66ebb1 PB |
6700 | } |
6701 | ||
d5a0a47b RE |
6702 | static inline bool |
6703 | arm_rtx_costs_1 (rtx x, enum rtx_code outer, int* total, bool speed) | |
9b66ebb1 PB |
6704 | { |
6705 | enum machine_mode mode = GET_MODE (x); | |
6706 | enum rtx_code subcode; | |
d5a0a47b RE |
6707 | rtx operand; |
6708 | enum rtx_code code = GET_CODE (x); | |
d5a0a47b | 6709 | *total = 0; |
9b66ebb1 | 6710 | |
e2c671ba RE |
6711 | switch (code) |
6712 | { | |
6713 | case MEM: | |
6714 | /* Memory costs quite a lot for the first word, but subsequent words | |
6715 | load at the equivalent of a single insn each. */ | |
d5a0a47b RE |
6716 | *total = COSTS_N_INSNS (2 + ARM_NUM_REGS (mode)); |
6717 | return true; | |
e2c671ba RE |
6718 | |
6719 | case DIV: | |
6720 | case MOD: | |
b9c53150 RS |
6721 | case UDIV: |
6722 | case UMOD: | |
d5a0a47b RE |
6723 | if (TARGET_HARD_FLOAT && mode == SFmode) |
6724 | *total = COSTS_N_INSNS (2); | |
e0dc3601 | 6725 | else if (TARGET_HARD_FLOAT && mode == DFmode && !TARGET_VFP_SINGLE) |
d5a0a47b RE |
6726 | *total = COSTS_N_INSNS (4); |
6727 | else | |
6728 | *total = COSTS_N_INSNS (20); | |
6729 | return false; | |
e2c671ba RE |
6730 | |
6731 | case ROTATE: | |
d5a0a47b RE |
6732 | if (GET_CODE (XEXP (x, 1)) == REG) |
6733 | *total = COSTS_N_INSNS (1); /* Need to subtract from 32 */ | |
6734 | else if (GET_CODE (XEXP (x, 1)) != CONST_INT) | |
6735 | *total = rtx_cost (XEXP (x, 1), code, speed); | |
6736 | ||
e2c671ba RE |
6737 | /* Fall through */ |
6738 | case ROTATERT: | |
6739 | if (mode != SImode) | |
d5a0a47b RE |
6740 | { |
6741 | *total += COSTS_N_INSNS (4); | |
6742 | return true; | |
6743 | } | |
6744 | ||
e2c671ba RE |
6745 | /* Fall through */ |
6746 | case ASHIFT: case LSHIFTRT: case ASHIFTRT: | |
d5a0a47b | 6747 | *total += rtx_cost (XEXP (x, 0), code, speed); |
e2c671ba | 6748 | if (mode == DImode) |
d5a0a47b RE |
6749 | { |
6750 | *total += COSTS_N_INSNS (3); | |
6751 | return true; | |
6752 | } | |
7612f14d | 6753 | |
d5a0a47b | 6754 | *total += COSTS_N_INSNS (1); |
7612f14d PB |
6755 | /* Increase the cost of complex shifts because they aren't any faster, |
6756 | and reduce dual issue opportunities. */ | |
6757 | if (arm_tune_cortex_a9 | |
6758 | && outer != SET && GET_CODE (XEXP (x, 1)) != CONST_INT) | |
d5a0a47b RE |
6759 | ++*total; |
6760 | ||
6761 | return true; | |
e2c671ba RE |
6762 | |
6763 | case MINUS: | |
6764 | if (mode == DImode) | |
d5a0a47b RE |
6765 | { |
6766 | *total = COSTS_N_INSNS (ARM_NUM_REGS (mode)); | |
6767 | if (GET_CODE (XEXP (x, 0)) == CONST_INT | |
6768 | && const_ok_for_arm (INTVAL (XEXP (x, 0)))) | |
6769 | { | |
6770 | *total += rtx_cost (XEXP (x, 1), code, speed); | |
6771 | return true; | |
6772 | } | |
6773 | ||
6774 | if (GET_CODE (XEXP (x, 1)) == CONST_INT | |
6775 | && const_ok_for_arm (INTVAL (XEXP (x, 1)))) | |
6776 | { | |
6777 | *total += rtx_cost (XEXP (x, 0), code, speed); | |
6778 | return true; | |
6779 | } | |
6780 | ||
6781 | return false; | |
6782 | } | |
e2c671ba RE |
6783 | |
6784 | if (GET_MODE_CLASS (mode) == MODE_FLOAT) | |
d5a0a47b | 6785 | { |
e0dc3601 PB |
6786 | if (TARGET_HARD_FLOAT |
6787 | && (mode == SFmode | |
6788 | || (mode == DFmode && !TARGET_VFP_SINGLE))) | |
d5a0a47b RE |
6789 | { |
6790 | *total = COSTS_N_INSNS (1); | |
6791 | if (GET_CODE (XEXP (x, 0)) == CONST_DOUBLE | |
6792 | && arm_const_double_rtx (XEXP (x, 0))) | |
6793 | { | |
6794 | *total += rtx_cost (XEXP (x, 1), code, speed); | |
6795 | return true; | |
6796 | } | |
6797 | ||
6798 | if (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE | |
6799 | && arm_const_double_rtx (XEXP (x, 1))) | |
6800 | { | |
6801 | *total += rtx_cost (XEXP (x, 0), code, speed); | |
6802 | return true; | |
6803 | } | |
6804 | ||
6805 | return false; | |
6806 | } | |
6807 | *total = COSTS_N_INSNS (20); | |
6808 | return false; | |
6809 | } | |
6810 | ||
6811 | *total = COSTS_N_INSNS (1); | |
6812 | if (GET_CODE (XEXP (x, 0)) == CONST_INT | |
6813 | && const_ok_for_arm (INTVAL (XEXP (x, 0)))) | |
6814 | { | |
6815 | *total += rtx_cost (XEXP (x, 1), code, speed); | |
6816 | return true; | |
6817 | } | |
6818 | ||
6819 | subcode = GET_CODE (XEXP (x, 1)); | |
6820 | if (subcode == ASHIFT || subcode == ASHIFTRT | |
6821 | || subcode == LSHIFTRT | |
6822 | || subcode == ROTATE || subcode == ROTATERT) | |
6823 | { | |
6824 | *total += rtx_cost (XEXP (x, 0), code, speed); | |
6825 | *total += rtx_cost (XEXP (XEXP (x, 1), 0), subcode, speed); | |
6826 | return true; | |
6827 | } | |
6828 | ||
b32f6fff KH |
6829 | /* A shift as a part of RSB costs no more than RSB itself. */ |
6830 | if (GET_CODE (XEXP (x, 0)) == MULT | |
4c7c486a | 6831 | && power_of_two_operand (XEXP (XEXP (x, 0), 1), SImode)) |
b32f6fff KH |
6832 | { |
6833 | *total += rtx_cost (XEXP (XEXP (x, 0), 0), code, speed); | |
6834 | *total += rtx_cost (XEXP (x, 1), code, speed); | |
6835 | return true; | |
6836 | } | |
6837 | ||
d5a0a47b | 6838 | if (subcode == MULT |
4c7c486a | 6839 | && power_of_two_operand (XEXP (XEXP (x, 1), 1), SImode)) |
d5a0a47b RE |
6840 | { |
6841 | *total += rtx_cost (XEXP (x, 0), code, speed); | |
6842 | *total += rtx_cost (XEXP (XEXP (x, 1), 0), subcode, speed); | |
6843 | return true; | |
6844 | } | |
6845 | ||
6846 | if (GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == RTX_COMPARE | |
6847 | || GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == RTX_COMM_COMPARE) | |
6848 | { | |
6849 | *total = COSTS_N_INSNS (1) + rtx_cost (XEXP (x, 0), code, speed); | |
6850 | if (GET_CODE (XEXP (XEXP (x, 1), 0)) == REG | |
6851 | && REGNO (XEXP (XEXP (x, 1), 0)) != CC_REGNUM) | |
6852 | *total += COSTS_N_INSNS (1); | |
6853 | ||
6854 | return true; | |
6855 | } | |
6856 | ||
e2c671ba RE |
6857 | /* Fall through */ |
6858 | ||
f676971a | 6859 | case PLUS: |
d5a0a47b | 6860 | if (code == PLUS && arm_arch6 && mode == SImode |
ff069900 PB |
6861 | && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND |
6862 | || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)) | |
d5a0a47b RE |
6863 | { |
6864 | *total = COSTS_N_INSNS (1); | |
6865 | *total += rtx_cost (XEXP (XEXP (x, 0), 0), GET_CODE (XEXP (x, 0)), | |
6866 | speed); | |
6867 | *total += rtx_cost (XEXP (x, 1), code, speed); | |
6868 | return true; | |
6869 | } | |
ff069900 | 6870 | |
d5a0a47b RE |
6871 | /* MLA: All arguments must be registers. We filter out |
6872 | multiplication by a power of two, so that we fall down into | |
6873 | the code below. */ | |
6874 | if (GET_CODE (XEXP (x, 0)) == MULT | |
4c7c486a | 6875 | && !power_of_two_operand (XEXP (XEXP (x, 0), 1), SImode)) |
26da58dd | 6876 | { |
d5a0a47b RE |
6877 | /* The cost comes from the cost of the multiply. */ |
6878 | return false; | |
26da58dd PB |
6879 | } |
6880 | ||
e2c671ba | 6881 | if (GET_MODE_CLASS (mode) == MODE_FLOAT) |
d5a0a47b | 6882 | { |
e0dc3601 PB |
6883 | if (TARGET_HARD_FLOAT |
6884 | && (mode == SFmode | |
6885 | || (mode == DFmode && !TARGET_VFP_SINGLE))) | |
d5a0a47b RE |
6886 | { |
6887 | *total = COSTS_N_INSNS (1); | |
6888 | if (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE | |
6889 | && arm_const_double_rtx (XEXP (x, 1))) | |
6890 | { | |
6891 | *total += rtx_cost (XEXP (x, 0), code, speed); | |
6892 | return true; | |
6893 | } | |
6894 | ||
6895 | return false; | |
6896 | } | |
6897 | ||
6898 | *total = COSTS_N_INSNS (20); | |
6899 | return false; | |
6900 | } | |
6901 | ||
6902 | if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == RTX_COMPARE | |
6903 | || GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == RTX_COMM_COMPARE) | |
6904 | { | |
6905 | *total = COSTS_N_INSNS (1) + rtx_cost (XEXP (x, 1), code, speed); | |
6906 | if (GET_CODE (XEXP (XEXP (x, 0), 0)) == REG | |
6907 | && REGNO (XEXP (XEXP (x, 0), 0)) != CC_REGNUM) | |
6908 | *total += COSTS_N_INSNS (1); | |
6909 | return true; | |
6910 | } | |
e2c671ba RE |
6911 | |
6912 | /* Fall through */ | |
d5a0a47b | 6913 | |
f676971a | 6914 | case AND: case XOR: case IOR: |
e2c671ba RE |
6915 | |
6916 | /* Normally the frame registers will be spilt into reg+const during | |
6917 | reload, so it is a bad idea to combine them with other instructions, | |
6918 | since then they might not be moved outside of loops. As a compromise | |
6919 | we allow integration with ops that have a constant as their second | |
6920 | operand. */ | |
13cc4787 BS |
6921 | if (REG_OR_SUBREG_REG (XEXP (x, 0)) |
6922 | && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0))) | |
6923 | && GET_CODE (XEXP (x, 1)) != CONST_INT) | |
6924 | *total = COSTS_N_INSNS (1); | |
e2c671ba RE |
6925 | |
6926 | if (mode == DImode) | |
d5a0a47b RE |
6927 | { |
6928 | *total += COSTS_N_INSNS (2); | |
6929 | if (GET_CODE (XEXP (x, 1)) == CONST_INT | |
6930 | && const_ok_for_op (INTVAL (XEXP (x, 1)), code)) | |
6931 | { | |
6932 | *total += rtx_cost (XEXP (x, 0), code, speed); | |
6933 | return true; | |
6934 | } | |
e2c671ba | 6935 | |
d5a0a47b RE |
6936 | return false; |
6937 | } | |
6938 | ||
6939 | *total += COSTS_N_INSNS (1); | |
6940 | if (GET_CODE (XEXP (x, 1)) == CONST_INT | |
6941 | && const_ok_for_op (INTVAL (XEXP (x, 1)), code)) | |
6942 | { | |
6943 | *total += rtx_cost (XEXP (x, 0), code, speed); | |
6944 | return true; | |
6945 | } | |
6946 | subcode = GET_CODE (XEXP (x, 0)); | |
6947 | if (subcode == ASHIFT || subcode == ASHIFTRT | |
6948 | || subcode == LSHIFTRT | |
6949 | || subcode == ROTATE || subcode == ROTATERT) | |
6950 | { | |
6951 | *total += rtx_cost (XEXP (x, 1), code, speed); | |
6952 | *total += rtx_cost (XEXP (XEXP (x, 0), 0), subcode, speed); | |
6953 | return true; | |
6954 | } | |
6955 | ||
6956 | if (subcode == MULT | |
4c7c486a | 6957 | && power_of_two_operand (XEXP (XEXP (x, 0), 1), SImode)) |
d5a0a47b RE |
6958 | { |
6959 | *total += rtx_cost (XEXP (x, 1), code, speed); | |
6960 | *total += rtx_cost (XEXP (XEXP (x, 0), 0), subcode, speed); | |
6961 | return true; | |
6962 | } | |
6963 | ||
6964 | if (subcode == UMIN || subcode == UMAX | |
6965 | || subcode == SMIN || subcode == SMAX) | |
6966 | { | |
6967 | *total = COSTS_N_INSNS (3); | |
6968 | return true; | |
6969 | } | |
6970 | ||
6971 | return false; | |
e2c671ba RE |
6972 | |
6973 | case MULT: | |
9b66ebb1 | 6974 | /* This should have been handled by the CPU specific routines. */ |
e6d29d15 | 6975 | gcc_unreachable (); |
e2c671ba | 6976 | |
56636818 | 6977 | case TRUNCATE: |
9b66ebb1 | 6978 | if (arm_arch3m && mode == SImode |
56636818 JL |
6979 | && GET_CODE (XEXP (x, 0)) == LSHIFTRT |
6980 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT | |
6981 | && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) | |
6982 | == GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1))) | |
6983 | && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ZERO_EXTEND | |
6984 | || GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == SIGN_EXTEND)) | |
d5a0a47b RE |
6985 | { |
6986 | *total = rtx_cost (XEXP (XEXP (x, 0), 0), LSHIFTRT, speed); | |
6987 | return true; | |
6988 | } | |
6989 | *total = COSTS_N_INSNS (2); /* Plus the cost of the MULT */ | |
6990 | return false; | |
56636818 | 6991 | |
e2c671ba RE |
6992 | case NEG: |
6993 | if (GET_MODE_CLASS (mode) == MODE_FLOAT) | |
d5a0a47b | 6994 | { |
e0dc3601 PB |
6995 | if (TARGET_HARD_FLOAT |
6996 | && (mode == SFmode | |
6997 | || (mode == DFmode && !TARGET_VFP_SINGLE))) | |
d5a0a47b RE |
6998 | { |
6999 | *total = COSTS_N_INSNS (1); | |
7000 | return false; | |
7001 | } | |
7002 | *total = COSTS_N_INSNS (2); | |
7003 | return false; | |
7004 | } | |
7005 | ||
e2c671ba RE |
7006 | /* Fall through */ |
7007 | case NOT: | |
d5a0a47b RE |
7008 | *total = COSTS_N_INSNS (ARM_NUM_REGS(mode)); |
7009 | if (mode == SImode && code == NOT) | |
7010 | { | |
7011 | subcode = GET_CODE (XEXP (x, 0)); | |
7012 | if (subcode == ASHIFT || subcode == ASHIFTRT | |
7013 | || subcode == LSHIFTRT | |
7014 | || subcode == ROTATE || subcode == ROTATERT | |
7015 | || (subcode == MULT | |
4c7c486a | 7016 | && power_of_two_operand (XEXP (XEXP (x, 0), 1), SImode))) |
d5a0a47b RE |
7017 | { |
7018 | *total += rtx_cost (XEXP (XEXP (x, 0), 0), subcode, speed); | |
7019 | /* Register shifts cost an extra cycle. */ | |
7020 | if (GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT) | |
7021 | *total += COSTS_N_INSNS (1) + rtx_cost (XEXP (XEXP (x, 0), 1), | |
7022 | subcode, speed); | |
7023 | return true; | |
7024 | } | |
7025 | } | |
e2c671ba | 7026 | |
d5a0a47b | 7027 | return false; |
e2c671ba RE |
7028 | |
7029 | case IF_THEN_ELSE: | |
7030 | if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC) | |
d5a0a47b RE |
7031 | { |
7032 | *total = COSTS_N_INSNS (4); | |
7033 | return true; | |
7034 | } | |
7035 | ||
7036 | operand = XEXP (x, 0); | |
7037 | ||
7038 | if (!((GET_RTX_CLASS (GET_CODE (operand)) == RTX_COMPARE | |
7039 | || GET_RTX_CLASS (GET_CODE (operand)) == RTX_COMM_COMPARE) | |
7040 | && GET_CODE (XEXP (operand, 0)) == REG | |
7041 | && REGNO (XEXP (operand, 0)) == CC_REGNUM)) | |
7042 | *total += COSTS_N_INSNS (1); | |
7043 | *total += (rtx_cost (XEXP (x, 1), code, speed) | |
7044 | + rtx_cost (XEXP (x, 2), code, speed)); | |
7045 | return true; | |
7046 | ||
7047 | case NE: | |
7048 | if (mode == SImode && XEXP (x, 1) == const0_rtx) | |
7049 | { | |
7050 | *total = COSTS_N_INSNS (2) + rtx_cost (XEXP (x, 0), code, speed); | |
7051 | return true; | |
7052 | } | |
7053 | goto scc_insn; | |
7054 | ||
7055 | case GE: | |
7056 | if ((GET_CODE (XEXP (x, 0)) != REG || REGNO (XEXP (x, 0)) != CC_REGNUM) | |
7057 | && mode == SImode && XEXP (x, 1) == const0_rtx) | |
7058 | { | |
7059 | *total = COSTS_N_INSNS (2) + rtx_cost (XEXP (x, 0), code, speed); | |
7060 | return true; | |
7061 | } | |
7062 | goto scc_insn; | |
7063 | ||
7064 | case LT: | |
7065 | if ((GET_CODE (XEXP (x, 0)) != REG || REGNO (XEXP (x, 0)) != CC_REGNUM) | |
7066 | && mode == SImode && XEXP (x, 1) == const0_rtx) | |
7067 | { | |
7068 | *total = COSTS_N_INSNS (1) + rtx_cost (XEXP (x, 0), code, speed); | |
7069 | return true; | |
7070 | } | |
7071 | goto scc_insn; | |
7072 | ||
7073 | case EQ: | |
7074 | case GT: | |
7075 | case LE: | |
7076 | case GEU: | |
7077 | case LTU: | |
7078 | case GTU: | |
7079 | case LEU: | |
7080 | case UNORDERED: | |
7081 | case ORDERED: | |
7082 | case UNEQ: | |
7083 | case UNGE: | |
7084 | case UNLT: | |
7085 | case UNGT: | |
7086 | case UNLE: | |
7087 | scc_insn: | |
7088 | /* SCC insns. In the case where the comparison has already been | |
7089 | performed, then they cost 2 instructions. Otherwise they need | |
7090 | an additional comparison before them. */ | |
7091 | *total = COSTS_N_INSNS (2); | |
7092 | if (GET_CODE (XEXP (x, 0)) == REG && REGNO (XEXP (x, 0)) == CC_REGNUM) | |
7093 | { | |
7094 | return true; | |
7095 | } | |
e2c671ba | 7096 | |
d5a0a47b | 7097 | /* Fall through */ |
e2c671ba | 7098 | case COMPARE: |
d5a0a47b RE |
7099 | if (GET_CODE (XEXP (x, 0)) == REG && REGNO (XEXP (x, 0)) == CC_REGNUM) |
7100 | { | |
7101 | *total = 0; | |
7102 | return true; | |
7103 | } | |
7104 | ||
7105 | *total += COSTS_N_INSNS (1); | |
7106 | if (GET_CODE (XEXP (x, 1)) == CONST_INT | |
7107 | && const_ok_for_op (INTVAL (XEXP (x, 1)), code)) | |
7108 | { | |
7109 | *total += rtx_cost (XEXP (x, 0), code, speed); | |
7110 | return true; | |
7111 | } | |
7112 | ||
7113 | subcode = GET_CODE (XEXP (x, 0)); | |
7114 | if (subcode == ASHIFT || subcode == ASHIFTRT | |
7115 | || subcode == LSHIFTRT | |
7116 | || subcode == ROTATE || subcode == ROTATERT) | |
7117 | { | |
7118 | *total += rtx_cost (XEXP (x, 1), code, speed); | |
7119 | *total += rtx_cost (XEXP (XEXP (x, 0), 0), subcode, speed); | |
7120 | return true; | |
7121 | } | |
7122 | ||
7123 | if (subcode == MULT | |
4c7c486a | 7124 | && power_of_two_operand (XEXP (XEXP (x, 0), 1), SImode)) |
d5a0a47b RE |
7125 | { |
7126 | *total += rtx_cost (XEXP (x, 1), code, speed); | |
7127 | *total += rtx_cost (XEXP (XEXP (x, 0), 0), subcode, speed); | |
7128 | return true; | |
7129 | } | |
7130 | ||
7131 | return false; | |
7132 | ||
7133 | case UMIN: | |
7134 | case UMAX: | |
7135 | case SMIN: | |
7136 | case SMAX: | |
7137 | *total = COSTS_N_INSNS (2) + rtx_cost (XEXP (x, 0), code, speed); | |
7138 | if (GET_CODE (XEXP (x, 1)) != CONST_INT | |
7139 | || !const_ok_for_arm (INTVAL (XEXP (x, 1)))) | |
7140 | *total += rtx_cost (XEXP (x, 1), code, speed); | |
7141 | return true; | |
e2c671ba RE |
7142 | |
7143 | case ABS: | |
bbbbb16a | 7144 | if (GET_MODE_CLASS (mode) == MODE_FLOAT) |
d5a0a47b | 7145 | { |
e0dc3601 PB |
7146 | if (TARGET_HARD_FLOAT |
7147 | && (mode == SFmode | |
7148 | || (mode == DFmode && !TARGET_VFP_SINGLE))) | |
d5a0a47b RE |
7149 | { |
7150 | *total = COSTS_N_INSNS (1); | |
7151 | return false; | |
7152 | } | |
7153 | *total = COSTS_N_INSNS (20); | |
7154 | return false; | |
7155 | } | |
7156 | *total = COSTS_N_INSNS (1); | |
7157 | if (mode == DImode) | |
7158 | *total += COSTS_N_INSNS (3); | |
7159 | return false; | |
e2c671ba RE |
7160 | |
7161 | case SIGN_EXTEND: | |
e2c671ba | 7162 | case ZERO_EXTEND: |
d5a0a47b RE |
7163 | *total = 0; |
7164 | if (GET_MODE_CLASS (mode) == MODE_INT) | |
e2c671ba | 7165 | { |
e4c6a07a BS |
7166 | rtx op = XEXP (x, 0); |
7167 | enum machine_mode opmode = GET_MODE (op); | |
7168 | ||
d5a0a47b RE |
7169 | if (mode == DImode) |
7170 | *total += COSTS_N_INSNS (1); | |
e2c671ba | 7171 | |
e4c6a07a | 7172 | if (opmode != SImode) |
d5a0a47b | 7173 | { |
e4c6a07a | 7174 | if (MEM_P (op)) |
d5a0a47b | 7175 | { |
e4c6a07a BS |
7176 | /* If !arm_arch4, we use one of the extendhisi2_mem |
7177 | or movhi_bytes patterns for HImode. For a QImode | |
7178 | sign extension, we first zero-extend from memory | |
7179 | and then perform a shift sequence. */ | |
7180 | if (!arm_arch4 && (opmode != QImode || code == SIGN_EXTEND)) | |
7181 | *total += COSTS_N_INSNS (2); | |
d5a0a47b | 7182 | } |
e4c6a07a BS |
7183 | else if (arm_arch6) |
7184 | *total += COSTS_N_INSNS (1); | |
7185 | ||
7186 | /* We don't have the necessary insn, so we need to perform some | |
7187 | other operation. */ | |
7188 | else if (TARGET_ARM && code == ZERO_EXTEND && mode == QImode) | |
7189 | /* An and with constant 255. */ | |
7190 | *total += COSTS_N_INSNS (1); | |
7191 | else | |
7192 | /* A shift sequence. Increase costs slightly to avoid | |
7193 | combining two shifts into an extend operation. */ | |
7194 | *total += COSTS_N_INSNS (2) + 1; | |
d5a0a47b | 7195 | } |
e2c671ba | 7196 | |
d5a0a47b RE |
7197 | return false; |
7198 | } | |
ad076f4e | 7199 | |
d5a0a47b RE |
7200 | switch (GET_MODE (XEXP (x, 0))) |
7201 | { | |
5a9335ef NC |
7202 | case V8QImode: |
7203 | case V4HImode: | |
7204 | case V2SImode: | |
7205 | case V4QImode: | |
7206 | case V2HImode: | |
d5a0a47b RE |
7207 | *total = COSTS_N_INSNS (1); |
7208 | return false; | |
5a9335ef | 7209 | |
ad076f4e | 7210 | default: |
e6d29d15 | 7211 | gcc_unreachable (); |
e2c671ba | 7212 | } |
e6d29d15 | 7213 | gcc_unreachable (); |
e2c671ba | 7214 | |
d5a0a47b RE |
7215 | case ZERO_EXTRACT: |
7216 | case SIGN_EXTRACT: | |
7217 | *total = COSTS_N_INSNS (1) + rtx_cost (XEXP (x, 0), code, speed); | |
7218 | return true; | |
7219 | ||
f676971a | 7220 | case CONST_INT: |
d5a0a47b RE |
7221 | if (const_ok_for_arm (INTVAL (x)) |
7222 | || const_ok_for_arm (~INTVAL (x))) | |
7223 | *total = COSTS_N_INSNS (1); | |
f676971a | 7224 | else |
d5a0a47b RE |
7225 | *total = COSTS_N_INSNS (arm_gen_constant (SET, mode, NULL_RTX, |
7226 | INTVAL (x), NULL_RTX, | |
7227 | NULL_RTX, 0, 0)); | |
7228 | return true; | |
f676971a EC |
7229 | |
7230 | case CONST: | |
7231 | case LABEL_REF: | |
7232 | case SYMBOL_REF: | |
d5a0a47b RE |
7233 | *total = COSTS_N_INSNS (3); |
7234 | return true; | |
f676971a | 7235 | |
571191af | 7236 | case HIGH: |
d5a0a47b RE |
7237 | *total = COSTS_N_INSNS (1); |
7238 | return true; | |
7239 | ||
571191af | 7240 | case LO_SUM: |
d5a0a47b RE |
7241 | *total = COSTS_N_INSNS (1); |
7242 | *total += rtx_cost (XEXP (x, 0), code, speed); | |
7243 | return true; | |
571191af | 7244 | |
f676971a | 7245 | case CONST_DOUBLE: |
e0dc3601 PB |
7246 | if (TARGET_HARD_FLOAT && vfp3_const_double_rtx (x) |
7247 | && (mode == SFmode || !TARGET_VFP_SINGLE)) | |
d5a0a47b RE |
7248 | *total = COSTS_N_INSNS (1); |
7249 | else | |
7250 | *total = COSTS_N_INSNS (4); | |
7251 | return true; | |
f676971a | 7252 | |
e2c671ba | 7253 | default: |
d5a0a47b RE |
7254 | *total = COSTS_N_INSNS (4); |
7255 | return false; | |
e2c671ba RE |
7256 | } |
7257 | } | |
32de079a | 7258 | |
7548c1be WG |
7259 | /* Estimates the size cost of thumb1 instructions. |
7260 | For now most of the code is copied from thumb1_rtx_costs. We need more | |
7261 | fine grain tuning when we have more related test cases. */ | |
7262 | static inline int | |
7263 | thumb1_size_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer) | |
7264 | { | |
7265 | enum machine_mode mode = GET_MODE (x); | |
7266 | ||
7267 | switch (code) | |
7268 | { | |
7269 | case ASHIFT: | |
7270 | case ASHIFTRT: | |
7271 | case LSHIFTRT: | |
7272 | case ROTATERT: | |
7273 | case PLUS: | |
7274 | case MINUS: | |
7275 | case COMPARE: | |
7276 | case NEG: | |
7277 | case NOT: | |
7278 | return COSTS_N_INSNS (1); | |
7279 | ||
7280 | case MULT: | |
7281 | if (GET_CODE (XEXP (x, 1)) == CONST_INT) | |
7282 | { | |
7283 | /* Thumb1 mul instruction can't operate on const. We must Load it | |
7284 | into a register first. */ | |
7285 | int const_size = thumb1_size_rtx_costs (XEXP (x, 1), CONST_INT, SET); | |
7286 | return COSTS_N_INSNS (1) + const_size; | |
7287 | } | |
7288 | return COSTS_N_INSNS (1); | |
7289 | ||
7290 | case SET: | |
7291 | return (COSTS_N_INSNS (1) | |
7292 | + 4 * ((GET_CODE (SET_SRC (x)) == MEM) | |
7293 | + GET_CODE (SET_DEST (x)) == MEM)); | |
7294 | ||
7295 | case CONST_INT: | |
7296 | if (outer == SET) | |
7297 | { | |
7298 | if ((unsigned HOST_WIDE_INT) INTVAL (x) < 256) | |
9b9ee6d3 | 7299 | return COSTS_N_INSNS (1); |
3393e880 MK |
7300 | /* See split "TARGET_THUMB1 && satisfies_constraint_J". */ |
7301 | if (INTVAL (x) >= -255 && INTVAL (x) <= -1) | |
7302 | return COSTS_N_INSNS (2); | |
7303 | /* See split "TARGET_THUMB1 && satisfies_constraint_K". */ | |
7548c1be WG |
7304 | if (thumb_shiftable_const (INTVAL (x))) |
7305 | return COSTS_N_INSNS (2); | |
7306 | return COSTS_N_INSNS (3); | |
7307 | } | |
7308 | else if ((outer == PLUS || outer == COMPARE) | |
7309 | && INTVAL (x) < 256 && INTVAL (x) > -256) | |
7310 | return 0; | |
7311 | else if ((outer == IOR || outer == XOR || outer == AND) | |
7312 | && INTVAL (x) < 256 && INTVAL (x) >= -256) | |
7313 | return COSTS_N_INSNS (1); | |
7314 | else if (outer == AND) | |
7315 | { | |
7316 | int i; | |
7317 | /* This duplicates the tests in the andsi3 expander. */ | |
7318 | for (i = 9; i <= 31; i++) | |
7319 | if ((((HOST_WIDE_INT) 1) << i) - 1 == INTVAL (x) | |
7320 | || (((HOST_WIDE_INT) 1) << i) - 1 == ~INTVAL (x)) | |
7321 | return COSTS_N_INSNS (2); | |
7322 | } | |
7323 | else if (outer == ASHIFT || outer == ASHIFTRT | |
7324 | || outer == LSHIFTRT) | |
7325 | return 0; | |
7326 | return COSTS_N_INSNS (2); | |
7327 | ||
7328 | case CONST: | |
7329 | case CONST_DOUBLE: | |
7330 | case LABEL_REF: | |
7331 | case SYMBOL_REF: | |
7332 | return COSTS_N_INSNS (3); | |
7333 | ||
7334 | case UDIV: | |
7335 | case UMOD: | |
7336 | case DIV: | |
7337 | case MOD: | |
7338 | return 100; | |
7339 | ||
7340 | case TRUNCATE: | |
7341 | return 99; | |
7342 | ||
7343 | case AND: | |
7344 | case XOR: | |
7345 | case IOR: | |
7346 | /* XXX guess. */ | |
7347 | return 8; | |
7348 | ||
7349 | case MEM: | |
7350 | /* XXX another guess. */ | |
7351 | /* Memory costs quite a lot for the first word, but subsequent words | |
7352 | load at the equivalent of a single insn each. */ | |
7353 | return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD) | |
7354 | + ((GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x)) | |
7355 | ? 4 : 0)); | |
7356 | ||
7357 | case IF_THEN_ELSE: | |
7358 | /* XXX a guess. */ | |
7359 | if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC) | |
7360 | return 14; | |
7361 | return 2; | |
7362 | ||
7363 | case ZERO_EXTEND: | |
7364 | /* XXX still guessing. */ | |
7365 | switch (GET_MODE (XEXP (x, 0))) | |
7366 | { | |
7367 | case QImode: | |
7368 | return (1 + (mode == DImode ? 4 : 0) | |
7369 | + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0)); | |
7370 | ||
7371 | case HImode: | |
7372 | return (4 + (mode == DImode ? 4 : 0) | |
7373 | + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0)); | |
7374 | ||
7375 | case SImode: | |
7376 | return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0)); | |
7377 | ||
7378 | default: | |
7379 | return 99; | |
7380 | } | |
7381 | ||
7382 | default: | |
7383 | return 99; | |
7384 | } | |
7385 | } | |
7386 | ||
21b5653c RE |
7387 | /* RTX costs when optimizing for size. */ |
7388 | static bool | |
d5a0a47b RE |
7389 | arm_size_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code, |
7390 | int *total) | |
21b5653c RE |
7391 | { |
7392 | enum machine_mode mode = GET_MODE (x); | |
09754904 | 7393 | if (TARGET_THUMB1) |
21b5653c | 7394 | { |
7548c1be | 7395 | *total = thumb1_size_rtx_costs (x, code, outer_code); |
21b5653c RE |
7396 | return true; |
7397 | } | |
7398 | ||
09754904 | 7399 | /* FIXME: This makes no attempt to prefer narrow Thumb-2 instructions. */ |
21b5653c RE |
7400 | switch (code) |
7401 | { | |
7402 | case MEM: | |
f676971a | 7403 | /* A memory access costs 1 insn if the mode is small, or the address is |
21b5653c RE |
7404 | a single register, otherwise it costs one insn per word. */ |
7405 | if (REG_P (XEXP (x, 0))) | |
7406 | *total = COSTS_N_INSNS (1); | |
d37c3c62 MK |
7407 | else if (flag_pic |
7408 | && GET_CODE (XEXP (x, 0)) == PLUS | |
7409 | && will_be_in_index_register (XEXP (XEXP (x, 0), 1))) | |
7410 | /* This will be split into two instructions. | |
7411 | See arm.md:calculate_pic_address. */ | |
7412 | *total = COSTS_N_INSNS (2); | |
21b5653c RE |
7413 | else |
7414 | *total = COSTS_N_INSNS (ARM_NUM_REGS (mode)); | |
7415 | return true; | |
7416 | ||
7417 | case DIV: | |
7418 | case MOD: | |
7419 | case UDIV: | |
7420 | case UMOD: | |
7421 | /* Needs a libcall, so it costs about this. */ | |
7422 | *total = COSTS_N_INSNS (2); | |
7423 | return false; | |
7424 | ||
7425 | case ROTATE: | |
7426 | if (mode == SImode && GET_CODE (XEXP (x, 1)) == REG) | |
7427 | { | |
f40751dd | 7428 | *total = COSTS_N_INSNS (2) + rtx_cost (XEXP (x, 0), code, false); |
21b5653c RE |
7429 | return true; |
7430 | } | |
7431 | /* Fall through */ | |
7432 | case ROTATERT: | |
7433 | case ASHIFT: | |
7434 | case LSHIFTRT: | |
7435 | case ASHIFTRT: | |
7436 | if (mode == DImode && GET_CODE (XEXP (x, 1)) == CONST_INT) | |
7437 | { | |
f40751dd | 7438 | *total = COSTS_N_INSNS (3) + rtx_cost (XEXP (x, 0), code, false); |
21b5653c RE |
7439 | return true; |
7440 | } | |
7441 | else if (mode == SImode) | |
7442 | { | |
f40751dd | 7443 | *total = COSTS_N_INSNS (1) + rtx_cost (XEXP (x, 0), code, false); |
21b5653c RE |
7444 | /* Slightly disparage register shifts, but not by much. */ |
7445 | if (GET_CODE (XEXP (x, 1)) != CONST_INT) | |
f40751dd | 7446 | *total += 1 + rtx_cost (XEXP (x, 1), code, false); |
21b5653c RE |
7447 | return true; |
7448 | } | |
7449 | ||
7450 | /* Needs a libcall. */ | |
7451 | *total = COSTS_N_INSNS (2); | |
7452 | return false; | |
7453 | ||
7454 | case MINUS: | |
e0dc3601 PB |
7455 | if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT |
7456 | && (mode == SFmode || !TARGET_VFP_SINGLE)) | |
21b5653c RE |
7457 | { |
7458 | *total = COSTS_N_INSNS (1); | |
7459 | return false; | |
7460 | } | |
7461 | ||
7462 | if (mode == SImode) | |
7463 | { | |
7464 | enum rtx_code subcode0 = GET_CODE (XEXP (x, 0)); | |
7465 | enum rtx_code subcode1 = GET_CODE (XEXP (x, 1)); | |
7466 | ||
7467 | if (subcode0 == ROTATE || subcode0 == ROTATERT || subcode0 == ASHIFT | |
7468 | || subcode0 == LSHIFTRT || subcode0 == ASHIFTRT | |
7469 | || subcode1 == ROTATE || subcode1 == ROTATERT | |
7470 | || subcode1 == ASHIFT || subcode1 == LSHIFTRT | |
7471 | || subcode1 == ASHIFTRT) | |
7472 | { | |
7473 | /* It's just the cost of the two operands. */ | |
7474 | *total = 0; | |
7475 | return false; | |
7476 | } | |
7477 | ||
7478 | *total = COSTS_N_INSNS (1); | |
7479 | return false; | |
7480 | } | |
7481 | ||
7482 | *total = COSTS_N_INSNS (ARM_NUM_REGS (mode)); | |
7483 | return false; | |
7484 | ||
f676971a | 7485 | case PLUS: |
e0dc3601 PB |
7486 | if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT |
7487 | && (mode == SFmode || !TARGET_VFP_SINGLE)) | |
21b5653c RE |
7488 | { |
7489 | *total = COSTS_N_INSNS (1); | |
7490 | return false; | |
7491 | } | |
7492 | ||
6e782a29 KH |
7493 | /* A shift as a part of ADD costs nothing. */ |
7494 | if (GET_CODE (XEXP (x, 0)) == MULT | |
7495 | && power_of_two_operand (XEXP (XEXP (x, 0), 1), SImode)) | |
7496 | { | |
7497 | *total = COSTS_N_INSNS (TARGET_THUMB2 ? 2 : 1); | |
7498 | *total += rtx_cost (XEXP (XEXP (x, 0), 0), code, false); | |
7499 | *total += rtx_cost (XEXP (x, 1), code, false); | |
7500 | return true; | |
7501 | } | |
7502 | ||
21b5653c RE |
7503 | /* Fall through */ |
7504 | case AND: case XOR: case IOR: | |
7505 | if (mode == SImode) | |
7506 | { | |
7507 | enum rtx_code subcode = GET_CODE (XEXP (x, 0)); | |
7508 | ||
7509 | if (subcode == ROTATE || subcode == ROTATERT || subcode == ASHIFT | |
7510 | || subcode == LSHIFTRT || subcode == ASHIFTRT | |
7511 | || (code == AND && subcode == NOT)) | |
7512 | { | |
7513 | /* It's just the cost of the two operands. */ | |
7514 | *total = 0; | |
7515 | return false; | |
7516 | } | |
7517 | } | |
7518 | ||
7519 | *total = COSTS_N_INSNS (ARM_NUM_REGS (mode)); | |
7520 | return false; | |
7521 | ||
7522 | case MULT: | |
7523 | *total = COSTS_N_INSNS (ARM_NUM_REGS (mode)); | |
7524 | return false; | |
7525 | ||
7526 | case NEG: | |
e0dc3601 PB |
7527 | if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT |
7528 | && (mode == SFmode || !TARGET_VFP_SINGLE)) | |
7ce8451d MG |
7529 | { |
7530 | *total = COSTS_N_INSNS (1); | |
7531 | return false; | |
7532 | } | |
7533 | ||
21b5653c RE |
7534 | /* Fall through */ |
7535 | case NOT: | |
7536 | *total = COSTS_N_INSNS (ARM_NUM_REGS (mode)); | |
7537 | ||
7538 | return false; | |
7539 | ||
7540 | case IF_THEN_ELSE: | |
7541 | *total = 0; | |
7542 | return false; | |
7543 | ||
7544 | case COMPARE: | |
7545 | if (cc_register (XEXP (x, 0), VOIDmode)) | |
7546 | * total = 0; | |
7547 | else | |
7548 | *total = COSTS_N_INSNS (1); | |
7549 | return false; | |
7550 | ||
7551 | case ABS: | |
e0dc3601 PB |
7552 | if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT |
7553 | && (mode == SFmode || !TARGET_VFP_SINGLE)) | |
21b5653c RE |
7554 | *total = COSTS_N_INSNS (1); |
7555 | else | |
7556 | *total = COSTS_N_INSNS (1 + ARM_NUM_REGS (mode)); | |
7557 | return false; | |
7558 | ||
7559 | case SIGN_EXTEND: | |
21b5653c | 7560 | case ZERO_EXTEND: |
e4c6a07a | 7561 | return arm_rtx_costs_1 (x, outer_code, total, 0); |
21b5653c | 7562 | |
f676971a EC |
7563 | case CONST_INT: |
7564 | if (const_ok_for_arm (INTVAL (x))) | |
6e782a29 KH |
7565 | /* A multiplication by a constant requires another instruction |
7566 | to load the constant to a register. */ | |
7567 | *total = COSTS_N_INSNS ((outer_code == SET || outer_code == MULT) | |
7568 | ? 1 : 0); | |
21b5653c RE |
7569 | else if (const_ok_for_arm (~INTVAL (x))) |
7570 | *total = COSTS_N_INSNS (outer_code == AND ? 0 : 1); | |
7571 | else if (const_ok_for_arm (-INTVAL (x))) | |
7572 | { | |
7573 | if (outer_code == COMPARE || outer_code == PLUS | |
7574 | || outer_code == MINUS) | |
7575 | *total = 0; | |
7576 | else | |
7577 | *total = COSTS_N_INSNS (1); | |
7578 | } | |
7579 | else | |
7580 | *total = COSTS_N_INSNS (2); | |
7581 | return true; | |
f676971a EC |
7582 | |
7583 | case CONST: | |
7584 | case LABEL_REF: | |
7585 | case SYMBOL_REF: | |
21b5653c RE |
7586 | *total = COSTS_N_INSNS (2); |
7587 | return true; | |
f676971a | 7588 | |
21b5653c RE |
7589 | case CONST_DOUBLE: |
7590 | *total = COSTS_N_INSNS (4); | |
7591 | return true; | |
7592 | ||
571191af PB |
7593 | case HIGH: |
7594 | case LO_SUM: | |
7595 | /* We prefer constant pool entries to MOVW/MOVT pairs, so bump the | |
7596 | cost of these slightly. */ | |
7597 | *total = COSTS_N_INSNS (1) + 1; | |
7598 | return true; | |
7599 | ||
21b5653c RE |
7600 | default: |
7601 | if (mode != VOIDmode) | |
7602 | *total = COSTS_N_INSNS (ARM_NUM_REGS (mode)); | |
7603 | else | |
7604 | *total = COSTS_N_INSNS (4); /* How knows? */ | |
7605 | return false; | |
7606 | } | |
7607 | } | |
7608 | ||
f40751dd JH |
7609 | /* RTX costs when optimizing for size. */ |
7610 | static bool | |
d5a0a47b RE |
7611 | arm_rtx_costs (rtx x, int code, int outer_code, int *total, |
7612 | bool speed) | |
f40751dd JH |
7613 | { |
7614 | if (!speed) | |
bbbbb16a ILT |
7615 | return arm_size_rtx_costs (x, (enum rtx_code) code, |
7616 | (enum rtx_code) outer_code, total); | |
f40751dd | 7617 | else |
1b78f575 RE |
7618 | return current_tune->rtx_costs (x, (enum rtx_code) code, |
7619 | (enum rtx_code) outer_code, | |
7620 | total, speed); | |
f40751dd JH |
7621 | } |
7622 | ||
5b3e6663 PB |
7623 | /* RTX costs for cores with a slow MUL implementation. Thumb-2 is not |
7624 | supported on any "slowmul" cores, so it can be ignored. */ | |
9b66ebb1 | 7625 | |
3c50106f | 7626 | static bool |
d5a0a47b RE |
7627 | arm_slowmul_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code, |
7628 | int *total, bool speed) | |
3c50106f | 7629 | { |
9b66ebb1 PB |
7630 | enum machine_mode mode = GET_MODE (x); |
7631 | ||
7632 | if (TARGET_THUMB) | |
7633 | { | |
5b3e6663 | 7634 | *total = thumb1_rtx_costs (x, code, outer_code); |
9b66ebb1 PB |
7635 | return true; |
7636 | } | |
f676971a | 7637 | |
9b66ebb1 PB |
7638 | switch (code) |
7639 | { | |
7640 | case MULT: | |
7641 | if (GET_MODE_CLASS (mode) == MODE_FLOAT | |
7642 | || mode == DImode) | |
7643 | { | |
d5a0a47b RE |
7644 | *total = COSTS_N_INSNS (20); |
7645 | return false; | |
9b66ebb1 PB |
7646 | } |
7647 | ||
7648 | if (GET_CODE (XEXP (x, 1)) == CONST_INT) | |
7649 | { | |
7650 | unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1)) | |
7651 | & (unsigned HOST_WIDE_INT) 0xffffffff); | |
7652 | int cost, const_ok = const_ok_for_arm (i); | |
7653 | int j, booth_unit_size; | |
7654 | ||
f676971a | 7655 | /* Tune as appropriate. */ |
9b66ebb1 PB |
7656 | cost = const_ok ? 4 : 8; |
7657 | booth_unit_size = 2; | |
7658 | for (j = 0; i && j < 32; j += booth_unit_size) | |
7659 | { | |
7660 | i >>= booth_unit_size; | |
d5a0a47b | 7661 | cost++; |
9b66ebb1 PB |
7662 | } |
7663 | ||
d5a0a47b RE |
7664 | *total = COSTS_N_INSNS (cost); |
7665 | *total += rtx_cost (XEXP (x, 0), code, speed); | |
9b66ebb1 PB |
7666 | return true; |
7667 | } | |
7668 | ||
d5a0a47b RE |
7669 | *total = COSTS_N_INSNS (20); |
7670 | return false; | |
f676971a | 7671 | |
9b66ebb1 | 7672 | default: |
d5a0a47b | 7673 | return arm_rtx_costs_1 (x, outer_code, total, speed);; |
9b66ebb1 | 7674 | } |
3c50106f RH |
7675 | } |
7676 | ||
9b66ebb1 PB |
7677 | |
7678 | /* RTX cost for cores with a fast multiply unit (M variants). */ | |
7679 | ||
7680 | static bool | |
d5a0a47b RE |
7681 | arm_fastmul_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code, |
7682 | int *total, bool speed) | |
9b66ebb1 PB |
7683 | { |
7684 | enum machine_mode mode = GET_MODE (x); | |
7685 | ||
5b3e6663 | 7686 | if (TARGET_THUMB1) |
9b66ebb1 | 7687 | { |
5b3e6663 | 7688 | *total = thumb1_rtx_costs (x, code, outer_code); |
9b66ebb1 PB |
7689 | return true; |
7690 | } | |
f676971a | 7691 | |
5b3e6663 | 7692 | /* ??? should thumb2 use different costs? */ |
9b66ebb1 PB |
7693 | switch (code) |
7694 | { | |
7695 | case MULT: | |
7696 | /* There is no point basing this on the tuning, since it is always the | |
7697 | fast variant if it exists at all. */ | |
7698 | if (mode == DImode | |
7699 | && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1))) | |
7700 | && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND | |
7701 | || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)) | |
7702 | { | |
d5a0a47b RE |
7703 | *total = COSTS_N_INSNS(2); |
7704 | return false; | |
9b66ebb1 | 7705 | } |
f676971a | 7706 | |
9b66ebb1 | 7707 | |
d5a0a47b | 7708 | if (mode == DImode) |
9b66ebb1 | 7709 | { |
d5a0a47b RE |
7710 | *total = COSTS_N_INSNS (5); |
7711 | return false; | |
9b66ebb1 PB |
7712 | } |
7713 | ||
7714 | if (GET_CODE (XEXP (x, 1)) == CONST_INT) | |
7715 | { | |
7716 | unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1)) | |
7717 | & (unsigned HOST_WIDE_INT) 0xffffffff); | |
7718 | int cost, const_ok = const_ok_for_arm (i); | |
7719 | int j, booth_unit_size; | |
7720 | ||
f676971a | 7721 | /* Tune as appropriate. */ |
9b66ebb1 PB |
7722 | cost = const_ok ? 4 : 8; |
7723 | booth_unit_size = 8; | |
7724 | for (j = 0; i && j < 32; j += booth_unit_size) | |
7725 | { | |
7726 | i >>= booth_unit_size; | |
d5a0a47b | 7727 | cost++; |
9b66ebb1 PB |
7728 | } |
7729 | ||
d5a0a47b RE |
7730 | *total = COSTS_N_INSNS(cost); |
7731 | return false; | |
9b66ebb1 PB |
7732 | } |
7733 | ||
d5a0a47b RE |
7734 | if (mode == SImode) |
7735 | { | |
7736 | *total = COSTS_N_INSNS (4); | |
7737 | return false; | |
7738 | } | |
7739 | ||
7740 | if (GET_MODE_CLASS (mode) == MODE_FLOAT) | |
7741 | { | |
e0dc3601 PB |
7742 | if (TARGET_HARD_FLOAT |
7743 | && (mode == SFmode | |
7744 | || (mode == DFmode && !TARGET_VFP_SINGLE))) | |
d5a0a47b RE |
7745 | { |
7746 | *total = COSTS_N_INSNS (1); | |
7747 | return false; | |
7748 | } | |
7749 | } | |
7750 | ||
7751 | /* Requires a lib call */ | |
7752 | *total = COSTS_N_INSNS (20); | |
7753 | return false; | |
f676971a | 7754 | |
9b66ebb1 | 7755 | default: |
d5a0a47b | 7756 | return arm_rtx_costs_1 (x, outer_code, total, speed); |
9b66ebb1 PB |
7757 | } |
7758 | } | |
7759 | ||
7760 | ||
5b3e6663 PB |
7761 | /* RTX cost for XScale CPUs. Thumb-2 is not supported on any xscale cores, |
7762 | so it can be ignored. */ | |
9b66ebb1 PB |
7763 | |
7764 | static bool | |
1b78f575 RE |
7765 | arm_xscale_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code, |
7766 | int *total, bool speed) | |
9b66ebb1 PB |
7767 | { |
7768 | enum machine_mode mode = GET_MODE (x); | |
7769 | ||
7770 | if (TARGET_THUMB) | |
7771 | { | |
5b3e6663 | 7772 | *total = thumb1_rtx_costs (x, code, outer_code); |
9b66ebb1 PB |
7773 | return true; |
7774 | } | |
f676971a | 7775 | |
9b66ebb1 PB |
7776 | switch (code) |
7777 | { | |
d5a0a47b RE |
7778 | case COMPARE: |
7779 | if (GET_CODE (XEXP (x, 0)) != MULT) | |
7780 | return arm_rtx_costs_1 (x, outer_code, total, speed); | |
7781 | ||
7782 | /* A COMPARE of a MULT is slow on XScale; the muls instruction | |
7783 | will stall until the multiplication is complete. */ | |
7784 | *total = COSTS_N_INSNS (3); | |
7785 | return false; | |
7786 | ||
9b66ebb1 PB |
7787 | case MULT: |
7788 | /* There is no point basing this on the tuning, since it is always the | |
7789 | fast variant if it exists at all. */ | |
7790 | if (mode == DImode | |
7791 | && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1))) | |
7792 | && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND | |
7793 | || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)) | |
7794 | { | |
d5a0a47b RE |
7795 | *total = COSTS_N_INSNS (2); |
7796 | return false; | |
9b66ebb1 | 7797 | } |
f676971a | 7798 | |
9b66ebb1 | 7799 | |
d5a0a47b | 7800 | if (mode == DImode) |
9b66ebb1 | 7801 | { |
d5a0a47b RE |
7802 | *total = COSTS_N_INSNS (5); |
7803 | return false; | |
9b66ebb1 PB |
7804 | } |
7805 | ||
7806 | if (GET_CODE (XEXP (x, 1)) == CONST_INT) | |
7807 | { | |
d5a0a47b RE |
7808 | /* If operand 1 is a constant we can more accurately |
7809 | calculate the cost of the multiply. The multiplier can | |
7810 | retire 15 bits on the first cycle and a further 12 on the | |
7811 | second. We do, of course, have to load the constant into | |
7812 | a register first. */ | |
7813 | unsigned HOST_WIDE_INT i = INTVAL (XEXP (x, 1)); | |
7814 | /* There's a general overhead of one cycle. */ | |
7815 | int cost = 1; | |
9b66ebb1 PB |
7816 | unsigned HOST_WIDE_INT masked_const; |
7817 | ||
d5a0a47b RE |
7818 | if (i & 0x80000000) |
7819 | i = ~i; | |
7820 | ||
7821 | i &= (unsigned HOST_WIDE_INT) 0xffffffff; | |
7822 | ||
9b66ebb1 | 7823 | masked_const = i & 0xffff8000; |
d5a0a47b | 7824 | if (masked_const != 0) |
9b66ebb1 | 7825 | { |
d5a0a47b | 7826 | cost++; |
9b66ebb1 | 7827 | masked_const = i & 0xf8000000; |
d5a0a47b RE |
7828 | if (masked_const != 0) |
7829 | cost++; | |
9b66ebb1 | 7830 | } |
d5a0a47b RE |
7831 | *total = COSTS_N_INSNS (cost); |
7832 | return false; | |
9b66ebb1 PB |
7833 | } |
7834 | ||
d5a0a47b RE |
7835 | if (mode == SImode) |
7836 | { | |
7837 | *total = COSTS_N_INSNS (3); | |
7838 | return false; | |
7839 | } | |
f676971a | 7840 | |
d5a0a47b RE |
7841 | /* Requires a lib call */ |
7842 | *total = COSTS_N_INSNS (20); | |
7843 | return false; | |
06d5588c | 7844 | |
9b66ebb1 | 7845 | default: |
d5a0a47b | 7846 | return arm_rtx_costs_1 (x, outer_code, total, speed); |
9b66ebb1 PB |
7847 | } |
7848 | } | |
7849 | ||
7850 | ||
7851 | /* RTX costs for 9e (and later) cores. */ | |
7852 | ||
7853 | static bool | |
d5a0a47b RE |
7854 | arm_9e_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code, |
7855 | int *total, bool speed) | |
9b66ebb1 PB |
7856 | { |
7857 | enum machine_mode mode = GET_MODE (x); | |
f676971a | 7858 | |
5b3e6663 | 7859 | if (TARGET_THUMB1) |
9b66ebb1 PB |
7860 | { |
7861 | switch (code) | |
7862 | { | |
7863 | case MULT: | |
7864 | *total = COSTS_N_INSNS (3); | |
7865 | return true; | |
f676971a | 7866 | |
9b66ebb1 | 7867 | default: |
5b3e6663 | 7868 | *total = thumb1_rtx_costs (x, code, outer_code); |
9b66ebb1 PB |
7869 | return true; |
7870 | } | |
7871 | } | |
f676971a | 7872 | |
9b66ebb1 PB |
7873 | switch (code) |
7874 | { | |
7875 | case MULT: | |
7876 | /* There is no point basing this on the tuning, since it is always the | |
7877 | fast variant if it exists at all. */ | |
7878 | if (mode == DImode | |
7879 | && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1))) | |
7880 | && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND | |
7881 | || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)) | |
7882 | { | |
d5a0a47b RE |
7883 | *total = COSTS_N_INSNS (2); |
7884 | return false; | |
9b66ebb1 | 7885 | } |
f676971a | 7886 | |
9b66ebb1 | 7887 | |
9b66ebb1 PB |
7888 | if (mode == DImode) |
7889 | { | |
d5a0a47b RE |
7890 | *total = COSTS_N_INSNS (5); |
7891 | return false; | |
9b66ebb1 | 7892 | } |
d5a0a47b RE |
7893 | |
7894 | if (mode == SImode) | |
9b66ebb1 | 7895 | { |
d5a0a47b RE |
7896 | *total = COSTS_N_INSNS (2); |
7897 | return false; | |
9b66ebb1 PB |
7898 | } |
7899 | ||
d5a0a47b RE |
7900 | if (GET_MODE_CLASS (mode) == MODE_FLOAT) |
7901 | { | |
e0dc3601 PB |
7902 | if (TARGET_HARD_FLOAT |
7903 | && (mode == SFmode | |
7904 | || (mode == DFmode && !TARGET_VFP_SINGLE))) | |
d5a0a47b RE |
7905 | { |
7906 | *total = COSTS_N_INSNS (1); | |
7907 | return false; | |
7908 | } | |
7909 | } | |
9b66ebb1 | 7910 | |
d5a0a47b RE |
7911 | *total = COSTS_N_INSNS (20); |
7912 | return false; | |
f676971a | 7913 | |
9b66ebb1 | 7914 | default: |
d5a0a47b | 7915 | return arm_rtx_costs_1 (x, outer_code, total, speed); |
9b66ebb1 PB |
7916 | } |
7917 | } | |
dcefdf67 RH |
7918 | /* All address computations that can be done are free, but rtx cost returns |
7919 | the same for practically all of them. So we weight the different types | |
7920 | of address here in the order (most pref first): | |
d6b4baa4 | 7921 | PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */ |
d2b6eb76 ZW |
7922 | static inline int |
7923 | arm_arm_address_cost (rtx x) | |
7924 | { | |
7925 | enum rtx_code c = GET_CODE (x); | |
7926 | ||
7927 | if (c == PRE_INC || c == PRE_DEC || c == POST_INC || c == POST_DEC) | |
7928 | return 0; | |
7929 | if (c == MEM || c == LABEL_REF || c == SYMBOL_REF) | |
7930 | return 10; | |
7931 | ||
17eb4921 | 7932 | if (c == PLUS) |
d2b6eb76 | 7933 | { |
17eb4921 | 7934 | if (GET_CODE (XEXP (x, 1)) == CONST_INT) |
d2b6eb76 ZW |
7935 | return 2; |
7936 | ||
ec8e098d | 7937 | if (ARITHMETIC_P (XEXP (x, 0)) || ARITHMETIC_P (XEXP (x, 1))) |
d2b6eb76 ZW |
7938 | return 3; |
7939 | ||
7940 | return 4; | |
7941 | } | |
7942 | ||
7943 | return 6; | |
7944 | } | |
7945 | ||
7946 | static inline int | |
7947 | arm_thumb_address_cost (rtx x) | |
7948 | { | |
7949 | enum rtx_code c = GET_CODE (x); | |
7950 | ||
7951 | if (c == REG) | |
7952 | return 1; | |
7953 | if (c == PLUS | |
7954 | && GET_CODE (XEXP (x, 0)) == REG | |
7955 | && GET_CODE (XEXP (x, 1)) == CONST_INT) | |
7956 | return 1; | |
7957 | ||
7958 | return 2; | |
7959 | } | |
7960 | ||
dcefdf67 | 7961 | static int |
f40751dd | 7962 | arm_address_cost (rtx x, bool speed ATTRIBUTE_UNUSED) |
dcefdf67 | 7963 | { |
5b3e6663 | 7964 | return TARGET_32BIT ? arm_arm_address_cost (x) : arm_thumb_address_cost (x); |
dcefdf67 | 7965 | } |
906668bb | 7966 | |
b0c13111 RR |
7967 | /* Adjust cost hook for XScale. */ |
7968 | static bool | |
7969 | xscale_sched_adjust_cost (rtx insn, rtx link, rtx dep, int * cost) | |
7970 | { | |
d19fb8e3 NC |
7971 | /* Some true dependencies can have a higher cost depending |
7972 | on precisely how certain input operands are used. */ | |
b0c13111 | 7973 | if (REG_NOTE_KIND(link) == 0 |
eda833e3 BE |
7974 | && recog_memoized (insn) >= 0 |
7975 | && recog_memoized (dep) >= 0) | |
d19fb8e3 NC |
7976 | { |
7977 | int shift_opnum = get_attr_shift (insn); | |
7978 | enum attr_type attr_type = get_attr_type (dep); | |
7979 | ||
7980 | /* If nonzero, SHIFT_OPNUM contains the operand number of a shifted | |
7981 | operand for INSN. If we have a shifted input operand and the | |
7982 | instruction we depend on is another ALU instruction, then we may | |
7983 | have to account for an additional stall. */ | |
9b66ebb1 PB |
7984 | if (shift_opnum != 0 |
7985 | && (attr_type == TYPE_ALU_SHIFT || attr_type == TYPE_ALU_SHIFT_REG)) | |
d19fb8e3 NC |
7986 | { |
7987 | rtx shifted_operand; | |
7988 | int opno; | |
f676971a | 7989 | |
d19fb8e3 NC |
7990 | /* Get the shifted operand. */ |
7991 | extract_insn (insn); | |
7992 | shifted_operand = recog_data.operand[shift_opnum]; | |
7993 | ||
7994 | /* Iterate over all the operands in DEP. If we write an operand | |
7995 | that overlaps with SHIFTED_OPERAND, then we have increase the | |
7996 | cost of this dependency. */ | |
7997 | extract_insn (dep); | |
7998 | preprocess_constraints (); | |
7999 | for (opno = 0; opno < recog_data.n_operands; opno++) | |
8000 | { | |
8001 | /* We can ignore strict inputs. */ | |
8002 | if (recog_data.operand_type[opno] == OP_IN) | |
8003 | continue; | |
8004 | ||
8005 | if (reg_overlap_mentioned_p (recog_data.operand[opno], | |
8006 | shifted_operand)) | |
b0c13111 RR |
8007 | { |
8008 | *cost = 2; | |
8009 | return false; | |
8010 | } | |
d19fb8e3 NC |
8011 | } |
8012 | } | |
8013 | } | |
b0c13111 RR |
8014 | return true; |
8015 | } | |
8016 | ||
8017 | /* Adjust cost hook for Cortex A9. */ | |
8018 | static bool | |
8019 | cortex_a9_sched_adjust_cost (rtx insn, rtx link, rtx dep, int * cost) | |
8020 | { | |
8021 | switch (REG_NOTE_KIND (link)) | |
8022 | { | |
8023 | case REG_DEP_ANTI: | |
8024 | *cost = 0; | |
8025 | return false; | |
8026 | ||
8027 | case REG_DEP_TRUE: | |
8028 | case REG_DEP_OUTPUT: | |
8029 | if (recog_memoized (insn) >= 0 | |
8030 | && recog_memoized (dep) >= 0) | |
8031 | { | |
8032 | if (GET_CODE (PATTERN (insn)) == SET) | |
8033 | { | |
8034 | if (GET_MODE_CLASS | |
8035 | (GET_MODE (SET_DEST (PATTERN (insn)))) == MODE_FLOAT | |
8036 | || GET_MODE_CLASS | |
8037 | (GET_MODE (SET_SRC (PATTERN (insn)))) == MODE_FLOAT) | |
8038 | { | |
8039 | enum attr_type attr_type_insn = get_attr_type (insn); | |
8040 | enum attr_type attr_type_dep = get_attr_type (dep); | |
8041 | ||
8042 | /* By default all dependencies of the form | |
8043 | s0 = s0 <op> s1 | |
8044 | s0 = s0 <op> s2 | |
8045 | have an extra latency of 1 cycle because | |
8046 | of the input and output dependency in this | |
8047 | case. However this gets modeled as an true | |
8048 | dependency and hence all these checks. */ | |
8049 | if (REG_P (SET_DEST (PATTERN (insn))) | |
8050 | && REG_P (SET_DEST (PATTERN (dep))) | |
8051 | && reg_overlap_mentioned_p (SET_DEST (PATTERN (insn)), | |
8052 | SET_DEST (PATTERN (dep)))) | |
8053 | { | |
8054 | /* FMACS is a special case where the dependant | |
8055 | instruction can be issued 3 cycles before | |
8056 | the normal latency in case of an output | |
8057 | dependency. */ | |
8058 | if ((attr_type_insn == TYPE_FMACS | |
8059 | || attr_type_insn == TYPE_FMACD) | |
8060 | && (attr_type_dep == TYPE_FMACS | |
8061 | || attr_type_dep == TYPE_FMACD)) | |
8062 | { | |
8063 | if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT) | |
8064 | *cost = insn_default_latency (dep) - 3; | |
8065 | else | |
8066 | *cost = insn_default_latency (dep); | |
8067 | return false; | |
8068 | } | |
8069 | else | |
8070 | { | |
8071 | if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT) | |
8072 | *cost = insn_default_latency (dep) + 1; | |
8073 | else | |
8074 | *cost = insn_default_latency (dep); | |
8075 | } | |
8076 | return false; | |
8077 | } | |
8078 | } | |
8079 | } | |
8080 | } | |
8081 | break; | |
8082 | ||
8083 | default: | |
8084 | gcc_unreachable (); | |
8085 | } | |
8086 | ||
8087 | return true; | |
8088 | } | |
8089 | ||
c02a5ccb SL |
8090 | /* Adjust cost hook for FA726TE. */ |
8091 | static bool | |
8092 | fa726te_sched_adjust_cost (rtx insn, rtx link, rtx dep, int * cost) | |
8093 | { | |
8094 | /* For FA726TE, true dependency on CPSR (i.e. set cond followed by predicated) | |
8095 | have penalty of 3. */ | |
8096 | if (REG_NOTE_KIND (link) == REG_DEP_TRUE | |
8097 | && recog_memoized (insn) >= 0 | |
8098 | && recog_memoized (dep) >= 0 | |
8099 | && get_attr_conds (dep) == CONDS_SET) | |
8100 | { | |
8101 | /* Use of carry (e.g. 64-bit arithmetic) in ALU: 3-cycle latency. */ | |
8102 | if (get_attr_conds (insn) == CONDS_USE | |
8103 | && get_attr_type (insn) != TYPE_BRANCH) | |
8104 | { | |
8105 | *cost = 3; | |
8106 | return false; | |
8107 | } | |
8108 | ||
8109 | if (GET_CODE (PATTERN (insn)) == COND_EXEC | |
8110 | || get_attr_conds (insn) == CONDS_USE) | |
8111 | { | |
8112 | *cost = 0; | |
8113 | return false; | |
8114 | } | |
8115 | } | |
8116 | ||
8117 | return true; | |
8118 | } | |
8119 | ||
b0c13111 RR |
8120 | /* This function implements the target macro TARGET_SCHED_ADJUST_COST. |
8121 | It corrects the value of COST based on the relationship between | |
8122 | INSN and DEP through the dependence LINK. It returns the new | |
8123 | value. There is a per-core adjust_cost hook to adjust scheduler costs | |
8124 | and the per-core hook can choose to completely override the generic | |
8125 | adjust_cost function. Only put bits of code into arm_adjust_cost that | |
8126 | are common across all cores. */ | |
8127 | static int | |
8128 | arm_adjust_cost (rtx insn, rtx link, rtx dep, int cost) | |
8129 | { | |
8130 | rtx i_pat, d_pat; | |
8131 | ||
8132 | /* When generating Thumb-1 code, we want to place flag-setting operations | |
8133 | close to a conditional branch which depends on them, so that we can | |
8134 | omit the comparison. */ | |
8135 | if (TARGET_THUMB1 | |
8136 | && REG_NOTE_KIND (link) == 0 | |
8137 | && recog_memoized (insn) == CODE_FOR_cbranchsi4_insn | |
8138 | && recog_memoized (dep) >= 0 | |
8139 | && get_attr_conds (dep) == CONDS_SET) | |
8140 | return 0; | |
8141 | ||
8142 | if (current_tune->sched_adjust_cost != NULL) | |
8143 | { | |
8144 | if (!current_tune->sched_adjust_cost (insn, link, dep, &cost)) | |
8145 | return cost; | |
8146 | } | |
d19fb8e3 | 8147 | |
6354dc9b | 8148 | /* XXX This is not strictly true for the FPA. */ |
d5b7b3ae RE |
8149 | if (REG_NOTE_KIND (link) == REG_DEP_ANTI |
8150 | || REG_NOTE_KIND (link) == REG_DEP_OUTPUT) | |
b36ba79f RE |
8151 | return 0; |
8152 | ||
d5b7b3ae RE |
8153 | /* Call insns don't incur a stall, even if they follow a load. */ |
8154 | if (REG_NOTE_KIND (link) == 0 | |
8155 | && GET_CODE (insn) == CALL_INSN) | |
8156 | return 1; | |
8157 | ||
32de079a RE |
8158 | if ((i_pat = single_set (insn)) != NULL |
8159 | && GET_CODE (SET_SRC (i_pat)) == MEM | |
8160 | && (d_pat = single_set (dep)) != NULL | |
8161 | && GET_CODE (SET_DEST (d_pat)) == MEM) | |
8162 | { | |
48f6efae | 8163 | rtx src_mem = XEXP (SET_SRC (i_pat), 0); |
32de079a RE |
8164 | /* This is a load after a store, there is no conflict if the load reads |
8165 | from a cached area. Assume that loads from the stack, and from the | |
f676971a | 8166 | constant pool are cached, and that others will miss. This is a |
6354dc9b | 8167 | hack. */ |
f676971a | 8168 | |
b0c13111 RR |
8169 | if ((GET_CODE (src_mem) == SYMBOL_REF |
8170 | && CONSTANT_POOL_ADDRESS_P (src_mem)) | |
48f6efae NC |
8171 | || reg_mentioned_p (stack_pointer_rtx, src_mem) |
8172 | || reg_mentioned_p (frame_pointer_rtx, src_mem) | |
8173 | || reg_mentioned_p (hard_frame_pointer_rtx, src_mem)) | |
949d79eb | 8174 | return 1; |
32de079a RE |
8175 | } |
8176 | ||
8177 | return cost; | |
8178 | } | |
8179 | ||
9b66ebb1 | 8180 | static int fp_consts_inited = 0; |
ff9940b0 | 8181 | |
9b66ebb1 PB |
8182 | /* Only zero is valid for VFP. Other values are also valid for FPA. */ |
8183 | static const char * const strings_fp[8] = | |
62b10bbc | 8184 | { |
2b835d68 RE |
8185 | "0", "1", "2", "3", |
8186 | "4", "5", "0.5", "10" | |
8187 | }; | |
ff9940b0 | 8188 | |
9b66ebb1 | 8189 | static REAL_VALUE_TYPE values_fp[8]; |
ff9940b0 RE |
8190 | |
8191 | static void | |
9b66ebb1 | 8192 | init_fp_table (void) |
ff9940b0 RE |
8193 | { |
8194 | int i; | |
8195 | REAL_VALUE_TYPE r; | |
8196 | ||
9b66ebb1 PB |
8197 | if (TARGET_VFP) |
8198 | fp_consts_inited = 1; | |
8199 | else | |
8200 | fp_consts_inited = 8; | |
8201 | ||
8202 | for (i = 0; i < fp_consts_inited; i++) | |
ff9940b0 | 8203 | { |
9b66ebb1 PB |
8204 | r = REAL_VALUE_ATOF (strings_fp[i], DFmode); |
8205 | values_fp[i] = r; | |
ff9940b0 | 8206 | } |
ff9940b0 RE |
8207 | } |
8208 | ||
9b66ebb1 | 8209 | /* Return TRUE if rtx X is a valid immediate FP constant. */ |
cce8749e | 8210 | int |
9b66ebb1 | 8211 | arm_const_double_rtx (rtx x) |
cce8749e | 8212 | { |
ff9940b0 RE |
8213 | REAL_VALUE_TYPE r; |
8214 | int i; | |
f676971a | 8215 | |
9b66ebb1 PB |
8216 | if (!fp_consts_inited) |
8217 | init_fp_table (); | |
f676971a | 8218 | |
ff9940b0 RE |
8219 | REAL_VALUE_FROM_CONST_DOUBLE (r, x); |
8220 | if (REAL_VALUE_MINUS_ZERO (r)) | |
8221 | return 0; | |
f3bb6135 | 8222 | |
9b66ebb1 PB |
8223 | for (i = 0; i < fp_consts_inited; i++) |
8224 | if (REAL_VALUES_EQUAL (r, values_fp[i])) | |
ff9940b0 | 8225 | return 1; |
f3bb6135 | 8226 | |
ff9940b0 | 8227 | return 0; |
f3bb6135 | 8228 | } |
ff9940b0 | 8229 | |
3b684012 | 8230 | /* Return TRUE if rtx X is a valid immediate FPA constant. */ |
ff9940b0 | 8231 | int |
e32bac5b | 8232 | neg_const_double_rtx_ok_for_fpa (rtx x) |
ff9940b0 RE |
8233 | { |
8234 | REAL_VALUE_TYPE r; | |
8235 | int i; | |
f676971a | 8236 | |
9b66ebb1 PB |
8237 | if (!fp_consts_inited) |
8238 | init_fp_table (); | |
f676971a | 8239 | |
ff9940b0 | 8240 | REAL_VALUE_FROM_CONST_DOUBLE (r, x); |
d49b6e1e | 8241 | r = real_value_negate (&r); |
ff9940b0 RE |
8242 | if (REAL_VALUE_MINUS_ZERO (r)) |
8243 | return 0; | |
f3bb6135 | 8244 | |
ff9940b0 | 8245 | for (i = 0; i < 8; i++) |
9b66ebb1 | 8246 | if (REAL_VALUES_EQUAL (r, values_fp[i])) |
ff9940b0 | 8247 | return 1; |
f3bb6135 | 8248 | |
ff9940b0 | 8249 | return 0; |
f3bb6135 | 8250 | } |
f1adb0a9 JB |
8251 | |
8252 | ||
8253 | /* VFPv3 has a fairly wide range of representable immediates, formed from | |
8254 | "quarter-precision" floating-point values. These can be evaluated using this | |
8255 | formula (with ^ for exponentiation): | |
8256 | ||
8257 | -1^s * n * 2^-r | |
8258 | ||
8259 | Where 's' is a sign bit (0/1), 'n' and 'r' are integers such that | |
8260 | 16 <= n <= 31 and 0 <= r <= 7. | |
8261 | ||
8262 | These values are mapped onto an 8-bit integer ABCDEFGH s.t. | |
8263 | ||
8264 | - A (most-significant) is the sign bit. | |
8265 | - BCD are the exponent (encoded as r XOR 3). | |
8266 | - EFGH are the mantissa (encoded as n - 16). | |
8267 | */ | |
8268 | ||
8269 | /* Return an integer index for a VFPv3 immediate operand X suitable for the | |
8270 | fconst[sd] instruction, or -1 if X isn't suitable. */ | |
8271 | static int | |
8272 | vfp3_const_double_index (rtx x) | |
8273 | { | |
8274 | REAL_VALUE_TYPE r, m; | |
8275 | int sign, exponent; | |
8276 | unsigned HOST_WIDE_INT mantissa, mant_hi; | |
8277 | unsigned HOST_WIDE_INT mask; | |
8e39e9af | 8278 | HOST_WIDE_INT m1, m2; |
f1adb0a9 JB |
8279 | int point_pos = 2 * HOST_BITS_PER_WIDE_INT - 1; |
8280 | ||
8281 | if (!TARGET_VFP3 || GET_CODE (x) != CONST_DOUBLE) | |
8282 | return -1; | |
8283 | ||
8284 | REAL_VALUE_FROM_CONST_DOUBLE (r, x); | |
8285 | ||
8286 | /* We can't represent these things, so detect them first. */ | |
8287 | if (REAL_VALUE_ISINF (r) || REAL_VALUE_ISNAN (r) || REAL_VALUE_MINUS_ZERO (r)) | |
8288 | return -1; | |
8289 | ||
8290 | /* Extract sign, exponent and mantissa. */ | |
8291 | sign = REAL_VALUE_NEGATIVE (r) ? 1 : 0; | |
d49b6e1e | 8292 | r = real_value_abs (&r); |
f1adb0a9 JB |
8293 | exponent = REAL_EXP (&r); |
8294 | /* For the mantissa, we expand into two HOST_WIDE_INTS, apart from the | |
8295 | highest (sign) bit, with a fixed binary point at bit point_pos. | |
8296 | WARNING: If there's ever a VFP version which uses more than 2 * H_W_I - 1 | |
8297 | bits for the mantissa, this may fail (low bits would be lost). */ | |
8298 | real_ldexp (&m, &r, point_pos - exponent); | |
8e39e9af RE |
8299 | REAL_VALUE_TO_INT (&m1, &m2, m); |
8300 | mantissa = m1; | |
8301 | mant_hi = m2; | |
f1adb0a9 JB |
8302 | |
8303 | /* If there are bits set in the low part of the mantissa, we can't | |
8304 | represent this value. */ | |
8305 | if (mantissa != 0) | |
8306 | return -1; | |
8307 | ||
8308 | /* Now make it so that mantissa contains the most-significant bits, and move | |
8309 | the point_pos to indicate that the least-significant bits have been | |
8310 | discarded. */ | |
8311 | point_pos -= HOST_BITS_PER_WIDE_INT; | |
8312 | mantissa = mant_hi; | |
8313 | ||
8314 | /* We can permit four significant bits of mantissa only, plus a high bit | |
8315 | which is always 1. */ | |
8316 | mask = ((unsigned HOST_WIDE_INT)1 << (point_pos - 5)) - 1; | |
8317 | if ((mantissa & mask) != 0) | |
8318 | return -1; | |
8319 | ||
8320 | /* Now we know the mantissa is in range, chop off the unneeded bits. */ | |
8321 | mantissa >>= point_pos - 5; | |
8322 | ||
8323 | /* The mantissa may be zero. Disallow that case. (It's possible to load the | |
8324 | floating-point immediate zero with Neon using an integer-zero load, but | |
8325 | that case is handled elsewhere.) */ | |
8326 | if (mantissa == 0) | |
8327 | return -1; | |
8328 | ||
8329 | gcc_assert (mantissa >= 16 && mantissa <= 31); | |
8330 | ||
8331 | /* The value of 5 here would be 4 if GCC used IEEE754-like encoding (where | |
6ed3da00 KH |
8332 | normalized significands are in the range [1, 2). (Our mantissa is shifted |
8333 | left 4 places at this point relative to normalized IEEE754 values). GCC | |
f1adb0a9 JB |
8334 | internally uses [0.5, 1) (see real.c), so the exponent returned from |
8335 | REAL_EXP must be altered. */ | |
8336 | exponent = 5 - exponent; | |
8337 | ||
8338 | if (exponent < 0 || exponent > 7) | |
8339 | return -1; | |
8340 | ||
8341 | /* Sign, mantissa and exponent are now in the correct form to plug into the | |
15dc95cb | 8342 | formula described in the comment above. */ |
f1adb0a9 JB |
8343 | return (sign << 7) | ((exponent ^ 3) << 4) | (mantissa - 16); |
8344 | } | |
8345 | ||
8346 | /* Return TRUE if rtx X is a valid immediate VFPv3 constant. */ | |
8347 | int | |
8348 | vfp3_const_double_rtx (rtx x) | |
8349 | { | |
8350 | if (!TARGET_VFP3) | |
8351 | return 0; | |
8352 | ||
8353 | return vfp3_const_double_index (x) != -1; | |
8354 | } | |
8355 | ||
88f77cba JB |
8356 | /* Recognize immediates which can be used in various Neon instructions. Legal |
8357 | immediates are described by the following table (for VMVN variants, the | |
8358 | bitwise inverse of the constant shown is recognized. In either case, VMOV | |
8359 | is output and the correct instruction to use for a given constant is chosen | |
8360 | by the assembler). The constant shown is replicated across all elements of | |
8361 | the destination vector. | |
8362 | ||
8363 | insn elems variant constant (binary) | |
8364 | ---- ----- ------- ----------------- | |
8365 | vmov i32 0 00000000 00000000 00000000 abcdefgh | |
8366 | vmov i32 1 00000000 00000000 abcdefgh 00000000 | |
8367 | vmov i32 2 00000000 abcdefgh 00000000 00000000 | |
8368 | vmov i32 3 abcdefgh 00000000 00000000 00000000 | |
8369 | vmov i16 4 00000000 abcdefgh | |
8370 | vmov i16 5 abcdefgh 00000000 | |
8371 | vmvn i32 6 00000000 00000000 00000000 abcdefgh | |
8372 | vmvn i32 7 00000000 00000000 abcdefgh 00000000 | |
8373 | vmvn i32 8 00000000 abcdefgh 00000000 00000000 | |
8374 | vmvn i32 9 abcdefgh 00000000 00000000 00000000 | |
8375 | vmvn i16 10 00000000 abcdefgh | |
8376 | vmvn i16 11 abcdefgh 00000000 | |
8377 | vmov i32 12 00000000 00000000 abcdefgh 11111111 | |
8378 | vmvn i32 13 00000000 00000000 abcdefgh 11111111 | |
8379 | vmov i32 14 00000000 abcdefgh 11111111 11111111 | |
8380 | vmvn i32 15 00000000 abcdefgh 11111111 11111111 | |
8381 | vmov i8 16 abcdefgh | |
8382 | vmov i64 17 aaaaaaaa bbbbbbbb cccccccc dddddddd | |
8383 | eeeeeeee ffffffff gggggggg hhhhhhhh | |
8384 | vmov f32 18 aBbbbbbc defgh000 00000000 00000000 | |
8385 | ||
8386 | For case 18, B = !b. Representable values are exactly those accepted by | |
8387 | vfp3_const_double_index, but are output as floating-point numbers rather | |
8388 | than indices. | |
8389 | ||
8390 | Variants 0-5 (inclusive) may also be used as immediates for the second | |
8391 | operand of VORR/VBIC instructions. | |
8392 | ||
8393 | The INVERSE argument causes the bitwise inverse of the given operand to be | |
8394 | recognized instead (used for recognizing legal immediates for the VAND/VORN | |
8395 | pseudo-instructions). If INVERSE is true, the value placed in *MODCONST is | |
8396 | *not* inverted (i.e. the pseudo-instruction forms vand/vorn should still be | |
8397 | output, rather than the real insns vbic/vorr). | |
8398 | ||
8399 | INVERSE makes no difference to the recognition of float vectors. | |
8400 | ||
8401 | The return value is the variant of immediate as shown in the above table, or | |
8402 | -1 if the given value doesn't match any of the listed patterns. | |
8403 | */ | |
8404 | static int | |
8405 | neon_valid_immediate (rtx op, enum machine_mode mode, int inverse, | |
8406 | rtx *modconst, int *elementwidth) | |
8407 | { | |
8408 | #define CHECK(STRIDE, ELSIZE, CLASS, TEST) \ | |
8409 | matches = 1; \ | |
8410 | for (i = 0; i < idx; i += (STRIDE)) \ | |
8411 | if (!(TEST)) \ | |
8412 | matches = 0; \ | |
8413 | if (matches) \ | |
8414 | { \ | |
8415 | immtype = (CLASS); \ | |
8416 | elsize = (ELSIZE); \ | |
8417 | break; \ | |
8418 | } | |
8419 | ||
ff128632 | 8420 | unsigned int i, elsize = 0, idx = 0, n_elts = CONST_VECTOR_NUNITS (op); |
88f77cba JB |
8421 | unsigned int innersize = GET_MODE_SIZE (GET_MODE_INNER (mode)); |
8422 | unsigned char bytes[16]; | |
8423 | int immtype = -1, matches; | |
8424 | unsigned int invmask = inverse ? 0xff : 0; | |
8425 | ||
8426 | /* Vectors of float constants. */ | |
8427 | if (GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT) | |
8428 | { | |
8429 | rtx el0 = CONST_VECTOR_ELT (op, 0); | |
8430 | REAL_VALUE_TYPE r0; | |
8431 | ||
8432 | if (!vfp3_const_double_rtx (el0)) | |
8433 | return -1; | |
8434 | ||
8435 | REAL_VALUE_FROM_CONST_DOUBLE (r0, el0); | |
8436 | ||
8437 | for (i = 1; i < n_elts; i++) | |
8438 | { | |
8439 | rtx elt = CONST_VECTOR_ELT (op, i); | |
8440 | REAL_VALUE_TYPE re; | |
8441 | ||
8442 | REAL_VALUE_FROM_CONST_DOUBLE (re, elt); | |
8443 | ||
8444 | if (!REAL_VALUES_EQUAL (r0, re)) | |
8445 | return -1; | |
8446 | } | |
8447 | ||
8448 | if (modconst) | |
8449 | *modconst = CONST_VECTOR_ELT (op, 0); | |
8450 | ||
8451 | if (elementwidth) | |
8452 | *elementwidth = 0; | |
8453 | ||
8454 | return 18; | |
8455 | } | |
8456 | ||
8457 | /* Splat vector constant out into a byte vector. */ | |
8458 | for (i = 0; i < n_elts; i++) | |
8459 | { | |
8460 | rtx el = CONST_VECTOR_ELT (op, i); | |
8461 | unsigned HOST_WIDE_INT elpart; | |
8462 | unsigned int part, parts; | |
8463 | ||
8464 | if (GET_CODE (el) == CONST_INT) | |
8465 | { | |
8466 | elpart = INTVAL (el); | |
8467 | parts = 1; | |
8468 | } | |
8469 | else if (GET_CODE (el) == CONST_DOUBLE) | |
8470 | { | |
8471 | elpart = CONST_DOUBLE_LOW (el); | |
8472 | parts = 2; | |
8473 | } | |
8474 | else | |
8475 | gcc_unreachable (); | |
8476 | ||
8477 | for (part = 0; part < parts; part++) | |
8478 | { | |
8479 | unsigned int byte; | |
8480 | for (byte = 0; byte < innersize; byte++) | |
8481 | { | |
8482 | bytes[idx++] = (elpart & 0xff) ^ invmask; | |
8483 | elpart >>= BITS_PER_UNIT; | |
8484 | } | |
8485 | if (GET_CODE (el) == CONST_DOUBLE) | |
8486 | elpart = CONST_DOUBLE_HIGH (el); | |
8487 | } | |
8488 | } | |
8489 | ||
8490 | /* Sanity check. */ | |
8491 | gcc_assert (idx == GET_MODE_SIZE (mode)); | |
8492 | ||
8493 | do | |
8494 | { | |
8495 | CHECK (4, 32, 0, bytes[i] == bytes[0] && bytes[i + 1] == 0 | |
8496 | && bytes[i + 2] == 0 && bytes[i + 3] == 0); | |
8497 | ||
8498 | CHECK (4, 32, 1, bytes[i] == 0 && bytes[i + 1] == bytes[1] | |
8499 | && bytes[i + 2] == 0 && bytes[i + 3] == 0); | |
8500 | ||
8501 | CHECK (4, 32, 2, bytes[i] == 0 && bytes[i + 1] == 0 | |
8502 | && bytes[i + 2] == bytes[2] && bytes[i + 3] == 0); | |
8503 | ||
8504 | CHECK (4, 32, 3, bytes[i] == 0 && bytes[i + 1] == 0 | |
8505 | && bytes[i + 2] == 0 && bytes[i + 3] == bytes[3]); | |
8506 | ||
8507 | CHECK (2, 16, 4, bytes[i] == bytes[0] && bytes[i + 1] == 0); | |
8508 | ||
8509 | CHECK (2, 16, 5, bytes[i] == 0 && bytes[i + 1] == bytes[1]); | |
8510 | ||
8511 | CHECK (4, 32, 6, bytes[i] == bytes[0] && bytes[i + 1] == 0xff | |
8512 | && bytes[i + 2] == 0xff && bytes[i + 3] == 0xff); | |
8513 | ||
8514 | CHECK (4, 32, 7, bytes[i] == 0xff && bytes[i + 1] == bytes[1] | |
8515 | && bytes[i + 2] == 0xff && bytes[i + 3] == 0xff); | |
8516 | ||
8517 | CHECK (4, 32, 8, bytes[i] == 0xff && bytes[i + 1] == 0xff | |
8518 | && bytes[i + 2] == bytes[2] && bytes[i + 3] == 0xff); | |
8519 | ||
8520 | CHECK (4, 32, 9, bytes[i] == 0xff && bytes[i + 1] == 0xff | |
8521 | && bytes[i + 2] == 0xff && bytes[i + 3] == bytes[3]); | |
8522 | ||
8523 | CHECK (2, 16, 10, bytes[i] == bytes[0] && bytes[i + 1] == 0xff); | |
8524 | ||
8525 | CHECK (2, 16, 11, bytes[i] == 0xff && bytes[i + 1] == bytes[1]); | |
8526 | ||
8527 | CHECK (4, 32, 12, bytes[i] == 0xff && bytes[i + 1] == bytes[1] | |
8528 | && bytes[i + 2] == 0 && bytes[i + 3] == 0); | |
8529 | ||
8530 | CHECK (4, 32, 13, bytes[i] == 0 && bytes[i + 1] == bytes[1] | |
8531 | && bytes[i + 2] == 0xff && bytes[i + 3] == 0xff); | |
8532 | ||
8533 | CHECK (4, 32, 14, bytes[i] == 0xff && bytes[i + 1] == 0xff | |
8534 | && bytes[i + 2] == bytes[2] && bytes[i + 3] == 0); | |
8535 | ||
8536 | CHECK (4, 32, 15, bytes[i] == 0 && bytes[i + 1] == 0 | |
8537 | && bytes[i + 2] == bytes[2] && bytes[i + 3] == 0xff); | |
8538 | ||
8539 | CHECK (1, 8, 16, bytes[i] == bytes[0]); | |
8540 | ||
8541 | CHECK (1, 64, 17, (bytes[i] == 0 || bytes[i] == 0xff) | |
8542 | && bytes[i] == bytes[(i + 8) % idx]); | |
8543 | } | |
8544 | while (0); | |
8545 | ||
8546 | if (immtype == -1) | |
8547 | return -1; | |
8548 | ||
8549 | if (elementwidth) | |
8550 | *elementwidth = elsize; | |
8551 | ||
8552 | if (modconst) | |
8553 | { | |
8554 | unsigned HOST_WIDE_INT imm = 0; | |
8555 | ||
cea618ac | 8556 | /* Un-invert bytes of recognized vector, if necessary. */ |
88f77cba JB |
8557 | if (invmask != 0) |
8558 | for (i = 0; i < idx; i++) | |
8559 | bytes[i] ^= invmask; | |
8560 | ||
8561 | if (immtype == 17) | |
8562 | { | |
8563 | /* FIXME: Broken on 32-bit H_W_I hosts. */ | |
8564 | gcc_assert (sizeof (HOST_WIDE_INT) == 8); | |
8565 | ||
8566 | for (i = 0; i < 8; i++) | |
8567 | imm |= (unsigned HOST_WIDE_INT) (bytes[i] ? 0xff : 0) | |
8568 | << (i * BITS_PER_UNIT); | |
8569 | ||
8570 | *modconst = GEN_INT (imm); | |
8571 | } | |
8572 | else | |
8573 | { | |
8574 | unsigned HOST_WIDE_INT imm = 0; | |
8575 | ||
8576 | for (i = 0; i < elsize / BITS_PER_UNIT; i++) | |
8577 | imm |= (unsigned HOST_WIDE_INT) bytes[i] << (i * BITS_PER_UNIT); | |
8578 | ||
8579 | *modconst = GEN_INT (imm); | |
8580 | } | |
8581 | } | |
8582 | ||
8583 | return immtype; | |
8584 | #undef CHECK | |
8585 | } | |
8586 | ||
8587 | /* Return TRUE if rtx X is legal for use as either a Neon VMOV (or, implicitly, | |
8588 | VMVN) immediate. Write back width per element to *ELEMENTWIDTH (or zero for | |
8589 | float elements), and a modified constant (whatever should be output for a | |
8590 | VMOV) in *MODCONST. */ | |
8591 | ||
8592 | int | |
8593 | neon_immediate_valid_for_move (rtx op, enum machine_mode mode, | |
8594 | rtx *modconst, int *elementwidth) | |
8595 | { | |
8596 | rtx tmpconst; | |
8597 | int tmpwidth; | |
8598 | int retval = neon_valid_immediate (op, mode, 0, &tmpconst, &tmpwidth); | |
8599 | ||
8600 | if (retval == -1) | |
8601 | return 0; | |
8602 | ||
8603 | if (modconst) | |
8604 | *modconst = tmpconst; | |
8605 | ||
8606 | if (elementwidth) | |
8607 | *elementwidth = tmpwidth; | |
8608 | ||
8609 | return 1; | |
8610 | } | |
8611 | ||
8612 | /* Return TRUE if rtx X is legal for use in a VORR or VBIC instruction. If | |
8613 | the immediate is valid, write a constant suitable for using as an operand | |
8614 | to VORR/VBIC/VAND/VORN to *MODCONST and the corresponding element width to | |
8615 | *ELEMENTWIDTH. See neon_valid_immediate for description of INVERSE. */ | |
8616 | ||
8617 | int | |
8618 | neon_immediate_valid_for_logic (rtx op, enum machine_mode mode, int inverse, | |
8619 | rtx *modconst, int *elementwidth) | |
8620 | { | |
8621 | rtx tmpconst; | |
8622 | int tmpwidth; | |
8623 | int retval = neon_valid_immediate (op, mode, inverse, &tmpconst, &tmpwidth); | |
8624 | ||
8625 | if (retval < 0 || retval > 5) | |
8626 | return 0; | |
8627 | ||
8628 | if (modconst) | |
8629 | *modconst = tmpconst; | |
8630 | ||
8631 | if (elementwidth) | |
8632 | *elementwidth = tmpwidth; | |
8633 | ||
8634 | return 1; | |
8635 | } | |
8636 | ||
8637 | /* Return a string suitable for output of Neon immediate logic operation | |
8638 | MNEM. */ | |
8639 | ||
8640 | char * | |
8641 | neon_output_logic_immediate (const char *mnem, rtx *op2, enum machine_mode mode, | |
8642 | int inverse, int quad) | |
8643 | { | |
8644 | int width, is_valid; | |
8645 | static char templ[40]; | |
8646 | ||
8647 | is_valid = neon_immediate_valid_for_logic (*op2, mode, inverse, op2, &width); | |
8648 | ||
8649 | gcc_assert (is_valid != 0); | |
8650 | ||
8651 | if (quad) | |
8652 | sprintf (templ, "%s.i%d\t%%q0, %%2", mnem, width); | |
8653 | else | |
8654 | sprintf (templ, "%s.i%d\t%%P0, %%2", mnem, width); | |
8655 | ||
8656 | return templ; | |
8657 | } | |
8658 | ||
8659 | /* Output a sequence of pairwise operations to implement a reduction. | |
8660 | NOTE: We do "too much work" here, because pairwise operations work on two | |
8661 | registers-worth of operands in one go. Unfortunately we can't exploit those | |
8662 | extra calculations to do the full operation in fewer steps, I don't think. | |
8663 | Although all vector elements of the result but the first are ignored, we | |
8664 | actually calculate the same result in each of the elements. An alternative | |
8665 | such as initially loading a vector with zero to use as each of the second | |
8666 | operands would use up an additional register and take an extra instruction, | |
8667 | for no particular gain. */ | |
8668 | ||
8669 | void | |
8670 | neon_pairwise_reduce (rtx op0, rtx op1, enum machine_mode mode, | |
8671 | rtx (*reduc) (rtx, rtx, rtx)) | |
8672 | { | |
8673 | enum machine_mode inner = GET_MODE_INNER (mode); | |
8674 | unsigned int i, parts = GET_MODE_SIZE (mode) / GET_MODE_SIZE (inner); | |
8675 | rtx tmpsum = op1; | |
8676 | ||
8677 | for (i = parts / 2; i >= 1; i /= 2) | |
8678 | { | |
8679 | rtx dest = (i == 1) ? op0 : gen_reg_rtx (mode); | |
8680 | emit_insn (reduc (dest, tmpsum, tmpsum)); | |
8681 | tmpsum = dest; | |
8682 | } | |
8683 | } | |
8684 | ||
814a4c3b DJ |
8685 | /* If VALS is a vector constant that can be loaded into a register |
8686 | using VDUP, generate instructions to do so and return an RTX to | |
8687 | assign to the register. Otherwise return NULL_RTX. */ | |
8688 | ||
8689 | static rtx | |
8690 | neon_vdup_constant (rtx vals) | |
8691 | { | |
8692 | enum machine_mode mode = GET_MODE (vals); | |
8693 | enum machine_mode inner_mode = GET_MODE_INNER (mode); | |
8694 | int n_elts = GET_MODE_NUNITS (mode); | |
8695 | bool all_same = true; | |
8696 | rtx x; | |
8697 | int i; | |
8698 | ||
8699 | if (GET_CODE (vals) != CONST_VECTOR || GET_MODE_SIZE (inner_mode) > 4) | |
8700 | return NULL_RTX; | |
8701 | ||
8702 | for (i = 0; i < n_elts; ++i) | |
8703 | { | |
8704 | x = XVECEXP (vals, 0, i); | |
8705 | if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0))) | |
8706 | all_same = false; | |
8707 | } | |
8708 | ||
8709 | if (!all_same) | |
8710 | /* The elements are not all the same. We could handle repeating | |
8711 | patterns of a mode larger than INNER_MODE here (e.g. int8x8_t | |
8712 | {0, C, 0, C, 0, C, 0, C} which can be loaded using | |
8713 | vdup.i16). */ | |
8714 | return NULL_RTX; | |
8715 | ||
8716 | /* We can load this constant by using VDUP and a constant in a | |
8717 | single ARM register. This will be cheaper than a vector | |
8718 | load. */ | |
8719 | ||
8720 | x = copy_to_mode_reg (inner_mode, XVECEXP (vals, 0, 0)); | |
a277dd9b | 8721 | return gen_rtx_VEC_DUPLICATE (mode, x); |
814a4c3b DJ |
8722 | } |
8723 | ||
8724 | /* Generate code to load VALS, which is a PARALLEL containing only | |
8725 | constants (for vec_init) or CONST_VECTOR, efficiently into a | |
8726 | register. Returns an RTX to copy into the register, or NULL_RTX | |
8727 | for a PARALLEL that can not be converted into a CONST_VECTOR. */ | |
8728 | ||
8729 | rtx | |
8730 | neon_make_constant (rtx vals) | |
8731 | { | |
8732 | enum machine_mode mode = GET_MODE (vals); | |
8733 | rtx target; | |
8734 | rtx const_vec = NULL_RTX; | |
8735 | int n_elts = GET_MODE_NUNITS (mode); | |
8736 | int n_const = 0; | |
8737 | int i; | |
8738 | ||
8739 | if (GET_CODE (vals) == CONST_VECTOR) | |
8740 | const_vec = vals; | |
8741 | else if (GET_CODE (vals) == PARALLEL) | |
8742 | { | |
8743 | /* A CONST_VECTOR must contain only CONST_INTs and | |
8744 | CONST_DOUBLEs, but CONSTANT_P allows more (e.g. SYMBOL_REF). | |
8745 | Only store valid constants in a CONST_VECTOR. */ | |
8746 | for (i = 0; i < n_elts; ++i) | |
8747 | { | |
8748 | rtx x = XVECEXP (vals, 0, i); | |
8749 | if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE) | |
8750 | n_const++; | |
8751 | } | |
8752 | if (n_const == n_elts) | |
8753 | const_vec = gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0)); | |
8754 | } | |
8755 | else | |
8756 | gcc_unreachable (); | |
8757 | ||
8758 | if (const_vec != NULL | |
8759 | && neon_immediate_valid_for_move (const_vec, mode, NULL, NULL)) | |
8760 | /* Load using VMOV. On Cortex-A8 this takes one cycle. */ | |
8761 | return const_vec; | |
8762 | else if ((target = neon_vdup_constant (vals)) != NULL_RTX) | |
8763 | /* Loaded using VDUP. On Cortex-A8 the VDUP takes one NEON | |
8764 | pipeline cycle; creating the constant takes one or two ARM | |
8765 | pipeline cycles. */ | |
8766 | return target; | |
8767 | else if (const_vec != NULL_RTX) | |
8768 | /* Load from constant pool. On Cortex-A8 this takes two cycles | |
8769 | (for either double or quad vectors). We can not take advantage | |
8770 | of single-cycle VLD1 because we need a PC-relative addressing | |
8771 | mode. */ | |
8772 | return const_vec; | |
8773 | else | |
8774 | /* A PARALLEL containing something not valid inside CONST_VECTOR. | |
8775 | We can not construct an initializer. */ | |
8776 | return NULL_RTX; | |
8777 | } | |
8778 | ||
8779 | /* Initialize vector TARGET to VALS. */ | |
88f77cba JB |
8780 | |
8781 | void | |
8782 | neon_expand_vector_init (rtx target, rtx vals) | |
8783 | { | |
8784 | enum machine_mode mode = GET_MODE (target); | |
814a4c3b DJ |
8785 | enum machine_mode inner_mode = GET_MODE_INNER (mode); |
8786 | int n_elts = GET_MODE_NUNITS (mode); | |
8787 | int n_var = 0, one_var = -1; | |
8788 | bool all_same = true; | |
8789 | rtx x, mem; | |
8790 | int i; | |
88f77cba | 8791 | |
814a4c3b DJ |
8792 | for (i = 0; i < n_elts; ++i) |
8793 | { | |
8794 | x = XVECEXP (vals, 0, i); | |
8795 | if (!CONSTANT_P (x)) | |
8796 | ++n_var, one_var = i; | |
8797 | ||
8798 | if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0))) | |
8799 | all_same = false; | |
8800 | } | |
88f77cba | 8801 | |
814a4c3b DJ |
8802 | if (n_var == 0) |
8803 | { | |
8804 | rtx constant = neon_make_constant (vals); | |
8805 | if (constant != NULL_RTX) | |
8806 | { | |
8807 | emit_move_insn (target, constant); | |
8808 | return; | |
8809 | } | |
8810 | } | |
8811 | ||
8812 | /* Splat a single non-constant element if we can. */ | |
8813 | if (all_same && GET_MODE_SIZE (inner_mode) <= 4) | |
8814 | { | |
8815 | x = copy_to_mode_reg (inner_mode, XVECEXP (vals, 0, 0)); | |
8816 | emit_insn (gen_rtx_SET (VOIDmode, target, | |
a277dd9b | 8817 | gen_rtx_VEC_DUPLICATE (mode, x))); |
814a4c3b DJ |
8818 | return; |
8819 | } | |
8820 | ||
8821 | /* One field is non-constant. Load constant then overwrite varying | |
8822 | field. This is more efficient than using the stack. */ | |
8823 | if (n_var == 1) | |
8824 | { | |
8825 | rtx copy = copy_rtx (vals); | |
a277dd9b | 8826 | rtx index = GEN_INT (one_var); |
814a4c3b DJ |
8827 | |
8828 | /* Load constant part of vector, substitute neighboring value for | |
8829 | varying element. */ | |
8830 | XVECEXP (copy, 0, one_var) = XVECEXP (vals, 0, (one_var + 1) % n_elts); | |
8831 | neon_expand_vector_init (target, copy); | |
8832 | ||
8833 | /* Insert variable. */ | |
8834 | x = copy_to_mode_reg (inner_mode, XVECEXP (vals, 0, one_var)); | |
a277dd9b SL |
8835 | switch (mode) |
8836 | { | |
8837 | case V8QImode: | |
8838 | emit_insn (gen_neon_vset_lanev8qi (target, x, target, index)); | |
8839 | break; | |
8840 | case V16QImode: | |
8841 | emit_insn (gen_neon_vset_lanev16qi (target, x, target, index)); | |
8842 | break; | |
8843 | case V4HImode: | |
8844 | emit_insn (gen_neon_vset_lanev4hi (target, x, target, index)); | |
8845 | break; | |
8846 | case V8HImode: | |
8847 | emit_insn (gen_neon_vset_lanev8hi (target, x, target, index)); | |
8848 | break; | |
8849 | case V2SImode: | |
8850 | emit_insn (gen_neon_vset_lanev2si (target, x, target, index)); | |
8851 | break; | |
8852 | case V4SImode: | |
8853 | emit_insn (gen_neon_vset_lanev4si (target, x, target, index)); | |
8854 | break; | |
8855 | case V2SFmode: | |
8856 | emit_insn (gen_neon_vset_lanev2sf (target, x, target, index)); | |
8857 | break; | |
8858 | case V4SFmode: | |
8859 | emit_insn (gen_neon_vset_lanev4sf (target, x, target, index)); | |
8860 | break; | |
8861 | case V2DImode: | |
8862 | emit_insn (gen_neon_vset_lanev2di (target, x, target, index)); | |
8863 | break; | |
8864 | default: | |
8865 | gcc_unreachable (); | |
8866 | } | |
814a4c3b DJ |
8867 | return; |
8868 | } | |
8869 | ||
8870 | /* Construct the vector in memory one field at a time | |
8871 | and load the whole vector. */ | |
88f77cba JB |
8872 | mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0); |
8873 | for (i = 0; i < n_elts; i++) | |
814a4c3b DJ |
8874 | emit_move_insn (adjust_address_nv (mem, inner_mode, |
8875 | i * GET_MODE_SIZE (inner_mode)), | |
8876 | XVECEXP (vals, 0, i)); | |
88f77cba JB |
8877 | emit_move_insn (target, mem); |
8878 | } | |
8879 | ||
b617fc71 JB |
8880 | /* Ensure OPERAND lies between LOW (inclusive) and HIGH (exclusive). Raise |
8881 | ERR if it doesn't. FIXME: NEON bounds checks occur late in compilation, so | |
8882 | reported source locations are bogus. */ | |
8883 | ||
8884 | static void | |
8885 | bounds_check (rtx operand, HOST_WIDE_INT low, HOST_WIDE_INT high, | |
8886 | const char *err) | |
8887 | { | |
8888 | HOST_WIDE_INT lane; | |
8889 | ||
8890 | gcc_assert (GET_CODE (operand) == CONST_INT); | |
8891 | ||
8892 | lane = INTVAL (operand); | |
8893 | ||
8894 | if (lane < low || lane >= high) | |
8895 | error (err); | |
8896 | } | |
8897 | ||
8898 | /* Bounds-check lanes. */ | |
8899 | ||
8900 | void | |
8901 | neon_lane_bounds (rtx operand, HOST_WIDE_INT low, HOST_WIDE_INT high) | |
8902 | { | |
8903 | bounds_check (operand, low, high, "lane out of range"); | |
8904 | } | |
8905 | ||
8906 | /* Bounds-check constants. */ | |
8907 | ||
8908 | void | |
8909 | neon_const_bounds (rtx operand, HOST_WIDE_INT low, HOST_WIDE_INT high) | |
8910 | { | |
8911 | bounds_check (operand, low, high, "constant out of range"); | |
8912 | } | |
8913 | ||
8914 | HOST_WIDE_INT | |
8915 | neon_element_bits (enum machine_mode mode) | |
8916 | { | |
8917 | if (mode == DImode) | |
8918 | return GET_MODE_BITSIZE (mode); | |
8919 | else | |
8920 | return GET_MODE_BITSIZE (GET_MODE_INNER (mode)); | |
8921 | } | |
8922 | ||
cce8749e CH |
8923 | \f |
8924 | /* Predicates for `match_operand' and `match_operator'. */ | |
8925 | ||
9b6b54e2 | 8926 | /* Return nonzero if OP is a valid Cirrus memory address pattern. */ |
9b6b54e2 | 8927 | int |
e32bac5b | 8928 | cirrus_memory_offset (rtx op) |
9b6b54e2 NC |
8929 | { |
8930 | /* Reject eliminable registers. */ | |
8931 | if (! (reload_in_progress || reload_completed) | |
8932 | && ( reg_mentioned_p (frame_pointer_rtx, op) | |
8933 | || reg_mentioned_p (arg_pointer_rtx, op) | |
8934 | || reg_mentioned_p (virtual_incoming_args_rtx, op) | |
8935 | || reg_mentioned_p (virtual_outgoing_args_rtx, op) | |
8936 | || reg_mentioned_p (virtual_stack_dynamic_rtx, op) | |
8937 | || reg_mentioned_p (virtual_stack_vars_rtx, op))) | |
8938 | return 0; | |
8939 | ||
8940 | if (GET_CODE (op) == MEM) | |
8941 | { | |
8942 | rtx ind; | |
8943 | ||
8944 | ind = XEXP (op, 0); | |
8945 | ||
8946 | /* Match: (mem (reg)). */ | |
8947 | if (GET_CODE (ind) == REG) | |
8948 | return 1; | |
8949 | ||
8950 | /* Match: | |
8951 | (mem (plus (reg) | |
8952 | (const))). */ | |
8953 | if (GET_CODE (ind) == PLUS | |
8954 | && GET_CODE (XEXP (ind, 0)) == REG | |
8955 | && REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode) | |
8956 | && GET_CODE (XEXP (ind, 1)) == CONST_INT) | |
8957 | return 1; | |
8958 | } | |
8959 | ||
8960 | return 0; | |
8961 | } | |
8962 | ||
f26b8ec9 | 8963 | /* Return TRUE if OP is a valid coprocessor memory address pattern. |
5b3e6663 PB |
8964 | WB is true if full writeback address modes are allowed and is false |
8965 | if limited writeback address modes (POST_INC and PRE_DEC) are | |
8966 | allowed. */ | |
9b66ebb1 PB |
8967 | |
8968 | int | |
fdd695fd | 8969 | arm_coproc_mem_operand (rtx op, bool wb) |
9b66ebb1 | 8970 | { |
fdd695fd | 8971 | rtx ind; |
9b66ebb1 | 8972 | |
fdd695fd | 8973 | /* Reject eliminable registers. */ |
9b66ebb1 PB |
8974 | if (! (reload_in_progress || reload_completed) |
8975 | && ( reg_mentioned_p (frame_pointer_rtx, op) | |
8976 | || reg_mentioned_p (arg_pointer_rtx, op) | |
8977 | || reg_mentioned_p (virtual_incoming_args_rtx, op) | |
8978 | || reg_mentioned_p (virtual_outgoing_args_rtx, op) | |
8979 | || reg_mentioned_p (virtual_stack_dynamic_rtx, op) | |
8980 | || reg_mentioned_p (virtual_stack_vars_rtx, op))) | |
8981 | return FALSE; | |
8982 | ||
59b9a953 | 8983 | /* Constants are converted into offsets from labels. */ |
fdd695fd PB |
8984 | if (GET_CODE (op) != MEM) |
8985 | return FALSE; | |
9b66ebb1 | 8986 | |
fdd695fd | 8987 | ind = XEXP (op, 0); |
9b66ebb1 | 8988 | |
fdd695fd PB |
8989 | if (reload_completed |
8990 | && (GET_CODE (ind) == LABEL_REF | |
8991 | || (GET_CODE (ind) == CONST | |
8992 | && GET_CODE (XEXP (ind, 0)) == PLUS | |
8993 | && GET_CODE (XEXP (XEXP (ind, 0), 0)) == LABEL_REF | |
8994 | && GET_CODE (XEXP (XEXP (ind, 0), 1)) == CONST_INT))) | |
8995 | return TRUE; | |
9b66ebb1 | 8996 | |
fdd695fd PB |
8997 | /* Match: (mem (reg)). */ |
8998 | if (GET_CODE (ind) == REG) | |
8999 | return arm_address_register_rtx_p (ind, 0); | |
9000 | ||
5b3e6663 PB |
9001 | /* Autoincremment addressing modes. POST_INC and PRE_DEC are |
9002 | acceptable in any case (subject to verification by | |
9003 | arm_address_register_rtx_p). We need WB to be true to accept | |
9004 | PRE_INC and POST_DEC. */ | |
9005 | if (GET_CODE (ind) == POST_INC | |
9006 | || GET_CODE (ind) == PRE_DEC | |
9007 | || (wb | |
9008 | && (GET_CODE (ind) == PRE_INC | |
9009 | || GET_CODE (ind) == POST_DEC))) | |
fdd695fd PB |
9010 | return arm_address_register_rtx_p (XEXP (ind, 0), 0); |
9011 | ||
9012 | if (wb | |
9013 | && (GET_CODE (ind) == POST_MODIFY || GET_CODE (ind) == PRE_MODIFY) | |
9014 | && arm_address_register_rtx_p (XEXP (ind, 0), 0) | |
9015 | && GET_CODE (XEXP (ind, 1)) == PLUS | |
9016 | && rtx_equal_p (XEXP (XEXP (ind, 1), 0), XEXP (ind, 0))) | |
9017 | ind = XEXP (ind, 1); | |
9018 | ||
9019 | /* Match: | |
9020 | (plus (reg) | |
9021 | (const)). */ | |
9022 | if (GET_CODE (ind) == PLUS | |
9023 | && GET_CODE (XEXP (ind, 0)) == REG | |
9024 | && REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode) | |
9025 | && GET_CODE (XEXP (ind, 1)) == CONST_INT | |
9026 | && INTVAL (XEXP (ind, 1)) > -1024 | |
9027 | && INTVAL (XEXP (ind, 1)) < 1024 | |
9028 | && (INTVAL (XEXP (ind, 1)) & 3) == 0) | |
9029 | return TRUE; | |
9b66ebb1 PB |
9030 | |
9031 | return FALSE; | |
9032 | } | |
9033 | ||
88f77cba | 9034 | /* Return TRUE if OP is a memory operand which we can load or store a vector |
dc34db56 PB |
9035 | to/from. TYPE is one of the following values: |
9036 | 0 - Vector load/stor (vldr) | |
9037 | 1 - Core registers (ldm) | |
9038 | 2 - Element/structure loads (vld1) | |
9039 | */ | |
88f77cba | 9040 | int |
dc34db56 | 9041 | neon_vector_mem_operand (rtx op, int type) |
88f77cba JB |
9042 | { |
9043 | rtx ind; | |
9044 | ||
9045 | /* Reject eliminable registers. */ | |
9046 | if (! (reload_in_progress || reload_completed) | |
9047 | && ( reg_mentioned_p (frame_pointer_rtx, op) | |
9048 | || reg_mentioned_p (arg_pointer_rtx, op) | |
9049 | || reg_mentioned_p (virtual_incoming_args_rtx, op) | |
9050 | || reg_mentioned_p (virtual_outgoing_args_rtx, op) | |
9051 | || reg_mentioned_p (virtual_stack_dynamic_rtx, op) | |
9052 | || reg_mentioned_p (virtual_stack_vars_rtx, op))) | |
9053 | return FALSE; | |
9054 | ||
9055 | /* Constants are converted into offsets from labels. */ | |
9056 | if (GET_CODE (op) != MEM) | |
9057 | return FALSE; | |
9058 | ||
9059 | ind = XEXP (op, 0); | |
9060 | ||
9061 | if (reload_completed | |
9062 | && (GET_CODE (ind) == LABEL_REF | |
9063 | || (GET_CODE (ind) == CONST | |
9064 | && GET_CODE (XEXP (ind, 0)) == PLUS | |
9065 | && GET_CODE (XEXP (XEXP (ind, 0), 0)) == LABEL_REF | |
9066 | && GET_CODE (XEXP (XEXP (ind, 0), 1)) == CONST_INT))) | |
9067 | return TRUE; | |
9068 | ||
9069 | /* Match: (mem (reg)). */ | |
9070 | if (GET_CODE (ind) == REG) | |
9071 | return arm_address_register_rtx_p (ind, 0); | |
9072 | ||
9073 | /* Allow post-increment with Neon registers. */ | |
c452684d JB |
9074 | if ((type != 1 && GET_CODE (ind) == POST_INC) |
9075 | || (type == 0 && GET_CODE (ind) == PRE_DEC)) | |
88f77cba JB |
9076 | return arm_address_register_rtx_p (XEXP (ind, 0), 0); |
9077 | ||
dc34db56 | 9078 | /* FIXME: vld1 allows register post-modify. */ |
88f77cba JB |
9079 | |
9080 | /* Match: | |
9081 | (plus (reg) | |
9082 | (const)). */ | |
dc34db56 | 9083 | if (type == 0 |
88f77cba JB |
9084 | && GET_CODE (ind) == PLUS |
9085 | && GET_CODE (XEXP (ind, 0)) == REG | |
9086 | && REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode) | |
9087 | && GET_CODE (XEXP (ind, 1)) == CONST_INT | |
9088 | && INTVAL (XEXP (ind, 1)) > -1024 | |
9089 | && INTVAL (XEXP (ind, 1)) < 1016 | |
9090 | && (INTVAL (XEXP (ind, 1)) & 3) == 0) | |
9091 | return TRUE; | |
9092 | ||
9093 | return FALSE; | |
9094 | } | |
9095 | ||
9096 | /* Return TRUE if OP is a mem suitable for loading/storing a Neon struct | |
9097 | type. */ | |
9098 | int | |
9099 | neon_struct_mem_operand (rtx op) | |
9100 | { | |
9101 | rtx ind; | |
9102 | ||
9103 | /* Reject eliminable registers. */ | |
9104 | if (! (reload_in_progress || reload_completed) | |
9105 | && ( reg_mentioned_p (frame_pointer_rtx, op) | |
9106 | || reg_mentioned_p (arg_pointer_rtx, op) | |
9107 | || reg_mentioned_p (virtual_incoming_args_rtx, op) | |
9108 | || reg_mentioned_p (virtual_outgoing_args_rtx, op) | |
9109 | || reg_mentioned_p (virtual_stack_dynamic_rtx, op) | |
9110 | || reg_mentioned_p (virtual_stack_vars_rtx, op))) | |
9111 | return FALSE; | |
9112 | ||
9113 | /* Constants are converted into offsets from labels. */ | |
9114 | if (GET_CODE (op) != MEM) | |
9115 | return FALSE; | |
9116 | ||
9117 | ind = XEXP (op, 0); | |
9118 | ||
9119 | if (reload_completed | |
9120 | && (GET_CODE (ind) == LABEL_REF | |
9121 | || (GET_CODE (ind) == CONST | |
9122 | && GET_CODE (XEXP (ind, 0)) == PLUS | |
9123 | && GET_CODE (XEXP (XEXP (ind, 0), 0)) == LABEL_REF | |
9124 | && GET_CODE (XEXP (XEXP (ind, 0), 1)) == CONST_INT))) | |
9125 | return TRUE; | |
9126 | ||
9127 | /* Match: (mem (reg)). */ | |
9128 | if (GET_CODE (ind) == REG) | |
9129 | return arm_address_register_rtx_p (ind, 0); | |
9130 | ||
9131 | return FALSE; | |
9132 | } | |
9133 | ||
6555b6bd RE |
9134 | /* Return true if X is a register that will be eliminated later on. */ |
9135 | int | |
9136 | arm_eliminable_register (rtx x) | |
9137 | { | |
9138 | return REG_P (x) && (REGNO (x) == FRAME_POINTER_REGNUM | |
9139 | || REGNO (x) == ARG_POINTER_REGNUM | |
9140 | || (REGNO (x) >= FIRST_VIRTUAL_REGISTER | |
9141 | && REGNO (x) <= LAST_VIRTUAL_REGISTER)); | |
9142 | } | |
9b66ebb1 | 9143 | |
9b66ebb1 | 9144 | /* Return GENERAL_REGS if a scratch register required to reload x to/from |
fe2d934b | 9145 | coprocessor registers. Otherwise return NO_REGS. */ |
9b66ebb1 PB |
9146 | |
9147 | enum reg_class | |
fe2d934b | 9148 | coproc_secondary_reload_class (enum machine_mode mode, rtx x, bool wb) |
9b66ebb1 | 9149 | { |
0fd8c3ad SL |
9150 | if (mode == HFmode) |
9151 | { | |
e0dc3601 PB |
9152 | if (!TARGET_NEON_FP16) |
9153 | return GENERAL_REGS; | |
0fd8c3ad SL |
9154 | if (s_register_operand (x, mode) || neon_vector_mem_operand (x, 2)) |
9155 | return NO_REGS; | |
9156 | return GENERAL_REGS; | |
9157 | } | |
9158 | ||
88f77cba JB |
9159 | if (TARGET_NEON |
9160 | && (GET_MODE_CLASS (mode) == MODE_VECTOR_INT | |
9161 | || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT) | |
dc34db56 | 9162 | && neon_vector_mem_operand (x, 0)) |
88f77cba JB |
9163 | return NO_REGS; |
9164 | ||
fe2d934b | 9165 | if (arm_coproc_mem_operand (x, wb) || s_register_operand (x, mode)) |
9b66ebb1 PB |
9166 | return NO_REGS; |
9167 | ||
9168 | return GENERAL_REGS; | |
9169 | } | |
9170 | ||
866af8a9 JB |
9171 | /* Values which must be returned in the most-significant end of the return |
9172 | register. */ | |
9173 | ||
9174 | static bool | |
586de218 | 9175 | arm_return_in_msb (const_tree valtype) |
866af8a9 JB |
9176 | { |
9177 | return (TARGET_AAPCS_BASED | |
9178 | && BYTES_BIG_ENDIAN | |
9179 | && (AGGREGATE_TYPE_P (valtype) | |
9180 | || TREE_CODE (valtype) == COMPLEX_TYPE)); | |
9181 | } | |
9b66ebb1 | 9182 | |
f0375c66 NC |
9183 | /* Returns TRUE if INSN is an "LDR REG, ADDR" instruction. |
9184 | Use by the Cirrus Maverick code which has to workaround | |
9185 | a hardware bug triggered by such instructions. */ | |
f0375c66 | 9186 | static bool |
e32bac5b | 9187 | arm_memory_load_p (rtx insn) |
9b6b54e2 NC |
9188 | { |
9189 | rtx body, lhs, rhs;; | |
9190 | ||
f0375c66 NC |
9191 | if (insn == NULL_RTX || GET_CODE (insn) != INSN) |
9192 | return false; | |
9b6b54e2 NC |
9193 | |
9194 | body = PATTERN (insn); | |
9195 | ||
9196 | if (GET_CODE (body) != SET) | |
f0375c66 | 9197 | return false; |
9b6b54e2 NC |
9198 | |
9199 | lhs = XEXP (body, 0); | |
9200 | rhs = XEXP (body, 1); | |
9201 | ||
f0375c66 NC |
9202 | lhs = REG_OR_SUBREG_RTX (lhs); |
9203 | ||
9204 | /* If the destination is not a general purpose | |
9205 | register we do not have to worry. */ | |
9206 | if (GET_CODE (lhs) != REG | |
9207 | || REGNO_REG_CLASS (REGNO (lhs)) != GENERAL_REGS) | |
9208 | return false; | |
9209 | ||
9210 | /* As well as loads from memory we also have to react | |
9211 | to loads of invalid constants which will be turned | |
9212 | into loads from the minipool. */ | |
9213 | return (GET_CODE (rhs) == MEM | |
9214 | || GET_CODE (rhs) == SYMBOL_REF | |
9215 | || note_invalid_constants (insn, -1, false)); | |
9b6b54e2 NC |
9216 | } |
9217 | ||
f0375c66 | 9218 | /* Return TRUE if INSN is a Cirrus instruction. */ |
f0375c66 | 9219 | static bool |
e32bac5b | 9220 | arm_cirrus_insn_p (rtx insn) |
9b6b54e2 NC |
9221 | { |
9222 | enum attr_cirrus attr; | |
9223 | ||
e6d29d15 | 9224 | /* get_attr cannot accept USE or CLOBBER. */ |
9b6b54e2 NC |
9225 | if (!insn |
9226 | || GET_CODE (insn) != INSN | |
9227 | || GET_CODE (PATTERN (insn)) == USE | |
9228 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
9229 | return 0; | |
9230 | ||
9231 | attr = get_attr_cirrus (insn); | |
9232 | ||
f0375c66 | 9233 | return attr != CIRRUS_NOT; |
9b6b54e2 NC |
9234 | } |
9235 | ||
9236 | /* Cirrus reorg for invalid instruction combinations. */ | |
9b6b54e2 | 9237 | static void |
e32bac5b | 9238 | cirrus_reorg (rtx first) |
9b6b54e2 NC |
9239 | { |
9240 | enum attr_cirrus attr; | |
9241 | rtx body = PATTERN (first); | |
9242 | rtx t; | |
9243 | int nops; | |
9244 | ||
9245 | /* Any branch must be followed by 2 non Cirrus instructions. */ | |
9246 | if (GET_CODE (first) == JUMP_INSN && GET_CODE (body) != RETURN) | |
9247 | { | |
9248 | nops = 0; | |
9249 | t = next_nonnote_insn (first); | |
9250 | ||
f0375c66 | 9251 | if (arm_cirrus_insn_p (t)) |
9b6b54e2 NC |
9252 | ++ nops; |
9253 | ||
f0375c66 | 9254 | if (arm_cirrus_insn_p (next_nonnote_insn (t))) |
9b6b54e2 NC |
9255 | ++ nops; |
9256 | ||
9257 | while (nops --) | |
9258 | emit_insn_after (gen_nop (), first); | |
9259 | ||
9260 | return; | |
9261 | } | |
9262 | ||
9263 | /* (float (blah)) is in parallel with a clobber. */ | |
9264 | if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0) | |
9265 | body = XVECEXP (body, 0, 0); | |
9266 | ||
9267 | if (GET_CODE (body) == SET) | |
9268 | { | |
9269 | rtx lhs = XEXP (body, 0), rhs = XEXP (body, 1); | |
9270 | ||
9271 | /* cfldrd, cfldr64, cfstrd, cfstr64 must | |
9272 | be followed by a non Cirrus insn. */ | |
9273 | if (get_attr_cirrus (first) == CIRRUS_DOUBLE) | |
9274 | { | |
f0375c66 | 9275 | if (arm_cirrus_insn_p (next_nonnote_insn (first))) |
9b6b54e2 NC |
9276 | emit_insn_after (gen_nop (), first); |
9277 | ||
9278 | return; | |
9279 | } | |
f0375c66 | 9280 | else if (arm_memory_load_p (first)) |
9b6b54e2 NC |
9281 | { |
9282 | unsigned int arm_regno; | |
9283 | ||
9284 | /* Any ldr/cfmvdlr, ldr/cfmvdhr, ldr/cfmvsr, ldr/cfmv64lr, | |
9285 | ldr/cfmv64hr combination where the Rd field is the same | |
9286 | in both instructions must be split with a non Cirrus | |
9287 | insn. Example: | |
9288 | ||
9289 | ldr r0, blah | |
9290 | nop | |
9291 | cfmvsr mvf0, r0. */ | |
9292 | ||
9293 | /* Get Arm register number for ldr insn. */ | |
9294 | if (GET_CODE (lhs) == REG) | |
9295 | arm_regno = REGNO (lhs); | |
9b6b54e2 | 9296 | else |
e6d29d15 NS |
9297 | { |
9298 | gcc_assert (GET_CODE (rhs) == REG); | |
9299 | arm_regno = REGNO (rhs); | |
9300 | } | |
9b6b54e2 NC |
9301 | |
9302 | /* Next insn. */ | |
9303 | first = next_nonnote_insn (first); | |
9304 | ||
f0375c66 | 9305 | if (! arm_cirrus_insn_p (first)) |
9b6b54e2 NC |
9306 | return; |
9307 | ||
9308 | body = PATTERN (first); | |
9309 | ||
9310 | /* (float (blah)) is in parallel with a clobber. */ | |
9311 | if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0)) | |
9312 | body = XVECEXP (body, 0, 0); | |
9313 | ||
9314 | if (GET_CODE (body) == FLOAT) | |
9315 | body = XEXP (body, 0); | |
9316 | ||
9317 | if (get_attr_cirrus (first) == CIRRUS_MOVE | |
9318 | && GET_CODE (XEXP (body, 1)) == REG | |
9319 | && arm_regno == REGNO (XEXP (body, 1))) | |
9320 | emit_insn_after (gen_nop (), first); | |
9321 | ||
9322 | return; | |
9323 | } | |
9324 | } | |
9325 | ||
e6d29d15 | 9326 | /* get_attr cannot accept USE or CLOBBER. */ |
9b6b54e2 NC |
9327 | if (!first |
9328 | || GET_CODE (first) != INSN | |
9329 | || GET_CODE (PATTERN (first)) == USE | |
9330 | || GET_CODE (PATTERN (first)) == CLOBBER) | |
9331 | return; | |
9332 | ||
9333 | attr = get_attr_cirrus (first); | |
9334 | ||
9335 | /* Any coprocessor compare instruction (cfcmps, cfcmpd, ...) | |
9336 | must be followed by a non-coprocessor instruction. */ | |
9337 | if (attr == CIRRUS_COMPARE) | |
9338 | { | |
9339 | nops = 0; | |
9340 | ||
9341 | t = next_nonnote_insn (first); | |
9342 | ||
f0375c66 | 9343 | if (arm_cirrus_insn_p (t)) |
9b6b54e2 NC |
9344 | ++ nops; |
9345 | ||
f0375c66 | 9346 | if (arm_cirrus_insn_p (next_nonnote_insn (t))) |
9b6b54e2 NC |
9347 | ++ nops; |
9348 | ||
9349 | while (nops --) | |
9350 | emit_insn_after (gen_nop (), first); | |
9351 | ||
9352 | return; | |
9353 | } | |
9354 | } | |
9355 | ||
2b835d68 RE |
9356 | /* Return TRUE if X references a SYMBOL_REF. */ |
9357 | int | |
e32bac5b | 9358 | symbol_mentioned_p (rtx x) |
2b835d68 | 9359 | { |
1d6e90ac NC |
9360 | const char * fmt; |
9361 | int i; | |
2b835d68 RE |
9362 | |
9363 | if (GET_CODE (x) == SYMBOL_REF) | |
9364 | return 1; | |
9365 | ||
d3585b76 DJ |
9366 | /* UNSPEC_TLS entries for a symbol include the SYMBOL_REF, but they |
9367 | are constant offsets, not symbols. */ | |
9368 | if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLS) | |
9369 | return 0; | |
9370 | ||
2b835d68 | 9371 | fmt = GET_RTX_FORMAT (GET_CODE (x)); |
f676971a | 9372 | |
2b835d68 RE |
9373 | for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--) |
9374 | { | |
9375 | if (fmt[i] == 'E') | |
9376 | { | |
1d6e90ac | 9377 | int j; |
2b835d68 RE |
9378 | |
9379 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
9380 | if (symbol_mentioned_p (XVECEXP (x, i, j))) | |
9381 | return 1; | |
9382 | } | |
9383 | else if (fmt[i] == 'e' && symbol_mentioned_p (XEXP (x, i))) | |
9384 | return 1; | |
9385 | } | |
9386 | ||
9387 | return 0; | |
9388 | } | |
9389 | ||
9390 | /* Return TRUE if X references a LABEL_REF. */ | |
9391 | int | |
e32bac5b | 9392 | label_mentioned_p (rtx x) |
2b835d68 | 9393 | { |
1d6e90ac NC |
9394 | const char * fmt; |
9395 | int i; | |
2b835d68 RE |
9396 | |
9397 | if (GET_CODE (x) == LABEL_REF) | |
9398 | return 1; | |
9399 | ||
d3585b76 DJ |
9400 | /* UNSPEC_TLS entries for a symbol include a LABEL_REF for the referencing |
9401 | instruction, but they are constant offsets, not symbols. */ | |
9402 | if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLS) | |
9403 | return 0; | |
9404 | ||
2b835d68 RE |
9405 | fmt = GET_RTX_FORMAT (GET_CODE (x)); |
9406 | for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--) | |
9407 | { | |
9408 | if (fmt[i] == 'E') | |
9409 | { | |
1d6e90ac | 9410 | int j; |
2b835d68 RE |
9411 | |
9412 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
9413 | if (label_mentioned_p (XVECEXP (x, i, j))) | |
9414 | return 1; | |
9415 | } | |
9416 | else if (fmt[i] == 'e' && label_mentioned_p (XEXP (x, i))) | |
9417 | return 1; | |
9418 | } | |
9419 | ||
9420 | return 0; | |
9421 | } | |
9422 | ||
d3585b76 DJ |
9423 | int |
9424 | tls_mentioned_p (rtx x) | |
9425 | { | |
9426 | switch (GET_CODE (x)) | |
9427 | { | |
9428 | case CONST: | |
9429 | return tls_mentioned_p (XEXP (x, 0)); | |
9430 | ||
9431 | case UNSPEC: | |
9432 | if (XINT (x, 1) == UNSPEC_TLS) | |
9433 | return 1; | |
9434 | ||
9435 | default: | |
9436 | return 0; | |
9437 | } | |
9438 | } | |
9439 | ||
2e5505a4 RE |
9440 | /* Must not copy any rtx that uses a pc-relative address. */ |
9441 | ||
9442 | static int | |
9443 | arm_note_pic_base (rtx *x, void *date ATTRIBUTE_UNUSED) | |
9444 | { | |
9445 | if (GET_CODE (*x) == UNSPEC | |
9446 | && XINT (*x, 1) == UNSPEC_PIC_BASE) | |
9447 | return 1; | |
9448 | return 0; | |
9449 | } | |
d3585b76 DJ |
9450 | |
9451 | static bool | |
9452 | arm_cannot_copy_insn_p (rtx insn) | |
9453 | { | |
2e5505a4 | 9454 | return for_each_rtx (&PATTERN (insn), arm_note_pic_base, NULL); |
d3585b76 DJ |
9455 | } |
9456 | ||
ff9940b0 | 9457 | enum rtx_code |
e32bac5b | 9458 | minmax_code (rtx x) |
ff9940b0 RE |
9459 | { |
9460 | enum rtx_code code = GET_CODE (x); | |
9461 | ||
e6d29d15 NS |
9462 | switch (code) |
9463 | { | |
9464 | case SMAX: | |
9465 | return GE; | |
9466 | case SMIN: | |
9467 | return LE; | |
9468 | case UMIN: | |
9469 | return LEU; | |
9470 | case UMAX: | |
9471 | return GEU; | |
9472 | default: | |
9473 | gcc_unreachable (); | |
9474 | } | |
ff9940b0 RE |
9475 | } |
9476 | ||
6354dc9b | 9477 | /* Return 1 if memory locations are adjacent. */ |
f3bb6135 | 9478 | int |
e32bac5b | 9479 | adjacent_mem_locations (rtx a, rtx b) |
ff9940b0 | 9480 | { |
15b5c4c1 RE |
9481 | /* We don't guarantee to preserve the order of these memory refs. */ |
9482 | if (volatile_refs_p (a) || volatile_refs_p (b)) | |
9483 | return 0; | |
9484 | ||
ff9940b0 RE |
9485 | if ((GET_CODE (XEXP (a, 0)) == REG |
9486 | || (GET_CODE (XEXP (a, 0)) == PLUS | |
9487 | && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT)) | |
9488 | && (GET_CODE (XEXP (b, 0)) == REG | |
9489 | || (GET_CODE (XEXP (b, 0)) == PLUS | |
9490 | && GET_CODE (XEXP (XEXP (b, 0), 1)) == CONST_INT))) | |
9491 | { | |
6555b6bd RE |
9492 | HOST_WIDE_INT val0 = 0, val1 = 0; |
9493 | rtx reg0, reg1; | |
9494 | int val_diff; | |
f676971a | 9495 | |
ff9940b0 RE |
9496 | if (GET_CODE (XEXP (a, 0)) == PLUS) |
9497 | { | |
6555b6bd | 9498 | reg0 = XEXP (XEXP (a, 0), 0); |
ff9940b0 RE |
9499 | val0 = INTVAL (XEXP (XEXP (a, 0), 1)); |
9500 | } | |
9501 | else | |
6555b6bd | 9502 | reg0 = XEXP (a, 0); |
1d6e90ac | 9503 | |
ff9940b0 RE |
9504 | if (GET_CODE (XEXP (b, 0)) == PLUS) |
9505 | { | |
6555b6bd | 9506 | reg1 = XEXP (XEXP (b, 0), 0); |
ff9940b0 RE |
9507 | val1 = INTVAL (XEXP (XEXP (b, 0), 1)); |
9508 | } | |
9509 | else | |
6555b6bd | 9510 | reg1 = XEXP (b, 0); |
1d6e90ac | 9511 | |
e32bac5b RE |
9512 | /* Don't accept any offset that will require multiple |
9513 | instructions to handle, since this would cause the | |
9514 | arith_adjacentmem pattern to output an overlong sequence. */ | |
bbbbb16a | 9515 | if (!const_ok_for_op (val0, PLUS) || !const_ok_for_op (val1, PLUS)) |
c75a3ddc | 9516 | return 0; |
f676971a | 9517 | |
6555b6bd RE |
9518 | /* Don't allow an eliminable register: register elimination can make |
9519 | the offset too large. */ | |
9520 | if (arm_eliminable_register (reg0)) | |
9521 | return 0; | |
9522 | ||
9523 | val_diff = val1 - val0; | |
15b5c4c1 RE |
9524 | |
9525 | if (arm_ld_sched) | |
9526 | { | |
9527 | /* If the target has load delay slots, then there's no benefit | |
9528 | to using an ldm instruction unless the offset is zero and | |
9529 | we are optimizing for size. */ | |
9530 | return (optimize_size && (REGNO (reg0) == REGNO (reg1)) | |
9531 | && (val0 == 0 || val1 == 0 || val0 == 4 || val1 == 4) | |
9532 | && (val_diff == 4 || val_diff == -4)); | |
9533 | } | |
9534 | ||
6555b6bd RE |
9535 | return ((REGNO (reg0) == REGNO (reg1)) |
9536 | && (val_diff == 4 || val_diff == -4)); | |
ff9940b0 | 9537 | } |
6555b6bd | 9538 | |
ff9940b0 RE |
9539 | return 0; |
9540 | } | |
9541 | ||
93b338c3 BS |
9542 | /* Return true iff it would be profitable to turn a sequence of NOPS loads |
9543 | or stores (depending on IS_STORE) into a load-multiple or store-multiple | |
9544 | instruction. ADD_OFFSET is nonzero if the base address register needs | |
9545 | to be modified with an add instruction before we can use it. */ | |
9546 | ||
9547 | static bool | |
9548 | multiple_operation_profitable_p (bool is_store ATTRIBUTE_UNUSED, | |
9549 | int nops, HOST_WIDE_INT add_offset) | |
9550 | { | |
9551 | /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm | |
9552 | if the offset isn't small enough. The reason 2 ldrs are faster | |
9553 | is because these ARMs are able to do more than one cache access | |
9554 | in a single cycle. The ARM9 and StrongARM have Harvard caches, | |
9555 | whilst the ARM8 has a double bandwidth cache. This means that | |
9556 | these cores can do both an instruction fetch and a data fetch in | |
9557 | a single cycle, so the trick of calculating the address into a | |
9558 | scratch register (one of the result regs) and then doing a load | |
9559 | multiple actually becomes slower (and no smaller in code size). | |
9560 | That is the transformation | |
9561 | ||
9562 | ldr rd1, [rbase + offset] | |
9563 | ldr rd2, [rbase + offset + 4] | |
9564 | ||
9565 | to | |
9566 | ||
9567 | add rd1, rbase, offset | |
9568 | ldmia rd1, {rd1, rd2} | |
9569 | ||
9570 | produces worse code -- '3 cycles + any stalls on rd2' instead of | |
9571 | '2 cycles + any stalls on rd2'. On ARMs with only one cache | |
9572 | access per cycle, the first sequence could never complete in less | |
9573 | than 6 cycles, whereas the ldm sequence would only take 5 and | |
9574 | would make better use of sequential accesses if not hitting the | |
9575 | cache. | |
9576 | ||
9577 | We cheat here and test 'arm_ld_sched' which we currently know to | |
9578 | only be true for the ARM8, ARM9 and StrongARM. If this ever | |
9579 | changes, then the test below needs to be reworked. */ | |
9580 | if (nops == 2 && arm_ld_sched && add_offset != 0) | |
9581 | return false; | |
9582 | ||
8f4c6e28 BS |
9583 | /* XScale has load-store double instructions, but they have stricter |
9584 | alignment requirements than load-store multiple, so we cannot | |
9585 | use them. | |
9586 | ||
9587 | For XScale ldm requires 2 + NREGS cycles to complete and blocks | |
9588 | the pipeline until completion. | |
9589 | ||
9590 | NREGS CYCLES | |
9591 | 1 3 | |
9592 | 2 4 | |
9593 | 3 5 | |
9594 | 4 6 | |
9595 | ||
9596 | An ldr instruction takes 1-3 cycles, but does not block the | |
9597 | pipeline. | |
9598 | ||
9599 | NREGS CYCLES | |
9600 | 1 1-3 | |
9601 | 2 2-6 | |
9602 | 3 3-9 | |
9603 | 4 4-12 | |
9604 | ||
9605 | Best case ldr will always win. However, the more ldr instructions | |
9606 | we issue, the less likely we are to be able to schedule them well. | |
9607 | Using ldr instructions also increases code size. | |
9608 | ||
9609 | As a compromise, we use ldr for counts of 1 or 2 regs, and ldm | |
9610 | for counts of 3 or 4 regs. */ | |
9611 | if (nops <= 2 && arm_tune_xscale && !optimize_size) | |
9612 | return false; | |
93b338c3 BS |
9613 | return true; |
9614 | } | |
9615 | ||
9616 | /* Subroutine of load_multiple_sequence and store_multiple_sequence. | |
9617 | Given an array of UNSORTED_OFFSETS, of which there are NOPS, compute | |
9618 | an array ORDER which describes the sequence to use when accessing the | |
9619 | offsets that produces an ascending order. In this sequence, each | |
9620 | offset must be larger by exactly 4 than the previous one. ORDER[0] | |
9621 | must have been filled in with the lowest offset by the caller. | |
9622 | If UNSORTED_REGS is nonnull, it is an array of register numbers that | |
9623 | we use to verify that ORDER produces an ascending order of registers. | |
9624 | Return true if it was possible to construct such an order, false if | |
9625 | not. */ | |
9626 | ||
9627 | static bool | |
9628 | compute_offset_order (int nops, HOST_WIDE_INT *unsorted_offsets, int *order, | |
9629 | int *unsorted_regs) | |
9630 | { | |
9631 | int i; | |
9632 | for (i = 1; i < nops; i++) | |
9633 | { | |
9634 | int j; | |
9635 | ||
9636 | order[i] = order[i - 1]; | |
9637 | for (j = 0; j < nops; j++) | |
9638 | if (unsorted_offsets[j] == unsorted_offsets[order[i - 1]] + 4) | |
9639 | { | |
9640 | /* We must find exactly one offset that is higher than the | |
9641 | previous one by 4. */ | |
9642 | if (order[i] != order[i - 1]) | |
9643 | return false; | |
9644 | order[i] = j; | |
9645 | } | |
9646 | if (order[i] == order[i - 1]) | |
9647 | return false; | |
9648 | /* The register numbers must be ascending. */ | |
9649 | if (unsorted_regs != NULL | |
9650 | && unsorted_regs[order[i]] <= unsorted_regs[order[i - 1]]) | |
9651 | return false; | |
9652 | } | |
9653 | return true; | |
9654 | } | |
9655 | ||
37119410 BS |
9656 | /* Used to determine in a peephole whether a sequence of load |
9657 | instructions can be changed into a load-multiple instruction. | |
9658 | NOPS is the number of separate load instructions we are examining. The | |
9659 | first NOPS entries in OPERANDS are the destination registers, the | |
9660 | next NOPS entries are memory operands. If this function is | |
9661 | successful, *BASE is set to the common base register of the memory | |
9662 | accesses; *LOAD_OFFSET is set to the first memory location's offset | |
9663 | from that base register. | |
9664 | REGS is an array filled in with the destination register numbers. | |
9665 | SAVED_ORDER (if nonnull), is an array filled in with an order that maps | |
9666 | insn numbers to to an ascending order of stores. If CHECK_REGS is true, | |
9667 | the sequence of registers in REGS matches the loads from ascending memory | |
9668 | locations, and the function verifies that the register numbers are | |
9669 | themselves ascending. If CHECK_REGS is false, the register numbers | |
9670 | are stored in the order they are found in the operands. */ | |
9671 | static int | |
9672 | load_multiple_sequence (rtx *operands, int nops, int *regs, int *saved_order, | |
9673 | int *base, HOST_WIDE_INT *load_offset, bool check_regs) | |
84ed5e79 | 9674 | { |
93b338c3 BS |
9675 | int unsorted_regs[MAX_LDM_STM_OPS]; |
9676 | HOST_WIDE_INT unsorted_offsets[MAX_LDM_STM_OPS]; | |
9677 | int order[MAX_LDM_STM_OPS]; | |
37119410 | 9678 | rtx base_reg_rtx = NULL; |
ad076f4e | 9679 | int base_reg = -1; |
93b338c3 | 9680 | int i, ldm_case; |
84ed5e79 | 9681 | |
93b338c3 BS |
9682 | /* Can only handle up to MAX_LDM_STM_OPS insns at present, though could be |
9683 | easily extended if required. */ | |
9684 | gcc_assert (nops >= 2 && nops <= MAX_LDM_STM_OPS); | |
84ed5e79 | 9685 | |
93b338c3 | 9686 | memset (order, 0, MAX_LDM_STM_OPS * sizeof (int)); |
f0b4bdd5 | 9687 | |
84ed5e79 | 9688 | /* Loop over the operands and check that the memory references are |
112cdef5 | 9689 | suitable (i.e. immediate offsets from the same base register). At |
84ed5e79 RE |
9690 | the same time, extract the target register, and the memory |
9691 | offsets. */ | |
9692 | for (i = 0; i < nops; i++) | |
9693 | { | |
9694 | rtx reg; | |
9695 | rtx offset; | |
9696 | ||
56636818 JL |
9697 | /* Convert a subreg of a mem into the mem itself. */ |
9698 | if (GET_CODE (operands[nops + i]) == SUBREG) | |
4e26a7af | 9699 | operands[nops + i] = alter_subreg (operands + (nops + i)); |
56636818 | 9700 | |
e6d29d15 | 9701 | gcc_assert (GET_CODE (operands[nops + i]) == MEM); |
84ed5e79 RE |
9702 | |
9703 | /* Don't reorder volatile memory references; it doesn't seem worth | |
9704 | looking for the case where the order is ok anyway. */ | |
9705 | if (MEM_VOLATILE_P (operands[nops + i])) | |
9706 | return 0; | |
9707 | ||
9708 | offset = const0_rtx; | |
9709 | ||
9710 | if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG | |
9711 | || (GET_CODE (reg) == SUBREG | |
9712 | && GET_CODE (reg = SUBREG_REG (reg)) == REG)) | |
9713 | || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS | |
9714 | && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0)) | |
9715 | == REG) | |
9716 | || (GET_CODE (reg) == SUBREG | |
9717 | && GET_CODE (reg = SUBREG_REG (reg)) == REG)) | |
9718 | && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1)) | |
9719 | == CONST_INT))) | |
9720 | { | |
9721 | if (i == 0) | |
84ed5e79 | 9722 | { |
37119410 BS |
9723 | base_reg = REGNO (reg); |
9724 | base_reg_rtx = reg; | |
9725 | if (TARGET_THUMB1 && base_reg > LAST_LO_REGNUM) | |
84ed5e79 | 9726 | return 0; |
84ed5e79 | 9727 | } |
37119410 BS |
9728 | else if (base_reg != (int) REGNO (reg)) |
9729 | /* Not addressed from the same base register. */ | |
9730 | return 0; | |
9731 | ||
93b338c3 BS |
9732 | unsorted_regs[i] = (GET_CODE (operands[i]) == REG |
9733 | ? REGNO (operands[i]) | |
9734 | : REGNO (SUBREG_REG (operands[i]))); | |
84ed5e79 RE |
9735 | |
9736 | /* If it isn't an integer register, or if it overwrites the | |
9737 | base register but isn't the last insn in the list, then | |
9738 | we can't do this. */ | |
37119410 BS |
9739 | if (unsorted_regs[i] < 0 |
9740 | || (TARGET_THUMB1 && unsorted_regs[i] > LAST_LO_REGNUM) | |
9741 | || unsorted_regs[i] > 14 | |
84ed5e79 RE |
9742 | || (i != nops - 1 && unsorted_regs[i] == base_reg)) |
9743 | return 0; | |
9744 | ||
9745 | unsorted_offsets[i] = INTVAL (offset); | |
93b338c3 BS |
9746 | if (i == 0 || unsorted_offsets[i] < unsorted_offsets[order[0]]) |
9747 | order[0] = i; | |
84ed5e79 RE |
9748 | } |
9749 | else | |
9750 | /* Not a suitable memory address. */ | |
9751 | return 0; | |
9752 | } | |
9753 | ||
9754 | /* All the useful information has now been extracted from the | |
9755 | operands into unsorted_regs and unsorted_offsets; additionally, | |
93b338c3 BS |
9756 | order[0] has been set to the lowest offset in the list. Sort |
9757 | the offsets into order, verifying that they are adjacent, and | |
9758 | check that the register numbers are ascending. */ | |
37119410 BS |
9759 | if (!compute_offset_order (nops, unsorted_offsets, order, |
9760 | check_regs ? unsorted_regs : NULL)) | |
93b338c3 | 9761 | return 0; |
84ed5e79 | 9762 | |
37119410 BS |
9763 | if (saved_order) |
9764 | memcpy (saved_order, order, sizeof order); | |
9765 | ||
84ed5e79 RE |
9766 | if (base) |
9767 | { | |
9768 | *base = base_reg; | |
9769 | ||
9770 | for (i = 0; i < nops; i++) | |
37119410 | 9771 | regs[i] = unsorted_regs[check_regs ? order[i] : i]; |
84ed5e79 RE |
9772 | |
9773 | *load_offset = unsorted_offsets[order[0]]; | |
9774 | } | |
9775 | ||
37119410 BS |
9776 | if (TARGET_THUMB1 |
9777 | && !peep2_reg_dead_p (nops, base_reg_rtx)) | |
9778 | return 0; | |
9779 | ||
84ed5e79 | 9780 | if (unsorted_offsets[order[0]] == 0) |
93b338c3 BS |
9781 | ldm_case = 1; /* ldmia */ |
9782 | else if (TARGET_ARM && unsorted_offsets[order[0]] == 4) | |
9783 | ldm_case = 2; /* ldmib */ | |
9784 | else if (TARGET_ARM && unsorted_offsets[order[nops - 1]] == 0) | |
9785 | ldm_case = 3; /* ldmda */ | |
37119410 | 9786 | else if (TARGET_32BIT && unsorted_offsets[order[nops - 1]] == -4) |
93b338c3 BS |
9787 | ldm_case = 4; /* ldmdb */ |
9788 | else if (const_ok_for_arm (unsorted_offsets[order[0]]) | |
9789 | || const_ok_for_arm (-unsorted_offsets[order[0]])) | |
9790 | ldm_case = 5; | |
9791 | else | |
9792 | return 0; | |
949d79eb | 9793 | |
93b338c3 BS |
9794 | if (!multiple_operation_profitable_p (false, nops, |
9795 | ldm_case == 5 | |
9796 | ? unsorted_offsets[order[0]] : 0)) | |
b36ba79f RE |
9797 | return 0; |
9798 | ||
93b338c3 | 9799 | return ldm_case; |
84ed5e79 RE |
9800 | } |
9801 | ||
37119410 BS |
9802 | /* Used to determine in a peephole whether a sequence of store instructions can |
9803 | be changed into a store-multiple instruction. | |
9804 | NOPS is the number of separate store instructions we are examining. | |
9805 | NOPS_TOTAL is the total number of instructions recognized by the peephole | |
9806 | pattern. | |
9807 | The first NOPS entries in OPERANDS are the source registers, the next | |
9808 | NOPS entries are memory operands. If this function is successful, *BASE is | |
9809 | set to the common base register of the memory accesses; *LOAD_OFFSET is set | |
9810 | to the first memory location's offset from that base register. REGS is an | |
9811 | array filled in with the source register numbers, REG_RTXS (if nonnull) is | |
9812 | likewise filled with the corresponding rtx's. | |
9813 | SAVED_ORDER (if nonnull), is an array filled in with an order that maps insn | |
9814 | numbers to to an ascending order of stores. | |
9815 | If CHECK_REGS is true, the sequence of registers in *REGS matches the stores | |
9816 | from ascending memory locations, and the function verifies that the register | |
9817 | numbers are themselves ascending. If CHECK_REGS is false, the register | |
9818 | numbers are stored in the order they are found in the operands. */ | |
9819 | static int | |
9820 | store_multiple_sequence (rtx *operands, int nops, int nops_total, | |
9821 | int *regs, rtx *reg_rtxs, int *saved_order, int *base, | |
9822 | HOST_WIDE_INT *load_offset, bool check_regs) | |
84ed5e79 | 9823 | { |
93b338c3 | 9824 | int unsorted_regs[MAX_LDM_STM_OPS]; |
37119410 | 9825 | rtx unsorted_reg_rtxs[MAX_LDM_STM_OPS]; |
93b338c3 BS |
9826 | HOST_WIDE_INT unsorted_offsets[MAX_LDM_STM_OPS]; |
9827 | int order[MAX_LDM_STM_OPS]; | |
ad076f4e | 9828 | int base_reg = -1; |
37119410 | 9829 | rtx base_reg_rtx = NULL; |
93b338c3 | 9830 | int i, stm_case; |
84ed5e79 | 9831 | |
93b338c3 BS |
9832 | /* Can only handle up to MAX_LDM_STM_OPS insns at present, though could be |
9833 | easily extended if required. */ | |
9834 | gcc_assert (nops >= 2 && nops <= MAX_LDM_STM_OPS); | |
84ed5e79 | 9835 | |
93b338c3 | 9836 | memset (order, 0, MAX_LDM_STM_OPS * sizeof (int)); |
f0b4bdd5 | 9837 | |
84ed5e79 | 9838 | /* Loop over the operands and check that the memory references are |
112cdef5 | 9839 | suitable (i.e. immediate offsets from the same base register). At |
84ed5e79 RE |
9840 | the same time, extract the target register, and the memory |
9841 | offsets. */ | |
9842 | for (i = 0; i < nops; i++) | |
9843 | { | |
9844 | rtx reg; | |
9845 | rtx offset; | |
9846 | ||
56636818 JL |
9847 | /* Convert a subreg of a mem into the mem itself. */ |
9848 | if (GET_CODE (operands[nops + i]) == SUBREG) | |
4e26a7af | 9849 | operands[nops + i] = alter_subreg (operands + (nops + i)); |
56636818 | 9850 | |
e6d29d15 | 9851 | gcc_assert (GET_CODE (operands[nops + i]) == MEM); |
84ed5e79 RE |
9852 | |
9853 | /* Don't reorder volatile memory references; it doesn't seem worth | |
9854 | looking for the case where the order is ok anyway. */ | |
9855 | if (MEM_VOLATILE_P (operands[nops + i])) | |
9856 | return 0; | |
9857 | ||
9858 | offset = const0_rtx; | |
9859 | ||
9860 | if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG | |
9861 | || (GET_CODE (reg) == SUBREG | |
9862 | && GET_CODE (reg = SUBREG_REG (reg)) == REG)) | |
9863 | || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS | |
9864 | && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0)) | |
9865 | == REG) | |
9866 | || (GET_CODE (reg) == SUBREG | |
9867 | && GET_CODE (reg = SUBREG_REG (reg)) == REG)) | |
9868 | && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1)) | |
9869 | == CONST_INT))) | |
9870 | { | |
37119410 BS |
9871 | unsorted_reg_rtxs[i] = (GET_CODE (operands[i]) == REG |
9872 | ? operands[i] : SUBREG_REG (operands[i])); | |
9873 | unsorted_regs[i] = REGNO (unsorted_reg_rtxs[i]); | |
9874 | ||
84ed5e79 | 9875 | if (i == 0) |
37119410 BS |
9876 | { |
9877 | base_reg = REGNO (reg); | |
9878 | base_reg_rtx = reg; | |
9879 | if (TARGET_THUMB1 && base_reg > LAST_LO_REGNUM) | |
9880 | return 0; | |
9881 | } | |
93b338c3 BS |
9882 | else if (base_reg != (int) REGNO (reg)) |
9883 | /* Not addressed from the same base register. */ | |
9884 | return 0; | |
84ed5e79 RE |
9885 | |
9886 | /* If it isn't an integer register, then we can't do this. */ | |
37119410 BS |
9887 | if (unsorted_regs[i] < 0 |
9888 | || (TARGET_THUMB1 && unsorted_regs[i] > LAST_LO_REGNUM) | |
9889 | || (TARGET_THUMB2 && unsorted_regs[i] == base_reg) | |
9890 | || (TARGET_THUMB2 && unsorted_regs[i] == SP_REGNUM) | |
9891 | || unsorted_regs[i] > 14) | |
84ed5e79 RE |
9892 | return 0; |
9893 | ||
9894 | unsorted_offsets[i] = INTVAL (offset); | |
93b338c3 BS |
9895 | if (i == 0 || unsorted_offsets[i] < unsorted_offsets[order[0]]) |
9896 | order[0] = i; | |
84ed5e79 RE |
9897 | } |
9898 | else | |
9899 | /* Not a suitable memory address. */ | |
9900 | return 0; | |
9901 | } | |
9902 | ||
9903 | /* All the useful information has now been extracted from the | |
9904 | operands into unsorted_regs and unsorted_offsets; additionally, | |
93b338c3 BS |
9905 | order[0] has been set to the lowest offset in the list. Sort |
9906 | the offsets into order, verifying that they are adjacent, and | |
9907 | check that the register numbers are ascending. */ | |
37119410 BS |
9908 | if (!compute_offset_order (nops, unsorted_offsets, order, |
9909 | check_regs ? unsorted_regs : NULL)) | |
93b338c3 | 9910 | return 0; |
84ed5e79 | 9911 | |
37119410 BS |
9912 | if (saved_order) |
9913 | memcpy (saved_order, order, sizeof order); | |
9914 | ||
84ed5e79 RE |
9915 | if (base) |
9916 | { | |
9917 | *base = base_reg; | |
9918 | ||
9919 | for (i = 0; i < nops; i++) | |
37119410 BS |
9920 | { |
9921 | regs[i] = unsorted_regs[check_regs ? order[i] : i]; | |
9922 | if (reg_rtxs) | |
9923 | reg_rtxs[i] = unsorted_reg_rtxs[check_regs ? order[i] : i]; | |
9924 | } | |
84ed5e79 RE |
9925 | |
9926 | *load_offset = unsorted_offsets[order[0]]; | |
9927 | } | |
9928 | ||
37119410 BS |
9929 | if (TARGET_THUMB1 |
9930 | && !peep2_reg_dead_p (nops_total, base_reg_rtx)) | |
9931 | return 0; | |
9932 | ||
84ed5e79 | 9933 | if (unsorted_offsets[order[0]] == 0) |
93b338c3 BS |
9934 | stm_case = 1; /* stmia */ |
9935 | else if (TARGET_ARM && unsorted_offsets[order[0]] == 4) | |
9936 | stm_case = 2; /* stmib */ | |
9937 | else if (TARGET_ARM && unsorted_offsets[order[nops - 1]] == 0) | |
9938 | stm_case = 3; /* stmda */ | |
37119410 | 9939 | else if (TARGET_32BIT && unsorted_offsets[order[nops - 1]] == -4) |
93b338c3 BS |
9940 | stm_case = 4; /* stmdb */ |
9941 | else | |
9942 | return 0; | |
84ed5e79 | 9943 | |
93b338c3 BS |
9944 | if (!multiple_operation_profitable_p (false, nops, 0)) |
9945 | return 0; | |
84ed5e79 | 9946 | |
93b338c3 | 9947 | return stm_case; |
84ed5e79 | 9948 | } |
ff9940b0 | 9949 | \f |
6354dc9b | 9950 | /* Routines for use in generating RTL. */ |
1d6e90ac | 9951 | |
37119410 BS |
9952 | /* Generate a load-multiple instruction. COUNT is the number of loads in |
9953 | the instruction; REGS and MEMS are arrays containing the operands. | |
9954 | BASEREG is the base register to be used in addressing the memory operands. | |
9955 | WBACK_OFFSET is nonzero if the instruction should update the base | |
9956 | register. */ | |
9957 | ||
9958 | static rtx | |
9959 | arm_gen_load_multiple_1 (int count, int *regs, rtx *mems, rtx basereg, | |
9960 | HOST_WIDE_INT wback_offset) | |
ff9940b0 RE |
9961 | { |
9962 | int i = 0, j; | |
9963 | rtx result; | |
ff9940b0 | 9964 | |
8f4c6e28 | 9965 | if (!multiple_operation_profitable_p (false, count, 0)) |
d19fb8e3 NC |
9966 | { |
9967 | rtx seq; | |
f676971a | 9968 | |
d19fb8e3 | 9969 | start_sequence (); |
f676971a | 9970 | |
d19fb8e3 | 9971 | for (i = 0; i < count; i++) |
37119410 | 9972 | emit_move_insn (gen_rtx_REG (SImode, regs[i]), mems[i]); |
d19fb8e3 | 9973 | |
37119410 BS |
9974 | if (wback_offset != 0) |
9975 | emit_move_insn (basereg, plus_constant (basereg, wback_offset)); | |
d19fb8e3 | 9976 | |
2f937369 | 9977 | seq = get_insns (); |
d19fb8e3 | 9978 | end_sequence (); |
f676971a | 9979 | |
d19fb8e3 NC |
9980 | return seq; |
9981 | } | |
9982 | ||
43cffd11 | 9983 | result = gen_rtx_PARALLEL (VOIDmode, |
37119410 BS |
9984 | rtvec_alloc (count + (wback_offset != 0 ? 1 : 0))); |
9985 | if (wback_offset != 0) | |
f3bb6135 | 9986 | { |
ff9940b0 | 9987 | XVECEXP (result, 0, 0) |
37119410 BS |
9988 | = gen_rtx_SET (VOIDmode, basereg, |
9989 | plus_constant (basereg, wback_offset)); | |
ff9940b0 RE |
9990 | i = 1; |
9991 | count++; | |
f3bb6135 RE |
9992 | } |
9993 | ||
ff9940b0 | 9994 | for (j = 0; i < count; i++, j++) |
37119410 BS |
9995 | XVECEXP (result, 0, i) |
9996 | = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regs[j]), mems[j]); | |
50ed9cea | 9997 | |
ff9940b0 RE |
9998 | return result; |
9999 | } | |
10000 | ||
37119410 BS |
10001 | /* Generate a store-multiple instruction. COUNT is the number of stores in |
10002 | the instruction; REGS and MEMS are arrays containing the operands. | |
10003 | BASEREG is the base register to be used in addressing the memory operands. | |
10004 | WBACK_OFFSET is nonzero if the instruction should update the base | |
10005 | register. */ | |
10006 | ||
10007 | static rtx | |
10008 | arm_gen_store_multiple_1 (int count, int *regs, rtx *mems, rtx basereg, | |
10009 | HOST_WIDE_INT wback_offset) | |
ff9940b0 RE |
10010 | { |
10011 | int i = 0, j; | |
10012 | rtx result; | |
ff9940b0 | 10013 | |
37119410 BS |
10014 | if (GET_CODE (basereg) == PLUS) |
10015 | basereg = XEXP (basereg, 0); | |
10016 | ||
8f4c6e28 | 10017 | if (!multiple_operation_profitable_p (false, count, 0)) |
d19fb8e3 NC |
10018 | { |
10019 | rtx seq; | |
f676971a | 10020 | |
d19fb8e3 | 10021 | start_sequence (); |
f676971a | 10022 | |
d19fb8e3 | 10023 | for (i = 0; i < count; i++) |
37119410 | 10024 | emit_move_insn (mems[i], gen_rtx_REG (SImode, regs[i])); |
d19fb8e3 | 10025 | |
37119410 BS |
10026 | if (wback_offset != 0) |
10027 | emit_move_insn (basereg, plus_constant (basereg, wback_offset)); | |
d19fb8e3 | 10028 | |
2f937369 | 10029 | seq = get_insns (); |
d19fb8e3 | 10030 | end_sequence (); |
f676971a | 10031 | |
d19fb8e3 NC |
10032 | return seq; |
10033 | } | |
10034 | ||
43cffd11 | 10035 | result = gen_rtx_PARALLEL (VOIDmode, |
37119410 BS |
10036 | rtvec_alloc (count + (wback_offset != 0 ? 1 : 0))); |
10037 | if (wback_offset != 0) | |
f3bb6135 | 10038 | { |
ff9940b0 | 10039 | XVECEXP (result, 0, 0) |
37119410 BS |
10040 | = gen_rtx_SET (VOIDmode, basereg, |
10041 | plus_constant (basereg, wback_offset)); | |
ff9940b0 RE |
10042 | i = 1; |
10043 | count++; | |
f3bb6135 RE |
10044 | } |
10045 | ||
ff9940b0 | 10046 | for (j = 0; i < count; i++, j++) |
37119410 BS |
10047 | XVECEXP (result, 0, i) |
10048 | = gen_rtx_SET (VOIDmode, mems[j], gen_rtx_REG (SImode, regs[j])); | |
10049 | ||
10050 | return result; | |
10051 | } | |
10052 | ||
10053 | /* Generate either a load-multiple or a store-multiple instruction. This | |
10054 | function can be used in situations where we can start with a single MEM | |
10055 | rtx and adjust its address upwards. | |
10056 | COUNT is the number of operations in the instruction, not counting a | |
10057 | possible update of the base register. REGS is an array containing the | |
10058 | register operands. | |
10059 | BASEREG is the base register to be used in addressing the memory operands, | |
10060 | which are constructed from BASEMEM. | |
10061 | WRITE_BACK specifies whether the generated instruction should include an | |
10062 | update of the base register. | |
10063 | OFFSETP is used to pass an offset to and from this function; this offset | |
10064 | is not used when constructing the address (instead BASEMEM should have an | |
10065 | appropriate offset in its address), it is used only for setting | |
10066 | MEM_OFFSET. It is updated only if WRITE_BACK is true.*/ | |
10067 | ||
10068 | static rtx | |
10069 | arm_gen_multiple_op (bool is_load, int *regs, int count, rtx basereg, | |
10070 | bool write_back, rtx basemem, HOST_WIDE_INT *offsetp) | |
10071 | { | |
10072 | rtx mems[MAX_LDM_STM_OPS]; | |
10073 | HOST_WIDE_INT offset = *offsetp; | |
10074 | int i; | |
10075 | ||
10076 | gcc_assert (count <= MAX_LDM_STM_OPS); | |
10077 | ||
10078 | if (GET_CODE (basereg) == PLUS) | |
10079 | basereg = XEXP (basereg, 0); | |
10080 | ||
10081 | for (i = 0; i < count; i++) | |
f3bb6135 | 10082 | { |
37119410 BS |
10083 | rtx addr = plus_constant (basereg, i * 4); |
10084 | mems[i] = adjust_automodify_address_nv (basemem, SImode, addr, offset); | |
10085 | offset += 4; | |
f3bb6135 RE |
10086 | } |
10087 | ||
50ed9cea RH |
10088 | if (write_back) |
10089 | *offsetp = offset; | |
10090 | ||
37119410 BS |
10091 | if (is_load) |
10092 | return arm_gen_load_multiple_1 (count, regs, mems, basereg, | |
10093 | write_back ? 4 * count : 0); | |
10094 | else | |
10095 | return arm_gen_store_multiple_1 (count, regs, mems, basereg, | |
10096 | write_back ? 4 * count : 0); | |
10097 | } | |
10098 | ||
10099 | rtx | |
10100 | arm_gen_load_multiple (int *regs, int count, rtx basereg, int write_back, | |
10101 | rtx basemem, HOST_WIDE_INT *offsetp) | |
10102 | { | |
10103 | return arm_gen_multiple_op (TRUE, regs, count, basereg, write_back, basemem, | |
10104 | offsetp); | |
10105 | } | |
10106 | ||
10107 | rtx | |
10108 | arm_gen_store_multiple (int *regs, int count, rtx basereg, int write_back, | |
10109 | rtx basemem, HOST_WIDE_INT *offsetp) | |
10110 | { | |
10111 | return arm_gen_multiple_op (FALSE, regs, count, basereg, write_back, basemem, | |
10112 | offsetp); | |
10113 | } | |
10114 | ||
10115 | /* Called from a peephole2 expander to turn a sequence of loads into an | |
10116 | LDM instruction. OPERANDS are the operands found by the peephole matcher; | |
10117 | NOPS indicates how many separate loads we are trying to combine. SORT_REGS | |
10118 | is true if we can reorder the registers because they are used commutatively | |
10119 | subsequently. | |
10120 | Returns true iff we could generate a new instruction. */ | |
10121 | ||
10122 | bool | |
10123 | gen_ldm_seq (rtx *operands, int nops, bool sort_regs) | |
10124 | { | |
10125 | int regs[MAX_LDM_STM_OPS], mem_order[MAX_LDM_STM_OPS]; | |
10126 | rtx mems[MAX_LDM_STM_OPS]; | |
10127 | int i, j, base_reg; | |
10128 | rtx base_reg_rtx; | |
10129 | HOST_WIDE_INT offset; | |
10130 | int write_back = FALSE; | |
10131 | int ldm_case; | |
10132 | rtx addr; | |
10133 | ||
10134 | ldm_case = load_multiple_sequence (operands, nops, regs, mem_order, | |
10135 | &base_reg, &offset, !sort_regs); | |
10136 | ||
10137 | if (ldm_case == 0) | |
10138 | return false; | |
10139 | ||
10140 | if (sort_regs) | |
10141 | for (i = 0; i < nops - 1; i++) | |
10142 | for (j = i + 1; j < nops; j++) | |
10143 | if (regs[i] > regs[j]) | |
10144 | { | |
10145 | int t = regs[i]; | |
10146 | regs[i] = regs[j]; | |
10147 | regs[j] = t; | |
10148 | } | |
10149 | base_reg_rtx = gen_rtx_REG (Pmode, base_reg); | |
10150 | ||
10151 | if (TARGET_THUMB1) | |
10152 | { | |
10153 | gcc_assert (peep2_reg_dead_p (nops, base_reg_rtx)); | |
10154 | gcc_assert (ldm_case == 1 || ldm_case == 5); | |
10155 | write_back = TRUE; | |
10156 | } | |
10157 | ||
10158 | if (ldm_case == 5) | |
10159 | { | |
10160 | rtx newbase = TARGET_THUMB1 ? base_reg_rtx : gen_rtx_REG (SImode, regs[0]); | |
10161 | emit_insn (gen_addsi3 (newbase, base_reg_rtx, GEN_INT (offset))); | |
10162 | offset = 0; | |
10163 | if (!TARGET_THUMB1) | |
10164 | { | |
10165 | base_reg = regs[0]; | |
10166 | base_reg_rtx = newbase; | |
10167 | } | |
10168 | } | |
10169 | ||
10170 | for (i = 0; i < nops; i++) | |
10171 | { | |
10172 | addr = plus_constant (base_reg_rtx, offset + i * 4); | |
10173 | mems[i] = adjust_automodify_address_nv (operands[nops + mem_order[i]], | |
10174 | SImode, addr, 0); | |
10175 | } | |
10176 | emit_insn (arm_gen_load_multiple_1 (nops, regs, mems, base_reg_rtx, | |
10177 | write_back ? offset + i * 4 : 0)); | |
10178 | return true; | |
10179 | } | |
10180 | ||
10181 | /* Called from a peephole2 expander to turn a sequence of stores into an | |
10182 | STM instruction. OPERANDS are the operands found by the peephole matcher; | |
10183 | NOPS indicates how many separate stores we are trying to combine. | |
10184 | Returns true iff we could generate a new instruction. */ | |
10185 | ||
10186 | bool | |
10187 | gen_stm_seq (rtx *operands, int nops) | |
10188 | { | |
10189 | int i; | |
10190 | int regs[MAX_LDM_STM_OPS], mem_order[MAX_LDM_STM_OPS]; | |
10191 | rtx mems[MAX_LDM_STM_OPS]; | |
10192 | int base_reg; | |
10193 | rtx base_reg_rtx; | |
10194 | HOST_WIDE_INT offset; | |
10195 | int write_back = FALSE; | |
10196 | int stm_case; | |
10197 | rtx addr; | |
10198 | bool base_reg_dies; | |
10199 | ||
10200 | stm_case = store_multiple_sequence (operands, nops, nops, regs, NULL, | |
10201 | mem_order, &base_reg, &offset, true); | |
10202 | ||
10203 | if (stm_case == 0) | |
10204 | return false; | |
10205 | ||
10206 | base_reg_rtx = gen_rtx_REG (Pmode, base_reg); | |
10207 | ||
10208 | base_reg_dies = peep2_reg_dead_p (nops, base_reg_rtx); | |
10209 | if (TARGET_THUMB1) | |
10210 | { | |
10211 | gcc_assert (base_reg_dies); | |
10212 | write_back = TRUE; | |
10213 | } | |
10214 | ||
10215 | if (stm_case == 5) | |
10216 | { | |
10217 | gcc_assert (base_reg_dies); | |
10218 | emit_insn (gen_addsi3 (base_reg_rtx, base_reg_rtx, GEN_INT (offset))); | |
10219 | offset = 0; | |
10220 | } | |
10221 | ||
10222 | addr = plus_constant (base_reg_rtx, offset); | |
10223 | ||
10224 | for (i = 0; i < nops; i++) | |
10225 | { | |
10226 | addr = plus_constant (base_reg_rtx, offset + i * 4); | |
10227 | mems[i] = adjust_automodify_address_nv (operands[nops + mem_order[i]], | |
10228 | SImode, addr, 0); | |
10229 | } | |
10230 | emit_insn (arm_gen_store_multiple_1 (nops, regs, mems, base_reg_rtx, | |
10231 | write_back ? offset + i * 4 : 0)); | |
10232 | return true; | |
10233 | } | |
10234 | ||
10235 | /* Called from a peephole2 expander to turn a sequence of stores that are | |
10236 | preceded by constant loads into an STM instruction. OPERANDS are the | |
10237 | operands found by the peephole matcher; NOPS indicates how many | |
10238 | separate stores we are trying to combine; there are 2 * NOPS | |
10239 | instructions in the peephole. | |
10240 | Returns true iff we could generate a new instruction. */ | |
10241 | ||
10242 | bool | |
10243 | gen_const_stm_seq (rtx *operands, int nops) | |
10244 | { | |
10245 | int regs[MAX_LDM_STM_OPS], sorted_regs[MAX_LDM_STM_OPS]; | |
10246 | int reg_order[MAX_LDM_STM_OPS], mem_order[MAX_LDM_STM_OPS]; | |
10247 | rtx reg_rtxs[MAX_LDM_STM_OPS], orig_reg_rtxs[MAX_LDM_STM_OPS]; | |
10248 | rtx mems[MAX_LDM_STM_OPS]; | |
10249 | int base_reg; | |
10250 | rtx base_reg_rtx; | |
10251 | HOST_WIDE_INT offset; | |
10252 | int write_back = FALSE; | |
10253 | int stm_case; | |
10254 | rtx addr; | |
10255 | bool base_reg_dies; | |
10256 | int i, j; | |
10257 | HARD_REG_SET allocated; | |
10258 | ||
10259 | stm_case = store_multiple_sequence (operands, nops, 2 * nops, regs, reg_rtxs, | |
10260 | mem_order, &base_reg, &offset, false); | |
10261 | ||
10262 | if (stm_case == 0) | |
10263 | return false; | |
10264 | ||
10265 | memcpy (orig_reg_rtxs, reg_rtxs, sizeof orig_reg_rtxs); | |
10266 | ||
10267 | /* If the same register is used more than once, try to find a free | |
10268 | register. */ | |
10269 | CLEAR_HARD_REG_SET (allocated); | |
10270 | for (i = 0; i < nops; i++) | |
10271 | { | |
10272 | for (j = i + 1; j < nops; j++) | |
10273 | if (regs[i] == regs[j]) | |
10274 | { | |
10275 | rtx t = peep2_find_free_register (0, nops * 2, | |
10276 | TARGET_THUMB1 ? "l" : "r", | |
10277 | SImode, &allocated); | |
10278 | if (t == NULL_RTX) | |
10279 | return false; | |
10280 | reg_rtxs[i] = t; | |
10281 | regs[i] = REGNO (t); | |
10282 | } | |
10283 | } | |
10284 | ||
10285 | /* Compute an ordering that maps the register numbers to an ascending | |
10286 | sequence. */ | |
10287 | reg_order[0] = 0; | |
10288 | for (i = 0; i < nops; i++) | |
10289 | if (regs[i] < regs[reg_order[0]]) | |
10290 | reg_order[0] = i; | |
10291 | ||
10292 | for (i = 1; i < nops; i++) | |
10293 | { | |
10294 | int this_order = reg_order[i - 1]; | |
10295 | for (j = 0; j < nops; j++) | |
10296 | if (regs[j] > regs[reg_order[i - 1]] | |
10297 | && (this_order == reg_order[i - 1] | |
10298 | || regs[j] < regs[this_order])) | |
10299 | this_order = j; | |
10300 | reg_order[i] = this_order; | |
10301 | } | |
10302 | ||
10303 | /* Ensure that registers that must be live after the instruction end | |
10304 | up with the correct value. */ | |
10305 | for (i = 0; i < nops; i++) | |
10306 | { | |
10307 | int this_order = reg_order[i]; | |
10308 | if ((this_order != mem_order[i] | |
10309 | || orig_reg_rtxs[this_order] != reg_rtxs[this_order]) | |
10310 | && !peep2_reg_dead_p (nops * 2, orig_reg_rtxs[this_order])) | |
10311 | return false; | |
10312 | } | |
10313 | ||
10314 | /* Load the constants. */ | |
10315 | for (i = 0; i < nops; i++) | |
10316 | { | |
10317 | rtx op = operands[2 * nops + mem_order[i]]; | |
10318 | sorted_regs[i] = regs[reg_order[i]]; | |
10319 | emit_move_insn (reg_rtxs[reg_order[i]], op); | |
10320 | } | |
10321 | ||
10322 | base_reg_rtx = gen_rtx_REG (Pmode, base_reg); | |
10323 | ||
10324 | base_reg_dies = peep2_reg_dead_p (nops * 2, base_reg_rtx); | |
10325 | if (TARGET_THUMB1) | |
10326 | { | |
10327 | gcc_assert (base_reg_dies); | |
10328 | write_back = TRUE; | |
10329 | } | |
10330 | ||
10331 | if (stm_case == 5) | |
10332 | { | |
10333 | gcc_assert (base_reg_dies); | |
10334 | emit_insn (gen_addsi3 (base_reg_rtx, base_reg_rtx, GEN_INT (offset))); | |
10335 | offset = 0; | |
10336 | } | |
10337 | ||
10338 | addr = plus_constant (base_reg_rtx, offset); | |
10339 | ||
10340 | for (i = 0; i < nops; i++) | |
10341 | { | |
10342 | addr = plus_constant (base_reg_rtx, offset + i * 4); | |
10343 | mems[i] = adjust_automodify_address_nv (operands[nops + mem_order[i]], | |
10344 | SImode, addr, 0); | |
10345 | } | |
10346 | emit_insn (arm_gen_store_multiple_1 (nops, sorted_regs, mems, base_reg_rtx, | |
10347 | write_back ? offset + i * 4 : 0)); | |
10348 | return true; | |
ff9940b0 RE |
10349 | } |
10350 | ||
880e2516 | 10351 | int |
70128ad9 | 10352 | arm_gen_movmemqi (rtx *operands) |
880e2516 RE |
10353 | { |
10354 | HOST_WIDE_INT in_words_to_go, out_words_to_go, last_bytes; | |
50ed9cea | 10355 | HOST_WIDE_INT srcoffset, dstoffset; |
ad076f4e | 10356 | int i; |
50ed9cea | 10357 | rtx src, dst, srcbase, dstbase; |
880e2516 | 10358 | rtx part_bytes_reg = NULL; |
56636818 | 10359 | rtx mem; |
880e2516 RE |
10360 | |
10361 | if (GET_CODE (operands[2]) != CONST_INT | |
10362 | || GET_CODE (operands[3]) != CONST_INT | |
10363 | || INTVAL (operands[2]) > 64 | |
10364 | || INTVAL (operands[3]) & 3) | |
10365 | return 0; | |
10366 | ||
50ed9cea RH |
10367 | dstbase = operands[0]; |
10368 | srcbase = operands[1]; | |
56636818 | 10369 | |
50ed9cea RH |
10370 | dst = copy_to_mode_reg (SImode, XEXP (dstbase, 0)); |
10371 | src = copy_to_mode_reg (SImode, XEXP (srcbase, 0)); | |
880e2516 | 10372 | |
e9d7b180 | 10373 | in_words_to_go = ARM_NUM_INTS (INTVAL (operands[2])); |
880e2516 RE |
10374 | out_words_to_go = INTVAL (operands[2]) / 4; |
10375 | last_bytes = INTVAL (operands[2]) & 3; | |
50ed9cea | 10376 | dstoffset = srcoffset = 0; |
880e2516 RE |
10377 | |
10378 | if (out_words_to_go != in_words_to_go && ((in_words_to_go - 1) & 3) != 0) | |
43cffd11 | 10379 | part_bytes_reg = gen_rtx_REG (SImode, (in_words_to_go - 1) & 3); |
880e2516 RE |
10380 | |
10381 | for (i = 0; in_words_to_go >= 2; i+=4) | |
10382 | { | |
bd9c7e23 | 10383 | if (in_words_to_go > 4) |
37119410 BS |
10384 | emit_insn (arm_gen_load_multiple (arm_regs_in_sequence, 4, src, |
10385 | TRUE, srcbase, &srcoffset)); | |
bd9c7e23 | 10386 | else |
37119410 BS |
10387 | emit_insn (arm_gen_load_multiple (arm_regs_in_sequence, in_words_to_go, |
10388 | src, FALSE, srcbase, | |
10389 | &srcoffset)); | |
bd9c7e23 | 10390 | |
880e2516 RE |
10391 | if (out_words_to_go) |
10392 | { | |
bd9c7e23 | 10393 | if (out_words_to_go > 4) |
37119410 BS |
10394 | emit_insn (arm_gen_store_multiple (arm_regs_in_sequence, 4, dst, |
10395 | TRUE, dstbase, &dstoffset)); | |
bd9c7e23 | 10396 | else if (out_words_to_go != 1) |
37119410 BS |
10397 | emit_insn (arm_gen_store_multiple (arm_regs_in_sequence, |
10398 | out_words_to_go, dst, | |
bd9c7e23 | 10399 | (last_bytes == 0 |
56636818 | 10400 | ? FALSE : TRUE), |
50ed9cea | 10401 | dstbase, &dstoffset)); |
880e2516 RE |
10402 | else |
10403 | { | |
50ed9cea | 10404 | mem = adjust_automodify_address (dstbase, SImode, dst, dstoffset); |
43cffd11 | 10405 | emit_move_insn (mem, gen_rtx_REG (SImode, 0)); |
bd9c7e23 | 10406 | if (last_bytes != 0) |
50ed9cea RH |
10407 | { |
10408 | emit_insn (gen_addsi3 (dst, dst, GEN_INT (4))); | |
10409 | dstoffset += 4; | |
10410 | } | |
880e2516 RE |
10411 | } |
10412 | } | |
10413 | ||
10414 | in_words_to_go -= in_words_to_go < 4 ? in_words_to_go : 4; | |
10415 | out_words_to_go -= out_words_to_go < 4 ? out_words_to_go : 4; | |
10416 | } | |
10417 | ||
10418 | /* OUT_WORDS_TO_GO will be zero here if there are byte stores to do. */ | |
10419 | if (out_words_to_go) | |
62b10bbc NC |
10420 | { |
10421 | rtx sreg; | |
f676971a | 10422 | |
50ed9cea RH |
10423 | mem = adjust_automodify_address (srcbase, SImode, src, srcoffset); |
10424 | sreg = copy_to_reg (mem); | |
10425 | ||
10426 | mem = adjust_automodify_address (dstbase, SImode, dst, dstoffset); | |
62b10bbc | 10427 | emit_move_insn (mem, sreg); |
62b10bbc | 10428 | in_words_to_go--; |
f676971a | 10429 | |
e6d29d15 | 10430 | gcc_assert (!in_words_to_go); /* Sanity check */ |
62b10bbc | 10431 | } |
880e2516 RE |
10432 | |
10433 | if (in_words_to_go) | |
10434 | { | |
e6d29d15 | 10435 | gcc_assert (in_words_to_go > 0); |
880e2516 | 10436 | |
50ed9cea | 10437 | mem = adjust_automodify_address (srcbase, SImode, src, srcoffset); |
56636818 | 10438 | part_bytes_reg = copy_to_mode_reg (SImode, mem); |
880e2516 RE |
10439 | } |
10440 | ||
e6d29d15 | 10441 | gcc_assert (!last_bytes || part_bytes_reg); |
d5b7b3ae | 10442 | |
880e2516 RE |
10443 | if (BYTES_BIG_ENDIAN && last_bytes) |
10444 | { | |
10445 | rtx tmp = gen_reg_rtx (SImode); | |
10446 | ||
6354dc9b | 10447 | /* The bytes we want are in the top end of the word. */ |
bee06f3d RE |
10448 | emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, |
10449 | GEN_INT (8 * (4 - last_bytes)))); | |
880e2516 | 10450 | part_bytes_reg = tmp; |
f676971a | 10451 | |
880e2516 RE |
10452 | while (last_bytes) |
10453 | { | |
50ed9cea RH |
10454 | mem = adjust_automodify_address (dstbase, QImode, |
10455 | plus_constant (dst, last_bytes - 1), | |
10456 | dstoffset + last_bytes - 1); | |
5d5603e2 BS |
10457 | emit_move_insn (mem, gen_lowpart (QImode, part_bytes_reg)); |
10458 | ||
880e2516 RE |
10459 | if (--last_bytes) |
10460 | { | |
10461 | tmp = gen_reg_rtx (SImode); | |
10462 | emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (8))); | |
10463 | part_bytes_reg = tmp; | |
10464 | } | |
10465 | } | |
f676971a | 10466 | |
880e2516 RE |
10467 | } |
10468 | else | |
10469 | { | |
d5b7b3ae | 10470 | if (last_bytes > 1) |
880e2516 | 10471 | { |
50ed9cea | 10472 | mem = adjust_automodify_address (dstbase, HImode, dst, dstoffset); |
5d5603e2 | 10473 | emit_move_insn (mem, gen_lowpart (HImode, part_bytes_reg)); |
d5b7b3ae RE |
10474 | last_bytes -= 2; |
10475 | if (last_bytes) | |
880e2516 RE |
10476 | { |
10477 | rtx tmp = gen_reg_rtx (SImode); | |
a556fd39 | 10478 | emit_insn (gen_addsi3 (dst, dst, const2_rtx)); |
d5b7b3ae | 10479 | emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (16))); |
880e2516 | 10480 | part_bytes_reg = tmp; |
50ed9cea | 10481 | dstoffset += 2; |
880e2516 RE |
10482 | } |
10483 | } | |
f676971a | 10484 | |
d5b7b3ae RE |
10485 | if (last_bytes) |
10486 | { | |
50ed9cea | 10487 | mem = adjust_automodify_address (dstbase, QImode, dst, dstoffset); |
5d5603e2 | 10488 | emit_move_insn (mem, gen_lowpart (QImode, part_bytes_reg)); |
d5b7b3ae | 10489 | } |
880e2516 RE |
10490 | } |
10491 | ||
10492 | return 1; | |
10493 | } | |
10494 | ||
03f1640c RE |
10495 | /* Select a dominance comparison mode if possible for a test of the general |
10496 | form (OP (COND_OR (X) (Y)) (const_int 0)). We support three forms. | |
f676971a | 10497 | COND_OR == DOM_CC_X_AND_Y => (X && Y) |
03f1640c | 10498 | COND_OR == DOM_CC_NX_OR_Y => ((! X) || Y) |
f676971a | 10499 | COND_OR == DOM_CC_X_OR_Y => (X || Y) |
03f1640c | 10500 | In all cases OP will be either EQ or NE, but we don't need to know which |
f676971a | 10501 | here. If we are unable to support a dominance comparison we return |
03f1640c RE |
10502 | CC mode. This will then fail to match for the RTL expressions that |
10503 | generate this call. */ | |
03f1640c | 10504 | enum machine_mode |
e32bac5b | 10505 | arm_select_dominance_cc_mode (rtx x, rtx y, HOST_WIDE_INT cond_or) |
84ed5e79 RE |
10506 | { |
10507 | enum rtx_code cond1, cond2; | |
10508 | int swapped = 0; | |
10509 | ||
10510 | /* Currently we will probably get the wrong result if the individual | |
10511 | comparisons are not simple. This also ensures that it is safe to | |
956d6950 | 10512 | reverse a comparison if necessary. */ |
84ed5e79 RE |
10513 | if ((arm_select_cc_mode (cond1 = GET_CODE (x), XEXP (x, 0), XEXP (x, 1)) |
10514 | != CCmode) | |
10515 | || (arm_select_cc_mode (cond2 = GET_CODE (y), XEXP (y, 0), XEXP (y, 1)) | |
10516 | != CCmode)) | |
10517 | return CCmode; | |
10518 | ||
1646cf41 RE |
10519 | /* The if_then_else variant of this tests the second condition if the |
10520 | first passes, but is true if the first fails. Reverse the first | |
10521 | condition to get a true "inclusive-or" expression. */ | |
03f1640c | 10522 | if (cond_or == DOM_CC_NX_OR_Y) |
84ed5e79 RE |
10523 | cond1 = reverse_condition (cond1); |
10524 | ||
10525 | /* If the comparisons are not equal, and one doesn't dominate the other, | |
10526 | then we can't do this. */ | |
f676971a | 10527 | if (cond1 != cond2 |
5895f793 RE |
10528 | && !comparison_dominates_p (cond1, cond2) |
10529 | && (swapped = 1, !comparison_dominates_p (cond2, cond1))) | |
84ed5e79 RE |
10530 | return CCmode; |
10531 | ||
10532 | if (swapped) | |
10533 | { | |
10534 | enum rtx_code temp = cond1; | |
10535 | cond1 = cond2; | |
10536 | cond2 = temp; | |
10537 | } | |
10538 | ||
10539 | switch (cond1) | |
10540 | { | |
10541 | case EQ: | |
e6d29d15 | 10542 | if (cond_or == DOM_CC_X_AND_Y) |
84ed5e79 RE |
10543 | return CC_DEQmode; |
10544 | ||
10545 | switch (cond2) | |
10546 | { | |
e6d29d15 | 10547 | case EQ: return CC_DEQmode; |
84ed5e79 RE |
10548 | case LE: return CC_DLEmode; |
10549 | case LEU: return CC_DLEUmode; | |
10550 | case GE: return CC_DGEmode; | |
10551 | case GEU: return CC_DGEUmode; | |
e6d29d15 | 10552 | default: gcc_unreachable (); |
84ed5e79 RE |
10553 | } |
10554 | ||
84ed5e79 | 10555 | case LT: |
e6d29d15 | 10556 | if (cond_or == DOM_CC_X_AND_Y) |
84ed5e79 | 10557 | return CC_DLTmode; |
e0b92319 | 10558 | |
e6d29d15 NS |
10559 | switch (cond2) |
10560 | { | |
10561 | case LT: | |
10562 | return CC_DLTmode; | |
10563 | case LE: | |
10564 | return CC_DLEmode; | |
10565 | case NE: | |
10566 | return CC_DNEmode; | |
10567 | default: | |
10568 | gcc_unreachable (); | |
10569 | } | |
84ed5e79 RE |
10570 | |
10571 | case GT: | |
e6d29d15 | 10572 | if (cond_or == DOM_CC_X_AND_Y) |
84ed5e79 | 10573 | return CC_DGTmode; |
e6d29d15 NS |
10574 | |
10575 | switch (cond2) | |
10576 | { | |
10577 | case GT: | |
10578 | return CC_DGTmode; | |
10579 | case GE: | |
10580 | return CC_DGEmode; | |
10581 | case NE: | |
10582 | return CC_DNEmode; | |
10583 | default: | |
10584 | gcc_unreachable (); | |
10585 | } | |
f676971a | 10586 | |
84ed5e79 | 10587 | case LTU: |
e6d29d15 | 10588 | if (cond_or == DOM_CC_X_AND_Y) |
84ed5e79 | 10589 | return CC_DLTUmode; |
e6d29d15 NS |
10590 | |
10591 | switch (cond2) | |
10592 | { | |
10593 | case LTU: | |
10594 | return CC_DLTUmode; | |
10595 | case LEU: | |
10596 | return CC_DLEUmode; | |
10597 | case NE: | |
10598 | return CC_DNEmode; | |
10599 | default: | |
10600 | gcc_unreachable (); | |
10601 | } | |
84ed5e79 RE |
10602 | |
10603 | case GTU: | |
e6d29d15 | 10604 | if (cond_or == DOM_CC_X_AND_Y) |
84ed5e79 | 10605 | return CC_DGTUmode; |
e0b92319 | 10606 | |
e6d29d15 NS |
10607 | switch (cond2) |
10608 | { | |
10609 | case GTU: | |
10610 | return CC_DGTUmode; | |
10611 | case GEU: | |
10612 | return CC_DGEUmode; | |
10613 | case NE: | |
10614 | return CC_DNEmode; | |
10615 | default: | |
10616 | gcc_unreachable (); | |
10617 | } | |
84ed5e79 RE |
10618 | |
10619 | /* The remaining cases only occur when both comparisons are the | |
10620 | same. */ | |
10621 | case NE: | |
e6d29d15 | 10622 | gcc_assert (cond1 == cond2); |
84ed5e79 RE |
10623 | return CC_DNEmode; |
10624 | ||
10625 | case LE: | |
e6d29d15 | 10626 | gcc_assert (cond1 == cond2); |
84ed5e79 RE |
10627 | return CC_DLEmode; |
10628 | ||
10629 | case GE: | |
e6d29d15 | 10630 | gcc_assert (cond1 == cond2); |
84ed5e79 RE |
10631 | return CC_DGEmode; |
10632 | ||
10633 | case LEU: | |
e6d29d15 | 10634 | gcc_assert (cond1 == cond2); |
84ed5e79 RE |
10635 | return CC_DLEUmode; |
10636 | ||
10637 | case GEU: | |
e6d29d15 | 10638 | gcc_assert (cond1 == cond2); |
84ed5e79 | 10639 | return CC_DGEUmode; |
ad076f4e RE |
10640 | |
10641 | default: | |
e6d29d15 | 10642 | gcc_unreachable (); |
84ed5e79 | 10643 | } |
84ed5e79 RE |
10644 | } |
10645 | ||
10646 | enum machine_mode | |
e32bac5b | 10647 | arm_select_cc_mode (enum rtx_code op, rtx x, rtx y) |
84ed5e79 RE |
10648 | { |
10649 | /* All floating point compares return CCFP if it is an equality | |
10650 | comparison, and CCFPE otherwise. */ | |
10651 | if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) | |
e45b72c4 RE |
10652 | { |
10653 | switch (op) | |
10654 | { | |
10655 | case EQ: | |
10656 | case NE: | |
10657 | case UNORDERED: | |
10658 | case ORDERED: | |
10659 | case UNLT: | |
10660 | case UNLE: | |
10661 | case UNGT: | |
10662 | case UNGE: | |
10663 | case UNEQ: | |
10664 | case LTGT: | |
10665 | return CCFPmode; | |
10666 | ||
10667 | case LT: | |
10668 | case LE: | |
10669 | case GT: | |
10670 | case GE: | |
9b66ebb1 | 10671 | if (TARGET_HARD_FLOAT && TARGET_MAVERICK) |
9b6b54e2 | 10672 | return CCFPmode; |
e45b72c4 RE |
10673 | return CCFPEmode; |
10674 | ||
10675 | default: | |
e6d29d15 | 10676 | gcc_unreachable (); |
e45b72c4 RE |
10677 | } |
10678 | } | |
f676971a | 10679 | |
84ed5e79 RE |
10680 | /* A compare with a shifted operand. Because of canonicalization, the |
10681 | comparison will have to be swapped when we emit the assembler. */ | |
3e2d9dcf RR |
10682 | if (GET_MODE (y) == SImode |
10683 | && (REG_P (y) || (GET_CODE (y) == SUBREG)) | |
84ed5e79 RE |
10684 | && (GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT |
10685 | || GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ROTATE | |
10686 | || GET_CODE (x) == ROTATERT)) | |
10687 | return CC_SWPmode; | |
10688 | ||
04d8b819 RE |
10689 | /* This operation is performed swapped, but since we only rely on the Z |
10690 | flag we don't need an additional mode. */ | |
3e2d9dcf RR |
10691 | if (GET_MODE (y) == SImode |
10692 | && (REG_P (y) || (GET_CODE (y) == SUBREG)) | |
04d8b819 RE |
10693 | && GET_CODE (x) == NEG |
10694 | && (op == EQ || op == NE)) | |
10695 | return CC_Zmode; | |
10696 | ||
f676971a | 10697 | /* This is a special case that is used by combine to allow a |
956d6950 | 10698 | comparison of a shifted byte load to be split into a zero-extend |
84ed5e79 | 10699 | followed by a comparison of the shifted integer (only valid for |
956d6950 | 10700 | equalities and unsigned inequalities). */ |
84ed5e79 RE |
10701 | if (GET_MODE (x) == SImode |
10702 | && GET_CODE (x) == ASHIFT | |
10703 | && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 24 | |
10704 | && GET_CODE (XEXP (x, 0)) == SUBREG | |
10705 | && GET_CODE (SUBREG_REG (XEXP (x, 0))) == MEM | |
10706 | && GET_MODE (SUBREG_REG (XEXP (x, 0))) == QImode | |
10707 | && (op == EQ || op == NE | |
10708 | || op == GEU || op == GTU || op == LTU || op == LEU) | |
10709 | && GET_CODE (y) == CONST_INT) | |
10710 | return CC_Zmode; | |
10711 | ||
1646cf41 RE |
10712 | /* A construct for a conditional compare, if the false arm contains |
10713 | 0, then both conditions must be true, otherwise either condition | |
10714 | must be true. Not all conditions are possible, so CCmode is | |
10715 | returned if it can't be done. */ | |
10716 | if (GET_CODE (x) == IF_THEN_ELSE | |
10717 | && (XEXP (x, 2) == const0_rtx | |
10718 | || XEXP (x, 2) == const1_rtx) | |
ec8e098d PB |
10719 | && COMPARISON_P (XEXP (x, 0)) |
10720 | && COMPARISON_P (XEXP (x, 1))) | |
f676971a | 10721 | return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1), |
03f1640c | 10722 | INTVAL (XEXP (x, 2))); |
1646cf41 RE |
10723 | |
10724 | /* Alternate canonicalizations of the above. These are somewhat cleaner. */ | |
10725 | if (GET_CODE (x) == AND | |
4d5d6586 | 10726 | && (op == EQ || op == NE) |
ec8e098d PB |
10727 | && COMPARISON_P (XEXP (x, 0)) |
10728 | && COMPARISON_P (XEXP (x, 1))) | |
03f1640c RE |
10729 | return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1), |
10730 | DOM_CC_X_AND_Y); | |
1646cf41 RE |
10731 | |
10732 | if (GET_CODE (x) == IOR | |
4d5d6586 | 10733 | && (op == EQ || op == NE) |
ec8e098d PB |
10734 | && COMPARISON_P (XEXP (x, 0)) |
10735 | && COMPARISON_P (XEXP (x, 1))) | |
03f1640c RE |
10736 | return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1), |
10737 | DOM_CC_X_OR_Y); | |
1646cf41 | 10738 | |
defc0463 RE |
10739 | /* An operation (on Thumb) where we want to test for a single bit. |
10740 | This is done by shifting that bit up into the top bit of a | |
10741 | scratch register; we can then branch on the sign bit. */ | |
5b3e6663 | 10742 | if (TARGET_THUMB1 |
defc0463 RE |
10743 | && GET_MODE (x) == SImode |
10744 | && (op == EQ || op == NE) | |
f9fa4363 RE |
10745 | && GET_CODE (x) == ZERO_EXTRACT |
10746 | && XEXP (x, 1) == const1_rtx) | |
defc0463 RE |
10747 | return CC_Nmode; |
10748 | ||
84ed5e79 RE |
10749 | /* An operation that sets the condition codes as a side-effect, the |
10750 | V flag is not set correctly, so we can only use comparisons where | |
10751 | this doesn't matter. (For LT and GE we can use "mi" and "pl" | |
defc0463 | 10752 | instead.) */ |
5b3e6663 | 10753 | /* ??? Does the ZERO_EXTRACT case really apply to thumb2? */ |
84ed5e79 RE |
10754 | if (GET_MODE (x) == SImode |
10755 | && y == const0_rtx | |
10756 | && (op == EQ || op == NE || op == LT || op == GE) | |
10757 | && (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS | |
10758 | || GET_CODE (x) == AND || GET_CODE (x) == IOR | |
10759 | || GET_CODE (x) == XOR || GET_CODE (x) == MULT | |
10760 | || GET_CODE (x) == NOT || GET_CODE (x) == NEG | |
10761 | || GET_CODE (x) == LSHIFTRT | |
10762 | || GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT | |
defc0463 | 10763 | || GET_CODE (x) == ROTATERT |
5b3e6663 | 10764 | || (TARGET_32BIT && GET_CODE (x) == ZERO_EXTRACT))) |
84ed5e79 RE |
10765 | return CC_NOOVmode; |
10766 | ||
84ed5e79 RE |
10767 | if (GET_MODE (x) == QImode && (op == EQ || op == NE)) |
10768 | return CC_Zmode; | |
10769 | ||
bd9c7e23 RE |
10770 | if (GET_MODE (x) == SImode && (op == LTU || op == GEU) |
10771 | && GET_CODE (x) == PLUS | |
10772 | && (rtx_equal_p (XEXP (x, 0), y) || rtx_equal_p (XEXP (x, 1), y))) | |
10773 | return CC_Cmode; | |
10774 | ||
73160ba9 DJ |
10775 | if (GET_MODE (x) == DImode || GET_MODE (y) == DImode) |
10776 | { | |
10777 | /* To keep things simple, always use the Cirrus cfcmp64 if it is | |
10778 | available. */ | |
10779 | if (TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK) | |
10780 | return CCmode; | |
10781 | ||
10782 | switch (op) | |
10783 | { | |
10784 | case EQ: | |
10785 | case NE: | |
10786 | /* A DImode comparison against zero can be implemented by | |
10787 | or'ing the two halves together. */ | |
10788 | if (y == const0_rtx) | |
10789 | return CC_Zmode; | |
10790 | ||
10791 | /* We can do an equality test in three Thumb instructions. */ | |
10792 | if (!TARGET_ARM) | |
10793 | return CC_Zmode; | |
10794 | ||
10795 | /* FALLTHROUGH */ | |
10796 | ||
10797 | case LTU: | |
10798 | case LEU: | |
10799 | case GTU: | |
10800 | case GEU: | |
10801 | /* DImode unsigned comparisons can be implemented by cmp + | |
10802 | cmpeq without a scratch register. Not worth doing in | |
10803 | Thumb-2. */ | |
10804 | if (TARGET_ARM) | |
10805 | return CC_CZmode; | |
10806 | ||
10807 | /* FALLTHROUGH */ | |
10808 | ||
10809 | case LT: | |
10810 | case LE: | |
10811 | case GT: | |
10812 | case GE: | |
10813 | /* DImode signed and unsigned comparisons can be implemented | |
10814 | by cmp + sbcs with a scratch register, but that does not | |
10815 | set the Z flag - we must reverse GT/LE/GTU/LEU. */ | |
10816 | gcc_assert (op != EQ && op != NE); | |
10817 | return CC_NCVmode; | |
10818 | ||
10819 | default: | |
10820 | gcc_unreachable (); | |
10821 | } | |
10822 | } | |
10823 | ||
84ed5e79 RE |
10824 | return CCmode; |
10825 | } | |
10826 | ||
ff9940b0 RE |
10827 | /* X and Y are two things to compare using CODE. Emit the compare insn and |
10828 | return the rtx for register 0 in the proper mode. FP means this is a | |
10829 | floating point compare: I don't think that it is needed on the arm. */ | |
ff9940b0 | 10830 | rtx |
e32bac5b | 10831 | arm_gen_compare_reg (enum rtx_code code, rtx x, rtx y) |
ff9940b0 | 10832 | { |
73160ba9 DJ |
10833 | enum machine_mode mode; |
10834 | rtx cc_reg; | |
10835 | int dimode_comparison = GET_MODE (x) == DImode || GET_MODE (y) == DImode; | |
ff9940b0 | 10836 | |
73160ba9 DJ |
10837 | /* We might have X as a constant, Y as a register because of the predicates |
10838 | used for cmpdi. If so, force X to a register here. */ | |
10839 | if (dimode_comparison && !REG_P (x)) | |
10840 | x = force_reg (DImode, x); | |
10841 | ||
10842 | mode = SELECT_CC_MODE (code, x, y); | |
10843 | cc_reg = gen_rtx_REG (mode, CC_REGNUM); | |
10844 | ||
10845 | if (dimode_comparison | |
10846 | && !(TARGET_HARD_FLOAT && TARGET_MAVERICK) | |
10847 | && mode != CC_CZmode) | |
10848 | { | |
10849 | rtx clobber, set; | |
10850 | ||
10851 | /* To compare two non-zero values for equality, XOR them and | |
10852 | then compare against zero. Not used for ARM mode; there | |
10853 | CC_CZmode is cheaper. */ | |
10854 | if (mode == CC_Zmode && y != const0_rtx) | |
10855 | { | |
10856 | x = expand_binop (DImode, xor_optab, x, y, NULL_RTX, 0, OPTAB_WIDEN); | |
10857 | y = const0_rtx; | |
10858 | } | |
10859 | /* A scratch register is required. */ | |
10860 | clobber = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (SImode)); | |
10861 | set = gen_rtx_SET (VOIDmode, cc_reg, gen_rtx_COMPARE (mode, x, y)); | |
10862 | emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber))); | |
10863 | } | |
10864 | else | |
10865 | emit_set_insn (cc_reg, gen_rtx_COMPARE (mode, x, y)); | |
ff9940b0 RE |
10866 | |
10867 | return cc_reg; | |
10868 | } | |
10869 | ||
fcd53748 JT |
10870 | /* Generate a sequence of insns that will generate the correct return |
10871 | address mask depending on the physical architecture that the program | |
10872 | is running on. */ | |
fcd53748 | 10873 | rtx |
e32bac5b | 10874 | arm_gen_return_addr_mask (void) |
fcd53748 JT |
10875 | { |
10876 | rtx reg = gen_reg_rtx (Pmode); | |
10877 | ||
10878 | emit_insn (gen_return_addr_mask (reg)); | |
10879 | return reg; | |
10880 | } | |
10881 | ||
0a81f500 | 10882 | void |
e32bac5b | 10883 | arm_reload_in_hi (rtx *operands) |
0a81f500 | 10884 | { |
f9cc092a RE |
10885 | rtx ref = operands[1]; |
10886 | rtx base, scratch; | |
10887 | HOST_WIDE_INT offset = 0; | |
10888 | ||
10889 | if (GET_CODE (ref) == SUBREG) | |
10890 | { | |
ddef6bc7 | 10891 | offset = SUBREG_BYTE (ref); |
f9cc092a RE |
10892 | ref = SUBREG_REG (ref); |
10893 | } | |
10894 | ||
10895 | if (GET_CODE (ref) == REG) | |
10896 | { | |
10897 | /* We have a pseudo which has been spilt onto the stack; there | |
10898 | are two cases here: the first where there is a simple | |
10899 | stack-slot replacement and a second where the stack-slot is | |
10900 | out of range, or is used as a subreg. */ | |
10901 | if (reg_equiv_mem[REGNO (ref)]) | |
10902 | { | |
10903 | ref = reg_equiv_mem[REGNO (ref)]; | |
10904 | base = find_replacement (&XEXP (ref, 0)); | |
10905 | } | |
10906 | else | |
6354dc9b | 10907 | /* The slot is out of range, or was dressed up in a SUBREG. */ |
f9cc092a RE |
10908 | base = reg_equiv_address[REGNO (ref)]; |
10909 | } | |
10910 | else | |
10911 | base = find_replacement (&XEXP (ref, 0)); | |
0a81f500 | 10912 | |
e5e809f4 JL |
10913 | /* Handle the case where the address is too complex to be offset by 1. */ |
10914 | if (GET_CODE (base) == MINUS | |
10915 | || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT)) | |
10916 | { | |
f9cc092a | 10917 | rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1); |
e5e809f4 | 10918 | |
d66437c5 | 10919 | emit_set_insn (base_plus, base); |
e5e809f4 JL |
10920 | base = base_plus; |
10921 | } | |
f9cc092a RE |
10922 | else if (GET_CODE (base) == PLUS) |
10923 | { | |
6354dc9b | 10924 | /* The addend must be CONST_INT, or we would have dealt with it above. */ |
f9cc092a RE |
10925 | HOST_WIDE_INT hi, lo; |
10926 | ||
10927 | offset += INTVAL (XEXP (base, 1)); | |
10928 | base = XEXP (base, 0); | |
10929 | ||
6354dc9b | 10930 | /* Rework the address into a legal sequence of insns. */ |
f9cc092a RE |
10931 | /* Valid range for lo is -4095 -> 4095 */ |
10932 | lo = (offset >= 0 | |
10933 | ? (offset & 0xfff) | |
10934 | : -((-offset) & 0xfff)); | |
10935 | ||
10936 | /* Corner case, if lo is the max offset then we would be out of range | |
10937 | once we have added the additional 1 below, so bump the msb into the | |
10938 | pre-loading insn(s). */ | |
10939 | if (lo == 4095) | |
10940 | lo &= 0x7ff; | |
10941 | ||
30cf4896 KG |
10942 | hi = ((((offset - lo) & (HOST_WIDE_INT) 0xffffffff) |
10943 | ^ (HOST_WIDE_INT) 0x80000000) | |
10944 | - (HOST_WIDE_INT) 0x80000000); | |
f9cc092a | 10945 | |
e6d29d15 | 10946 | gcc_assert (hi + lo == offset); |
f9cc092a RE |
10947 | |
10948 | if (hi != 0) | |
10949 | { | |
10950 | rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1); | |
10951 | ||
10952 | /* Get the base address; addsi3 knows how to handle constants | |
6354dc9b | 10953 | that require more than one insn. */ |
f9cc092a RE |
10954 | emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi))); |
10955 | base = base_plus; | |
10956 | offset = lo; | |
10957 | } | |
10958 | } | |
e5e809f4 | 10959 | |
3a1944a6 RE |
10960 | /* Operands[2] may overlap operands[0] (though it won't overlap |
10961 | operands[1]), that's why we asked for a DImode reg -- so we can | |
10962 | use the bit that does not overlap. */ | |
10963 | if (REGNO (operands[2]) == REGNO (operands[0])) | |
10964 | scratch = gen_rtx_REG (SImode, REGNO (operands[2]) + 1); | |
10965 | else | |
10966 | scratch = gen_rtx_REG (SImode, REGNO (operands[2])); | |
10967 | ||
f9cc092a RE |
10968 | emit_insn (gen_zero_extendqisi2 (scratch, |
10969 | gen_rtx_MEM (QImode, | |
10970 | plus_constant (base, | |
10971 | offset)))); | |
43cffd11 | 10972 | emit_insn (gen_zero_extendqisi2 (gen_rtx_SUBREG (SImode, operands[0], 0), |
f676971a | 10973 | gen_rtx_MEM (QImode, |
f9cc092a RE |
10974 | plus_constant (base, |
10975 | offset + 1)))); | |
5895f793 | 10976 | if (!BYTES_BIG_ENDIAN) |
d66437c5 RE |
10977 | emit_set_insn (gen_rtx_SUBREG (SImode, operands[0], 0), |
10978 | gen_rtx_IOR (SImode, | |
10979 | gen_rtx_ASHIFT | |
10980 | (SImode, | |
10981 | gen_rtx_SUBREG (SImode, operands[0], 0), | |
10982 | GEN_INT (8)), | |
10983 | scratch)); | |
0a81f500 | 10984 | else |
d66437c5 RE |
10985 | emit_set_insn (gen_rtx_SUBREG (SImode, operands[0], 0), |
10986 | gen_rtx_IOR (SImode, | |
10987 | gen_rtx_ASHIFT (SImode, scratch, | |
10988 | GEN_INT (8)), | |
10989 | gen_rtx_SUBREG (SImode, operands[0], 0))); | |
0a81f500 RE |
10990 | } |
10991 | ||
72ac76be | 10992 | /* Handle storing a half-word to memory during reload by synthesizing as two |
f9cc092a RE |
10993 | byte stores. Take care not to clobber the input values until after we |
10994 | have moved them somewhere safe. This code assumes that if the DImode | |
10995 | scratch in operands[2] overlaps either the input value or output address | |
10996 | in some way, then that value must die in this insn (we absolutely need | |
10997 | two scratch registers for some corner cases). */ | |
f3bb6135 | 10998 | void |
e32bac5b | 10999 | arm_reload_out_hi (rtx *operands) |
af48348a | 11000 | { |
f9cc092a RE |
11001 | rtx ref = operands[0]; |
11002 | rtx outval = operands[1]; | |
11003 | rtx base, scratch; | |
11004 | HOST_WIDE_INT offset = 0; | |
11005 | ||
11006 | if (GET_CODE (ref) == SUBREG) | |
11007 | { | |
ddef6bc7 | 11008 | offset = SUBREG_BYTE (ref); |
f9cc092a RE |
11009 | ref = SUBREG_REG (ref); |
11010 | } | |
11011 | ||
f9cc092a RE |
11012 | if (GET_CODE (ref) == REG) |
11013 | { | |
11014 | /* We have a pseudo which has been spilt onto the stack; there | |
11015 | are two cases here: the first where there is a simple | |
11016 | stack-slot replacement and a second where the stack-slot is | |
11017 | out of range, or is used as a subreg. */ | |
11018 | if (reg_equiv_mem[REGNO (ref)]) | |
11019 | { | |
11020 | ref = reg_equiv_mem[REGNO (ref)]; | |
11021 | base = find_replacement (&XEXP (ref, 0)); | |
11022 | } | |
11023 | else | |
6354dc9b | 11024 | /* The slot is out of range, or was dressed up in a SUBREG. */ |
f9cc092a RE |
11025 | base = reg_equiv_address[REGNO (ref)]; |
11026 | } | |
11027 | else | |
11028 | base = find_replacement (&XEXP (ref, 0)); | |
11029 | ||
11030 | scratch = gen_rtx_REG (SImode, REGNO (operands[2])); | |
11031 | ||
11032 | /* Handle the case where the address is too complex to be offset by 1. */ | |
11033 | if (GET_CODE (base) == MINUS | |
11034 | || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT)) | |
11035 | { | |
11036 | rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1); | |
11037 | ||
11038 | /* Be careful not to destroy OUTVAL. */ | |
11039 | if (reg_overlap_mentioned_p (base_plus, outval)) | |
11040 | { | |
11041 | /* Updating base_plus might destroy outval, see if we can | |
11042 | swap the scratch and base_plus. */ | |
5895f793 | 11043 | if (!reg_overlap_mentioned_p (scratch, outval)) |
f9cc092a RE |
11044 | { |
11045 | rtx tmp = scratch; | |
11046 | scratch = base_plus; | |
11047 | base_plus = tmp; | |
11048 | } | |
11049 | else | |
11050 | { | |
11051 | rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2])); | |
11052 | ||
11053 | /* Be conservative and copy OUTVAL into the scratch now, | |
11054 | this should only be necessary if outval is a subreg | |
11055 | of something larger than a word. */ | |
11056 | /* XXX Might this clobber base? I can't see how it can, | |
11057 | since scratch is known to overlap with OUTVAL, and | |
11058 | must be wider than a word. */ | |
11059 | emit_insn (gen_movhi (scratch_hi, outval)); | |
11060 | outval = scratch_hi; | |
11061 | } | |
11062 | } | |
11063 | ||
d66437c5 | 11064 | emit_set_insn (base_plus, base); |
f9cc092a RE |
11065 | base = base_plus; |
11066 | } | |
11067 | else if (GET_CODE (base) == PLUS) | |
11068 | { | |
6354dc9b | 11069 | /* The addend must be CONST_INT, or we would have dealt with it above. */ |
f9cc092a RE |
11070 | HOST_WIDE_INT hi, lo; |
11071 | ||
11072 | offset += INTVAL (XEXP (base, 1)); | |
11073 | base = XEXP (base, 0); | |
11074 | ||
6354dc9b | 11075 | /* Rework the address into a legal sequence of insns. */ |
f9cc092a RE |
11076 | /* Valid range for lo is -4095 -> 4095 */ |
11077 | lo = (offset >= 0 | |
11078 | ? (offset & 0xfff) | |
11079 | : -((-offset) & 0xfff)); | |
11080 | ||
11081 | /* Corner case, if lo is the max offset then we would be out of range | |
11082 | once we have added the additional 1 below, so bump the msb into the | |
11083 | pre-loading insn(s). */ | |
11084 | if (lo == 4095) | |
11085 | lo &= 0x7ff; | |
11086 | ||
30cf4896 KG |
11087 | hi = ((((offset - lo) & (HOST_WIDE_INT) 0xffffffff) |
11088 | ^ (HOST_WIDE_INT) 0x80000000) | |
11089 | - (HOST_WIDE_INT) 0x80000000); | |
f9cc092a | 11090 | |
e6d29d15 | 11091 | gcc_assert (hi + lo == offset); |
f9cc092a RE |
11092 | |
11093 | if (hi != 0) | |
11094 | { | |
11095 | rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1); | |
11096 | ||
11097 | /* Be careful not to destroy OUTVAL. */ | |
11098 | if (reg_overlap_mentioned_p (base_plus, outval)) | |
11099 | { | |
11100 | /* Updating base_plus might destroy outval, see if we | |
11101 | can swap the scratch and base_plus. */ | |
5895f793 | 11102 | if (!reg_overlap_mentioned_p (scratch, outval)) |
f9cc092a RE |
11103 | { |
11104 | rtx tmp = scratch; | |
11105 | scratch = base_plus; | |
11106 | base_plus = tmp; | |
11107 | } | |
11108 | else | |
11109 | { | |
11110 | rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2])); | |
11111 | ||
11112 | /* Be conservative and copy outval into scratch now, | |
11113 | this should only be necessary if outval is a | |
11114 | subreg of something larger than a word. */ | |
11115 | /* XXX Might this clobber base? I can't see how it | |
11116 | can, since scratch is known to overlap with | |
11117 | outval. */ | |
11118 | emit_insn (gen_movhi (scratch_hi, outval)); | |
11119 | outval = scratch_hi; | |
11120 | } | |
11121 | } | |
11122 | ||
11123 | /* Get the base address; addsi3 knows how to handle constants | |
6354dc9b | 11124 | that require more than one insn. */ |
f9cc092a RE |
11125 | emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi))); |
11126 | base = base_plus; | |
11127 | offset = lo; | |
11128 | } | |
11129 | } | |
af48348a | 11130 | |
b5cc037f RE |
11131 | if (BYTES_BIG_ENDIAN) |
11132 | { | |
f676971a | 11133 | emit_insn (gen_movqi (gen_rtx_MEM (QImode, |
f9cc092a | 11134 | plus_constant (base, offset + 1)), |
5d5603e2 | 11135 | gen_lowpart (QImode, outval))); |
f9cc092a RE |
11136 | emit_insn (gen_lshrsi3 (scratch, |
11137 | gen_rtx_SUBREG (SImode, outval, 0), | |
b5cc037f | 11138 | GEN_INT (8))); |
f9cc092a | 11139 | emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)), |
5d5603e2 | 11140 | gen_lowpart (QImode, scratch))); |
b5cc037f RE |
11141 | } |
11142 | else | |
11143 | { | |
f9cc092a | 11144 | emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)), |
5d5603e2 | 11145 | gen_lowpart (QImode, outval))); |
f9cc092a RE |
11146 | emit_insn (gen_lshrsi3 (scratch, |
11147 | gen_rtx_SUBREG (SImode, outval, 0), | |
b5cc037f | 11148 | GEN_INT (8))); |
f9cc092a RE |
11149 | emit_insn (gen_movqi (gen_rtx_MEM (QImode, |
11150 | plus_constant (base, offset + 1)), | |
5d5603e2 | 11151 | gen_lowpart (QImode, scratch))); |
b5cc037f | 11152 | } |
af48348a | 11153 | } |
866af8a9 JB |
11154 | |
11155 | /* Return true if a type must be passed in memory. For AAPCS, small aggregates | |
11156 | (padded to the size of a word) should be passed in a register. */ | |
11157 | ||
11158 | static bool | |
586de218 | 11159 | arm_must_pass_in_stack (enum machine_mode mode, const_tree type) |
866af8a9 JB |
11160 | { |
11161 | if (TARGET_AAPCS_BASED) | |
11162 | return must_pass_in_stack_var_size (mode, type); | |
11163 | else | |
11164 | return must_pass_in_stack_var_size_or_pad (mode, type); | |
11165 | } | |
11166 | ||
11167 | ||
11168 | /* For use by FUNCTION_ARG_PADDING (MODE, TYPE). | |
11169 | Return true if an argument passed on the stack should be padded upwards, | |
5a29b385 PB |
11170 | i.e. if the least-significant byte has useful data. |
11171 | For legacy APCS ABIs we use the default. For AAPCS based ABIs small | |
11172 | aggregate types are placed in the lowest memory address. */ | |
866af8a9 JB |
11173 | |
11174 | bool | |
586de218 | 11175 | arm_pad_arg_upward (enum machine_mode mode, const_tree type) |
866af8a9 JB |
11176 | { |
11177 | if (!TARGET_AAPCS_BASED) | |
5a29b385 | 11178 | return DEFAULT_FUNCTION_ARG_PADDING(mode, type) == upward; |
866af8a9 JB |
11179 | |
11180 | if (type && BYTES_BIG_ENDIAN && INTEGRAL_TYPE_P (type)) | |
11181 | return false; | |
11182 | ||
11183 | return true; | |
11184 | } | |
11185 | ||
11186 | ||
11187 | /* Similarly, for use by BLOCK_REG_PADDING (MODE, TYPE, FIRST). | |
11188 | For non-AAPCS, return !BYTES_BIG_ENDIAN if the least significant | |
11189 | byte of the register has useful data, and return the opposite if the | |
11190 | most significant byte does. | |
11191 | For AAPCS, small aggregates and small complex types are always padded | |
11192 | upwards. */ | |
11193 | ||
11194 | bool | |
11195 | arm_pad_reg_upward (enum machine_mode mode ATTRIBUTE_UNUSED, | |
11196 | tree type, int first ATTRIBUTE_UNUSED) | |
11197 | { | |
11198 | if (TARGET_AAPCS_BASED | |
11199 | && BYTES_BIG_ENDIAN | |
11200 | && (AGGREGATE_TYPE_P (type) || TREE_CODE (type) == COMPLEX_TYPE) | |
11201 | && int_size_in_bytes (type) <= 4) | |
11202 | return true; | |
11203 | ||
11204 | /* Otherwise, use default padding. */ | |
11205 | return !BYTES_BIG_ENDIAN; | |
11206 | } | |
11207 | ||
2b835d68 | 11208 | \f |
d5b7b3ae RE |
11209 | /* Print a symbolic form of X to the debug file, F. */ |
11210 | static void | |
e32bac5b | 11211 | arm_print_value (FILE *f, rtx x) |
d5b7b3ae RE |
11212 | { |
11213 | switch (GET_CODE (x)) | |
11214 | { | |
11215 | case CONST_INT: | |
11216 | fprintf (f, HOST_WIDE_INT_PRINT_HEX, INTVAL (x)); | |
11217 | return; | |
11218 | ||
11219 | case CONST_DOUBLE: | |
11220 | fprintf (f, "<0x%lx,0x%lx>", (long)XWINT (x, 2), (long)XWINT (x, 3)); | |
11221 | return; | |
11222 | ||
5a9335ef NC |
11223 | case CONST_VECTOR: |
11224 | { | |
11225 | int i; | |
11226 | ||
11227 | fprintf (f, "<"); | |
11228 | for (i = 0; i < CONST_VECTOR_NUNITS (x); i++) | |
11229 | { | |
11230 | fprintf (f, HOST_WIDE_INT_PRINT_HEX, INTVAL (CONST_VECTOR_ELT (x, i))); | |
11231 | if (i < (CONST_VECTOR_NUNITS (x) - 1)) | |
11232 | fputc (',', f); | |
11233 | } | |
11234 | fprintf (f, ">"); | |
11235 | } | |
11236 | return; | |
11237 | ||
d5b7b3ae RE |
11238 | case CONST_STRING: |
11239 | fprintf (f, "\"%s\"", XSTR (x, 0)); | |
11240 | return; | |
11241 | ||
11242 | case SYMBOL_REF: | |
11243 | fprintf (f, "`%s'", XSTR (x, 0)); | |
11244 | return; | |
11245 | ||
11246 | case LABEL_REF: | |
11247 | fprintf (f, "L%d", INSN_UID (XEXP (x, 0))); | |
11248 | return; | |
11249 | ||
11250 | case CONST: | |
11251 | arm_print_value (f, XEXP (x, 0)); | |
11252 | return; | |
11253 | ||
11254 | case PLUS: | |
11255 | arm_print_value (f, XEXP (x, 0)); | |
11256 | fprintf (f, "+"); | |
11257 | arm_print_value (f, XEXP (x, 1)); | |
11258 | return; | |
11259 | ||
11260 | case PC: | |
11261 | fprintf (f, "pc"); | |
11262 | return; | |
11263 | ||
11264 | default: | |
11265 | fprintf (f, "????"); | |
11266 | return; | |
11267 | } | |
11268 | } | |
11269 | \f | |
2b835d68 | 11270 | /* Routines for manipulation of the constant pool. */ |
2b835d68 | 11271 | |
949d79eb RE |
11272 | /* Arm instructions cannot load a large constant directly into a |
11273 | register; they have to come from a pc relative load. The constant | |
11274 | must therefore be placed in the addressable range of the pc | |
11275 | relative load. Depending on the precise pc relative load | |
11276 | instruction the range is somewhere between 256 bytes and 4k. This | |
11277 | means that we often have to dump a constant inside a function, and | |
2b835d68 RE |
11278 | generate code to branch around it. |
11279 | ||
949d79eb RE |
11280 | It is important to minimize this, since the branches will slow |
11281 | things down and make the code larger. | |
2b835d68 | 11282 | |
949d79eb RE |
11283 | Normally we can hide the table after an existing unconditional |
11284 | branch so that there is no interruption of the flow, but in the | |
11285 | worst case the code looks like this: | |
2b835d68 RE |
11286 | |
11287 | ldr rn, L1 | |
949d79eb | 11288 | ... |
2b835d68 RE |
11289 | b L2 |
11290 | align | |
11291 | L1: .long value | |
11292 | L2: | |
949d79eb | 11293 | ... |
2b835d68 | 11294 | |
2b835d68 | 11295 | ldr rn, L3 |
949d79eb | 11296 | ... |
2b835d68 RE |
11297 | b L4 |
11298 | align | |
2b835d68 RE |
11299 | L3: .long value |
11300 | L4: | |
949d79eb RE |
11301 | ... |
11302 | ||
11303 | We fix this by performing a scan after scheduling, which notices | |
11304 | which instructions need to have their operands fetched from the | |
11305 | constant table and builds the table. | |
11306 | ||
11307 | The algorithm starts by building a table of all the constants that | |
11308 | need fixing up and all the natural barriers in the function (places | |
11309 | where a constant table can be dropped without breaking the flow). | |
11310 | For each fixup we note how far the pc-relative replacement will be | |
11311 | able to reach and the offset of the instruction into the function. | |
11312 | ||
11313 | Having built the table we then group the fixes together to form | |
11314 | tables that are as large as possible (subject to addressing | |
11315 | constraints) and emit each table of constants after the last | |
11316 | barrier that is within range of all the instructions in the group. | |
11317 | If a group does not contain a barrier, then we forcibly create one | |
11318 | by inserting a jump instruction into the flow. Once the table has | |
11319 | been inserted, the insns are then modified to reference the | |
11320 | relevant entry in the pool. | |
11321 | ||
6354dc9b | 11322 | Possible enhancements to the algorithm (not implemented) are: |
949d79eb | 11323 | |
d5b7b3ae | 11324 | 1) For some processors and object formats, there may be benefit in |
949d79eb RE |
11325 | aligning the pools to the start of cache lines; this alignment |
11326 | would need to be taken into account when calculating addressability | |
6354dc9b | 11327 | of a pool. */ |
2b835d68 | 11328 | |
d5b7b3ae RE |
11329 | /* These typedefs are located at the start of this file, so that |
11330 | they can be used in the prototypes there. This comment is to | |
11331 | remind readers of that fact so that the following structures | |
11332 | can be understood more easily. | |
11333 | ||
11334 | typedef struct minipool_node Mnode; | |
11335 | typedef struct minipool_fixup Mfix; */ | |
11336 | ||
11337 | struct minipool_node | |
11338 | { | |
11339 | /* Doubly linked chain of entries. */ | |
11340 | Mnode * next; | |
11341 | Mnode * prev; | |
11342 | /* The maximum offset into the code that this entry can be placed. While | |
11343 | pushing fixes for forward references, all entries are sorted in order | |
11344 | of increasing max_address. */ | |
11345 | HOST_WIDE_INT max_address; | |
5519a4f9 | 11346 | /* Similarly for an entry inserted for a backwards ref. */ |
d5b7b3ae RE |
11347 | HOST_WIDE_INT min_address; |
11348 | /* The number of fixes referencing this entry. This can become zero | |
11349 | if we "unpush" an entry. In this case we ignore the entry when we | |
11350 | come to emit the code. */ | |
11351 | int refcount; | |
11352 | /* The offset from the start of the minipool. */ | |
11353 | HOST_WIDE_INT offset; | |
11354 | /* The value in table. */ | |
11355 | rtx value; | |
11356 | /* The mode of value. */ | |
11357 | enum machine_mode mode; | |
5a9335ef NC |
11358 | /* The size of the value. With iWMMXt enabled |
11359 | sizes > 4 also imply an alignment of 8-bytes. */ | |
d5b7b3ae RE |
11360 | int fix_size; |
11361 | }; | |
11362 | ||
11363 | struct minipool_fixup | |
2b835d68 | 11364 | { |
d5b7b3ae RE |
11365 | Mfix * next; |
11366 | rtx insn; | |
11367 | HOST_WIDE_INT address; | |
11368 | rtx * loc; | |
11369 | enum machine_mode mode; | |
11370 | int fix_size; | |
11371 | rtx value; | |
11372 | Mnode * minipool; | |
11373 | HOST_WIDE_INT forwards; | |
11374 | HOST_WIDE_INT backwards; | |
11375 | }; | |
2b835d68 | 11376 | |
d5b7b3ae RE |
11377 | /* Fixes less than a word need padding out to a word boundary. */ |
11378 | #define MINIPOOL_FIX_SIZE(mode) \ | |
11379 | (GET_MODE_SIZE ((mode)) >= 4 ? GET_MODE_SIZE ((mode)) : 4) | |
2b835d68 | 11380 | |
d5b7b3ae RE |
11381 | static Mnode * minipool_vector_head; |
11382 | static Mnode * minipool_vector_tail; | |
11383 | static rtx minipool_vector_label; | |
34a9f549 | 11384 | static int minipool_pad; |
332072db | 11385 | |
d5b7b3ae RE |
11386 | /* The linked list of all minipool fixes required for this function. */ |
11387 | Mfix * minipool_fix_head; | |
11388 | Mfix * minipool_fix_tail; | |
11389 | /* The fix entry for the current minipool, once it has been placed. */ | |
11390 | Mfix * minipool_barrier; | |
11391 | ||
11392 | /* Determines if INSN is the start of a jump table. Returns the end | |
11393 | of the TABLE or NULL_RTX. */ | |
11394 | static rtx | |
e32bac5b | 11395 | is_jump_table (rtx insn) |
2b835d68 | 11396 | { |
d5b7b3ae | 11397 | rtx table; |
f676971a | 11398 | |
d5b7b3ae RE |
11399 | if (GET_CODE (insn) == JUMP_INSN |
11400 | && JUMP_LABEL (insn) != NULL | |
11401 | && ((table = next_real_insn (JUMP_LABEL (insn))) | |
11402 | == next_real_insn (insn)) | |
11403 | && table != NULL | |
11404 | && GET_CODE (table) == JUMP_INSN | |
11405 | && (GET_CODE (PATTERN (table)) == ADDR_VEC | |
11406 | || GET_CODE (PATTERN (table)) == ADDR_DIFF_VEC)) | |
11407 | return table; | |
11408 | ||
11409 | return NULL_RTX; | |
2b835d68 RE |
11410 | } |
11411 | ||
657d9449 RE |
11412 | #ifndef JUMP_TABLES_IN_TEXT_SECTION |
11413 | #define JUMP_TABLES_IN_TEXT_SECTION 0 | |
11414 | #endif | |
11415 | ||
d5b7b3ae | 11416 | static HOST_WIDE_INT |
e32bac5b | 11417 | get_jump_table_size (rtx insn) |
2b835d68 | 11418 | { |
657d9449 RE |
11419 | /* ADDR_VECs only take room if read-only data does into the text |
11420 | section. */ | |
d6b5193b | 11421 | if (JUMP_TABLES_IN_TEXT_SECTION || readonly_data_section == text_section) |
657d9449 RE |
11422 | { |
11423 | rtx body = PATTERN (insn); | |
11424 | int elt = GET_CODE (body) == ADDR_DIFF_VEC ? 1 : 0; | |
5b3e6663 PB |
11425 | HOST_WIDE_INT size; |
11426 | HOST_WIDE_INT modesize; | |
2b835d68 | 11427 | |
5b3e6663 PB |
11428 | modesize = GET_MODE_SIZE (GET_MODE (body)); |
11429 | size = modesize * XVECLEN (body, elt); | |
11430 | switch (modesize) | |
11431 | { | |
11432 | case 1: | |
88512ba0 | 11433 | /* Round up size of TBB table to a halfword boundary. */ |
5b3e6663 PB |
11434 | size = (size + 1) & ~(HOST_WIDE_INT)1; |
11435 | break; | |
11436 | case 2: | |
7a085dce | 11437 | /* No padding necessary for TBH. */ |
5b3e6663 PB |
11438 | break; |
11439 | case 4: | |
11440 | /* Add two bytes for alignment on Thumb. */ | |
11441 | if (TARGET_THUMB) | |
11442 | size += 2; | |
11443 | break; | |
11444 | default: | |
11445 | gcc_unreachable (); | |
11446 | } | |
11447 | return size; | |
657d9449 RE |
11448 | } |
11449 | ||
11450 | return 0; | |
d5b7b3ae | 11451 | } |
2b835d68 | 11452 | |
d5b7b3ae RE |
11453 | /* Move a minipool fix MP from its current location to before MAX_MP. |
11454 | If MAX_MP is NULL, then MP doesn't need moving, but the addressing | |
093354e0 | 11455 | constraints may need updating. */ |
d5b7b3ae | 11456 | static Mnode * |
e32bac5b RE |
11457 | move_minipool_fix_forward_ref (Mnode *mp, Mnode *max_mp, |
11458 | HOST_WIDE_INT max_address) | |
d5b7b3ae | 11459 | { |
e6d29d15 NS |
11460 | /* The code below assumes these are different. */ |
11461 | gcc_assert (mp != max_mp); | |
d5b7b3ae RE |
11462 | |
11463 | if (max_mp == NULL) | |
11464 | { | |
11465 | if (max_address < mp->max_address) | |
11466 | mp->max_address = max_address; | |
11467 | } | |
11468 | else | |
2b835d68 | 11469 | { |
d5b7b3ae RE |
11470 | if (max_address > max_mp->max_address - mp->fix_size) |
11471 | mp->max_address = max_mp->max_address - mp->fix_size; | |
11472 | else | |
11473 | mp->max_address = max_address; | |
2b835d68 | 11474 | |
d5b7b3ae RE |
11475 | /* Unlink MP from its current position. Since max_mp is non-null, |
11476 | mp->prev must be non-null. */ | |
11477 | mp->prev->next = mp->next; | |
11478 | if (mp->next != NULL) | |
11479 | mp->next->prev = mp->prev; | |
11480 | else | |
11481 | minipool_vector_tail = mp->prev; | |
2b835d68 | 11482 | |
d5b7b3ae RE |
11483 | /* Re-insert it before MAX_MP. */ |
11484 | mp->next = max_mp; | |
11485 | mp->prev = max_mp->prev; | |
11486 | max_mp->prev = mp; | |
f676971a | 11487 | |
d5b7b3ae RE |
11488 | if (mp->prev != NULL) |
11489 | mp->prev->next = mp; | |
11490 | else | |
11491 | minipool_vector_head = mp; | |
11492 | } | |
2b835d68 | 11493 | |
d5b7b3ae RE |
11494 | /* Save the new entry. */ |
11495 | max_mp = mp; | |
11496 | ||
d6a7951f | 11497 | /* Scan over the preceding entries and adjust their addresses as |
d5b7b3ae RE |
11498 | required. */ |
11499 | while (mp->prev != NULL | |
11500 | && mp->prev->max_address > mp->max_address - mp->prev->fix_size) | |
11501 | { | |
11502 | mp->prev->max_address = mp->max_address - mp->prev->fix_size; | |
11503 | mp = mp->prev; | |
2b835d68 RE |
11504 | } |
11505 | ||
d5b7b3ae | 11506 | return max_mp; |
2b835d68 RE |
11507 | } |
11508 | ||
d5b7b3ae RE |
11509 | /* Add a constant to the minipool for a forward reference. Returns the |
11510 | node added or NULL if the constant will not fit in this pool. */ | |
11511 | static Mnode * | |
e32bac5b | 11512 | add_minipool_forward_ref (Mfix *fix) |
d5b7b3ae RE |
11513 | { |
11514 | /* If set, max_mp is the first pool_entry that has a lower | |
11515 | constraint than the one we are trying to add. */ | |
11516 | Mnode * max_mp = NULL; | |
34a9f549 | 11517 | HOST_WIDE_INT max_address = fix->address + fix->forwards - minipool_pad; |
d5b7b3ae | 11518 | Mnode * mp; |
f676971a | 11519 | |
7a7017bc PB |
11520 | /* If the minipool starts before the end of FIX->INSN then this FIX |
11521 | can not be placed into the current pool. Furthermore, adding the | |
11522 | new constant pool entry may cause the pool to start FIX_SIZE bytes | |
11523 | earlier. */ | |
d5b7b3ae | 11524 | if (minipool_vector_head && |
7a7017bc PB |
11525 | (fix->address + get_attr_length (fix->insn) |
11526 | >= minipool_vector_head->max_address - fix->fix_size)) | |
d5b7b3ae | 11527 | return NULL; |
2b835d68 | 11528 | |
d5b7b3ae RE |
11529 | /* Scan the pool to see if a constant with the same value has |
11530 | already been added. While we are doing this, also note the | |
11531 | location where we must insert the constant if it doesn't already | |
11532 | exist. */ | |
11533 | for (mp = minipool_vector_head; mp != NULL; mp = mp->next) | |
11534 | { | |
11535 | if (GET_CODE (fix->value) == GET_CODE (mp->value) | |
11536 | && fix->mode == mp->mode | |
11537 | && (GET_CODE (fix->value) != CODE_LABEL | |
11538 | || (CODE_LABEL_NUMBER (fix->value) | |
11539 | == CODE_LABEL_NUMBER (mp->value))) | |
11540 | && rtx_equal_p (fix->value, mp->value)) | |
11541 | { | |
11542 | /* More than one fix references this entry. */ | |
11543 | mp->refcount++; | |
11544 | return move_minipool_fix_forward_ref (mp, max_mp, max_address); | |
11545 | } | |
11546 | ||
11547 | /* Note the insertion point if necessary. */ | |
11548 | if (max_mp == NULL | |
11549 | && mp->max_address > max_address) | |
11550 | max_mp = mp; | |
5a9335ef NC |
11551 | |
11552 | /* If we are inserting an 8-bytes aligned quantity and | |
11553 | we have not already found an insertion point, then | |
11554 | make sure that all such 8-byte aligned quantities are | |
11555 | placed at the start of the pool. */ | |
5848830f | 11556 | if (ARM_DOUBLEWORD_ALIGN |
5a9335ef | 11557 | && max_mp == NULL |
88f77cba JB |
11558 | && fix->fix_size >= 8 |
11559 | && mp->fix_size < 8) | |
5a9335ef NC |
11560 | { |
11561 | max_mp = mp; | |
11562 | max_address = mp->max_address; | |
11563 | } | |
d5b7b3ae RE |
11564 | } |
11565 | ||
11566 | /* The value is not currently in the minipool, so we need to create | |
11567 | a new entry for it. If MAX_MP is NULL, the entry will be put on | |
11568 | the end of the list since the placement is less constrained than | |
11569 | any existing entry. Otherwise, we insert the new fix before | |
6bc82793 | 11570 | MAX_MP and, if necessary, adjust the constraints on the other |
d5b7b3ae | 11571 | entries. */ |
5ed6ace5 | 11572 | mp = XNEW (Mnode); |
d5b7b3ae RE |
11573 | mp->fix_size = fix->fix_size; |
11574 | mp->mode = fix->mode; | |
11575 | mp->value = fix->value; | |
11576 | mp->refcount = 1; | |
11577 | /* Not yet required for a backwards ref. */ | |
11578 | mp->min_address = -65536; | |
11579 | ||
11580 | if (max_mp == NULL) | |
11581 | { | |
11582 | mp->max_address = max_address; | |
11583 | mp->next = NULL; | |
11584 | mp->prev = minipool_vector_tail; | |
11585 | ||
11586 | if (mp->prev == NULL) | |
11587 | { | |
11588 | minipool_vector_head = mp; | |
11589 | minipool_vector_label = gen_label_rtx (); | |
7551cbc7 | 11590 | } |
2b835d68 | 11591 | else |
d5b7b3ae | 11592 | mp->prev->next = mp; |
2b835d68 | 11593 | |
d5b7b3ae RE |
11594 | minipool_vector_tail = mp; |
11595 | } | |
11596 | else | |
11597 | { | |
11598 | if (max_address > max_mp->max_address - mp->fix_size) | |
11599 | mp->max_address = max_mp->max_address - mp->fix_size; | |
11600 | else | |
11601 | mp->max_address = max_address; | |
11602 | ||
11603 | mp->next = max_mp; | |
11604 | mp->prev = max_mp->prev; | |
11605 | max_mp->prev = mp; | |
11606 | if (mp->prev != NULL) | |
11607 | mp->prev->next = mp; | |
11608 | else | |
11609 | minipool_vector_head = mp; | |
11610 | } | |
11611 | ||
11612 | /* Save the new entry. */ | |
11613 | max_mp = mp; | |
11614 | ||
d6a7951f | 11615 | /* Scan over the preceding entries and adjust their addresses as |
d5b7b3ae RE |
11616 | required. */ |
11617 | while (mp->prev != NULL | |
11618 | && mp->prev->max_address > mp->max_address - mp->prev->fix_size) | |
11619 | { | |
11620 | mp->prev->max_address = mp->max_address - mp->prev->fix_size; | |
11621 | mp = mp->prev; | |
2b835d68 RE |
11622 | } |
11623 | ||
d5b7b3ae RE |
11624 | return max_mp; |
11625 | } | |
11626 | ||
11627 | static Mnode * | |
e32bac5b RE |
11628 | move_minipool_fix_backward_ref (Mnode *mp, Mnode *min_mp, |
11629 | HOST_WIDE_INT min_address) | |
d5b7b3ae RE |
11630 | { |
11631 | HOST_WIDE_INT offset; | |
11632 | ||
e6d29d15 NS |
11633 | /* The code below assumes these are different. */ |
11634 | gcc_assert (mp != min_mp); | |
d5b7b3ae RE |
11635 | |
11636 | if (min_mp == NULL) | |
2b835d68 | 11637 | { |
d5b7b3ae RE |
11638 | if (min_address > mp->min_address) |
11639 | mp->min_address = min_address; | |
11640 | } | |
11641 | else | |
11642 | { | |
11643 | /* We will adjust this below if it is too loose. */ | |
11644 | mp->min_address = min_address; | |
11645 | ||
11646 | /* Unlink MP from its current position. Since min_mp is non-null, | |
11647 | mp->next must be non-null. */ | |
11648 | mp->next->prev = mp->prev; | |
11649 | if (mp->prev != NULL) | |
11650 | mp->prev->next = mp->next; | |
11651 | else | |
11652 | minipool_vector_head = mp->next; | |
11653 | ||
11654 | /* Reinsert it after MIN_MP. */ | |
11655 | mp->prev = min_mp; | |
11656 | mp->next = min_mp->next; | |
11657 | min_mp->next = mp; | |
11658 | if (mp->next != NULL) | |
11659 | mp->next->prev = mp; | |
2b835d68 | 11660 | else |
d5b7b3ae RE |
11661 | minipool_vector_tail = mp; |
11662 | } | |
11663 | ||
11664 | min_mp = mp; | |
11665 | ||
11666 | offset = 0; | |
11667 | for (mp = minipool_vector_head; mp != NULL; mp = mp->next) | |
11668 | { | |
11669 | mp->offset = offset; | |
11670 | if (mp->refcount > 0) | |
11671 | offset += mp->fix_size; | |
11672 | ||
11673 | if (mp->next && mp->next->min_address < mp->min_address + mp->fix_size) | |
11674 | mp->next->min_address = mp->min_address + mp->fix_size; | |
11675 | } | |
11676 | ||
11677 | return min_mp; | |
f676971a | 11678 | } |
d5b7b3ae RE |
11679 | |
11680 | /* Add a constant to the minipool for a backward reference. Returns the | |
f676971a | 11681 | node added or NULL if the constant will not fit in this pool. |
d5b7b3ae RE |
11682 | |
11683 | Note that the code for insertion for a backwards reference can be | |
11684 | somewhat confusing because the calculated offsets for each fix do | |
11685 | not take into account the size of the pool (which is still under | |
11686 | construction. */ | |
11687 | static Mnode * | |
e32bac5b | 11688 | add_minipool_backward_ref (Mfix *fix) |
d5b7b3ae RE |
11689 | { |
11690 | /* If set, min_mp is the last pool_entry that has a lower constraint | |
11691 | than the one we are trying to add. */ | |
e32bac5b | 11692 | Mnode *min_mp = NULL; |
d5b7b3ae RE |
11693 | /* This can be negative, since it is only a constraint. */ |
11694 | HOST_WIDE_INT min_address = fix->address - fix->backwards; | |
e32bac5b | 11695 | Mnode *mp; |
d5b7b3ae RE |
11696 | |
11697 | /* If we can't reach the current pool from this insn, or if we can't | |
11698 | insert this entry at the end of the pool without pushing other | |
11699 | fixes out of range, then we don't try. This ensures that we | |
11700 | can't fail later on. */ | |
11701 | if (min_address >= minipool_barrier->address | |
11702 | || (minipool_vector_tail->min_address + fix->fix_size | |
11703 | >= minipool_barrier->address)) | |
11704 | return NULL; | |
11705 | ||
11706 | /* Scan the pool to see if a constant with the same value has | |
11707 | already been added. While we are doing this, also note the | |
11708 | location where we must insert the constant if it doesn't already | |
11709 | exist. */ | |
11710 | for (mp = minipool_vector_tail; mp != NULL; mp = mp->prev) | |
11711 | { | |
11712 | if (GET_CODE (fix->value) == GET_CODE (mp->value) | |
11713 | && fix->mode == mp->mode | |
11714 | && (GET_CODE (fix->value) != CODE_LABEL | |
11715 | || (CODE_LABEL_NUMBER (fix->value) | |
11716 | == CODE_LABEL_NUMBER (mp->value))) | |
11717 | && rtx_equal_p (fix->value, mp->value) | |
11718 | /* Check that there is enough slack to move this entry to the | |
11719 | end of the table (this is conservative). */ | |
f676971a EC |
11720 | && (mp->max_address |
11721 | > (minipool_barrier->address | |
d5b7b3ae RE |
11722 | + minipool_vector_tail->offset |
11723 | + minipool_vector_tail->fix_size))) | |
11724 | { | |
11725 | mp->refcount++; | |
11726 | return move_minipool_fix_backward_ref (mp, min_mp, min_address); | |
11727 | } | |
11728 | ||
11729 | if (min_mp != NULL) | |
11730 | mp->min_address += fix->fix_size; | |
11731 | else | |
11732 | { | |
11733 | /* Note the insertion point if necessary. */ | |
11734 | if (mp->min_address < min_address) | |
5a9335ef NC |
11735 | { |
11736 | /* For now, we do not allow the insertion of 8-byte alignment | |
11737 | requiring nodes anywhere but at the start of the pool. */ | |
5848830f | 11738 | if (ARM_DOUBLEWORD_ALIGN |
88f77cba | 11739 | && fix->fix_size >= 8 && mp->fix_size < 8) |
5a9335ef NC |
11740 | return NULL; |
11741 | else | |
11742 | min_mp = mp; | |
11743 | } | |
d5b7b3ae RE |
11744 | else if (mp->max_address |
11745 | < minipool_barrier->address + mp->offset + fix->fix_size) | |
11746 | { | |
11747 | /* Inserting before this entry would push the fix beyond | |
11748 | its maximum address (which can happen if we have | |
11749 | re-located a forwards fix); force the new fix to come | |
11750 | after it. */ | |
853ff9e2 JM |
11751 | if (ARM_DOUBLEWORD_ALIGN |
11752 | && fix->fix_size >= 8 && mp->fix_size < 8) | |
11753 | return NULL; | |
11754 | else | |
11755 | { | |
11756 | min_mp = mp; | |
11757 | min_address = mp->min_address + fix->fix_size; | |
11758 | } | |
d5b7b3ae | 11759 | } |
853ff9e2 JM |
11760 | /* Do not insert a non-8-byte aligned quantity before 8-byte |
11761 | aligned quantities. */ | |
5848830f | 11762 | else if (ARM_DOUBLEWORD_ALIGN |
853ff9e2 JM |
11763 | && fix->fix_size < 8 |
11764 | && mp->fix_size >= 8) | |
5a9335ef NC |
11765 | { |
11766 | min_mp = mp; | |
11767 | min_address = mp->min_address + fix->fix_size; | |
11768 | } | |
d5b7b3ae RE |
11769 | } |
11770 | } | |
11771 | ||
11772 | /* We need to create a new entry. */ | |
5ed6ace5 | 11773 | mp = XNEW (Mnode); |
d5b7b3ae RE |
11774 | mp->fix_size = fix->fix_size; |
11775 | mp->mode = fix->mode; | |
11776 | mp->value = fix->value; | |
11777 | mp->refcount = 1; | |
11778 | mp->max_address = minipool_barrier->address + 65536; | |
11779 | ||
11780 | mp->min_address = min_address; | |
11781 | ||
11782 | if (min_mp == NULL) | |
11783 | { | |
11784 | mp->prev = NULL; | |
11785 | mp->next = minipool_vector_head; | |
11786 | ||
11787 | if (mp->next == NULL) | |
11788 | { | |
11789 | minipool_vector_tail = mp; | |
11790 | minipool_vector_label = gen_label_rtx (); | |
11791 | } | |
11792 | else | |
11793 | mp->next->prev = mp; | |
11794 | ||
11795 | minipool_vector_head = mp; | |
11796 | } | |
11797 | else | |
11798 | { | |
11799 | mp->next = min_mp->next; | |
11800 | mp->prev = min_mp; | |
11801 | min_mp->next = mp; | |
f676971a | 11802 | |
d5b7b3ae RE |
11803 | if (mp->next != NULL) |
11804 | mp->next->prev = mp; | |
11805 | else | |
11806 | minipool_vector_tail = mp; | |
11807 | } | |
11808 | ||
11809 | /* Save the new entry. */ | |
11810 | min_mp = mp; | |
11811 | ||
11812 | if (mp->prev) | |
11813 | mp = mp->prev; | |
11814 | else | |
11815 | mp->offset = 0; | |
11816 | ||
11817 | /* Scan over the following entries and adjust their offsets. */ | |
11818 | while (mp->next != NULL) | |
11819 | { | |
11820 | if (mp->next->min_address < mp->min_address + mp->fix_size) | |
11821 | mp->next->min_address = mp->min_address + mp->fix_size; | |
11822 | ||
11823 | if (mp->refcount) | |
11824 | mp->next->offset = mp->offset + mp->fix_size; | |
11825 | else | |
11826 | mp->next->offset = mp->offset; | |
11827 | ||
11828 | mp = mp->next; | |
11829 | } | |
11830 | ||
11831 | return min_mp; | |
11832 | } | |
11833 | ||
11834 | static void | |
e32bac5b | 11835 | assign_minipool_offsets (Mfix *barrier) |
d5b7b3ae RE |
11836 | { |
11837 | HOST_WIDE_INT offset = 0; | |
e32bac5b | 11838 | Mnode *mp; |
d5b7b3ae RE |
11839 | |
11840 | minipool_barrier = barrier; | |
11841 | ||
11842 | for (mp = minipool_vector_head; mp != NULL; mp = mp->next) | |
11843 | { | |
11844 | mp->offset = offset; | |
f676971a | 11845 | |
d5b7b3ae RE |
11846 | if (mp->refcount > 0) |
11847 | offset += mp->fix_size; | |
11848 | } | |
11849 | } | |
11850 | ||
11851 | /* Output the literal table */ | |
11852 | static void | |
e32bac5b | 11853 | dump_minipool (rtx scan) |
d5b7b3ae | 11854 | { |
5a9335ef NC |
11855 | Mnode * mp; |
11856 | Mnode * nmp; | |
11857 | int align64 = 0; | |
11858 | ||
5848830f | 11859 | if (ARM_DOUBLEWORD_ALIGN) |
5a9335ef | 11860 | for (mp = minipool_vector_head; mp != NULL; mp = mp->next) |
88f77cba | 11861 | if (mp->refcount > 0 && mp->fix_size >= 8) |
5a9335ef NC |
11862 | { |
11863 | align64 = 1; | |
11864 | break; | |
11865 | } | |
d5b7b3ae | 11866 | |
c263766c RH |
11867 | if (dump_file) |
11868 | fprintf (dump_file, | |
5a9335ef NC |
11869 | ";; Emitting minipool after insn %u; address %ld; align %d (bytes)\n", |
11870 | INSN_UID (scan), (unsigned long) minipool_barrier->address, align64 ? 8 : 4); | |
d5b7b3ae RE |
11871 | |
11872 | scan = emit_label_after (gen_label_rtx (), scan); | |
5a9335ef | 11873 | scan = emit_insn_after (align64 ? gen_align_8 () : gen_align_4 (), scan); |
d5b7b3ae RE |
11874 | scan = emit_label_after (minipool_vector_label, scan); |
11875 | ||
11876 | for (mp = minipool_vector_head; mp != NULL; mp = nmp) | |
11877 | { | |
11878 | if (mp->refcount > 0) | |
11879 | { | |
c263766c | 11880 | if (dump_file) |
d5b7b3ae | 11881 | { |
f676971a | 11882 | fprintf (dump_file, |
d5b7b3ae RE |
11883 | ";; Offset %u, min %ld, max %ld ", |
11884 | (unsigned) mp->offset, (unsigned long) mp->min_address, | |
11885 | (unsigned long) mp->max_address); | |
c263766c RH |
11886 | arm_print_value (dump_file, mp->value); |
11887 | fputc ('\n', dump_file); | |
d5b7b3ae RE |
11888 | } |
11889 | ||
11890 | switch (mp->fix_size) | |
11891 | { | |
11892 | #ifdef HAVE_consttable_1 | |
11893 | case 1: | |
11894 | scan = emit_insn_after (gen_consttable_1 (mp->value), scan); | |
11895 | break; | |
11896 | ||
11897 | #endif | |
11898 | #ifdef HAVE_consttable_2 | |
11899 | case 2: | |
11900 | scan = emit_insn_after (gen_consttable_2 (mp->value), scan); | |
11901 | break; | |
11902 | ||
11903 | #endif | |
11904 | #ifdef HAVE_consttable_4 | |
11905 | case 4: | |
11906 | scan = emit_insn_after (gen_consttable_4 (mp->value), scan); | |
11907 | break; | |
11908 | ||
11909 | #endif | |
11910 | #ifdef HAVE_consttable_8 | |
11911 | case 8: | |
11912 | scan = emit_insn_after (gen_consttable_8 (mp->value), scan); | |
11913 | break; | |
11914 | ||
88f77cba JB |
11915 | #endif |
11916 | #ifdef HAVE_consttable_16 | |
11917 | case 16: | |
11918 | scan = emit_insn_after (gen_consttable_16 (mp->value), scan); | |
11919 | break; | |
11920 | ||
d5b7b3ae RE |
11921 | #endif |
11922 | default: | |
e6d29d15 | 11923 | gcc_unreachable (); |
d5b7b3ae RE |
11924 | } |
11925 | } | |
11926 | ||
11927 | nmp = mp->next; | |
11928 | free (mp); | |
2b835d68 RE |
11929 | } |
11930 | ||
d5b7b3ae RE |
11931 | minipool_vector_head = minipool_vector_tail = NULL; |
11932 | scan = emit_insn_after (gen_consttable_end (), scan); | |
11933 | scan = emit_barrier_after (scan); | |
2b835d68 RE |
11934 | } |
11935 | ||
d5b7b3ae RE |
11936 | /* Return the cost of forcibly inserting a barrier after INSN. */ |
11937 | static int | |
e32bac5b | 11938 | arm_barrier_cost (rtx insn) |
949d79eb | 11939 | { |
d5b7b3ae RE |
11940 | /* Basing the location of the pool on the loop depth is preferable, |
11941 | but at the moment, the basic block information seems to be | |
11942 | corrupt by this stage of the compilation. */ | |
11943 | int base_cost = 50; | |
11944 | rtx next = next_nonnote_insn (insn); | |
11945 | ||
11946 | if (next != NULL && GET_CODE (next) == CODE_LABEL) | |
11947 | base_cost -= 20; | |
11948 | ||
11949 | switch (GET_CODE (insn)) | |
11950 | { | |
11951 | case CODE_LABEL: | |
11952 | /* It will always be better to place the table before the label, rather | |
11953 | than after it. */ | |
f676971a | 11954 | return 50; |
949d79eb | 11955 | |
d5b7b3ae RE |
11956 | case INSN: |
11957 | case CALL_INSN: | |
11958 | return base_cost; | |
11959 | ||
11960 | case JUMP_INSN: | |
11961 | return base_cost - 10; | |
11962 | ||
11963 | default: | |
11964 | return base_cost + 10; | |
11965 | } | |
11966 | } | |
11967 | ||
11968 | /* Find the best place in the insn stream in the range | |
11969 | (FIX->address,MAX_ADDRESS) to forcibly insert a minipool barrier. | |
11970 | Create the barrier by inserting a jump and add a new fix entry for | |
11971 | it. */ | |
11972 | static Mfix * | |
e32bac5b | 11973 | create_fix_barrier (Mfix *fix, HOST_WIDE_INT max_address) |
d5b7b3ae RE |
11974 | { |
11975 | HOST_WIDE_INT count = 0; | |
11976 | rtx barrier; | |
11977 | rtx from = fix->insn; | |
7a7017bc PB |
11978 | /* The instruction after which we will insert the jump. */ |
11979 | rtx selected = NULL; | |
d5b7b3ae | 11980 | int selected_cost; |
7a7017bc | 11981 | /* The address at which the jump instruction will be placed. */ |
d5b7b3ae RE |
11982 | HOST_WIDE_INT selected_address; |
11983 | Mfix * new_fix; | |
11984 | HOST_WIDE_INT max_count = max_address - fix->address; | |
11985 | rtx label = gen_label_rtx (); | |
11986 | ||
11987 | selected_cost = arm_barrier_cost (from); | |
11988 | selected_address = fix->address; | |
11989 | ||
11990 | while (from && count < max_count) | |
11991 | { | |
11992 | rtx tmp; | |
11993 | int new_cost; | |
11994 | ||
11995 | /* This code shouldn't have been called if there was a natural barrier | |
11996 | within range. */ | |
e6d29d15 | 11997 | gcc_assert (GET_CODE (from) != BARRIER); |
d5b7b3ae RE |
11998 | |
11999 | /* Count the length of this insn. */ | |
12000 | count += get_attr_length (from); | |
12001 | ||
12002 | /* If there is a jump table, add its length. */ | |
12003 | tmp = is_jump_table (from); | |
12004 | if (tmp != NULL) | |
12005 | { | |
12006 | count += get_jump_table_size (tmp); | |
12007 | ||
12008 | /* Jump tables aren't in a basic block, so base the cost on | |
12009 | the dispatch insn. If we select this location, we will | |
12010 | still put the pool after the table. */ | |
12011 | new_cost = arm_barrier_cost (from); | |
12012 | ||
7a7017bc PB |
12013 | if (count < max_count |
12014 | && (!selected || new_cost <= selected_cost)) | |
d5b7b3ae RE |
12015 | { |
12016 | selected = tmp; | |
12017 | selected_cost = new_cost; | |
12018 | selected_address = fix->address + count; | |
12019 | } | |
12020 | ||
12021 | /* Continue after the dispatch table. */ | |
12022 | from = NEXT_INSN (tmp); | |
12023 | continue; | |
12024 | } | |
12025 | ||
12026 | new_cost = arm_barrier_cost (from); | |
f676971a | 12027 | |
7a7017bc PB |
12028 | if (count < max_count |
12029 | && (!selected || new_cost <= selected_cost)) | |
d5b7b3ae RE |
12030 | { |
12031 | selected = from; | |
12032 | selected_cost = new_cost; | |
12033 | selected_address = fix->address + count; | |
12034 | } | |
12035 | ||
12036 | from = NEXT_INSN (from); | |
12037 | } | |
12038 | ||
7a7017bc PB |
12039 | /* Make sure that we found a place to insert the jump. */ |
12040 | gcc_assert (selected); | |
12041 | ||
b6a75dda RR |
12042 | /* Make sure we do not split a call and its corresponding |
12043 | CALL_ARG_LOCATION note. */ | |
12044 | if (CALL_P (selected)) | |
12045 | { | |
12046 | rtx next = NEXT_INSN (selected); | |
12047 | if (next && NOTE_P (next) | |
12048 | && NOTE_KIND (next) == NOTE_INSN_CALL_ARG_LOCATION) | |
12049 | selected = next; | |
12050 | } | |
12051 | ||
d5b7b3ae RE |
12052 | /* Create a new JUMP_INSN that branches around a barrier. */ |
12053 | from = emit_jump_insn_after (gen_jump (label), selected); | |
12054 | JUMP_LABEL (from) = label; | |
12055 | barrier = emit_barrier_after (from); | |
12056 | emit_label_after (label, barrier); | |
12057 | ||
12058 | /* Create a minipool barrier entry for the new barrier. */ | |
c7319d87 | 12059 | new_fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* new_fix)); |
d5b7b3ae RE |
12060 | new_fix->insn = barrier; |
12061 | new_fix->address = selected_address; | |
12062 | new_fix->next = fix->next; | |
12063 | fix->next = new_fix; | |
12064 | ||
12065 | return new_fix; | |
12066 | } | |
12067 | ||
12068 | /* Record that there is a natural barrier in the insn stream at | |
12069 | ADDRESS. */ | |
949d79eb | 12070 | static void |
e32bac5b | 12071 | push_minipool_barrier (rtx insn, HOST_WIDE_INT address) |
2b835d68 | 12072 | { |
c7319d87 | 12073 | Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix)); |
ad076f4e | 12074 | |
949d79eb RE |
12075 | fix->insn = insn; |
12076 | fix->address = address; | |
2b835d68 | 12077 | |
949d79eb RE |
12078 | fix->next = NULL; |
12079 | if (minipool_fix_head != NULL) | |
12080 | minipool_fix_tail->next = fix; | |
12081 | else | |
12082 | minipool_fix_head = fix; | |
12083 | ||
12084 | minipool_fix_tail = fix; | |
12085 | } | |
2b835d68 | 12086 | |
d5b7b3ae RE |
12087 | /* Record INSN, which will need fixing up to load a value from the |
12088 | minipool. ADDRESS is the offset of the insn since the start of the | |
12089 | function; LOC is a pointer to the part of the insn which requires | |
12090 | fixing; VALUE is the constant that must be loaded, which is of type | |
12091 | MODE. */ | |
949d79eb | 12092 | static void |
e32bac5b RE |
12093 | push_minipool_fix (rtx insn, HOST_WIDE_INT address, rtx *loc, |
12094 | enum machine_mode mode, rtx value) | |
949d79eb | 12095 | { |
c7319d87 | 12096 | Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix)); |
949d79eb | 12097 | |
949d79eb RE |
12098 | fix->insn = insn; |
12099 | fix->address = address; | |
12100 | fix->loc = loc; | |
12101 | fix->mode = mode; | |
d5b7b3ae | 12102 | fix->fix_size = MINIPOOL_FIX_SIZE (mode); |
949d79eb | 12103 | fix->value = value; |
d5b7b3ae RE |
12104 | fix->forwards = get_attr_pool_range (insn); |
12105 | fix->backwards = get_attr_neg_pool_range (insn); | |
12106 | fix->minipool = NULL; | |
949d79eb RE |
12107 | |
12108 | /* If an insn doesn't have a range defined for it, then it isn't | |
e6d29d15 | 12109 | expecting to be reworked by this code. Better to stop now than |
949d79eb | 12110 | to generate duff assembly code. */ |
e6d29d15 | 12111 | gcc_assert (fix->forwards || fix->backwards); |
949d79eb | 12112 | |
34a9f549 PB |
12113 | /* If an entry requires 8-byte alignment then assume all constant pools |
12114 | require 4 bytes of padding. Trying to do this later on a per-pool | |
917f1b7e | 12115 | basis is awkward because existing pool entries have to be modified. */ |
88f77cba | 12116 | if (ARM_DOUBLEWORD_ALIGN && fix->fix_size >= 8) |
34a9f549 | 12117 | minipool_pad = 4; |
5a9335ef | 12118 | |
c263766c | 12119 | if (dump_file) |
d5b7b3ae | 12120 | { |
c263766c | 12121 | fprintf (dump_file, |
d5b7b3ae RE |
12122 | ";; %smode fixup for i%d; addr %lu, range (%ld,%ld): ", |
12123 | GET_MODE_NAME (mode), | |
f676971a | 12124 | INSN_UID (insn), (unsigned long) address, |
d5b7b3ae | 12125 | -1 * (long)fix->backwards, (long)fix->forwards); |
c263766c RH |
12126 | arm_print_value (dump_file, fix->value); |
12127 | fprintf (dump_file, "\n"); | |
d5b7b3ae RE |
12128 | } |
12129 | ||
6354dc9b | 12130 | /* Add it to the chain of fixes. */ |
949d79eb | 12131 | fix->next = NULL; |
f676971a | 12132 | |
949d79eb RE |
12133 | if (minipool_fix_head != NULL) |
12134 | minipool_fix_tail->next = fix; | |
12135 | else | |
12136 | minipool_fix_head = fix; | |
12137 | ||
12138 | minipool_fix_tail = fix; | |
12139 | } | |
12140 | ||
9b901d50 | 12141 | /* Return the cost of synthesizing a 64-bit constant VAL inline. |
2075b05d RE |
12142 | Returns the number of insns needed, or 99 if we don't know how to |
12143 | do it. */ | |
12144 | int | |
12145 | arm_const_double_inline_cost (rtx val) | |
b9e8bfda | 12146 | { |
9b901d50 RE |
12147 | rtx lowpart, highpart; |
12148 | enum machine_mode mode; | |
e0b92319 | 12149 | |
9b901d50 | 12150 | mode = GET_MODE (val); |
b9e8bfda | 12151 | |
9b901d50 RE |
12152 | if (mode == VOIDmode) |
12153 | mode = DImode; | |
12154 | ||
12155 | gcc_assert (GET_MODE_SIZE (mode) == 8); | |
e0b92319 | 12156 | |
9b901d50 RE |
12157 | lowpart = gen_lowpart (SImode, val); |
12158 | highpart = gen_highpart_mode (SImode, mode, val); | |
e0b92319 | 12159 | |
9b901d50 RE |
12160 | gcc_assert (GET_CODE (lowpart) == CONST_INT); |
12161 | gcc_assert (GET_CODE (highpart) == CONST_INT); | |
12162 | ||
12163 | return (arm_gen_constant (SET, SImode, NULL_RTX, INTVAL (lowpart), | |
2075b05d | 12164 | NULL_RTX, NULL_RTX, 0, 0) |
9b901d50 | 12165 | + arm_gen_constant (SET, SImode, NULL_RTX, INTVAL (highpart), |
2075b05d RE |
12166 | NULL_RTX, NULL_RTX, 0, 0)); |
12167 | } | |
12168 | ||
f3b569ca | 12169 | /* Return true if it is worthwhile to split a 64-bit constant into two |
b4a58f80 RE |
12170 | 32-bit operations. This is the case if optimizing for size, or |
12171 | if we have load delay slots, or if one 32-bit part can be done with | |
12172 | a single data operation. */ | |
12173 | bool | |
12174 | arm_const_double_by_parts (rtx val) | |
12175 | { | |
12176 | enum machine_mode mode = GET_MODE (val); | |
12177 | rtx part; | |
12178 | ||
12179 | if (optimize_size || arm_ld_sched) | |
12180 | return true; | |
12181 | ||
12182 | if (mode == VOIDmode) | |
12183 | mode = DImode; | |
e0b92319 | 12184 | |
b4a58f80 | 12185 | part = gen_highpart_mode (SImode, mode, val); |
e0b92319 | 12186 | |
b4a58f80 | 12187 | gcc_assert (GET_CODE (part) == CONST_INT); |
e0b92319 | 12188 | |
b4a58f80 RE |
12189 | if (const_ok_for_arm (INTVAL (part)) |
12190 | || const_ok_for_arm (~INTVAL (part))) | |
12191 | return true; | |
e0b92319 | 12192 | |
b4a58f80 | 12193 | part = gen_lowpart (SImode, val); |
e0b92319 | 12194 | |
b4a58f80 | 12195 | gcc_assert (GET_CODE (part) == CONST_INT); |
e0b92319 | 12196 | |
b4a58f80 RE |
12197 | if (const_ok_for_arm (INTVAL (part)) |
12198 | || const_ok_for_arm (~INTVAL (part))) | |
12199 | return true; | |
e0b92319 | 12200 | |
b4a58f80 RE |
12201 | return false; |
12202 | } | |
12203 | ||
73160ba9 DJ |
12204 | /* Return true if it is possible to inline both the high and low parts |
12205 | of a 64-bit constant into 32-bit data processing instructions. */ | |
12206 | bool | |
12207 | arm_const_double_by_immediates (rtx val) | |
12208 | { | |
12209 | enum machine_mode mode = GET_MODE (val); | |
12210 | rtx part; | |
12211 | ||
12212 | if (mode == VOIDmode) | |
12213 | mode = DImode; | |
12214 | ||
12215 | part = gen_highpart_mode (SImode, mode, val); | |
12216 | ||
12217 | gcc_assert (GET_CODE (part) == CONST_INT); | |
12218 | ||
12219 | if (!const_ok_for_arm (INTVAL (part))) | |
12220 | return false; | |
12221 | ||
12222 | part = gen_lowpart (SImode, val); | |
12223 | ||
12224 | gcc_assert (GET_CODE (part) == CONST_INT); | |
12225 | ||
12226 | if (!const_ok_for_arm (INTVAL (part))) | |
12227 | return false; | |
12228 | ||
12229 | return true; | |
12230 | } | |
12231 | ||
f0375c66 NC |
12232 | /* Scan INSN and note any of its operands that need fixing. |
12233 | If DO_PUSHES is false we do not actually push any of the fixups | |
9b901d50 | 12234 | needed. The function returns TRUE if any fixups were needed/pushed. |
f0375c66 NC |
12235 | This is used by arm_memory_load_p() which needs to know about loads |
12236 | of constants that will be converted into minipool loads. */ | |
f0375c66 | 12237 | static bool |
e32bac5b | 12238 | note_invalid_constants (rtx insn, HOST_WIDE_INT address, int do_pushes) |
949d79eb | 12239 | { |
f0375c66 | 12240 | bool result = false; |
949d79eb RE |
12241 | int opno; |
12242 | ||
d5b7b3ae | 12243 | extract_insn (insn); |
949d79eb | 12244 | |
5895f793 | 12245 | if (!constrain_operands (1)) |
949d79eb RE |
12246 | fatal_insn_not_found (insn); |
12247 | ||
8c2a5582 RE |
12248 | if (recog_data.n_alternatives == 0) |
12249 | return false; | |
12250 | ||
9b901d50 RE |
12251 | /* Fill in recog_op_alt with information about the constraints of |
12252 | this insn. */ | |
949d79eb RE |
12253 | preprocess_constraints (); |
12254 | ||
1ccbefce | 12255 | for (opno = 0; opno < recog_data.n_operands; opno++) |
949d79eb | 12256 | { |
6354dc9b | 12257 | /* Things we need to fix can only occur in inputs. */ |
36ab44c7 | 12258 | if (recog_data.operand_type[opno] != OP_IN) |
949d79eb RE |
12259 | continue; |
12260 | ||
12261 | /* If this alternative is a memory reference, then any mention | |
12262 | of constants in this alternative is really to fool reload | |
12263 | into allowing us to accept one there. We need to fix them up | |
12264 | now so that we output the right code. */ | |
12265 | if (recog_op_alt[opno][which_alternative].memory_ok) | |
12266 | { | |
1ccbefce | 12267 | rtx op = recog_data.operand[opno]; |
949d79eb | 12268 | |
9b901d50 | 12269 | if (CONSTANT_P (op)) |
f0375c66 NC |
12270 | { |
12271 | if (do_pushes) | |
12272 | push_minipool_fix (insn, address, recog_data.operand_loc[opno], | |
12273 | recog_data.operand_mode[opno], op); | |
12274 | result = true; | |
12275 | } | |
d5b7b3ae | 12276 | else if (GET_CODE (op) == MEM |
949d79eb RE |
12277 | && GET_CODE (XEXP (op, 0)) == SYMBOL_REF |
12278 | && CONSTANT_POOL_ADDRESS_P (XEXP (op, 0))) | |
f0375c66 NC |
12279 | { |
12280 | if (do_pushes) | |
244b1afb RE |
12281 | { |
12282 | rtx cop = avoid_constant_pool_reference (op); | |
12283 | ||
12284 | /* Casting the address of something to a mode narrower | |
12285 | than a word can cause avoid_constant_pool_reference() | |
12286 | to return the pool reference itself. That's no good to | |
f676971a | 12287 | us here. Lets just hope that we can use the |
244b1afb RE |
12288 | constant pool value directly. */ |
12289 | if (op == cop) | |
c769a35d | 12290 | cop = get_pool_constant (XEXP (op, 0)); |
244b1afb RE |
12291 | |
12292 | push_minipool_fix (insn, address, | |
12293 | recog_data.operand_loc[opno], | |
c769a35d | 12294 | recog_data.operand_mode[opno], cop); |
244b1afb | 12295 | } |
f0375c66 NC |
12296 | |
12297 | result = true; | |
12298 | } | |
949d79eb | 12299 | } |
2b835d68 | 12300 | } |
f0375c66 NC |
12301 | |
12302 | return result; | |
2b835d68 RE |
12303 | } |
12304 | ||
eef5973d BS |
12305 | /* Convert instructions to their cc-clobbering variant if possible, since |
12306 | that allows us to use smaller encodings. */ | |
12307 | ||
12308 | static void | |
12309 | thumb2_reorg (void) | |
12310 | { | |
12311 | basic_block bb; | |
12312 | regset_head live; | |
12313 | ||
12314 | INIT_REG_SET (&live); | |
12315 | ||
12316 | /* We are freeing block_for_insn in the toplev to keep compatibility | |
12317 | with old MDEP_REORGS that are not CFG based. Recompute it now. */ | |
12318 | compute_bb_for_insn (); | |
12319 | df_analyze (); | |
12320 | ||
12321 | FOR_EACH_BB (bb) | |
12322 | { | |
12323 | rtx insn; | |
c994a0ce | 12324 | |
eef5973d BS |
12325 | COPY_REG_SET (&live, DF_LR_OUT (bb)); |
12326 | df_simulate_initialize_backwards (bb, &live); | |
12327 | FOR_BB_INSNS_REVERSE (bb, insn) | |
12328 | { | |
12329 | if (NONJUMP_INSN_P (insn) | |
12330 | && !REGNO_REG_SET_P (&live, CC_REGNUM)) | |
12331 | { | |
12332 | rtx pat = PATTERN (insn); | |
12333 | if (GET_CODE (pat) == SET | |
12334 | && low_register_operand (XEXP (pat, 0), SImode) | |
12335 | && thumb_16bit_operator (XEXP (pat, 1), SImode) | |
12336 | && low_register_operand (XEXP (XEXP (pat, 1), 0), SImode) | |
12337 | && low_register_operand (XEXP (XEXP (pat, 1), 1), SImode)) | |
12338 | { | |
12339 | rtx dst = XEXP (pat, 0); | |
12340 | rtx src = XEXP (pat, 1); | |
12341 | rtx op0 = XEXP (src, 0); | |
c994a0ce RE |
12342 | rtx op1 = (GET_RTX_CLASS (GET_CODE (src)) == RTX_COMM_ARITH |
12343 | ? XEXP (src, 1) : NULL); | |
12344 | ||
eef5973d BS |
12345 | if (rtx_equal_p (dst, op0) |
12346 | || GET_CODE (src) == PLUS || GET_CODE (src) == MINUS) | |
12347 | { | |
12348 | rtx ccreg = gen_rtx_REG (CCmode, CC_REGNUM); | |
12349 | rtx clobber = gen_rtx_CLOBBER (VOIDmode, ccreg); | |
f63a6726 | 12350 | rtvec vec = gen_rtvec (2, pat, clobber); |
c994a0ce RE |
12351 | |
12352 | PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode, vec); | |
12353 | INSN_CODE (insn) = -1; | |
12354 | } | |
12355 | /* We can also handle a commutative operation where the | |
12356 | second operand matches the destination. */ | |
12357 | else if (op1 && rtx_equal_p (dst, op1)) | |
12358 | { | |
12359 | rtx ccreg = gen_rtx_REG (CCmode, CC_REGNUM); | |
12360 | rtx clobber = gen_rtx_CLOBBER (VOIDmode, ccreg); | |
12361 | rtvec vec; | |
12362 | ||
12363 | src = copy_rtx (src); | |
12364 | XEXP (src, 0) = op1; | |
12365 | XEXP (src, 1) = op0; | |
12366 | pat = gen_rtx_SET (VOIDmode, dst, src); | |
12367 | vec = gen_rtvec (2, pat, clobber); | |
eef5973d BS |
12368 | PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode, vec); |
12369 | INSN_CODE (insn) = -1; | |
12370 | } | |
12371 | } | |
12372 | } | |
c994a0ce | 12373 | |
eef5973d BS |
12374 | if (NONDEBUG_INSN_P (insn)) |
12375 | df_simulate_one_insn_backwards (bb, insn, &live); | |
12376 | } | |
12377 | } | |
c994a0ce | 12378 | |
eef5973d BS |
12379 | CLEAR_REG_SET (&live); |
12380 | } | |
12381 | ||
18dbd950 RS |
12382 | /* Gcc puts the pool in the wrong place for ARM, since we can only |
12383 | load addresses a limited distance around the pc. We do some | |
12384 | special munging to move the constant pool values to the correct | |
12385 | point in the code. */ | |
18dbd950 | 12386 | static void |
e32bac5b | 12387 | arm_reorg (void) |
2b835d68 RE |
12388 | { |
12389 | rtx insn; | |
d5b7b3ae RE |
12390 | HOST_WIDE_INT address = 0; |
12391 | Mfix * fix; | |
ad076f4e | 12392 | |
eef5973d BS |
12393 | if (TARGET_THUMB2) |
12394 | thumb2_reorg (); | |
12395 | ||
949d79eb | 12396 | minipool_fix_head = minipool_fix_tail = NULL; |
2b835d68 | 12397 | |
949d79eb RE |
12398 | /* The first insn must always be a note, or the code below won't |
12399 | scan it properly. */ | |
18dbd950 | 12400 | insn = get_insns (); |
e6d29d15 | 12401 | gcc_assert (GET_CODE (insn) == NOTE); |
34a9f549 | 12402 | minipool_pad = 0; |
949d79eb RE |
12403 | |
12404 | /* Scan all the insns and record the operands that will need fixing. */ | |
18dbd950 | 12405 | for (insn = next_nonnote_insn (insn); insn; insn = next_nonnote_insn (insn)) |
2b835d68 | 12406 | { |
9b6b54e2 | 12407 | if (TARGET_CIRRUS_FIX_INVALID_INSNS |
f0375c66 | 12408 | && (arm_cirrus_insn_p (insn) |
9b6b54e2 | 12409 | || GET_CODE (insn) == JUMP_INSN |
f0375c66 | 12410 | || arm_memory_load_p (insn))) |
9b6b54e2 NC |
12411 | cirrus_reorg (insn); |
12412 | ||
949d79eb | 12413 | if (GET_CODE (insn) == BARRIER) |
d5b7b3ae | 12414 | push_minipool_barrier (insn, address); |
f0375c66 | 12415 | else if (INSN_P (insn)) |
949d79eb RE |
12416 | { |
12417 | rtx table; | |
12418 | ||
f0375c66 | 12419 | note_invalid_constants (insn, address, true); |
949d79eb | 12420 | address += get_attr_length (insn); |
d5b7b3ae | 12421 | |
949d79eb RE |
12422 | /* If the insn is a vector jump, add the size of the table |
12423 | and skip the table. */ | |
d5b7b3ae | 12424 | if ((table = is_jump_table (insn)) != NULL) |
2b835d68 | 12425 | { |
d5b7b3ae | 12426 | address += get_jump_table_size (table); |
949d79eb RE |
12427 | insn = table; |
12428 | } | |
12429 | } | |
12430 | } | |
332072db | 12431 | |
d5b7b3ae | 12432 | fix = minipool_fix_head; |
f676971a | 12433 | |
949d79eb | 12434 | /* Now scan the fixups and perform the required changes. */ |
d5b7b3ae | 12435 | while (fix) |
949d79eb | 12436 | { |
d5b7b3ae RE |
12437 | Mfix * ftmp; |
12438 | Mfix * fdel; | |
12439 | Mfix * last_added_fix; | |
12440 | Mfix * last_barrier = NULL; | |
12441 | Mfix * this_fix; | |
949d79eb RE |
12442 | |
12443 | /* Skip any further barriers before the next fix. */ | |
12444 | while (fix && GET_CODE (fix->insn) == BARRIER) | |
12445 | fix = fix->next; | |
12446 | ||
d5b7b3ae | 12447 | /* No more fixes. */ |
949d79eb RE |
12448 | if (fix == NULL) |
12449 | break; | |
332072db | 12450 | |
d5b7b3ae | 12451 | last_added_fix = NULL; |
2b835d68 | 12452 | |
d5b7b3ae | 12453 | for (ftmp = fix; ftmp; ftmp = ftmp->next) |
949d79eb | 12454 | { |
949d79eb | 12455 | if (GET_CODE (ftmp->insn) == BARRIER) |
949d79eb | 12456 | { |
d5b7b3ae RE |
12457 | if (ftmp->address >= minipool_vector_head->max_address) |
12458 | break; | |
2b835d68 | 12459 | |
d5b7b3ae | 12460 | last_barrier = ftmp; |
2b835d68 | 12461 | } |
d5b7b3ae RE |
12462 | else if ((ftmp->minipool = add_minipool_forward_ref (ftmp)) == NULL) |
12463 | break; | |
12464 | ||
12465 | last_added_fix = ftmp; /* Keep track of the last fix added. */ | |
2b835d68 | 12466 | } |
949d79eb | 12467 | |
d5b7b3ae RE |
12468 | /* If we found a barrier, drop back to that; any fixes that we |
12469 | could have reached but come after the barrier will now go in | |
12470 | the next mini-pool. */ | |
949d79eb RE |
12471 | if (last_barrier != NULL) |
12472 | { | |
f676971a | 12473 | /* Reduce the refcount for those fixes that won't go into this |
d5b7b3ae RE |
12474 | pool after all. */ |
12475 | for (fdel = last_barrier->next; | |
12476 | fdel && fdel != ftmp; | |
12477 | fdel = fdel->next) | |
12478 | { | |
12479 | fdel->minipool->refcount--; | |
12480 | fdel->minipool = NULL; | |
12481 | } | |
12482 | ||
949d79eb RE |
12483 | ftmp = last_barrier; |
12484 | } | |
12485 | else | |
2bfa88dc | 12486 | { |
d5b7b3ae RE |
12487 | /* ftmp is first fix that we can't fit into this pool and |
12488 | there no natural barriers that we could use. Insert a | |
12489 | new barrier in the code somewhere between the previous | |
12490 | fix and this one, and arrange to jump around it. */ | |
12491 | HOST_WIDE_INT max_address; | |
12492 | ||
12493 | /* The last item on the list of fixes must be a barrier, so | |
12494 | we can never run off the end of the list of fixes without | |
12495 | last_barrier being set. */ | |
e6d29d15 | 12496 | gcc_assert (ftmp); |
d5b7b3ae RE |
12497 | |
12498 | max_address = minipool_vector_head->max_address; | |
2bfa88dc RE |
12499 | /* Check that there isn't another fix that is in range that |
12500 | we couldn't fit into this pool because the pool was | |
12501 | already too large: we need to put the pool before such an | |
7a7017bc PB |
12502 | instruction. The pool itself may come just after the |
12503 | fix because create_fix_barrier also allows space for a | |
12504 | jump instruction. */ | |
d5b7b3ae | 12505 | if (ftmp->address < max_address) |
7a7017bc | 12506 | max_address = ftmp->address + 1; |
d5b7b3ae RE |
12507 | |
12508 | last_barrier = create_fix_barrier (last_added_fix, max_address); | |
12509 | } | |
12510 | ||
12511 | assign_minipool_offsets (last_barrier); | |
12512 | ||
12513 | while (ftmp) | |
12514 | { | |
12515 | if (GET_CODE (ftmp->insn) != BARRIER | |
12516 | && ((ftmp->minipool = add_minipool_backward_ref (ftmp)) | |
12517 | == NULL)) | |
12518 | break; | |
2bfa88dc | 12519 | |
d5b7b3ae | 12520 | ftmp = ftmp->next; |
2bfa88dc | 12521 | } |
949d79eb RE |
12522 | |
12523 | /* Scan over the fixes we have identified for this pool, fixing them | |
12524 | up and adding the constants to the pool itself. */ | |
d5b7b3ae | 12525 | for (this_fix = fix; this_fix && ftmp != this_fix; |
949d79eb RE |
12526 | this_fix = this_fix->next) |
12527 | if (GET_CODE (this_fix->insn) != BARRIER) | |
12528 | { | |
949d79eb | 12529 | rtx addr |
f676971a | 12530 | = plus_constant (gen_rtx_LABEL_REF (VOIDmode, |
949d79eb | 12531 | minipool_vector_label), |
d5b7b3ae | 12532 | this_fix->minipool->offset); |
949d79eb RE |
12533 | *this_fix->loc = gen_rtx_MEM (this_fix->mode, addr); |
12534 | } | |
12535 | ||
d5b7b3ae | 12536 | dump_minipool (last_barrier->insn); |
949d79eb | 12537 | fix = ftmp; |
2b835d68 | 12538 | } |
4b632bf1 | 12539 | |
949d79eb RE |
12540 | /* From now on we must synthesize any constants that we can't handle |
12541 | directly. This can happen if the RTL gets split during final | |
12542 | instruction generation. */ | |
4b632bf1 | 12543 | after_arm_reorg = 1; |
c7319d87 RE |
12544 | |
12545 | /* Free the minipool memory. */ | |
12546 | obstack_free (&minipool_obstack, minipool_startobj); | |
2b835d68 | 12547 | } |
cce8749e CH |
12548 | \f |
12549 | /* Routines to output assembly language. */ | |
12550 | ||
f3bb6135 | 12551 | /* If the rtx is the correct value then return the string of the number. |
ff9940b0 | 12552 | In this way we can ensure that valid double constants are generated even |
6354dc9b | 12553 | when cross compiling. */ |
cd2b33d0 | 12554 | const char * |
e32bac5b | 12555 | fp_immediate_constant (rtx x) |
ff9940b0 RE |
12556 | { |
12557 | REAL_VALUE_TYPE r; | |
12558 | int i; | |
f676971a | 12559 | |
9b66ebb1 PB |
12560 | if (!fp_consts_inited) |
12561 | init_fp_table (); | |
f676971a | 12562 | |
ff9940b0 RE |
12563 | REAL_VALUE_FROM_CONST_DOUBLE (r, x); |
12564 | for (i = 0; i < 8; i++) | |
9b66ebb1 PB |
12565 | if (REAL_VALUES_EQUAL (r, values_fp[i])) |
12566 | return strings_fp[i]; | |
f3bb6135 | 12567 | |
e6d29d15 | 12568 | gcc_unreachable (); |
ff9940b0 RE |
12569 | } |
12570 | ||
9997d19d | 12571 | /* As for fp_immediate_constant, but value is passed directly, not in rtx. */ |
cd2b33d0 | 12572 | static const char * |
e32bac5b | 12573 | fp_const_from_val (REAL_VALUE_TYPE *r) |
9997d19d RE |
12574 | { |
12575 | int i; | |
12576 | ||
9b66ebb1 PB |
12577 | if (!fp_consts_inited) |
12578 | init_fp_table (); | |
9997d19d RE |
12579 | |
12580 | for (i = 0; i < 8; i++) | |
9b66ebb1 PB |
12581 | if (REAL_VALUES_EQUAL (*r, values_fp[i])) |
12582 | return strings_fp[i]; | |
9997d19d | 12583 | |
e6d29d15 | 12584 | gcc_unreachable (); |
9997d19d | 12585 | } |
ff9940b0 | 12586 | |
cce8749e CH |
12587 | /* Output the operands of a LDM/STM instruction to STREAM. |
12588 | MASK is the ARM register set mask of which only bits 0-15 are important. | |
6d3d9133 | 12589 | REG is the base register, either the frame pointer or the stack pointer, |
a15908a4 PB |
12590 | INSTR is the possibly suffixed load or store instruction. |
12591 | RFE is nonzero if the instruction should also copy spsr to cpsr. */ | |
b279b20a | 12592 | |
d5b7b3ae | 12593 | static void |
b279b20a | 12594 | print_multi_reg (FILE *stream, const char *instr, unsigned reg, |
a15908a4 | 12595 | unsigned long mask, int rfe) |
cce8749e | 12596 | { |
b279b20a NC |
12597 | unsigned i; |
12598 | bool not_first = FALSE; | |
cce8749e | 12599 | |
a15908a4 | 12600 | gcc_assert (!rfe || (mask & (1 << PC_REGNUM))); |
1d5473cb | 12601 | fputc ('\t', stream); |
dd18ae56 | 12602 | asm_fprintf (stream, instr, reg); |
5b3e6663 | 12603 | fputc ('{', stream); |
f676971a | 12604 | |
d5b7b3ae | 12605 | for (i = 0; i <= LAST_ARM_REGNUM; i++) |
cce8749e CH |
12606 | if (mask & (1 << i)) |
12607 | { | |
12608 | if (not_first) | |
12609 | fprintf (stream, ", "); | |
f676971a | 12610 | |
dd18ae56 | 12611 | asm_fprintf (stream, "%r", i); |
cce8749e CH |
12612 | not_first = TRUE; |
12613 | } | |
f3bb6135 | 12614 | |
a15908a4 PB |
12615 | if (rfe) |
12616 | fprintf (stream, "}^\n"); | |
12617 | else | |
12618 | fprintf (stream, "}\n"); | |
f3bb6135 | 12619 | } |
cce8749e | 12620 | |
9b66ebb1 | 12621 | |
8edfc4cc | 12622 | /* Output a FLDMD instruction to STREAM. |
9728c9d1 PB |
12623 | BASE if the register containing the address. |
12624 | REG and COUNT specify the register range. | |
8edfc4cc MS |
12625 | Extra registers may be added to avoid hardware bugs. |
12626 | ||
12627 | We output FLDMD even for ARMv5 VFP implementations. Although | |
12628 | FLDMD is technically not supported until ARMv6, it is believed | |
12629 | that all VFP implementations support its use in this context. */ | |
9b66ebb1 PB |
12630 | |
12631 | static void | |
8edfc4cc | 12632 | vfp_output_fldmd (FILE * stream, unsigned int base, int reg, int count) |
9b66ebb1 PB |
12633 | { |
12634 | int i; | |
12635 | ||
9728c9d1 PB |
12636 | /* Workaround ARM10 VFPr1 bug. */ |
12637 | if (count == 2 && !arm_arch6) | |
12638 | { | |
12639 | if (reg == 15) | |
12640 | reg--; | |
12641 | count++; | |
12642 | } | |
12643 | ||
f1adb0a9 JB |
12644 | /* FLDMD may not load more than 16 doubleword registers at a time. Split the |
12645 | load into multiple parts if we have to handle more than 16 registers. */ | |
12646 | if (count > 16) | |
12647 | { | |
12648 | vfp_output_fldmd (stream, base, reg, 16); | |
12649 | vfp_output_fldmd (stream, base, reg + 16, count - 16); | |
12650 | return; | |
12651 | } | |
12652 | ||
9b66ebb1 | 12653 | fputc ('\t', stream); |
8edfc4cc | 12654 | asm_fprintf (stream, "fldmfdd\t%r!, {", base); |
9b66ebb1 | 12655 | |
9728c9d1 | 12656 | for (i = reg; i < reg + count; i++) |
9b66ebb1 | 12657 | { |
9728c9d1 | 12658 | if (i > reg) |
9b66ebb1 | 12659 | fputs (", ", stream); |
9728c9d1 | 12660 | asm_fprintf (stream, "d%d", i); |
9b66ebb1 PB |
12661 | } |
12662 | fputs ("}\n", stream); | |
9728c9d1 | 12663 | |
9b66ebb1 PB |
12664 | } |
12665 | ||
12666 | ||
12667 | /* Output the assembly for a store multiple. */ | |
12668 | ||
12669 | const char * | |
8edfc4cc | 12670 | vfp_output_fstmd (rtx * operands) |
9b66ebb1 PB |
12671 | { |
12672 | char pattern[100]; | |
12673 | int p; | |
12674 | int base; | |
12675 | int i; | |
12676 | ||
8edfc4cc | 12677 | strcpy (pattern, "fstmfdd\t%m0!, {%P1"); |
9b66ebb1 PB |
12678 | p = strlen (pattern); |
12679 | ||
e6d29d15 | 12680 | gcc_assert (GET_CODE (operands[1]) == REG); |
9b66ebb1 PB |
12681 | |
12682 | base = (REGNO (operands[1]) - FIRST_VFP_REGNUM) / 2; | |
12683 | for (i = 1; i < XVECLEN (operands[2], 0); i++) | |
12684 | { | |
12685 | p += sprintf (&pattern[p], ", d%d", base + i); | |
12686 | } | |
12687 | strcpy (&pattern[p], "}"); | |
12688 | ||
12689 | output_asm_insn (pattern, operands); | |
12690 | return ""; | |
12691 | } | |
12692 | ||
12693 | ||
9728c9d1 PB |
12694 | /* Emit RTL to save block of VFP register pairs to the stack. Returns the |
12695 | number of bytes pushed. */ | |
9b66ebb1 | 12696 | |
9728c9d1 | 12697 | static int |
8edfc4cc | 12698 | vfp_emit_fstmd (int base_reg, int count) |
9b66ebb1 PB |
12699 | { |
12700 | rtx par; | |
12701 | rtx dwarf; | |
12702 | rtx tmp, reg; | |
12703 | int i; | |
12704 | ||
9728c9d1 PB |
12705 | /* Workaround ARM10 VFPr1 bug. Data corruption can occur when exactly two |
12706 | register pairs are stored by a store multiple insn. We avoid this | |
12707 | by pushing an extra pair. */ | |
12708 | if (count == 2 && !arm_arch6) | |
12709 | { | |
12710 | if (base_reg == LAST_VFP_REGNUM - 3) | |
12711 | base_reg -= 2; | |
12712 | count++; | |
12713 | } | |
12714 | ||
f1adb0a9 JB |
12715 | /* FSTMD may not store more than 16 doubleword registers at once. Split |
12716 | larger stores into multiple parts (up to a maximum of two, in | |
12717 | practice). */ | |
12718 | if (count > 16) | |
12719 | { | |
12720 | int saved; | |
12721 | /* NOTE: base_reg is an internal register number, so each D register | |
12722 | counts as 2. */ | |
12723 | saved = vfp_emit_fstmd (base_reg + 32, count - 16); | |
12724 | saved += vfp_emit_fstmd (base_reg, 16); | |
12725 | return saved; | |
12726 | } | |
12727 | ||
9b66ebb1 PB |
12728 | par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); |
12729 | dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (count + 1)); | |
12730 | ||
12731 | reg = gen_rtx_REG (DFmode, base_reg); | |
12732 | base_reg += 2; | |
12733 | ||
12734 | XVECEXP (par, 0, 0) | |
12735 | = gen_rtx_SET (VOIDmode, | |
9abf5d7b RR |
12736 | gen_frame_mem |
12737 | (BLKmode, | |
12738 | gen_rtx_PRE_MODIFY (Pmode, | |
12739 | stack_pointer_rtx, | |
12740 | plus_constant | |
12741 | (stack_pointer_rtx, | |
12742 | - (count * 8))) | |
12743 | ), | |
9b66ebb1 PB |
12744 | gen_rtx_UNSPEC (BLKmode, |
12745 | gen_rtvec (1, reg), | |
12746 | UNSPEC_PUSH_MULT)); | |
12747 | ||
12748 | tmp = gen_rtx_SET (VOIDmode, stack_pointer_rtx, | |
8edfc4cc | 12749 | plus_constant (stack_pointer_rtx, -(count * 8))); |
9b66ebb1 PB |
12750 | RTX_FRAME_RELATED_P (tmp) = 1; |
12751 | XVECEXP (dwarf, 0, 0) = tmp; | |
12752 | ||
12753 | tmp = gen_rtx_SET (VOIDmode, | |
31fa16b6 | 12754 | gen_frame_mem (DFmode, stack_pointer_rtx), |
9b66ebb1 PB |
12755 | reg); |
12756 | RTX_FRAME_RELATED_P (tmp) = 1; | |
12757 | XVECEXP (dwarf, 0, 1) = tmp; | |
12758 | ||
12759 | for (i = 1; i < count; i++) | |
12760 | { | |
12761 | reg = gen_rtx_REG (DFmode, base_reg); | |
12762 | base_reg += 2; | |
12763 | XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode, reg); | |
12764 | ||
12765 | tmp = gen_rtx_SET (VOIDmode, | |
31fa16b6 | 12766 | gen_frame_mem (DFmode, |
d66437c5 RE |
12767 | plus_constant (stack_pointer_rtx, |
12768 | i * 8)), | |
9b66ebb1 PB |
12769 | reg); |
12770 | RTX_FRAME_RELATED_P (tmp) = 1; | |
12771 | XVECEXP (dwarf, 0, i + 1) = tmp; | |
12772 | } | |
12773 | ||
12774 | par = emit_insn (par); | |
bbbbb16a | 12775 | add_reg_note (par, REG_FRAME_RELATED_EXPR, dwarf); |
9728c9d1 PB |
12776 | RTX_FRAME_RELATED_P (par) = 1; |
12777 | ||
8edfc4cc | 12778 | return count * 8; |
9b66ebb1 PB |
12779 | } |
12780 | ||
9403b7f7 RS |
12781 | /* Emit a call instruction with pattern PAT. ADDR is the address of |
12782 | the call target. */ | |
12783 | ||
12784 | void | |
12785 | arm_emit_call_insn (rtx pat, rtx addr) | |
12786 | { | |
12787 | rtx insn; | |
12788 | ||
12789 | insn = emit_call_insn (pat); | |
12790 | ||
12791 | /* The PIC register is live on entry to VxWorks PIC PLT entries. | |
12792 | If the call might use such an entry, add a use of the PIC register | |
12793 | to the instruction's CALL_INSN_FUNCTION_USAGE. */ | |
12794 | if (TARGET_VXWORKS_RTP | |
12795 | && flag_pic | |
12796 | && GET_CODE (addr) == SYMBOL_REF | |
12797 | && (SYMBOL_REF_DECL (addr) | |
12798 | ? !targetm.binds_local_p (SYMBOL_REF_DECL (addr)) | |
12799 | : !SYMBOL_REF_LOCAL_P (addr))) | |
12800 | { | |
12801 | require_pic_register (); | |
12802 | use_reg (&CALL_INSN_FUNCTION_USAGE (insn), cfun->machine->pic_reg); | |
12803 | } | |
12804 | } | |
9b66ebb1 | 12805 | |
6354dc9b | 12806 | /* Output a 'call' insn. */ |
cd2b33d0 | 12807 | const char * |
e32bac5b | 12808 | output_call (rtx *operands) |
cce8749e | 12809 | { |
e6d29d15 | 12810 | gcc_assert (!arm_arch5); /* Patterns should call blx <reg> directly. */ |
cce8749e | 12811 | |
68d560d4 | 12812 | /* Handle calls to lr using ip (which may be clobbered in subr anyway). */ |
62b10bbc | 12813 | if (REGNO (operands[0]) == LR_REGNUM) |
cce8749e | 12814 | { |
62b10bbc | 12815 | operands[0] = gen_rtx_REG (SImode, IP_REGNUM); |
1d5473cb | 12816 | output_asm_insn ("mov%?\t%0, %|lr", operands); |
cce8749e | 12817 | } |
f676971a | 12818 | |
1d5473cb | 12819 | output_asm_insn ("mov%?\t%|lr, %|pc", operands); |
f676971a | 12820 | |
68d560d4 | 12821 | if (TARGET_INTERWORK || arm_arch4t) |
da6558fd NC |
12822 | output_asm_insn ("bx%?\t%0", operands); |
12823 | else | |
12824 | output_asm_insn ("mov%?\t%|pc, %0", operands); | |
f676971a | 12825 | |
f3bb6135 RE |
12826 | return ""; |
12827 | } | |
cce8749e | 12828 | |
0986ef45 JB |
12829 | /* Output a 'call' insn that is a reference in memory. This is |
12830 | disabled for ARMv5 and we prefer a blx instead because otherwise | |
12831 | there's a significant performance overhead. */ | |
cd2b33d0 | 12832 | const char * |
e32bac5b | 12833 | output_call_mem (rtx *operands) |
ff9940b0 | 12834 | { |
0986ef45 JB |
12835 | gcc_assert (!arm_arch5); |
12836 | if (TARGET_INTERWORK) | |
da6558fd NC |
12837 | { |
12838 | output_asm_insn ("ldr%?\t%|ip, %0", operands); | |
12839 | output_asm_insn ("mov%?\t%|lr, %|pc", operands); | |
12840 | output_asm_insn ("bx%?\t%|ip", operands); | |
12841 | } | |
6ab5da80 RE |
12842 | else if (regno_use_in (LR_REGNUM, operands[0])) |
12843 | { | |
12844 | /* LR is used in the memory address. We load the address in the | |
12845 | first instruction. It's safe to use IP as the target of the | |
12846 | load since the call will kill it anyway. */ | |
12847 | output_asm_insn ("ldr%?\t%|ip, %0", operands); | |
0986ef45 JB |
12848 | output_asm_insn ("mov%?\t%|lr, %|pc", operands); |
12849 | if (arm_arch4t) | |
12850 | output_asm_insn ("bx%?\t%|ip", operands); | |
68d560d4 | 12851 | else |
0986ef45 | 12852 | output_asm_insn ("mov%?\t%|pc, %|ip", operands); |
6ab5da80 | 12853 | } |
da6558fd NC |
12854 | else |
12855 | { | |
12856 | output_asm_insn ("mov%?\t%|lr, %|pc", operands); | |
12857 | output_asm_insn ("ldr%?\t%|pc, %0", operands); | |
12858 | } | |
12859 | ||
f3bb6135 RE |
12860 | return ""; |
12861 | } | |
ff9940b0 RE |
12862 | |
12863 | ||
3b684012 RE |
12864 | /* Output a move from arm registers to an fpa registers. |
12865 | OPERANDS[0] is an fpa register. | |
ff9940b0 | 12866 | OPERANDS[1] is the first registers of an arm register pair. */ |
cd2b33d0 | 12867 | const char * |
e32bac5b | 12868 | output_mov_long_double_fpa_from_arm (rtx *operands) |
ff9940b0 RE |
12869 | { |
12870 | int arm_reg0 = REGNO (operands[1]); | |
12871 | rtx ops[3]; | |
12872 | ||
e6d29d15 | 12873 | gcc_assert (arm_reg0 != IP_REGNUM); |
f3bb6135 | 12874 | |
43cffd11 RE |
12875 | ops[0] = gen_rtx_REG (SImode, arm_reg0); |
12876 | ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0); | |
12877 | ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0); | |
f676971a | 12878 | |
5b3e6663 | 12879 | output_asm_insn ("stm%(fd%)\t%|sp!, {%0, %1, %2}", ops); |
1d5473cb | 12880 | output_asm_insn ("ldf%?e\t%0, [%|sp], #12", operands); |
f676971a | 12881 | |
f3bb6135 RE |
12882 | return ""; |
12883 | } | |
ff9940b0 | 12884 | |
3b684012 | 12885 | /* Output a move from an fpa register to arm registers. |
ff9940b0 | 12886 | OPERANDS[0] is the first registers of an arm register pair. |
3b684012 | 12887 | OPERANDS[1] is an fpa register. */ |
cd2b33d0 | 12888 | const char * |
e32bac5b | 12889 | output_mov_long_double_arm_from_fpa (rtx *operands) |
ff9940b0 RE |
12890 | { |
12891 | int arm_reg0 = REGNO (operands[0]); | |
12892 | rtx ops[3]; | |
12893 | ||
e6d29d15 | 12894 | gcc_assert (arm_reg0 != IP_REGNUM); |
f3bb6135 | 12895 | |
43cffd11 RE |
12896 | ops[0] = gen_rtx_REG (SImode, arm_reg0); |
12897 | ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0); | |
12898 | ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0); | |
ff9940b0 | 12899 | |
1d5473cb | 12900 | output_asm_insn ("stf%?e\t%1, [%|sp, #-12]!", operands); |
5b3e6663 | 12901 | output_asm_insn ("ldm%(fd%)\t%|sp!, {%0, %1, %2}", ops); |
f3bb6135 RE |
12902 | return ""; |
12903 | } | |
ff9940b0 RE |
12904 | |
12905 | /* Output a move from arm registers to arm registers of a long double | |
12906 | OPERANDS[0] is the destination. | |
12907 | OPERANDS[1] is the source. */ | |
cd2b33d0 | 12908 | const char * |
e32bac5b | 12909 | output_mov_long_double_arm_from_arm (rtx *operands) |
ff9940b0 | 12910 | { |
6354dc9b | 12911 | /* We have to be careful here because the two might overlap. */ |
ff9940b0 RE |
12912 | int dest_start = REGNO (operands[0]); |
12913 | int src_start = REGNO (operands[1]); | |
12914 | rtx ops[2]; | |
12915 | int i; | |
12916 | ||
12917 | if (dest_start < src_start) | |
12918 | { | |
12919 | for (i = 0; i < 3; i++) | |
12920 | { | |
43cffd11 RE |
12921 | ops[0] = gen_rtx_REG (SImode, dest_start + i); |
12922 | ops[1] = gen_rtx_REG (SImode, src_start + i); | |
9997d19d | 12923 | output_asm_insn ("mov%?\t%0, %1", ops); |
ff9940b0 RE |
12924 | } |
12925 | } | |
12926 | else | |
12927 | { | |
12928 | for (i = 2; i >= 0; i--) | |
12929 | { | |
43cffd11 RE |
12930 | ops[0] = gen_rtx_REG (SImode, dest_start + i); |
12931 | ops[1] = gen_rtx_REG (SImode, src_start + i); | |
9997d19d | 12932 | output_asm_insn ("mov%?\t%0, %1", ops); |
ff9940b0 RE |
12933 | } |
12934 | } | |
f3bb6135 | 12935 | |
ff9940b0 RE |
12936 | return ""; |
12937 | } | |
12938 | ||
a552b644 RR |
12939 | void |
12940 | arm_emit_movpair (rtx dest, rtx src) | |
12941 | { | |
12942 | /* If the src is an immediate, simplify it. */ | |
12943 | if (CONST_INT_P (src)) | |
12944 | { | |
12945 | HOST_WIDE_INT val = INTVAL (src); | |
12946 | emit_set_insn (dest, GEN_INT (val & 0x0000ffff)); | |
12947 | if ((val >> 16) & 0x0000ffff) | |
12948 | emit_set_insn (gen_rtx_ZERO_EXTRACT (SImode, dest, GEN_INT (16), | |
12949 | GEN_INT (16)), | |
12950 | GEN_INT ((val >> 16) & 0x0000ffff)); | |
12951 | return; | |
12952 | } | |
12953 | emit_set_insn (dest, gen_rtx_HIGH (SImode, src)); | |
12954 | emit_set_insn (dest, gen_rtx_LO_SUM (SImode, dest, src)); | |
12955 | } | |
571191af | 12956 | |
3b684012 RE |
12957 | /* Output a move from arm registers to an fpa registers. |
12958 | OPERANDS[0] is an fpa register. | |
cce8749e | 12959 | OPERANDS[1] is the first registers of an arm register pair. */ |
cd2b33d0 | 12960 | const char * |
e32bac5b | 12961 | output_mov_double_fpa_from_arm (rtx *operands) |
cce8749e CH |
12962 | { |
12963 | int arm_reg0 = REGNO (operands[1]); | |
12964 | rtx ops[2]; | |
12965 | ||
e6d29d15 | 12966 | gcc_assert (arm_reg0 != IP_REGNUM); |
f676971a | 12967 | |
43cffd11 RE |
12968 | ops[0] = gen_rtx_REG (SImode, arm_reg0); |
12969 | ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0); | |
5b3e6663 | 12970 | output_asm_insn ("stm%(fd%)\t%|sp!, {%0, %1}", ops); |
1d5473cb | 12971 | output_asm_insn ("ldf%?d\t%0, [%|sp], #8", operands); |
f3bb6135 RE |
12972 | return ""; |
12973 | } | |
cce8749e | 12974 | |
3b684012 | 12975 | /* Output a move from an fpa register to arm registers. |
cce8749e | 12976 | OPERANDS[0] is the first registers of an arm register pair. |
3b684012 | 12977 | OPERANDS[1] is an fpa register. */ |
cd2b33d0 | 12978 | const char * |
e32bac5b | 12979 | output_mov_double_arm_from_fpa (rtx *operands) |
cce8749e CH |
12980 | { |
12981 | int arm_reg0 = REGNO (operands[0]); | |
12982 | rtx ops[2]; | |
12983 | ||
e6d29d15 | 12984 | gcc_assert (arm_reg0 != IP_REGNUM); |
f3bb6135 | 12985 | |
43cffd11 RE |
12986 | ops[0] = gen_rtx_REG (SImode, arm_reg0); |
12987 | ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0); | |
1d5473cb | 12988 | output_asm_insn ("stf%?d\t%1, [%|sp, #-8]!", operands); |
5b3e6663 | 12989 | output_asm_insn ("ldm%(fd%)\t%|sp!, {%0, %1}", ops); |
f3bb6135 RE |
12990 | return ""; |
12991 | } | |
cce8749e | 12992 | |
16a9afdc JZ |
12993 | /* Output a move between double words. It must be REG<-MEM |
12994 | or MEM<-REG. */ | |
cd2b33d0 | 12995 | const char * |
e32bac5b | 12996 | output_move_double (rtx *operands) |
cce8749e CH |
12997 | { |
12998 | enum rtx_code code0 = GET_CODE (operands[0]); | |
12999 | enum rtx_code code1 = GET_CODE (operands[1]); | |
56636818 | 13000 | rtx otherops[3]; |
cce8749e CH |
13001 | |
13002 | if (code0 == REG) | |
13003 | { | |
f0b4bdd5 | 13004 | unsigned int reg0 = REGNO (operands[0]); |
cce8749e | 13005 | |
43cffd11 | 13006 | otherops[0] = gen_rtx_REG (SImode, 1 + reg0); |
f676971a | 13007 | |
e6d29d15 NS |
13008 | gcc_assert (code1 == MEM); /* Constraints should ensure this. */ |
13009 | ||
13010 | switch (GET_CODE (XEXP (operands[1], 0))) | |
cce8749e | 13011 | { |
e6d29d15 | 13012 | case REG: |
5fd42423 PB |
13013 | if (TARGET_LDRD |
13014 | && !(fix_cm3_ldrd && reg0 == REGNO(XEXP (operands[1], 0)))) | |
5dea0c19 PB |
13015 | output_asm_insn ("ldr%(d%)\t%0, [%m1]", operands); |
13016 | else | |
13017 | output_asm_insn ("ldm%(ia%)\t%m1, %M0", operands); | |
e6d29d15 | 13018 | break; |
e0b92319 | 13019 | |
e6d29d15 NS |
13020 | case PRE_INC: |
13021 | gcc_assert (TARGET_LDRD); | |
5b3e6663 | 13022 | output_asm_insn ("ldr%(d%)\t%0, [%m1, #8]!", operands); |
e6d29d15 | 13023 | break; |
e0b92319 | 13024 | |
e6d29d15 | 13025 | case PRE_DEC: |
5b3e6663 PB |
13026 | if (TARGET_LDRD) |
13027 | output_asm_insn ("ldr%(d%)\t%0, [%m1, #-8]!", operands); | |
13028 | else | |
13029 | output_asm_insn ("ldm%(db%)\t%m1!, %M0", operands); | |
e6d29d15 | 13030 | break; |
e0b92319 | 13031 | |
e6d29d15 | 13032 | case POST_INC: |
5dea0c19 PB |
13033 | if (TARGET_LDRD) |
13034 | output_asm_insn ("ldr%(d%)\t%0, [%m1], #8", operands); | |
13035 | else | |
13036 | output_asm_insn ("ldm%(ia%)\t%m1!, %M0", operands); | |
e6d29d15 | 13037 | break; |
e0b92319 | 13038 | |
e6d29d15 NS |
13039 | case POST_DEC: |
13040 | gcc_assert (TARGET_LDRD); | |
5b3e6663 | 13041 | output_asm_insn ("ldr%(d%)\t%0, [%m1], #-8", operands); |
e6d29d15 | 13042 | break; |
e0b92319 | 13043 | |
e6d29d15 NS |
13044 | case PRE_MODIFY: |
13045 | case POST_MODIFY: | |
5fd42423 PB |
13046 | /* Autoicrement addressing modes should never have overlapping |
13047 | base and destination registers, and overlapping index registers | |
13048 | are already prohibited, so this doesn't need to worry about | |
13049 | fix_cm3_ldrd. */ | |
e6d29d15 NS |
13050 | otherops[0] = operands[0]; |
13051 | otherops[1] = XEXP (XEXP (XEXP (operands[1], 0), 1), 0); | |
13052 | otherops[2] = XEXP (XEXP (XEXP (operands[1], 0), 1), 1); | |
e0b92319 | 13053 | |
e6d29d15 | 13054 | if (GET_CODE (XEXP (operands[1], 0)) == PRE_MODIFY) |
cce8749e | 13055 | { |
e6d29d15 | 13056 | if (reg_overlap_mentioned_p (otherops[0], otherops[2])) |
fdd695fd | 13057 | { |
e6d29d15 NS |
13058 | /* Registers overlap so split out the increment. */ |
13059 | output_asm_insn ("add%?\t%1, %1, %2", otherops); | |
5b3e6663 | 13060 | output_asm_insn ("ldr%(d%)\t%0, [%1] @split", otherops); |
fdd695fd PB |
13061 | } |
13062 | else | |
fe2d934b | 13063 | { |
ff128632 RE |
13064 | /* Use a single insn if we can. |
13065 | FIXME: IWMMXT allows offsets larger than ldrd can | |
13066 | handle, fix these up with a pair of ldr. */ | |
13067 | if (TARGET_THUMB2 | |
13068 | || GET_CODE (otherops[2]) != CONST_INT | |
13069 | || (INTVAL (otherops[2]) > -256 | |
13070 | && INTVAL (otherops[2]) < 256)) | |
13071 | output_asm_insn ("ldr%(d%)\t%0, [%1, %2]!", otherops); | |
13072 | else | |
fe2d934b PB |
13073 | { |
13074 | output_asm_insn ("ldr%?\t%0, [%1, %2]!", otherops); | |
ff128632 | 13075 | output_asm_insn ("ldr%?\t%H0, [%1, #4]", otherops); |
fe2d934b | 13076 | } |
fe2d934b | 13077 | } |
e6d29d15 NS |
13078 | } |
13079 | else | |
13080 | { | |
ff128632 RE |
13081 | /* Use a single insn if we can. |
13082 | FIXME: IWMMXT allows offsets larger than ldrd can handle, | |
fe2d934b | 13083 | fix these up with a pair of ldr. */ |
ff128632 RE |
13084 | if (TARGET_THUMB2 |
13085 | || GET_CODE (otherops[2]) != CONST_INT | |
13086 | || (INTVAL (otherops[2]) > -256 | |
13087 | && INTVAL (otherops[2]) < 256)) | |
13088 | output_asm_insn ("ldr%(d%)\t%0, [%1], %2", otherops); | |
13089 | else | |
fe2d934b | 13090 | { |
ff128632 | 13091 | output_asm_insn ("ldr%?\t%H0, [%1, #4]", otherops); |
fe2d934b PB |
13092 | output_asm_insn ("ldr%?\t%0, [%1], %2", otherops); |
13093 | } | |
e6d29d15 NS |
13094 | } |
13095 | break; | |
e0b92319 | 13096 | |
e6d29d15 NS |
13097 | case LABEL_REF: |
13098 | case CONST: | |
5dea0c19 PB |
13099 | /* We might be able to use ldrd %0, %1 here. However the range is |
13100 | different to ldr/adr, and it is broken on some ARMv7-M | |
13101 | implementations. */ | |
5fd42423 PB |
13102 | /* Use the second register of the pair to avoid problematic |
13103 | overlap. */ | |
13104 | otherops[1] = operands[1]; | |
13105 | output_asm_insn ("adr%?\t%0, %1", otherops); | |
13106 | operands[1] = otherops[0]; | |
5dea0c19 | 13107 | if (TARGET_LDRD) |
5fd42423 | 13108 | output_asm_insn ("ldr%(d%)\t%0, [%1]", operands); |
5dea0c19 | 13109 | else |
5fd42423 | 13110 | output_asm_insn ("ldm%(ia%)\t%1, %M0", operands); |
e6d29d15 | 13111 | break; |
e0b92319 | 13112 | |
5b3e6663 | 13113 | /* ??? This needs checking for thumb2. */ |
e6d29d15 NS |
13114 | default: |
13115 | if (arm_add_operand (XEXP (XEXP (operands[1], 0), 1), | |
13116 | GET_MODE (XEXP (XEXP (operands[1], 0), 1)))) | |
13117 | { | |
13118 | otherops[0] = operands[0]; | |
13119 | otherops[1] = XEXP (XEXP (operands[1], 0), 0); | |
13120 | otherops[2] = XEXP (XEXP (operands[1], 0), 1); | |
e0b92319 | 13121 | |
e6d29d15 | 13122 | if (GET_CODE (XEXP (operands[1], 0)) == PLUS) |
fdd695fd | 13123 | { |
5dea0c19 | 13124 | if (GET_CODE (otherops[2]) == CONST_INT && !TARGET_LDRD) |
2b835d68 | 13125 | { |
e6d29d15 | 13126 | switch ((int) INTVAL (otherops[2])) |
2b835d68 | 13127 | { |
e6d29d15 | 13128 | case -8: |
5b3e6663 | 13129 | output_asm_insn ("ldm%(db%)\t%1, %M0", otherops); |
e6d29d15 NS |
13130 | return ""; |
13131 | case -4: | |
5b3e6663 PB |
13132 | if (TARGET_THUMB2) |
13133 | break; | |
13134 | output_asm_insn ("ldm%(da%)\t%1, %M0", otherops); | |
e6d29d15 NS |
13135 | return ""; |
13136 | case 4: | |
5b3e6663 PB |
13137 | if (TARGET_THUMB2) |
13138 | break; | |
13139 | output_asm_insn ("ldm%(ib%)\t%1, %M0", otherops); | |
e6d29d15 | 13140 | return ""; |
fdd695fd | 13141 | } |
e6d29d15 | 13142 | } |
5fd42423 PB |
13143 | otherops[0] = gen_rtx_REG(SImode, REGNO(operands[0]) + 1); |
13144 | operands[1] = otherops[0]; | |
e6d29d15 NS |
13145 | if (TARGET_LDRD |
13146 | && (GET_CODE (otherops[2]) == REG | |
ff128632 | 13147 | || TARGET_THUMB2 |
e6d29d15 NS |
13148 | || (GET_CODE (otherops[2]) == CONST_INT |
13149 | && INTVAL (otherops[2]) > -256 | |
13150 | && INTVAL (otherops[2]) < 256))) | |
13151 | { | |
5fd42423 | 13152 | if (reg_overlap_mentioned_p (operands[0], |
e6d29d15 | 13153 | otherops[2])) |
fdd695fd | 13154 | { |
5fd42423 | 13155 | rtx tmp; |
e6d29d15 NS |
13156 | /* Swap base and index registers over to |
13157 | avoid a conflict. */ | |
5fd42423 PB |
13158 | tmp = otherops[1]; |
13159 | otherops[1] = otherops[2]; | |
13160 | otherops[2] = tmp; | |
fdd695fd | 13161 | } |
e6d29d15 NS |
13162 | /* If both registers conflict, it will usually |
13163 | have been fixed by a splitter. */ | |
5fd42423 PB |
13164 | if (reg_overlap_mentioned_p (operands[0], otherops[2]) |
13165 | || (fix_cm3_ldrd && reg0 == REGNO (otherops[1]))) | |
fdd695fd | 13166 | { |
5fd42423 PB |
13167 | output_asm_insn ("add%?\t%0, %1, %2", otherops); |
13168 | output_asm_insn ("ldr%(d%)\t%0, [%1]", operands); | |
2b835d68 RE |
13169 | } |
13170 | else | |
5fd42423 PB |
13171 | { |
13172 | otherops[0] = operands[0]; | |
13173 | output_asm_insn ("ldr%(d%)\t%0, [%1, %2]", otherops); | |
13174 | } | |
e6d29d15 | 13175 | return ""; |
2b835d68 | 13176 | } |
e0b92319 | 13177 | |
e6d29d15 | 13178 | if (GET_CODE (otherops[2]) == CONST_INT) |
2b835d68 | 13179 | { |
e6d29d15 NS |
13180 | if (!(const_ok_for_arm (INTVAL (otherops[2])))) |
13181 | output_asm_insn ("sub%?\t%0, %1, #%n2", otherops); | |
13182 | else | |
13183 | output_asm_insn ("add%?\t%0, %1, %2", otherops); | |
2b835d68 RE |
13184 | } |
13185 | else | |
e6d29d15 NS |
13186 | output_asm_insn ("add%?\t%0, %1, %2", otherops); |
13187 | } | |
13188 | else | |
13189 | output_asm_insn ("sub%?\t%0, %1, %2", otherops); | |
13190 | ||
5dea0c19 | 13191 | if (TARGET_LDRD) |
5fd42423 | 13192 | return "ldr%(d%)\t%0, [%1]"; |
5dea0c19 | 13193 | |
5fd42423 | 13194 | return "ldm%(ia%)\t%1, %M0"; |
e6d29d15 NS |
13195 | } |
13196 | else | |
13197 | { | |
13198 | otherops[1] = adjust_address (operands[1], SImode, 4); | |
13199 | /* Take care of overlapping base/data reg. */ | |
13200 | if (reg_mentioned_p (operands[0], operands[1])) | |
13201 | { | |
13202 | output_asm_insn ("ldr%?\t%0, %1", otherops); | |
13203 | output_asm_insn ("ldr%?\t%0, %1", operands); | |
13204 | } | |
13205 | else | |
13206 | { | |
13207 | output_asm_insn ("ldr%?\t%0, %1", operands); | |
13208 | output_asm_insn ("ldr%?\t%0, %1", otherops); | |
cce8749e CH |
13209 | } |
13210 | } | |
13211 | } | |
cce8749e | 13212 | } |
e6d29d15 | 13213 | else |
cce8749e | 13214 | { |
e6d29d15 NS |
13215 | /* Constraints should ensure this. */ |
13216 | gcc_assert (code0 == MEM && code1 == REG); | |
13217 | gcc_assert (REGNO (operands[1]) != IP_REGNUM); | |
2b835d68 | 13218 | |
ff9940b0 RE |
13219 | switch (GET_CODE (XEXP (operands[0], 0))) |
13220 | { | |
13221 | case REG: | |
5dea0c19 PB |
13222 | if (TARGET_LDRD) |
13223 | output_asm_insn ("str%(d%)\t%1, [%m0]", operands); | |
13224 | else | |
13225 | output_asm_insn ("stm%(ia%)\t%m0, %M1", operands); | |
ff9940b0 | 13226 | break; |
2b835d68 | 13227 | |
ff9940b0 | 13228 | case PRE_INC: |
e6d29d15 | 13229 | gcc_assert (TARGET_LDRD); |
5b3e6663 | 13230 | output_asm_insn ("str%(d%)\t%1, [%m0, #8]!", operands); |
ff9940b0 | 13231 | break; |
2b835d68 | 13232 | |
ff9940b0 | 13233 | case PRE_DEC: |
5b3e6663 PB |
13234 | if (TARGET_LDRD) |
13235 | output_asm_insn ("str%(d%)\t%1, [%m0, #-8]!", operands); | |
13236 | else | |
13237 | output_asm_insn ("stm%(db%)\t%m0!, %M1", operands); | |
ff9940b0 | 13238 | break; |
2b835d68 | 13239 | |
ff9940b0 | 13240 | case POST_INC: |
5dea0c19 PB |
13241 | if (TARGET_LDRD) |
13242 | output_asm_insn ("str%(d%)\t%1, [%m0], #8", operands); | |
13243 | else | |
13244 | output_asm_insn ("stm%(ia%)\t%m0!, %M1", operands); | |
ff9940b0 | 13245 | break; |
2b835d68 | 13246 | |
ff9940b0 | 13247 | case POST_DEC: |
e6d29d15 | 13248 | gcc_assert (TARGET_LDRD); |
5b3e6663 | 13249 | output_asm_insn ("str%(d%)\t%1, [%m0], #-8", operands); |
fdd695fd PB |
13250 | break; |
13251 | ||
13252 | case PRE_MODIFY: | |
13253 | case POST_MODIFY: | |
13254 | otherops[0] = operands[1]; | |
13255 | otherops[1] = XEXP (XEXP (XEXP (operands[0], 0), 1), 0); | |
13256 | otherops[2] = XEXP (XEXP (XEXP (operands[0], 0), 1), 1); | |
13257 | ||
fe2d934b PB |
13258 | /* IWMMXT allows offsets larger than ldrd can handle, |
13259 | fix these up with a pair of ldr. */ | |
ff128632 RE |
13260 | if (!TARGET_THUMB2 |
13261 | && GET_CODE (otherops[2]) == CONST_INT | |
fe2d934b PB |
13262 | && (INTVAL(otherops[2]) <= -256 |
13263 | || INTVAL(otherops[2]) >= 256)) | |
13264 | { | |
fe2d934b PB |
13265 | if (GET_CODE (XEXP (operands[0], 0)) == PRE_MODIFY) |
13266 | { | |
8019fcfb YQ |
13267 | output_asm_insn ("str%?\t%0, [%1, %2]!", otherops); |
13268 | output_asm_insn ("str%?\t%H0, [%1, #4]", otherops); | |
fe2d934b PB |
13269 | } |
13270 | else | |
13271 | { | |
8019fcfb YQ |
13272 | output_asm_insn ("str%?\t%H0, [%1, #4]", otherops); |
13273 | output_asm_insn ("str%?\t%0, [%1], %2", otherops); | |
fe2d934b PB |
13274 | } |
13275 | } | |
13276 | else if (GET_CODE (XEXP (operands[0], 0)) == PRE_MODIFY) | |
5b3e6663 | 13277 | output_asm_insn ("str%(d%)\t%0, [%1, %2]!", otherops); |
fdd695fd | 13278 | else |
5b3e6663 | 13279 | output_asm_insn ("str%(d%)\t%0, [%1], %2", otherops); |
ff9940b0 | 13280 | break; |
2b835d68 RE |
13281 | |
13282 | case PLUS: | |
fdd695fd | 13283 | otherops[2] = XEXP (XEXP (operands[0], 0), 1); |
5dea0c19 | 13284 | if (GET_CODE (otherops[2]) == CONST_INT && !TARGET_LDRD) |
2b835d68 | 13285 | { |
06bea5aa | 13286 | switch ((int) INTVAL (XEXP (XEXP (operands[0], 0), 1))) |
2b835d68 RE |
13287 | { |
13288 | case -8: | |
5b3e6663 | 13289 | output_asm_insn ("stm%(db%)\t%m0, %M1", operands); |
2b835d68 RE |
13290 | return ""; |
13291 | ||
13292 | case -4: | |
5b3e6663 PB |
13293 | if (TARGET_THUMB2) |
13294 | break; | |
13295 | output_asm_insn ("stm%(da%)\t%m0, %M1", operands); | |
2b835d68 RE |
13296 | return ""; |
13297 | ||
13298 | case 4: | |
5b3e6663 PB |
13299 | if (TARGET_THUMB2) |
13300 | break; | |
13301 | output_asm_insn ("stm%(ib%)\t%m0, %M1", operands); | |
2b835d68 RE |
13302 | return ""; |
13303 | } | |
13304 | } | |
fdd695fd PB |
13305 | if (TARGET_LDRD |
13306 | && (GET_CODE (otherops[2]) == REG | |
ff128632 | 13307 | || TARGET_THUMB2 |
fdd695fd PB |
13308 | || (GET_CODE (otherops[2]) == CONST_INT |
13309 | && INTVAL (otherops[2]) > -256 | |
13310 | && INTVAL (otherops[2]) < 256))) | |
13311 | { | |
13312 | otherops[0] = operands[1]; | |
13313 | otherops[1] = XEXP (XEXP (operands[0], 0), 0); | |
5b3e6663 | 13314 | output_asm_insn ("str%(d%)\t%0, [%1, %2]", otherops); |
fdd695fd PB |
13315 | return ""; |
13316 | } | |
2b835d68 RE |
13317 | /* Fall through */ |
13318 | ||
ff9940b0 | 13319 | default: |
a4a37b30 | 13320 | otherops[0] = adjust_address (operands[0], SImode, 4); |
ff128632 | 13321 | otherops[1] = operands[1]; |
9997d19d | 13322 | output_asm_insn ("str%?\t%1, %0", operands); |
ff128632 | 13323 | output_asm_insn ("str%?\t%H1, %0", otherops); |
cce8749e CH |
13324 | } |
13325 | } | |
cce8749e | 13326 | |
9997d19d RE |
13327 | return ""; |
13328 | } | |
cce8749e | 13329 | |
88f77cba | 13330 | /* Output a move, load or store for quad-word vectors in ARM registers. Only |
dc34db56 | 13331 | handles MEMs accepted by neon_vector_mem_operand with TYPE=1. */ |
5b3e6663 PB |
13332 | |
13333 | const char * | |
88f77cba | 13334 | output_move_quad (rtx *operands) |
5b3e6663 | 13335 | { |
88f77cba JB |
13336 | if (REG_P (operands[0])) |
13337 | { | |
13338 | /* Load, or reg->reg move. */ | |
5b3e6663 | 13339 | |
88f77cba JB |
13340 | if (MEM_P (operands[1])) |
13341 | { | |
13342 | switch (GET_CODE (XEXP (operands[1], 0))) | |
13343 | { | |
13344 | case REG: | |
13345 | output_asm_insn ("ldm%(ia%)\t%m1, %M0", operands); | |
13346 | break; | |
13347 | ||
13348 | case LABEL_REF: | |
13349 | case CONST: | |
13350 | output_asm_insn ("adr%?\t%0, %1", operands); | |
13351 | output_asm_insn ("ldm%(ia%)\t%0, %M0", operands); | |
13352 | break; | |
13353 | ||
13354 | default: | |
13355 | gcc_unreachable (); | |
13356 | } | |
13357 | } | |
13358 | else | |
13359 | { | |
13360 | rtx ops[2]; | |
13361 | int dest, src, i; | |
5b3e6663 | 13362 | |
88f77cba | 13363 | gcc_assert (REG_P (operands[1])); |
5b3e6663 | 13364 | |
88f77cba JB |
13365 | dest = REGNO (operands[0]); |
13366 | src = REGNO (operands[1]); | |
5b3e6663 | 13367 | |
88f77cba JB |
13368 | /* This seems pretty dumb, but hopefully GCC won't try to do it |
13369 | very often. */ | |
13370 | if (dest < src) | |
13371 | for (i = 0; i < 4; i++) | |
13372 | { | |
13373 | ops[0] = gen_rtx_REG (SImode, dest + i); | |
13374 | ops[1] = gen_rtx_REG (SImode, src + i); | |
13375 | output_asm_insn ("mov%?\t%0, %1", ops); | |
13376 | } | |
13377 | else | |
13378 | for (i = 3; i >= 0; i--) | |
13379 | { | |
13380 | ops[0] = gen_rtx_REG (SImode, dest + i); | |
13381 | ops[1] = gen_rtx_REG (SImode, src + i); | |
13382 | output_asm_insn ("mov%?\t%0, %1", ops); | |
13383 | } | |
13384 | } | |
13385 | } | |
13386 | else | |
13387 | { | |
13388 | gcc_assert (MEM_P (operands[0])); | |
13389 | gcc_assert (REG_P (operands[1])); | |
13390 | gcc_assert (!reg_overlap_mentioned_p (operands[1], operands[0])); | |
13391 | ||
13392 | switch (GET_CODE (XEXP (operands[0], 0))) | |
13393 | { | |
13394 | case REG: | |
13395 | output_asm_insn ("stm%(ia%)\t%m0, %M1", operands); | |
13396 | break; | |
13397 | ||
13398 | default: | |
13399 | gcc_unreachable (); | |
13400 | } | |
13401 | } | |
13402 | ||
13403 | return ""; | |
13404 | } | |
13405 | ||
13406 | /* Output a VFP load or store instruction. */ | |
13407 | ||
13408 | const char * | |
13409 | output_move_vfp (rtx *operands) | |
13410 | { | |
13411 | rtx reg, mem, addr, ops[2]; | |
13412 | int load = REG_P (operands[0]); | |
13413 | int dp = GET_MODE_SIZE (GET_MODE (operands[0])) == 8; | |
13414 | int integer_p = GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT; | |
0a2aaacc | 13415 | const char *templ; |
88f77cba JB |
13416 | char buff[50]; |
13417 | enum machine_mode mode; | |
13418 | ||
13419 | reg = operands[!load]; | |
13420 | mem = operands[load]; | |
13421 | ||
13422 | mode = GET_MODE (reg); | |
13423 | ||
13424 | gcc_assert (REG_P (reg)); | |
13425 | gcc_assert (IS_VFP_REGNUM (REGNO (reg))); | |
13426 | gcc_assert (mode == SFmode | |
13427 | || mode == DFmode | |
13428 | || mode == SImode | |
13429 | || mode == DImode | |
13430 | || (TARGET_NEON && VALID_NEON_DREG_MODE (mode))); | |
13431 | gcc_assert (MEM_P (mem)); | |
13432 | ||
13433 | addr = XEXP (mem, 0); | |
13434 | ||
13435 | switch (GET_CODE (addr)) | |
13436 | { | |
13437 | case PRE_DEC: | |
0a2aaacc | 13438 | templ = "f%smdb%c%%?\t%%0!, {%%%s1}%s"; |
88f77cba JB |
13439 | ops[0] = XEXP (addr, 0); |
13440 | ops[1] = reg; | |
5b3e6663 PB |
13441 | break; |
13442 | ||
13443 | case POST_INC: | |
0a2aaacc | 13444 | templ = "f%smia%c%%?\t%%0!, {%%%s1}%s"; |
5b3e6663 PB |
13445 | ops[0] = XEXP (addr, 0); |
13446 | ops[1] = reg; | |
13447 | break; | |
13448 | ||
13449 | default: | |
0a2aaacc | 13450 | templ = "f%s%c%%?\t%%%s0, %%1%s"; |
5b3e6663 PB |
13451 | ops[0] = reg; |
13452 | ops[1] = mem; | |
13453 | break; | |
13454 | } | |
13455 | ||
0a2aaacc | 13456 | sprintf (buff, templ, |
5b3e6663 PB |
13457 | load ? "ld" : "st", |
13458 | dp ? 'd' : 's', | |
13459 | dp ? "P" : "", | |
13460 | integer_p ? "\t%@ int" : ""); | |
13461 | output_asm_insn (buff, ops); | |
13462 | ||
13463 | return ""; | |
13464 | } | |
13465 | ||
88f77cba | 13466 | /* Output a Neon quad-word load or store, or a load or store for |
874d42b9 | 13467 | larger structure modes. |
88f77cba | 13468 | |
874d42b9 JM |
13469 | WARNING: The ordering of elements is weird in big-endian mode, |
13470 | because we use VSTM, as required by the EABI. GCC RTL defines | |
13471 | element ordering based on in-memory order. This can be differ | |
13472 | from the architectural ordering of elements within a NEON register. | |
13473 | The intrinsics defined in arm_neon.h use the NEON register element | |
13474 | ordering, not the GCC RTL element ordering. | |
88f77cba | 13475 | |
874d42b9 JM |
13476 | For example, the in-memory ordering of a big-endian a quadword |
13477 | vector with 16-bit elements when stored from register pair {d0,d1} | |
13478 | will be (lowest address first, d0[N] is NEON register element N): | |
88f77cba | 13479 | |
874d42b9 | 13480 | [d0[3], d0[2], d0[1], d0[0], d1[7], d1[6], d1[5], d1[4]] |
88f77cba | 13481 | |
874d42b9 JM |
13482 | When necessary, quadword registers (dN, dN+1) are moved to ARM |
13483 | registers from rN in the order: | |
88f77cba JB |
13484 | |
13485 | dN -> (rN+1, rN), dN+1 -> (rN+3, rN+2) | |
13486 | ||
874d42b9 JM |
13487 | So that STM/LDM can be used on vectors in ARM registers, and the |
13488 | same memory layout will result as if VSTM/VLDM were used. */ | |
88f77cba JB |
13489 | |
13490 | const char * | |
13491 | output_move_neon (rtx *operands) | |
13492 | { | |
13493 | rtx reg, mem, addr, ops[2]; | |
13494 | int regno, load = REG_P (operands[0]); | |
0a2aaacc | 13495 | const char *templ; |
88f77cba JB |
13496 | char buff[50]; |
13497 | enum machine_mode mode; | |
13498 | ||
13499 | reg = operands[!load]; | |
13500 | mem = operands[load]; | |
13501 | ||
13502 | mode = GET_MODE (reg); | |
13503 | ||
13504 | gcc_assert (REG_P (reg)); | |
13505 | regno = REGNO (reg); | |
13506 | gcc_assert (VFP_REGNO_OK_FOR_DOUBLE (regno) | |
13507 | || NEON_REGNO_OK_FOR_QUAD (regno)); | |
13508 | gcc_assert (VALID_NEON_DREG_MODE (mode) | |
13509 | || VALID_NEON_QREG_MODE (mode) | |
13510 | || VALID_NEON_STRUCT_MODE (mode)); | |
13511 | gcc_assert (MEM_P (mem)); | |
13512 | ||
13513 | addr = XEXP (mem, 0); | |
13514 | ||
13515 | /* Strip off const from addresses like (const (plus (...))). */ | |
13516 | if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == PLUS) | |
13517 | addr = XEXP (addr, 0); | |
13518 | ||
13519 | switch (GET_CODE (addr)) | |
13520 | { | |
13521 | case POST_INC: | |
0a2aaacc | 13522 | templ = "v%smia%%?\t%%0!, %%h1"; |
88f77cba JB |
13523 | ops[0] = XEXP (addr, 0); |
13524 | ops[1] = reg; | |
13525 | break; | |
13526 | ||
dc34db56 PB |
13527 | case PRE_DEC: |
13528 | /* FIXME: We should be using vld1/vst1 here in BE mode? */ | |
13529 | templ = "v%smdb%%?\t%%0!, %%h1"; | |
13530 | ops[0] = XEXP (addr, 0); | |
13531 | ops[1] = reg; | |
13532 | break; | |
13533 | ||
88f77cba JB |
13534 | case POST_MODIFY: |
13535 | /* FIXME: Not currently enabled in neon_vector_mem_operand. */ | |
13536 | gcc_unreachable (); | |
13537 | ||
13538 | case LABEL_REF: | |
13539 | case PLUS: | |
13540 | { | |
13541 | int nregs = HARD_REGNO_NREGS (REGNO (reg), mode) / 2; | |
13542 | int i; | |
13543 | int overlap = -1; | |
13544 | for (i = 0; i < nregs; i++) | |
13545 | { | |
13546 | /* We're only using DImode here because it's a convenient size. */ | |
13547 | ops[0] = gen_rtx_REG (DImode, REGNO (reg) + 2 * i); | |
5728868b | 13548 | ops[1] = adjust_address (mem, DImode, 8 * i); |
88f77cba JB |
13549 | if (reg_overlap_mentioned_p (ops[0], mem)) |
13550 | { | |
13551 | gcc_assert (overlap == -1); | |
13552 | overlap = i; | |
13553 | } | |
13554 | else | |
13555 | { | |
13556 | sprintf (buff, "v%sr%%?\t%%P0, %%1", load ? "ld" : "st"); | |
13557 | output_asm_insn (buff, ops); | |
13558 | } | |
13559 | } | |
13560 | if (overlap != -1) | |
13561 | { | |
13562 | ops[0] = gen_rtx_REG (DImode, REGNO (reg) + 2 * overlap); | |
13563 | ops[1] = adjust_address (mem, SImode, 8 * overlap); | |
13564 | sprintf (buff, "v%sr%%?\t%%P0, %%1", load ? "ld" : "st"); | |
13565 | output_asm_insn (buff, ops); | |
13566 | } | |
13567 | ||
13568 | return ""; | |
13569 | } | |
13570 | ||
13571 | default: | |
0a2aaacc | 13572 | templ = "v%smia%%?\t%%m0, %%h1"; |
88f77cba JB |
13573 | ops[0] = mem; |
13574 | ops[1] = reg; | |
13575 | } | |
13576 | ||
0a2aaacc | 13577 | sprintf (buff, templ, load ? "ld" : "st"); |
88f77cba JB |
13578 | output_asm_insn (buff, ops); |
13579 | ||
13580 | return ""; | |
13581 | } | |
13582 | ||
7c4f0041 JZ |
13583 | /* Compute and return the length of neon_mov<mode>, where <mode> is |
13584 | one of VSTRUCT modes: EI, OI, CI or XI. */ | |
13585 | int | |
13586 | arm_attr_length_move_neon (rtx insn) | |
13587 | { | |
13588 | rtx reg, mem, addr; | |
e4dde839 | 13589 | int load; |
7c4f0041 JZ |
13590 | enum machine_mode mode; |
13591 | ||
13592 | extract_insn_cached (insn); | |
13593 | ||
13594 | if (REG_P (recog_data.operand[0]) && REG_P (recog_data.operand[1])) | |
13595 | { | |
13596 | mode = GET_MODE (recog_data.operand[0]); | |
13597 | switch (mode) | |
13598 | { | |
13599 | case EImode: | |
13600 | case OImode: | |
13601 | return 8; | |
13602 | case CImode: | |
13603 | return 12; | |
13604 | case XImode: | |
13605 | return 16; | |
13606 | default: | |
13607 | gcc_unreachable (); | |
13608 | } | |
13609 | } | |
13610 | ||
13611 | load = REG_P (recog_data.operand[0]); | |
13612 | reg = recog_data.operand[!load]; | |
13613 | mem = recog_data.operand[load]; | |
13614 | ||
13615 | gcc_assert (MEM_P (mem)); | |
13616 | ||
13617 | mode = GET_MODE (reg); | |
7c4f0041 JZ |
13618 | addr = XEXP (mem, 0); |
13619 | ||
13620 | /* Strip off const from addresses like (const (plus (...))). */ | |
13621 | if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == PLUS) | |
13622 | addr = XEXP (addr, 0); | |
13623 | ||
13624 | if (GET_CODE (addr) == LABEL_REF || GET_CODE (addr) == PLUS) | |
13625 | { | |
13626 | int insns = HARD_REGNO_NREGS (REGNO (reg), mode) / 2; | |
13627 | return insns * 4; | |
13628 | } | |
13629 | else | |
13630 | return 4; | |
13631 | } | |
13632 | ||
47d8f18d JZ |
13633 | /* Return nonzero if the offset in the address is an immediate. Otherwise, |
13634 | return zero. */ | |
13635 | ||
13636 | int | |
13637 | arm_address_offset_is_imm (rtx insn) | |
13638 | { | |
13639 | rtx mem, addr; | |
13640 | ||
13641 | extract_insn_cached (insn); | |
13642 | ||
13643 | if (REG_P (recog_data.operand[0])) | |
13644 | return 0; | |
13645 | ||
13646 | mem = recog_data.operand[0]; | |
13647 | ||
13648 | gcc_assert (MEM_P (mem)); | |
13649 | ||
13650 | addr = XEXP (mem, 0); | |
13651 | ||
13652 | if (GET_CODE (addr) == REG | |
13653 | || (GET_CODE (addr) == PLUS | |
13654 | && GET_CODE (XEXP (addr, 0)) == REG | |
13655 | && GET_CODE (XEXP (addr, 1)) == CONST_INT)) | |
13656 | return 1; | |
13657 | else | |
13658 | return 0; | |
13659 | } | |
13660 | ||
1d6e90ac NC |
13661 | /* Output an ADD r, s, #n where n may be too big for one instruction. |
13662 | If adding zero to one register, output nothing. */ | |
cd2b33d0 | 13663 | const char * |
e32bac5b | 13664 | output_add_immediate (rtx *operands) |
cce8749e | 13665 | { |
f3bb6135 | 13666 | HOST_WIDE_INT n = INTVAL (operands[2]); |
cce8749e CH |
13667 | |
13668 | if (n != 0 || REGNO (operands[0]) != REGNO (operands[1])) | |
13669 | { | |
13670 | if (n < 0) | |
13671 | output_multi_immediate (operands, | |
9997d19d RE |
13672 | "sub%?\t%0, %1, %2", "sub%?\t%0, %0, %2", 2, |
13673 | -n); | |
cce8749e CH |
13674 | else |
13675 | output_multi_immediate (operands, | |
9997d19d RE |
13676 | "add%?\t%0, %1, %2", "add%?\t%0, %0, %2", 2, |
13677 | n); | |
cce8749e | 13678 | } |
f3bb6135 RE |
13679 | |
13680 | return ""; | |
13681 | } | |
cce8749e | 13682 | |
cce8749e CH |
13683 | /* Output a multiple immediate operation. |
13684 | OPERANDS is the vector of operands referred to in the output patterns. | |
13685 | INSTR1 is the output pattern to use for the first constant. | |
13686 | INSTR2 is the output pattern to use for subsequent constants. | |
13687 | IMMED_OP is the index of the constant slot in OPERANDS. | |
13688 | N is the constant value. */ | |
cd2b33d0 | 13689 | static const char * |
e32bac5b RE |
13690 | output_multi_immediate (rtx *operands, const char *instr1, const char *instr2, |
13691 | int immed_op, HOST_WIDE_INT n) | |
cce8749e | 13692 | { |
f3bb6135 | 13693 | #if HOST_BITS_PER_WIDE_INT > 32 |
30cf4896 | 13694 | n &= 0xffffffff; |
f3bb6135 RE |
13695 | #endif |
13696 | ||
cce8749e CH |
13697 | if (n == 0) |
13698 | { | |
1d6e90ac | 13699 | /* Quick and easy output. */ |
cce8749e | 13700 | operands[immed_op] = const0_rtx; |
1d6e90ac | 13701 | output_asm_insn (instr1, operands); |
cce8749e CH |
13702 | } |
13703 | else | |
13704 | { | |
13705 | int i; | |
cd2b33d0 | 13706 | const char * instr = instr1; |
cce8749e | 13707 | |
6354dc9b | 13708 | /* Note that n is never zero here (which would give no output). */ |
cce8749e CH |
13709 | for (i = 0; i < 32; i += 2) |
13710 | { | |
13711 | if (n & (3 << i)) | |
13712 | { | |
f3bb6135 RE |
13713 | operands[immed_op] = GEN_INT (n & (255 << i)); |
13714 | output_asm_insn (instr, operands); | |
cce8749e CH |
13715 | instr = instr2; |
13716 | i += 6; | |
13717 | } | |
13718 | } | |
13719 | } | |
f676971a | 13720 | |
f3bb6135 | 13721 | return ""; |
9997d19d | 13722 | } |
cce8749e | 13723 | |
5b3e6663 PB |
13724 | /* Return the name of a shifter operation. */ |
13725 | static const char * | |
13726 | arm_shift_nmem(enum rtx_code code) | |
13727 | { | |
13728 | switch (code) | |
13729 | { | |
13730 | case ASHIFT: | |
13731 | return ARM_LSL_NAME; | |
13732 | ||
13733 | case ASHIFTRT: | |
13734 | return "asr"; | |
13735 | ||
13736 | case LSHIFTRT: | |
13737 | return "lsr"; | |
13738 | ||
13739 | case ROTATERT: | |
13740 | return "ror"; | |
13741 | ||
13742 | default: | |
13743 | abort(); | |
13744 | } | |
13745 | } | |
13746 | ||
cce8749e CH |
13747 | /* Return the appropriate ARM instruction for the operation code. |
13748 | The returned result should not be overwritten. OP is the rtx of the | |
13749 | operation. SHIFT_FIRST_ARG is TRUE if the first argument of the operator | |
13750 | was shifted. */ | |
cd2b33d0 | 13751 | const char * |
e32bac5b | 13752 | arithmetic_instr (rtx op, int shift_first_arg) |
cce8749e | 13753 | { |
9997d19d | 13754 | switch (GET_CODE (op)) |
cce8749e CH |
13755 | { |
13756 | case PLUS: | |
f3bb6135 RE |
13757 | return "add"; |
13758 | ||
cce8749e | 13759 | case MINUS: |
f3bb6135 RE |
13760 | return shift_first_arg ? "rsb" : "sub"; |
13761 | ||
cce8749e | 13762 | case IOR: |
f3bb6135 RE |
13763 | return "orr"; |
13764 | ||
cce8749e | 13765 | case XOR: |
f3bb6135 RE |
13766 | return "eor"; |
13767 | ||
cce8749e | 13768 | case AND: |
f3bb6135 RE |
13769 | return "and"; |
13770 | ||
5b3e6663 PB |
13771 | case ASHIFT: |
13772 | case ASHIFTRT: | |
13773 | case LSHIFTRT: | |
13774 | case ROTATERT: | |
13775 | return arm_shift_nmem(GET_CODE(op)); | |
13776 | ||
cce8749e | 13777 | default: |
e6d29d15 | 13778 | gcc_unreachable (); |
cce8749e | 13779 | } |
f3bb6135 | 13780 | } |
cce8749e | 13781 | |
cce8749e CH |
13782 | /* Ensure valid constant shifts and return the appropriate shift mnemonic |
13783 | for the operation code. The returned result should not be overwritten. | |
13784 | OP is the rtx code of the shift. | |
9997d19d | 13785 | On exit, *AMOUNTP will be -1 if the shift is by a register, or a constant |
6354dc9b | 13786 | shift. */ |
cd2b33d0 | 13787 | static const char * |
e32bac5b | 13788 | shift_op (rtx op, HOST_WIDE_INT *amountp) |
cce8749e | 13789 | { |
cd2b33d0 | 13790 | const char * mnem; |
e2c671ba | 13791 | enum rtx_code code = GET_CODE (op); |
cce8749e | 13792 | |
e6d29d15 NS |
13793 | switch (GET_CODE (XEXP (op, 1))) |
13794 | { | |
13795 | case REG: | |
13796 | case SUBREG: | |
13797 | *amountp = -1; | |
13798 | break; | |
13799 | ||
13800 | case CONST_INT: | |
13801 | *amountp = INTVAL (XEXP (op, 1)); | |
13802 | break; | |
13803 | ||
13804 | default: | |
13805 | gcc_unreachable (); | |
13806 | } | |
9997d19d | 13807 | |
e2c671ba | 13808 | switch (code) |
cce8749e | 13809 | { |
a657c98a | 13810 | case ROTATE: |
e6d29d15 | 13811 | gcc_assert (*amountp != -1); |
a657c98a | 13812 | *amountp = 32 - *amountp; |
5b3e6663 | 13813 | code = ROTATERT; |
a657c98a RE |
13814 | |
13815 | /* Fall through. */ | |
13816 | ||
5b3e6663 PB |
13817 | case ASHIFT: |
13818 | case ASHIFTRT: | |
13819 | case LSHIFTRT: | |
9997d19d | 13820 | case ROTATERT: |
5b3e6663 | 13821 | mnem = arm_shift_nmem(code); |
9997d19d RE |
13822 | break; |
13823 | ||
ff9940b0 | 13824 | case MULT: |
e2c671ba RE |
13825 | /* We never have to worry about the amount being other than a |
13826 | power of 2, since this case can never be reloaded from a reg. */ | |
e6d29d15 NS |
13827 | gcc_assert (*amountp != -1); |
13828 | *amountp = int_log2 (*amountp); | |
5b3e6663 | 13829 | return ARM_LSL_NAME; |
f3bb6135 | 13830 | |
cce8749e | 13831 | default: |
e6d29d15 | 13832 | gcc_unreachable (); |
cce8749e CH |
13833 | } |
13834 | ||
e2c671ba RE |
13835 | if (*amountp != -1) |
13836 | { | |
13837 | /* This is not 100% correct, but follows from the desire to merge | |
13838 | multiplication by a power of 2 with the recognizer for a | |
5b3e6663 | 13839 | shift. >=32 is not a valid shift for "lsl", so we must try and |
e2c671ba | 13840 | output a shift that produces the correct arithmetical result. |
ddd5a7c1 | 13841 | Using lsr #32 is identical except for the fact that the carry bit |
f676971a | 13842 | is not set correctly if we set the flags; but we never use the |
e2c671ba RE |
13843 | carry bit from such an operation, so we can ignore that. */ |
13844 | if (code == ROTATERT) | |
1d6e90ac NC |
13845 | /* Rotate is just modulo 32. */ |
13846 | *amountp &= 31; | |
e2c671ba RE |
13847 | else if (*amountp != (*amountp & 31)) |
13848 | { | |
13849 | if (code == ASHIFT) | |
13850 | mnem = "lsr"; | |
13851 | *amountp = 32; | |
13852 | } | |
13853 | ||
13854 | /* Shifts of 0 are no-ops. */ | |
13855 | if (*amountp == 0) | |
13856 | return NULL; | |
f676971a | 13857 | } |
e2c671ba | 13858 | |
9997d19d RE |
13859 | return mnem; |
13860 | } | |
cce8749e | 13861 | |
6354dc9b | 13862 | /* Obtain the shift from the POWER of two. */ |
1d6e90ac | 13863 | |
18af7313 | 13864 | static HOST_WIDE_INT |
e32bac5b | 13865 | int_log2 (HOST_WIDE_INT power) |
cce8749e | 13866 | { |
f3bb6135 | 13867 | HOST_WIDE_INT shift = 0; |
cce8749e | 13868 | |
30cf4896 | 13869 | while ((((HOST_WIDE_INT) 1 << shift) & power) == 0) |
cce8749e | 13870 | { |
e6d29d15 | 13871 | gcc_assert (shift <= 31); |
e32bac5b | 13872 | shift++; |
cce8749e | 13873 | } |
f3bb6135 RE |
13874 | |
13875 | return shift; | |
13876 | } | |
cce8749e | 13877 | |
c5ff069d ZW |
13878 | /* Output a .ascii pseudo-op, keeping track of lengths. This is |
13879 | because /bin/as is horribly restrictive. The judgement about | |
13880 | whether or not each character is 'printable' (and can be output as | |
13881 | is) or not (and must be printed with an octal escape) must be made | |
13882 | with reference to the *host* character set -- the situation is | |
13883 | similar to that discussed in the comments above pp_c_char in | |
13884 | c-pretty-print.c. */ | |
13885 | ||
6cfc7210 | 13886 | #define MAX_ASCII_LEN 51 |
cce8749e CH |
13887 | |
13888 | void | |
e32bac5b | 13889 | output_ascii_pseudo_op (FILE *stream, const unsigned char *p, int len) |
cce8749e CH |
13890 | { |
13891 | int i; | |
6cfc7210 | 13892 | int len_so_far = 0; |
cce8749e | 13893 | |
6cfc7210 | 13894 | fputs ("\t.ascii\t\"", stream); |
f676971a | 13895 | |
cce8749e CH |
13896 | for (i = 0; i < len; i++) |
13897 | { | |
1d6e90ac | 13898 | int c = p[i]; |
cce8749e | 13899 | |
6cfc7210 | 13900 | if (len_so_far >= MAX_ASCII_LEN) |
cce8749e | 13901 | { |
6cfc7210 | 13902 | fputs ("\"\n\t.ascii\t\"", stream); |
cce8749e | 13903 | len_so_far = 0; |
cce8749e CH |
13904 | } |
13905 | ||
c5ff069d | 13906 | if (ISPRINT (c)) |
cce8749e | 13907 | { |
c5ff069d | 13908 | if (c == '\\' || c == '\"') |
6cfc7210 | 13909 | { |
c5ff069d | 13910 | putc ('\\', stream); |
5895f793 | 13911 | len_so_far++; |
6cfc7210 | 13912 | } |
c5ff069d ZW |
13913 | putc (c, stream); |
13914 | len_so_far++; | |
13915 | } | |
13916 | else | |
13917 | { | |
13918 | fprintf (stream, "\\%03o", c); | |
13919 | len_so_far += 4; | |
cce8749e | 13920 | } |
cce8749e | 13921 | } |
f3bb6135 | 13922 | |
cce8749e | 13923 | fputs ("\"\n", stream); |
f3bb6135 | 13924 | } |
cce8749e | 13925 | \f |
c9ca9b88 | 13926 | /* Compute the register save mask for registers 0 through 12 |
5848830f | 13927 | inclusive. This code is used by arm_compute_save_reg_mask. */ |
b279b20a | 13928 | |
6d3d9133 | 13929 | static unsigned long |
e32bac5b | 13930 | arm_compute_save_reg0_reg12_mask (void) |
6d3d9133 | 13931 | { |
121308d4 | 13932 | unsigned long func_type = arm_current_func_type (); |
b279b20a | 13933 | unsigned long save_reg_mask = 0; |
6d3d9133 | 13934 | unsigned int reg; |
6d3d9133 | 13935 | |
7b8b8ade | 13936 | if (IS_INTERRUPT (func_type)) |
6d3d9133 | 13937 | { |
7b8b8ade | 13938 | unsigned int max_reg; |
7b8b8ade NC |
13939 | /* Interrupt functions must not corrupt any registers, |
13940 | even call clobbered ones. If this is a leaf function | |
13941 | we can just examine the registers used by the RTL, but | |
13942 | otherwise we have to assume that whatever function is | |
13943 | called might clobber anything, and so we have to save | |
13944 | all the call-clobbered registers as well. */ | |
13945 | if (ARM_FUNC_TYPE (func_type) == ARM_FT_FIQ) | |
13946 | /* FIQ handlers have registers r8 - r12 banked, so | |
13947 | we only need to check r0 - r7, Normal ISRs only | |
121308d4 | 13948 | bank r14 and r15, so we must check up to r12. |
7b8b8ade NC |
13949 | r13 is the stack pointer which is always preserved, |
13950 | so we do not need to consider it here. */ | |
13951 | max_reg = 7; | |
13952 | else | |
13953 | max_reg = 12; | |
f676971a | 13954 | |
7b8b8ade | 13955 | for (reg = 0; reg <= max_reg; reg++) |
6fb5fa3c DB |
13956 | if (df_regs_ever_live_p (reg) |
13957 | || (! current_function_is_leaf && call_used_regs[reg])) | |
6d3d9133 | 13958 | save_reg_mask |= (1 << reg); |
cfa01aab | 13959 | |
286d28c3 | 13960 | /* Also save the pic base register if necessary. */ |
cfa01aab PB |
13961 | if (flag_pic |
13962 | && !TARGET_SINGLE_PIC_BASE | |
020a4035 | 13963 | && arm_pic_register != INVALID_REGNUM |
e3b5732b | 13964 | && crtl->uses_pic_offset_table) |
cfa01aab | 13965 | save_reg_mask |= 1 << PIC_OFFSET_TABLE_REGNUM; |
6d3d9133 | 13966 | } |
1586899e PB |
13967 | else if (IS_VOLATILE(func_type)) |
13968 | { | |
13969 | /* For noreturn functions we historically omitted register saves | |
13970 | altogether. However this really messes up debugging. As a | |
3ed04dbd | 13971 | compromise save just the frame pointers. Combined with the link |
1586899e PB |
13972 | register saved elsewhere this should be sufficient to get |
13973 | a backtrace. */ | |
13974 | if (frame_pointer_needed) | |
13975 | save_reg_mask |= 1 << HARD_FRAME_POINTER_REGNUM; | |
13976 | if (df_regs_ever_live_p (ARM_HARD_FRAME_POINTER_REGNUM)) | |
13977 | save_reg_mask |= 1 << ARM_HARD_FRAME_POINTER_REGNUM; | |
13978 | if (df_regs_ever_live_p (THUMB_HARD_FRAME_POINTER_REGNUM)) | |
13979 | save_reg_mask |= 1 << THUMB_HARD_FRAME_POINTER_REGNUM; | |
13980 | } | |
6d3d9133 NC |
13981 | else |
13982 | { | |
13983 | /* In the normal case we only need to save those registers | |
13984 | which are call saved and which are used by this function. */ | |
ec6237e4 | 13985 | for (reg = 0; reg <= 11; reg++) |
6fb5fa3c | 13986 | if (df_regs_ever_live_p (reg) && ! call_used_regs[reg]) |
6d3d9133 NC |
13987 | save_reg_mask |= (1 << reg); |
13988 | ||
13989 | /* Handle the frame pointer as a special case. */ | |
ec6237e4 | 13990 | if (frame_pointer_needed) |
6d3d9133 NC |
13991 | save_reg_mask |= 1 << HARD_FRAME_POINTER_REGNUM; |
13992 | ||
13993 | /* If we aren't loading the PIC register, | |
13994 | don't stack it even though it may be live. */ | |
13995 | if (flag_pic | |
e0b92319 | 13996 | && !TARGET_SINGLE_PIC_BASE |
020a4035 | 13997 | && arm_pic_register != INVALID_REGNUM |
6fb5fa3c | 13998 | && (df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM) |
e3b5732b | 13999 | || crtl->uses_pic_offset_table)) |
6d3d9133 | 14000 | save_reg_mask |= 1 << PIC_OFFSET_TABLE_REGNUM; |
5b3e6663 PB |
14001 | |
14002 | /* The prologue will copy SP into R0, so save it. */ | |
14003 | if (IS_STACKALIGN (func_type)) | |
14004 | save_reg_mask |= 1; | |
6d3d9133 NC |
14005 | } |
14006 | ||
c9ca9b88 | 14007 | /* Save registers so the exception handler can modify them. */ |
e3b5732b | 14008 | if (crtl->calls_eh_return) |
c9ca9b88 PB |
14009 | { |
14010 | unsigned int i; | |
f676971a | 14011 | |
c9ca9b88 PB |
14012 | for (i = 0; ; i++) |
14013 | { | |
14014 | reg = EH_RETURN_DATA_REGNO (i); | |
14015 | if (reg == INVALID_REGNUM) | |
14016 | break; | |
14017 | save_reg_mask |= 1 << reg; | |
14018 | } | |
14019 | } | |
14020 | ||
121308d4 NC |
14021 | return save_reg_mask; |
14022 | } | |
14023 | ||
5b3e6663 | 14024 | |
35596784 AJ |
14025 | /* Compute the number of bytes used to store the static chain register on the |
14026 | stack, above the stack frame. We need to know this accurately to get the | |
14027 | alignment of the rest of the stack frame correct. */ | |
14028 | ||
14029 | static int arm_compute_static_chain_stack_bytes (void) | |
14030 | { | |
14031 | unsigned long func_type = arm_current_func_type (); | |
14032 | int static_chain_stack_bytes = 0; | |
14033 | ||
14034 | if (TARGET_APCS_FRAME && frame_pointer_needed && TARGET_ARM && | |
14035 | IS_NESTED (func_type) && | |
14036 | df_regs_ever_live_p (3) && crtl->args.pretend_args_size == 0) | |
14037 | static_chain_stack_bytes = 4; | |
14038 | ||
14039 | return static_chain_stack_bytes; | |
14040 | } | |
14041 | ||
14042 | ||
121308d4 | 14043 | /* Compute a bit mask of which registers need to be |
954954d1 PB |
14044 | saved on the stack for the current function. |
14045 | This is used by arm_get_frame_offsets, which may add extra registers. */ | |
121308d4 NC |
14046 | |
14047 | static unsigned long | |
e32bac5b | 14048 | arm_compute_save_reg_mask (void) |
121308d4 NC |
14049 | { |
14050 | unsigned int save_reg_mask = 0; | |
14051 | unsigned long func_type = arm_current_func_type (); | |
5b3e6663 | 14052 | unsigned int reg; |
121308d4 NC |
14053 | |
14054 | if (IS_NAKED (func_type)) | |
14055 | /* This should never really happen. */ | |
14056 | return 0; | |
14057 | ||
14058 | /* If we are creating a stack frame, then we must save the frame pointer, | |
14059 | IP (which will hold the old stack pointer), LR and the PC. */ | |
ec6237e4 | 14060 | if (TARGET_APCS_FRAME && frame_pointer_needed && TARGET_ARM) |
121308d4 NC |
14061 | save_reg_mask |= |
14062 | (1 << ARM_HARD_FRAME_POINTER_REGNUM) | |
14063 | | (1 << IP_REGNUM) | |
14064 | | (1 << LR_REGNUM) | |
14065 | | (1 << PC_REGNUM); | |
14066 | ||
121308d4 NC |
14067 | save_reg_mask |= arm_compute_save_reg0_reg12_mask (); |
14068 | ||
6d3d9133 NC |
14069 | /* Decide if we need to save the link register. |
14070 | Interrupt routines have their own banked link register, | |
14071 | so they never need to save it. | |
1768c26f | 14072 | Otherwise if we do not use the link register we do not need to save |
6d3d9133 NC |
14073 | it. If we are pushing other registers onto the stack however, we |
14074 | can save an instruction in the epilogue by pushing the link register | |
14075 | now and then popping it back into the PC. This incurs extra memory | |
72ac76be | 14076 | accesses though, so we only do it when optimizing for size, and only |
6d3d9133 | 14077 | if we know that we will not need a fancy return sequence. */ |
6fb5fa3c DB |
14078 | if (df_regs_ever_live_p (LR_REGNUM) |
14079 | || (save_reg_mask | |
14080 | && optimize_size | |
14081 | && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL | |
e3b5732b | 14082 | && !crtl->calls_eh_return)) |
6d3d9133 NC |
14083 | save_reg_mask |= 1 << LR_REGNUM; |
14084 | ||
6f7ebcbb NC |
14085 | if (cfun->machine->lr_save_eliminated) |
14086 | save_reg_mask &= ~ (1 << LR_REGNUM); | |
14087 | ||
5a9335ef NC |
14088 | if (TARGET_REALLY_IWMMXT |
14089 | && ((bit_count (save_reg_mask) | |
35596784 AJ |
14090 | + ARM_NUM_INTS (crtl->args.pretend_args_size + |
14091 | arm_compute_static_chain_stack_bytes()) | |
14092 | ) % 2) != 0) | |
5a9335ef | 14093 | { |
5a9335ef NC |
14094 | /* The total number of registers that are going to be pushed |
14095 | onto the stack is odd. We need to ensure that the stack | |
14096 | is 64-bit aligned before we start to save iWMMXt registers, | |
14097 | and also before we start to create locals. (A local variable | |
14098 | might be a double or long long which we will load/store using | |
14099 | an iWMMXt instruction). Therefore we need to push another | |
14100 | ARM register, so that the stack will be 64-bit aligned. We | |
14101 | try to avoid using the arg registers (r0 -r3) as they might be | |
14102 | used to pass values in a tail call. */ | |
14103 | for (reg = 4; reg <= 12; reg++) | |
14104 | if ((save_reg_mask & (1 << reg)) == 0) | |
14105 | break; | |
14106 | ||
14107 | if (reg <= 12) | |
14108 | save_reg_mask |= (1 << reg); | |
14109 | else | |
14110 | { | |
14111 | cfun->machine->sibcall_blocked = 1; | |
14112 | save_reg_mask |= (1 << 3); | |
14113 | } | |
14114 | } | |
14115 | ||
5b3e6663 PB |
14116 | /* We may need to push an additional register for use initializing the |
14117 | PIC base register. */ | |
14118 | if (TARGET_THUMB2 && IS_NESTED (func_type) && flag_pic | |
14119 | && (save_reg_mask & THUMB2_WORK_REGS) == 0) | |
14120 | { | |
14121 | reg = thumb_find_work_register (1 << 4); | |
14122 | if (!call_used_regs[reg]) | |
14123 | save_reg_mask |= (1 << reg); | |
14124 | } | |
14125 | ||
6d3d9133 NC |
14126 | return save_reg_mask; |
14127 | } | |
14128 | ||
9728c9d1 | 14129 | |
57934c39 PB |
14130 | /* Compute a bit mask of which registers need to be |
14131 | saved on the stack for the current function. */ | |
14132 | static unsigned long | |
5b3e6663 | 14133 | thumb1_compute_save_reg_mask (void) |
57934c39 PB |
14134 | { |
14135 | unsigned long mask; | |
b279b20a | 14136 | unsigned reg; |
57934c39 PB |
14137 | |
14138 | mask = 0; | |
14139 | for (reg = 0; reg < 12; reg ++) | |
6fb5fa3c | 14140 | if (df_regs_ever_live_p (reg) && !call_used_regs[reg]) |
b279b20a | 14141 | mask |= 1 << reg; |
57934c39 | 14142 | |
39c39be0 RE |
14143 | if (flag_pic |
14144 | && !TARGET_SINGLE_PIC_BASE | |
020a4035 | 14145 | && arm_pic_register != INVALID_REGNUM |
e3b5732b | 14146 | && crtl->uses_pic_offset_table) |
39c39be0 | 14147 | mask |= 1 << PIC_OFFSET_TABLE_REGNUM; |
b279b20a | 14148 | |
a2503645 RS |
14149 | /* See if we might need r11 for calls to _interwork_r11_call_via_rN(). */ |
14150 | if (!frame_pointer_needed && CALLER_INTERWORKING_SLOT_SIZE > 0) | |
14151 | mask |= 1 << ARM_HARD_FRAME_POINTER_REGNUM; | |
57934c39 | 14152 | |
b279b20a | 14153 | /* LR will also be pushed if any lo regs are pushed. */ |
57934c39 PB |
14154 | if (mask & 0xff || thumb_force_lr_save ()) |
14155 | mask |= (1 << LR_REGNUM); | |
14156 | ||
b279b20a NC |
14157 | /* Make sure we have a low work register if we need one. |
14158 | We will need one if we are going to push a high register, | |
14159 | but we are not currently intending to push a low register. */ | |
14160 | if ((mask & 0xff) == 0 | |
57934c39 | 14161 | && ((mask & 0x0f00) || TARGET_BACKTRACE)) |
b279b20a NC |
14162 | { |
14163 | /* Use thumb_find_work_register to choose which register | |
14164 | we will use. If the register is live then we will | |
14165 | have to push it. Use LAST_LO_REGNUM as our fallback | |
14166 | choice for the register to select. */ | |
14167 | reg = thumb_find_work_register (1 << LAST_LO_REGNUM); | |
19e723f4 PB |
14168 | /* Make sure the register returned by thumb_find_work_register is |
14169 | not part of the return value. */ | |
954954d1 | 14170 | if (reg * UNITS_PER_WORD <= (unsigned) arm_size_return_regs ()) |
19e723f4 | 14171 | reg = LAST_LO_REGNUM; |
b279b20a NC |
14172 | |
14173 | if (! call_used_regs[reg]) | |
14174 | mask |= 1 << reg; | |
14175 | } | |
57934c39 | 14176 | |
35596784 AJ |
14177 | /* The 504 below is 8 bytes less than 512 because there are two possible |
14178 | alignment words. We can't tell here if they will be present or not so we | |
14179 | have to play it safe and assume that they are. */ | |
14180 | if ((CALLER_INTERWORKING_SLOT_SIZE + | |
14181 | ROUND_UP_WORD (get_frame_size ()) + | |
14182 | crtl->outgoing_args_size) >= 504) | |
14183 | { | |
14184 | /* This is the same as the code in thumb1_expand_prologue() which | |
14185 | determines which register to use for stack decrement. */ | |
14186 | for (reg = LAST_ARG_REGNUM + 1; reg <= LAST_LO_REGNUM; reg++) | |
14187 | if (mask & (1 << reg)) | |
14188 | break; | |
14189 | ||
14190 | if (reg > LAST_LO_REGNUM) | |
14191 | { | |
14192 | /* Make sure we have a register available for stack decrement. */ | |
14193 | mask |= 1 << LAST_LO_REGNUM; | |
14194 | } | |
14195 | } | |
14196 | ||
57934c39 PB |
14197 | return mask; |
14198 | } | |
14199 | ||
14200 | ||
9728c9d1 PB |
14201 | /* Return the number of bytes required to save VFP registers. */ |
14202 | static int | |
14203 | arm_get_vfp_saved_size (void) | |
14204 | { | |
14205 | unsigned int regno; | |
14206 | int count; | |
14207 | int saved; | |
14208 | ||
14209 | saved = 0; | |
14210 | /* Space for saved VFP registers. */ | |
14211 | if (TARGET_HARD_FLOAT && TARGET_VFP) | |
14212 | { | |
14213 | count = 0; | |
14214 | for (regno = FIRST_VFP_REGNUM; | |
14215 | regno < LAST_VFP_REGNUM; | |
14216 | regno += 2) | |
14217 | { | |
6fb5fa3c DB |
14218 | if ((!df_regs_ever_live_p (regno) || call_used_regs[regno]) |
14219 | && (!df_regs_ever_live_p (regno + 1) || call_used_regs[regno + 1])) | |
9728c9d1 PB |
14220 | { |
14221 | if (count > 0) | |
14222 | { | |
14223 | /* Workaround ARM10 VFPr1 bug. */ | |
14224 | if (count == 2 && !arm_arch6) | |
14225 | count++; | |
8edfc4cc | 14226 | saved += count * 8; |
9728c9d1 PB |
14227 | } |
14228 | count = 0; | |
14229 | } | |
14230 | else | |
14231 | count++; | |
14232 | } | |
14233 | if (count > 0) | |
14234 | { | |
14235 | if (count == 2 && !arm_arch6) | |
14236 | count++; | |
8edfc4cc | 14237 | saved += count * 8; |
9728c9d1 PB |
14238 | } |
14239 | } | |
14240 | return saved; | |
14241 | } | |
14242 | ||
14243 | ||
699a4925 | 14244 | /* Generate a function exit sequence. If REALLY_RETURN is false, then do |
6d3d9133 | 14245 | everything bar the final return instruction. */ |
cd2b33d0 | 14246 | const char * |
e32bac5b | 14247 | output_return_instruction (rtx operand, int really_return, int reverse) |
ff9940b0 | 14248 | { |
6d3d9133 | 14249 | char conditional[10]; |
ff9940b0 | 14250 | char instr[100]; |
b279b20a | 14251 | unsigned reg; |
6d3d9133 NC |
14252 | unsigned long live_regs_mask; |
14253 | unsigned long func_type; | |
5848830f | 14254 | arm_stack_offsets *offsets; |
e26053d1 | 14255 | |
6d3d9133 | 14256 | func_type = arm_current_func_type (); |
e2c671ba | 14257 | |
6d3d9133 | 14258 | if (IS_NAKED (func_type)) |
d5b7b3ae | 14259 | return ""; |
6d3d9133 NC |
14260 | |
14261 | if (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN) | |
e2c671ba | 14262 | { |
699a4925 RE |
14263 | /* If this function was declared non-returning, and we have |
14264 | found a tail call, then we have to trust that the called | |
14265 | function won't return. */ | |
3a5a4282 PB |
14266 | if (really_return) |
14267 | { | |
14268 | rtx ops[2]; | |
f676971a | 14269 | |
3a5a4282 PB |
14270 | /* Otherwise, trap an attempted return by aborting. */ |
14271 | ops[0] = operand; | |
f676971a | 14272 | ops[1] = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)" |
3a5a4282 PB |
14273 | : "abort"); |
14274 | assemble_external_libcall (ops[1]); | |
14275 | output_asm_insn (reverse ? "bl%D0\t%a1" : "bl%d0\t%a1", ops); | |
14276 | } | |
f676971a | 14277 | |
e2c671ba RE |
14278 | return ""; |
14279 | } | |
6d3d9133 | 14280 | |
e3b5732b | 14281 | gcc_assert (!cfun->calls_alloca || really_return); |
ff9940b0 | 14282 | |
c414f8a9 | 14283 | sprintf (conditional, "%%?%%%c0", reverse ? 'D' : 'd'); |
d5b7b3ae | 14284 | |
934c2060 | 14285 | cfun->machine->return_used_this_function = 1; |
ff9940b0 | 14286 | |
954954d1 PB |
14287 | offsets = arm_get_frame_offsets (); |
14288 | live_regs_mask = offsets->saved_regs_mask; | |
ff9940b0 | 14289 | |
1768c26f | 14290 | if (live_regs_mask) |
6d3d9133 | 14291 | { |
1768c26f PB |
14292 | const char * return_reg; |
14293 | ||
f676971a | 14294 | /* If we do not have any special requirements for function exit |
a15908a4 | 14295 | (e.g. interworking) then we can load the return address |
1768c26f PB |
14296 | directly into the PC. Otherwise we must load it into LR. */ |
14297 | if (really_return | |
a15908a4 | 14298 | && (IS_INTERRUPT (func_type) || !TARGET_INTERWORK)) |
1768c26f | 14299 | return_reg = reg_names[PC_REGNUM]; |
6d3d9133 | 14300 | else |
1768c26f PB |
14301 | return_reg = reg_names[LR_REGNUM]; |
14302 | ||
6d3d9133 | 14303 | if ((live_regs_mask & (1 << IP_REGNUM)) == (1 << IP_REGNUM)) |
b034930f ILT |
14304 | { |
14305 | /* There are three possible reasons for the IP register | |
14306 | being saved. 1) a stack frame was created, in which case | |
14307 | IP contains the old stack pointer, or 2) an ISR routine | |
14308 | corrupted it, or 3) it was saved to align the stack on | |
14309 | iWMMXt. In case 1, restore IP into SP, otherwise just | |
14310 | restore IP. */ | |
14311 | if (frame_pointer_needed) | |
14312 | { | |
14313 | live_regs_mask &= ~ (1 << IP_REGNUM); | |
14314 | live_regs_mask |= (1 << SP_REGNUM); | |
14315 | } | |
14316 | else | |
e6d29d15 | 14317 | gcc_assert (IS_INTERRUPT (func_type) || TARGET_REALLY_IWMMXT); |
b034930f | 14318 | } |
f3bb6135 | 14319 | |
3a7731fd PB |
14320 | /* On some ARM architectures it is faster to use LDR rather than |
14321 | LDM to load a single register. On other architectures, the | |
14322 | cost is the same. In 26 bit mode, or for exception handlers, | |
14323 | we have to use LDM to load the PC so that the CPSR is also | |
14324 | restored. */ | |
14325 | for (reg = 0; reg <= LAST_ARM_REGNUM; reg++) | |
b279b20a NC |
14326 | if (live_regs_mask == (1U << reg)) |
14327 | break; | |
14328 | ||
3a7731fd PB |
14329 | if (reg <= LAST_ARM_REGNUM |
14330 | && (reg != LR_REGNUM | |
f676971a | 14331 | || ! really_return |
61f0ccff | 14332 | || ! IS_INTERRUPT (func_type))) |
3a7731fd | 14333 | { |
f676971a | 14334 | sprintf (instr, "ldr%s\t%%|%s, [%%|sp], #4", conditional, |
3a7731fd | 14335 | (reg == LR_REGNUM) ? return_reg : reg_names[reg]); |
6d3d9133 | 14336 | } |
ff9940b0 | 14337 | else |
1d5473cb | 14338 | { |
1768c26f PB |
14339 | char *p; |
14340 | int first = 1; | |
6d3d9133 | 14341 | |
699a4925 RE |
14342 | /* Generate the load multiple instruction to restore the |
14343 | registers. Note we can get here, even if | |
14344 | frame_pointer_needed is true, but only if sp already | |
14345 | points to the base of the saved core registers. */ | |
14346 | if (live_regs_mask & (1 << SP_REGNUM)) | |
a72d4945 | 14347 | { |
5848830f PB |
14348 | unsigned HOST_WIDE_INT stack_adjust; |
14349 | ||
5848830f | 14350 | stack_adjust = offsets->outgoing_args - offsets->saved_regs; |
e6d29d15 | 14351 | gcc_assert (stack_adjust == 0 || stack_adjust == 4); |
a72d4945 | 14352 | |
5b3e6663 | 14353 | if (stack_adjust && arm_arch5 && TARGET_ARM) |
c7e9ab97 RR |
14354 | if (TARGET_UNIFIED_ASM) |
14355 | sprintf (instr, "ldmib%s\t%%|sp, {", conditional); | |
14356 | else | |
14357 | sprintf (instr, "ldm%sib\t%%|sp, {", conditional); | |
a72d4945 RE |
14358 | else |
14359 | { | |
b279b20a NC |
14360 | /* If we can't use ldmib (SA110 bug), |
14361 | then try to pop r3 instead. */ | |
a72d4945 RE |
14362 | if (stack_adjust) |
14363 | live_regs_mask |= 1 << 3; | |
c7e9ab97 RR |
14364 | |
14365 | if (TARGET_UNIFIED_ASM) | |
14366 | sprintf (instr, "ldmfd%s\t%%|sp, {", conditional); | |
14367 | else | |
14368 | sprintf (instr, "ldm%sfd\t%%|sp, {", conditional); | |
a72d4945 RE |
14369 | } |
14370 | } | |
da6558fd | 14371 | else |
c7e9ab97 RR |
14372 | if (TARGET_UNIFIED_ASM) |
14373 | sprintf (instr, "pop%s\t{", conditional); | |
14374 | else | |
14375 | sprintf (instr, "ldm%sfd\t%%|sp!, {", conditional); | |
1768c26f PB |
14376 | |
14377 | p = instr + strlen (instr); | |
6d3d9133 | 14378 | |
1768c26f PB |
14379 | for (reg = 0; reg <= SP_REGNUM; reg++) |
14380 | if (live_regs_mask & (1 << reg)) | |
14381 | { | |
14382 | int l = strlen (reg_names[reg]); | |
14383 | ||
14384 | if (first) | |
14385 | first = 0; | |
14386 | else | |
14387 | { | |
14388 | memcpy (p, ", ", 2); | |
14389 | p += 2; | |
14390 | } | |
14391 | ||
14392 | memcpy (p, "%|", 2); | |
14393 | memcpy (p + 2, reg_names[reg], l); | |
14394 | p += l + 2; | |
14395 | } | |
f676971a | 14396 | |
1768c26f PB |
14397 | if (live_regs_mask & (1 << LR_REGNUM)) |
14398 | { | |
b17fe233 | 14399 | sprintf (p, "%s%%|%s}", first ? "" : ", ", return_reg); |
61f0ccff RE |
14400 | /* If returning from an interrupt, restore the CPSR. */ |
14401 | if (IS_INTERRUPT (func_type)) | |
b17fe233 | 14402 | strcat (p, "^"); |
1768c26f PB |
14403 | } |
14404 | else | |
14405 | strcpy (p, "}"); | |
1d5473cb | 14406 | } |
da6558fd | 14407 | |
1768c26f PB |
14408 | output_asm_insn (instr, & operand); |
14409 | ||
3a7731fd PB |
14410 | /* See if we need to generate an extra instruction to |
14411 | perform the actual function return. */ | |
14412 | if (really_return | |
14413 | && func_type != ARM_FT_INTERWORKED | |
14414 | && (live_regs_mask & (1 << LR_REGNUM)) != 0) | |
da6558fd | 14415 | { |
3a7731fd PB |
14416 | /* The return has already been handled |
14417 | by loading the LR into the PC. */ | |
14418 | really_return = 0; | |
da6558fd | 14419 | } |
ff9940b0 | 14420 | } |
e26053d1 | 14421 | |
1768c26f | 14422 | if (really_return) |
ff9940b0 | 14423 | { |
6d3d9133 NC |
14424 | switch ((int) ARM_FUNC_TYPE (func_type)) |
14425 | { | |
14426 | case ARM_FT_ISR: | |
14427 | case ARM_FT_FIQ: | |
5b3e6663 | 14428 | /* ??? This is wrong for unified assembly syntax. */ |
6d3d9133 NC |
14429 | sprintf (instr, "sub%ss\t%%|pc, %%|lr, #4", conditional); |
14430 | break; | |
14431 | ||
14432 | case ARM_FT_INTERWORKED: | |
14433 | sprintf (instr, "bx%s\t%%|lr", conditional); | |
14434 | break; | |
14435 | ||
14436 | case ARM_FT_EXCEPTION: | |
5b3e6663 | 14437 | /* ??? This is wrong for unified assembly syntax. */ |
6d3d9133 NC |
14438 | sprintf (instr, "mov%ss\t%%|pc, %%|lr", conditional); |
14439 | break; | |
14440 | ||
14441 | default: | |
68d560d4 RE |
14442 | /* Use bx if it's available. */ |
14443 | if (arm_arch5 || arm_arch4t) | |
f676971a | 14444 | sprintf (instr, "bx%s\t%%|lr", conditional); |
1768c26f | 14445 | else |
61f0ccff | 14446 | sprintf (instr, "mov%s\t%%|pc, %%|lr", conditional); |
6d3d9133 NC |
14447 | break; |
14448 | } | |
1768c26f PB |
14449 | |
14450 | output_asm_insn (instr, & operand); | |
ff9940b0 | 14451 | } |
f3bb6135 | 14452 | |
ff9940b0 RE |
14453 | return ""; |
14454 | } | |
14455 | ||
ef179a26 NC |
14456 | /* Write the function name into the code section, directly preceding |
14457 | the function prologue. | |
14458 | ||
14459 | Code will be output similar to this: | |
14460 | t0 | |
14461 | .ascii "arm_poke_function_name", 0 | |
14462 | .align | |
14463 | t1 | |
14464 | .word 0xff000000 + (t1 - t0) | |
14465 | arm_poke_function_name | |
14466 | mov ip, sp | |
14467 | stmfd sp!, {fp, ip, lr, pc} | |
14468 | sub fp, ip, #4 | |
14469 | ||
14470 | When performing a stack backtrace, code can inspect the value | |
14471 | of 'pc' stored at 'fp' + 0. If the trace function then looks | |
14472 | at location pc - 12 and the top 8 bits are set, then we know | |
14473 | that there is a function name embedded immediately preceding this | |
14474 | location and has length ((pc[-3]) & 0xff000000). | |
14475 | ||
14476 | We assume that pc is declared as a pointer to an unsigned long. | |
14477 | ||
14478 | It is of no benefit to output the function name if we are assembling | |
14479 | a leaf function. These function types will not contain a stack | |
14480 | backtrace structure, therefore it is not possible to determine the | |
14481 | function name. */ | |
ef179a26 | 14482 | void |
e32bac5b | 14483 | arm_poke_function_name (FILE *stream, const char *name) |
ef179a26 NC |
14484 | { |
14485 | unsigned long alignlength; | |
14486 | unsigned long length; | |
14487 | rtx x; | |
14488 | ||
d5b7b3ae | 14489 | length = strlen (name) + 1; |
0c2ca901 | 14490 | alignlength = ROUND_UP_WORD (length); |
f676971a | 14491 | |
949d79eb | 14492 | ASM_OUTPUT_ASCII (stream, name, length); |
ef179a26 | 14493 | ASM_OUTPUT_ALIGN (stream, 2); |
30cf4896 | 14494 | x = GEN_INT ((unsigned HOST_WIDE_INT) 0xff000000 + alignlength); |
301d03af | 14495 | assemble_aligned_integer (UNITS_PER_WORD, x); |
ef179a26 NC |
14496 | } |
14497 | ||
6d3d9133 NC |
14498 | /* Place some comments into the assembler stream |
14499 | describing the current function. */ | |
08c148a8 | 14500 | static void |
e32bac5b | 14501 | arm_output_function_prologue (FILE *f, HOST_WIDE_INT frame_size) |
cce8749e | 14502 | { |
6d3d9133 | 14503 | unsigned long func_type; |
08c148a8 | 14504 | |
5b3e6663 | 14505 | if (TARGET_THUMB1) |
08c148a8 | 14506 | { |
5b3e6663 | 14507 | thumb1_output_function_prologue (f, frame_size); |
08c148a8 NB |
14508 | return; |
14509 | } | |
f676971a | 14510 | |
6d3d9133 | 14511 | /* Sanity check. */ |
e6d29d15 | 14512 | gcc_assert (!arm_ccfsm_state && !arm_target_insn); |
31fdb4d5 | 14513 | |
6d3d9133 | 14514 | func_type = arm_current_func_type (); |
f676971a | 14515 | |
6d3d9133 NC |
14516 | switch ((int) ARM_FUNC_TYPE (func_type)) |
14517 | { | |
14518 | default: | |
14519 | case ARM_FT_NORMAL: | |
14520 | break; | |
14521 | case ARM_FT_INTERWORKED: | |
14522 | asm_fprintf (f, "\t%@ Function supports interworking.\n"); | |
14523 | break; | |
6d3d9133 NC |
14524 | case ARM_FT_ISR: |
14525 | asm_fprintf (f, "\t%@ Interrupt Service Routine.\n"); | |
14526 | break; | |
14527 | case ARM_FT_FIQ: | |
14528 | asm_fprintf (f, "\t%@ Fast Interrupt Service Routine.\n"); | |
14529 | break; | |
14530 | case ARM_FT_EXCEPTION: | |
14531 | asm_fprintf (f, "\t%@ ARM Exception Handler.\n"); | |
14532 | break; | |
14533 | } | |
f676971a | 14534 | |
6d3d9133 NC |
14535 | if (IS_NAKED (func_type)) |
14536 | asm_fprintf (f, "\t%@ Naked Function: prologue and epilogue provided by programmer.\n"); | |
14537 | ||
14538 | if (IS_VOLATILE (func_type)) | |
14539 | asm_fprintf (f, "\t%@ Volatile: function does not return.\n"); | |
14540 | ||
14541 | if (IS_NESTED (func_type)) | |
14542 | asm_fprintf (f, "\t%@ Nested: function declared inside another function.\n"); | |
5b3e6663 PB |
14543 | if (IS_STACKALIGN (func_type)) |
14544 | asm_fprintf (f, "\t%@ Stack Align: May be called with mis-aligned SP.\n"); | |
f676971a | 14545 | |
c53dddc2 | 14546 | asm_fprintf (f, "\t%@ args = %d, pretend = %d, frame = %wd\n", |
38173d38 JH |
14547 | crtl->args.size, |
14548 | crtl->args.pretend_args_size, frame_size); | |
6d3d9133 | 14549 | |
3cb66fd7 | 14550 | asm_fprintf (f, "\t%@ frame_needed = %d, uses_anonymous_args = %d\n", |
dd18ae56 | 14551 | frame_pointer_needed, |
3cb66fd7 | 14552 | cfun->machine->uses_anonymous_args); |
cce8749e | 14553 | |
6f7ebcbb NC |
14554 | if (cfun->machine->lr_save_eliminated) |
14555 | asm_fprintf (f, "\t%@ link register save eliminated.\n"); | |
14556 | ||
e3b5732b | 14557 | if (crtl->calls_eh_return) |
c9ca9b88 PB |
14558 | asm_fprintf (f, "\t@ Calls __builtin_eh_return.\n"); |
14559 | ||
f3bb6135 | 14560 | } |
cce8749e | 14561 | |
cd2b33d0 | 14562 | const char * |
a72d4945 | 14563 | arm_output_epilogue (rtx sibling) |
cce8749e | 14564 | { |
949d79eb | 14565 | int reg; |
6f7ebcbb | 14566 | unsigned long saved_regs_mask; |
6d3d9133 | 14567 | unsigned long func_type; |
f676971a | 14568 | /* Floats_offset is the offset from the "virtual" frame. In an APCS |
c882c7ac RE |
14569 | frame that is $fp + 4 for a non-variadic function. */ |
14570 | int floats_offset = 0; | |
cce8749e | 14571 | rtx operands[3]; |
d5b7b3ae | 14572 | FILE * f = asm_out_file; |
5a9335ef | 14573 | unsigned int lrm_count = 0; |
a72d4945 | 14574 | int really_return = (sibling == NULL); |
9b66ebb1 | 14575 | int start_reg; |
5848830f | 14576 | arm_stack_offsets *offsets; |
cce8749e | 14577 | |
6d3d9133 NC |
14578 | /* If we have already generated the return instruction |
14579 | then it is futile to generate anything else. */ | |
934c2060 RR |
14580 | if (use_return_insn (FALSE, sibling) && |
14581 | (cfun->machine->return_used_this_function != 0)) | |
949d79eb | 14582 | return ""; |
cce8749e | 14583 | |
6d3d9133 | 14584 | func_type = arm_current_func_type (); |
d5b7b3ae | 14585 | |
6d3d9133 NC |
14586 | if (IS_NAKED (func_type)) |
14587 | /* Naked functions don't have epilogues. */ | |
14588 | return ""; | |
0616531f | 14589 | |
6d3d9133 | 14590 | if (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN) |
e2c671ba | 14591 | { |
86efdc8e | 14592 | rtx op; |
f676971a | 14593 | |
6d3d9133 | 14594 | /* A volatile function should never return. Call abort. */ |
ed0e6530 | 14595 | op = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)" : "abort"); |
2b835d68 | 14596 | assemble_external_libcall (op); |
e2c671ba | 14597 | output_asm_insn ("bl\t%a0", &op); |
f676971a | 14598 | |
949d79eb | 14599 | return ""; |
e2c671ba RE |
14600 | } |
14601 | ||
e6d29d15 NS |
14602 | /* If we are throwing an exception, then we really must be doing a |
14603 | return, so we can't tail-call. */ | |
e3b5732b | 14604 | gcc_assert (!crtl->calls_eh_return || really_return); |
f676971a | 14605 | |
5848830f | 14606 | offsets = arm_get_frame_offsets (); |
954954d1 | 14607 | saved_regs_mask = offsets->saved_regs_mask; |
5a9335ef NC |
14608 | |
14609 | if (TARGET_IWMMXT) | |
14610 | lrm_count = bit_count (saved_regs_mask); | |
14611 | ||
5848830f | 14612 | floats_offset = offsets->saved_args; |
6d3d9133 | 14613 | /* Compute how far away the floats will be. */ |
5a9335ef | 14614 | for (reg = 0; reg <= LAST_ARM_REGNUM; reg++) |
6f7ebcbb | 14615 | if (saved_regs_mask & (1 << reg)) |
6ed30148 | 14616 | floats_offset += 4; |
f676971a | 14617 | |
ec6237e4 | 14618 | if (TARGET_APCS_FRAME && frame_pointer_needed && TARGET_ARM) |
cce8749e | 14619 | { |
9b66ebb1 | 14620 | /* This variable is for the Virtual Frame Pointer, not VFP regs. */ |
5848830f | 14621 | int vfp_offset = offsets->frame; |
c882c7ac | 14622 | |
d79f3032 | 14623 | if (TARGET_FPA_EMU2) |
b111229a | 14624 | { |
9b66ebb1 | 14625 | for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--) |
6fb5fa3c | 14626 | if (df_regs_ever_live_p (reg) && !call_used_regs[reg]) |
b111229a RE |
14627 | { |
14628 | floats_offset += 12; | |
f676971a | 14629 | asm_fprintf (f, "\tldfe\t%r, [%r, #-%d]\n", |
c882c7ac | 14630 | reg, FP_REGNUM, floats_offset - vfp_offset); |
b111229a RE |
14631 | } |
14632 | } | |
14633 | else | |
14634 | { | |
9b66ebb1 | 14635 | start_reg = LAST_FPA_REGNUM; |
b111229a | 14636 | |
9b66ebb1 | 14637 | for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--) |
b111229a | 14638 | { |
6fb5fa3c | 14639 | if (df_regs_ever_live_p (reg) && !call_used_regs[reg]) |
b111229a RE |
14640 | { |
14641 | floats_offset += 12; | |
f676971a | 14642 | |
6354dc9b | 14643 | /* We can't unstack more than four registers at once. */ |
b111229a RE |
14644 | if (start_reg - reg == 3) |
14645 | { | |
dd18ae56 | 14646 | asm_fprintf (f, "\tlfm\t%r, 4, [%r, #-%d]\n", |
c882c7ac | 14647 | reg, FP_REGNUM, floats_offset - vfp_offset); |
b111229a RE |
14648 | start_reg = reg - 1; |
14649 | } | |
14650 | } | |
14651 | else | |
14652 | { | |
14653 | if (reg != start_reg) | |
dd18ae56 NC |
14654 | asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n", |
14655 | reg + 1, start_reg - reg, | |
c882c7ac | 14656 | FP_REGNUM, floats_offset - vfp_offset); |
b111229a RE |
14657 | start_reg = reg - 1; |
14658 | } | |
14659 | } | |
14660 | ||
14661 | /* Just in case the last register checked also needs unstacking. */ | |
14662 | if (reg != start_reg) | |
dd18ae56 NC |
14663 | asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n", |
14664 | reg + 1, start_reg - reg, | |
c882c7ac | 14665 | FP_REGNUM, floats_offset - vfp_offset); |
b111229a | 14666 | } |
6d3d9133 | 14667 | |
9b66ebb1 PB |
14668 | if (TARGET_HARD_FLOAT && TARGET_VFP) |
14669 | { | |
9728c9d1 | 14670 | int saved_size; |
9b66ebb1 | 14671 | |
8edfc4cc MS |
14672 | /* The fldmd insns do not have base+offset addressing |
14673 | modes, so we use IP to hold the address. */ | |
9728c9d1 | 14674 | saved_size = arm_get_vfp_saved_size (); |
9b66ebb1 | 14675 | |
9728c9d1 | 14676 | if (saved_size > 0) |
9b66ebb1 | 14677 | { |
9728c9d1 | 14678 | floats_offset += saved_size; |
9b66ebb1 PB |
14679 | asm_fprintf (f, "\tsub\t%r, %r, #%d\n", IP_REGNUM, |
14680 | FP_REGNUM, floats_offset - vfp_offset); | |
14681 | } | |
14682 | start_reg = FIRST_VFP_REGNUM; | |
14683 | for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2) | |
14684 | { | |
6fb5fa3c DB |
14685 | if ((!df_regs_ever_live_p (reg) || call_used_regs[reg]) |
14686 | && (!df_regs_ever_live_p (reg + 1) || call_used_regs[reg + 1])) | |
9b66ebb1 PB |
14687 | { |
14688 | if (start_reg != reg) | |
8edfc4cc | 14689 | vfp_output_fldmd (f, IP_REGNUM, |
9728c9d1 PB |
14690 | (start_reg - FIRST_VFP_REGNUM) / 2, |
14691 | (reg - start_reg) / 2); | |
9b66ebb1 PB |
14692 | start_reg = reg + 2; |
14693 | } | |
14694 | } | |
14695 | if (start_reg != reg) | |
8edfc4cc | 14696 | vfp_output_fldmd (f, IP_REGNUM, |
9728c9d1 PB |
14697 | (start_reg - FIRST_VFP_REGNUM) / 2, |
14698 | (reg - start_reg) / 2); | |
9b66ebb1 PB |
14699 | } |
14700 | ||
5a9335ef NC |
14701 | if (TARGET_IWMMXT) |
14702 | { | |
14703 | /* The frame pointer is guaranteed to be non-double-word aligned. | |
14704 | This is because it is set to (old_stack_pointer - 4) and the | |
14705 | old_stack_pointer was double word aligned. Thus the offset to | |
14706 | the iWMMXt registers to be loaded must also be non-double-word | |
14707 | sized, so that the resultant address *is* double-word aligned. | |
14708 | We can ignore floats_offset since that was already included in | |
14709 | the live_regs_mask. */ | |
14710 | lrm_count += (lrm_count % 2 ? 2 : 1); | |
f676971a | 14711 | |
01d4c813 | 14712 | for (reg = LAST_IWMMXT_REGNUM; reg >= FIRST_IWMMXT_REGNUM; reg--) |
6fb5fa3c | 14713 | if (df_regs_ever_live_p (reg) && !call_used_regs[reg]) |
5a9335ef | 14714 | { |
f676971a | 14715 | asm_fprintf (f, "\twldrd\t%r, [%r, #-%d]\n", |
5a9335ef | 14716 | reg, FP_REGNUM, lrm_count * 4); |
f676971a | 14717 | lrm_count += 2; |
5a9335ef NC |
14718 | } |
14719 | } | |
14720 | ||
6f7ebcbb | 14721 | /* saved_regs_mask should contain the IP, which at the time of stack |
6d3d9133 NC |
14722 | frame generation actually contains the old stack pointer. So a |
14723 | quick way to unwind the stack is just pop the IP register directly | |
14724 | into the stack pointer. */ | |
e6d29d15 | 14725 | gcc_assert (saved_regs_mask & (1 << IP_REGNUM)); |
6f7ebcbb NC |
14726 | saved_regs_mask &= ~ (1 << IP_REGNUM); |
14727 | saved_regs_mask |= (1 << SP_REGNUM); | |
6d3d9133 | 14728 | |
6f7ebcbb | 14729 | /* There are two registers left in saved_regs_mask - LR and PC. We |
6d3d9133 NC |
14730 | only need to restore the LR register (the return address), but to |
14731 | save time we can load it directly into the PC, unless we need a | |
14732 | special function exit sequence, or we are not really returning. */ | |
c9ca9b88 PB |
14733 | if (really_return |
14734 | && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL | |
e3b5732b | 14735 | && !crtl->calls_eh_return) |
6d3d9133 NC |
14736 | /* Delete the LR from the register mask, so that the LR on |
14737 | the stack is loaded into the PC in the register mask. */ | |
6f7ebcbb | 14738 | saved_regs_mask &= ~ (1 << LR_REGNUM); |
b111229a | 14739 | else |
6f7ebcbb | 14740 | saved_regs_mask &= ~ (1 << PC_REGNUM); |
efc2515b RE |
14741 | |
14742 | /* We must use SP as the base register, because SP is one of the | |
14743 | registers being restored. If an interrupt or page fault | |
14744 | happens in the ldm instruction, the SP might or might not | |
14745 | have been restored. That would be bad, as then SP will no | |
14746 | longer indicate the safe area of stack, and we can get stack | |
14747 | corruption. Using SP as the base register means that it will | |
14748 | be reset correctly to the original value, should an interrupt | |
699a4925 RE |
14749 | occur. If the stack pointer already points at the right |
14750 | place, then omit the subtraction. */ | |
5848830f | 14751 | if (offsets->outgoing_args != (1 + (int) bit_count (saved_regs_mask)) |
e3b5732b | 14752 | || cfun->calls_alloca) |
699a4925 RE |
14753 | asm_fprintf (f, "\tsub\t%r, %r, #%d\n", SP_REGNUM, FP_REGNUM, |
14754 | 4 * bit_count (saved_regs_mask)); | |
a15908a4 | 14755 | print_multi_reg (f, "ldmfd\t%r, ", SP_REGNUM, saved_regs_mask, 0); |
7b8b8ade NC |
14756 | |
14757 | if (IS_INTERRUPT (func_type)) | |
14758 | /* Interrupt handlers will have pushed the | |
14759 | IP onto the stack, so restore it now. */ | |
a15908a4 | 14760 | print_multi_reg (f, "ldmfd\t%r!, ", SP_REGNUM, 1 << IP_REGNUM, 0); |
cce8749e CH |
14761 | } |
14762 | else | |
14763 | { | |
ec6237e4 PB |
14764 | /* This branch is executed for ARM mode (non-apcs frames) and |
14765 | Thumb-2 mode. Frame layout is essentially the same for those | |
14766 | cases, except that in ARM mode frame pointer points to the | |
14767 | first saved register, while in Thumb-2 mode the frame pointer points | |
14768 | to the last saved register. | |
14769 | ||
14770 | It is possible to make frame pointer point to last saved | |
14771 | register in both cases, and remove some conditionals below. | |
14772 | That means that fp setup in prologue would be just "mov fp, sp" | |
14773 | and sp restore in epilogue would be just "mov sp, fp", whereas | |
14774 | now we have to use add/sub in those cases. However, the value | |
14775 | of that would be marginal, as both mov and add/sub are 32-bit | |
14776 | in ARM mode, and it would require extra conditionals | |
14777 | in arm_expand_prologue to distingish ARM-apcs-frame case | |
14778 | (where frame pointer is required to point at first register) | |
14779 | and ARM-non-apcs-frame. Therefore, such change is postponed | |
14780 | until real need arise. */ | |
f0b4bdd5 | 14781 | unsigned HOST_WIDE_INT amount; |
a15908a4 | 14782 | int rfe; |
d2288d8d | 14783 | /* Restore stack pointer if necessary. */ |
ec6237e4 | 14784 | if (TARGET_ARM && frame_pointer_needed) |
5b3e6663 PB |
14785 | { |
14786 | operands[0] = stack_pointer_rtx; | |
ec6237e4 PB |
14787 | operands[1] = hard_frame_pointer_rtx; |
14788 | ||
14789 | operands[2] = GEN_INT (offsets->frame - offsets->saved_regs); | |
14790 | output_add_immediate (operands); | |
5b3e6663 | 14791 | } |
ec6237e4 | 14792 | else |
5b3e6663 | 14793 | { |
ec6237e4 PB |
14794 | if (frame_pointer_needed) |
14795 | { | |
14796 | /* For Thumb-2 restore sp from the frame pointer. | |
14797 | Operand restrictions mean we have to incrememnt FP, then copy | |
14798 | to SP. */ | |
14799 | amount = offsets->locals_base - offsets->saved_regs; | |
14800 | operands[0] = hard_frame_pointer_rtx; | |
14801 | } | |
14802 | else | |
14803 | { | |
954954d1 | 14804 | unsigned long count; |
ec6237e4 PB |
14805 | operands[0] = stack_pointer_rtx; |
14806 | amount = offsets->outgoing_args - offsets->saved_regs; | |
954954d1 PB |
14807 | /* pop call clobbered registers if it avoids a |
14808 | separate stack adjustment. */ | |
14809 | count = offsets->saved_regs - offsets->saved_args; | |
14810 | if (optimize_size | |
14811 | && count != 0 | |
e3b5732b | 14812 | && !crtl->calls_eh_return |
954954d1 PB |
14813 | && bit_count(saved_regs_mask) * 4 == count |
14814 | && !IS_INTERRUPT (func_type) | |
e3b5732b | 14815 | && !crtl->tail_call_emit) |
954954d1 PB |
14816 | { |
14817 | unsigned long mask; | |
c92f1823 IB |
14818 | /* Preserve return values, of any size. */ |
14819 | mask = (1 << ((arm_size_return_regs() + 3) / 4)) - 1; | |
954954d1 PB |
14820 | mask ^= 0xf; |
14821 | mask &= ~saved_regs_mask; | |
14822 | reg = 0; | |
14823 | while (bit_count (mask) * 4 > amount) | |
14824 | { | |
14825 | while ((mask & (1 << reg)) == 0) | |
14826 | reg++; | |
14827 | mask &= ~(1 << reg); | |
14828 | } | |
14829 | if (bit_count (mask) * 4 == amount) { | |
14830 | amount = 0; | |
14831 | saved_regs_mask |= mask; | |
14832 | } | |
14833 | } | |
ec6237e4 PB |
14834 | } |
14835 | ||
14836 | if (amount) | |
14837 | { | |
14838 | operands[1] = operands[0]; | |
14839 | operands[2] = GEN_INT (amount); | |
14840 | output_add_immediate (operands); | |
14841 | } | |
14842 | if (frame_pointer_needed) | |
14843 | asm_fprintf (f, "\tmov\t%r, %r\n", | |
14844 | SP_REGNUM, HARD_FRAME_POINTER_REGNUM); | |
d2288d8d TG |
14845 | } |
14846 | ||
d79f3032 | 14847 | if (TARGET_FPA_EMU2) |
b111229a | 14848 | { |
9b66ebb1 | 14849 | for (reg = FIRST_FPA_REGNUM; reg <= LAST_FPA_REGNUM; reg++) |
6fb5fa3c | 14850 | if (df_regs_ever_live_p (reg) && !call_used_regs[reg]) |
dd18ae56 NC |
14851 | asm_fprintf (f, "\tldfe\t%r, [%r], #12\n", |
14852 | reg, SP_REGNUM); | |
b111229a RE |
14853 | } |
14854 | else | |
14855 | { | |
9b66ebb1 | 14856 | start_reg = FIRST_FPA_REGNUM; |
b111229a | 14857 | |
9b66ebb1 | 14858 | for (reg = FIRST_FPA_REGNUM; reg <= LAST_FPA_REGNUM; reg++) |
b111229a | 14859 | { |
6fb5fa3c | 14860 | if (df_regs_ever_live_p (reg) && !call_used_regs[reg]) |
b111229a RE |
14861 | { |
14862 | if (reg - start_reg == 3) | |
14863 | { | |
dd18ae56 NC |
14864 | asm_fprintf (f, "\tlfmfd\t%r, 4, [%r]!\n", |
14865 | start_reg, SP_REGNUM); | |
b111229a RE |
14866 | start_reg = reg + 1; |
14867 | } | |
14868 | } | |
14869 | else | |
14870 | { | |
14871 | if (reg != start_reg) | |
dd18ae56 NC |
14872 | asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n", |
14873 | start_reg, reg - start_reg, | |
14874 | SP_REGNUM); | |
f676971a | 14875 | |
b111229a RE |
14876 | start_reg = reg + 1; |
14877 | } | |
14878 | } | |
14879 | ||
14880 | /* Just in case the last register checked also needs unstacking. */ | |
14881 | if (reg != start_reg) | |
dd18ae56 NC |
14882 | asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n", |
14883 | start_reg, reg - start_reg, SP_REGNUM); | |
b111229a RE |
14884 | } |
14885 | ||
9b66ebb1 PB |
14886 | if (TARGET_HARD_FLOAT && TARGET_VFP) |
14887 | { | |
f8b68ed3 RE |
14888 | int end_reg = LAST_VFP_REGNUM + 1; |
14889 | ||
14890 | /* Scan the registers in reverse order. We need to match | |
14891 | any groupings made in the prologue and generate matching | |
14892 | pop operations. */ | |
14893 | for (reg = LAST_VFP_REGNUM - 1; reg >= FIRST_VFP_REGNUM; reg -= 2) | |
9b66ebb1 | 14894 | { |
6fb5fa3c | 14895 | if ((!df_regs_ever_live_p (reg) || call_used_regs[reg]) |
f8b68ed3 RE |
14896 | && (!df_regs_ever_live_p (reg + 1) |
14897 | || call_used_regs[reg + 1])) | |
9b66ebb1 | 14898 | { |
f8b68ed3 | 14899 | if (end_reg > reg + 2) |
8edfc4cc | 14900 | vfp_output_fldmd (f, SP_REGNUM, |
f8b68ed3 RE |
14901 | (reg + 2 - FIRST_VFP_REGNUM) / 2, |
14902 | (end_reg - (reg + 2)) / 2); | |
14903 | end_reg = reg; | |
9b66ebb1 PB |
14904 | } |
14905 | } | |
f8b68ed3 RE |
14906 | if (end_reg > reg + 2) |
14907 | vfp_output_fldmd (f, SP_REGNUM, 0, | |
14908 | (end_reg - (reg + 2)) / 2); | |
9b66ebb1 | 14909 | } |
f8b68ed3 | 14910 | |
5a9335ef NC |
14911 | if (TARGET_IWMMXT) |
14912 | for (reg = FIRST_IWMMXT_REGNUM; reg <= LAST_IWMMXT_REGNUM; reg++) | |
6fb5fa3c | 14913 | if (df_regs_ever_live_p (reg) && !call_used_regs[reg]) |
01d4c813 | 14914 | asm_fprintf (f, "\twldrd\t%r, [%r], #8\n", reg, SP_REGNUM); |
5a9335ef | 14915 | |
6d3d9133 | 14916 | /* If we can, restore the LR into the PC. */ |
a15908a4 PB |
14917 | if (ARM_FUNC_TYPE (func_type) != ARM_FT_INTERWORKED |
14918 | && (TARGET_ARM || ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL) | |
5b3e6663 | 14919 | && !IS_STACKALIGN (func_type) |
6d3d9133 | 14920 | && really_return |
38173d38 | 14921 | && crtl->args.pretend_args_size == 0 |
c9ca9b88 | 14922 | && saved_regs_mask & (1 << LR_REGNUM) |
e3b5732b | 14923 | && !crtl->calls_eh_return) |
cce8749e | 14924 | { |
6f7ebcbb NC |
14925 | saved_regs_mask &= ~ (1 << LR_REGNUM); |
14926 | saved_regs_mask |= (1 << PC_REGNUM); | |
a15908a4 | 14927 | rfe = IS_INTERRUPT (func_type); |
6d3d9133 | 14928 | } |
a15908a4 PB |
14929 | else |
14930 | rfe = 0; | |
d5b7b3ae | 14931 | |
6d3d9133 | 14932 | /* Load the registers off the stack. If we only have one register |
5b3e6663 PB |
14933 | to load use the LDR instruction - it is faster. For Thumb-2 |
14934 | always use pop and the assembler will pick the best instruction.*/ | |
a15908a4 PB |
14935 | if (TARGET_ARM && saved_regs_mask == (1 << LR_REGNUM) |
14936 | && !IS_INTERRUPT(func_type)) | |
6d3d9133 | 14937 | { |
c9ca9b88 | 14938 | asm_fprintf (f, "\tldr\t%r, [%r], #4\n", LR_REGNUM, SP_REGNUM); |
cce8749e | 14939 | } |
6f7ebcbb | 14940 | else if (saved_regs_mask) |
f1acdf8b NC |
14941 | { |
14942 | if (saved_regs_mask & (1 << SP_REGNUM)) | |
14943 | /* Note - write back to the stack register is not enabled | |
112cdef5 | 14944 | (i.e. "ldmfd sp!..."). We know that the stack pointer is |
f1acdf8b NC |
14945 | in the list of registers and if we add writeback the |
14946 | instruction becomes UNPREDICTABLE. */ | |
a15908a4 PB |
14947 | print_multi_reg (f, "ldmfd\t%r, ", SP_REGNUM, saved_regs_mask, |
14948 | rfe); | |
5b3e6663 | 14949 | else if (TARGET_ARM) |
a15908a4 PB |
14950 | print_multi_reg (f, "ldmfd\t%r!, ", SP_REGNUM, saved_regs_mask, |
14951 | rfe); | |
f1acdf8b | 14952 | else |
a15908a4 | 14953 | print_multi_reg (f, "pop\t", SP_REGNUM, saved_regs_mask, 0); |
f1acdf8b | 14954 | } |
6d3d9133 | 14955 | |
38173d38 | 14956 | if (crtl->args.pretend_args_size) |
cce8749e | 14957 | { |
6d3d9133 NC |
14958 | /* Unwind the pre-pushed regs. */ |
14959 | operands[0] = operands[1] = stack_pointer_rtx; | |
38173d38 | 14960 | operands[2] = GEN_INT (crtl->args.pretend_args_size); |
6d3d9133 NC |
14961 | output_add_immediate (operands); |
14962 | } | |
14963 | } | |
32de079a | 14964 | |
2966b00e | 14965 | /* We may have already restored PC directly from the stack. */ |
0cc3dda8 | 14966 | if (!really_return || saved_regs_mask & (1 << PC_REGNUM)) |
6d3d9133 | 14967 | return ""; |
d5b7b3ae | 14968 | |
c9ca9b88 | 14969 | /* Stack adjustment for exception handler. */ |
e3b5732b | 14970 | if (crtl->calls_eh_return) |
f676971a | 14971 | asm_fprintf (f, "\tadd\t%r, %r, %r\n", SP_REGNUM, SP_REGNUM, |
c9ca9b88 PB |
14972 | ARM_EH_STACKADJ_REGNUM); |
14973 | ||
6d3d9133 NC |
14974 | /* Generate the return instruction. */ |
14975 | switch ((int) ARM_FUNC_TYPE (func_type)) | |
14976 | { | |
6d3d9133 NC |
14977 | case ARM_FT_ISR: |
14978 | case ARM_FT_FIQ: | |
14979 | asm_fprintf (f, "\tsubs\t%r, %r, #4\n", PC_REGNUM, LR_REGNUM); | |
14980 | break; | |
14981 | ||
14982 | case ARM_FT_EXCEPTION: | |
14983 | asm_fprintf (f, "\tmovs\t%r, %r\n", PC_REGNUM, LR_REGNUM); | |
14984 | break; | |
14985 | ||
14986 | case ARM_FT_INTERWORKED: | |
14987 | asm_fprintf (f, "\tbx\t%r\n", LR_REGNUM); | |
14988 | break; | |
14989 | ||
14990 | default: | |
5b3e6663 PB |
14991 | if (IS_STACKALIGN (func_type)) |
14992 | { | |
14993 | /* See comment in arm_expand_prologue. */ | |
14994 | asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, 0); | |
14995 | } | |
68d560d4 RE |
14996 | if (arm_arch5 || arm_arch4t) |
14997 | asm_fprintf (f, "\tbx\t%r\n", LR_REGNUM); | |
14998 | else | |
14999 | asm_fprintf (f, "\tmov\t%r, %r\n", PC_REGNUM, LR_REGNUM); | |
6d3d9133 | 15000 | break; |
cce8749e | 15001 | } |
f3bb6135 | 15002 | |
949d79eb RE |
15003 | return ""; |
15004 | } | |
15005 | ||
08c148a8 | 15006 | static void |
e32bac5b | 15007 | arm_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED, |
5848830f | 15008 | HOST_WIDE_INT frame_size ATTRIBUTE_UNUSED) |
949d79eb | 15009 | { |
5848830f PB |
15010 | arm_stack_offsets *offsets; |
15011 | ||
5b3e6663 | 15012 | if (TARGET_THUMB1) |
d5b7b3ae | 15013 | { |
b12a00f1 RE |
15014 | int regno; |
15015 | ||
15016 | /* Emit any call-via-reg trampolines that are needed for v4t support | |
15017 | of call_reg and call_value_reg type insns. */ | |
57ecec57 | 15018 | for (regno = 0; regno < LR_REGNUM; regno++) |
b12a00f1 RE |
15019 | { |
15020 | rtx label = cfun->machine->call_via[regno]; | |
15021 | ||
15022 | if (label != NULL) | |
15023 | { | |
d6b5193b | 15024 | switch_to_section (function_section (current_function_decl)); |
b12a00f1 RE |
15025 | targetm.asm_out.internal_label (asm_out_file, "L", |
15026 | CODE_LABEL_NUMBER (label)); | |
15027 | asm_fprintf (asm_out_file, "\tbx\t%r\n", regno); | |
15028 | } | |
15029 | } | |
15030 | ||
d5b7b3ae RE |
15031 | /* ??? Probably not safe to set this here, since it assumes that a |
15032 | function will be emitted as assembly immediately after we generate | |
15033 | RTL for it. This does not happen for inline functions. */ | |
934c2060 | 15034 | cfun->machine->return_used_this_function = 0; |
d5b7b3ae | 15035 | } |
5b3e6663 | 15036 | else /* TARGET_32BIT */ |
d5b7b3ae | 15037 | { |
0977774b | 15038 | /* We need to take into account any stack-frame rounding. */ |
5848830f | 15039 | offsets = arm_get_frame_offsets (); |
0977774b | 15040 | |
e6d29d15 | 15041 | gcc_assert (!use_return_insn (FALSE, NULL) |
934c2060 | 15042 | || (cfun->machine->return_used_this_function != 0) |
e6d29d15 NS |
15043 | || offsets->saved_regs == offsets->outgoing_args |
15044 | || frame_pointer_needed); | |
f3bb6135 | 15045 | |
d5b7b3ae | 15046 | /* Reset the ARM-specific per-function variables. */ |
d5b7b3ae RE |
15047 | after_arm_reorg = 0; |
15048 | } | |
f3bb6135 | 15049 | } |
e2c671ba | 15050 | |
2c849145 JM |
15051 | /* Generate and emit an insn that we will recognize as a push_multi. |
15052 | Unfortunately, since this insn does not reflect very well the actual | |
15053 | semantics of the operation, we need to annotate the insn for the benefit | |
15054 | of DWARF2 frame unwind information. */ | |
2c849145 | 15055 | static rtx |
b279b20a | 15056 | emit_multi_reg_push (unsigned long mask) |
e2c671ba RE |
15057 | { |
15058 | int num_regs = 0; | |
9b598fa0 | 15059 | int num_dwarf_regs; |
e2c671ba RE |
15060 | int i, j; |
15061 | rtx par; | |
2c849145 | 15062 | rtx dwarf; |
87e27392 | 15063 | int dwarf_par_index; |
2c849145 | 15064 | rtx tmp, reg; |
e2c671ba | 15065 | |
d5b7b3ae | 15066 | for (i = 0; i <= LAST_ARM_REGNUM; i++) |
e2c671ba | 15067 | if (mask & (1 << i)) |
5895f793 | 15068 | num_regs++; |
e2c671ba | 15069 | |
e6d29d15 | 15070 | gcc_assert (num_regs && num_regs <= 16); |
e2c671ba | 15071 | |
9b598fa0 RE |
15072 | /* We don't record the PC in the dwarf frame information. */ |
15073 | num_dwarf_regs = num_regs; | |
15074 | if (mask & (1 << PC_REGNUM)) | |
15075 | num_dwarf_regs--; | |
15076 | ||
87e27392 | 15077 | /* For the body of the insn we are going to generate an UNSPEC in |
05713b80 | 15078 | parallel with several USEs. This allows the insn to be recognized |
9abf5d7b RR |
15079 | by the push_multi pattern in the arm.md file. |
15080 | ||
15081 | The body of the insn looks something like this: | |
87e27392 | 15082 | |
f676971a | 15083 | (parallel [ |
9abf5d7b RR |
15084 | (set (mem:BLK (pre_modify:SI (reg:SI sp) |
15085 | (const_int:SI <num>))) | |
b15bca31 | 15086 | (unspec:BLK [(reg:SI r4)] UNSPEC_PUSH_MULT)) |
9abf5d7b RR |
15087 | (use (reg:SI XX)) |
15088 | (use (reg:SI YY)) | |
15089 | ... | |
87e27392 NC |
15090 | ]) |
15091 | ||
15092 | For the frame note however, we try to be more explicit and actually | |
15093 | show each register being stored into the stack frame, plus a (single) | |
15094 | decrement of the stack pointer. We do it this way in order to be | |
15095 | friendly to the stack unwinding code, which only wants to see a single | |
15096 | stack decrement per instruction. The RTL we generate for the note looks | |
15097 | something like this: | |
15098 | ||
f676971a | 15099 | (sequence [ |
87e27392 NC |
15100 | (set (reg:SI sp) (plus:SI (reg:SI sp) (const_int -20))) |
15101 | (set (mem:SI (reg:SI sp)) (reg:SI r4)) | |
9abf5d7b RR |
15102 | (set (mem:SI (plus:SI (reg:SI sp) (const_int 4))) (reg:SI XX)) |
15103 | (set (mem:SI (plus:SI (reg:SI sp) (const_int 8))) (reg:SI YY)) | |
15104 | ... | |
87e27392 NC |
15105 | ]) |
15106 | ||
9abf5d7b RR |
15107 | FIXME:: In an ideal world the PRE_MODIFY would not exist and |
15108 | instead we'd have a parallel expression detailing all | |
15109 | the stores to the various memory addresses so that debug | |
15110 | information is more up-to-date. Remember however while writing | |
15111 | this to take care of the constraints with the push instruction. | |
15112 | ||
15113 | Note also that this has to be taken care of for the VFP registers. | |
15114 | ||
15115 | For more see PR43399. */ | |
f676971a | 15116 | |
43cffd11 | 15117 | par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (num_regs)); |
9b598fa0 | 15118 | dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (num_dwarf_regs + 1)); |
87e27392 | 15119 | dwarf_par_index = 1; |
e2c671ba | 15120 | |
d5b7b3ae | 15121 | for (i = 0; i <= LAST_ARM_REGNUM; i++) |
e2c671ba RE |
15122 | { |
15123 | if (mask & (1 << i)) | |
15124 | { | |
2c849145 JM |
15125 | reg = gen_rtx_REG (SImode, i); |
15126 | ||
e2c671ba | 15127 | XVECEXP (par, 0, 0) |
43cffd11 | 15128 | = gen_rtx_SET (VOIDmode, |
9abf5d7b RR |
15129 | gen_frame_mem |
15130 | (BLKmode, | |
15131 | gen_rtx_PRE_MODIFY (Pmode, | |
15132 | stack_pointer_rtx, | |
15133 | plus_constant | |
15134 | (stack_pointer_rtx, | |
15135 | -4 * num_regs)) | |
15136 | ), | |
43cffd11 | 15137 | gen_rtx_UNSPEC (BLKmode, |
2c849145 | 15138 | gen_rtvec (1, reg), |
9b598fa0 | 15139 | UNSPEC_PUSH_MULT)); |
2c849145 | 15140 | |
9b598fa0 RE |
15141 | if (i != PC_REGNUM) |
15142 | { | |
15143 | tmp = gen_rtx_SET (VOIDmode, | |
31fa16b6 | 15144 | gen_frame_mem (SImode, stack_pointer_rtx), |
9b598fa0 RE |
15145 | reg); |
15146 | RTX_FRAME_RELATED_P (tmp) = 1; | |
15147 | XVECEXP (dwarf, 0, dwarf_par_index) = tmp; | |
15148 | dwarf_par_index++; | |
15149 | } | |
2c849145 | 15150 | |
e2c671ba RE |
15151 | break; |
15152 | } | |
15153 | } | |
15154 | ||
15155 | for (j = 1, i++; j < num_regs; i++) | |
15156 | { | |
15157 | if (mask & (1 << i)) | |
15158 | { | |
2c849145 JM |
15159 | reg = gen_rtx_REG (SImode, i); |
15160 | ||
15161 | XVECEXP (par, 0, j) = gen_rtx_USE (VOIDmode, reg); | |
15162 | ||
9b598fa0 RE |
15163 | if (i != PC_REGNUM) |
15164 | { | |
31fa16b6 RE |
15165 | tmp |
15166 | = gen_rtx_SET (VOIDmode, | |
9abf5d7b RR |
15167 | gen_frame_mem |
15168 | (SImode, | |
15169 | plus_constant (stack_pointer_rtx, | |
15170 | 4 * j)), | |
31fa16b6 | 15171 | reg); |
9b598fa0 RE |
15172 | RTX_FRAME_RELATED_P (tmp) = 1; |
15173 | XVECEXP (dwarf, 0, dwarf_par_index++) = tmp; | |
15174 | } | |
15175 | ||
e2c671ba RE |
15176 | j++; |
15177 | } | |
15178 | } | |
b111229a | 15179 | |
2c849145 | 15180 | par = emit_insn (par); |
f676971a | 15181 | |
d66437c5 | 15182 | tmp = gen_rtx_SET (VOIDmode, |
87e27392 | 15183 | stack_pointer_rtx, |
d66437c5 | 15184 | plus_constant (stack_pointer_rtx, -4 * num_regs)); |
87e27392 NC |
15185 | RTX_FRAME_RELATED_P (tmp) = 1; |
15186 | XVECEXP (dwarf, 0, 0) = tmp; | |
f676971a | 15187 | |
bbbbb16a ILT |
15188 | add_reg_note (par, REG_FRAME_RELATED_EXPR, dwarf); |
15189 | ||
2c849145 | 15190 | return par; |
b111229a RE |
15191 | } |
15192 | ||
4f5dfed0 | 15193 | /* Calculate the size of the return value that is passed in registers. */ |
466e4b7a | 15194 | static unsigned |
4f5dfed0 JC |
15195 | arm_size_return_regs (void) |
15196 | { | |
15197 | enum machine_mode mode; | |
15198 | ||
38173d38 JH |
15199 | if (crtl->return_rtx != 0) |
15200 | mode = GET_MODE (crtl->return_rtx); | |
4f5dfed0 JC |
15201 | else |
15202 | mode = DECL_MODE (DECL_RESULT (current_function_decl)); | |
15203 | ||
15204 | return GET_MODE_SIZE (mode); | |
15205 | } | |
15206 | ||
2c849145 | 15207 | static rtx |
e32bac5b | 15208 | emit_sfm (int base_reg, int count) |
b111229a RE |
15209 | { |
15210 | rtx par; | |
2c849145 JM |
15211 | rtx dwarf; |
15212 | rtx tmp, reg; | |
b111229a RE |
15213 | int i; |
15214 | ||
43cffd11 | 15215 | par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); |
8ee6eb4e | 15216 | dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (count + 1)); |
2c849145 JM |
15217 | |
15218 | reg = gen_rtx_REG (XFmode, base_reg++); | |
43cffd11 RE |
15219 | |
15220 | XVECEXP (par, 0, 0) | |
f676971a | 15221 | = gen_rtx_SET (VOIDmode, |
9abf5d7b RR |
15222 | gen_frame_mem |
15223 | (BLKmode, | |
15224 | gen_rtx_PRE_MODIFY (Pmode, | |
15225 | stack_pointer_rtx, | |
15226 | plus_constant | |
15227 | (stack_pointer_rtx, | |
15228 | -12 * count)) | |
15229 | ), | |
43cffd11 | 15230 | gen_rtx_UNSPEC (BLKmode, |
2c849145 | 15231 | gen_rtvec (1, reg), |
b15bca31 | 15232 | UNSPEC_PUSH_MULT)); |
f676971a | 15233 | tmp = gen_rtx_SET (VOIDmode, |
31fa16b6 | 15234 | gen_frame_mem (XFmode, stack_pointer_rtx), reg); |
2c849145 | 15235 | RTX_FRAME_RELATED_P (tmp) = 1; |
f676971a EC |
15236 | XVECEXP (dwarf, 0, 1) = tmp; |
15237 | ||
b111229a | 15238 | for (i = 1; i < count; i++) |
2c849145 JM |
15239 | { |
15240 | reg = gen_rtx_REG (XFmode, base_reg++); | |
15241 | XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode, reg); | |
15242 | ||
f676971a | 15243 | tmp = gen_rtx_SET (VOIDmode, |
31fa16b6 RE |
15244 | gen_frame_mem (XFmode, |
15245 | plus_constant (stack_pointer_rtx, | |
15246 | i * 12)), | |
2c849145 JM |
15247 | reg); |
15248 | RTX_FRAME_RELATED_P (tmp) = 1; | |
f676971a | 15249 | XVECEXP (dwarf, 0, i + 1) = tmp; |
2c849145 | 15250 | } |
b111229a | 15251 | |
8ee6eb4e PB |
15252 | tmp = gen_rtx_SET (VOIDmode, |
15253 | stack_pointer_rtx, | |
d66437c5 RE |
15254 | plus_constant (stack_pointer_rtx, -12 * count)); |
15255 | ||
8ee6eb4e PB |
15256 | RTX_FRAME_RELATED_P (tmp) = 1; |
15257 | XVECEXP (dwarf, 0, 0) = tmp; | |
15258 | ||
2c849145 | 15259 | par = emit_insn (par); |
bbbbb16a ILT |
15260 | add_reg_note (par, REG_FRAME_RELATED_EXPR, dwarf); |
15261 | ||
2c849145 | 15262 | return par; |
e2c671ba RE |
15263 | } |
15264 | ||
9b66ebb1 | 15265 | |
3c7ad43e PB |
15266 | /* Return true if the current function needs to save/restore LR. */ |
15267 | ||
15268 | static bool | |
15269 | thumb_force_lr_save (void) | |
15270 | { | |
15271 | return !cfun->machine->lr_save_eliminated | |
15272 | && (!leaf_function_p () | |
15273 | || thumb_far_jump_used_p () | |
6fb5fa3c | 15274 | || df_regs_ever_live_p (LR_REGNUM)); |
3c7ad43e PB |
15275 | } |
15276 | ||
15277 | ||
147a0bcf JJ |
15278 | /* Return true if r3 is used by any of the tail call insns in the |
15279 | current function. */ | |
15280 | ||
15281 | static bool | |
15282 | any_sibcall_uses_r3 (void) | |
15283 | { | |
15284 | edge_iterator ei; | |
15285 | edge e; | |
15286 | ||
15287 | if (!crtl->tail_call_emit) | |
15288 | return false; | |
15289 | FOR_EACH_EDGE (e, ei, EXIT_BLOCK_PTR->preds) | |
15290 | if (e->flags & EDGE_SIBCALL) | |
15291 | { | |
15292 | rtx call = BB_END (e->src); | |
15293 | if (!CALL_P (call)) | |
15294 | call = prev_nonnote_nondebug_insn (call); | |
15295 | gcc_assert (CALL_P (call) && SIBLING_CALL_P (call)); | |
15296 | if (find_regno_fusage (call, USE, 3)) | |
15297 | return true; | |
15298 | } | |
15299 | return false; | |
15300 | } | |
15301 | ||
15302 | ||
095bb276 NC |
15303 | /* Compute the distance from register FROM to register TO. |
15304 | These can be the arg pointer (26), the soft frame pointer (25), | |
15305 | the stack pointer (13) or the hard frame pointer (11). | |
c9ca9b88 | 15306 | In thumb mode r7 is used as the soft frame pointer, if needed. |
095bb276 NC |
15307 | Typical stack layout looks like this: |
15308 | ||
15309 | old stack pointer -> | | | |
15310 | ---- | |
15311 | | | \ | |
15312 | | | saved arguments for | |
15313 | | | vararg functions | |
15314 | | | / | |
15315 | -- | |
15316 | hard FP & arg pointer -> | | \ | |
15317 | | | stack | |
15318 | | | frame | |
15319 | | | / | |
15320 | -- | |
15321 | | | \ | |
15322 | | | call saved | |
15323 | | | registers | |
15324 | soft frame pointer -> | | / | |
15325 | -- | |
15326 | | | \ | |
15327 | | | local | |
15328 | | | variables | |
2591db65 | 15329 | locals base pointer -> | | / |
095bb276 NC |
15330 | -- |
15331 | | | \ | |
15332 | | | outgoing | |
15333 | | | arguments | |
15334 | current stack pointer -> | | / | |
15335 | -- | |
15336 | ||
43aa4e05 | 15337 | For a given function some or all of these stack components |
095bb276 NC |
15338 | may not be needed, giving rise to the possibility of |
15339 | eliminating some of the registers. | |
15340 | ||
825dda42 | 15341 | The values returned by this function must reflect the behavior |
095bb276 NC |
15342 | of arm_expand_prologue() and arm_compute_save_reg_mask(). |
15343 | ||
15344 | The sign of the number returned reflects the direction of stack | |
15345 | growth, so the values are positive for all eliminations except | |
5848830f PB |
15346 | from the soft frame pointer to the hard frame pointer. |
15347 | ||
15348 | SFP may point just inside the local variables block to ensure correct | |
15349 | alignment. */ | |
15350 | ||
15351 | ||
15352 | /* Calculate stack offsets. These are used to calculate register elimination | |
954954d1 PB |
15353 | offsets and in prologue/epilogue code. Also calculates which registers |
15354 | should be saved. */ | |
5848830f PB |
15355 | |
15356 | static arm_stack_offsets * | |
15357 | arm_get_frame_offsets (void) | |
095bb276 | 15358 | { |
5848830f | 15359 | struct arm_stack_offsets *offsets; |
095bb276 | 15360 | unsigned long func_type; |
5848830f | 15361 | int leaf; |
5848830f | 15362 | int saved; |
954954d1 | 15363 | int core_saved; |
5848830f | 15364 | HOST_WIDE_INT frame_size; |
954954d1 | 15365 | int i; |
5848830f PB |
15366 | |
15367 | offsets = &cfun->machine->stack_offsets; | |
f676971a | 15368 | |
5848830f PB |
15369 | /* We need to know if we are a leaf function. Unfortunately, it |
15370 | is possible to be called after start_sequence has been called, | |
15371 | which causes get_insns to return the insns for the sequence, | |
15372 | not the function, which will cause leaf_function_p to return | |
15373 | the incorrect result. | |
095bb276 | 15374 | |
5848830f PB |
15375 | to know about leaf functions once reload has completed, and the |
15376 | frame size cannot be changed after that time, so we can safely | |
15377 | use the cached value. */ | |
15378 | ||
15379 | if (reload_completed) | |
15380 | return offsets; | |
15381 | ||
666c27b9 KH |
15382 | /* Initially this is the size of the local variables. It will translated |
15383 | into an offset once we have determined the size of preceding data. */ | |
5848830f PB |
15384 | frame_size = ROUND_UP_WORD (get_frame_size ()); |
15385 | ||
15386 | leaf = leaf_function_p (); | |
15387 | ||
15388 | /* Space for variadic functions. */ | |
38173d38 | 15389 | offsets->saved_args = crtl->args.pretend_args_size; |
5848830f | 15390 | |
5b3e6663 | 15391 | /* In Thumb mode this is incorrect, but never used. */ |
35596784 AJ |
15392 | offsets->frame = offsets->saved_args + (frame_pointer_needed ? 4 : 0) + |
15393 | arm_compute_static_chain_stack_bytes(); | |
5848830f | 15394 | |
5b3e6663 | 15395 | if (TARGET_32BIT) |
095bb276 | 15396 | { |
5848830f | 15397 | unsigned int regno; |
ef7112de | 15398 | |
954954d1 PB |
15399 | offsets->saved_regs_mask = arm_compute_save_reg_mask (); |
15400 | core_saved = bit_count (offsets->saved_regs_mask) * 4; | |
15401 | saved = core_saved; | |
5a9335ef | 15402 | |
5848830f PB |
15403 | /* We know that SP will be doubleword aligned on entry, and we must |
15404 | preserve that condition at any subroutine call. We also require the | |
15405 | soft frame pointer to be doubleword aligned. */ | |
15406 | ||
15407 | if (TARGET_REALLY_IWMMXT) | |
9b66ebb1 | 15408 | { |
5848830f PB |
15409 | /* Check for the call-saved iWMMXt registers. */ |
15410 | for (regno = FIRST_IWMMXT_REGNUM; | |
15411 | regno <= LAST_IWMMXT_REGNUM; | |
15412 | regno++) | |
6fb5fa3c | 15413 | if (df_regs_ever_live_p (regno) && ! call_used_regs[regno]) |
5848830f PB |
15414 | saved += 8; |
15415 | } | |
15416 | ||
15417 | func_type = arm_current_func_type (); | |
15418 | if (! IS_VOLATILE (func_type)) | |
15419 | { | |
15420 | /* Space for saved FPA registers. */ | |
15421 | for (regno = FIRST_FPA_REGNUM; regno <= LAST_FPA_REGNUM; regno++) | |
6fb5fa3c | 15422 | if (df_regs_ever_live_p (regno) && ! call_used_regs[regno]) |
5848830f PB |
15423 | saved += 12; |
15424 | ||
15425 | /* Space for saved VFP registers. */ | |
15426 | if (TARGET_HARD_FLOAT && TARGET_VFP) | |
9728c9d1 | 15427 | saved += arm_get_vfp_saved_size (); |
9b66ebb1 | 15428 | } |
5848830f | 15429 | } |
5b3e6663 | 15430 | else /* TARGET_THUMB1 */ |
5848830f | 15431 | { |
954954d1 PB |
15432 | offsets->saved_regs_mask = thumb1_compute_save_reg_mask (); |
15433 | core_saved = bit_count (offsets->saved_regs_mask) * 4; | |
15434 | saved = core_saved; | |
5848830f | 15435 | if (TARGET_BACKTRACE) |
57934c39 | 15436 | saved += 16; |
5848830f | 15437 | } |
9b66ebb1 | 15438 | |
5848830f | 15439 | /* Saved registers include the stack frame. */ |
35596784 AJ |
15440 | offsets->saved_regs = offsets->saved_args + saved + |
15441 | arm_compute_static_chain_stack_bytes(); | |
a2503645 | 15442 | offsets->soft_frame = offsets->saved_regs + CALLER_INTERWORKING_SLOT_SIZE; |
5848830f PB |
15443 | /* A leaf function does not need any stack alignment if it has nothing |
15444 | on the stack. */ | |
7c71147d CLT |
15445 | if (leaf && frame_size == 0 |
15446 | /* However if it calls alloca(), we have a dynamically allocated | |
15447 | block of BIGGEST_ALIGNMENT on stack, so still do stack alignment. */ | |
15448 | && ! cfun->calls_alloca) | |
5848830f PB |
15449 | { |
15450 | offsets->outgoing_args = offsets->soft_frame; | |
a3a531ec | 15451 | offsets->locals_base = offsets->soft_frame; |
5848830f PB |
15452 | return offsets; |
15453 | } | |
15454 | ||
15455 | /* Ensure SFP has the correct alignment. */ | |
15456 | if (ARM_DOUBLEWORD_ALIGN | |
15457 | && (offsets->soft_frame & 7)) | |
954954d1 PB |
15458 | { |
15459 | offsets->soft_frame += 4; | |
15460 | /* Try to align stack by pushing an extra reg. Don't bother doing this | |
15461 | when there is a stack frame as the alignment will be rolled into | |
15462 | the normal stack adjustment. */ | |
38173d38 | 15463 | if (frame_size + crtl->outgoing_args_size == 0) |
954954d1 PB |
15464 | { |
15465 | int reg = -1; | |
15466 | ||
55b2829b RE |
15467 | /* If it is safe to use r3, then do so. This sometimes |
15468 | generates better code on Thumb-2 by avoiding the need to | |
15469 | use 32-bit push/pop instructions. */ | |
147a0bcf | 15470 | if (! any_sibcall_uses_r3 () |
fb2f8cf8 JZ |
15471 | && arm_size_return_regs () <= 12 |
15472 | && (offsets->saved_regs_mask & (1 << 3)) == 0) | |
954954d1 | 15473 | { |
954954d1 PB |
15474 | reg = 3; |
15475 | } | |
55b2829b RE |
15476 | else |
15477 | for (i = 4; i <= (TARGET_THUMB1 ? LAST_LO_REGNUM : 11); i++) | |
15478 | { | |
15479 | if ((offsets->saved_regs_mask & (1 << i)) == 0) | |
15480 | { | |
15481 | reg = i; | |
15482 | break; | |
15483 | } | |
15484 | } | |
954954d1 PB |
15485 | |
15486 | if (reg != -1) | |
15487 | { | |
15488 | offsets->saved_regs += 4; | |
15489 | offsets->saved_regs_mask |= (1 << reg); | |
15490 | } | |
15491 | } | |
15492 | } | |
5848830f | 15493 | |
2591db65 RE |
15494 | offsets->locals_base = offsets->soft_frame + frame_size; |
15495 | offsets->outgoing_args = (offsets->locals_base | |
38173d38 | 15496 | + crtl->outgoing_args_size); |
5848830f PB |
15497 | |
15498 | if (ARM_DOUBLEWORD_ALIGN) | |
15499 | { | |
15500 | /* Ensure SP remains doubleword aligned. */ | |
15501 | if (offsets->outgoing_args & 7) | |
15502 | offsets->outgoing_args += 4; | |
e6d29d15 | 15503 | gcc_assert (!(offsets->outgoing_args & 7)); |
095bb276 NC |
15504 | } |
15505 | ||
5848830f PB |
15506 | return offsets; |
15507 | } | |
15508 | ||
15509 | ||
666c27b9 | 15510 | /* Calculate the relative offsets for the different stack pointers. Positive |
5848830f PB |
15511 | offsets are in the direction of stack growth. */ |
15512 | ||
b3f8d95d | 15513 | HOST_WIDE_INT |
5848830f PB |
15514 | arm_compute_initial_elimination_offset (unsigned int from, unsigned int to) |
15515 | { | |
15516 | arm_stack_offsets *offsets; | |
15517 | ||
15518 | offsets = arm_get_frame_offsets (); | |
095bb276 | 15519 | |
095bb276 NC |
15520 | /* OK, now we have enough information to compute the distances. |
15521 | There must be an entry in these switch tables for each pair | |
15522 | of registers in ELIMINABLE_REGS, even if some of the entries | |
15523 | seem to be redundant or useless. */ | |
15524 | switch (from) | |
15525 | { | |
15526 | case ARG_POINTER_REGNUM: | |
15527 | switch (to) | |
15528 | { | |
15529 | case THUMB_HARD_FRAME_POINTER_REGNUM: | |
15530 | return 0; | |
15531 | ||
15532 | case FRAME_POINTER_REGNUM: | |
15533 | /* This is the reverse of the soft frame pointer | |
15534 | to hard frame pointer elimination below. */ | |
5848830f | 15535 | return offsets->soft_frame - offsets->saved_args; |
095bb276 NC |
15536 | |
15537 | case ARM_HARD_FRAME_POINTER_REGNUM: | |
35596784 AJ |
15538 | /* This is only non-zero in the case where the static chain register |
15539 | is stored above the frame. */ | |
15540 | return offsets->frame - offsets->saved_args - 4; | |
095bb276 NC |
15541 | |
15542 | case STACK_POINTER_REGNUM: | |
15543 | /* If nothing has been pushed on the stack at all | |
15544 | then this will return -4. This *is* correct! */ | |
5848830f | 15545 | return offsets->outgoing_args - (offsets->saved_args + 4); |
095bb276 NC |
15546 | |
15547 | default: | |
e6d29d15 | 15548 | gcc_unreachable (); |
095bb276 | 15549 | } |
e6d29d15 | 15550 | gcc_unreachable (); |
095bb276 NC |
15551 | |
15552 | case FRAME_POINTER_REGNUM: | |
15553 | switch (to) | |
15554 | { | |
15555 | case THUMB_HARD_FRAME_POINTER_REGNUM: | |
15556 | return 0; | |
15557 | ||
15558 | case ARM_HARD_FRAME_POINTER_REGNUM: | |
15559 | /* The hard frame pointer points to the top entry in the | |
15560 | stack frame. The soft frame pointer to the bottom entry | |
15561 | in the stack frame. If there is no stack frame at all, | |
15562 | then they are identical. */ | |
5848830f PB |
15563 | |
15564 | return offsets->frame - offsets->soft_frame; | |
095bb276 NC |
15565 | |
15566 | case STACK_POINTER_REGNUM: | |
5848830f | 15567 | return offsets->outgoing_args - offsets->soft_frame; |
095bb276 NC |
15568 | |
15569 | default: | |
e6d29d15 | 15570 | gcc_unreachable (); |
095bb276 | 15571 | } |
e6d29d15 | 15572 | gcc_unreachable (); |
095bb276 NC |
15573 | |
15574 | default: | |
15575 | /* You cannot eliminate from the stack pointer. | |
15576 | In theory you could eliminate from the hard frame | |
15577 | pointer to the stack pointer, but this will never | |
15578 | happen, since if a stack frame is not needed the | |
15579 | hard frame pointer will never be used. */ | |
e6d29d15 | 15580 | gcc_unreachable (); |
095bb276 NC |
15581 | } |
15582 | } | |
15583 | ||
7b5cbb57 AS |
15584 | /* Given FROM and TO register numbers, say whether this elimination is |
15585 | allowed. Frame pointer elimination is automatically handled. | |
15586 | ||
15587 | All eliminations are permissible. Note that ARG_POINTER_REGNUM and | |
15588 | HARD_FRAME_POINTER_REGNUM are in fact the same thing. If we need a frame | |
15589 | pointer, we must eliminate FRAME_POINTER_REGNUM into | |
15590 | HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM or | |
15591 | ARG_POINTER_REGNUM. */ | |
15592 | ||
15593 | bool | |
15594 | arm_can_eliminate (const int from, const int to) | |
15595 | { | |
15596 | return ((to == FRAME_POINTER_REGNUM && from == ARG_POINTER_REGNUM) ? false : | |
15597 | (to == STACK_POINTER_REGNUM && frame_pointer_needed) ? false : | |
15598 | (to == ARM_HARD_FRAME_POINTER_REGNUM && TARGET_THUMB) ? false : | |
15599 | (to == THUMB_HARD_FRAME_POINTER_REGNUM && TARGET_ARM) ? false : | |
15600 | true); | |
15601 | } | |
0977774b | 15602 | |
7a085dce | 15603 | /* Emit RTL to save coprocessor registers on function entry. Returns the |
5b3e6663 PB |
15604 | number of bytes pushed. */ |
15605 | ||
15606 | static int | |
15607 | arm_save_coproc_regs(void) | |
15608 | { | |
15609 | int saved_size = 0; | |
15610 | unsigned reg; | |
15611 | unsigned start_reg; | |
15612 | rtx insn; | |
15613 | ||
15614 | for (reg = LAST_IWMMXT_REGNUM; reg >= FIRST_IWMMXT_REGNUM; reg--) | |
6fb5fa3c | 15615 | if (df_regs_ever_live_p (reg) && ! call_used_regs[reg]) |
5b3e6663 | 15616 | { |
d8d55ac0 | 15617 | insn = gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx); |
5b3e6663 PB |
15618 | insn = gen_rtx_MEM (V2SImode, insn); |
15619 | insn = emit_set_insn (insn, gen_rtx_REG (V2SImode, reg)); | |
15620 | RTX_FRAME_RELATED_P (insn) = 1; | |
15621 | saved_size += 8; | |
15622 | } | |
15623 | ||
15624 | /* Save any floating point call-saved registers used by this | |
15625 | function. */ | |
d79f3032 | 15626 | if (TARGET_FPA_EMU2) |
5b3e6663 PB |
15627 | { |
15628 | for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--) | |
6fb5fa3c | 15629 | if (df_regs_ever_live_p (reg) && !call_used_regs[reg]) |
5b3e6663 | 15630 | { |
d8d55ac0 | 15631 | insn = gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx); |
5b3e6663 PB |
15632 | insn = gen_rtx_MEM (XFmode, insn); |
15633 | insn = emit_set_insn (insn, gen_rtx_REG (XFmode, reg)); | |
15634 | RTX_FRAME_RELATED_P (insn) = 1; | |
15635 | saved_size += 12; | |
15636 | } | |
15637 | } | |
15638 | else | |
15639 | { | |
15640 | start_reg = LAST_FPA_REGNUM; | |
15641 | ||
15642 | for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--) | |
15643 | { | |
6fb5fa3c | 15644 | if (df_regs_ever_live_p (reg) && !call_used_regs[reg]) |
5b3e6663 PB |
15645 | { |
15646 | if (start_reg - reg == 3) | |
15647 | { | |
15648 | insn = emit_sfm (reg, 4); | |
15649 | RTX_FRAME_RELATED_P (insn) = 1; | |
15650 | saved_size += 48; | |
15651 | start_reg = reg - 1; | |
15652 | } | |
15653 | } | |
15654 | else | |
15655 | { | |
15656 | if (start_reg != reg) | |
15657 | { | |
15658 | insn = emit_sfm (reg + 1, start_reg - reg); | |
15659 | RTX_FRAME_RELATED_P (insn) = 1; | |
15660 | saved_size += (start_reg - reg) * 12; | |
15661 | } | |
15662 | start_reg = reg - 1; | |
15663 | } | |
15664 | } | |
15665 | ||
15666 | if (start_reg != reg) | |
15667 | { | |
15668 | insn = emit_sfm (reg + 1, start_reg - reg); | |
15669 | saved_size += (start_reg - reg) * 12; | |
15670 | RTX_FRAME_RELATED_P (insn) = 1; | |
15671 | } | |
15672 | } | |
15673 | if (TARGET_HARD_FLOAT && TARGET_VFP) | |
15674 | { | |
15675 | start_reg = FIRST_VFP_REGNUM; | |
15676 | ||
15677 | for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2) | |
15678 | { | |
6fb5fa3c DB |
15679 | if ((!df_regs_ever_live_p (reg) || call_used_regs[reg]) |
15680 | && (!df_regs_ever_live_p (reg + 1) || call_used_regs[reg + 1])) | |
5b3e6663 PB |
15681 | { |
15682 | if (start_reg != reg) | |
15683 | saved_size += vfp_emit_fstmd (start_reg, | |
15684 | (reg - start_reg) / 2); | |
15685 | start_reg = reg + 2; | |
15686 | } | |
15687 | } | |
15688 | if (start_reg != reg) | |
15689 | saved_size += vfp_emit_fstmd (start_reg, | |
15690 | (reg - start_reg) / 2); | |
15691 | } | |
15692 | return saved_size; | |
15693 | } | |
15694 | ||
15695 | ||
15696 | /* Set the Thumb frame pointer from the stack pointer. */ | |
15697 | ||
15698 | static void | |
15699 | thumb_set_frame_pointer (arm_stack_offsets *offsets) | |
15700 | { | |
15701 | HOST_WIDE_INT amount; | |
15702 | rtx insn, dwarf; | |
15703 | ||
15704 | amount = offsets->outgoing_args - offsets->locals_base; | |
15705 | if (amount < 1024) | |
15706 | insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx, | |
15707 | stack_pointer_rtx, GEN_INT (amount))); | |
15708 | else | |
15709 | { | |
15710 | emit_insn (gen_movsi (hard_frame_pointer_rtx, GEN_INT (amount))); | |
f5c630c3 PB |
15711 | /* Thumb-2 RTL patterns expect sp as the first input. Thumb-1 |
15712 | expects the first two operands to be the same. */ | |
15713 | if (TARGET_THUMB2) | |
15714 | { | |
15715 | insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx, | |
15716 | stack_pointer_rtx, | |
15717 | hard_frame_pointer_rtx)); | |
15718 | } | |
15719 | else | |
15720 | { | |
15721 | insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx, | |
15722 | hard_frame_pointer_rtx, | |
15723 | stack_pointer_rtx)); | |
15724 | } | |
5b3e6663 PB |
15725 | dwarf = gen_rtx_SET (VOIDmode, hard_frame_pointer_rtx, |
15726 | plus_constant (stack_pointer_rtx, amount)); | |
15727 | RTX_FRAME_RELATED_P (dwarf) = 1; | |
bbbbb16a | 15728 | add_reg_note (insn, REG_FRAME_RELATED_EXPR, dwarf); |
5b3e6663 PB |
15729 | } |
15730 | ||
15731 | RTX_FRAME_RELATED_P (insn) = 1; | |
15732 | } | |
15733 | ||
15734 | /* Generate the prologue instructions for entry into an ARM or Thumb-2 | |
15735 | function. */ | |
e2c671ba | 15736 | void |
e32bac5b | 15737 | arm_expand_prologue (void) |
e2c671ba | 15738 | { |
6d3d9133 | 15739 | rtx amount; |
2c849145 | 15740 | rtx insn; |
68dfd979 | 15741 | rtx ip_rtx; |
6d3d9133 NC |
15742 | unsigned long live_regs_mask; |
15743 | unsigned long func_type; | |
68dfd979 | 15744 | int fp_offset = 0; |
095bb276 | 15745 | int saved_pretend_args = 0; |
5848830f | 15746 | int saved_regs = 0; |
b9705a21 | 15747 | unsigned HOST_WIDE_INT args_to_push; |
5848830f | 15748 | arm_stack_offsets *offsets; |
d3236b4d | 15749 | |
6d3d9133 | 15750 | func_type = arm_current_func_type (); |
e2c671ba | 15751 | |
31fdb4d5 | 15752 | /* Naked functions don't have prologues. */ |
6d3d9133 | 15753 | if (IS_NAKED (func_type)) |
31fdb4d5 DE |
15754 | return; |
15755 | ||
095bb276 | 15756 | /* Make a copy of c_f_p_a_s as we may need to modify it locally. */ |
38173d38 | 15757 | args_to_push = crtl->args.pretend_args_size; |
f676971a | 15758 | |
6d3d9133 | 15759 | /* Compute which register we will have to save onto the stack. */ |
954954d1 PB |
15760 | offsets = arm_get_frame_offsets (); |
15761 | live_regs_mask = offsets->saved_regs_mask; | |
e2c671ba | 15762 | |
68dfd979 | 15763 | ip_rtx = gen_rtx_REG (SImode, IP_REGNUM); |
d3236b4d | 15764 | |
5b3e6663 PB |
15765 | if (IS_STACKALIGN (func_type)) |
15766 | { | |
15767 | rtx dwarf; | |
15768 | rtx r0; | |
15769 | rtx r1; | |
15770 | /* Handle a word-aligned stack pointer. We generate the following: | |
15771 | ||
15772 | mov r0, sp | |
15773 | bic r1, r0, #7 | |
15774 | mov sp, r1 | |
15775 | <save and restore r0 in normal prologue/epilogue> | |
15776 | mov sp, r0 | |
15777 | bx lr | |
15778 | ||
15779 | The unwinder doesn't need to know about the stack realignment. | |
15780 | Just tell it we saved SP in r0. */ | |
15781 | gcc_assert (TARGET_THUMB2 && !arm_arch_notm && args_to_push == 0); | |
15782 | ||
15783 | r0 = gen_rtx_REG (SImode, 0); | |
15784 | r1 = gen_rtx_REG (SImode, 1); | |
44bfa35b NF |
15785 | /* Use a real rtvec rather than NULL_RTVEC so the rest of the |
15786 | compiler won't choke. */ | |
15787 | dwarf = gen_rtx_UNSPEC (SImode, rtvec_alloc (0), UNSPEC_STACK_ALIGN); | |
5b3e6663 PB |
15788 | dwarf = gen_rtx_SET (VOIDmode, r0, dwarf); |
15789 | insn = gen_movsi (r0, stack_pointer_rtx); | |
15790 | RTX_FRAME_RELATED_P (insn) = 1; | |
bbbbb16a | 15791 | add_reg_note (insn, REG_FRAME_RELATED_EXPR, dwarf); |
5b3e6663 PB |
15792 | emit_insn (insn); |
15793 | emit_insn (gen_andsi3 (r1, r0, GEN_INT (~(HOST_WIDE_INT)7))); | |
15794 | emit_insn (gen_movsi (stack_pointer_rtx, r1)); | |
15795 | } | |
15796 | ||
ec6237e4 PB |
15797 | /* For APCS frames, if IP register is clobbered |
15798 | when creating frame, save that register in a special | |
15799 | way. */ | |
15800 | if (TARGET_APCS_FRAME && frame_pointer_needed && TARGET_ARM) | |
e2c671ba | 15801 | { |
7b8b8ade NC |
15802 | if (IS_INTERRUPT (func_type)) |
15803 | { | |
15804 | /* Interrupt functions must not corrupt any registers. | |
15805 | Creating a frame pointer however, corrupts the IP | |
15806 | register, so we must push it first. */ | |
15807 | insn = emit_multi_reg_push (1 << IP_REGNUM); | |
121308d4 NC |
15808 | |
15809 | /* Do not set RTX_FRAME_RELATED_P on this insn. | |
15810 | The dwarf stack unwinding code only wants to see one | |
15811 | stack decrement per function, and this is not it. If | |
15812 | this instruction is labeled as being part of the frame | |
15813 | creation sequence then dwarf2out_frame_debug_expr will | |
e6d29d15 | 15814 | die when it encounters the assignment of IP to FP |
121308d4 NC |
15815 | later on, since the use of SP here establishes SP as |
15816 | the CFA register and not IP. | |
15817 | ||
15818 | Anyway this instruction is not really part of the stack | |
15819 | frame creation although it is part of the prologue. */ | |
7b8b8ade NC |
15820 | } |
15821 | else if (IS_NESTED (func_type)) | |
68dfd979 NC |
15822 | { |
15823 | /* The Static chain register is the same as the IP register | |
15824 | used as a scratch register during stack frame creation. | |
15825 | To get around this need to find somewhere to store IP | |
15826 | whilst the frame is being created. We try the following | |
15827 | places in order: | |
f676971a | 15828 | |
6d3d9133 | 15829 | 1. The last argument register. |
68dfd979 NC |
15830 | 2. A slot on the stack above the frame. (This only |
15831 | works if the function is not a varargs function). | |
095bb276 NC |
15832 | 3. Register r3, after pushing the argument registers |
15833 | onto the stack. | |
6d3d9133 | 15834 | |
34ce3d7b JM |
15835 | Note - we only need to tell the dwarf2 backend about the SP |
15836 | adjustment in the second variant; the static chain register | |
15837 | doesn't need to be unwound, as it doesn't contain a value | |
15838 | inherited from the caller. */ | |
d3236b4d | 15839 | |
6fb5fa3c | 15840 | if (df_regs_ever_live_p (3) == false) |
d66437c5 | 15841 | insn = emit_set_insn (gen_rtx_REG (SImode, 3), ip_rtx); |
095bb276 | 15842 | else if (args_to_push == 0) |
68dfd979 | 15843 | { |
f0b4bdd5 RE |
15844 | rtx dwarf; |
15845 | ||
35596784 AJ |
15846 | gcc_assert(arm_compute_static_chain_stack_bytes() == 4); |
15847 | saved_regs += 4; | |
15848 | ||
d66437c5 RE |
15849 | insn = gen_rtx_PRE_DEC (SImode, stack_pointer_rtx); |
15850 | insn = emit_set_insn (gen_frame_mem (SImode, insn), ip_rtx); | |
68dfd979 | 15851 | fp_offset = 4; |
34ce3d7b JM |
15852 | |
15853 | /* Just tell the dwarf backend that we adjusted SP. */ | |
15854 | dwarf = gen_rtx_SET (VOIDmode, stack_pointer_rtx, | |
d66437c5 RE |
15855 | plus_constant (stack_pointer_rtx, |
15856 | -fp_offset)); | |
34ce3d7b | 15857 | RTX_FRAME_RELATED_P (insn) = 1; |
bbbbb16a | 15858 | add_reg_note (insn, REG_FRAME_RELATED_EXPR, dwarf); |
68dfd979 NC |
15859 | } |
15860 | else | |
095bb276 NC |
15861 | { |
15862 | /* Store the args on the stack. */ | |
3cb66fd7 | 15863 | if (cfun->machine->uses_anonymous_args) |
095bb276 NC |
15864 | insn = emit_multi_reg_push |
15865 | ((0xf0 >> (args_to_push / 4)) & 0xf); | |
15866 | else | |
15867 | insn = emit_insn | |
f676971a | 15868 | (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, |
095bb276 NC |
15869 | GEN_INT (- args_to_push))); |
15870 | ||
15871 | RTX_FRAME_RELATED_P (insn) = 1; | |
15872 | ||
15873 | saved_pretend_args = 1; | |
15874 | fp_offset = args_to_push; | |
15875 | args_to_push = 0; | |
15876 | ||
15877 | /* Now reuse r3 to preserve IP. */ | |
d66437c5 | 15878 | emit_set_insn (gen_rtx_REG (SImode, 3), ip_rtx); |
095bb276 | 15879 | } |
68dfd979 NC |
15880 | } |
15881 | ||
d66437c5 RE |
15882 | insn = emit_set_insn (ip_rtx, |
15883 | plus_constant (stack_pointer_rtx, fp_offset)); | |
8e56560e | 15884 | RTX_FRAME_RELATED_P (insn) = 1; |
e2c671ba RE |
15885 | } |
15886 | ||
095bb276 | 15887 | if (args_to_push) |
e2c671ba | 15888 | { |
6d3d9133 | 15889 | /* Push the argument registers, or reserve space for them. */ |
3cb66fd7 | 15890 | if (cfun->machine->uses_anonymous_args) |
2c849145 | 15891 | insn = emit_multi_reg_push |
095bb276 | 15892 | ((0xf0 >> (args_to_push / 4)) & 0xf); |
e2c671ba | 15893 | else |
2c849145 | 15894 | insn = emit_insn |
f676971a | 15895 | (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, |
095bb276 | 15896 | GEN_INT (- args_to_push))); |
2c849145 | 15897 | RTX_FRAME_RELATED_P (insn) = 1; |
e2c671ba RE |
15898 | } |
15899 | ||
06bea5aa | 15900 | /* If this is an interrupt service routine, and the link register |
ec6237e4 PB |
15901 | is going to be pushed, and we're not generating extra |
15902 | push of IP (needed when frame is needed and frame layout if apcs), | |
06bea5aa NC |
15903 | subtracting four from LR now will mean that the function return |
15904 | can be done with a single instruction. */ | |
3a7731fd | 15905 | if ((func_type == ARM_FT_ISR || func_type == ARM_FT_FIQ) |
06bea5aa | 15906 | && (live_regs_mask & (1 << LR_REGNUM)) != 0 |
ec6237e4 | 15907 | && !(frame_pointer_needed && TARGET_APCS_FRAME) |
a15908a4 | 15908 | && TARGET_ARM) |
d66437c5 RE |
15909 | { |
15910 | rtx lr = gen_rtx_REG (SImode, LR_REGNUM); | |
15911 | ||
15912 | emit_set_insn (lr, plus_constant (lr, -4)); | |
15913 | } | |
3a7731fd | 15914 | |
e2c671ba RE |
15915 | if (live_regs_mask) |
15916 | { | |
5848830f | 15917 | saved_regs += bit_count (live_regs_mask) * 4; |
954954d1 PB |
15918 | if (optimize_size && !frame_pointer_needed |
15919 | && saved_regs == offsets->saved_regs - offsets->saved_args) | |
15920 | { | |
15921 | /* If no coprocessor registers are being pushed and we don't have | |
15922 | to worry about a frame pointer then push extra registers to | |
15923 | create the stack frame. This is done is a way that does not | |
15924 | alter the frame layout, so is independent of the epilogue. */ | |
15925 | int n; | |
15926 | int frame; | |
15927 | n = 0; | |
15928 | while (n < 8 && (live_regs_mask & (1 << n)) == 0) | |
15929 | n++; | |
15930 | frame = offsets->outgoing_args - (offsets->saved_args + saved_regs); | |
15931 | if (frame && n * 4 >= frame) | |
15932 | { | |
15933 | n = frame / 4; | |
15934 | live_regs_mask |= (1 << n) - 1; | |
15935 | saved_regs += frame; | |
15936 | } | |
15937 | } | |
15938 | insn = emit_multi_reg_push (live_regs_mask); | |
2c849145 | 15939 | RTX_FRAME_RELATED_P (insn) = 1; |
e2c671ba | 15940 | } |
d5b7b3ae | 15941 | |
6d3d9133 | 15942 | if (! IS_VOLATILE (func_type)) |
5b3e6663 | 15943 | saved_regs += arm_save_coproc_regs (); |
b111229a | 15944 | |
5b3e6663 PB |
15945 | if (frame_pointer_needed && TARGET_ARM) |
15946 | { | |
15947 | /* Create the new frame pointer. */ | |
ec6237e4 | 15948 | if (TARGET_APCS_FRAME) |
9b66ebb1 | 15949 | { |
5b3e6663 PB |
15950 | insn = GEN_INT (-(4 + args_to_push + fp_offset)); |
15951 | insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx, ip_rtx, insn)); | |
15952 | RTX_FRAME_RELATED_P (insn) = 1; | |
9b66ebb1 | 15953 | |
5b3e6663 | 15954 | if (IS_NESTED (func_type)) |
9b66ebb1 | 15955 | { |
5b3e6663 | 15956 | /* Recover the static chain register. */ |
6fb5fa3c | 15957 | if (!df_regs_ever_live_p (3) |
5b3e6663 PB |
15958 | || saved_pretend_args) |
15959 | insn = gen_rtx_REG (SImode, 3); | |
38173d38 | 15960 | else /* if (crtl->args.pretend_args_size == 0) */ |
9b66ebb1 | 15961 | { |
5b3e6663 PB |
15962 | insn = plus_constant (hard_frame_pointer_rtx, 4); |
15963 | insn = gen_frame_mem (SImode, insn); | |
9b66ebb1 | 15964 | } |
5b3e6663 PB |
15965 | emit_set_insn (ip_rtx, insn); |
15966 | /* Add a USE to stop propagate_one_insn() from barfing. */ | |
15967 | emit_insn (gen_prologue_use (ip_rtx)); | |
9b66ebb1 | 15968 | } |
68dfd979 | 15969 | } |
ec6237e4 PB |
15970 | else |
15971 | { | |
15972 | insn = GEN_INT (saved_regs - 4); | |
15973 | insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx, | |
15974 | stack_pointer_rtx, insn)); | |
15975 | RTX_FRAME_RELATED_P (insn) = 1; | |
15976 | } | |
2c849145 | 15977 | } |
e2c671ba | 15978 | |
55256000 TK |
15979 | if (flag_stack_usage) |
15980 | current_function_static_stack_size | |
15981 | = offsets->outgoing_args - offsets->saved_args; | |
15982 | ||
5848830f | 15983 | if (offsets->outgoing_args != offsets->saved_args + saved_regs) |
e2c671ba | 15984 | { |
745b9093 JM |
15985 | /* This add can produce multiple insns for a large constant, so we |
15986 | need to get tricky. */ | |
15987 | rtx last = get_last_insn (); | |
5848830f PB |
15988 | |
15989 | amount = GEN_INT (offsets->saved_args + saved_regs | |
15990 | - offsets->outgoing_args); | |
15991 | ||
2c849145 JM |
15992 | insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, |
15993 | amount)); | |
745b9093 JM |
15994 | do |
15995 | { | |
15996 | last = last ? NEXT_INSN (last) : get_insns (); | |
15997 | RTX_FRAME_RELATED_P (last) = 1; | |
15998 | } | |
15999 | while (last != insn); | |
e04c2d6c RE |
16000 | |
16001 | /* If the frame pointer is needed, emit a special barrier that | |
16002 | will prevent the scheduler from moving stores to the frame | |
16003 | before the stack adjustment. */ | |
16004 | if (frame_pointer_needed) | |
3894f59e RE |
16005 | insn = emit_insn (gen_stack_tie (stack_pointer_rtx, |
16006 | hard_frame_pointer_rtx)); | |
e2c671ba RE |
16007 | } |
16008 | ||
876f13b0 | 16009 | |
5b3e6663 PB |
16010 | if (frame_pointer_needed && TARGET_THUMB2) |
16011 | thumb_set_frame_pointer (offsets); | |
16012 | ||
020a4035 | 16013 | if (flag_pic && arm_pic_register != INVALID_REGNUM) |
5b3e6663 PB |
16014 | { |
16015 | unsigned long mask; | |
16016 | ||
16017 | mask = live_regs_mask; | |
16018 | mask &= THUMB2_WORK_REGS; | |
16019 | if (!IS_NESTED (func_type)) | |
16020 | mask |= (1 << IP_REGNUM); | |
16021 | arm_load_pic_register (mask); | |
16022 | } | |
876f13b0 | 16023 | |
e2c671ba | 16024 | /* If we are profiling, make sure no instructions are scheduled before |
f5a1b0d2 | 16025 | the call to mcount. Similarly if the user has requested no |
74d9c39f DJ |
16026 | scheduling in the prolog. Similarly if we want non-call exceptions |
16027 | using the EABI unwinder, to prevent faulting instructions from being | |
16028 | swapped with a stack adjustment. */ | |
e3b5732b | 16029 | if (crtl->profile || !TARGET_SCHED_PROLOG |
d5fabb58 | 16030 | || (arm_except_unwind_info (&global_options) == UI_TARGET |
f0a0390e | 16031 | && cfun->can_throw_non_call_exceptions)) |
e2c671ba | 16032 | emit_insn (gen_blockage ()); |
6f7ebcbb NC |
16033 | |
16034 | /* If the link register is being kept alive, with the return address in it, | |
16035 | then make sure that it does not get reused by the ce2 pass. */ | |
16036 | if ((live_regs_mask & (1 << LR_REGNUM)) == 0) | |
6fb5fa3c | 16037 | cfun->machine->lr_save_eliminated = 1; |
e2c671ba | 16038 | } |
cce8749e | 16039 | \f |
5b3e6663 PB |
16040 | /* Print condition code to STREAM. Helper function for arm_print_operand. */ |
16041 | static void | |
16042 | arm_print_condition (FILE *stream) | |
16043 | { | |
16044 | if (arm_ccfsm_state == 3 || arm_ccfsm_state == 4) | |
16045 | { | |
16046 | /* Branch conversion is not implemented for Thumb-2. */ | |
16047 | if (TARGET_THUMB) | |
16048 | { | |
16049 | output_operand_lossage ("predicated Thumb instruction"); | |
16050 | return; | |
16051 | } | |
16052 | if (current_insn_predicate != NULL) | |
16053 | { | |
16054 | output_operand_lossage | |
16055 | ("predicated instruction in conditional sequence"); | |
16056 | return; | |
16057 | } | |
16058 | ||
16059 | fputs (arm_condition_codes[arm_current_cc], stream); | |
16060 | } | |
16061 | else if (current_insn_predicate) | |
16062 | { | |
16063 | enum arm_cond_code code; | |
16064 | ||
16065 | if (TARGET_THUMB1) | |
16066 | { | |
16067 | output_operand_lossage ("predicated Thumb instruction"); | |
16068 | return; | |
16069 | } | |
16070 | ||
16071 | code = get_arm_condition_code (current_insn_predicate); | |
16072 | fputs (arm_condition_codes[code], stream); | |
16073 | } | |
16074 | } | |
16075 | ||
16076 | ||
9997d19d RE |
16077 | /* If CODE is 'd', then the X is a condition operand and the instruction |
16078 | should only be executed if the condition is true. | |
ddd5a7c1 | 16079 | if CODE is 'D', then the X is a condition operand and the instruction |
9997d19d RE |
16080 | should only be executed if the condition is false: however, if the mode |
16081 | of the comparison is CCFPEmode, then always execute the instruction -- we | |
16082 | do this because in these circumstances !GE does not necessarily imply LT; | |
16083 | in these cases the instruction pattern will take care to make sure that | |
16084 | an instruction containing %d will follow, thereby undoing the effects of | |
ddd5a7c1 | 16085 | doing this instruction unconditionally. |
9997d19d RE |
16086 | If CODE is 'N' then X is a floating point operand that must be negated |
16087 | before output. | |
16088 | If CODE is 'B' then output a bitwise inverted value of X (a const int). | |
16089 | If X is a REG and CODE is `M', output a ldm/stm style multi-reg. */ | |
944442bb | 16090 | static void |
e32bac5b | 16091 | arm_print_operand (FILE *stream, rtx x, int code) |
9997d19d RE |
16092 | { |
16093 | switch (code) | |
16094 | { | |
16095 | case '@': | |
f3139301 | 16096 | fputs (ASM_COMMENT_START, stream); |
9997d19d RE |
16097 | return; |
16098 | ||
d5b7b3ae RE |
16099 | case '_': |
16100 | fputs (user_label_prefix, stream); | |
16101 | return; | |
f676971a | 16102 | |
9997d19d | 16103 | case '|': |
f3139301 | 16104 | fputs (REGISTER_PREFIX, stream); |
9997d19d RE |
16105 | return; |
16106 | ||
16107 | case '?': | |
5b3e6663 PB |
16108 | arm_print_condition (stream); |
16109 | return; | |
cca0a211 | 16110 | |
5b3e6663 PB |
16111 | case '(': |
16112 | /* Nothing in unified syntax, otherwise the current condition code. */ | |
16113 | if (!TARGET_UNIFIED_ASM) | |
16114 | arm_print_condition (stream); | |
16115 | break; | |
16116 | ||
16117 | case ')': | |
16118 | /* The current condition code in unified syntax, otherwise nothing. */ | |
16119 | if (TARGET_UNIFIED_ASM) | |
16120 | arm_print_condition (stream); | |
16121 | break; | |
16122 | ||
16123 | case '.': | |
16124 | /* The current condition code for a condition code setting instruction. | |
7a085dce | 16125 | Preceded by 's' in unified syntax, otherwise followed by 's'. */ |
5b3e6663 PB |
16126 | if (TARGET_UNIFIED_ASM) |
16127 | { | |
16128 | fputc('s', stream); | |
16129 | arm_print_condition (stream); | |
cca0a211 | 16130 | } |
5b3e6663 | 16131 | else |
cca0a211 | 16132 | { |
5b3e6663 PB |
16133 | arm_print_condition (stream); |
16134 | fputc('s', stream); | |
cca0a211 | 16135 | } |
9997d19d RE |
16136 | return; |
16137 | ||
5b3e6663 PB |
16138 | case '!': |
16139 | /* If the instruction is conditionally executed then print | |
16140 | the current condition code, otherwise print 's'. */ | |
16141 | gcc_assert (TARGET_THUMB2 && TARGET_UNIFIED_ASM); | |
16142 | if (current_insn_predicate) | |
16143 | arm_print_condition (stream); | |
16144 | else | |
16145 | fputc('s', stream); | |
16146 | break; | |
16147 | ||
88f77cba | 16148 | /* %# is a "break" sequence. It doesn't output anything, but is used to |
cea618ac | 16149 | separate e.g. operand numbers from following text, if that text consists |
88f77cba JB |
16150 | of further digits which we don't want to be part of the operand |
16151 | number. */ | |
16152 | case '#': | |
16153 | return; | |
16154 | ||
9997d19d RE |
16155 | case 'N': |
16156 | { | |
16157 | REAL_VALUE_TYPE r; | |
16158 | REAL_VALUE_FROM_CONST_DOUBLE (r, x); | |
d49b6e1e | 16159 | r = real_value_negate (&r); |
9997d19d RE |
16160 | fprintf (stream, "%s", fp_const_from_val (&r)); |
16161 | } | |
16162 | return; | |
16163 | ||
571191af | 16164 | /* An integer or symbol address without a preceding # sign. */ |
88f77cba | 16165 | case 'c': |
571191af PB |
16166 | switch (GET_CODE (x)) |
16167 | { | |
16168 | case CONST_INT: | |
16169 | fprintf (stream, HOST_WIDE_INT_PRINT_DEC, INTVAL (x)); | |
16170 | break; | |
16171 | ||
16172 | case SYMBOL_REF: | |
16173 | output_addr_const (stream, x); | |
16174 | break; | |
16175 | ||
16176 | default: | |
16177 | gcc_unreachable (); | |
16178 | } | |
88f77cba JB |
16179 | return; |
16180 | ||
9997d19d RE |
16181 | case 'B': |
16182 | if (GET_CODE (x) == CONST_INT) | |
4bc74ece NC |
16183 | { |
16184 | HOST_WIDE_INT val; | |
5895f793 | 16185 | val = ARM_SIGN_EXTEND (~INTVAL (x)); |
36ba9cb8 | 16186 | fprintf (stream, HOST_WIDE_INT_PRINT_DEC, val); |
4bc74ece | 16187 | } |
9997d19d RE |
16188 | else |
16189 | { | |
16190 | putc ('~', stream); | |
16191 | output_addr_const (stream, x); | |
16192 | } | |
16193 | return; | |
16194 | ||
5b3e6663 PB |
16195 | case 'L': |
16196 | /* The low 16 bits of an immediate constant. */ | |
16197 | fprintf (stream, HOST_WIDE_INT_PRINT_DEC, INTVAL(x) & 0xffff); | |
16198 | return; | |
16199 | ||
9997d19d RE |
16200 | case 'i': |
16201 | fprintf (stream, "%s", arithmetic_instr (x, 1)); | |
16202 | return; | |
16203 | ||
9b6b54e2 NC |
16204 | /* Truncate Cirrus shift counts. */ |
16205 | case 's': | |
16206 | if (GET_CODE (x) == CONST_INT) | |
16207 | { | |
16208 | fprintf (stream, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0x3f); | |
16209 | return; | |
16210 | } | |
16211 | arm_print_operand (stream, x, 0); | |
16212 | return; | |
16213 | ||
9997d19d RE |
16214 | case 'I': |
16215 | fprintf (stream, "%s", arithmetic_instr (x, 0)); | |
16216 | return; | |
16217 | ||
16218 | case 'S': | |
16219 | { | |
16220 | HOST_WIDE_INT val; | |
beed32b8 RE |
16221 | const char *shift; |
16222 | ||
16223 | if (!shift_operator (x, SImode)) | |
16224 | { | |
16225 | output_operand_lossage ("invalid shift operand"); | |
16226 | break; | |
16227 | } | |
16228 | ||
16229 | shift = shift_op (x, &val); | |
9997d19d | 16230 | |
e2c671ba RE |
16231 | if (shift) |
16232 | { | |
beed32b8 | 16233 | fprintf (stream, ", %s ", shift); |
e2c671ba RE |
16234 | if (val == -1) |
16235 | arm_print_operand (stream, XEXP (x, 1), 0); | |
16236 | else | |
4a0a75dd | 16237 | fprintf (stream, "#" HOST_WIDE_INT_PRINT_DEC, val); |
e2c671ba | 16238 | } |
9997d19d RE |
16239 | } |
16240 | return; | |
16241 | ||
d5b7b3ae | 16242 | /* An explanation of the 'Q', 'R' and 'H' register operands: |
f676971a | 16243 | |
d5b7b3ae RE |
16244 | In a pair of registers containing a DI or DF value the 'Q' |
16245 | operand returns the register number of the register containing | |
093354e0 | 16246 | the least significant part of the value. The 'R' operand returns |
d5b7b3ae RE |
16247 | the register number of the register containing the most |
16248 | significant part of the value. | |
f676971a | 16249 | |
d5b7b3ae RE |
16250 | The 'H' operand returns the higher of the two register numbers. |
16251 | On a run where WORDS_BIG_ENDIAN is true the 'H' operand is the | |
093354e0 | 16252 | same as the 'Q' operand, since the most significant part of the |
d5b7b3ae RE |
16253 | value is held in the lower number register. The reverse is true |
16254 | on systems where WORDS_BIG_ENDIAN is false. | |
f676971a | 16255 | |
d5b7b3ae RE |
16256 | The purpose of these operands is to distinguish between cases |
16257 | where the endian-ness of the values is important (for example | |
16258 | when they are added together), and cases where the endian-ness | |
16259 | is irrelevant, but the order of register operations is important. | |
16260 | For example when loading a value from memory into a register | |
16261 | pair, the endian-ness does not matter. Provided that the value | |
16262 | from the lower memory address is put into the lower numbered | |
16263 | register, and the value from the higher address is put into the | |
16264 | higher numbered register, the load will work regardless of whether | |
16265 | the value being loaded is big-wordian or little-wordian. The | |
16266 | order of the two register loads can matter however, if the address | |
16267 | of the memory location is actually held in one of the registers | |
73160ba9 DJ |
16268 | being overwritten by the load. |
16269 | ||
16270 | The 'Q' and 'R' constraints are also available for 64-bit | |
16271 | constants. */ | |
c1c2bc04 | 16272 | case 'Q': |
73160ba9 DJ |
16273 | if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE) |
16274 | { | |
16275 | rtx part = gen_lowpart (SImode, x); | |
16276 | fprintf (stream, "#" HOST_WIDE_INT_PRINT_DEC, INTVAL (part)); | |
16277 | return; | |
16278 | } | |
16279 | ||
22de4c3d RE |
16280 | if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM) |
16281 | { | |
16282 | output_operand_lossage ("invalid operand for code '%c'", code); | |
16283 | return; | |
16284 | } | |
16285 | ||
d5b7b3ae | 16286 | asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 1 : 0)); |
c1c2bc04 RE |
16287 | return; |
16288 | ||
9997d19d | 16289 | case 'R': |
73160ba9 DJ |
16290 | if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE) |
16291 | { | |
16292 | enum machine_mode mode = GET_MODE (x); | |
16293 | rtx part; | |
16294 | ||
16295 | if (mode == VOIDmode) | |
16296 | mode = DImode; | |
16297 | part = gen_highpart_mode (SImode, mode, x); | |
16298 | fprintf (stream, "#" HOST_WIDE_INT_PRINT_DEC, INTVAL (part)); | |
16299 | return; | |
16300 | } | |
16301 | ||
22de4c3d RE |
16302 | if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM) |
16303 | { | |
16304 | output_operand_lossage ("invalid operand for code '%c'", code); | |
16305 | return; | |
16306 | } | |
16307 | ||
d5b7b3ae RE |
16308 | asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 0 : 1)); |
16309 | return; | |
16310 | ||
16311 | case 'H': | |
22de4c3d RE |
16312 | if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM) |
16313 | { | |
16314 | output_operand_lossage ("invalid operand for code '%c'", code); | |
16315 | return; | |
16316 | } | |
16317 | ||
d5b7b3ae | 16318 | asm_fprintf (stream, "%r", REGNO (x) + 1); |
9997d19d RE |
16319 | return; |
16320 | ||
88f77cba JB |
16321 | case 'J': |
16322 | if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM) | |
16323 | { | |
16324 | output_operand_lossage ("invalid operand for code '%c'", code); | |
16325 | return; | |
16326 | } | |
16327 | ||
16328 | asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 3 : 2)); | |
16329 | return; | |
16330 | ||
16331 | case 'K': | |
16332 | if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM) | |
16333 | { | |
16334 | output_operand_lossage ("invalid operand for code '%c'", code); | |
16335 | return; | |
16336 | } | |
16337 | ||
16338 | asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 2 : 3)); | |
16339 | return; | |
16340 | ||
9997d19d | 16341 | case 'm': |
f676971a | 16342 | asm_fprintf (stream, "%r", |
d5b7b3ae RE |
16343 | GET_CODE (XEXP (x, 0)) == REG |
16344 | ? REGNO (XEXP (x, 0)) : REGNO (XEXP (XEXP (x, 0), 0))); | |
9997d19d RE |
16345 | return; |
16346 | ||
16347 | case 'M': | |
dd18ae56 | 16348 | asm_fprintf (stream, "{%r-%r}", |
d5b7b3ae | 16349 | REGNO (x), |
e9d7b180 | 16350 | REGNO (x) + ARM_NUM_REGS (GET_MODE (x)) - 1); |
9997d19d RE |
16351 | return; |
16352 | ||
88f77cba JB |
16353 | /* Like 'M', but writing doubleword vector registers, for use by Neon |
16354 | insns. */ | |
16355 | case 'h': | |
16356 | { | |
16357 | int regno = (REGNO (x) - FIRST_VFP_REGNUM) / 2; | |
16358 | int numregs = ARM_NUM_REGS (GET_MODE (x)) / 2; | |
16359 | if (numregs == 1) | |
16360 | asm_fprintf (stream, "{d%d}", regno); | |
16361 | else | |
16362 | asm_fprintf (stream, "{d%d-d%d}", regno, regno + numregs - 1); | |
16363 | } | |
16364 | return; | |
16365 | ||
9997d19d | 16366 | case 'd': |
64e92a26 RE |
16367 | /* CONST_TRUE_RTX means always -- that's the default. */ |
16368 | if (x == const_true_rtx) | |
d5b7b3ae | 16369 | return; |
f676971a | 16370 | |
22de4c3d RE |
16371 | if (!COMPARISON_P (x)) |
16372 | { | |
16373 | output_operand_lossage ("invalid operand for code '%c'", code); | |
16374 | return; | |
16375 | } | |
16376 | ||
defc0463 RE |
16377 | fputs (arm_condition_codes[get_arm_condition_code (x)], |
16378 | stream); | |
9997d19d RE |
16379 | return; |
16380 | ||
16381 | case 'D': | |
112cdef5 | 16382 | /* CONST_TRUE_RTX means not always -- i.e. never. We shouldn't ever |
64e92a26 RE |
16383 | want to do that. */ |
16384 | if (x == const_true_rtx) | |
22de4c3d | 16385 | { |
4dad0aca | 16386 | output_operand_lossage ("instruction never executed"); |
22de4c3d RE |
16387 | return; |
16388 | } | |
16389 | if (!COMPARISON_P (x)) | |
16390 | { | |
16391 | output_operand_lossage ("invalid operand for code '%c'", code); | |
16392 | return; | |
16393 | } | |
d5b7b3ae | 16394 | |
defc0463 RE |
16395 | fputs (arm_condition_codes[ARM_INVERSE_CONDITION_CODE |
16396 | (get_arm_condition_code (x))], | |
16397 | stream); | |
9997d19d RE |
16398 | return; |
16399 | ||
9b6b54e2 NC |
16400 | /* Cirrus registers can be accessed in a variety of ways: |
16401 | single floating point (f) | |
16402 | double floating point (d) | |
16403 | 32bit integer (fx) | |
16404 | 64bit integer (dx). */ | |
16405 | case 'W': /* Cirrus register in F mode. */ | |
16406 | case 'X': /* Cirrus register in D mode. */ | |
16407 | case 'Y': /* Cirrus register in FX mode. */ | |
16408 | case 'Z': /* Cirrus register in DX mode. */ | |
e6d29d15 NS |
16409 | gcc_assert (GET_CODE (x) == REG |
16410 | && REGNO_REG_CLASS (REGNO (x)) == CIRRUS_REGS); | |
9b6b54e2 NC |
16411 | |
16412 | fprintf (stream, "mv%s%s", | |
16413 | code == 'W' ? "f" | |
16414 | : code == 'X' ? "d" | |
16415 | : code == 'Y' ? "fx" : "dx", reg_names[REGNO (x)] + 2); | |
16416 | ||
16417 | return; | |
16418 | ||
16419 | /* Print cirrus register in the mode specified by the register's mode. */ | |
16420 | case 'V': | |
16421 | { | |
16422 | int mode = GET_MODE (x); | |
16423 | ||
16424 | if (GET_CODE (x) != REG || REGNO_REG_CLASS (REGNO (x)) != CIRRUS_REGS) | |
22de4c3d RE |
16425 | { |
16426 | output_operand_lossage ("invalid operand for code '%c'", code); | |
16427 | return; | |
16428 | } | |
9b6b54e2 NC |
16429 | |
16430 | fprintf (stream, "mv%s%s", | |
16431 | mode == DFmode ? "d" | |
16432 | : mode == SImode ? "fx" | |
16433 | : mode == DImode ? "dx" | |
16434 | : "f", reg_names[REGNO (x)] + 2); | |
16435 | ||
16436 | return; | |
16437 | } | |
16438 | ||
5a9335ef NC |
16439 | case 'U': |
16440 | if (GET_CODE (x) != REG | |
16441 | || REGNO (x) < FIRST_IWMMXT_GR_REGNUM | |
16442 | || REGNO (x) > LAST_IWMMXT_GR_REGNUM) | |
16443 | /* Bad value for wCG register number. */ | |
22de4c3d RE |
16444 | { |
16445 | output_operand_lossage ("invalid operand for code '%c'", code); | |
16446 | return; | |
16447 | } | |
16448 | ||
5a9335ef NC |
16449 | else |
16450 | fprintf (stream, "%d", REGNO (x) - FIRST_IWMMXT_GR_REGNUM); | |
16451 | return; | |
16452 | ||
16453 | /* Print an iWMMXt control register name. */ | |
16454 | case 'w': | |
16455 | if (GET_CODE (x) != CONST_INT | |
16456 | || INTVAL (x) < 0 | |
16457 | || INTVAL (x) >= 16) | |
16458 | /* Bad value for wC register number. */ | |
22de4c3d RE |
16459 | { |
16460 | output_operand_lossage ("invalid operand for code '%c'", code); | |
16461 | return; | |
16462 | } | |
16463 | ||
5a9335ef NC |
16464 | else |
16465 | { | |
16466 | static const char * wc_reg_names [16] = | |
16467 | { | |
16468 | "wCID", "wCon", "wCSSF", "wCASF", | |
16469 | "wC4", "wC5", "wC6", "wC7", | |
16470 | "wCGR0", "wCGR1", "wCGR2", "wCGR3", | |
16471 | "wC12", "wC13", "wC14", "wC15" | |
16472 | }; | |
f676971a | 16473 | |
5a9335ef NC |
16474 | fprintf (stream, wc_reg_names [INTVAL (x)]); |
16475 | } | |
16476 | return; | |
16477 | ||
e0dc3601 PB |
16478 | /* Print the high single-precision register of a VFP double-precision |
16479 | register. */ | |
16480 | case 'p': | |
16481 | { | |
16482 | int mode = GET_MODE (x); | |
16483 | int regno; | |
16484 | ||
16485 | if (GET_MODE_SIZE (mode) != 8 || GET_CODE (x) != REG) | |
16486 | { | |
16487 | output_operand_lossage ("invalid operand for code '%c'", code); | |
16488 | return; | |
16489 | } | |
16490 | ||
16491 | regno = REGNO (x); | |
16492 | if (!VFP_REGNO_OK_FOR_DOUBLE (regno)) | |
16493 | { | |
16494 | output_operand_lossage ("invalid operand for code '%c'", code); | |
16495 | return; | |
16496 | } | |
16497 | ||
16498 | fprintf (stream, "s%d", regno - FIRST_VFP_REGNUM + 1); | |
16499 | } | |
16500 | return; | |
16501 | ||
88f77cba | 16502 | /* Print a VFP/Neon double precision or quad precision register name. */ |
9b66ebb1 | 16503 | case 'P': |
88f77cba | 16504 | case 'q': |
9b66ebb1 PB |
16505 | { |
16506 | int mode = GET_MODE (x); | |
88f77cba JB |
16507 | int is_quad = (code == 'q'); |
16508 | int regno; | |
9b66ebb1 | 16509 | |
88f77cba | 16510 | if (GET_MODE_SIZE (mode) != (is_quad ? 16 : 8)) |
22de4c3d RE |
16511 | { |
16512 | output_operand_lossage ("invalid operand for code '%c'", code); | |
16513 | return; | |
16514 | } | |
9b66ebb1 PB |
16515 | |
16516 | if (GET_CODE (x) != REG | |
16517 | || !IS_VFP_REGNUM (REGNO (x))) | |
22de4c3d RE |
16518 | { |
16519 | output_operand_lossage ("invalid operand for code '%c'", code); | |
16520 | return; | |
16521 | } | |
9b66ebb1 | 16522 | |
88f77cba JB |
16523 | regno = REGNO (x); |
16524 | if ((is_quad && !NEON_REGNO_OK_FOR_QUAD (regno)) | |
16525 | || (!is_quad && !VFP_REGNO_OK_FOR_DOUBLE (regno))) | |
22de4c3d RE |
16526 | { |
16527 | output_operand_lossage ("invalid operand for code '%c'", code); | |
16528 | return; | |
16529 | } | |
9b66ebb1 | 16530 | |
88f77cba JB |
16531 | fprintf (stream, "%c%d", is_quad ? 'q' : 'd', |
16532 | (regno - FIRST_VFP_REGNUM) >> (is_quad ? 2 : 1)); | |
16533 | } | |
16534 | return; | |
16535 | ||
16536 | /* These two codes print the low/high doubleword register of a Neon quad | |
16537 | register, respectively. For pair-structure types, can also print | |
16538 | low/high quadword registers. */ | |
16539 | case 'e': | |
16540 | case 'f': | |
16541 | { | |
16542 | int mode = GET_MODE (x); | |
16543 | int regno; | |
16544 | ||
16545 | if ((GET_MODE_SIZE (mode) != 16 | |
16546 | && GET_MODE_SIZE (mode) != 32) || GET_CODE (x) != REG) | |
16547 | { | |
16548 | output_operand_lossage ("invalid operand for code '%c'", code); | |
16549 | return; | |
16550 | } | |
16551 | ||
16552 | regno = REGNO (x); | |
16553 | if (!NEON_REGNO_OK_FOR_QUAD (regno)) | |
16554 | { | |
16555 | output_operand_lossage ("invalid operand for code '%c'", code); | |
16556 | return; | |
16557 | } | |
16558 | ||
16559 | if (GET_MODE_SIZE (mode) == 16) | |
16560 | fprintf (stream, "d%d", ((regno - FIRST_VFP_REGNUM) >> 1) | |
16561 | + (code == 'f' ? 1 : 0)); | |
16562 | else | |
16563 | fprintf (stream, "q%d", ((regno - FIRST_VFP_REGNUM) >> 2) | |
16564 | + (code == 'f' ? 1 : 0)); | |
9b66ebb1 PB |
16565 | } |
16566 | return; | |
16567 | ||
f1adb0a9 JB |
16568 | /* Print a VFPv3 floating-point constant, represented as an integer |
16569 | index. */ | |
16570 | case 'G': | |
16571 | { | |
16572 | int index = vfp3_const_double_index (x); | |
16573 | gcc_assert (index != -1); | |
16574 | fprintf (stream, "%d", index); | |
16575 | } | |
16576 | return; | |
16577 | ||
88f77cba JB |
16578 | /* Print bits representing opcode features for Neon. |
16579 | ||
16580 | Bit 0 is 1 for signed, 0 for unsigned. Floats count as signed | |
16581 | and polynomials as unsigned. | |
16582 | ||
16583 | Bit 1 is 1 for floats and polynomials, 0 for ordinary integers. | |
16584 | ||
16585 | Bit 2 is 1 for rounding functions, 0 otherwise. */ | |
16586 | ||
16587 | /* Identify the type as 's', 'u', 'p' or 'f'. */ | |
16588 | case 'T': | |
16589 | { | |
16590 | HOST_WIDE_INT bits = INTVAL (x); | |
16591 | fputc ("uspf"[bits & 3], stream); | |
16592 | } | |
16593 | return; | |
16594 | ||
16595 | /* Likewise, but signed and unsigned integers are both 'i'. */ | |
16596 | case 'F': | |
16597 | { | |
16598 | HOST_WIDE_INT bits = INTVAL (x); | |
16599 | fputc ("iipf"[bits & 3], stream); | |
16600 | } | |
16601 | return; | |
16602 | ||
16603 | /* As for 'T', but emit 'u' instead of 'p'. */ | |
16604 | case 't': | |
16605 | { | |
16606 | HOST_WIDE_INT bits = INTVAL (x); | |
16607 | fputc ("usuf"[bits & 3], stream); | |
16608 | } | |
16609 | return; | |
16610 | ||
16611 | /* Bit 2: rounding (vs none). */ | |
16612 | case 'O': | |
16613 | { | |
16614 | HOST_WIDE_INT bits = INTVAL (x); | |
16615 | fputs ((bits & 4) != 0 ? "r" : "", stream); | |
16616 | } | |
16617 | return; | |
16618 | ||
dc34db56 PB |
16619 | /* Memory operand for vld1/vst1 instruction. */ |
16620 | case 'A': | |
16621 | { | |
16622 | rtx addr; | |
16623 | bool postinc = FALSE; | |
c452684d JB |
16624 | unsigned align, modesize, align_bits; |
16625 | ||
dc34db56 PB |
16626 | gcc_assert (GET_CODE (x) == MEM); |
16627 | addr = XEXP (x, 0); | |
16628 | if (GET_CODE (addr) == POST_INC) | |
16629 | { | |
16630 | postinc = 1; | |
16631 | addr = XEXP (addr, 0); | |
16632 | } | |
c452684d JB |
16633 | asm_fprintf (stream, "[%r", REGNO (addr)); |
16634 | ||
16635 | /* We know the alignment of this access, so we can emit a hint in the | |
16636 | instruction (for some alignments) as an aid to the memory subsystem | |
16637 | of the target. */ | |
16638 | align = MEM_ALIGN (x) >> 3; | |
16639 | modesize = GET_MODE_SIZE (GET_MODE (x)); | |
16640 | ||
16641 | /* Only certain alignment specifiers are supported by the hardware. */ | |
16642 | if (modesize == 16 && (align % 32) == 0) | |
16643 | align_bits = 256; | |
16644 | else if ((modesize == 8 || modesize == 16) && (align % 16) == 0) | |
16645 | align_bits = 128; | |
16646 | else if ((align % 8) == 0) | |
16647 | align_bits = 64; | |
16648 | else | |
16649 | align_bits = 0; | |
16650 | ||
16651 | if (align_bits != 0) | |
16652 | asm_fprintf (stream, ":%d", align_bits); | |
16653 | ||
16654 | asm_fprintf (stream, "]"); | |
16655 | ||
dc34db56 PB |
16656 | if (postinc) |
16657 | fputs("!", stream); | |
16658 | } | |
16659 | return; | |
16660 | ||
029e79eb MS |
16661 | case 'C': |
16662 | { | |
16663 | rtx addr; | |
16664 | ||
16665 | gcc_assert (GET_CODE (x) == MEM); | |
16666 | addr = XEXP (x, 0); | |
16667 | gcc_assert (GET_CODE (addr) == REG); | |
16668 | asm_fprintf (stream, "[%r]", REGNO (addr)); | |
16669 | } | |
16670 | return; | |
16671 | ||
814a4c3b DJ |
16672 | /* Translate an S register number into a D register number and element index. */ |
16673 | case 'y': | |
16674 | { | |
16675 | int mode = GET_MODE (x); | |
16676 | int regno; | |
16677 | ||
16678 | if (GET_MODE_SIZE (mode) != 4 || GET_CODE (x) != REG) | |
16679 | { | |
16680 | output_operand_lossage ("invalid operand for code '%c'", code); | |
16681 | return; | |
16682 | } | |
16683 | ||
16684 | regno = REGNO (x); | |
16685 | if (!VFP_REGNO_OK_FOR_SINGLE (regno)) | |
16686 | { | |
16687 | output_operand_lossage ("invalid operand for code '%c'", code); | |
16688 | return; | |
16689 | } | |
16690 | ||
16691 | regno = regno - FIRST_VFP_REGNUM; | |
16692 | fprintf (stream, "d%d[%d]", regno / 2, regno % 2); | |
16693 | } | |
16694 | return; | |
16695 | ||
0fd8c3ad SL |
16696 | /* Register specifier for vld1.16/vst1.16. Translate the S register |
16697 | number into a D register number and element index. */ | |
16698 | case 'z': | |
16699 | { | |
16700 | int mode = GET_MODE (x); | |
16701 | int regno; | |
16702 | ||
16703 | if (GET_MODE_SIZE (mode) != 2 || GET_CODE (x) != REG) | |
16704 | { | |
16705 | output_operand_lossage ("invalid operand for code '%c'", code); | |
16706 | return; | |
16707 | } | |
16708 | ||
16709 | regno = REGNO (x); | |
16710 | if (!VFP_REGNO_OK_FOR_SINGLE (regno)) | |
16711 | { | |
16712 | output_operand_lossage ("invalid operand for code '%c'", code); | |
16713 | return; | |
16714 | } | |
16715 | ||
16716 | regno = regno - FIRST_VFP_REGNUM; | |
16717 | fprintf (stream, "d%d[%d]", regno/2, ((regno % 2) ? 2 : 0)); | |
16718 | } | |
16719 | return; | |
16720 | ||
9997d19d RE |
16721 | default: |
16722 | if (x == 0) | |
22de4c3d RE |
16723 | { |
16724 | output_operand_lossage ("missing operand"); | |
16725 | return; | |
16726 | } | |
9997d19d | 16727 | |
e6d29d15 | 16728 | switch (GET_CODE (x)) |
9997d19d | 16729 | { |
e6d29d15 NS |
16730 | case REG: |
16731 | asm_fprintf (stream, "%r", REGNO (x)); | |
16732 | break; | |
16733 | ||
16734 | case MEM: | |
9997d19d RE |
16735 | output_memory_reference_mode = GET_MODE (x); |
16736 | output_address (XEXP (x, 0)); | |
e6d29d15 NS |
16737 | break; |
16738 | ||
16739 | case CONST_DOUBLE: | |
88f77cba JB |
16740 | if (TARGET_NEON) |
16741 | { | |
16742 | char fpstr[20]; | |
16743 | real_to_decimal (fpstr, CONST_DOUBLE_REAL_VALUE (x), | |
16744 | sizeof (fpstr), 0, 1); | |
16745 | fprintf (stream, "#%s", fpstr); | |
16746 | } | |
16747 | else | |
16748 | fprintf (stream, "#%s", fp_immediate_constant (x)); | |
e6d29d15 NS |
16749 | break; |
16750 | ||
16751 | default: | |
16752 | gcc_assert (GET_CODE (x) != NEG); | |
9997d19d | 16753 | fputc ('#', stream); |
d58bc084 NS |
16754 | if (GET_CODE (x) == HIGH) |
16755 | { | |
16756 | fputs (":lower16:", stream); | |
16757 | x = XEXP (x, 0); | |
16758 | } | |
16759 | ||
9997d19d | 16760 | output_addr_const (stream, x); |
e6d29d15 | 16761 | break; |
9997d19d RE |
16762 | } |
16763 | } | |
16764 | } | |
cce8749e | 16765 | \f |
944442bb NF |
16766 | /* Target hook for printing a memory address. */ |
16767 | static void | |
16768 | arm_print_operand_address (FILE *stream, rtx x) | |
16769 | { | |
16770 | if (TARGET_32BIT) | |
16771 | { | |
16772 | int is_minus = GET_CODE (x) == MINUS; | |
16773 | ||
16774 | if (GET_CODE (x) == REG) | |
16775 | asm_fprintf (stream, "[%r, #0]", REGNO (x)); | |
16776 | else if (GET_CODE (x) == PLUS || is_minus) | |
16777 | { | |
16778 | rtx base = XEXP (x, 0); | |
16779 | rtx index = XEXP (x, 1); | |
16780 | HOST_WIDE_INT offset = 0; | |
16781 | if (GET_CODE (base) != REG | |
16782 | || (GET_CODE (index) == REG && REGNO (index) == SP_REGNUM)) | |
16783 | { | |
16784 | /* Ensure that BASE is a register. */ | |
16785 | /* (one of them must be). */ | |
16786 | /* Also ensure the SP is not used as in index register. */ | |
16787 | rtx temp = base; | |
16788 | base = index; | |
16789 | index = temp; | |
16790 | } | |
16791 | switch (GET_CODE (index)) | |
16792 | { | |
16793 | case CONST_INT: | |
16794 | offset = INTVAL (index); | |
16795 | if (is_minus) | |
16796 | offset = -offset; | |
16797 | asm_fprintf (stream, "[%r, #%wd]", | |
16798 | REGNO (base), offset); | |
16799 | break; | |
16800 | ||
16801 | case REG: | |
16802 | asm_fprintf (stream, "[%r, %s%r]", | |
16803 | REGNO (base), is_minus ? "-" : "", | |
16804 | REGNO (index)); | |
16805 | break; | |
16806 | ||
16807 | case MULT: | |
16808 | case ASHIFTRT: | |
16809 | case LSHIFTRT: | |
16810 | case ASHIFT: | |
16811 | case ROTATERT: | |
16812 | { | |
16813 | asm_fprintf (stream, "[%r, %s%r", | |
16814 | REGNO (base), is_minus ? "-" : "", | |
16815 | REGNO (XEXP (index, 0))); | |
16816 | arm_print_operand (stream, index, 'S'); | |
16817 | fputs ("]", stream); | |
16818 | break; | |
16819 | } | |
16820 | ||
16821 | default: | |
16822 | gcc_unreachable (); | |
16823 | } | |
16824 | } | |
16825 | else if (GET_CODE (x) == PRE_INC || GET_CODE (x) == POST_INC | |
16826 | || GET_CODE (x) == PRE_DEC || GET_CODE (x) == POST_DEC) | |
16827 | { | |
16828 | extern enum machine_mode output_memory_reference_mode; | |
16829 | ||
16830 | gcc_assert (GET_CODE (XEXP (x, 0)) == REG); | |
16831 | ||
16832 | if (GET_CODE (x) == PRE_DEC || GET_CODE (x) == PRE_INC) | |
16833 | asm_fprintf (stream, "[%r, #%s%d]!", | |
16834 | REGNO (XEXP (x, 0)), | |
16835 | GET_CODE (x) == PRE_DEC ? "-" : "", | |
16836 | GET_MODE_SIZE (output_memory_reference_mode)); | |
16837 | else | |
16838 | asm_fprintf (stream, "[%r], #%s%d", | |
16839 | REGNO (XEXP (x, 0)), | |
16840 | GET_CODE (x) == POST_DEC ? "-" : "", | |
16841 | GET_MODE_SIZE (output_memory_reference_mode)); | |
16842 | } | |
16843 | else if (GET_CODE (x) == PRE_MODIFY) | |
16844 | { | |
16845 | asm_fprintf (stream, "[%r, ", REGNO (XEXP (x, 0))); | |
16846 | if (GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT) | |
16847 | asm_fprintf (stream, "#%wd]!", | |
16848 | INTVAL (XEXP (XEXP (x, 1), 1))); | |
16849 | else | |
16850 | asm_fprintf (stream, "%r]!", | |
16851 | REGNO (XEXP (XEXP (x, 1), 1))); | |
16852 | } | |
16853 | else if (GET_CODE (x) == POST_MODIFY) | |
16854 | { | |
16855 | asm_fprintf (stream, "[%r], ", REGNO (XEXP (x, 0))); | |
16856 | if (GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT) | |
16857 | asm_fprintf (stream, "#%wd", | |
16858 | INTVAL (XEXP (XEXP (x, 1), 1))); | |
16859 | else | |
16860 | asm_fprintf (stream, "%r", | |
16861 | REGNO (XEXP (XEXP (x, 1), 1))); | |
16862 | } | |
16863 | else output_addr_const (stream, x); | |
16864 | } | |
16865 | else | |
16866 | { | |
16867 | if (GET_CODE (x) == REG) | |
16868 | asm_fprintf (stream, "[%r]", REGNO (x)); | |
16869 | else if (GET_CODE (x) == POST_INC) | |
16870 | asm_fprintf (stream, "%r!", REGNO (XEXP (x, 0))); | |
16871 | else if (GET_CODE (x) == PLUS) | |
16872 | { | |
16873 | gcc_assert (GET_CODE (XEXP (x, 0)) == REG); | |
16874 | if (GET_CODE (XEXP (x, 1)) == CONST_INT) | |
16875 | asm_fprintf (stream, "[%r, #%wd]", | |
16876 | REGNO (XEXP (x, 0)), | |
16877 | INTVAL (XEXP (x, 1))); | |
16878 | else | |
16879 | asm_fprintf (stream, "[%r, %r]", | |
16880 | REGNO (XEXP (x, 0)), | |
16881 | REGNO (XEXP (x, 1))); | |
16882 | } | |
16883 | else | |
16884 | output_addr_const (stream, x); | |
16885 | } | |
16886 | } | |
16887 | \f | |
16888 | /* Target hook for indicating whether a punctuation character for | |
16889 | TARGET_PRINT_OPERAND is valid. */ | |
16890 | static bool | |
16891 | arm_print_operand_punct_valid_p (unsigned char code) | |
16892 | { | |
16893 | return (code == '@' || code == '|' || code == '.' | |
16894 | || code == '(' || code == ')' || code == '#' | |
16895 | || (TARGET_32BIT && (code == '?')) | |
16896 | || (TARGET_THUMB2 && (code == '!')) | |
16897 | || (TARGET_THUMB && (code == '_'))); | |
16898 | } | |
16899 | \f | |
301d03af RS |
16900 | /* Target hook for assembling integer objects. The ARM version needs to |
16901 | handle word-sized values specially. */ | |
301d03af | 16902 | static bool |
e32bac5b | 16903 | arm_assemble_integer (rtx x, unsigned int size, int aligned_p) |
301d03af | 16904 | { |
88f77cba JB |
16905 | enum machine_mode mode; |
16906 | ||
301d03af RS |
16907 | if (size == UNITS_PER_WORD && aligned_p) |
16908 | { | |
16909 | fputs ("\t.word\t", asm_out_file); | |
16910 | output_addr_const (asm_out_file, x); | |
16911 | ||
16912 | /* Mark symbols as position independent. We only do this in the | |
d6b4baa4 | 16913 | .text segment, not in the .data segment. */ |
301d03af RS |
16914 | if (NEED_GOT_RELOC && flag_pic && making_const_table && |
16915 | (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)) | |
16916 | { | |
9403b7f7 RS |
16917 | /* See legitimize_pic_address for an explanation of the |
16918 | TARGET_VXWORKS_RTP check. */ | |
16919 | if (TARGET_VXWORKS_RTP | |
16920 | || (GET_CODE (x) == SYMBOL_REF && !SYMBOL_REF_LOCAL_P (x))) | |
301d03af | 16921 | fputs ("(GOT)", asm_out_file); |
9403b7f7 RS |
16922 | else |
16923 | fputs ("(GOTOFF)", asm_out_file); | |
301d03af RS |
16924 | } |
16925 | fputc ('\n', asm_out_file); | |
16926 | return true; | |
16927 | } | |
1d6e90ac | 16928 | |
88f77cba JB |
16929 | mode = GET_MODE (x); |
16930 | ||
16931 | if (arm_vector_mode_supported_p (mode)) | |
5a9335ef NC |
16932 | { |
16933 | int i, units; | |
16934 | ||
e6d29d15 | 16935 | gcc_assert (GET_CODE (x) == CONST_VECTOR); |
5a9335ef NC |
16936 | |
16937 | units = CONST_VECTOR_NUNITS (x); | |
88f77cba | 16938 | size = GET_MODE_SIZE (GET_MODE_INNER (mode)); |
5a9335ef | 16939 | |
88f77cba JB |
16940 | if (GET_MODE_CLASS (mode) == MODE_VECTOR_INT) |
16941 | for (i = 0; i < units; i++) | |
16942 | { | |
874d42b9 | 16943 | rtx elt = CONST_VECTOR_ELT (x, i); |
88f77cba JB |
16944 | assemble_integer |
16945 | (elt, size, i == 0 ? BIGGEST_ALIGNMENT : size * BITS_PER_UNIT, 1); | |
16946 | } | |
16947 | else | |
16948 | for (i = 0; i < units; i++) | |
16949 | { | |
16950 | rtx elt = CONST_VECTOR_ELT (x, i); | |
16951 | REAL_VALUE_TYPE rval; | |
5a9335ef | 16952 | |
88f77cba JB |
16953 | REAL_VALUE_FROM_CONST_DOUBLE (rval, elt); |
16954 | ||
16955 | assemble_real | |
16956 | (rval, GET_MODE_INNER (mode), | |
16957 | i == 0 ? BIGGEST_ALIGNMENT : size * BITS_PER_UNIT); | |
16958 | } | |
5a9335ef NC |
16959 | |
16960 | return true; | |
16961 | } | |
16962 | ||
301d03af RS |
16963 | return default_assemble_integer (x, size, aligned_p); |
16964 | } | |
7abc66b1 | 16965 | |
7abc66b1 | 16966 | static void |
9f296620 | 16967 | arm_elf_asm_cdtor (rtx symbol, int priority, bool is_ctor) |
7abc66b1 | 16968 | { |
50603eed PB |
16969 | section *s; |
16970 | ||
7abc66b1 JB |
16971 | if (!TARGET_AAPCS_BASED) |
16972 | { | |
9f296620 MM |
16973 | (is_ctor ? |
16974 | default_named_section_asm_out_constructor | |
16975 | : default_named_section_asm_out_destructor) (symbol, priority); | |
7abc66b1 JB |
16976 | return; |
16977 | } | |
16978 | ||
16979 | /* Put these in the .init_array section, using a special relocation. */ | |
50603eed PB |
16980 | if (priority != DEFAULT_INIT_PRIORITY) |
16981 | { | |
16982 | char buf[18]; | |
9f296620 MM |
16983 | sprintf (buf, "%s.%.5u", |
16984 | is_ctor ? ".init_array" : ".fini_array", | |
16985 | priority); | |
50603eed PB |
16986 | s = get_section (buf, SECTION_WRITE, NULL_TREE); |
16987 | } | |
9f296620 | 16988 | else if (is_ctor) |
50603eed | 16989 | s = ctors_section; |
9f296620 MM |
16990 | else |
16991 | s = dtors_section; | |
50603eed PB |
16992 | |
16993 | switch_to_section (s); | |
7abc66b1 JB |
16994 | assemble_align (POINTER_SIZE); |
16995 | fputs ("\t.word\t", asm_out_file); | |
16996 | output_addr_const (asm_out_file, symbol); | |
16997 | fputs ("(target1)\n", asm_out_file); | |
16998 | } | |
9f296620 MM |
16999 | |
17000 | /* Add a function to the list of static constructors. */ | |
17001 | ||
17002 | static void | |
17003 | arm_elf_asm_constructor (rtx symbol, int priority) | |
17004 | { | |
17005 | arm_elf_asm_cdtor (symbol, priority, /*is_ctor=*/true); | |
17006 | } | |
17007 | ||
17008 | /* Add a function to the list of static destructors. */ | |
17009 | ||
17010 | static void | |
17011 | arm_elf_asm_destructor (rtx symbol, int priority) | |
17012 | { | |
17013 | arm_elf_asm_cdtor (symbol, priority, /*is_ctor=*/false); | |
17014 | } | |
301d03af | 17015 | \f |
cce8749e CH |
17016 | /* A finite state machine takes care of noticing whether or not instructions |
17017 | can be conditionally executed, and thus decrease execution time and code | |
17018 | size by deleting branch instructions. The fsm is controlled by | |
17019 | final_prescan_insn, and controls the actions of ASM_OUTPUT_OPCODE. */ | |
17020 | ||
17021 | /* The state of the fsm controlling condition codes are: | |
17022 | 0: normal, do nothing special | |
17023 | 1: make ASM_OUTPUT_OPCODE not output this instruction | |
17024 | 2: make ASM_OUTPUT_OPCODE not output this instruction | |
17025 | 3: make instructions conditional | |
17026 | 4: make instructions conditional | |
17027 | ||
17028 | State transitions (state->state by whom under condition): | |
17029 | 0 -> 1 final_prescan_insn if the `target' is a label | |
17030 | 0 -> 2 final_prescan_insn if the `target' is an unconditional branch | |
17031 | 1 -> 3 ASM_OUTPUT_OPCODE after not having output the conditional branch | |
17032 | 2 -> 4 ASM_OUTPUT_OPCODE after not having output the conditional branch | |
4977bab6 | 17033 | 3 -> 0 (*targetm.asm_out.internal_label) if the `target' label is reached |
cce8749e CH |
17034 | (the target label has CODE_LABEL_NUMBER equal to arm_target_label). |
17035 | 4 -> 0 final_prescan_insn if the `target' unconditional branch is reached | |
17036 | (the target insn is arm_target_insn). | |
17037 | ||
ff9940b0 RE |
17038 | If the jump clobbers the conditions then we use states 2 and 4. |
17039 | ||
17040 | A similar thing can be done with conditional return insns. | |
17041 | ||
cce8749e CH |
17042 | XXX In case the `target' is an unconditional branch, this conditionalising |
17043 | of the instructions always reduces code size, but not always execution | |
17044 | time. But then, I want to reduce the code size to somewhere near what | |
17045 | /bin/cc produces. */ | |
17046 | ||
5b3e6663 PB |
17047 | /* In addition to this, state is maintained for Thumb-2 COND_EXEC |
17048 | instructions. When a COND_EXEC instruction is seen the subsequent | |
17049 | instructions are scanned so that multiple conditional instructions can be | |
17050 | combined into a single IT block. arm_condexec_count and arm_condexec_mask | |
17051 | specify the length and true/false mask for the IT block. These will be | |
17052 | decremented/zeroed by arm_asm_output_opcode as the insns are output. */ | |
17053 | ||
cce8749e CH |
17054 | /* Returns the index of the ARM condition code string in |
17055 | `arm_condition_codes'. COMPARISON should be an rtx like | |
17056 | `(eq (...) (...))'. */ | |
84ed5e79 | 17057 | static enum arm_cond_code |
e32bac5b | 17058 | get_arm_condition_code (rtx comparison) |
cce8749e | 17059 | { |
5165176d | 17060 | enum machine_mode mode = GET_MODE (XEXP (comparison, 0)); |
81f40b79 | 17061 | enum arm_cond_code code; |
1d6e90ac | 17062 | enum rtx_code comp_code = GET_CODE (comparison); |
5165176d RE |
17063 | |
17064 | if (GET_MODE_CLASS (mode) != MODE_CC) | |
84ed5e79 | 17065 | mode = SELECT_CC_MODE (comp_code, XEXP (comparison, 0), |
5165176d RE |
17066 | XEXP (comparison, 1)); |
17067 | ||
17068 | switch (mode) | |
cce8749e | 17069 | { |
84ed5e79 RE |
17070 | case CC_DNEmode: code = ARM_NE; goto dominance; |
17071 | case CC_DEQmode: code = ARM_EQ; goto dominance; | |
17072 | case CC_DGEmode: code = ARM_GE; goto dominance; | |
17073 | case CC_DGTmode: code = ARM_GT; goto dominance; | |
17074 | case CC_DLEmode: code = ARM_LE; goto dominance; | |
17075 | case CC_DLTmode: code = ARM_LT; goto dominance; | |
17076 | case CC_DGEUmode: code = ARM_CS; goto dominance; | |
17077 | case CC_DGTUmode: code = ARM_HI; goto dominance; | |
17078 | case CC_DLEUmode: code = ARM_LS; goto dominance; | |
17079 | case CC_DLTUmode: code = ARM_CC; | |
17080 | ||
17081 | dominance: | |
e6d29d15 | 17082 | gcc_assert (comp_code == EQ || comp_code == NE); |
84ed5e79 RE |
17083 | |
17084 | if (comp_code == EQ) | |
17085 | return ARM_INVERSE_CONDITION_CODE (code); | |
17086 | return code; | |
17087 | ||
5165176d | 17088 | case CC_NOOVmode: |
84ed5e79 | 17089 | switch (comp_code) |
5165176d | 17090 | { |
84ed5e79 RE |
17091 | case NE: return ARM_NE; |
17092 | case EQ: return ARM_EQ; | |
17093 | case GE: return ARM_PL; | |
17094 | case LT: return ARM_MI; | |
e6d29d15 | 17095 | default: gcc_unreachable (); |
5165176d RE |
17096 | } |
17097 | ||
17098 | case CC_Zmode: | |
84ed5e79 | 17099 | switch (comp_code) |
5165176d | 17100 | { |
84ed5e79 RE |
17101 | case NE: return ARM_NE; |
17102 | case EQ: return ARM_EQ; | |
e6d29d15 | 17103 | default: gcc_unreachable (); |
5165176d RE |
17104 | } |
17105 | ||
defc0463 RE |
17106 | case CC_Nmode: |
17107 | switch (comp_code) | |
17108 | { | |
17109 | case NE: return ARM_MI; | |
17110 | case EQ: return ARM_PL; | |
e6d29d15 | 17111 | default: gcc_unreachable (); |
defc0463 RE |
17112 | } |
17113 | ||
5165176d | 17114 | case CCFPEmode: |
e45b72c4 RE |
17115 | case CCFPmode: |
17116 | /* These encodings assume that AC=1 in the FPA system control | |
17117 | byte. This allows us to handle all cases except UNEQ and | |
17118 | LTGT. */ | |
84ed5e79 RE |
17119 | switch (comp_code) |
17120 | { | |
17121 | case GE: return ARM_GE; | |
17122 | case GT: return ARM_GT; | |
17123 | case LE: return ARM_LS; | |
17124 | case LT: return ARM_MI; | |
e45b72c4 RE |
17125 | case NE: return ARM_NE; |
17126 | case EQ: return ARM_EQ; | |
17127 | case ORDERED: return ARM_VC; | |
17128 | case UNORDERED: return ARM_VS; | |
17129 | case UNLT: return ARM_LT; | |
17130 | case UNLE: return ARM_LE; | |
17131 | case UNGT: return ARM_HI; | |
17132 | case UNGE: return ARM_PL; | |
17133 | /* UNEQ and LTGT do not have a representation. */ | |
17134 | case UNEQ: /* Fall through. */ | |
17135 | case LTGT: /* Fall through. */ | |
e6d29d15 | 17136 | default: gcc_unreachable (); |
84ed5e79 RE |
17137 | } |
17138 | ||
17139 | case CC_SWPmode: | |
17140 | switch (comp_code) | |
17141 | { | |
17142 | case NE: return ARM_NE; | |
17143 | case EQ: return ARM_EQ; | |
17144 | case GE: return ARM_LE; | |
17145 | case GT: return ARM_LT; | |
17146 | case LE: return ARM_GE; | |
17147 | case LT: return ARM_GT; | |
17148 | case GEU: return ARM_LS; | |
17149 | case GTU: return ARM_CC; | |
17150 | case LEU: return ARM_CS; | |
17151 | case LTU: return ARM_HI; | |
e6d29d15 | 17152 | default: gcc_unreachable (); |
84ed5e79 RE |
17153 | } |
17154 | ||
bd9c7e23 RE |
17155 | case CC_Cmode: |
17156 | switch (comp_code) | |
18e8200f BS |
17157 | { |
17158 | case LTU: return ARM_CS; | |
17159 | case GEU: return ARM_CC; | |
17160 | default: gcc_unreachable (); | |
17161 | } | |
17162 | ||
73160ba9 DJ |
17163 | case CC_CZmode: |
17164 | switch (comp_code) | |
17165 | { | |
17166 | case NE: return ARM_NE; | |
17167 | case EQ: return ARM_EQ; | |
17168 | case GEU: return ARM_CS; | |
17169 | case GTU: return ARM_HI; | |
17170 | case LEU: return ARM_LS; | |
17171 | case LTU: return ARM_CC; | |
17172 | default: gcc_unreachable (); | |
17173 | } | |
17174 | ||
17175 | case CC_NCVmode: | |
17176 | switch (comp_code) | |
17177 | { | |
17178 | case GE: return ARM_GE; | |
17179 | case LT: return ARM_LT; | |
17180 | case GEU: return ARM_CS; | |
17181 | case LTU: return ARM_CC; | |
17182 | default: gcc_unreachable (); | |
17183 | } | |
17184 | ||
5165176d | 17185 | case CCmode: |
84ed5e79 | 17186 | switch (comp_code) |
5165176d | 17187 | { |
84ed5e79 RE |
17188 | case NE: return ARM_NE; |
17189 | case EQ: return ARM_EQ; | |
17190 | case GE: return ARM_GE; | |
17191 | case GT: return ARM_GT; | |
17192 | case LE: return ARM_LE; | |
17193 | case LT: return ARM_LT; | |
17194 | case GEU: return ARM_CS; | |
17195 | case GTU: return ARM_HI; | |
17196 | case LEU: return ARM_LS; | |
17197 | case LTU: return ARM_CC; | |
e6d29d15 | 17198 | default: gcc_unreachable (); |
5165176d RE |
17199 | } |
17200 | ||
e6d29d15 | 17201 | default: gcc_unreachable (); |
cce8749e | 17202 | } |
f3bb6135 | 17203 | } |
cce8749e | 17204 | |
44c7bd63 | 17205 | /* Tell arm_asm_output_opcode to output IT blocks for conditionally executed |
5b3e6663 PB |
17206 | instructions. */ |
17207 | void | |
17208 | thumb2_final_prescan_insn (rtx insn) | |
17209 | { | |
17210 | rtx first_insn = insn; | |
17211 | rtx body = PATTERN (insn); | |
17212 | rtx predicate; | |
17213 | enum arm_cond_code code; | |
17214 | int n; | |
17215 | int mask; | |
17216 | ||
17217 | /* Remove the previous insn from the count of insns to be output. */ | |
17218 | if (arm_condexec_count) | |
17219 | arm_condexec_count--; | |
17220 | ||
17221 | /* Nothing to do if we are already inside a conditional block. */ | |
17222 | if (arm_condexec_count) | |
17223 | return; | |
17224 | ||
17225 | if (GET_CODE (body) != COND_EXEC) | |
17226 | return; | |
17227 | ||
17228 | /* Conditional jumps are implemented directly. */ | |
17229 | if (GET_CODE (insn) == JUMP_INSN) | |
17230 | return; | |
17231 | ||
17232 | predicate = COND_EXEC_TEST (body); | |
17233 | arm_current_cc = get_arm_condition_code (predicate); | |
17234 | ||
17235 | n = get_attr_ce_count (insn); | |
17236 | arm_condexec_count = 1; | |
17237 | arm_condexec_mask = (1 << n) - 1; | |
17238 | arm_condexec_masklen = n; | |
17239 | /* See if subsequent instructions can be combined into the same block. */ | |
17240 | for (;;) | |
17241 | { | |
17242 | insn = next_nonnote_insn (insn); | |
17243 | ||
17244 | /* Jumping into the middle of an IT block is illegal, so a label or | |
17245 | barrier terminates the block. */ | |
17246 | if (GET_CODE (insn) != INSN && GET_CODE(insn) != JUMP_INSN) | |
17247 | break; | |
17248 | ||
17249 | body = PATTERN (insn); | |
17250 | /* USE and CLOBBER aren't really insns, so just skip them. */ | |
17251 | if (GET_CODE (body) == USE | |
17252 | || GET_CODE (body) == CLOBBER) | |
5b0202af | 17253 | continue; |
5b3e6663 | 17254 | |
7a085dce | 17255 | /* ??? Recognize conditional jumps, and combine them with IT blocks. */ |
5b3e6663 PB |
17256 | if (GET_CODE (body) != COND_EXEC) |
17257 | break; | |
17258 | /* Allow up to 4 conditionally executed instructions in a block. */ | |
17259 | n = get_attr_ce_count (insn); | |
17260 | if (arm_condexec_masklen + n > 4) | |
17261 | break; | |
17262 | ||
17263 | predicate = COND_EXEC_TEST (body); | |
17264 | code = get_arm_condition_code (predicate); | |
17265 | mask = (1 << n) - 1; | |
17266 | if (arm_current_cc == code) | |
17267 | arm_condexec_mask |= (mask << arm_condexec_masklen); | |
17268 | else if (arm_current_cc != ARM_INVERSE_CONDITION_CODE(code)) | |
17269 | break; | |
17270 | ||
17271 | arm_condexec_count++; | |
17272 | arm_condexec_masklen += n; | |
17273 | ||
17274 | /* A jump must be the last instruction in a conditional block. */ | |
17275 | if (GET_CODE(insn) == JUMP_INSN) | |
17276 | break; | |
17277 | } | |
17278 | /* Restore recog_data (getting the attributes of other insns can | |
17279 | destroy this array, but final.c assumes that it remains intact | |
17280 | across this call). */ | |
17281 | extract_constrain_insn_cached (first_insn); | |
17282 | } | |
17283 | ||
cce8749e | 17284 | void |
e32bac5b | 17285 | arm_final_prescan_insn (rtx insn) |
cce8749e CH |
17286 | { |
17287 | /* BODY will hold the body of INSN. */ | |
1d6e90ac | 17288 | rtx body = PATTERN (insn); |
cce8749e CH |
17289 | |
17290 | /* This will be 1 if trying to repeat the trick, and things need to be | |
17291 | reversed if it appears to fail. */ | |
17292 | int reverse = 0; | |
17293 | ||
6354dc9b | 17294 | /* If we start with a return insn, we only succeed if we find another one. */ |
ff9940b0 | 17295 | int seeking_return = 0; |
f676971a | 17296 | |
cce8749e CH |
17297 | /* START_INSN will hold the insn from where we start looking. This is the |
17298 | first insn after the following code_label if REVERSE is true. */ | |
17299 | rtx start_insn = insn; | |
17300 | ||
17301 | /* If in state 4, check if the target branch is reached, in order to | |
17302 | change back to state 0. */ | |
17303 | if (arm_ccfsm_state == 4) | |
17304 | { | |
17305 | if (insn == arm_target_insn) | |
f5a1b0d2 NC |
17306 | { |
17307 | arm_target_insn = NULL; | |
17308 | arm_ccfsm_state = 0; | |
17309 | } | |
cce8749e CH |
17310 | return; |
17311 | } | |
17312 | ||
17313 | /* If in state 3, it is possible to repeat the trick, if this insn is an | |
17314 | unconditional branch to a label, and immediately following this branch | |
17315 | is the previous target label which is only used once, and the label this | |
17316 | branch jumps to is not too far off. */ | |
17317 | if (arm_ccfsm_state == 3) | |
17318 | { | |
17319 | if (simplejump_p (insn)) | |
17320 | { | |
17321 | start_insn = next_nonnote_insn (start_insn); | |
17322 | if (GET_CODE (start_insn) == BARRIER) | |
17323 | { | |
17324 | /* XXX Isn't this always a barrier? */ | |
17325 | start_insn = next_nonnote_insn (start_insn); | |
17326 | } | |
17327 | if (GET_CODE (start_insn) == CODE_LABEL | |
17328 | && CODE_LABEL_NUMBER (start_insn) == arm_target_label | |
17329 | && LABEL_NUSES (start_insn) == 1) | |
17330 | reverse = TRUE; | |
17331 | else | |
17332 | return; | |
17333 | } | |
ff9940b0 RE |
17334 | else if (GET_CODE (body) == RETURN) |
17335 | { | |
17336 | start_insn = next_nonnote_insn (start_insn); | |
17337 | if (GET_CODE (start_insn) == BARRIER) | |
17338 | start_insn = next_nonnote_insn (start_insn); | |
17339 | if (GET_CODE (start_insn) == CODE_LABEL | |
17340 | && CODE_LABEL_NUMBER (start_insn) == arm_target_label | |
17341 | && LABEL_NUSES (start_insn) == 1) | |
17342 | { | |
17343 | reverse = TRUE; | |
17344 | seeking_return = 1; | |
17345 | } | |
17346 | else | |
17347 | return; | |
17348 | } | |
cce8749e CH |
17349 | else |
17350 | return; | |
17351 | } | |
17352 | ||
e6d29d15 | 17353 | gcc_assert (!arm_ccfsm_state || reverse); |
cce8749e CH |
17354 | if (GET_CODE (insn) != JUMP_INSN) |
17355 | return; | |
17356 | ||
f676971a | 17357 | /* This jump might be paralleled with a clobber of the condition codes |
ff9940b0 RE |
17358 | the jump should always come first */ |
17359 | if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0) | |
17360 | body = XVECEXP (body, 0, 0); | |
17361 | ||
cce8749e CH |
17362 | if (reverse |
17363 | || (GET_CODE (body) == SET && GET_CODE (SET_DEST (body)) == PC | |
17364 | && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE)) | |
17365 | { | |
bd9c7e23 RE |
17366 | int insns_skipped; |
17367 | int fail = FALSE, succeed = FALSE; | |
cce8749e CH |
17368 | /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */ |
17369 | int then_not_else = TRUE; | |
ff9940b0 | 17370 | rtx this_insn = start_insn, label = 0; |
cce8749e CH |
17371 | |
17372 | /* Register the insn jumped to. */ | |
17373 | if (reverse) | |
ff9940b0 RE |
17374 | { |
17375 | if (!seeking_return) | |
17376 | label = XEXP (SET_SRC (body), 0); | |
17377 | } | |
cce8749e CH |
17378 | else if (GET_CODE (XEXP (SET_SRC (body), 1)) == LABEL_REF) |
17379 | label = XEXP (XEXP (SET_SRC (body), 1), 0); | |
17380 | else if (GET_CODE (XEXP (SET_SRC (body), 2)) == LABEL_REF) | |
17381 | { | |
17382 | label = XEXP (XEXP (SET_SRC (body), 2), 0); | |
17383 | then_not_else = FALSE; | |
17384 | } | |
ff9940b0 RE |
17385 | else if (GET_CODE (XEXP (SET_SRC (body), 1)) == RETURN) |
17386 | seeking_return = 1; | |
17387 | else if (GET_CODE (XEXP (SET_SRC (body), 2)) == RETURN) | |
17388 | { | |
17389 | seeking_return = 1; | |
17390 | then_not_else = FALSE; | |
17391 | } | |
cce8749e | 17392 | else |
e6d29d15 | 17393 | gcc_unreachable (); |
cce8749e CH |
17394 | |
17395 | /* See how many insns this branch skips, and what kind of insns. If all | |
17396 | insns are okay, and the label or unconditional branch to the same | |
17397 | label is not too far away, succeed. */ | |
17398 | for (insns_skipped = 0; | |
b36ba79f | 17399 | !fail && !succeed && insns_skipped++ < max_insns_skipped;) |
cce8749e CH |
17400 | { |
17401 | rtx scanbody; | |
17402 | ||
17403 | this_insn = next_nonnote_insn (this_insn); | |
17404 | if (!this_insn) | |
17405 | break; | |
17406 | ||
cce8749e CH |
17407 | switch (GET_CODE (this_insn)) |
17408 | { | |
17409 | case CODE_LABEL: | |
17410 | /* Succeed if it is the target label, otherwise fail since | |
17411 | control falls in from somewhere else. */ | |
17412 | if (this_insn == label) | |
17413 | { | |
accbd151 | 17414 | arm_ccfsm_state = 1; |
cce8749e CH |
17415 | succeed = TRUE; |
17416 | } | |
17417 | else | |
17418 | fail = TRUE; | |
17419 | break; | |
17420 | ||
ff9940b0 | 17421 | case BARRIER: |
cce8749e | 17422 | /* Succeed if the following insn is the target label. |
f676971a EC |
17423 | Otherwise fail. |
17424 | If return insns are used then the last insn in a function | |
6354dc9b | 17425 | will be a barrier. */ |
cce8749e | 17426 | this_insn = next_nonnote_insn (this_insn); |
ff9940b0 | 17427 | if (this_insn && this_insn == label) |
cce8749e | 17428 | { |
accbd151 | 17429 | arm_ccfsm_state = 1; |
cce8749e CH |
17430 | succeed = TRUE; |
17431 | } | |
17432 | else | |
17433 | fail = TRUE; | |
17434 | break; | |
17435 | ||
ff9940b0 | 17436 | case CALL_INSN: |
68d560d4 RE |
17437 | /* The AAPCS says that conditional calls should not be |
17438 | used since they make interworking inefficient (the | |
17439 | linker can't transform BL<cond> into BLX). That's | |
17440 | only a problem if the machine has BLX. */ | |
17441 | if (arm_arch5) | |
17442 | { | |
17443 | fail = TRUE; | |
17444 | break; | |
17445 | } | |
17446 | ||
61f0ccff RE |
17447 | /* Succeed if the following insn is the target label, or |
17448 | if the following two insns are a barrier and the | |
17449 | target label. */ | |
17450 | this_insn = next_nonnote_insn (this_insn); | |
17451 | if (this_insn && GET_CODE (this_insn) == BARRIER) | |
17452 | this_insn = next_nonnote_insn (this_insn); | |
bd9c7e23 | 17453 | |
61f0ccff RE |
17454 | if (this_insn && this_insn == label |
17455 | && insns_skipped < max_insns_skipped) | |
17456 | { | |
accbd151 | 17457 | arm_ccfsm_state = 1; |
61f0ccff | 17458 | succeed = TRUE; |
bd9c7e23 | 17459 | } |
61f0ccff RE |
17460 | else |
17461 | fail = TRUE; | |
ff9940b0 | 17462 | break; |
2b835d68 | 17463 | |
cce8749e CH |
17464 | case JUMP_INSN: |
17465 | /* If this is an unconditional branch to the same label, succeed. | |
17466 | If it is to another label, do nothing. If it is conditional, | |
17467 | fail. */ | |
e32bac5b RE |
17468 | /* XXX Probably, the tests for SET and the PC are |
17469 | unnecessary. */ | |
cce8749e | 17470 | |
ed4c4348 | 17471 | scanbody = PATTERN (this_insn); |
ff9940b0 RE |
17472 | if (GET_CODE (scanbody) == SET |
17473 | && GET_CODE (SET_DEST (scanbody)) == PC) | |
cce8749e CH |
17474 | { |
17475 | if (GET_CODE (SET_SRC (scanbody)) == LABEL_REF | |
17476 | && XEXP (SET_SRC (scanbody), 0) == label && !reverse) | |
17477 | { | |
17478 | arm_ccfsm_state = 2; | |
17479 | succeed = TRUE; | |
17480 | } | |
17481 | else if (GET_CODE (SET_SRC (scanbody)) == IF_THEN_ELSE) | |
17482 | fail = TRUE; | |
17483 | } | |
112cdef5 | 17484 | /* Fail if a conditional return is undesirable (e.g. on a |
b36ba79f RE |
17485 | StrongARM), but still allow this if optimizing for size. */ |
17486 | else if (GET_CODE (scanbody) == RETURN | |
a72d4945 | 17487 | && !use_return_insn (TRUE, NULL) |
5895f793 | 17488 | && !optimize_size) |
b36ba79f | 17489 | fail = TRUE; |
ff9940b0 RE |
17490 | else if (GET_CODE (scanbody) == RETURN |
17491 | && seeking_return) | |
17492 | { | |
17493 | arm_ccfsm_state = 2; | |
17494 | succeed = TRUE; | |
17495 | } | |
17496 | else if (GET_CODE (scanbody) == PARALLEL) | |
17497 | { | |
17498 | switch (get_attr_conds (this_insn)) | |
17499 | { | |
17500 | case CONDS_NOCOND: | |
17501 | break; | |
17502 | default: | |
17503 | fail = TRUE; | |
17504 | break; | |
17505 | } | |
17506 | } | |
4e67550b | 17507 | else |
112cdef5 | 17508 | fail = TRUE; /* Unrecognized jump (e.g. epilogue). */ |
4e67550b | 17509 | |
cce8749e CH |
17510 | break; |
17511 | ||
17512 | case INSN: | |
ff9940b0 RE |
17513 | /* Instructions using or affecting the condition codes make it |
17514 | fail. */ | |
ed4c4348 | 17515 | scanbody = PATTERN (this_insn); |
5895f793 RE |
17516 | if (!(GET_CODE (scanbody) == SET |
17517 | || GET_CODE (scanbody) == PARALLEL) | |
74641843 | 17518 | || get_attr_conds (this_insn) != CONDS_NOCOND) |
cce8749e | 17519 | fail = TRUE; |
9b6b54e2 NC |
17520 | |
17521 | /* A conditional cirrus instruction must be followed by | |
17522 | a non Cirrus instruction. However, since we | |
17523 | conditionalize instructions in this function and by | |
17524 | the time we get here we can't add instructions | |
17525 | (nops), because shorten_branches() has already been | |
17526 | called, we will disable conditionalizing Cirrus | |
17527 | instructions to be safe. */ | |
17528 | if (GET_CODE (scanbody) != USE | |
17529 | && GET_CODE (scanbody) != CLOBBER | |
f0375c66 | 17530 | && get_attr_cirrus (this_insn) != CIRRUS_NOT) |
9b6b54e2 | 17531 | fail = TRUE; |
cce8749e CH |
17532 | break; |
17533 | ||
17534 | default: | |
17535 | break; | |
17536 | } | |
17537 | } | |
17538 | if (succeed) | |
17539 | { | |
ff9940b0 | 17540 | if ((!seeking_return) && (arm_ccfsm_state == 1 || reverse)) |
cce8749e | 17541 | arm_target_label = CODE_LABEL_NUMBER (label); |
e6d29d15 | 17542 | else |
ff9940b0 | 17543 | { |
e6d29d15 | 17544 | gcc_assert (seeking_return || arm_ccfsm_state == 2); |
e0b92319 | 17545 | |
ff9940b0 RE |
17546 | while (this_insn && GET_CODE (PATTERN (this_insn)) == USE) |
17547 | { | |
17548 | this_insn = next_nonnote_insn (this_insn); | |
e6d29d15 NS |
17549 | gcc_assert (!this_insn |
17550 | || (GET_CODE (this_insn) != BARRIER | |
17551 | && GET_CODE (this_insn) != CODE_LABEL)); | |
ff9940b0 RE |
17552 | } |
17553 | if (!this_insn) | |
17554 | { | |
d6b4baa4 | 17555 | /* Oh, dear! we ran off the end.. give up. */ |
5b3e6663 | 17556 | extract_constrain_insn_cached (insn); |
ff9940b0 | 17557 | arm_ccfsm_state = 0; |
abaa26e5 | 17558 | arm_target_insn = NULL; |
ff9940b0 RE |
17559 | return; |
17560 | } | |
17561 | arm_target_insn = this_insn; | |
17562 | } | |
accbd151 PB |
17563 | |
17564 | /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from | |
17565 | what it was. */ | |
17566 | if (!reverse) | |
17567 | arm_current_cc = get_arm_condition_code (XEXP (SET_SRC (body), 0)); | |
cce8749e | 17568 | |
cce8749e CH |
17569 | if (reverse || then_not_else) |
17570 | arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc); | |
17571 | } | |
f676971a | 17572 | |
1ccbefce | 17573 | /* Restore recog_data (getting the attributes of other insns can |
ff9940b0 | 17574 | destroy this array, but final.c assumes that it remains intact |
5b3e6663 PB |
17575 | across this call. */ |
17576 | extract_constrain_insn_cached (insn); | |
17577 | } | |
17578 | } | |
17579 | ||
17580 | /* Output IT instructions. */ | |
17581 | void | |
17582 | thumb2_asm_output_opcode (FILE * stream) | |
17583 | { | |
17584 | char buff[5]; | |
17585 | int n; | |
17586 | ||
17587 | if (arm_condexec_mask) | |
17588 | { | |
17589 | for (n = 0; n < arm_condexec_masklen; n++) | |
17590 | buff[n] = (arm_condexec_mask & (1 << n)) ? 't' : 'e'; | |
17591 | buff[n] = 0; | |
17592 | asm_fprintf(stream, "i%s\t%s\n\t", buff, | |
17593 | arm_condition_codes[arm_current_cc]); | |
17594 | arm_condexec_mask = 0; | |
cce8749e | 17595 | } |
f3bb6135 | 17596 | } |
cce8749e | 17597 | |
4b02997f | 17598 | /* Returns true if REGNO is a valid register |
21b5653c | 17599 | for holding a quantity of type MODE. */ |
4b02997f | 17600 | int |
e32bac5b | 17601 | arm_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode) |
4b02997f NC |
17602 | { |
17603 | if (GET_MODE_CLASS (mode) == MODE_CC) | |
a6a5de04 RE |
17604 | return (regno == CC_REGNUM |
17605 | || (TARGET_HARD_FLOAT && TARGET_VFP | |
17606 | && regno == VFPCC_REGNUM)); | |
f676971a | 17607 | |
5b3e6663 | 17608 | if (TARGET_THUMB1) |
4b02997f NC |
17609 | /* For the Thumb we only allow values bigger than SImode in |
17610 | registers 0 - 6, so that there is always a second low | |
17611 | register available to hold the upper part of the value. | |
17612 | We probably we ought to ensure that the register is the | |
17613 | start of an even numbered register pair. */ | |
e9d7b180 | 17614 | return (ARM_NUM_REGS (mode) < 2) || (regno < LAST_LO_REGNUM); |
4b02997f | 17615 | |
a6a5de04 RE |
17616 | if (TARGET_HARD_FLOAT && TARGET_MAVERICK |
17617 | && IS_CIRRUS_REGNUM (regno)) | |
9b6b54e2 NC |
17618 | /* We have outlawed SI values in Cirrus registers because they |
17619 | reside in the lower 32 bits, but SF values reside in the | |
17620 | upper 32 bits. This causes gcc all sorts of grief. We can't | |
17621 | even split the registers into pairs because Cirrus SI values | |
17622 | get sign extended to 64bits-- aldyh. */ | |
17623 | return (GET_MODE_CLASS (mode) == MODE_FLOAT) || (mode == DImode); | |
17624 | ||
a6a5de04 RE |
17625 | if (TARGET_HARD_FLOAT && TARGET_VFP |
17626 | && IS_VFP_REGNUM (regno)) | |
9b66ebb1 PB |
17627 | { |
17628 | if (mode == SFmode || mode == SImode) | |
f1adb0a9 | 17629 | return VFP_REGNO_OK_FOR_SINGLE (regno); |
9b66ebb1 | 17630 | |
9b66ebb1 | 17631 | if (mode == DFmode) |
f1adb0a9 | 17632 | return VFP_REGNO_OK_FOR_DOUBLE (regno); |
88f77cba | 17633 | |
0fd8c3ad | 17634 | /* VFP registers can hold HFmode values, but there is no point in |
e0dc3601 | 17635 | putting them there unless we have hardware conversion insns. */ |
0fd8c3ad | 17636 | if (mode == HFmode) |
e0dc3601 | 17637 | return TARGET_FP16 && VFP_REGNO_OK_FOR_SINGLE (regno); |
0fd8c3ad | 17638 | |
88f77cba JB |
17639 | if (TARGET_NEON) |
17640 | return (VALID_NEON_DREG_MODE (mode) && VFP_REGNO_OK_FOR_DOUBLE (regno)) | |
17641 | || (VALID_NEON_QREG_MODE (mode) | |
17642 | && NEON_REGNO_OK_FOR_QUAD (regno)) | |
17643 | || (mode == TImode && NEON_REGNO_OK_FOR_NREGS (regno, 2)) | |
17644 | || (mode == EImode && NEON_REGNO_OK_FOR_NREGS (regno, 3)) | |
17645 | || (mode == OImode && NEON_REGNO_OK_FOR_NREGS (regno, 4)) | |
17646 | || (mode == CImode && NEON_REGNO_OK_FOR_NREGS (regno, 6)) | |
17647 | || (mode == XImode && NEON_REGNO_OK_FOR_NREGS (regno, 8)); | |
17648 | ||
9b66ebb1 PB |
17649 | return FALSE; |
17650 | } | |
17651 | ||
a6a5de04 RE |
17652 | if (TARGET_REALLY_IWMMXT) |
17653 | { | |
17654 | if (IS_IWMMXT_GR_REGNUM (regno)) | |
17655 | return mode == SImode; | |
5a9335ef | 17656 | |
a6a5de04 RE |
17657 | if (IS_IWMMXT_REGNUM (regno)) |
17658 | return VALID_IWMMXT_REG_MODE (mode); | |
17659 | } | |
17660 | ||
2e94c12d | 17661 | /* We allow almost any value to be stored in the general registers. |
fdd695fd | 17662 | Restrict doubleword quantities to even register pairs so that we can |
2e94c12d JB |
17663 | use ldrd. Do not allow very large Neon structure opaque modes in |
17664 | general registers; they would use too many. */ | |
4b02997f | 17665 | if (regno <= LAST_ARM_REGNUM) |
88f77cba | 17666 | return !(TARGET_LDRD && GET_MODE_SIZE (mode) > 4 && (regno & 1) != 0) |
2e94c12d | 17667 | && ARM_NUM_REGS (mode) <= 4; |
4b02997f | 17668 | |
a6a5de04 | 17669 | if (regno == FRAME_POINTER_REGNUM |
4b02997f NC |
17670 | || regno == ARG_POINTER_REGNUM) |
17671 | /* We only allow integers in the fake hard registers. */ | |
17672 | return GET_MODE_CLASS (mode) == MODE_INT; | |
17673 | ||
3b684012 | 17674 | /* The only registers left are the FPA registers |
4b02997f | 17675 | which we only allow to hold FP values. */ |
a6a5de04 RE |
17676 | return (TARGET_HARD_FLOAT && TARGET_FPA |
17677 | && GET_MODE_CLASS (mode) == MODE_FLOAT | |
17678 | && regno >= FIRST_FPA_REGNUM | |
17679 | && regno <= LAST_FPA_REGNUM); | |
4b02997f NC |
17680 | } |
17681 | ||
5b3e6663 PB |
17682 | /* For efficiency and historical reasons LO_REGS, HI_REGS and CC_REGS are |
17683 | not used in arm mode. */ | |
bbbbb16a ILT |
17684 | |
17685 | enum reg_class | |
e32bac5b | 17686 | arm_regno_class (int regno) |
d5b7b3ae | 17687 | { |
5b3e6663 | 17688 | if (TARGET_THUMB1) |
d5b7b3ae RE |
17689 | { |
17690 | if (regno == STACK_POINTER_REGNUM) | |
17691 | return STACK_REG; | |
17692 | if (regno == CC_REGNUM) | |
17693 | return CC_REG; | |
17694 | if (regno < 8) | |
17695 | return LO_REGS; | |
17696 | return HI_REGS; | |
17697 | } | |
17698 | ||
5b3e6663 PB |
17699 | if (TARGET_THUMB2 && regno < 8) |
17700 | return LO_REGS; | |
17701 | ||
d5b7b3ae RE |
17702 | if ( regno <= LAST_ARM_REGNUM |
17703 | || regno == FRAME_POINTER_REGNUM | |
17704 | || regno == ARG_POINTER_REGNUM) | |
5b3e6663 | 17705 | return TARGET_THUMB2 ? HI_REGS : GENERAL_REGS; |
f676971a | 17706 | |
9b66ebb1 | 17707 | if (regno == CC_REGNUM || regno == VFPCC_REGNUM) |
5b3e6663 | 17708 | return TARGET_THUMB2 ? CC_REG : NO_REGS; |
d5b7b3ae | 17709 | |
9b6b54e2 NC |
17710 | if (IS_CIRRUS_REGNUM (regno)) |
17711 | return CIRRUS_REGS; | |
17712 | ||
9b66ebb1 | 17713 | if (IS_VFP_REGNUM (regno)) |
f1adb0a9 JB |
17714 | { |
17715 | if (regno <= D7_VFP_REGNUM) | |
17716 | return VFP_D0_D7_REGS; | |
17717 | else if (regno <= LAST_LO_VFP_REGNUM) | |
17718 | return VFP_LO_REGS; | |
17719 | else | |
17720 | return VFP_HI_REGS; | |
17721 | } | |
9b66ebb1 | 17722 | |
5a9335ef NC |
17723 | if (IS_IWMMXT_REGNUM (regno)) |
17724 | return IWMMXT_REGS; | |
17725 | ||
e99faaaa ILT |
17726 | if (IS_IWMMXT_GR_REGNUM (regno)) |
17727 | return IWMMXT_GR_REGS; | |
17728 | ||
3b684012 | 17729 | return FPA_REGS; |
d5b7b3ae RE |
17730 | } |
17731 | ||
17732 | /* Handle a special case when computing the offset | |
17733 | of an argument from the frame pointer. */ | |
17734 | int | |
e32bac5b | 17735 | arm_debugger_arg_offset (int value, rtx addr) |
d5b7b3ae RE |
17736 | { |
17737 | rtx insn; | |
17738 | ||
17739 | /* We are only interested if dbxout_parms() failed to compute the offset. */ | |
17740 | if (value != 0) | |
17741 | return 0; | |
17742 | ||
17743 | /* We can only cope with the case where the address is held in a register. */ | |
17744 | if (GET_CODE (addr) != REG) | |
17745 | return 0; | |
17746 | ||
17747 | /* If we are using the frame pointer to point at the argument, then | |
17748 | an offset of 0 is correct. */ | |
cd2b33d0 | 17749 | if (REGNO (addr) == (unsigned) HARD_FRAME_POINTER_REGNUM) |
d5b7b3ae | 17750 | return 0; |
f676971a | 17751 | |
d5b7b3ae RE |
17752 | /* If we are using the stack pointer to point at the |
17753 | argument, then an offset of 0 is correct. */ | |
5b3e6663 | 17754 | /* ??? Check this is consistent with thumb2 frame layout. */ |
5895f793 | 17755 | if ((TARGET_THUMB || !frame_pointer_needed) |
d5b7b3ae RE |
17756 | && REGNO (addr) == SP_REGNUM) |
17757 | return 0; | |
f676971a | 17758 | |
d5b7b3ae RE |
17759 | /* Oh dear. The argument is pointed to by a register rather |
17760 | than being held in a register, or being stored at a known | |
17761 | offset from the frame pointer. Since GDB only understands | |
17762 | those two kinds of argument we must translate the address | |
17763 | held in the register into an offset from the frame pointer. | |
17764 | We do this by searching through the insns for the function | |
17765 | looking to see where this register gets its value. If the | |
4912a07c | 17766 | register is initialized from the frame pointer plus an offset |
d5b7b3ae | 17767 | then we are in luck and we can continue, otherwise we give up. |
f676971a | 17768 | |
d5b7b3ae RE |
17769 | This code is exercised by producing debugging information |
17770 | for a function with arguments like this: | |
f676971a | 17771 | |
d5b7b3ae | 17772 | double func (double a, double b, int c, double d) {return d;} |
f676971a | 17773 | |
d5b7b3ae RE |
17774 | Without this code the stab for parameter 'd' will be set to |
17775 | an offset of 0 from the frame pointer, rather than 8. */ | |
17776 | ||
17777 | /* The if() statement says: | |
17778 | ||
17779 | If the insn is a normal instruction | |
17780 | and if the insn is setting the value in a register | |
17781 | and if the register being set is the register holding the address of the argument | |
17782 | and if the address is computing by an addition | |
17783 | that involves adding to a register | |
17784 | which is the frame pointer | |
17785 | a constant integer | |
17786 | ||
d6b4baa4 | 17787 | then... */ |
f676971a | 17788 | |
d5b7b3ae RE |
17789 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) |
17790 | { | |
f676971a | 17791 | if ( GET_CODE (insn) == INSN |
d5b7b3ae RE |
17792 | && GET_CODE (PATTERN (insn)) == SET |
17793 | && REGNO (XEXP (PATTERN (insn), 0)) == REGNO (addr) | |
17794 | && GET_CODE (XEXP (PATTERN (insn), 1)) == PLUS | |
17795 | && GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 0)) == REG | |
cd2b33d0 | 17796 | && REGNO (XEXP (XEXP (PATTERN (insn), 1), 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM |
d5b7b3ae RE |
17797 | && GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 1)) == CONST_INT |
17798 | ) | |
17799 | { | |
17800 | value = INTVAL (XEXP (XEXP (PATTERN (insn), 1), 1)); | |
f676971a | 17801 | |
d5b7b3ae RE |
17802 | break; |
17803 | } | |
17804 | } | |
f676971a | 17805 | |
d5b7b3ae RE |
17806 | if (value == 0) |
17807 | { | |
17808 | debug_rtx (addr); | |
d4ee4d25 | 17809 | warning (0, "unable to compute real location of stacked parameter"); |
d5b7b3ae RE |
17810 | value = 8; /* XXX magic hack */ |
17811 | } | |
17812 | ||
17813 | return value; | |
17814 | } | |
d5b7b3ae | 17815 | \f |
5a9335ef NC |
17816 | #define def_mbuiltin(MASK, NAME, TYPE, CODE) \ |
17817 | do \ | |
17818 | { \ | |
17819 | if ((MASK) & insn_flags) \ | |
c79efc4d RÁE |
17820 | add_builtin_function ((NAME), (TYPE), (CODE), \ |
17821 | BUILT_IN_MD, NULL, NULL_TREE); \ | |
5a9335ef NC |
17822 | } \ |
17823 | while (0) | |
17824 | ||
17825 | struct builtin_description | |
17826 | { | |
17827 | const unsigned int mask; | |
17828 | const enum insn_code icode; | |
17829 | const char * const name; | |
17830 | const enum arm_builtins code; | |
17831 | const enum rtx_code comparison; | |
17832 | const unsigned int flag; | |
17833 | }; | |
17834 | ||
17835 | static const struct builtin_description bdesc_2arg[] = | |
17836 | { | |
17837 | #define IWMMXT_BUILTIN(code, string, builtin) \ | |
17838 | { FL_IWMMXT, CODE_FOR_##code, "__builtin_arm_" string, \ | |
81f40b79 | 17839 | ARM_BUILTIN_##builtin, UNKNOWN, 0 }, |
5a9335ef NC |
17840 | |
17841 | IWMMXT_BUILTIN (addv8qi3, "waddb", WADDB) | |
17842 | IWMMXT_BUILTIN (addv4hi3, "waddh", WADDH) | |
17843 | IWMMXT_BUILTIN (addv2si3, "waddw", WADDW) | |
17844 | IWMMXT_BUILTIN (subv8qi3, "wsubb", WSUBB) | |
17845 | IWMMXT_BUILTIN (subv4hi3, "wsubh", WSUBH) | |
17846 | IWMMXT_BUILTIN (subv2si3, "wsubw", WSUBW) | |
17847 | IWMMXT_BUILTIN (ssaddv8qi3, "waddbss", WADDSSB) | |
17848 | IWMMXT_BUILTIN (ssaddv4hi3, "waddhss", WADDSSH) | |
17849 | IWMMXT_BUILTIN (ssaddv2si3, "waddwss", WADDSSW) | |
17850 | IWMMXT_BUILTIN (sssubv8qi3, "wsubbss", WSUBSSB) | |
17851 | IWMMXT_BUILTIN (sssubv4hi3, "wsubhss", WSUBSSH) | |
17852 | IWMMXT_BUILTIN (sssubv2si3, "wsubwss", WSUBSSW) | |
17853 | IWMMXT_BUILTIN (usaddv8qi3, "waddbus", WADDUSB) | |
17854 | IWMMXT_BUILTIN (usaddv4hi3, "waddhus", WADDUSH) | |
17855 | IWMMXT_BUILTIN (usaddv2si3, "waddwus", WADDUSW) | |
17856 | IWMMXT_BUILTIN (ussubv8qi3, "wsubbus", WSUBUSB) | |
17857 | IWMMXT_BUILTIN (ussubv4hi3, "wsubhus", WSUBUSH) | |
17858 | IWMMXT_BUILTIN (ussubv2si3, "wsubwus", WSUBUSW) | |
17859 | IWMMXT_BUILTIN (mulv4hi3, "wmulul", WMULUL) | |
f07a6b21 BE |
17860 | IWMMXT_BUILTIN (smulv4hi3_highpart, "wmulsm", WMULSM) |
17861 | IWMMXT_BUILTIN (umulv4hi3_highpart, "wmulum", WMULUM) | |
5a9335ef NC |
17862 | IWMMXT_BUILTIN (eqv8qi3, "wcmpeqb", WCMPEQB) |
17863 | IWMMXT_BUILTIN (eqv4hi3, "wcmpeqh", WCMPEQH) | |
17864 | IWMMXT_BUILTIN (eqv2si3, "wcmpeqw", WCMPEQW) | |
17865 | IWMMXT_BUILTIN (gtuv8qi3, "wcmpgtub", WCMPGTUB) | |
17866 | IWMMXT_BUILTIN (gtuv4hi3, "wcmpgtuh", WCMPGTUH) | |
17867 | IWMMXT_BUILTIN (gtuv2si3, "wcmpgtuw", WCMPGTUW) | |
17868 | IWMMXT_BUILTIN (gtv8qi3, "wcmpgtsb", WCMPGTSB) | |
17869 | IWMMXT_BUILTIN (gtv4hi3, "wcmpgtsh", WCMPGTSH) | |
17870 | IWMMXT_BUILTIN (gtv2si3, "wcmpgtsw", WCMPGTSW) | |
17871 | IWMMXT_BUILTIN (umaxv8qi3, "wmaxub", WMAXUB) | |
17872 | IWMMXT_BUILTIN (smaxv8qi3, "wmaxsb", WMAXSB) | |
17873 | IWMMXT_BUILTIN (umaxv4hi3, "wmaxuh", WMAXUH) | |
17874 | IWMMXT_BUILTIN (smaxv4hi3, "wmaxsh", WMAXSH) | |
17875 | IWMMXT_BUILTIN (umaxv2si3, "wmaxuw", WMAXUW) | |
17876 | IWMMXT_BUILTIN (smaxv2si3, "wmaxsw", WMAXSW) | |
17877 | IWMMXT_BUILTIN (uminv8qi3, "wminub", WMINUB) | |
17878 | IWMMXT_BUILTIN (sminv8qi3, "wminsb", WMINSB) | |
17879 | IWMMXT_BUILTIN (uminv4hi3, "wminuh", WMINUH) | |
17880 | IWMMXT_BUILTIN (sminv4hi3, "wminsh", WMINSH) | |
17881 | IWMMXT_BUILTIN (uminv2si3, "wminuw", WMINUW) | |
17882 | IWMMXT_BUILTIN (sminv2si3, "wminsw", WMINSW) | |
17883 | IWMMXT_BUILTIN (iwmmxt_anddi3, "wand", WAND) | |
17884 | IWMMXT_BUILTIN (iwmmxt_nanddi3, "wandn", WANDN) | |
17885 | IWMMXT_BUILTIN (iwmmxt_iordi3, "wor", WOR) | |
17886 | IWMMXT_BUILTIN (iwmmxt_xordi3, "wxor", WXOR) | |
17887 | IWMMXT_BUILTIN (iwmmxt_uavgv8qi3, "wavg2b", WAVG2B) | |
17888 | IWMMXT_BUILTIN (iwmmxt_uavgv4hi3, "wavg2h", WAVG2H) | |
17889 | IWMMXT_BUILTIN (iwmmxt_uavgrndv8qi3, "wavg2br", WAVG2BR) | |
17890 | IWMMXT_BUILTIN (iwmmxt_uavgrndv4hi3, "wavg2hr", WAVG2HR) | |
17891 | IWMMXT_BUILTIN (iwmmxt_wunpckilb, "wunpckilb", WUNPCKILB) | |
17892 | IWMMXT_BUILTIN (iwmmxt_wunpckilh, "wunpckilh", WUNPCKILH) | |
17893 | IWMMXT_BUILTIN (iwmmxt_wunpckilw, "wunpckilw", WUNPCKILW) | |
17894 | IWMMXT_BUILTIN (iwmmxt_wunpckihb, "wunpckihb", WUNPCKIHB) | |
17895 | IWMMXT_BUILTIN (iwmmxt_wunpckihh, "wunpckihh", WUNPCKIHH) | |
17896 | IWMMXT_BUILTIN (iwmmxt_wunpckihw, "wunpckihw", WUNPCKIHW) | |
17897 | IWMMXT_BUILTIN (iwmmxt_wmadds, "wmadds", WMADDS) | |
17898 | IWMMXT_BUILTIN (iwmmxt_wmaddu, "wmaddu", WMADDU) | |
17899 | ||
17900 | #define IWMMXT_BUILTIN2(code, builtin) \ | |
81f40b79 | 17901 | { FL_IWMMXT, CODE_FOR_##code, NULL, ARM_BUILTIN_##builtin, UNKNOWN, 0 }, |
f676971a | 17902 | |
5a9335ef NC |
17903 | IWMMXT_BUILTIN2 (iwmmxt_wpackhss, WPACKHSS) |
17904 | IWMMXT_BUILTIN2 (iwmmxt_wpackwss, WPACKWSS) | |
17905 | IWMMXT_BUILTIN2 (iwmmxt_wpackdss, WPACKDSS) | |
17906 | IWMMXT_BUILTIN2 (iwmmxt_wpackhus, WPACKHUS) | |
17907 | IWMMXT_BUILTIN2 (iwmmxt_wpackwus, WPACKWUS) | |
17908 | IWMMXT_BUILTIN2 (iwmmxt_wpackdus, WPACKDUS) | |
17909 | IWMMXT_BUILTIN2 (ashlv4hi3_di, WSLLH) | |
88f77cba | 17910 | IWMMXT_BUILTIN2 (ashlv4hi3_iwmmxt, WSLLHI) |
5a9335ef | 17911 | IWMMXT_BUILTIN2 (ashlv2si3_di, WSLLW) |
88f77cba | 17912 | IWMMXT_BUILTIN2 (ashlv2si3_iwmmxt, WSLLWI) |
5a9335ef NC |
17913 | IWMMXT_BUILTIN2 (ashldi3_di, WSLLD) |
17914 | IWMMXT_BUILTIN2 (ashldi3_iwmmxt, WSLLDI) | |
17915 | IWMMXT_BUILTIN2 (lshrv4hi3_di, WSRLH) | |
88f77cba | 17916 | IWMMXT_BUILTIN2 (lshrv4hi3_iwmmxt, WSRLHI) |
5a9335ef | 17917 | IWMMXT_BUILTIN2 (lshrv2si3_di, WSRLW) |
88f77cba | 17918 | IWMMXT_BUILTIN2 (lshrv2si3_iwmmxt, WSRLWI) |
5a9335ef | 17919 | IWMMXT_BUILTIN2 (lshrdi3_di, WSRLD) |
9b66ebb1 | 17920 | IWMMXT_BUILTIN2 (lshrdi3_iwmmxt, WSRLDI) |
5a9335ef | 17921 | IWMMXT_BUILTIN2 (ashrv4hi3_di, WSRAH) |
88f77cba | 17922 | IWMMXT_BUILTIN2 (ashrv4hi3_iwmmxt, WSRAHI) |
5a9335ef | 17923 | IWMMXT_BUILTIN2 (ashrv2si3_di, WSRAW) |
88f77cba | 17924 | IWMMXT_BUILTIN2 (ashrv2si3_iwmmxt, WSRAWI) |
5a9335ef | 17925 | IWMMXT_BUILTIN2 (ashrdi3_di, WSRAD) |
9b66ebb1 | 17926 | IWMMXT_BUILTIN2 (ashrdi3_iwmmxt, WSRADI) |
5a9335ef NC |
17927 | IWMMXT_BUILTIN2 (rorv4hi3_di, WRORH) |
17928 | IWMMXT_BUILTIN2 (rorv4hi3, WRORHI) | |
17929 | IWMMXT_BUILTIN2 (rorv2si3_di, WRORW) | |
17930 | IWMMXT_BUILTIN2 (rorv2si3, WRORWI) | |
17931 | IWMMXT_BUILTIN2 (rordi3_di, WRORD) | |
17932 | IWMMXT_BUILTIN2 (rordi3, WRORDI) | |
17933 | IWMMXT_BUILTIN2 (iwmmxt_wmacuz, WMACUZ) | |
17934 | IWMMXT_BUILTIN2 (iwmmxt_wmacsz, WMACSZ) | |
17935 | }; | |
17936 | ||
17937 | static const struct builtin_description bdesc_1arg[] = | |
17938 | { | |
17939 | IWMMXT_BUILTIN (iwmmxt_tmovmskb, "tmovmskb", TMOVMSKB) | |
17940 | IWMMXT_BUILTIN (iwmmxt_tmovmskh, "tmovmskh", TMOVMSKH) | |
17941 | IWMMXT_BUILTIN (iwmmxt_tmovmskw, "tmovmskw", TMOVMSKW) | |
17942 | IWMMXT_BUILTIN (iwmmxt_waccb, "waccb", WACCB) | |
17943 | IWMMXT_BUILTIN (iwmmxt_wacch, "wacch", WACCH) | |
17944 | IWMMXT_BUILTIN (iwmmxt_waccw, "waccw", WACCW) | |
17945 | IWMMXT_BUILTIN (iwmmxt_wunpckehub, "wunpckehub", WUNPCKEHUB) | |
17946 | IWMMXT_BUILTIN (iwmmxt_wunpckehuh, "wunpckehuh", WUNPCKEHUH) | |
17947 | IWMMXT_BUILTIN (iwmmxt_wunpckehuw, "wunpckehuw", WUNPCKEHUW) | |
17948 | IWMMXT_BUILTIN (iwmmxt_wunpckehsb, "wunpckehsb", WUNPCKEHSB) | |
17949 | IWMMXT_BUILTIN (iwmmxt_wunpckehsh, "wunpckehsh", WUNPCKEHSH) | |
17950 | IWMMXT_BUILTIN (iwmmxt_wunpckehsw, "wunpckehsw", WUNPCKEHSW) | |
17951 | IWMMXT_BUILTIN (iwmmxt_wunpckelub, "wunpckelub", WUNPCKELUB) | |
17952 | IWMMXT_BUILTIN (iwmmxt_wunpckeluh, "wunpckeluh", WUNPCKELUH) | |
17953 | IWMMXT_BUILTIN (iwmmxt_wunpckeluw, "wunpckeluw", WUNPCKELUW) | |
17954 | IWMMXT_BUILTIN (iwmmxt_wunpckelsb, "wunpckelsb", WUNPCKELSB) | |
17955 | IWMMXT_BUILTIN (iwmmxt_wunpckelsh, "wunpckelsh", WUNPCKELSH) | |
17956 | IWMMXT_BUILTIN (iwmmxt_wunpckelsw, "wunpckelsw", WUNPCKELSW) | |
17957 | }; | |
17958 | ||
17959 | /* Set up all the iWMMXt builtins. This is | |
17960 | not called if TARGET_IWMMXT is zero. */ | |
17961 | ||
17962 | static void | |
17963 | arm_init_iwmmxt_builtins (void) | |
17964 | { | |
17965 | const struct builtin_description * d; | |
17966 | size_t i; | |
17967 | tree endlink = void_list_node; | |
17968 | ||
4a5eab38 PB |
17969 | tree V2SI_type_node = build_vector_type_for_mode (intSI_type_node, V2SImode); |
17970 | tree V4HI_type_node = build_vector_type_for_mode (intHI_type_node, V4HImode); | |
17971 | tree V8QI_type_node = build_vector_type_for_mode (intQI_type_node, V8QImode); | |
17972 | ||
5a9335ef NC |
17973 | tree int_ftype_int |
17974 | = build_function_type (integer_type_node, | |
17975 | tree_cons (NULL_TREE, integer_type_node, endlink)); | |
17976 | tree v8qi_ftype_v8qi_v8qi_int | |
17977 | = build_function_type (V8QI_type_node, | |
17978 | tree_cons (NULL_TREE, V8QI_type_node, | |
17979 | tree_cons (NULL_TREE, V8QI_type_node, | |
17980 | tree_cons (NULL_TREE, | |
17981 | integer_type_node, | |
17982 | endlink)))); | |
17983 | tree v4hi_ftype_v4hi_int | |
17984 | = build_function_type (V4HI_type_node, | |
17985 | tree_cons (NULL_TREE, V4HI_type_node, | |
17986 | tree_cons (NULL_TREE, integer_type_node, | |
17987 | endlink))); | |
17988 | tree v2si_ftype_v2si_int | |
17989 | = build_function_type (V2SI_type_node, | |
17990 | tree_cons (NULL_TREE, V2SI_type_node, | |
17991 | tree_cons (NULL_TREE, integer_type_node, | |
17992 | endlink))); | |
17993 | tree v2si_ftype_di_di | |
17994 | = build_function_type (V2SI_type_node, | |
17995 | tree_cons (NULL_TREE, long_long_integer_type_node, | |
17996 | tree_cons (NULL_TREE, long_long_integer_type_node, | |
17997 | endlink))); | |
17998 | tree di_ftype_di_int | |
17999 | = build_function_type (long_long_integer_type_node, | |
18000 | tree_cons (NULL_TREE, long_long_integer_type_node, | |
18001 | tree_cons (NULL_TREE, integer_type_node, | |
18002 | endlink))); | |
18003 | tree di_ftype_di_int_int | |
18004 | = build_function_type (long_long_integer_type_node, | |
18005 | tree_cons (NULL_TREE, long_long_integer_type_node, | |
18006 | tree_cons (NULL_TREE, integer_type_node, | |
18007 | tree_cons (NULL_TREE, | |
18008 | integer_type_node, | |
18009 | endlink)))); | |
18010 | tree int_ftype_v8qi | |
18011 | = build_function_type (integer_type_node, | |
18012 | tree_cons (NULL_TREE, V8QI_type_node, | |
18013 | endlink)); | |
18014 | tree int_ftype_v4hi | |
18015 | = build_function_type (integer_type_node, | |
18016 | tree_cons (NULL_TREE, V4HI_type_node, | |
18017 | endlink)); | |
18018 | tree int_ftype_v2si | |
18019 | = build_function_type (integer_type_node, | |
18020 | tree_cons (NULL_TREE, V2SI_type_node, | |
18021 | endlink)); | |
18022 | tree int_ftype_v8qi_int | |
18023 | = build_function_type (integer_type_node, | |
18024 | tree_cons (NULL_TREE, V8QI_type_node, | |
18025 | tree_cons (NULL_TREE, integer_type_node, | |
18026 | endlink))); | |
18027 | tree int_ftype_v4hi_int | |
18028 | = build_function_type (integer_type_node, | |
18029 | tree_cons (NULL_TREE, V4HI_type_node, | |
18030 | tree_cons (NULL_TREE, integer_type_node, | |
18031 | endlink))); | |
18032 | tree int_ftype_v2si_int | |
18033 | = build_function_type (integer_type_node, | |
18034 | tree_cons (NULL_TREE, V2SI_type_node, | |
18035 | tree_cons (NULL_TREE, integer_type_node, | |
18036 | endlink))); | |
18037 | tree v8qi_ftype_v8qi_int_int | |
18038 | = build_function_type (V8QI_type_node, | |
18039 | tree_cons (NULL_TREE, V8QI_type_node, | |
18040 | tree_cons (NULL_TREE, integer_type_node, | |
18041 | tree_cons (NULL_TREE, | |
18042 | integer_type_node, | |
18043 | endlink)))); | |
18044 | tree v4hi_ftype_v4hi_int_int | |
18045 | = build_function_type (V4HI_type_node, | |
18046 | tree_cons (NULL_TREE, V4HI_type_node, | |
18047 | tree_cons (NULL_TREE, integer_type_node, | |
18048 | tree_cons (NULL_TREE, | |
18049 | integer_type_node, | |
18050 | endlink)))); | |
18051 | tree v2si_ftype_v2si_int_int | |
18052 | = build_function_type (V2SI_type_node, | |
18053 | tree_cons (NULL_TREE, V2SI_type_node, | |
18054 | tree_cons (NULL_TREE, integer_type_node, | |
18055 | tree_cons (NULL_TREE, | |
18056 | integer_type_node, | |
18057 | endlink)))); | |
18058 | /* Miscellaneous. */ | |
18059 | tree v8qi_ftype_v4hi_v4hi | |
18060 | = build_function_type (V8QI_type_node, | |
18061 | tree_cons (NULL_TREE, V4HI_type_node, | |
18062 | tree_cons (NULL_TREE, V4HI_type_node, | |
18063 | endlink))); | |
18064 | tree v4hi_ftype_v2si_v2si | |
18065 | = build_function_type (V4HI_type_node, | |
18066 | tree_cons (NULL_TREE, V2SI_type_node, | |
18067 | tree_cons (NULL_TREE, V2SI_type_node, | |
18068 | endlink))); | |
18069 | tree v2si_ftype_v4hi_v4hi | |
18070 | = build_function_type (V2SI_type_node, | |
18071 | tree_cons (NULL_TREE, V4HI_type_node, | |
18072 | tree_cons (NULL_TREE, V4HI_type_node, | |
18073 | endlink))); | |
18074 | tree v2si_ftype_v8qi_v8qi | |
18075 | = build_function_type (V2SI_type_node, | |
18076 | tree_cons (NULL_TREE, V8QI_type_node, | |
18077 | tree_cons (NULL_TREE, V8QI_type_node, | |
18078 | endlink))); | |
18079 | tree v4hi_ftype_v4hi_di | |
18080 | = build_function_type (V4HI_type_node, | |
18081 | tree_cons (NULL_TREE, V4HI_type_node, | |
18082 | tree_cons (NULL_TREE, | |
18083 | long_long_integer_type_node, | |
18084 | endlink))); | |
18085 | tree v2si_ftype_v2si_di | |
18086 | = build_function_type (V2SI_type_node, | |
18087 | tree_cons (NULL_TREE, V2SI_type_node, | |
18088 | tree_cons (NULL_TREE, | |
18089 | long_long_integer_type_node, | |
18090 | endlink))); | |
18091 | tree void_ftype_int_int | |
18092 | = build_function_type (void_type_node, | |
18093 | tree_cons (NULL_TREE, integer_type_node, | |
18094 | tree_cons (NULL_TREE, integer_type_node, | |
18095 | endlink))); | |
18096 | tree di_ftype_void | |
18097 | = build_function_type (long_long_unsigned_type_node, endlink); | |
18098 | tree di_ftype_v8qi | |
18099 | = build_function_type (long_long_integer_type_node, | |
18100 | tree_cons (NULL_TREE, V8QI_type_node, | |
18101 | endlink)); | |
18102 | tree di_ftype_v4hi | |
18103 | = build_function_type (long_long_integer_type_node, | |
18104 | tree_cons (NULL_TREE, V4HI_type_node, | |
18105 | endlink)); | |
18106 | tree di_ftype_v2si | |
18107 | = build_function_type (long_long_integer_type_node, | |
18108 | tree_cons (NULL_TREE, V2SI_type_node, | |
18109 | endlink)); | |
18110 | tree v2si_ftype_v4hi | |
18111 | = build_function_type (V2SI_type_node, | |
18112 | tree_cons (NULL_TREE, V4HI_type_node, | |
18113 | endlink)); | |
18114 | tree v4hi_ftype_v8qi | |
18115 | = build_function_type (V4HI_type_node, | |
18116 | tree_cons (NULL_TREE, V8QI_type_node, | |
18117 | endlink)); | |
18118 | ||
18119 | tree di_ftype_di_v4hi_v4hi | |
18120 | = build_function_type (long_long_unsigned_type_node, | |
18121 | tree_cons (NULL_TREE, | |
18122 | long_long_unsigned_type_node, | |
18123 | tree_cons (NULL_TREE, V4HI_type_node, | |
18124 | tree_cons (NULL_TREE, | |
18125 | V4HI_type_node, | |
18126 | endlink)))); | |
18127 | ||
18128 | tree di_ftype_v4hi_v4hi | |
18129 | = build_function_type (long_long_unsigned_type_node, | |
18130 | tree_cons (NULL_TREE, V4HI_type_node, | |
18131 | tree_cons (NULL_TREE, V4HI_type_node, | |
18132 | endlink))); | |
18133 | ||
18134 | /* Normal vector binops. */ | |
18135 | tree v8qi_ftype_v8qi_v8qi | |
18136 | = build_function_type (V8QI_type_node, | |
18137 | tree_cons (NULL_TREE, V8QI_type_node, | |
18138 | tree_cons (NULL_TREE, V8QI_type_node, | |
18139 | endlink))); | |
18140 | tree v4hi_ftype_v4hi_v4hi | |
18141 | = build_function_type (V4HI_type_node, | |
18142 | tree_cons (NULL_TREE, V4HI_type_node, | |
18143 | tree_cons (NULL_TREE, V4HI_type_node, | |
18144 | endlink))); | |
18145 | tree v2si_ftype_v2si_v2si | |
18146 | = build_function_type (V2SI_type_node, | |
18147 | tree_cons (NULL_TREE, V2SI_type_node, | |
18148 | tree_cons (NULL_TREE, V2SI_type_node, | |
18149 | endlink))); | |
18150 | tree di_ftype_di_di | |
18151 | = build_function_type (long_long_unsigned_type_node, | |
18152 | tree_cons (NULL_TREE, long_long_unsigned_type_node, | |
18153 | tree_cons (NULL_TREE, | |
18154 | long_long_unsigned_type_node, | |
18155 | endlink))); | |
18156 | ||
18157 | /* Add all builtins that are more or less simple operations on two | |
18158 | operands. */ | |
e97a46ce | 18159 | for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++) |
5a9335ef NC |
18160 | { |
18161 | /* Use one of the operands; the target can have a different mode for | |
18162 | mask-generating compares. */ | |
18163 | enum machine_mode mode; | |
18164 | tree type; | |
18165 | ||
18166 | if (d->name == 0) | |
18167 | continue; | |
18168 | ||
18169 | mode = insn_data[d->icode].operand[1].mode; | |
18170 | ||
18171 | switch (mode) | |
18172 | { | |
18173 | case V8QImode: | |
18174 | type = v8qi_ftype_v8qi_v8qi; | |
18175 | break; | |
18176 | case V4HImode: | |
18177 | type = v4hi_ftype_v4hi_v4hi; | |
18178 | break; | |
18179 | case V2SImode: | |
18180 | type = v2si_ftype_v2si_v2si; | |
18181 | break; | |
18182 | case DImode: | |
18183 | type = di_ftype_di_di; | |
18184 | break; | |
18185 | ||
18186 | default: | |
e6d29d15 | 18187 | gcc_unreachable (); |
5a9335ef NC |
18188 | } |
18189 | ||
18190 | def_mbuiltin (d->mask, d->name, type, d->code); | |
18191 | } | |
18192 | ||
18193 | /* Add the remaining MMX insns with somewhat more complicated types. */ | |
18194 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wzero", di_ftype_void, ARM_BUILTIN_WZERO); | |
18195 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_setwcx", void_ftype_int_int, ARM_BUILTIN_SETWCX); | |
18196 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_getwcx", int_ftype_int, ARM_BUILTIN_GETWCX); | |
18197 | ||
18198 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSLLH); | |
18199 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllw", v2si_ftype_v2si_di, ARM_BUILTIN_WSLLW); | |
18200 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wslld", di_ftype_di_di, ARM_BUILTIN_WSLLD); | |
18201 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSLLHI); | |
18202 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllwi", v2si_ftype_v2si_int, ARM_BUILTIN_WSLLWI); | |
18203 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wslldi", di_ftype_di_int, ARM_BUILTIN_WSLLDI); | |
18204 | ||
18205 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSRLH); | |
18206 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlw", v2si_ftype_v2si_di, ARM_BUILTIN_WSRLW); | |
18207 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrld", di_ftype_di_di, ARM_BUILTIN_WSRLD); | |
18208 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSRLHI); | |
18209 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlwi", v2si_ftype_v2si_int, ARM_BUILTIN_WSRLWI); | |
18210 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrldi", di_ftype_di_int, ARM_BUILTIN_WSRLDI); | |
18211 | ||
18212 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrah", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSRAH); | |
18213 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsraw", v2si_ftype_v2si_di, ARM_BUILTIN_WSRAW); | |
18214 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrad", di_ftype_di_di, ARM_BUILTIN_WSRAD); | |
18215 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrahi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSRAHI); | |
18216 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrawi", v2si_ftype_v2si_int, ARM_BUILTIN_WSRAWI); | |
18217 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsradi", di_ftype_di_int, ARM_BUILTIN_WSRADI); | |
18218 | ||
18219 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WRORH); | |
18220 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorw", v2si_ftype_v2si_di, ARM_BUILTIN_WRORW); | |
18221 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrord", di_ftype_di_di, ARM_BUILTIN_WRORD); | |
18222 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WRORHI); | |
18223 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorwi", v2si_ftype_v2si_int, ARM_BUILTIN_WRORWI); | |
18224 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrordi", di_ftype_di_int, ARM_BUILTIN_WRORDI); | |
18225 | ||
18226 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wshufh", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSHUFH); | |
18227 | ||
18228 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadb", v2si_ftype_v8qi_v8qi, ARM_BUILTIN_WSADB); | |
18229 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadh", v2si_ftype_v4hi_v4hi, ARM_BUILTIN_WSADH); | |
18230 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadbz", v2si_ftype_v8qi_v8qi, ARM_BUILTIN_WSADBZ); | |
18231 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadhz", v2si_ftype_v4hi_v4hi, ARM_BUILTIN_WSADHZ); | |
18232 | ||
18233 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsb", int_ftype_v8qi_int, ARM_BUILTIN_TEXTRMSB); | |
18234 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsh", int_ftype_v4hi_int, ARM_BUILTIN_TEXTRMSH); | |
18235 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsw", int_ftype_v2si_int, ARM_BUILTIN_TEXTRMSW); | |
18236 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmub", int_ftype_v8qi_int, ARM_BUILTIN_TEXTRMUB); | |
18237 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmuh", int_ftype_v4hi_int, ARM_BUILTIN_TEXTRMUH); | |
18238 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmuw", int_ftype_v2si_int, ARM_BUILTIN_TEXTRMUW); | |
18239 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrb", v8qi_ftype_v8qi_int_int, ARM_BUILTIN_TINSRB); | |
18240 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrh", v4hi_ftype_v4hi_int_int, ARM_BUILTIN_TINSRH); | |
18241 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrw", v2si_ftype_v2si_int_int, ARM_BUILTIN_TINSRW); | |
18242 | ||
18243 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_waccb", di_ftype_v8qi, ARM_BUILTIN_WACCB); | |
18244 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wacch", di_ftype_v4hi, ARM_BUILTIN_WACCH); | |
18245 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_waccw", di_ftype_v2si, ARM_BUILTIN_WACCW); | |
18246 | ||
18247 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskb", int_ftype_v8qi, ARM_BUILTIN_TMOVMSKB); | |
18248 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskh", int_ftype_v4hi, ARM_BUILTIN_TMOVMSKH); | |
18249 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskw", int_ftype_v2si, ARM_BUILTIN_TMOVMSKW); | |
18250 | ||
18251 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackhss", v8qi_ftype_v4hi_v4hi, ARM_BUILTIN_WPACKHSS); | |
18252 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackhus", v8qi_ftype_v4hi_v4hi, ARM_BUILTIN_WPACKHUS); | |
18253 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackwus", v4hi_ftype_v2si_v2si, ARM_BUILTIN_WPACKWUS); | |
18254 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackwss", v4hi_ftype_v2si_v2si, ARM_BUILTIN_WPACKWSS); | |
18255 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackdus", v2si_ftype_di_di, ARM_BUILTIN_WPACKDUS); | |
18256 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackdss", v2si_ftype_di_di, ARM_BUILTIN_WPACKDSS); | |
18257 | ||
18258 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehub", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKEHUB); | |
18259 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehuh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKEHUH); | |
18260 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehuw", di_ftype_v2si, ARM_BUILTIN_WUNPCKEHUW); | |
18261 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsb", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKEHSB); | |
18262 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKEHSH); | |
18263 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsw", di_ftype_v2si, ARM_BUILTIN_WUNPCKEHSW); | |
18264 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelub", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKELUB); | |
18265 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckeluh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKELUH); | |
18266 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckeluw", di_ftype_v2si, ARM_BUILTIN_WUNPCKELUW); | |
18267 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsb", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKELSB); | |
18268 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKELSH); | |
18269 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsw", di_ftype_v2si, ARM_BUILTIN_WUNPCKELSW); | |
18270 | ||
18271 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacs", di_ftype_di_v4hi_v4hi, ARM_BUILTIN_WMACS); | |
18272 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacsz", di_ftype_v4hi_v4hi, ARM_BUILTIN_WMACSZ); | |
18273 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacu", di_ftype_di_v4hi_v4hi, ARM_BUILTIN_WMACU); | |
18274 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacuz", di_ftype_v4hi_v4hi, ARM_BUILTIN_WMACUZ); | |
18275 | ||
18276 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_walign", v8qi_ftype_v8qi_v8qi_int, ARM_BUILTIN_WALIGN); | |
18277 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmia", di_ftype_di_int_int, ARM_BUILTIN_TMIA); | |
18278 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiaph", di_ftype_di_int_int, ARM_BUILTIN_TMIAPH); | |
18279 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiabb", di_ftype_di_int_int, ARM_BUILTIN_TMIABB); | |
18280 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiabt", di_ftype_di_int_int, ARM_BUILTIN_TMIABT); | |
18281 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiatb", di_ftype_di_int_int, ARM_BUILTIN_TMIATB); | |
18282 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiatt", di_ftype_di_int_int, ARM_BUILTIN_TMIATT); | |
18283 | } | |
18284 | ||
d3585b76 DJ |
18285 | static void |
18286 | arm_init_tls_builtins (void) | |
18287 | { | |
ebfe65a3 | 18288 | tree ftype, decl; |
d3585b76 DJ |
18289 | |
18290 | ftype = build_function_type (ptr_type_node, void_list_node); | |
ebfe65a3 JJ |
18291 | decl = add_builtin_function ("__builtin_thread_pointer", ftype, |
18292 | ARM_BUILTIN_THREAD_POINTER, BUILT_IN_MD, | |
18293 | NULL, NULL_TREE); | |
18294 | TREE_NOTHROW (decl) = 1; | |
18295 | TREE_READONLY (decl) = 1; | |
d3585b76 DJ |
18296 | } |
18297 | ||
81f40b79 | 18298 | enum neon_builtin_type_bits { |
88f77cba JB |
18299 | T_V8QI = 0x0001, |
18300 | T_V4HI = 0x0002, | |
18301 | T_V2SI = 0x0004, | |
18302 | T_V2SF = 0x0008, | |
18303 | T_DI = 0x0010, | |
18304 | T_V16QI = 0x0020, | |
18305 | T_V8HI = 0x0040, | |
18306 | T_V4SI = 0x0080, | |
18307 | T_V4SF = 0x0100, | |
18308 | T_V2DI = 0x0200, | |
18309 | T_TI = 0x0400, | |
18310 | T_EI = 0x0800, | |
18311 | T_OI = 0x1000 | |
81f40b79 | 18312 | }; |
88f77cba JB |
18313 | |
18314 | #define v8qi_UP T_V8QI | |
18315 | #define v4hi_UP T_V4HI | |
18316 | #define v2si_UP T_V2SI | |
18317 | #define v2sf_UP T_V2SF | |
18318 | #define di_UP T_DI | |
18319 | #define v16qi_UP T_V16QI | |
18320 | #define v8hi_UP T_V8HI | |
18321 | #define v4si_UP T_V4SI | |
18322 | #define v4sf_UP T_V4SF | |
18323 | #define v2di_UP T_V2DI | |
18324 | #define ti_UP T_TI | |
18325 | #define ei_UP T_EI | |
18326 | #define oi_UP T_OI | |
18327 | ||
18328 | #define UP(X) X##_UP | |
18329 | ||
18330 | #define T_MAX 13 | |
18331 | ||
18332 | typedef enum { | |
18333 | NEON_BINOP, | |
18334 | NEON_TERNOP, | |
18335 | NEON_UNOP, | |
18336 | NEON_GETLANE, | |
18337 | NEON_SETLANE, | |
18338 | NEON_CREATE, | |
18339 | NEON_DUP, | |
18340 | NEON_DUPLANE, | |
18341 | NEON_COMBINE, | |
18342 | NEON_SPLIT, | |
18343 | NEON_LANEMUL, | |
18344 | NEON_LANEMULL, | |
18345 | NEON_LANEMULH, | |
18346 | NEON_LANEMAC, | |
18347 | NEON_SCALARMUL, | |
18348 | NEON_SCALARMULL, | |
18349 | NEON_SCALARMULH, | |
18350 | NEON_SCALARMAC, | |
18351 | NEON_CONVERT, | |
18352 | NEON_FIXCONV, | |
18353 | NEON_SELECT, | |
18354 | NEON_RESULTPAIR, | |
18355 | NEON_REINTERP, | |
18356 | NEON_VTBL, | |
18357 | NEON_VTBX, | |
18358 | NEON_LOAD1, | |
18359 | NEON_LOAD1LANE, | |
18360 | NEON_STORE1, | |
18361 | NEON_STORE1LANE, | |
18362 | NEON_LOADSTRUCT, | |
18363 | NEON_LOADSTRUCTLANE, | |
18364 | NEON_STORESTRUCT, | |
18365 | NEON_STORESTRUCTLANE, | |
18366 | NEON_LOGICBINOP, | |
18367 | NEON_SHIFTINSERT, | |
18368 | NEON_SHIFTIMM, | |
18369 | NEON_SHIFTACC | |
18370 | } neon_itype; | |
18371 | ||
18372 | typedef struct { | |
18373 | const char *name; | |
18374 | const neon_itype itype; | |
81f40b79 | 18375 | const int bits; |
88f77cba JB |
18376 | const enum insn_code codes[T_MAX]; |
18377 | const unsigned int num_vars; | |
18378 | unsigned int base_fcode; | |
18379 | } neon_builtin_datum; | |
18380 | ||
18381 | #define CF(N,X) CODE_FOR_neon_##N##X | |
18382 | ||
18383 | #define VAR1(T, N, A) \ | |
18384 | #N, NEON_##T, UP (A), { CF (N, A) }, 1, 0 | |
18385 | #define VAR2(T, N, A, B) \ | |
18386 | #N, NEON_##T, UP (A) | UP (B), { CF (N, A), CF (N, B) }, 2, 0 | |
18387 | #define VAR3(T, N, A, B, C) \ | |
18388 | #N, NEON_##T, UP (A) | UP (B) | UP (C), \ | |
18389 | { CF (N, A), CF (N, B), CF (N, C) }, 3, 0 | |
18390 | #define VAR4(T, N, A, B, C, D) \ | |
18391 | #N, NEON_##T, UP (A) | UP (B) | UP (C) | UP (D), \ | |
18392 | { CF (N, A), CF (N, B), CF (N, C), CF (N, D) }, 4, 0 | |
18393 | #define VAR5(T, N, A, B, C, D, E) \ | |
18394 | #N, NEON_##T, UP (A) | UP (B) | UP (C) | UP (D) | UP (E), \ | |
18395 | { CF (N, A), CF (N, B), CF (N, C), CF (N, D), CF (N, E) }, 5, 0 | |
18396 | #define VAR6(T, N, A, B, C, D, E, F) \ | |
18397 | #N, NEON_##T, UP (A) | UP (B) | UP (C) | UP (D) | UP (E) | UP (F), \ | |
18398 | { CF (N, A), CF (N, B), CF (N, C), CF (N, D), CF (N, E), CF (N, F) }, 6, 0 | |
18399 | #define VAR7(T, N, A, B, C, D, E, F, G) \ | |
18400 | #N, NEON_##T, UP (A) | UP (B) | UP (C) | UP (D) | UP (E) | UP (F) | UP (G), \ | |
18401 | { CF (N, A), CF (N, B), CF (N, C), CF (N, D), CF (N, E), CF (N, F), \ | |
18402 | CF (N, G) }, 7, 0 | |
18403 | #define VAR8(T, N, A, B, C, D, E, F, G, H) \ | |
18404 | #N, NEON_##T, UP (A) | UP (B) | UP (C) | UP (D) | UP (E) | UP (F) | UP (G) \ | |
18405 | | UP (H), \ | |
18406 | { CF (N, A), CF (N, B), CF (N, C), CF (N, D), CF (N, E), CF (N, F), \ | |
18407 | CF (N, G), CF (N, H) }, 8, 0 | |
18408 | #define VAR9(T, N, A, B, C, D, E, F, G, H, I) \ | |
18409 | #N, NEON_##T, UP (A) | UP (B) | UP (C) | UP (D) | UP (E) | UP (F) | UP (G) \ | |
18410 | | UP (H) | UP (I), \ | |
18411 | { CF (N, A), CF (N, B), CF (N, C), CF (N, D), CF (N, E), CF (N, F), \ | |
18412 | CF (N, G), CF (N, H), CF (N, I) }, 9, 0 | |
18413 | #define VAR10(T, N, A, B, C, D, E, F, G, H, I, J) \ | |
18414 | #N, NEON_##T, UP (A) | UP (B) | UP (C) | UP (D) | UP (E) | UP (F) | UP (G) \ | |
18415 | | UP (H) | UP (I) | UP (J), \ | |
18416 | { CF (N, A), CF (N, B), CF (N, C), CF (N, D), CF (N, E), CF (N, F), \ | |
18417 | CF (N, G), CF (N, H), CF (N, I), CF (N, J) }, 10, 0 | |
18418 | ||
18419 | /* The mode entries in the following table correspond to the "key" type of the | |
18420 | instruction variant, i.e. equivalent to that which would be specified after | |
18421 | the assembler mnemonic, which usually refers to the last vector operand. | |
18422 | (Signed/unsigned/polynomial types are not differentiated between though, and | |
18423 | are all mapped onto the same mode for a given element size.) The modes | |
18424 | listed per instruction should be the same as those defined for that | |
18425 | instruction's pattern in neon.md. | |
18426 | WARNING: Variants should be listed in the same increasing order as | |
18427 | neon_builtin_type_bits. */ | |
18428 | ||
18429 | static neon_builtin_datum neon_builtin_data[] = | |
18430 | { | |
18431 | { VAR10 (BINOP, vadd, | |
18432 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, | |
18433 | { VAR3 (BINOP, vaddl, v8qi, v4hi, v2si) }, | |
18434 | { VAR3 (BINOP, vaddw, v8qi, v4hi, v2si) }, | |
18435 | { VAR6 (BINOP, vhadd, v8qi, v4hi, v2si, v16qi, v8hi, v4si) }, | |
18436 | { VAR8 (BINOP, vqadd, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, | |
18437 | { VAR3 (BINOP, vaddhn, v8hi, v4si, v2di) }, | |
18438 | { VAR8 (BINOP, vmul, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) }, | |
18439 | { VAR8 (TERNOP, vmla, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) }, | |
18440 | { VAR3 (TERNOP, vmlal, v8qi, v4hi, v2si) }, | |
18441 | { VAR8 (TERNOP, vmls, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) }, | |
18442 | { VAR3 (TERNOP, vmlsl, v8qi, v4hi, v2si) }, | |
18443 | { VAR4 (BINOP, vqdmulh, v4hi, v2si, v8hi, v4si) }, | |
18444 | { VAR2 (TERNOP, vqdmlal, v4hi, v2si) }, | |
18445 | { VAR2 (TERNOP, vqdmlsl, v4hi, v2si) }, | |
18446 | { VAR3 (BINOP, vmull, v8qi, v4hi, v2si) }, | |
18447 | { VAR2 (SCALARMULL, vmull_n, v4hi, v2si) }, | |
18448 | { VAR2 (LANEMULL, vmull_lane, v4hi, v2si) }, | |
18449 | { VAR2 (SCALARMULL, vqdmull_n, v4hi, v2si) }, | |
18450 | { VAR2 (LANEMULL, vqdmull_lane, v4hi, v2si) }, | |
18451 | { VAR4 (SCALARMULH, vqdmulh_n, v4hi, v2si, v8hi, v4si) }, | |
18452 | { VAR4 (LANEMULH, vqdmulh_lane, v4hi, v2si, v8hi, v4si) }, | |
18453 | { VAR2 (BINOP, vqdmull, v4hi, v2si) }, | |
18454 | { VAR8 (BINOP, vshl, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, | |
18455 | { VAR8 (BINOP, vqshl, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, | |
18456 | { VAR8 (SHIFTIMM, vshr_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, | |
18457 | { VAR3 (SHIFTIMM, vshrn_n, v8hi, v4si, v2di) }, | |
18458 | { VAR3 (SHIFTIMM, vqshrn_n, v8hi, v4si, v2di) }, | |
18459 | { VAR3 (SHIFTIMM, vqshrun_n, v8hi, v4si, v2di) }, | |
18460 | { VAR8 (SHIFTIMM, vshl_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, | |
18461 | { VAR8 (SHIFTIMM, vqshl_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, | |
18462 | { VAR8 (SHIFTIMM, vqshlu_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, | |
18463 | { VAR3 (SHIFTIMM, vshll_n, v8qi, v4hi, v2si) }, | |
18464 | { VAR8 (SHIFTACC, vsra_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, | |
18465 | { VAR10 (BINOP, vsub, | |
18466 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, | |
18467 | { VAR3 (BINOP, vsubl, v8qi, v4hi, v2si) }, | |
18468 | { VAR3 (BINOP, vsubw, v8qi, v4hi, v2si) }, | |
18469 | { VAR8 (BINOP, vqsub, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, | |
18470 | { VAR6 (BINOP, vhsub, v8qi, v4hi, v2si, v16qi, v8hi, v4si) }, | |
18471 | { VAR3 (BINOP, vsubhn, v8hi, v4si, v2di) }, | |
18472 | { VAR8 (BINOP, vceq, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) }, | |
18473 | { VAR8 (BINOP, vcge, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) }, | |
18474 | { VAR8 (BINOP, vcgt, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) }, | |
18475 | { VAR2 (BINOP, vcage, v2sf, v4sf) }, | |
18476 | { VAR2 (BINOP, vcagt, v2sf, v4sf) }, | |
18477 | { VAR6 (BINOP, vtst, v8qi, v4hi, v2si, v16qi, v8hi, v4si) }, | |
18478 | { VAR8 (BINOP, vabd, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) }, | |
18479 | { VAR3 (BINOP, vabdl, v8qi, v4hi, v2si) }, | |
18480 | { VAR6 (TERNOP, vaba, v8qi, v4hi, v2si, v16qi, v8hi, v4si) }, | |
18481 | { VAR3 (TERNOP, vabal, v8qi, v4hi, v2si) }, | |
18482 | { VAR8 (BINOP, vmax, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) }, | |
18483 | { VAR8 (BINOP, vmin, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) }, | |
18484 | { VAR4 (BINOP, vpadd, v8qi, v4hi, v2si, v2sf) }, | |
18485 | { VAR6 (UNOP, vpaddl, v8qi, v4hi, v2si, v16qi, v8hi, v4si) }, | |
18486 | { VAR6 (BINOP, vpadal, v8qi, v4hi, v2si, v16qi, v8hi, v4si) }, | |
18487 | { VAR4 (BINOP, vpmax, v8qi, v4hi, v2si, v2sf) }, | |
18488 | { VAR4 (BINOP, vpmin, v8qi, v4hi, v2si, v2sf) }, | |
18489 | { VAR2 (BINOP, vrecps, v2sf, v4sf) }, | |
18490 | { VAR2 (BINOP, vrsqrts, v2sf, v4sf) }, | |
18491 | { VAR8 (SHIFTINSERT, vsri_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, | |
18492 | { VAR8 (SHIFTINSERT, vsli_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, | |
18493 | { VAR8 (UNOP, vabs, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) }, | |
18494 | { VAR6 (UNOP, vqabs, v8qi, v4hi, v2si, v16qi, v8hi, v4si) }, | |
18495 | { VAR8 (UNOP, vneg, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) }, | |
18496 | { VAR6 (UNOP, vqneg, v8qi, v4hi, v2si, v16qi, v8hi, v4si) }, | |
18497 | { VAR6 (UNOP, vcls, v8qi, v4hi, v2si, v16qi, v8hi, v4si) }, | |
18498 | { VAR6 (UNOP, vclz, v8qi, v4hi, v2si, v16qi, v8hi, v4si) }, | |
18499 | { VAR2 (UNOP, vcnt, v8qi, v16qi) }, | |
18500 | { VAR4 (UNOP, vrecpe, v2si, v2sf, v4si, v4sf) }, | |
18501 | { VAR4 (UNOP, vrsqrte, v2si, v2sf, v4si, v4sf) }, | |
18502 | { VAR6 (UNOP, vmvn, v8qi, v4hi, v2si, v16qi, v8hi, v4si) }, | |
18503 | /* FIXME: vget_lane supports more variants than this! */ | |
18504 | { VAR10 (GETLANE, vget_lane, | |
18505 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, | |
18506 | { VAR10 (SETLANE, vset_lane, | |
18507 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, | |
18508 | { VAR5 (CREATE, vcreate, v8qi, v4hi, v2si, v2sf, di) }, | |
18509 | { VAR10 (DUP, vdup_n, | |
18510 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, | |
18511 | { VAR10 (DUPLANE, vdup_lane, | |
18512 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, | |
18513 | { VAR5 (COMBINE, vcombine, v8qi, v4hi, v2si, v2sf, di) }, | |
18514 | { VAR5 (SPLIT, vget_high, v16qi, v8hi, v4si, v4sf, v2di) }, | |
18515 | { VAR5 (SPLIT, vget_low, v16qi, v8hi, v4si, v4sf, v2di) }, | |
18516 | { VAR3 (UNOP, vmovn, v8hi, v4si, v2di) }, | |
18517 | { VAR3 (UNOP, vqmovn, v8hi, v4si, v2di) }, | |
18518 | { VAR3 (UNOP, vqmovun, v8hi, v4si, v2di) }, | |
18519 | { VAR3 (UNOP, vmovl, v8qi, v4hi, v2si) }, | |
18520 | { VAR6 (LANEMUL, vmul_lane, v4hi, v2si, v2sf, v8hi, v4si, v4sf) }, | |
18521 | { VAR6 (LANEMAC, vmla_lane, v4hi, v2si, v2sf, v8hi, v4si, v4sf) }, | |
18522 | { VAR2 (LANEMAC, vmlal_lane, v4hi, v2si) }, | |
18523 | { VAR2 (LANEMAC, vqdmlal_lane, v4hi, v2si) }, | |
18524 | { VAR6 (LANEMAC, vmls_lane, v4hi, v2si, v2sf, v8hi, v4si, v4sf) }, | |
18525 | { VAR2 (LANEMAC, vmlsl_lane, v4hi, v2si) }, | |
18526 | { VAR2 (LANEMAC, vqdmlsl_lane, v4hi, v2si) }, | |
18527 | { VAR6 (SCALARMUL, vmul_n, v4hi, v2si, v2sf, v8hi, v4si, v4sf) }, | |
18528 | { VAR6 (SCALARMAC, vmla_n, v4hi, v2si, v2sf, v8hi, v4si, v4sf) }, | |
18529 | { VAR2 (SCALARMAC, vmlal_n, v4hi, v2si) }, | |
18530 | { VAR2 (SCALARMAC, vqdmlal_n, v4hi, v2si) }, | |
18531 | { VAR6 (SCALARMAC, vmls_n, v4hi, v2si, v2sf, v8hi, v4si, v4sf) }, | |
18532 | { VAR2 (SCALARMAC, vmlsl_n, v4hi, v2si) }, | |
18533 | { VAR2 (SCALARMAC, vqdmlsl_n, v4hi, v2si) }, | |
18534 | { VAR10 (BINOP, vext, | |
18535 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, | |
18536 | { VAR8 (UNOP, vrev64, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) }, | |
18537 | { VAR4 (UNOP, vrev32, v8qi, v4hi, v16qi, v8hi) }, | |
18538 | { VAR2 (UNOP, vrev16, v8qi, v16qi) }, | |
18539 | { VAR4 (CONVERT, vcvt, v2si, v2sf, v4si, v4sf) }, | |
18540 | { VAR4 (FIXCONV, vcvt_n, v2si, v2sf, v4si, v4sf) }, | |
18541 | { VAR10 (SELECT, vbsl, | |
18542 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, | |
18543 | { VAR1 (VTBL, vtbl1, v8qi) }, | |
18544 | { VAR1 (VTBL, vtbl2, v8qi) }, | |
18545 | { VAR1 (VTBL, vtbl3, v8qi) }, | |
18546 | { VAR1 (VTBL, vtbl4, v8qi) }, | |
18547 | { VAR1 (VTBX, vtbx1, v8qi) }, | |
18548 | { VAR1 (VTBX, vtbx2, v8qi) }, | |
18549 | { VAR1 (VTBX, vtbx3, v8qi) }, | |
18550 | { VAR1 (VTBX, vtbx4, v8qi) }, | |
18551 | { VAR8 (RESULTPAIR, vtrn, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) }, | |
18552 | { VAR8 (RESULTPAIR, vzip, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) }, | |
18553 | { VAR8 (RESULTPAIR, vuzp, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) }, | |
18554 | { VAR5 (REINTERP, vreinterpretv8qi, v8qi, v4hi, v2si, v2sf, di) }, | |
18555 | { VAR5 (REINTERP, vreinterpretv4hi, v8qi, v4hi, v2si, v2sf, di) }, | |
18556 | { VAR5 (REINTERP, vreinterpretv2si, v8qi, v4hi, v2si, v2sf, di) }, | |
18557 | { VAR5 (REINTERP, vreinterpretv2sf, v8qi, v4hi, v2si, v2sf, di) }, | |
18558 | { VAR5 (REINTERP, vreinterpretdi, v8qi, v4hi, v2si, v2sf, di) }, | |
18559 | { VAR5 (REINTERP, vreinterpretv16qi, v16qi, v8hi, v4si, v4sf, v2di) }, | |
18560 | { VAR5 (REINTERP, vreinterpretv8hi, v16qi, v8hi, v4si, v4sf, v2di) }, | |
18561 | { VAR5 (REINTERP, vreinterpretv4si, v16qi, v8hi, v4si, v4sf, v2di) }, | |
18562 | { VAR5 (REINTERP, vreinterpretv4sf, v16qi, v8hi, v4si, v4sf, v2di) }, | |
18563 | { VAR5 (REINTERP, vreinterpretv2di, v16qi, v8hi, v4si, v4sf, v2di) }, | |
18564 | { VAR10 (LOAD1, vld1, | |
18565 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, | |
18566 | { VAR10 (LOAD1LANE, vld1_lane, | |
18567 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, | |
18568 | { VAR10 (LOAD1, vld1_dup, | |
18569 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, | |
18570 | { VAR10 (STORE1, vst1, | |
18571 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, | |
18572 | { VAR10 (STORE1LANE, vst1_lane, | |
18573 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, | |
18574 | { VAR9 (LOADSTRUCT, | |
18575 | vld2, v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf) }, | |
18576 | { VAR7 (LOADSTRUCTLANE, vld2_lane, | |
18577 | v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf) }, | |
18578 | { VAR5 (LOADSTRUCT, vld2_dup, v8qi, v4hi, v2si, v2sf, di) }, | |
18579 | { VAR9 (STORESTRUCT, vst2, | |
18580 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf) }, | |
18581 | { VAR7 (STORESTRUCTLANE, vst2_lane, | |
18582 | v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf) }, | |
18583 | { VAR9 (LOADSTRUCT, | |
18584 | vld3, v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf) }, | |
18585 | { VAR7 (LOADSTRUCTLANE, vld3_lane, | |
18586 | v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf) }, | |
18587 | { VAR5 (LOADSTRUCT, vld3_dup, v8qi, v4hi, v2si, v2sf, di) }, | |
18588 | { VAR9 (STORESTRUCT, vst3, | |
18589 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf) }, | |
18590 | { VAR7 (STORESTRUCTLANE, vst3_lane, | |
18591 | v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf) }, | |
18592 | { VAR9 (LOADSTRUCT, vld4, | |
18593 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf) }, | |
18594 | { VAR7 (LOADSTRUCTLANE, vld4_lane, | |
18595 | v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf) }, | |
18596 | { VAR5 (LOADSTRUCT, vld4_dup, v8qi, v4hi, v2si, v2sf, di) }, | |
18597 | { VAR9 (STORESTRUCT, vst4, | |
18598 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf) }, | |
18599 | { VAR7 (STORESTRUCTLANE, vst4_lane, | |
18600 | v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf) }, | |
18601 | { VAR10 (LOGICBINOP, vand, | |
18602 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, | |
18603 | { VAR10 (LOGICBINOP, vorr, | |
18604 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, | |
18605 | { VAR10 (BINOP, veor, | |
18606 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, | |
18607 | { VAR10 (LOGICBINOP, vbic, | |
18608 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, | |
18609 | { VAR10 (LOGICBINOP, vorn, | |
18610 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) } | |
18611 | }; | |
18612 | ||
18613 | #undef CF | |
18614 | #undef VAR1 | |
18615 | #undef VAR2 | |
18616 | #undef VAR3 | |
18617 | #undef VAR4 | |
18618 | #undef VAR5 | |
18619 | #undef VAR6 | |
18620 | #undef VAR7 | |
18621 | #undef VAR8 | |
18622 | #undef VAR9 | |
18623 | #undef VAR10 | |
18624 | ||
18625 | static void | |
18626 | arm_init_neon_builtins (void) | |
18627 | { | |
18628 | unsigned int i, fcode = ARM_BUILTIN_NEON_BASE; | |
18629 | ||
af06585a JM |
18630 | tree neon_intQI_type_node; |
18631 | tree neon_intHI_type_node; | |
18632 | tree neon_polyQI_type_node; | |
18633 | tree neon_polyHI_type_node; | |
18634 | tree neon_intSI_type_node; | |
18635 | tree neon_intDI_type_node; | |
18636 | tree neon_float_type_node; | |
18637 | ||
18638 | tree intQI_pointer_node; | |
18639 | tree intHI_pointer_node; | |
18640 | tree intSI_pointer_node; | |
18641 | tree intDI_pointer_node; | |
18642 | tree float_pointer_node; | |
18643 | ||
18644 | tree const_intQI_node; | |
18645 | tree const_intHI_node; | |
18646 | tree const_intSI_node; | |
18647 | tree const_intDI_node; | |
18648 | tree const_float_node; | |
18649 | ||
18650 | tree const_intQI_pointer_node; | |
18651 | tree const_intHI_pointer_node; | |
18652 | tree const_intSI_pointer_node; | |
18653 | tree const_intDI_pointer_node; | |
18654 | tree const_float_pointer_node; | |
18655 | ||
18656 | tree V8QI_type_node; | |
18657 | tree V4HI_type_node; | |
18658 | tree V2SI_type_node; | |
18659 | tree V2SF_type_node; | |
18660 | tree V16QI_type_node; | |
18661 | tree V8HI_type_node; | |
18662 | tree V4SI_type_node; | |
18663 | tree V4SF_type_node; | |
18664 | tree V2DI_type_node; | |
18665 | ||
18666 | tree intUQI_type_node; | |
18667 | tree intUHI_type_node; | |
18668 | tree intUSI_type_node; | |
18669 | tree intUDI_type_node; | |
18670 | ||
18671 | tree intEI_type_node; | |
18672 | tree intOI_type_node; | |
18673 | tree intCI_type_node; | |
18674 | tree intXI_type_node; | |
18675 | ||
18676 | tree V8QI_pointer_node; | |
18677 | tree V4HI_pointer_node; | |
18678 | tree V2SI_pointer_node; | |
18679 | tree V2SF_pointer_node; | |
18680 | tree V16QI_pointer_node; | |
18681 | tree V8HI_pointer_node; | |
18682 | tree V4SI_pointer_node; | |
18683 | tree V4SF_pointer_node; | |
18684 | tree V2DI_pointer_node; | |
18685 | ||
18686 | tree void_ftype_pv8qi_v8qi_v8qi; | |
18687 | tree void_ftype_pv4hi_v4hi_v4hi; | |
18688 | tree void_ftype_pv2si_v2si_v2si; | |
18689 | tree void_ftype_pv2sf_v2sf_v2sf; | |
18690 | tree void_ftype_pdi_di_di; | |
18691 | tree void_ftype_pv16qi_v16qi_v16qi; | |
18692 | tree void_ftype_pv8hi_v8hi_v8hi; | |
18693 | tree void_ftype_pv4si_v4si_v4si; | |
18694 | tree void_ftype_pv4sf_v4sf_v4sf; | |
18695 | tree void_ftype_pv2di_v2di_v2di; | |
18696 | ||
18697 | tree reinterp_ftype_dreg[5][5]; | |
18698 | tree reinterp_ftype_qreg[5][5]; | |
18699 | tree dreg_types[5], qreg_types[5]; | |
18700 | ||
88f77cba JB |
18701 | /* Create distinguished type nodes for NEON vector element types, |
18702 | and pointers to values of such types, so we can detect them later. */ | |
af06585a JM |
18703 | neon_intQI_type_node = make_signed_type (GET_MODE_PRECISION (QImode)); |
18704 | neon_intHI_type_node = make_signed_type (GET_MODE_PRECISION (HImode)); | |
18705 | neon_polyQI_type_node = make_signed_type (GET_MODE_PRECISION (QImode)); | |
18706 | neon_polyHI_type_node = make_signed_type (GET_MODE_PRECISION (HImode)); | |
18707 | neon_intSI_type_node = make_signed_type (GET_MODE_PRECISION (SImode)); | |
18708 | neon_intDI_type_node = make_signed_type (GET_MODE_PRECISION (DImode)); | |
18709 | neon_float_type_node = make_node (REAL_TYPE); | |
18710 | TYPE_PRECISION (neon_float_type_node) = FLOAT_TYPE_SIZE; | |
18711 | layout_type (neon_float_type_node); | |
18712 | ||
bcbdbbb0 JM |
18713 | /* Define typedefs which exactly correspond to the modes we are basing vector |
18714 | types on. If you change these names you'll need to change | |
18715 | the table used by arm_mangle_type too. */ | |
18716 | (*lang_hooks.types.register_builtin_type) (neon_intQI_type_node, | |
18717 | "__builtin_neon_qi"); | |
18718 | (*lang_hooks.types.register_builtin_type) (neon_intHI_type_node, | |
18719 | "__builtin_neon_hi"); | |
18720 | (*lang_hooks.types.register_builtin_type) (neon_intSI_type_node, | |
18721 | "__builtin_neon_si"); | |
18722 | (*lang_hooks.types.register_builtin_type) (neon_float_type_node, | |
18723 | "__builtin_neon_sf"); | |
18724 | (*lang_hooks.types.register_builtin_type) (neon_intDI_type_node, | |
18725 | "__builtin_neon_di"); | |
18726 | (*lang_hooks.types.register_builtin_type) (neon_polyQI_type_node, | |
18727 | "__builtin_neon_poly8"); | |
18728 | (*lang_hooks.types.register_builtin_type) (neon_polyHI_type_node, | |
18729 | "__builtin_neon_poly16"); | |
18730 | ||
af06585a JM |
18731 | intQI_pointer_node = build_pointer_type (neon_intQI_type_node); |
18732 | intHI_pointer_node = build_pointer_type (neon_intHI_type_node); | |
18733 | intSI_pointer_node = build_pointer_type (neon_intSI_type_node); | |
18734 | intDI_pointer_node = build_pointer_type (neon_intDI_type_node); | |
18735 | float_pointer_node = build_pointer_type (neon_float_type_node); | |
88f77cba JB |
18736 | |
18737 | /* Next create constant-qualified versions of the above types. */ | |
af06585a JM |
18738 | const_intQI_node = build_qualified_type (neon_intQI_type_node, |
18739 | TYPE_QUAL_CONST); | |
18740 | const_intHI_node = build_qualified_type (neon_intHI_type_node, | |
18741 | TYPE_QUAL_CONST); | |
18742 | const_intSI_node = build_qualified_type (neon_intSI_type_node, | |
18743 | TYPE_QUAL_CONST); | |
18744 | const_intDI_node = build_qualified_type (neon_intDI_type_node, | |
18745 | TYPE_QUAL_CONST); | |
18746 | const_float_node = build_qualified_type (neon_float_type_node, | |
18747 | TYPE_QUAL_CONST); | |
18748 | ||
18749 | const_intQI_pointer_node = build_pointer_type (const_intQI_node); | |
18750 | const_intHI_pointer_node = build_pointer_type (const_intHI_node); | |
18751 | const_intSI_pointer_node = build_pointer_type (const_intSI_node); | |
18752 | const_intDI_pointer_node = build_pointer_type (const_intDI_node); | |
18753 | const_float_pointer_node = build_pointer_type (const_float_node); | |
88f77cba JB |
18754 | |
18755 | /* Now create vector types based on our NEON element types. */ | |
18756 | /* 64-bit vectors. */ | |
af06585a | 18757 | V8QI_type_node = |
88f77cba | 18758 | build_vector_type_for_mode (neon_intQI_type_node, V8QImode); |
af06585a | 18759 | V4HI_type_node = |
88f77cba | 18760 | build_vector_type_for_mode (neon_intHI_type_node, V4HImode); |
af06585a | 18761 | V2SI_type_node = |
88f77cba | 18762 | build_vector_type_for_mode (neon_intSI_type_node, V2SImode); |
af06585a | 18763 | V2SF_type_node = |
88f77cba JB |
18764 | build_vector_type_for_mode (neon_float_type_node, V2SFmode); |
18765 | /* 128-bit vectors. */ | |
af06585a | 18766 | V16QI_type_node = |
88f77cba | 18767 | build_vector_type_for_mode (neon_intQI_type_node, V16QImode); |
af06585a | 18768 | V8HI_type_node = |
88f77cba | 18769 | build_vector_type_for_mode (neon_intHI_type_node, V8HImode); |
af06585a | 18770 | V4SI_type_node = |
88f77cba | 18771 | build_vector_type_for_mode (neon_intSI_type_node, V4SImode); |
af06585a | 18772 | V4SF_type_node = |
88f77cba | 18773 | build_vector_type_for_mode (neon_float_type_node, V4SFmode); |
af06585a | 18774 | V2DI_type_node = |
88f77cba JB |
18775 | build_vector_type_for_mode (neon_intDI_type_node, V2DImode); |
18776 | ||
18777 | /* Unsigned integer types for various mode sizes. */ | |
af06585a JM |
18778 | intUQI_type_node = make_unsigned_type (GET_MODE_PRECISION (QImode)); |
18779 | intUHI_type_node = make_unsigned_type (GET_MODE_PRECISION (HImode)); | |
18780 | intUSI_type_node = make_unsigned_type (GET_MODE_PRECISION (SImode)); | |
18781 | intUDI_type_node = make_unsigned_type (GET_MODE_PRECISION (DImode)); | |
88f77cba | 18782 | |
bcbdbbb0 JM |
18783 | (*lang_hooks.types.register_builtin_type) (intUQI_type_node, |
18784 | "__builtin_neon_uqi"); | |
18785 | (*lang_hooks.types.register_builtin_type) (intUHI_type_node, | |
18786 | "__builtin_neon_uhi"); | |
18787 | (*lang_hooks.types.register_builtin_type) (intUSI_type_node, | |
18788 | "__builtin_neon_usi"); | |
18789 | (*lang_hooks.types.register_builtin_type) (intUDI_type_node, | |
18790 | "__builtin_neon_udi"); | |
18791 | ||
88f77cba | 18792 | /* Opaque integer types for structures of vectors. */ |
af06585a JM |
18793 | intEI_type_node = make_signed_type (GET_MODE_PRECISION (EImode)); |
18794 | intOI_type_node = make_signed_type (GET_MODE_PRECISION (OImode)); | |
18795 | intCI_type_node = make_signed_type (GET_MODE_PRECISION (CImode)); | |
18796 | intXI_type_node = make_signed_type (GET_MODE_PRECISION (XImode)); | |
88f77cba | 18797 | |
bcbdbbb0 JM |
18798 | (*lang_hooks.types.register_builtin_type) (intTI_type_node, |
18799 | "__builtin_neon_ti"); | |
18800 | (*lang_hooks.types.register_builtin_type) (intEI_type_node, | |
18801 | "__builtin_neon_ei"); | |
18802 | (*lang_hooks.types.register_builtin_type) (intOI_type_node, | |
18803 | "__builtin_neon_oi"); | |
18804 | (*lang_hooks.types.register_builtin_type) (intCI_type_node, | |
18805 | "__builtin_neon_ci"); | |
18806 | (*lang_hooks.types.register_builtin_type) (intXI_type_node, | |
18807 | "__builtin_neon_xi"); | |
18808 | ||
88f77cba | 18809 | /* Pointers to vector types. */ |
af06585a JM |
18810 | V8QI_pointer_node = build_pointer_type (V8QI_type_node); |
18811 | V4HI_pointer_node = build_pointer_type (V4HI_type_node); | |
18812 | V2SI_pointer_node = build_pointer_type (V2SI_type_node); | |
18813 | V2SF_pointer_node = build_pointer_type (V2SF_type_node); | |
18814 | V16QI_pointer_node = build_pointer_type (V16QI_type_node); | |
18815 | V8HI_pointer_node = build_pointer_type (V8HI_type_node); | |
18816 | V4SI_pointer_node = build_pointer_type (V4SI_type_node); | |
18817 | V4SF_pointer_node = build_pointer_type (V4SF_type_node); | |
18818 | V2DI_pointer_node = build_pointer_type (V2DI_type_node); | |
88f77cba JB |
18819 | |
18820 | /* Operations which return results as pairs. */ | |
af06585a | 18821 | void_ftype_pv8qi_v8qi_v8qi = |
88f77cba JB |
18822 | build_function_type_list (void_type_node, V8QI_pointer_node, V8QI_type_node, |
18823 | V8QI_type_node, NULL); | |
af06585a | 18824 | void_ftype_pv4hi_v4hi_v4hi = |
88f77cba JB |
18825 | build_function_type_list (void_type_node, V4HI_pointer_node, V4HI_type_node, |
18826 | V4HI_type_node, NULL); | |
af06585a | 18827 | void_ftype_pv2si_v2si_v2si = |
88f77cba JB |
18828 | build_function_type_list (void_type_node, V2SI_pointer_node, V2SI_type_node, |
18829 | V2SI_type_node, NULL); | |
af06585a | 18830 | void_ftype_pv2sf_v2sf_v2sf = |
88f77cba JB |
18831 | build_function_type_list (void_type_node, V2SF_pointer_node, V2SF_type_node, |
18832 | V2SF_type_node, NULL); | |
af06585a | 18833 | void_ftype_pdi_di_di = |
88f77cba JB |
18834 | build_function_type_list (void_type_node, intDI_pointer_node, |
18835 | neon_intDI_type_node, neon_intDI_type_node, NULL); | |
af06585a | 18836 | void_ftype_pv16qi_v16qi_v16qi = |
88f77cba JB |
18837 | build_function_type_list (void_type_node, V16QI_pointer_node, |
18838 | V16QI_type_node, V16QI_type_node, NULL); | |
af06585a | 18839 | void_ftype_pv8hi_v8hi_v8hi = |
88f77cba JB |
18840 | build_function_type_list (void_type_node, V8HI_pointer_node, V8HI_type_node, |
18841 | V8HI_type_node, NULL); | |
af06585a | 18842 | void_ftype_pv4si_v4si_v4si = |
88f77cba JB |
18843 | build_function_type_list (void_type_node, V4SI_pointer_node, V4SI_type_node, |
18844 | V4SI_type_node, NULL); | |
af06585a | 18845 | void_ftype_pv4sf_v4sf_v4sf = |
88f77cba JB |
18846 | build_function_type_list (void_type_node, V4SF_pointer_node, V4SF_type_node, |
18847 | V4SF_type_node, NULL); | |
af06585a | 18848 | void_ftype_pv2di_v2di_v2di = |
88f77cba JB |
18849 | build_function_type_list (void_type_node, V2DI_pointer_node, V2DI_type_node, |
18850 | V2DI_type_node, NULL); | |
18851 | ||
88f77cba JB |
18852 | dreg_types[0] = V8QI_type_node; |
18853 | dreg_types[1] = V4HI_type_node; | |
18854 | dreg_types[2] = V2SI_type_node; | |
18855 | dreg_types[3] = V2SF_type_node; | |
18856 | dreg_types[4] = neon_intDI_type_node; | |
18857 | ||
18858 | qreg_types[0] = V16QI_type_node; | |
18859 | qreg_types[1] = V8HI_type_node; | |
18860 | qreg_types[2] = V4SI_type_node; | |
18861 | qreg_types[3] = V4SF_type_node; | |
18862 | qreg_types[4] = V2DI_type_node; | |
18863 | ||
18864 | for (i = 0; i < 5; i++) | |
18865 | { | |
18866 | int j; | |
18867 | for (j = 0; j < 5; j++) | |
18868 | { | |
18869 | reinterp_ftype_dreg[i][j] | |
18870 | = build_function_type_list (dreg_types[i], dreg_types[j], NULL); | |
18871 | reinterp_ftype_qreg[i][j] | |
18872 | = build_function_type_list (qreg_types[i], qreg_types[j], NULL); | |
18873 | } | |
18874 | } | |
18875 | ||
18876 | for (i = 0; i < ARRAY_SIZE (neon_builtin_data); i++) | |
18877 | { | |
18878 | neon_builtin_datum *d = &neon_builtin_data[i]; | |
18879 | unsigned int j, codeidx = 0; | |
18880 | ||
18881 | d->base_fcode = fcode; | |
18882 | ||
18883 | for (j = 0; j < T_MAX; j++) | |
18884 | { | |
18885 | const char* const modenames[] = { | |
18886 | "v8qi", "v4hi", "v2si", "v2sf", "di", | |
18887 | "v16qi", "v8hi", "v4si", "v4sf", "v2di" | |
18888 | }; | |
18889 | char namebuf[60]; | |
18890 | tree ftype = NULL; | |
18891 | enum insn_code icode; | |
18892 | int is_load = 0, is_store = 0; | |
18893 | ||
18894 | if ((d->bits & (1 << j)) == 0) | |
18895 | continue; | |
18896 | ||
18897 | icode = d->codes[codeidx++]; | |
18898 | ||
18899 | switch (d->itype) | |
18900 | { | |
18901 | case NEON_LOAD1: | |
18902 | case NEON_LOAD1LANE: | |
18903 | case NEON_LOADSTRUCT: | |
18904 | case NEON_LOADSTRUCTLANE: | |
18905 | is_load = 1; | |
18906 | /* Fall through. */ | |
18907 | case NEON_STORE1: | |
18908 | case NEON_STORE1LANE: | |
18909 | case NEON_STORESTRUCT: | |
18910 | case NEON_STORESTRUCTLANE: | |
18911 | if (!is_load) | |
18912 | is_store = 1; | |
18913 | /* Fall through. */ | |
18914 | case NEON_UNOP: | |
18915 | case NEON_BINOP: | |
18916 | case NEON_LOGICBINOP: | |
18917 | case NEON_SHIFTINSERT: | |
18918 | case NEON_TERNOP: | |
18919 | case NEON_GETLANE: | |
18920 | case NEON_SETLANE: | |
18921 | case NEON_CREATE: | |
18922 | case NEON_DUP: | |
18923 | case NEON_DUPLANE: | |
18924 | case NEON_SHIFTIMM: | |
18925 | case NEON_SHIFTACC: | |
18926 | case NEON_COMBINE: | |
18927 | case NEON_SPLIT: | |
18928 | case NEON_CONVERT: | |
18929 | case NEON_FIXCONV: | |
18930 | case NEON_LANEMUL: | |
18931 | case NEON_LANEMULL: | |
18932 | case NEON_LANEMULH: | |
18933 | case NEON_LANEMAC: | |
18934 | case NEON_SCALARMUL: | |
18935 | case NEON_SCALARMULL: | |
18936 | case NEON_SCALARMULH: | |
18937 | case NEON_SCALARMAC: | |
18938 | case NEON_SELECT: | |
18939 | case NEON_VTBL: | |
18940 | case NEON_VTBX: | |
18941 | { | |
18942 | int k; | |
18943 | tree return_type = void_type_node, args = void_list_node; | |
18944 | ||
18945 | /* Build a function type directly from the insn_data for this | |
18946 | builtin. The build_function_type() function takes care of | |
18947 | removing duplicates for us. */ | |
18948 | for (k = insn_data[icode].n_operands - 1; k >= 0; k--) | |
18949 | { | |
18950 | tree eltype; | |
18951 | ||
18952 | if (is_load && k == 1) | |
18953 | { | |
18954 | /* Neon load patterns always have the memory operand | |
18955 | (a SImode pointer) in the operand 1 position. We | |
18956 | want a const pointer to the element type in that | |
18957 | position. */ | |
18958 | gcc_assert (insn_data[icode].operand[k].mode == SImode); | |
18959 | ||
18960 | switch (1 << j) | |
18961 | { | |
18962 | case T_V8QI: | |
18963 | case T_V16QI: | |
18964 | eltype = const_intQI_pointer_node; | |
18965 | break; | |
18966 | ||
18967 | case T_V4HI: | |
18968 | case T_V8HI: | |
18969 | eltype = const_intHI_pointer_node; | |
18970 | break; | |
18971 | ||
18972 | case T_V2SI: | |
18973 | case T_V4SI: | |
18974 | eltype = const_intSI_pointer_node; | |
18975 | break; | |
18976 | ||
18977 | case T_V2SF: | |
18978 | case T_V4SF: | |
18979 | eltype = const_float_pointer_node; | |
18980 | break; | |
18981 | ||
18982 | case T_DI: | |
18983 | case T_V2DI: | |
18984 | eltype = const_intDI_pointer_node; | |
18985 | break; | |
18986 | ||
18987 | default: gcc_unreachable (); | |
18988 | } | |
18989 | } | |
18990 | else if (is_store && k == 0) | |
18991 | { | |
18992 | /* Similarly, Neon store patterns use operand 0 as | |
18993 | the memory location to store to (a SImode pointer). | |
18994 | Use a pointer to the element type of the store in | |
18995 | that position. */ | |
18996 | gcc_assert (insn_data[icode].operand[k].mode == SImode); | |
18997 | ||
18998 | switch (1 << j) | |
18999 | { | |
19000 | case T_V8QI: | |
19001 | case T_V16QI: | |
19002 | eltype = intQI_pointer_node; | |
19003 | break; | |
19004 | ||
19005 | case T_V4HI: | |
19006 | case T_V8HI: | |
19007 | eltype = intHI_pointer_node; | |
19008 | break; | |
19009 | ||
19010 | case T_V2SI: | |
19011 | case T_V4SI: | |
19012 | eltype = intSI_pointer_node; | |
19013 | break; | |
19014 | ||
19015 | case T_V2SF: | |
19016 | case T_V4SF: | |
19017 | eltype = float_pointer_node; | |
19018 | break; | |
19019 | ||
19020 | case T_DI: | |
19021 | case T_V2DI: | |
19022 | eltype = intDI_pointer_node; | |
19023 | break; | |
19024 | ||
19025 | default: gcc_unreachable (); | |
19026 | } | |
19027 | } | |
19028 | else | |
19029 | { | |
19030 | switch (insn_data[icode].operand[k].mode) | |
19031 | { | |
19032 | case VOIDmode: eltype = void_type_node; break; | |
19033 | /* Scalars. */ | |
19034 | case QImode: eltype = neon_intQI_type_node; break; | |
19035 | case HImode: eltype = neon_intHI_type_node; break; | |
19036 | case SImode: eltype = neon_intSI_type_node; break; | |
19037 | case SFmode: eltype = neon_float_type_node; break; | |
19038 | case DImode: eltype = neon_intDI_type_node; break; | |
19039 | case TImode: eltype = intTI_type_node; break; | |
19040 | case EImode: eltype = intEI_type_node; break; | |
19041 | case OImode: eltype = intOI_type_node; break; | |
19042 | case CImode: eltype = intCI_type_node; break; | |
19043 | case XImode: eltype = intXI_type_node; break; | |
19044 | /* 64-bit vectors. */ | |
19045 | case V8QImode: eltype = V8QI_type_node; break; | |
19046 | case V4HImode: eltype = V4HI_type_node; break; | |
19047 | case V2SImode: eltype = V2SI_type_node; break; | |
19048 | case V2SFmode: eltype = V2SF_type_node; break; | |
19049 | /* 128-bit vectors. */ | |
19050 | case V16QImode: eltype = V16QI_type_node; break; | |
19051 | case V8HImode: eltype = V8HI_type_node; break; | |
19052 | case V4SImode: eltype = V4SI_type_node; break; | |
19053 | case V4SFmode: eltype = V4SF_type_node; break; | |
19054 | case V2DImode: eltype = V2DI_type_node; break; | |
19055 | default: gcc_unreachable (); | |
19056 | } | |
19057 | } | |
19058 | ||
19059 | if (k == 0 && !is_store) | |
19060 | return_type = eltype; | |
19061 | else | |
19062 | args = tree_cons (NULL_TREE, eltype, args); | |
19063 | } | |
19064 | ||
19065 | ftype = build_function_type (return_type, args); | |
19066 | } | |
19067 | break; | |
19068 | ||
19069 | case NEON_RESULTPAIR: | |
19070 | { | |
19071 | switch (insn_data[icode].operand[1].mode) | |
19072 | { | |
19073 | case V8QImode: ftype = void_ftype_pv8qi_v8qi_v8qi; break; | |
19074 | case V4HImode: ftype = void_ftype_pv4hi_v4hi_v4hi; break; | |
19075 | case V2SImode: ftype = void_ftype_pv2si_v2si_v2si; break; | |
19076 | case V2SFmode: ftype = void_ftype_pv2sf_v2sf_v2sf; break; | |
19077 | case DImode: ftype = void_ftype_pdi_di_di; break; | |
19078 | case V16QImode: ftype = void_ftype_pv16qi_v16qi_v16qi; break; | |
19079 | case V8HImode: ftype = void_ftype_pv8hi_v8hi_v8hi; break; | |
19080 | case V4SImode: ftype = void_ftype_pv4si_v4si_v4si; break; | |
19081 | case V4SFmode: ftype = void_ftype_pv4sf_v4sf_v4sf; break; | |
19082 | case V2DImode: ftype = void_ftype_pv2di_v2di_v2di; break; | |
19083 | default: gcc_unreachable (); | |
19084 | } | |
19085 | } | |
19086 | break; | |
19087 | ||
19088 | case NEON_REINTERP: | |
19089 | { | |
19090 | /* We iterate over 5 doubleword types, then 5 quadword | |
19091 | types. */ | |
19092 | int rhs = j % 5; | |
19093 | switch (insn_data[icode].operand[0].mode) | |
19094 | { | |
19095 | case V8QImode: ftype = reinterp_ftype_dreg[0][rhs]; break; | |
19096 | case V4HImode: ftype = reinterp_ftype_dreg[1][rhs]; break; | |
19097 | case V2SImode: ftype = reinterp_ftype_dreg[2][rhs]; break; | |
19098 | case V2SFmode: ftype = reinterp_ftype_dreg[3][rhs]; break; | |
19099 | case DImode: ftype = reinterp_ftype_dreg[4][rhs]; break; | |
19100 | case V16QImode: ftype = reinterp_ftype_qreg[0][rhs]; break; | |
19101 | case V8HImode: ftype = reinterp_ftype_qreg[1][rhs]; break; | |
19102 | case V4SImode: ftype = reinterp_ftype_qreg[2][rhs]; break; | |
19103 | case V4SFmode: ftype = reinterp_ftype_qreg[3][rhs]; break; | |
19104 | case V2DImode: ftype = reinterp_ftype_qreg[4][rhs]; break; | |
19105 | default: gcc_unreachable (); | |
19106 | } | |
19107 | } | |
19108 | break; | |
19109 | ||
19110 | default: | |
19111 | gcc_unreachable (); | |
19112 | } | |
19113 | ||
19114 | gcc_assert (ftype != NULL); | |
19115 | ||
19116 | sprintf (namebuf, "__builtin_neon_%s%s", d->name, modenames[j]); | |
19117 | ||
19118 | add_builtin_function (namebuf, ftype, fcode++, BUILT_IN_MD, NULL, | |
19119 | NULL_TREE); | |
19120 | } | |
19121 | } | |
19122 | } | |
19123 | ||
0fd8c3ad SL |
19124 | static void |
19125 | arm_init_fp16_builtins (void) | |
19126 | { | |
19127 | tree fp16_type = make_node (REAL_TYPE); | |
19128 | TYPE_PRECISION (fp16_type) = 16; | |
19129 | layout_type (fp16_type); | |
19130 | (*lang_hooks.types.register_builtin_type) (fp16_type, "__fp16"); | |
19131 | } | |
19132 | ||
5a9335ef NC |
19133 | static void |
19134 | arm_init_builtins (void) | |
19135 | { | |
d3585b76 DJ |
19136 | arm_init_tls_builtins (); |
19137 | ||
5a9335ef NC |
19138 | if (TARGET_REALLY_IWMMXT) |
19139 | arm_init_iwmmxt_builtins (); | |
88f77cba JB |
19140 | |
19141 | if (TARGET_NEON) | |
19142 | arm_init_neon_builtins (); | |
0fd8c3ad SL |
19143 | |
19144 | if (arm_fp16_format) | |
19145 | arm_init_fp16_builtins (); | |
19146 | } | |
19147 | ||
19148 | /* Implement TARGET_INVALID_PARAMETER_TYPE. */ | |
19149 | ||
19150 | static const char * | |
19151 | arm_invalid_parameter_type (const_tree t) | |
19152 | { | |
19153 | if (SCALAR_FLOAT_TYPE_P (t) && TYPE_PRECISION (t) == 16) | |
19154 | return N_("function parameters cannot have __fp16 type"); | |
19155 | return NULL; | |
19156 | } | |
19157 | ||
19158 | /* Implement TARGET_INVALID_PARAMETER_TYPE. */ | |
19159 | ||
19160 | static const char * | |
19161 | arm_invalid_return_type (const_tree t) | |
19162 | { | |
19163 | if (SCALAR_FLOAT_TYPE_P (t) && TYPE_PRECISION (t) == 16) | |
19164 | return N_("functions cannot return __fp16 type"); | |
19165 | return NULL; | |
19166 | } | |
19167 | ||
19168 | /* Implement TARGET_PROMOTED_TYPE. */ | |
19169 | ||
19170 | static tree | |
19171 | arm_promoted_type (const_tree t) | |
19172 | { | |
19173 | if (SCALAR_FLOAT_TYPE_P (t) && TYPE_PRECISION (t) == 16) | |
19174 | return float_type_node; | |
19175 | return NULL_TREE; | |
19176 | } | |
19177 | ||
19178 | /* Implement TARGET_CONVERT_TO_TYPE. | |
19179 | Specifically, this hook implements the peculiarity of the ARM | |
19180 | half-precision floating-point C semantics that requires conversions between | |
19181 | __fp16 to or from double to do an intermediate conversion to float. */ | |
19182 | ||
19183 | static tree | |
19184 | arm_convert_to_type (tree type, tree expr) | |
19185 | { | |
19186 | tree fromtype = TREE_TYPE (expr); | |
19187 | if (!SCALAR_FLOAT_TYPE_P (fromtype) || !SCALAR_FLOAT_TYPE_P (type)) | |
19188 | return NULL_TREE; | |
19189 | if ((TYPE_PRECISION (fromtype) == 16 && TYPE_PRECISION (type) > 32) | |
19190 | || (TYPE_PRECISION (type) == 16 && TYPE_PRECISION (fromtype) > 32)) | |
19191 | return convert (type, convert (float_type_node, expr)); | |
19192 | return NULL_TREE; | |
5a9335ef NC |
19193 | } |
19194 | ||
bdc4827b SL |
19195 | /* Implement TARGET_SCALAR_MODE_SUPPORTED_P. |
19196 | This simply adds HFmode as a supported mode; even though we don't | |
19197 | implement arithmetic on this type directly, it's supported by | |
19198 | optabs conversions, much the way the double-word arithmetic is | |
19199 | special-cased in the default hook. */ | |
19200 | ||
19201 | static bool | |
19202 | arm_scalar_mode_supported_p (enum machine_mode mode) | |
19203 | { | |
19204 | if (mode == HFmode) | |
19205 | return (arm_fp16_format != ARM_FP16_FORMAT_NONE); | |
19206 | else | |
19207 | return default_scalar_mode_supported_p (mode); | |
19208 | } | |
19209 | ||
5a9335ef NC |
19210 | /* Errors in the source file can cause expand_expr to return const0_rtx |
19211 | where we expect a vector. To avoid crashing, use one of the vector | |
19212 | clear instructions. */ | |
19213 | ||
19214 | static rtx | |
19215 | safe_vector_operand (rtx x, enum machine_mode mode) | |
19216 | { | |
19217 | if (x != const0_rtx) | |
19218 | return x; | |
19219 | x = gen_reg_rtx (mode); | |
19220 | ||
19221 | emit_insn (gen_iwmmxt_clrdi (mode == DImode ? x | |
19222 | : gen_rtx_SUBREG (DImode, x, 0))); | |
19223 | return x; | |
19224 | } | |
19225 | ||
19226 | /* Subroutine of arm_expand_builtin to take care of binop insns. */ | |
19227 | ||
19228 | static rtx | |
19229 | arm_expand_binop_builtin (enum insn_code icode, | |
5039610b | 19230 | tree exp, rtx target) |
5a9335ef NC |
19231 | { |
19232 | rtx pat; | |
5039610b SL |
19233 | tree arg0 = CALL_EXPR_ARG (exp, 0); |
19234 | tree arg1 = CALL_EXPR_ARG (exp, 1); | |
84217346 MD |
19235 | rtx op0 = expand_normal (arg0); |
19236 | rtx op1 = expand_normal (arg1); | |
5a9335ef NC |
19237 | enum machine_mode tmode = insn_data[icode].operand[0].mode; |
19238 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
19239 | enum machine_mode mode1 = insn_data[icode].operand[2].mode; | |
19240 | ||
19241 | if (VECTOR_MODE_P (mode0)) | |
19242 | op0 = safe_vector_operand (op0, mode0); | |
19243 | if (VECTOR_MODE_P (mode1)) | |
19244 | op1 = safe_vector_operand (op1, mode1); | |
19245 | ||
19246 | if (! target | |
19247 | || GET_MODE (target) != tmode | |
19248 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
19249 | target = gen_reg_rtx (tmode); | |
19250 | ||
e6d29d15 | 19251 | gcc_assert (GET_MODE (op0) == mode0 && GET_MODE (op1) == mode1); |
5a9335ef NC |
19252 | |
19253 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
19254 | op0 = copy_to_mode_reg (mode0, op0); | |
19255 | if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) | |
19256 | op1 = copy_to_mode_reg (mode1, op1); | |
19257 | ||
19258 | pat = GEN_FCN (icode) (target, op0, op1); | |
19259 | if (! pat) | |
19260 | return 0; | |
19261 | emit_insn (pat); | |
19262 | return target; | |
19263 | } | |
19264 | ||
19265 | /* Subroutine of arm_expand_builtin to take care of unop insns. */ | |
19266 | ||
19267 | static rtx | |
19268 | arm_expand_unop_builtin (enum insn_code icode, | |
5039610b | 19269 | tree exp, rtx target, int do_load) |
5a9335ef NC |
19270 | { |
19271 | rtx pat; | |
5039610b | 19272 | tree arg0 = CALL_EXPR_ARG (exp, 0); |
84217346 | 19273 | rtx op0 = expand_normal (arg0); |
5a9335ef NC |
19274 | enum machine_mode tmode = insn_data[icode].operand[0].mode; |
19275 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
19276 | ||
19277 | if (! target | |
19278 | || GET_MODE (target) != tmode | |
19279 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
19280 | target = gen_reg_rtx (tmode); | |
19281 | if (do_load) | |
19282 | op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0)); | |
19283 | else | |
19284 | { | |
19285 | if (VECTOR_MODE_P (mode0)) | |
19286 | op0 = safe_vector_operand (op0, mode0); | |
19287 | ||
19288 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
19289 | op0 = copy_to_mode_reg (mode0, op0); | |
19290 | } | |
19291 | ||
19292 | pat = GEN_FCN (icode) (target, op0); | |
19293 | if (! pat) | |
19294 | return 0; | |
19295 | emit_insn (pat); | |
19296 | return target; | |
19297 | } | |
19298 | ||
88f77cba JB |
19299 | static int |
19300 | neon_builtin_compare (const void *a, const void *b) | |
19301 | { | |
5ead67f6 KG |
19302 | const neon_builtin_datum *const key = (const neon_builtin_datum *) a; |
19303 | const neon_builtin_datum *const memb = (const neon_builtin_datum *) b; | |
88f77cba JB |
19304 | unsigned int soughtcode = key->base_fcode; |
19305 | ||
19306 | if (soughtcode >= memb->base_fcode | |
19307 | && soughtcode < memb->base_fcode + memb->num_vars) | |
19308 | return 0; | |
19309 | else if (soughtcode < memb->base_fcode) | |
19310 | return -1; | |
19311 | else | |
19312 | return 1; | |
19313 | } | |
19314 | ||
19315 | static enum insn_code | |
19316 | locate_neon_builtin_icode (int fcode, neon_itype *itype) | |
19317 | { | |
21272a45 JR |
19318 | neon_builtin_datum key |
19319 | = { NULL, (neon_itype) 0, 0, { CODE_FOR_nothing }, 0, 0 }; | |
19320 | neon_builtin_datum *found; | |
88f77cba JB |
19321 | int idx; |
19322 | ||
19323 | key.base_fcode = fcode; | |
5ead67f6 KG |
19324 | found = (neon_builtin_datum *) |
19325 | bsearch (&key, &neon_builtin_data[0], ARRAY_SIZE (neon_builtin_data), | |
88f77cba JB |
19326 | sizeof (neon_builtin_data[0]), neon_builtin_compare); |
19327 | gcc_assert (found); | |
19328 | idx = fcode - (int) found->base_fcode; | |
19329 | gcc_assert (idx >= 0 && idx < T_MAX && idx < (int)found->num_vars); | |
19330 | ||
19331 | if (itype) | |
19332 | *itype = found->itype; | |
19333 | ||
19334 | return found->codes[idx]; | |
19335 | } | |
19336 | ||
19337 | typedef enum { | |
19338 | NEON_ARG_COPY_TO_REG, | |
19339 | NEON_ARG_CONSTANT, | |
19340 | NEON_ARG_STOP | |
19341 | } builtin_arg; | |
19342 | ||
19343 | #define NEON_MAX_BUILTIN_ARGS 5 | |
19344 | ||
19345 | /* Expand a Neon builtin. */ | |
19346 | static rtx | |
19347 | arm_expand_neon_args (rtx target, int icode, int have_retval, | |
19348 | tree exp, ...) | |
19349 | { | |
19350 | va_list ap; | |
19351 | rtx pat; | |
19352 | tree arg[NEON_MAX_BUILTIN_ARGS]; | |
19353 | rtx op[NEON_MAX_BUILTIN_ARGS]; | |
19354 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
19355 | enum machine_mode mode[NEON_MAX_BUILTIN_ARGS]; | |
19356 | int argc = 0; | |
19357 | ||
19358 | if (have_retval | |
19359 | && (!target | |
19360 | || GET_MODE (target) != tmode | |
19361 | || !(*insn_data[icode].operand[0].predicate) (target, tmode))) | |
19362 | target = gen_reg_rtx (tmode); | |
19363 | ||
19364 | va_start (ap, exp); | |
19365 | ||
19366 | for (;;) | |
19367 | { | |
81f40b79 | 19368 | builtin_arg thisarg = (builtin_arg) va_arg (ap, int); |
88f77cba JB |
19369 | |
19370 | if (thisarg == NEON_ARG_STOP) | |
19371 | break; | |
19372 | else | |
19373 | { | |
19374 | arg[argc] = CALL_EXPR_ARG (exp, argc); | |
19375 | op[argc] = expand_normal (arg[argc]); | |
19376 | mode[argc] = insn_data[icode].operand[argc + have_retval].mode; | |
19377 | ||
19378 | switch (thisarg) | |
19379 | { | |
19380 | case NEON_ARG_COPY_TO_REG: | |
19381 | /*gcc_assert (GET_MODE (op[argc]) == mode[argc]);*/ | |
19382 | if (!(*insn_data[icode].operand[argc + have_retval].predicate) | |
19383 | (op[argc], mode[argc])) | |
19384 | op[argc] = copy_to_mode_reg (mode[argc], op[argc]); | |
19385 | break; | |
19386 | ||
19387 | case NEON_ARG_CONSTANT: | |
19388 | /* FIXME: This error message is somewhat unhelpful. */ | |
19389 | if (!(*insn_data[icode].operand[argc + have_retval].predicate) | |
19390 | (op[argc], mode[argc])) | |
19391 | error ("argument must be a constant"); | |
19392 | break; | |
19393 | ||
19394 | case NEON_ARG_STOP: | |
19395 | gcc_unreachable (); | |
19396 | } | |
19397 | ||
19398 | argc++; | |
19399 | } | |
19400 | } | |
19401 | ||
19402 | va_end (ap); | |
19403 | ||
19404 | if (have_retval) | |
19405 | switch (argc) | |
19406 | { | |
19407 | case 1: | |
19408 | pat = GEN_FCN (icode) (target, op[0]); | |
19409 | break; | |
19410 | ||
19411 | case 2: | |
19412 | pat = GEN_FCN (icode) (target, op[0], op[1]); | |
19413 | break; | |
19414 | ||
19415 | case 3: | |
19416 | pat = GEN_FCN (icode) (target, op[0], op[1], op[2]); | |
19417 | break; | |
19418 | ||
19419 | case 4: | |
19420 | pat = GEN_FCN (icode) (target, op[0], op[1], op[2], op[3]); | |
19421 | break; | |
19422 | ||
19423 | case 5: | |
19424 | pat = GEN_FCN (icode) (target, op[0], op[1], op[2], op[3], op[4]); | |
19425 | break; | |
19426 | ||
19427 | default: | |
19428 | gcc_unreachable (); | |
19429 | } | |
19430 | else | |
19431 | switch (argc) | |
19432 | { | |
19433 | case 1: | |
19434 | pat = GEN_FCN (icode) (op[0]); | |
19435 | break; | |
19436 | ||
19437 | case 2: | |
19438 | pat = GEN_FCN (icode) (op[0], op[1]); | |
19439 | break; | |
19440 | ||
19441 | case 3: | |
19442 | pat = GEN_FCN (icode) (op[0], op[1], op[2]); | |
19443 | break; | |
19444 | ||
19445 | case 4: | |
19446 | pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3]); | |
19447 | break; | |
19448 | ||
19449 | case 5: | |
19450 | pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3], op[4]); | |
19451 | break; | |
19452 | ||
19453 | default: | |
19454 | gcc_unreachable (); | |
19455 | } | |
19456 | ||
19457 | if (!pat) | |
19458 | return 0; | |
19459 | ||
19460 | emit_insn (pat); | |
19461 | ||
19462 | return target; | |
19463 | } | |
19464 | ||
19465 | /* Expand a Neon builtin. These are "special" because they don't have symbolic | |
19466 | constants defined per-instruction or per instruction-variant. Instead, the | |
19467 | required info is looked up in the table neon_builtin_data. */ | |
19468 | static rtx | |
19469 | arm_expand_neon_builtin (int fcode, tree exp, rtx target) | |
19470 | { | |
19471 | neon_itype itype; | |
19472 | enum insn_code icode = locate_neon_builtin_icode (fcode, &itype); | |
19473 | ||
19474 | switch (itype) | |
19475 | { | |
19476 | case NEON_UNOP: | |
19477 | case NEON_CONVERT: | |
19478 | case NEON_DUPLANE: | |
19479 | return arm_expand_neon_args (target, icode, 1, exp, | |
19480 | NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, NEON_ARG_STOP); | |
19481 | ||
19482 | case NEON_BINOP: | |
19483 | case NEON_SETLANE: | |
19484 | case NEON_SCALARMUL: | |
19485 | case NEON_SCALARMULL: | |
19486 | case NEON_SCALARMULH: | |
19487 | case NEON_SHIFTINSERT: | |
19488 | case NEON_LOGICBINOP: | |
19489 | return arm_expand_neon_args (target, icode, 1, exp, | |
19490 | NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, | |
19491 | NEON_ARG_STOP); | |
19492 | ||
19493 | case NEON_TERNOP: | |
19494 | return arm_expand_neon_args (target, icode, 1, exp, | |
19495 | NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, | |
19496 | NEON_ARG_CONSTANT, NEON_ARG_STOP); | |
19497 | ||
19498 | case NEON_GETLANE: | |
19499 | case NEON_FIXCONV: | |
19500 | case NEON_SHIFTIMM: | |
19501 | return arm_expand_neon_args (target, icode, 1, exp, | |
19502 | NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, NEON_ARG_CONSTANT, | |
19503 | NEON_ARG_STOP); | |
19504 | ||
19505 | case NEON_CREATE: | |
19506 | return arm_expand_neon_args (target, icode, 1, exp, | |
19507 | NEON_ARG_COPY_TO_REG, NEON_ARG_STOP); | |
19508 | ||
19509 | case NEON_DUP: | |
19510 | case NEON_SPLIT: | |
19511 | case NEON_REINTERP: | |
19512 | return arm_expand_neon_args (target, icode, 1, exp, | |
19513 | NEON_ARG_COPY_TO_REG, NEON_ARG_STOP); | |
19514 | ||
19515 | case NEON_COMBINE: | |
19516 | case NEON_VTBL: | |
19517 | return arm_expand_neon_args (target, icode, 1, exp, | |
19518 | NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_STOP); | |
19519 | ||
19520 | case NEON_RESULTPAIR: | |
19521 | return arm_expand_neon_args (target, icode, 0, exp, | |
19522 | NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, | |
19523 | NEON_ARG_STOP); | |
19524 | ||
19525 | case NEON_LANEMUL: | |
19526 | case NEON_LANEMULL: | |
19527 | case NEON_LANEMULH: | |
19528 | return arm_expand_neon_args (target, icode, 1, exp, | |
19529 | NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, | |
19530 | NEON_ARG_CONSTANT, NEON_ARG_STOP); | |
19531 | ||
19532 | case NEON_LANEMAC: | |
19533 | return arm_expand_neon_args (target, icode, 1, exp, | |
19534 | NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, | |
19535 | NEON_ARG_CONSTANT, NEON_ARG_CONSTANT, NEON_ARG_STOP); | |
19536 | ||
19537 | case NEON_SHIFTACC: | |
19538 | return arm_expand_neon_args (target, icode, 1, exp, | |
19539 | NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, | |
19540 | NEON_ARG_CONSTANT, NEON_ARG_STOP); | |
19541 | ||
19542 | case NEON_SCALARMAC: | |
19543 | return arm_expand_neon_args (target, icode, 1, exp, | |
19544 | NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, | |
19545 | NEON_ARG_CONSTANT, NEON_ARG_STOP); | |
19546 | ||
19547 | case NEON_SELECT: | |
19548 | case NEON_VTBX: | |
19549 | return arm_expand_neon_args (target, icode, 1, exp, | |
19550 | NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, | |
19551 | NEON_ARG_STOP); | |
19552 | ||
19553 | case NEON_LOAD1: | |
19554 | case NEON_LOADSTRUCT: | |
19555 | return arm_expand_neon_args (target, icode, 1, exp, | |
19556 | NEON_ARG_COPY_TO_REG, NEON_ARG_STOP); | |
19557 | ||
19558 | case NEON_LOAD1LANE: | |
19559 | case NEON_LOADSTRUCTLANE: | |
19560 | return arm_expand_neon_args (target, icode, 1, exp, | |
19561 | NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, | |
19562 | NEON_ARG_STOP); | |
19563 | ||
19564 | case NEON_STORE1: | |
19565 | case NEON_STORESTRUCT: | |
19566 | return arm_expand_neon_args (target, icode, 0, exp, | |
19567 | NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_STOP); | |
19568 | ||
19569 | case NEON_STORE1LANE: | |
19570 | case NEON_STORESTRUCTLANE: | |
19571 | return arm_expand_neon_args (target, icode, 0, exp, | |
19572 | NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, | |
19573 | NEON_ARG_STOP); | |
19574 | } | |
19575 | ||
19576 | gcc_unreachable (); | |
19577 | } | |
19578 | ||
19579 | /* Emit code to reinterpret one Neon type as another, without altering bits. */ | |
19580 | void | |
19581 | neon_reinterpret (rtx dest, rtx src) | |
19582 | { | |
19583 | emit_move_insn (dest, gen_lowpart (GET_MODE (dest), src)); | |
19584 | } | |
19585 | ||
19586 | /* Emit code to place a Neon pair result in memory locations (with equal | |
19587 | registers). */ | |
19588 | void | |
19589 | neon_emit_pair_result_insn (enum machine_mode mode, | |
19590 | rtx (*intfn) (rtx, rtx, rtx, rtx), rtx destaddr, | |
19591 | rtx op1, rtx op2) | |
19592 | { | |
19593 | rtx mem = gen_rtx_MEM (mode, destaddr); | |
19594 | rtx tmp1 = gen_reg_rtx (mode); | |
19595 | rtx tmp2 = gen_reg_rtx (mode); | |
19596 | ||
19597 | emit_insn (intfn (tmp1, op1, tmp2, op2)); | |
19598 | ||
19599 | emit_move_insn (mem, tmp1); | |
19600 | mem = adjust_address (mem, mode, GET_MODE_SIZE (mode)); | |
19601 | emit_move_insn (mem, tmp2); | |
19602 | } | |
19603 | ||
19604 | /* Set up operands for a register copy from src to dest, taking care not to | |
19605 | clobber registers in the process. | |
19606 | FIXME: This has rather high polynomial complexity (O(n^3)?) but shouldn't | |
19607 | be called with a large N, so that should be OK. */ | |
19608 | ||
19609 | void | |
19610 | neon_disambiguate_copy (rtx *operands, rtx *dest, rtx *src, unsigned int count) | |
19611 | { | |
19612 | unsigned int copied = 0, opctr = 0; | |
19613 | unsigned int done = (1 << count) - 1; | |
19614 | unsigned int i, j; | |
19615 | ||
19616 | while (copied != done) | |
19617 | { | |
19618 | for (i = 0; i < count; i++) | |
19619 | { | |
19620 | int good = 1; | |
19621 | ||
19622 | for (j = 0; good && j < count; j++) | |
19623 | if (i != j && (copied & (1 << j)) == 0 | |
19624 | && reg_overlap_mentioned_p (src[j], dest[i])) | |
19625 | good = 0; | |
19626 | ||
19627 | if (good) | |
19628 | { | |
19629 | operands[opctr++] = dest[i]; | |
19630 | operands[opctr++] = src[i]; | |
19631 | copied |= 1 << i; | |
19632 | } | |
19633 | } | |
19634 | } | |
19635 | ||
19636 | gcc_assert (opctr == count * 2); | |
19637 | } | |
19638 | ||
5a9335ef NC |
19639 | /* Expand an expression EXP that calls a built-in function, |
19640 | with result going to TARGET if that's convenient | |
19641 | (and in mode MODE if that's convenient). | |
19642 | SUBTARGET may be used as the target for computing one of EXP's operands. | |
19643 | IGNORE is nonzero if the value is to be ignored. */ | |
19644 | ||
19645 | static rtx | |
19646 | arm_expand_builtin (tree exp, | |
19647 | rtx target, | |
19648 | rtx subtarget ATTRIBUTE_UNUSED, | |
19649 | enum machine_mode mode ATTRIBUTE_UNUSED, | |
19650 | int ignore ATTRIBUTE_UNUSED) | |
19651 | { | |
19652 | const struct builtin_description * d; | |
19653 | enum insn_code icode; | |
5039610b | 19654 | tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); |
5a9335ef NC |
19655 | tree arg0; |
19656 | tree arg1; | |
19657 | tree arg2; | |
19658 | rtx op0; | |
19659 | rtx op1; | |
19660 | rtx op2; | |
19661 | rtx pat; | |
19662 | int fcode = DECL_FUNCTION_CODE (fndecl); | |
19663 | size_t i; | |
19664 | enum machine_mode tmode; | |
19665 | enum machine_mode mode0; | |
19666 | enum machine_mode mode1; | |
19667 | enum machine_mode mode2; | |
19668 | ||
88f77cba JB |
19669 | if (fcode >= ARM_BUILTIN_NEON_BASE) |
19670 | return arm_expand_neon_builtin (fcode, exp, target); | |
19671 | ||
5a9335ef NC |
19672 | switch (fcode) |
19673 | { | |
19674 | case ARM_BUILTIN_TEXTRMSB: | |
19675 | case ARM_BUILTIN_TEXTRMUB: | |
19676 | case ARM_BUILTIN_TEXTRMSH: | |
19677 | case ARM_BUILTIN_TEXTRMUH: | |
19678 | case ARM_BUILTIN_TEXTRMSW: | |
19679 | case ARM_BUILTIN_TEXTRMUW: | |
19680 | icode = (fcode == ARM_BUILTIN_TEXTRMSB ? CODE_FOR_iwmmxt_textrmsb | |
19681 | : fcode == ARM_BUILTIN_TEXTRMUB ? CODE_FOR_iwmmxt_textrmub | |
19682 | : fcode == ARM_BUILTIN_TEXTRMSH ? CODE_FOR_iwmmxt_textrmsh | |
19683 | : fcode == ARM_BUILTIN_TEXTRMUH ? CODE_FOR_iwmmxt_textrmuh | |
19684 | : CODE_FOR_iwmmxt_textrmw); | |
19685 | ||
5039610b SL |
19686 | arg0 = CALL_EXPR_ARG (exp, 0); |
19687 | arg1 = CALL_EXPR_ARG (exp, 1); | |
84217346 MD |
19688 | op0 = expand_normal (arg0); |
19689 | op1 = expand_normal (arg1); | |
5a9335ef NC |
19690 | tmode = insn_data[icode].operand[0].mode; |
19691 | mode0 = insn_data[icode].operand[1].mode; | |
19692 | mode1 = insn_data[icode].operand[2].mode; | |
19693 | ||
19694 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
19695 | op0 = copy_to_mode_reg (mode0, op0); | |
19696 | if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) | |
19697 | { | |
19698 | /* @@@ better error message */ | |
19699 | error ("selector must be an immediate"); | |
19700 | return gen_reg_rtx (tmode); | |
19701 | } | |
19702 | if (target == 0 | |
19703 | || GET_MODE (target) != tmode | |
19704 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
19705 | target = gen_reg_rtx (tmode); | |
19706 | pat = GEN_FCN (icode) (target, op0, op1); | |
19707 | if (! pat) | |
19708 | return 0; | |
19709 | emit_insn (pat); | |
19710 | return target; | |
19711 | ||
19712 | case ARM_BUILTIN_TINSRB: | |
19713 | case ARM_BUILTIN_TINSRH: | |
19714 | case ARM_BUILTIN_TINSRW: | |
19715 | icode = (fcode == ARM_BUILTIN_TINSRB ? CODE_FOR_iwmmxt_tinsrb | |
19716 | : fcode == ARM_BUILTIN_TINSRH ? CODE_FOR_iwmmxt_tinsrh | |
19717 | : CODE_FOR_iwmmxt_tinsrw); | |
5039610b SL |
19718 | arg0 = CALL_EXPR_ARG (exp, 0); |
19719 | arg1 = CALL_EXPR_ARG (exp, 1); | |
19720 | arg2 = CALL_EXPR_ARG (exp, 2); | |
84217346 MD |
19721 | op0 = expand_normal (arg0); |
19722 | op1 = expand_normal (arg1); | |
19723 | op2 = expand_normal (arg2); | |
5a9335ef NC |
19724 | tmode = insn_data[icode].operand[0].mode; |
19725 | mode0 = insn_data[icode].operand[1].mode; | |
19726 | mode1 = insn_data[icode].operand[2].mode; | |
19727 | mode2 = insn_data[icode].operand[3].mode; | |
19728 | ||
19729 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
19730 | op0 = copy_to_mode_reg (mode0, op0); | |
19731 | if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) | |
19732 | op1 = copy_to_mode_reg (mode1, op1); | |
19733 | if (! (*insn_data[icode].operand[3].predicate) (op2, mode2)) | |
19734 | { | |
19735 | /* @@@ better error message */ | |
19736 | error ("selector must be an immediate"); | |
19737 | return const0_rtx; | |
19738 | } | |
19739 | if (target == 0 | |
19740 | || GET_MODE (target) != tmode | |
19741 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
19742 | target = gen_reg_rtx (tmode); | |
19743 | pat = GEN_FCN (icode) (target, op0, op1, op2); | |
19744 | if (! pat) | |
19745 | return 0; | |
19746 | emit_insn (pat); | |
19747 | return target; | |
19748 | ||
19749 | case ARM_BUILTIN_SETWCX: | |
5039610b SL |
19750 | arg0 = CALL_EXPR_ARG (exp, 0); |
19751 | arg1 = CALL_EXPR_ARG (exp, 1); | |
84217346 MD |
19752 | op0 = force_reg (SImode, expand_normal (arg0)); |
19753 | op1 = expand_normal (arg1); | |
f07a6b21 | 19754 | emit_insn (gen_iwmmxt_tmcr (op1, op0)); |
5a9335ef NC |
19755 | return 0; |
19756 | ||
19757 | case ARM_BUILTIN_GETWCX: | |
5039610b | 19758 | arg0 = CALL_EXPR_ARG (exp, 0); |
84217346 | 19759 | op0 = expand_normal (arg0); |
5a9335ef NC |
19760 | target = gen_reg_rtx (SImode); |
19761 | emit_insn (gen_iwmmxt_tmrc (target, op0)); | |
19762 | return target; | |
19763 | ||
19764 | case ARM_BUILTIN_WSHUFH: | |
19765 | icode = CODE_FOR_iwmmxt_wshufh; | |
5039610b SL |
19766 | arg0 = CALL_EXPR_ARG (exp, 0); |
19767 | arg1 = CALL_EXPR_ARG (exp, 1); | |
84217346 MD |
19768 | op0 = expand_normal (arg0); |
19769 | op1 = expand_normal (arg1); | |
5a9335ef NC |
19770 | tmode = insn_data[icode].operand[0].mode; |
19771 | mode1 = insn_data[icode].operand[1].mode; | |
19772 | mode2 = insn_data[icode].operand[2].mode; | |
19773 | ||
19774 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode1)) | |
19775 | op0 = copy_to_mode_reg (mode1, op0); | |
19776 | if (! (*insn_data[icode].operand[2].predicate) (op1, mode2)) | |
19777 | { | |
19778 | /* @@@ better error message */ | |
19779 | error ("mask must be an immediate"); | |
19780 | return const0_rtx; | |
19781 | } | |
19782 | if (target == 0 | |
19783 | || GET_MODE (target) != tmode | |
19784 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
19785 | target = gen_reg_rtx (tmode); | |
19786 | pat = GEN_FCN (icode) (target, op0, op1); | |
19787 | if (! pat) | |
19788 | return 0; | |
19789 | emit_insn (pat); | |
19790 | return target; | |
19791 | ||
19792 | case ARM_BUILTIN_WSADB: | |
5039610b | 19793 | return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadb, exp, target); |
5a9335ef | 19794 | case ARM_BUILTIN_WSADH: |
5039610b | 19795 | return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadh, exp, target); |
5a9335ef | 19796 | case ARM_BUILTIN_WSADBZ: |
5039610b | 19797 | return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadbz, exp, target); |
5a9335ef | 19798 | case ARM_BUILTIN_WSADHZ: |
5039610b | 19799 | return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadhz, exp, target); |
5a9335ef NC |
19800 | |
19801 | /* Several three-argument builtins. */ | |
19802 | case ARM_BUILTIN_WMACS: | |
19803 | case ARM_BUILTIN_WMACU: | |
19804 | case ARM_BUILTIN_WALIGN: | |
19805 | case ARM_BUILTIN_TMIA: | |
19806 | case ARM_BUILTIN_TMIAPH: | |
19807 | case ARM_BUILTIN_TMIATT: | |
19808 | case ARM_BUILTIN_TMIATB: | |
19809 | case ARM_BUILTIN_TMIABT: | |
19810 | case ARM_BUILTIN_TMIABB: | |
19811 | icode = (fcode == ARM_BUILTIN_WMACS ? CODE_FOR_iwmmxt_wmacs | |
19812 | : fcode == ARM_BUILTIN_WMACU ? CODE_FOR_iwmmxt_wmacu | |
19813 | : fcode == ARM_BUILTIN_TMIA ? CODE_FOR_iwmmxt_tmia | |
19814 | : fcode == ARM_BUILTIN_TMIAPH ? CODE_FOR_iwmmxt_tmiaph | |
19815 | : fcode == ARM_BUILTIN_TMIABB ? CODE_FOR_iwmmxt_tmiabb | |
19816 | : fcode == ARM_BUILTIN_TMIABT ? CODE_FOR_iwmmxt_tmiabt | |
19817 | : fcode == ARM_BUILTIN_TMIATB ? CODE_FOR_iwmmxt_tmiatb | |
19818 | : fcode == ARM_BUILTIN_TMIATT ? CODE_FOR_iwmmxt_tmiatt | |
19819 | : CODE_FOR_iwmmxt_walign); | |
5039610b SL |
19820 | arg0 = CALL_EXPR_ARG (exp, 0); |
19821 | arg1 = CALL_EXPR_ARG (exp, 1); | |
19822 | arg2 = CALL_EXPR_ARG (exp, 2); | |
84217346 MD |
19823 | op0 = expand_normal (arg0); |
19824 | op1 = expand_normal (arg1); | |
19825 | op2 = expand_normal (arg2); | |
5a9335ef NC |
19826 | tmode = insn_data[icode].operand[0].mode; |
19827 | mode0 = insn_data[icode].operand[1].mode; | |
19828 | mode1 = insn_data[icode].operand[2].mode; | |
19829 | mode2 = insn_data[icode].operand[3].mode; | |
19830 | ||
19831 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
19832 | op0 = copy_to_mode_reg (mode0, op0); | |
19833 | if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) | |
19834 | op1 = copy_to_mode_reg (mode1, op1); | |
19835 | if (! (*insn_data[icode].operand[3].predicate) (op2, mode2)) | |
19836 | op2 = copy_to_mode_reg (mode2, op2); | |
19837 | if (target == 0 | |
19838 | || GET_MODE (target) != tmode | |
19839 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
19840 | target = gen_reg_rtx (tmode); | |
19841 | pat = GEN_FCN (icode) (target, op0, op1, op2); | |
19842 | if (! pat) | |
19843 | return 0; | |
19844 | emit_insn (pat); | |
19845 | return target; | |
f676971a | 19846 | |
5a9335ef NC |
19847 | case ARM_BUILTIN_WZERO: |
19848 | target = gen_reg_rtx (DImode); | |
19849 | emit_insn (gen_iwmmxt_clrdi (target)); | |
19850 | return target; | |
19851 | ||
d3585b76 DJ |
19852 | case ARM_BUILTIN_THREAD_POINTER: |
19853 | return arm_load_tp (target); | |
19854 | ||
5a9335ef NC |
19855 | default: |
19856 | break; | |
19857 | } | |
19858 | ||
e97a46ce | 19859 | for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++) |
5a9335ef | 19860 | if (d->code == (const enum arm_builtins) fcode) |
5039610b | 19861 | return arm_expand_binop_builtin (d->icode, exp, target); |
5a9335ef | 19862 | |
e97a46ce | 19863 | for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++) |
5a9335ef | 19864 | if (d->code == (const enum arm_builtins) fcode) |
5039610b | 19865 | return arm_expand_unop_builtin (d->icode, exp, target, 0); |
5a9335ef NC |
19866 | |
19867 | /* @@@ Should really do something sensible here. */ | |
19868 | return NULL_RTX; | |
19869 | } | |
19870 | \f | |
1d6e90ac NC |
19871 | /* Return the number (counting from 0) of |
19872 | the least significant set bit in MASK. */ | |
19873 | ||
e32bac5b | 19874 | inline static int |
b279b20a | 19875 | number_of_first_bit_set (unsigned mask) |
d5b7b3ae RE |
19876 | { |
19877 | int bit; | |
19878 | ||
19879 | for (bit = 0; | |
19880 | (mask & (1 << bit)) == 0; | |
5895f793 | 19881 | ++bit) |
d5b7b3ae RE |
19882 | continue; |
19883 | ||
19884 | return bit; | |
19885 | } | |
19886 | ||
b279b20a NC |
19887 | /* Emit code to push or pop registers to or from the stack. F is the |
19888 | assembly file. MASK is the registers to push or pop. PUSH is | |
19889 | nonzero if we should push, and zero if we should pop. For debugging | |
19890 | output, if pushing, adjust CFA_OFFSET by the amount of space added | |
19891 | to the stack. REAL_REGS should have the same number of bits set as | |
19892 | MASK, and will be used instead (in the same order) to describe which | |
19893 | registers were saved - this is used to mark the save slots when we | |
19894 | push high registers after moving them to low registers. */ | |
19895 | static void | |
19896 | thumb_pushpop (FILE *f, unsigned long mask, int push, int *cfa_offset, | |
19897 | unsigned long real_regs) | |
19898 | { | |
19899 | int regno; | |
19900 | int lo_mask = mask & 0xFF; | |
19901 | int pushed_words = 0; | |
19902 | ||
e6d29d15 | 19903 | gcc_assert (mask); |
b279b20a NC |
19904 | |
19905 | if (lo_mask == 0 && !push && (mask & (1 << PC_REGNUM))) | |
19906 | { | |
19907 | /* Special case. Do not generate a POP PC statement here, do it in | |
19908 | thumb_exit() */ | |
19909 | thumb_exit (f, -1); | |
19910 | return; | |
19911 | } | |
19912 | ||
d5fabb58 | 19913 | if (push && arm_except_unwind_info (&global_options) == UI_TARGET) |
617a1b71 PB |
19914 | { |
19915 | fprintf (f, "\t.save\t{"); | |
19916 | for (regno = 0; regno < 15; regno++) | |
19917 | { | |
19918 | if (real_regs & (1 << regno)) | |
19919 | { | |
19920 | if (real_regs & ((1 << regno) -1)) | |
19921 | fprintf (f, ", "); | |
19922 | asm_fprintf (f, "%r", regno); | |
19923 | } | |
19924 | } | |
19925 | fprintf (f, "}\n"); | |
19926 | } | |
19927 | ||
b279b20a NC |
19928 | fprintf (f, "\t%s\t{", push ? "push" : "pop"); |
19929 | ||
19930 | /* Look at the low registers first. */ | |
19931 | for (regno = 0; regno <= LAST_LO_REGNUM; regno++, lo_mask >>= 1) | |
19932 | { | |
19933 | if (lo_mask & 1) | |
19934 | { | |
19935 | asm_fprintf (f, "%r", regno); | |
19936 | ||
19937 | if ((lo_mask & ~1) != 0) | |
19938 | fprintf (f, ", "); | |
19939 | ||
19940 | pushed_words++; | |
19941 | } | |
19942 | } | |
19943 | ||
19944 | if (push && (mask & (1 << LR_REGNUM))) | |
19945 | { | |
19946 | /* Catch pushing the LR. */ | |
19947 | if (mask & 0xFF) | |
19948 | fprintf (f, ", "); | |
19949 | ||
19950 | asm_fprintf (f, "%r", LR_REGNUM); | |
19951 | ||
19952 | pushed_words++; | |
19953 | } | |
19954 | else if (!push && (mask & (1 << PC_REGNUM))) | |
19955 | { | |
19956 | /* Catch popping the PC. */ | |
19957 | if (TARGET_INTERWORK || TARGET_BACKTRACE | |
e3b5732b | 19958 | || crtl->calls_eh_return) |
b279b20a NC |
19959 | { |
19960 | /* The PC is never poped directly, instead | |
19961 | it is popped into r3 and then BX is used. */ | |
19962 | fprintf (f, "}\n"); | |
19963 | ||
19964 | thumb_exit (f, -1); | |
19965 | ||
19966 | return; | |
19967 | } | |
19968 | else | |
19969 | { | |
19970 | if (mask & 0xFF) | |
19971 | fprintf (f, ", "); | |
19972 | ||
19973 | asm_fprintf (f, "%r", PC_REGNUM); | |
19974 | } | |
19975 | } | |
19976 | ||
19977 | fprintf (f, "}\n"); | |
19978 | ||
19979 | if (push && pushed_words && dwarf2out_do_frame ()) | |
19980 | { | |
d342c045 | 19981 | char *l = dwarf2out_cfi_label (false); |
b279b20a NC |
19982 | int pushed_mask = real_regs; |
19983 | ||
19984 | *cfa_offset += pushed_words * 4; | |
19985 | dwarf2out_def_cfa (l, SP_REGNUM, *cfa_offset); | |
19986 | ||
19987 | pushed_words = 0; | |
19988 | pushed_mask = real_regs; | |
19989 | for (regno = 0; regno <= 14; regno++, pushed_mask >>= 1) | |
19990 | { | |
19991 | if (pushed_mask & 1) | |
19992 | dwarf2out_reg_save (l, regno, 4 * pushed_words++ - *cfa_offset); | |
19993 | } | |
19994 | } | |
19995 | } | |
19996 | ||
d5b7b3ae RE |
19997 | /* Generate code to return from a thumb function. |
19998 | If 'reg_containing_return_addr' is -1, then the return address is | |
19999 | actually on the stack, at the stack pointer. */ | |
20000 | static void | |
c9ca9b88 | 20001 | thumb_exit (FILE *f, int reg_containing_return_addr) |
d5b7b3ae RE |
20002 | { |
20003 | unsigned regs_available_for_popping; | |
20004 | unsigned regs_to_pop; | |
20005 | int pops_needed; | |
20006 | unsigned available; | |
20007 | unsigned required; | |
20008 | int mode; | |
20009 | int size; | |
20010 | int restore_a4 = FALSE; | |
20011 | ||
20012 | /* Compute the registers we need to pop. */ | |
20013 | regs_to_pop = 0; | |
20014 | pops_needed = 0; | |
20015 | ||
c9ca9b88 | 20016 | if (reg_containing_return_addr == -1) |
d5b7b3ae | 20017 | { |
d5b7b3ae | 20018 | regs_to_pop |= 1 << LR_REGNUM; |
5895f793 | 20019 | ++pops_needed; |
d5b7b3ae RE |
20020 | } |
20021 | ||
20022 | if (TARGET_BACKTRACE) | |
20023 | { | |
20024 | /* Restore the (ARM) frame pointer and stack pointer. */ | |
20025 | regs_to_pop |= (1 << ARM_HARD_FRAME_POINTER_REGNUM) | (1 << SP_REGNUM); | |
20026 | pops_needed += 2; | |
20027 | } | |
20028 | ||
20029 | /* If there is nothing to pop then just emit the BX instruction and | |
20030 | return. */ | |
20031 | if (pops_needed == 0) | |
20032 | { | |
e3b5732b | 20033 | if (crtl->calls_eh_return) |
c9ca9b88 | 20034 | asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, ARM_EH_STACKADJ_REGNUM); |
d5b7b3ae RE |
20035 | |
20036 | asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr); | |
20037 | return; | |
20038 | } | |
20039 | /* Otherwise if we are not supporting interworking and we have not created | |
20040 | a backtrace structure and the function was not entered in ARM mode then | |
20041 | just pop the return address straight into the PC. */ | |
5895f793 RE |
20042 | else if (!TARGET_INTERWORK |
20043 | && !TARGET_BACKTRACE | |
c9ca9b88 | 20044 | && !is_called_in_ARM_mode (current_function_decl) |
e3b5732b | 20045 | && !crtl->calls_eh_return) |
d5b7b3ae | 20046 | { |
c9ca9b88 | 20047 | asm_fprintf (f, "\tpop\t{%r}\n", PC_REGNUM); |
d5b7b3ae RE |
20048 | return; |
20049 | } | |
20050 | ||
20051 | /* Find out how many of the (return) argument registers we can corrupt. */ | |
20052 | regs_available_for_popping = 0; | |
20053 | ||
20054 | /* If returning via __builtin_eh_return, the bottom three registers | |
20055 | all contain information needed for the return. */ | |
e3b5732b | 20056 | if (crtl->calls_eh_return) |
d5b7b3ae RE |
20057 | size = 12; |
20058 | else | |
20059 | { | |
d5b7b3ae RE |
20060 | /* If we can deduce the registers used from the function's |
20061 | return value. This is more reliable that examining | |
6fb5fa3c | 20062 | df_regs_ever_live_p () because that will be set if the register is |
d5b7b3ae RE |
20063 | ever used in the function, not just if the register is used |
20064 | to hold a return value. */ | |
20065 | ||
38173d38 JH |
20066 | if (crtl->return_rtx != 0) |
20067 | mode = GET_MODE (crtl->return_rtx); | |
d5b7b3ae | 20068 | else |
d5b7b3ae RE |
20069 | mode = DECL_MODE (DECL_RESULT (current_function_decl)); |
20070 | ||
20071 | size = GET_MODE_SIZE (mode); | |
20072 | ||
20073 | if (size == 0) | |
20074 | { | |
20075 | /* In a void function we can use any argument register. | |
20076 | In a function that returns a structure on the stack | |
20077 | we can use the second and third argument registers. */ | |
20078 | if (mode == VOIDmode) | |
20079 | regs_available_for_popping = | |
20080 | (1 << ARG_REGISTER (1)) | |
20081 | | (1 << ARG_REGISTER (2)) | |
20082 | | (1 << ARG_REGISTER (3)); | |
20083 | else | |
20084 | regs_available_for_popping = | |
20085 | (1 << ARG_REGISTER (2)) | |
20086 | | (1 << ARG_REGISTER (3)); | |
20087 | } | |
20088 | else if (size <= 4) | |
20089 | regs_available_for_popping = | |
20090 | (1 << ARG_REGISTER (2)) | |
20091 | | (1 << ARG_REGISTER (3)); | |
20092 | else if (size <= 8) | |
20093 | regs_available_for_popping = | |
20094 | (1 << ARG_REGISTER (3)); | |
20095 | } | |
20096 | ||
20097 | /* Match registers to be popped with registers into which we pop them. */ | |
20098 | for (available = regs_available_for_popping, | |
20099 | required = regs_to_pop; | |
20100 | required != 0 && available != 0; | |
20101 | available &= ~(available & - available), | |
20102 | required &= ~(required & - required)) | |
20103 | -- pops_needed; | |
20104 | ||
20105 | /* If we have any popping registers left over, remove them. */ | |
20106 | if (available > 0) | |
5895f793 | 20107 | regs_available_for_popping &= ~available; |
f676971a | 20108 | |
d5b7b3ae RE |
20109 | /* Otherwise if we need another popping register we can use |
20110 | the fourth argument register. */ | |
20111 | else if (pops_needed) | |
20112 | { | |
20113 | /* If we have not found any free argument registers and | |
20114 | reg a4 contains the return address, we must move it. */ | |
20115 | if (regs_available_for_popping == 0 | |
20116 | && reg_containing_return_addr == LAST_ARG_REGNUM) | |
20117 | { | |
20118 | asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, LAST_ARG_REGNUM); | |
20119 | reg_containing_return_addr = LR_REGNUM; | |
20120 | } | |
20121 | else if (size > 12) | |
20122 | { | |
20123 | /* Register a4 is being used to hold part of the return value, | |
20124 | but we have dire need of a free, low register. */ | |
20125 | restore_a4 = TRUE; | |
f676971a | 20126 | |
d5b7b3ae RE |
20127 | asm_fprintf (f, "\tmov\t%r, %r\n",IP_REGNUM, LAST_ARG_REGNUM); |
20128 | } | |
f676971a | 20129 | |
d5b7b3ae RE |
20130 | if (reg_containing_return_addr != LAST_ARG_REGNUM) |
20131 | { | |
20132 | /* The fourth argument register is available. */ | |
20133 | regs_available_for_popping |= 1 << LAST_ARG_REGNUM; | |
f676971a | 20134 | |
5895f793 | 20135 | --pops_needed; |
d5b7b3ae RE |
20136 | } |
20137 | } | |
20138 | ||
20139 | /* Pop as many registers as we can. */ | |
980e61bb DJ |
20140 | thumb_pushpop (f, regs_available_for_popping, FALSE, NULL, |
20141 | regs_available_for_popping); | |
d5b7b3ae RE |
20142 | |
20143 | /* Process the registers we popped. */ | |
20144 | if (reg_containing_return_addr == -1) | |
20145 | { | |
20146 | /* The return address was popped into the lowest numbered register. */ | |
5895f793 | 20147 | regs_to_pop &= ~(1 << LR_REGNUM); |
f676971a | 20148 | |
d5b7b3ae RE |
20149 | reg_containing_return_addr = |
20150 | number_of_first_bit_set (regs_available_for_popping); | |
20151 | ||
20152 | /* Remove this register for the mask of available registers, so that | |
6bc82793 | 20153 | the return address will not be corrupted by further pops. */ |
5895f793 | 20154 | regs_available_for_popping &= ~(1 << reg_containing_return_addr); |
d5b7b3ae RE |
20155 | } |
20156 | ||
20157 | /* If we popped other registers then handle them here. */ | |
20158 | if (regs_available_for_popping) | |
20159 | { | |
20160 | int frame_pointer; | |
f676971a | 20161 | |
d5b7b3ae RE |
20162 | /* Work out which register currently contains the frame pointer. */ |
20163 | frame_pointer = number_of_first_bit_set (regs_available_for_popping); | |
20164 | ||
20165 | /* Move it into the correct place. */ | |
20166 | asm_fprintf (f, "\tmov\t%r, %r\n", | |
20167 | ARM_HARD_FRAME_POINTER_REGNUM, frame_pointer); | |
20168 | ||
20169 | /* (Temporarily) remove it from the mask of popped registers. */ | |
5895f793 RE |
20170 | regs_available_for_popping &= ~(1 << frame_pointer); |
20171 | regs_to_pop &= ~(1 << ARM_HARD_FRAME_POINTER_REGNUM); | |
f676971a | 20172 | |
d5b7b3ae RE |
20173 | if (regs_available_for_popping) |
20174 | { | |
20175 | int stack_pointer; | |
f676971a | 20176 | |
d5b7b3ae RE |
20177 | /* We popped the stack pointer as well, |
20178 | find the register that contains it. */ | |
20179 | stack_pointer = number_of_first_bit_set (regs_available_for_popping); | |
20180 | ||
20181 | /* Move it into the stack register. */ | |
20182 | asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, stack_pointer); | |
f676971a | 20183 | |
d5b7b3ae RE |
20184 | /* At this point we have popped all necessary registers, so |
20185 | do not worry about restoring regs_available_for_popping | |
20186 | to its correct value: | |
20187 | ||
20188 | assert (pops_needed == 0) | |
20189 | assert (regs_available_for_popping == (1 << frame_pointer)) | |
20190 | assert (regs_to_pop == (1 << STACK_POINTER)) */ | |
20191 | } | |
20192 | else | |
20193 | { | |
20194 | /* Since we have just move the popped value into the frame | |
20195 | pointer, the popping register is available for reuse, and | |
20196 | we know that we still have the stack pointer left to pop. */ | |
20197 | regs_available_for_popping |= (1 << frame_pointer); | |
20198 | } | |
20199 | } | |
f676971a | 20200 | |
d5b7b3ae RE |
20201 | /* If we still have registers left on the stack, but we no longer have |
20202 | any registers into which we can pop them, then we must move the return | |
20203 | address into the link register and make available the register that | |
20204 | contained it. */ | |
20205 | if (regs_available_for_popping == 0 && pops_needed > 0) | |
20206 | { | |
20207 | regs_available_for_popping |= 1 << reg_containing_return_addr; | |
f676971a | 20208 | |
d5b7b3ae RE |
20209 | asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, |
20210 | reg_containing_return_addr); | |
f676971a | 20211 | |
d5b7b3ae RE |
20212 | reg_containing_return_addr = LR_REGNUM; |
20213 | } | |
20214 | ||
20215 | /* If we have registers left on the stack then pop some more. | |
20216 | We know that at most we will want to pop FP and SP. */ | |
20217 | if (pops_needed > 0) | |
20218 | { | |
20219 | int popped_into; | |
20220 | int move_to; | |
f676971a | 20221 | |
980e61bb DJ |
20222 | thumb_pushpop (f, regs_available_for_popping, FALSE, NULL, |
20223 | regs_available_for_popping); | |
d5b7b3ae RE |
20224 | |
20225 | /* We have popped either FP or SP. | |
20226 | Move whichever one it is into the correct register. */ | |
20227 | popped_into = number_of_first_bit_set (regs_available_for_popping); | |
20228 | move_to = number_of_first_bit_set (regs_to_pop); | |
20229 | ||
20230 | asm_fprintf (f, "\tmov\t%r, %r\n", move_to, popped_into); | |
20231 | ||
5895f793 | 20232 | regs_to_pop &= ~(1 << move_to); |
d5b7b3ae | 20233 | |
5895f793 | 20234 | --pops_needed; |
d5b7b3ae | 20235 | } |
f676971a | 20236 | |
d5b7b3ae RE |
20237 | /* If we still have not popped everything then we must have only |
20238 | had one register available to us and we are now popping the SP. */ | |
20239 | if (pops_needed > 0) | |
20240 | { | |
20241 | int popped_into; | |
f676971a | 20242 | |
980e61bb DJ |
20243 | thumb_pushpop (f, regs_available_for_popping, FALSE, NULL, |
20244 | regs_available_for_popping); | |
d5b7b3ae RE |
20245 | |
20246 | popped_into = number_of_first_bit_set (regs_available_for_popping); | |
20247 | ||
20248 | asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, popped_into); | |
20249 | /* | |
20250 | assert (regs_to_pop == (1 << STACK_POINTER)) | |
20251 | assert (pops_needed == 1) | |
20252 | */ | |
20253 | } | |
20254 | ||
20255 | /* If necessary restore the a4 register. */ | |
20256 | if (restore_a4) | |
20257 | { | |
20258 | if (reg_containing_return_addr != LR_REGNUM) | |
20259 | { | |
20260 | asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, LAST_ARG_REGNUM); | |
20261 | reg_containing_return_addr = LR_REGNUM; | |
20262 | } | |
f676971a | 20263 | |
d5b7b3ae RE |
20264 | asm_fprintf (f, "\tmov\t%r, %r\n", LAST_ARG_REGNUM, IP_REGNUM); |
20265 | } | |
20266 | ||
e3b5732b | 20267 | if (crtl->calls_eh_return) |
c9ca9b88 | 20268 | asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, ARM_EH_STACKADJ_REGNUM); |
d5b7b3ae RE |
20269 | |
20270 | /* Return to caller. */ | |
20271 | asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr); | |
20272 | } | |
d5b7b3ae | 20273 | \f |
906668bb BS |
20274 | /* Scan INSN just before assembler is output for it. |
20275 | For Thumb-1, we track the status of the condition codes; this | |
20276 | information is used in the cbranchsi4_insn pattern. */ | |
d5b7b3ae | 20277 | void |
5b3e6663 | 20278 | thumb1_final_prescan_insn (rtx insn) |
d5b7b3ae | 20279 | { |
d5b7b3ae | 20280 | if (flag_print_asm_name) |
9d98a694 AO |
20281 | asm_fprintf (asm_out_file, "%@ 0x%04x\n", |
20282 | INSN_ADDRESSES (INSN_UID (insn))); | |
906668bb BS |
20283 | /* Don't overwrite the previous setter when we get to a cbranch. */ |
20284 | if (INSN_CODE (insn) != CODE_FOR_cbranchsi4_insn) | |
20285 | { | |
20286 | enum attr_conds conds; | |
20287 | ||
20288 | if (cfun->machine->thumb1_cc_insn) | |
20289 | { | |
20290 | if (modified_in_p (cfun->machine->thumb1_cc_op0, insn) | |
20291 | || modified_in_p (cfun->machine->thumb1_cc_op1, insn)) | |
20292 | CC_STATUS_INIT; | |
20293 | } | |
20294 | conds = get_attr_conds (insn); | |
20295 | if (conds == CONDS_SET) | |
20296 | { | |
20297 | rtx set = single_set (insn); | |
20298 | cfun->machine->thumb1_cc_insn = insn; | |
20299 | cfun->machine->thumb1_cc_op0 = SET_DEST (set); | |
20300 | cfun->machine->thumb1_cc_op1 = const0_rtx; | |
20301 | cfun->machine->thumb1_cc_mode = CC_NOOVmode; | |
20302 | if (INSN_CODE (insn) == CODE_FOR_thumb1_subsi3_insn) | |
20303 | { | |
20304 | rtx src1 = XEXP (SET_SRC (set), 1); | |
20305 | if (src1 == const0_rtx) | |
20306 | cfun->machine->thumb1_cc_mode = CCmode; | |
20307 | } | |
20308 | } | |
20309 | else if (conds != CONDS_NOCOND) | |
20310 | cfun->machine->thumb1_cc_insn = NULL_RTX; | |
20311 | } | |
d5b7b3ae RE |
20312 | } |
20313 | ||
20314 | int | |
e32bac5b | 20315 | thumb_shiftable_const (unsigned HOST_WIDE_INT val) |
d5b7b3ae RE |
20316 | { |
20317 | unsigned HOST_WIDE_INT mask = 0xff; | |
20318 | int i; | |
20319 | ||
ce41c38b | 20320 | val = val & (unsigned HOST_WIDE_INT)0xffffffffu; |
d5b7b3ae RE |
20321 | if (val == 0) /* XXX */ |
20322 | return 0; | |
f676971a | 20323 | |
d5b7b3ae RE |
20324 | for (i = 0; i < 25; i++) |
20325 | if ((val & (mask << i)) == val) | |
20326 | return 1; | |
20327 | ||
20328 | return 0; | |
20329 | } | |
20330 | ||
825dda42 | 20331 | /* Returns nonzero if the current function contains, |
d5b7b3ae | 20332 | or might contain a far jump. */ |
5848830f PB |
20333 | static int |
20334 | thumb_far_jump_used_p (void) | |
d5b7b3ae RE |
20335 | { |
20336 | rtx insn; | |
20337 | ||
20338 | /* This test is only important for leaf functions. */ | |
5895f793 | 20339 | /* assert (!leaf_function_p ()); */ |
f676971a | 20340 | |
d5b7b3ae RE |
20341 | /* If we have already decided that far jumps may be used, |
20342 | do not bother checking again, and always return true even if | |
20343 | it turns out that they are not being used. Once we have made | |
20344 | the decision that far jumps are present (and that hence the link | |
20345 | register will be pushed onto the stack) we cannot go back on it. */ | |
20346 | if (cfun->machine->far_jump_used) | |
20347 | return 1; | |
20348 | ||
20349 | /* If this function is not being called from the prologue/epilogue | |
20350 | generation code then it must be being called from the | |
20351 | INITIAL_ELIMINATION_OFFSET macro. */ | |
5848830f | 20352 | if (!(ARM_DOUBLEWORD_ALIGN || reload_completed)) |
d5b7b3ae RE |
20353 | { |
20354 | /* In this case we know that we are being asked about the elimination | |
20355 | of the arg pointer register. If that register is not being used, | |
20356 | then there are no arguments on the stack, and we do not have to | |
20357 | worry that a far jump might force the prologue to push the link | |
20358 | register, changing the stack offsets. In this case we can just | |
20359 | return false, since the presence of far jumps in the function will | |
20360 | not affect stack offsets. | |
20361 | ||
20362 | If the arg pointer is live (or if it was live, but has now been | |
20363 | eliminated and so set to dead) then we do have to test to see if | |
20364 | the function might contain a far jump. This test can lead to some | |
20365 | false negatives, since before reload is completed, then length of | |
20366 | branch instructions is not known, so gcc defaults to returning their | |
20367 | longest length, which in turn sets the far jump attribute to true. | |
20368 | ||
20369 | A false negative will not result in bad code being generated, but it | |
20370 | will result in a needless push and pop of the link register. We | |
5848830f PB |
20371 | hope that this does not occur too often. |
20372 | ||
20373 | If we need doubleword stack alignment this could affect the other | |
20374 | elimination offsets so we can't risk getting it wrong. */ | |
6fb5fa3c | 20375 | if (df_regs_ever_live_p (ARG_POINTER_REGNUM)) |
d5b7b3ae | 20376 | cfun->machine->arg_pointer_live = 1; |
5895f793 | 20377 | else if (!cfun->machine->arg_pointer_live) |
d5b7b3ae RE |
20378 | return 0; |
20379 | } | |
20380 | ||
20381 | /* Check to see if the function contains a branch | |
20382 | insn with the far jump attribute set. */ | |
20383 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) | |
20384 | { | |
20385 | if (GET_CODE (insn) == JUMP_INSN | |
20386 | /* Ignore tablejump patterns. */ | |
20387 | && GET_CODE (PATTERN (insn)) != ADDR_VEC | |
20388 | && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC | |
20389 | && get_attr_far_jump (insn) == FAR_JUMP_YES | |
20390 | ) | |
20391 | { | |
9a9f7594 | 20392 | /* Record the fact that we have decided that |
d5b7b3ae RE |
20393 | the function does use far jumps. */ |
20394 | cfun->machine->far_jump_used = 1; | |
20395 | return 1; | |
20396 | } | |
20397 | } | |
f676971a | 20398 | |
d5b7b3ae RE |
20399 | return 0; |
20400 | } | |
20401 | ||
825dda42 | 20402 | /* Return nonzero if FUNC must be entered in ARM mode. */ |
d5b7b3ae | 20403 | int |
e32bac5b | 20404 | is_called_in_ARM_mode (tree func) |
d5b7b3ae | 20405 | { |
e6d29d15 | 20406 | gcc_assert (TREE_CODE (func) == FUNCTION_DECL); |
d5b7b3ae | 20407 | |
696e78bf | 20408 | /* Ignore the problem about functions whose address is taken. */ |
d5b7b3ae RE |
20409 | if (TARGET_CALLEE_INTERWORKING && TREE_PUBLIC (func)) |
20410 | return TRUE; | |
20411 | ||
f676971a | 20412 | #ifdef ARM_PE |
91d231cb | 20413 | return lookup_attribute ("interfacearm", DECL_ATTRIBUTES (func)) != NULL_TREE; |
d5b7b3ae RE |
20414 | #else |
20415 | return FALSE; | |
20416 | #endif | |
20417 | } | |
20418 | ||
e784c52c BS |
20419 | /* Given the stack offsets and register mask in OFFSETS, decide how |
20420 | many additional registers to push instead of subtracting a constant | |
20421 | from SP. For epilogues the principle is the same except we use pop. | |
20422 | FOR_PROLOGUE indicates which we're generating. */ | |
20423 | static int | |
20424 | thumb1_extra_regs_pushed (arm_stack_offsets *offsets, bool for_prologue) | |
20425 | { | |
20426 | HOST_WIDE_INT amount; | |
20427 | unsigned long live_regs_mask = offsets->saved_regs_mask; | |
20428 | /* Extract a mask of the ones we can give to the Thumb's push/pop | |
20429 | instruction. */ | |
20430 | unsigned long l_mask = live_regs_mask & (for_prologue ? 0x40ff : 0xff); | |
20431 | /* Then count how many other high registers will need to be pushed. */ | |
20432 | unsigned long high_regs_pushed = bit_count (live_regs_mask & 0x0f00); | |
20433 | int n_free, reg_base; | |
20434 | ||
20435 | if (!for_prologue && frame_pointer_needed) | |
20436 | amount = offsets->locals_base - offsets->saved_regs; | |
20437 | else | |
20438 | amount = offsets->outgoing_args - offsets->saved_regs; | |
20439 | ||
20440 | /* If the stack frame size is 512 exactly, we can save one load | |
20441 | instruction, which should make this a win even when optimizing | |
20442 | for speed. */ | |
20443 | if (!optimize_size && amount != 512) | |
20444 | return 0; | |
20445 | ||
20446 | /* Can't do this if there are high registers to push. */ | |
20447 | if (high_regs_pushed != 0) | |
20448 | return 0; | |
20449 | ||
20450 | /* Shouldn't do it in the prologue if no registers would normally | |
20451 | be pushed at all. In the epilogue, also allow it if we'll have | |
20452 | a pop insn for the PC. */ | |
20453 | if (l_mask == 0 | |
20454 | && (for_prologue | |
20455 | || TARGET_BACKTRACE | |
20456 | || (live_regs_mask & 1 << LR_REGNUM) == 0 | |
20457 | || TARGET_INTERWORK | |
20458 | || crtl->args.pretend_args_size != 0)) | |
20459 | return 0; | |
20460 | ||
20461 | /* Don't do this if thumb_expand_prologue wants to emit instructions | |
20462 | between the push and the stack frame allocation. */ | |
20463 | if (for_prologue | |
20464 | && ((flag_pic && arm_pic_register != INVALID_REGNUM) | |
20465 | || (!frame_pointer_needed && CALLER_INTERWORKING_SLOT_SIZE > 0))) | |
20466 | return 0; | |
20467 | ||
20468 | reg_base = 0; | |
20469 | n_free = 0; | |
20470 | if (!for_prologue) | |
20471 | { | |
20472 | reg_base = arm_size_return_regs () / UNITS_PER_WORD; | |
20473 | live_regs_mask >>= reg_base; | |
20474 | } | |
20475 | ||
20476 | while (reg_base + n_free < 8 && !(live_regs_mask & 1) | |
20477 | && (for_prologue || call_used_regs[reg_base + n_free])) | |
20478 | { | |
20479 | live_regs_mask >>= 1; | |
20480 | n_free++; | |
20481 | } | |
20482 | ||
20483 | if (n_free == 0) | |
20484 | return 0; | |
20485 | gcc_assert (amount / 4 * 4 == amount); | |
20486 | ||
20487 | if (amount >= 512 && (amount - n_free * 4) < 512) | |
20488 | return (amount - 508) / 4; | |
20489 | if (amount <= n_free * 4) | |
20490 | return amount / 4; | |
20491 | return 0; | |
20492 | } | |
20493 | ||
d6b4baa4 | 20494 | /* The bits which aren't usefully expanded as rtl. */ |
cd2b33d0 | 20495 | const char * |
e32bac5b | 20496 | thumb_unexpanded_epilogue (void) |
d5b7b3ae | 20497 | { |
954954d1 | 20498 | arm_stack_offsets *offsets; |
d5b7b3ae | 20499 | int regno; |
b279b20a | 20500 | unsigned long live_regs_mask = 0; |
d5b7b3ae | 20501 | int high_regs_pushed = 0; |
e784c52c | 20502 | int extra_pop; |
d5b7b3ae | 20503 | int had_to_push_lr; |
57934c39 | 20504 | int size; |
d5b7b3ae | 20505 | |
934c2060 | 20506 | if (cfun->machine->return_used_this_function != 0) |
d5b7b3ae RE |
20507 | return ""; |
20508 | ||
58e60158 AN |
20509 | if (IS_NAKED (arm_current_func_type ())) |
20510 | return ""; | |
20511 | ||
954954d1 PB |
20512 | offsets = arm_get_frame_offsets (); |
20513 | live_regs_mask = offsets->saved_regs_mask; | |
57934c39 PB |
20514 | high_regs_pushed = bit_count (live_regs_mask & 0x0f00); |
20515 | ||
20516 | /* If we can deduce the registers used from the function's return value. | |
6fb5fa3c | 20517 | This is more reliable that examining df_regs_ever_live_p () because that |
57934c39 PB |
20518 | will be set if the register is ever used in the function, not just if |
20519 | the register is used to hold a return value. */ | |
4f5dfed0 | 20520 | size = arm_size_return_regs (); |
d5b7b3ae | 20521 | |
e784c52c BS |
20522 | extra_pop = thumb1_extra_regs_pushed (offsets, false); |
20523 | if (extra_pop > 0) | |
20524 | { | |
20525 | unsigned long extra_mask = (1 << extra_pop) - 1; | |
20526 | live_regs_mask |= extra_mask << (size / UNITS_PER_WORD); | |
20527 | } | |
20528 | ||
d5b7b3ae | 20529 | /* The prolog may have pushed some high registers to use as |
112cdef5 | 20530 | work registers. e.g. the testsuite file: |
d5b7b3ae RE |
20531 | gcc/testsuite/gcc/gcc.c-torture/execute/complex-2.c |
20532 | compiles to produce: | |
20533 | push {r4, r5, r6, r7, lr} | |
20534 | mov r7, r9 | |
20535 | mov r6, r8 | |
20536 | push {r6, r7} | |
20537 | as part of the prolog. We have to undo that pushing here. */ | |
f676971a | 20538 | |
d5b7b3ae RE |
20539 | if (high_regs_pushed) |
20540 | { | |
b279b20a | 20541 | unsigned long mask = live_regs_mask & 0xff; |
d5b7b3ae | 20542 | int next_hi_reg; |
d5b7b3ae | 20543 | |
57934c39 PB |
20544 | /* The available low registers depend on the size of the value we are |
20545 | returning. */ | |
20546 | if (size <= 12) | |
d5b7b3ae | 20547 | mask |= 1 << 3; |
57934c39 PB |
20548 | if (size <= 8) |
20549 | mask |= 1 << 2; | |
d5b7b3ae RE |
20550 | |
20551 | if (mask == 0) | |
20552 | /* Oh dear! We have no low registers into which we can pop | |
20553 | high registers! */ | |
400500c4 RK |
20554 | internal_error |
20555 | ("no low registers available for popping high registers"); | |
f676971a | 20556 | |
d5b7b3ae | 20557 | for (next_hi_reg = 8; next_hi_reg < 13; next_hi_reg++) |
57934c39 | 20558 | if (live_regs_mask & (1 << next_hi_reg)) |
d5b7b3ae RE |
20559 | break; |
20560 | ||
20561 | while (high_regs_pushed) | |
20562 | { | |
20563 | /* Find lo register(s) into which the high register(s) can | |
20564 | be popped. */ | |
20565 | for (regno = 0; regno <= LAST_LO_REGNUM; regno++) | |
20566 | { | |
20567 | if (mask & (1 << regno)) | |
20568 | high_regs_pushed--; | |
20569 | if (high_regs_pushed == 0) | |
20570 | break; | |
20571 | } | |
20572 | ||
20573 | mask &= (2 << regno) - 1; /* A noop if regno == 8 */ | |
20574 | ||
d6b4baa4 | 20575 | /* Pop the values into the low register(s). */ |
980e61bb | 20576 | thumb_pushpop (asm_out_file, mask, 0, NULL, mask); |
d5b7b3ae RE |
20577 | |
20578 | /* Move the value(s) into the high registers. */ | |
20579 | for (regno = 0; regno <= LAST_LO_REGNUM; regno++) | |
20580 | { | |
20581 | if (mask & (1 << regno)) | |
20582 | { | |
20583 | asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", next_hi_reg, | |
20584 | regno); | |
f676971a | 20585 | |
d5b7b3ae | 20586 | for (next_hi_reg++; next_hi_reg < 13; next_hi_reg++) |
57934c39 | 20587 | if (live_regs_mask & (1 << next_hi_reg)) |
d5b7b3ae RE |
20588 | break; |
20589 | } | |
20590 | } | |
20591 | } | |
57934c39 | 20592 | live_regs_mask &= ~0x0f00; |
d5b7b3ae RE |
20593 | } |
20594 | ||
57934c39 PB |
20595 | had_to_push_lr = (live_regs_mask & (1 << LR_REGNUM)) != 0; |
20596 | live_regs_mask &= 0xff; | |
20597 | ||
38173d38 | 20598 | if (crtl->args.pretend_args_size == 0 || TARGET_BACKTRACE) |
d5b7b3ae | 20599 | { |
f676971a | 20600 | /* Pop the return address into the PC. */ |
57934c39 | 20601 | if (had_to_push_lr) |
d5b7b3ae RE |
20602 | live_regs_mask |= 1 << PC_REGNUM; |
20603 | ||
20604 | /* Either no argument registers were pushed or a backtrace | |
20605 | structure was created which includes an adjusted stack | |
20606 | pointer, so just pop everything. */ | |
20607 | if (live_regs_mask) | |
980e61bb DJ |
20608 | thumb_pushpop (asm_out_file, live_regs_mask, FALSE, NULL, |
20609 | live_regs_mask); | |
57934c39 | 20610 | |
d5b7b3ae | 20611 | /* We have either just popped the return address into the |
e784c52c BS |
20612 | PC or it is was kept in LR for the entire function. |
20613 | Note that thumb_pushpop has already called thumb_exit if the | |
20614 | PC was in the list. */ | |
57934c39 PB |
20615 | if (!had_to_push_lr) |
20616 | thumb_exit (asm_out_file, LR_REGNUM); | |
d5b7b3ae RE |
20617 | } |
20618 | else | |
20619 | { | |
20620 | /* Pop everything but the return address. */ | |
d5b7b3ae | 20621 | if (live_regs_mask) |
980e61bb DJ |
20622 | thumb_pushpop (asm_out_file, live_regs_mask, FALSE, NULL, |
20623 | live_regs_mask); | |
d5b7b3ae RE |
20624 | |
20625 | if (had_to_push_lr) | |
57934c39 PB |
20626 | { |
20627 | if (size > 12) | |
20628 | { | |
20629 | /* We have no free low regs, so save one. */ | |
20630 | asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", IP_REGNUM, | |
20631 | LAST_ARG_REGNUM); | |
20632 | } | |
20633 | ||
20634 | /* Get the return address into a temporary register. */ | |
20635 | thumb_pushpop (asm_out_file, 1 << LAST_ARG_REGNUM, 0, NULL, | |
20636 | 1 << LAST_ARG_REGNUM); | |
20637 | ||
20638 | if (size > 12) | |
20639 | { | |
20640 | /* Move the return address to lr. */ | |
20641 | asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", LR_REGNUM, | |
20642 | LAST_ARG_REGNUM); | |
20643 | /* Restore the low register. */ | |
20644 | asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", LAST_ARG_REGNUM, | |
20645 | IP_REGNUM); | |
20646 | regno = LR_REGNUM; | |
20647 | } | |
20648 | else | |
20649 | regno = LAST_ARG_REGNUM; | |
20650 | } | |
20651 | else | |
20652 | regno = LR_REGNUM; | |
f676971a | 20653 | |
d5b7b3ae RE |
20654 | /* Remove the argument registers that were pushed onto the stack. */ |
20655 | asm_fprintf (asm_out_file, "\tadd\t%r, %r, #%d\n", | |
20656 | SP_REGNUM, SP_REGNUM, | |
38173d38 | 20657 | crtl->args.pretend_args_size); |
f676971a | 20658 | |
57934c39 | 20659 | thumb_exit (asm_out_file, regno); |
d5b7b3ae RE |
20660 | } |
20661 | ||
20662 | return ""; | |
20663 | } | |
20664 | ||
20665 | /* Functions to save and restore machine-specific function data. */ | |
e2500fed | 20666 | static struct machine_function * |
e32bac5b | 20667 | arm_init_machine_status (void) |
d5b7b3ae | 20668 | { |
e2500fed | 20669 | struct machine_function *machine; |
a9429e29 | 20670 | machine = ggc_alloc_cleared_machine_function (); |
6d3d9133 | 20671 | |
f676971a | 20672 | #if ARM_FT_UNKNOWN != 0 |
e2500fed | 20673 | machine->func_type = ARM_FT_UNKNOWN; |
6d3d9133 | 20674 | #endif |
e2500fed | 20675 | return machine; |
f7a80099 NC |
20676 | } |
20677 | ||
d5b7b3ae RE |
20678 | /* Return an RTX indicating where the return address to the |
20679 | calling function can be found. */ | |
20680 | rtx | |
e32bac5b | 20681 | arm_return_addr (int count, rtx frame ATTRIBUTE_UNUSED) |
d5b7b3ae | 20682 | { |
d5b7b3ae RE |
20683 | if (count != 0) |
20684 | return NULL_RTX; | |
20685 | ||
61f0ccff | 20686 | return get_hard_reg_initial_val (Pmode, LR_REGNUM); |
d5b7b3ae RE |
20687 | } |
20688 | ||
20689 | /* Do anything needed before RTL is emitted for each function. */ | |
20690 | void | |
e32bac5b | 20691 | arm_init_expanders (void) |
d5b7b3ae RE |
20692 | { |
20693 | /* Arrange to initialize and mark the machine per-function status. */ | |
20694 | init_machine_status = arm_init_machine_status; | |
3ac5ea7c RH |
20695 | |
20696 | /* This is to stop the combine pass optimizing away the alignment | |
20697 | adjustment of va_arg. */ | |
20698 | /* ??? It is claimed that this should not be necessary. */ | |
20699 | if (cfun) | |
20700 | mark_reg_pointer (arg_pointer_rtx, PARM_BOUNDARY); | |
d5b7b3ae RE |
20701 | } |
20702 | ||
0977774b | 20703 | |
2591db65 RE |
20704 | /* Like arm_compute_initial_elimination offset. Simpler because there |
20705 | isn't an ABI specified frame pointer for Thumb. Instead, we set it | |
20706 | to point at the base of the local variables after static stack | |
20707 | space for a function has been allocated. */ | |
0977774b | 20708 | |
5848830f PB |
20709 | HOST_WIDE_INT |
20710 | thumb_compute_initial_elimination_offset (unsigned int from, unsigned int to) | |
20711 | { | |
20712 | arm_stack_offsets *offsets; | |
0977774b | 20713 | |
5848830f | 20714 | offsets = arm_get_frame_offsets (); |
0977774b | 20715 | |
5848830f | 20716 | switch (from) |
0977774b | 20717 | { |
5848830f PB |
20718 | case ARG_POINTER_REGNUM: |
20719 | switch (to) | |
20720 | { | |
20721 | case STACK_POINTER_REGNUM: | |
20722 | return offsets->outgoing_args - offsets->saved_args; | |
0977774b | 20723 | |
5848830f PB |
20724 | case FRAME_POINTER_REGNUM: |
20725 | return offsets->soft_frame - offsets->saved_args; | |
0977774b | 20726 | |
5848830f PB |
20727 | case ARM_HARD_FRAME_POINTER_REGNUM: |
20728 | return offsets->saved_regs - offsets->saved_args; | |
0977774b | 20729 | |
2591db65 RE |
20730 | case THUMB_HARD_FRAME_POINTER_REGNUM: |
20731 | return offsets->locals_base - offsets->saved_args; | |
20732 | ||
5848830f | 20733 | default: |
e6d29d15 | 20734 | gcc_unreachable (); |
5848830f PB |
20735 | } |
20736 | break; | |
0977774b | 20737 | |
5848830f PB |
20738 | case FRAME_POINTER_REGNUM: |
20739 | switch (to) | |
20740 | { | |
20741 | case STACK_POINTER_REGNUM: | |
20742 | return offsets->outgoing_args - offsets->soft_frame; | |
0977774b | 20743 | |
5848830f PB |
20744 | case ARM_HARD_FRAME_POINTER_REGNUM: |
20745 | return offsets->saved_regs - offsets->soft_frame; | |
0977774b | 20746 | |
2591db65 RE |
20747 | case THUMB_HARD_FRAME_POINTER_REGNUM: |
20748 | return offsets->locals_base - offsets->soft_frame; | |
20749 | ||
5848830f | 20750 | default: |
e6d29d15 | 20751 | gcc_unreachable (); |
5848830f PB |
20752 | } |
20753 | break; | |
0977774b | 20754 | |
5848830f | 20755 | default: |
e6d29d15 | 20756 | gcc_unreachable (); |
5848830f | 20757 | } |
0977774b JT |
20758 | } |
20759 | ||
d5b7b3ae RE |
20760 | /* Generate the rest of a function's prologue. */ |
20761 | void | |
5b3e6663 | 20762 | thumb1_expand_prologue (void) |
d5b7b3ae | 20763 | { |
980e61bb DJ |
20764 | rtx insn, dwarf; |
20765 | ||
5848830f PB |
20766 | HOST_WIDE_INT amount; |
20767 | arm_stack_offsets *offsets; | |
6d3d9133 | 20768 | unsigned long func_type; |
3c7ad43e | 20769 | int regno; |
57934c39 | 20770 | unsigned long live_regs_mask; |
6d3d9133 NC |
20771 | |
20772 | func_type = arm_current_func_type (); | |
f676971a | 20773 | |
d5b7b3ae | 20774 | /* Naked functions don't have prologues. */ |
6d3d9133 | 20775 | if (IS_NAKED (func_type)) |
d5b7b3ae RE |
20776 | return; |
20777 | ||
6d3d9133 NC |
20778 | if (IS_INTERRUPT (func_type)) |
20779 | { | |
c725bd79 | 20780 | error ("interrupt Service Routines cannot be coded in Thumb mode"); |
6d3d9133 NC |
20781 | return; |
20782 | } | |
20783 | ||
954954d1 PB |
20784 | offsets = arm_get_frame_offsets (); |
20785 | live_regs_mask = offsets->saved_regs_mask; | |
b279b20a NC |
20786 | /* Load the pic register before setting the frame pointer, |
20787 | so we can use r7 as a temporary work register. */ | |
020a4035 | 20788 | if (flag_pic && arm_pic_register != INVALID_REGNUM) |
e55ef7f4 | 20789 | arm_load_pic_register (live_regs_mask); |
876f13b0 | 20790 | |
2591db65 | 20791 | if (!frame_pointer_needed && CALLER_INTERWORKING_SLOT_SIZE > 0) |
a2503645 RS |
20792 | emit_move_insn (gen_rtx_REG (Pmode, ARM_HARD_FRAME_POINTER_REGNUM), |
20793 | stack_pointer_rtx); | |
d5b7b3ae | 20794 | |
55256000 TK |
20795 | if (flag_stack_usage) |
20796 | current_function_static_stack_size | |
20797 | = offsets->outgoing_args - offsets->saved_args; | |
20798 | ||
5848830f | 20799 | amount = offsets->outgoing_args - offsets->saved_regs; |
e784c52c | 20800 | amount -= 4 * thumb1_extra_regs_pushed (offsets, true); |
d5b7b3ae RE |
20801 | if (amount) |
20802 | { | |
d5b7b3ae | 20803 | if (amount < 512) |
980e61bb DJ |
20804 | { |
20805 | insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, | |
20806 | GEN_INT (- amount))); | |
20807 | RTX_FRAME_RELATED_P (insn) = 1; | |
20808 | } | |
d5b7b3ae RE |
20809 | else |
20810 | { | |
d5b7b3ae RE |
20811 | rtx reg; |
20812 | ||
20813 | /* The stack decrement is too big for an immediate value in a single | |
20814 | insn. In theory we could issue multiple subtracts, but after | |
20815 | three of them it becomes more space efficient to place the full | |
20816 | value in the constant pool and load into a register. (Also the | |
20817 | ARM debugger really likes to see only one stack decrement per | |
20818 | function). So instead we look for a scratch register into which | |
20819 | we can load the decrement, and then we subtract this from the | |
20820 | stack pointer. Unfortunately on the thumb the only available | |
20821 | scratch registers are the argument registers, and we cannot use | |
20822 | these as they may hold arguments to the function. Instead we | |
20823 | attempt to locate a call preserved register which is used by this | |
20824 | function. If we can find one, then we know that it will have | |
20825 | been pushed at the start of the prologue and so we can corrupt | |
20826 | it now. */ | |
20827 | for (regno = LAST_ARG_REGNUM + 1; regno <= LAST_LO_REGNUM; regno++) | |
35596784 | 20828 | if (live_regs_mask & (1 << regno)) |
d5b7b3ae RE |
20829 | break; |
20830 | ||
35596784 | 20831 | gcc_assert(regno <= LAST_LO_REGNUM); |
d5b7b3ae | 20832 | |
35596784 | 20833 | reg = gen_rtx_REG (SImode, regno); |
d5b7b3ae | 20834 | |
35596784 | 20835 | emit_insn (gen_movsi (reg, GEN_INT (- amount))); |
980e61bb | 20836 | |
35596784 AJ |
20837 | insn = emit_insn (gen_addsi3 (stack_pointer_rtx, |
20838 | stack_pointer_rtx, reg)); | |
20839 | RTX_FRAME_RELATED_P (insn) = 1; | |
20840 | dwarf = gen_rtx_SET (VOIDmode, stack_pointer_rtx, | |
20841 | plus_constant (stack_pointer_rtx, | |
20842 | -amount)); | |
20843 | RTX_FRAME_RELATED_P (dwarf) = 1; | |
bbbbb16a | 20844 | add_reg_note (insn, REG_FRAME_RELATED_EXPR, dwarf); |
d5b7b3ae | 20845 | } |
2591db65 RE |
20846 | } |
20847 | ||
20848 | if (frame_pointer_needed) | |
5b3e6663 | 20849 | thumb_set_frame_pointer (offsets); |
f676971a | 20850 | |
74d9c39f DJ |
20851 | /* If we are profiling, make sure no instructions are scheduled before |
20852 | the call to mcount. Similarly if the user has requested no | |
20853 | scheduling in the prolog. Similarly if we want non-call exceptions | |
20854 | using the EABI unwinder, to prevent faulting instructions from being | |
20855 | swapped with a stack adjustment. */ | |
e3b5732b | 20856 | if (crtl->profile || !TARGET_SCHED_PROLOG |
d5fabb58 | 20857 | || (arm_except_unwind_info (&global_options) == UI_TARGET |
f0a0390e | 20858 | && cfun->can_throw_non_call_exceptions)) |
d5b7b3ae | 20859 | emit_insn (gen_blockage ()); |
3c7ad43e PB |
20860 | |
20861 | cfun->machine->lr_save_eliminated = !thumb_force_lr_save (); | |
57934c39 PB |
20862 | if (live_regs_mask & 0xff) |
20863 | cfun->machine->lr_save_eliminated = 0; | |
d5b7b3ae RE |
20864 | } |
20865 | ||
57934c39 | 20866 | |
d5b7b3ae | 20867 | void |
5b3e6663 | 20868 | thumb1_expand_epilogue (void) |
d5b7b3ae | 20869 | { |
5848830f PB |
20870 | HOST_WIDE_INT amount; |
20871 | arm_stack_offsets *offsets; | |
defc0463 RE |
20872 | int regno; |
20873 | ||
6d3d9133 NC |
20874 | /* Naked functions don't have prologues. */ |
20875 | if (IS_NAKED (arm_current_func_type ())) | |
d5b7b3ae RE |
20876 | return; |
20877 | ||
5848830f PB |
20878 | offsets = arm_get_frame_offsets (); |
20879 | amount = offsets->outgoing_args - offsets->saved_regs; | |
20880 | ||
d5b7b3ae | 20881 | if (frame_pointer_needed) |
2591db65 RE |
20882 | { |
20883 | emit_insn (gen_movsi (stack_pointer_rtx, hard_frame_pointer_rtx)); | |
20884 | amount = offsets->locals_base - offsets->saved_regs; | |
20885 | } | |
e784c52c | 20886 | amount -= 4 * thumb1_extra_regs_pushed (offsets, false); |
e0b92319 | 20887 | |
a3a531ec | 20888 | gcc_assert (amount >= 0); |
2591db65 | 20889 | if (amount) |
d5b7b3ae | 20890 | { |
d5b7b3ae RE |
20891 | if (amount < 512) |
20892 | emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, | |
20893 | GEN_INT (amount))); | |
20894 | else | |
20895 | { | |
20896 | /* r3 is always free in the epilogue. */ | |
f1c25d3b | 20897 | rtx reg = gen_rtx_REG (SImode, LAST_ARG_REGNUM); |
d5b7b3ae RE |
20898 | |
20899 | emit_insn (gen_movsi (reg, GEN_INT (amount))); | |
20900 | emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, reg)); | |
20901 | } | |
20902 | } | |
f676971a | 20903 | |
d5b7b3ae RE |
20904 | /* Emit a USE (stack_pointer_rtx), so that |
20905 | the stack adjustment will not be deleted. */ | |
6bacc7b0 | 20906 | emit_insn (gen_prologue_use (stack_pointer_rtx)); |
d5b7b3ae | 20907 | |
e3b5732b | 20908 | if (crtl->profile || !TARGET_SCHED_PROLOG) |
d5b7b3ae | 20909 | emit_insn (gen_blockage ()); |
defc0463 RE |
20910 | |
20911 | /* Emit a clobber for each insn that will be restored in the epilogue, | |
20912 | so that flow2 will get register lifetimes correct. */ | |
20913 | for (regno = 0; regno < 13; regno++) | |
6fb5fa3c | 20914 | if (df_regs_ever_live_p (regno) && !call_used_regs[regno]) |
c41c1387 | 20915 | emit_clobber (gen_rtx_REG (SImode, regno)); |
defc0463 | 20916 | |
6fb5fa3c | 20917 | if (! df_regs_ever_live_p (LR_REGNUM)) |
c41c1387 | 20918 | emit_use (gen_rtx_REG (SImode, LR_REGNUM)); |
d5b7b3ae RE |
20919 | } |
20920 | ||
08c148a8 | 20921 | static void |
5b3e6663 | 20922 | thumb1_output_function_prologue (FILE *f, HOST_WIDE_INT size ATTRIBUTE_UNUSED) |
d5b7b3ae | 20923 | { |
954954d1 | 20924 | arm_stack_offsets *offsets; |
b279b20a NC |
20925 | unsigned long live_regs_mask = 0; |
20926 | unsigned long l_mask; | |
20927 | unsigned high_regs_pushed = 0; | |
980e61bb | 20928 | int cfa_offset = 0; |
d5b7b3ae RE |
20929 | int regno; |
20930 | ||
6d3d9133 | 20931 | if (IS_NAKED (arm_current_func_type ())) |
d5b7b3ae RE |
20932 | return; |
20933 | ||
20934 | if (is_called_in_ARM_mode (current_function_decl)) | |
20935 | { | |
20936 | const char * name; | |
20937 | ||
e6d29d15 NS |
20938 | gcc_assert (GET_CODE (DECL_RTL (current_function_decl)) == MEM); |
20939 | gcc_assert (GET_CODE (XEXP (DECL_RTL (current_function_decl), 0)) | |
20940 | == SYMBOL_REF); | |
d5b7b3ae | 20941 | name = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0); |
f676971a | 20942 | |
d5b7b3ae RE |
20943 | /* Generate code sequence to switch us into Thumb mode. */ |
20944 | /* The .code 32 directive has already been emitted by | |
6d77b53e | 20945 | ASM_DECLARE_FUNCTION_NAME. */ |
d5b7b3ae RE |
20946 | asm_fprintf (f, "\torr\t%r, %r, #1\n", IP_REGNUM, PC_REGNUM); |
20947 | asm_fprintf (f, "\tbx\t%r\n", IP_REGNUM); | |
20948 | ||
20949 | /* Generate a label, so that the debugger will notice the | |
20950 | change in instruction sets. This label is also used by | |
20951 | the assembler to bypass the ARM code when this function | |
20952 | is called from a Thumb encoded function elsewhere in the | |
20953 | same file. Hence the definition of STUB_NAME here must | |
d6b4baa4 | 20954 | agree with the definition in gas/config/tc-arm.c. */ |
f676971a | 20955 | |
d5b7b3ae | 20956 | #define STUB_NAME ".real_start_of" |
f676971a | 20957 | |
761c70aa | 20958 | fprintf (f, "\t.code\t16\n"); |
d5b7b3ae RE |
20959 | #ifdef ARM_PE |
20960 | if (arm_dllexport_name_p (name)) | |
e5951263 | 20961 | name = arm_strip_name_encoding (name); |
f676971a | 20962 | #endif |
d5b7b3ae | 20963 | asm_fprintf (f, "\t.globl %s%U%s\n", STUB_NAME, name); |
761c70aa | 20964 | fprintf (f, "\t.thumb_func\n"); |
d5b7b3ae RE |
20965 | asm_fprintf (f, "%s%U%s:\n", STUB_NAME, name); |
20966 | } | |
f676971a | 20967 | |
38173d38 | 20968 | if (crtl->args.pretend_args_size) |
d5b7b3ae | 20969 | { |
617a1b71 | 20970 | /* Output unwind directive for the stack adjustment. */ |
d5fabb58 | 20971 | if (arm_except_unwind_info (&global_options) == UI_TARGET) |
617a1b71 | 20972 | fprintf (f, "\t.pad #%d\n", |
38173d38 | 20973 | crtl->args.pretend_args_size); |
617a1b71 | 20974 | |
3cb66fd7 | 20975 | if (cfun->machine->uses_anonymous_args) |
d5b7b3ae RE |
20976 | { |
20977 | int num_pushes; | |
f676971a | 20978 | |
761c70aa | 20979 | fprintf (f, "\tpush\t{"); |
d5b7b3ae | 20980 | |
38173d38 | 20981 | num_pushes = ARM_NUM_INTS (crtl->args.pretend_args_size); |
f676971a | 20982 | |
d5b7b3ae RE |
20983 | for (regno = LAST_ARG_REGNUM + 1 - num_pushes; |
20984 | regno <= LAST_ARG_REGNUM; | |
5895f793 | 20985 | regno++) |
d5b7b3ae RE |
20986 | asm_fprintf (f, "%r%s", regno, |
20987 | regno == LAST_ARG_REGNUM ? "" : ", "); | |
20988 | ||
761c70aa | 20989 | fprintf (f, "}\n"); |
d5b7b3ae RE |
20990 | } |
20991 | else | |
f676971a | 20992 | asm_fprintf (f, "\tsub\t%r, %r, #%d\n", |
d5b7b3ae | 20993 | SP_REGNUM, SP_REGNUM, |
38173d38 | 20994 | crtl->args.pretend_args_size); |
980e61bb DJ |
20995 | |
20996 | /* We don't need to record the stores for unwinding (would it | |
20997 | help the debugger any if we did?), but record the change in | |
20998 | the stack pointer. */ | |
20999 | if (dwarf2out_do_frame ()) | |
21000 | { | |
d342c045 | 21001 | char *l = dwarf2out_cfi_label (false); |
b279b20a | 21002 | |
38173d38 | 21003 | cfa_offset = cfa_offset + crtl->args.pretend_args_size; |
980e61bb DJ |
21004 | dwarf2out_def_cfa (l, SP_REGNUM, cfa_offset); |
21005 | } | |
d5b7b3ae RE |
21006 | } |
21007 | ||
b279b20a | 21008 | /* Get the registers we are going to push. */ |
954954d1 PB |
21009 | offsets = arm_get_frame_offsets (); |
21010 | live_regs_mask = offsets->saved_regs_mask; | |
b279b20a | 21011 | /* Extract a mask of the ones we can give to the Thumb's push instruction. */ |
57934c39 | 21012 | l_mask = live_regs_mask & 0x40ff; |
b279b20a NC |
21013 | /* Then count how many other high registers will need to be pushed. */ |
21014 | high_regs_pushed = bit_count (live_regs_mask & 0x0f00); | |
d5b7b3ae RE |
21015 | |
21016 | if (TARGET_BACKTRACE) | |
21017 | { | |
b279b20a NC |
21018 | unsigned offset; |
21019 | unsigned work_register; | |
f676971a | 21020 | |
d5b7b3ae RE |
21021 | /* We have been asked to create a stack backtrace structure. |
21022 | The code looks like this: | |
f676971a | 21023 | |
d5b7b3ae RE |
21024 | 0 .align 2 |
21025 | 0 func: | |
21026 | 0 sub SP, #16 Reserve space for 4 registers. | |
57934c39 | 21027 | 2 push {R7} Push low registers. |
d5b7b3ae RE |
21028 | 4 add R7, SP, #20 Get the stack pointer before the push. |
21029 | 6 str R7, [SP, #8] Store the stack pointer (before reserving the space). | |
21030 | 8 mov R7, PC Get hold of the start of this code plus 12. | |
21031 | 10 str R7, [SP, #16] Store it. | |
21032 | 12 mov R7, FP Get hold of the current frame pointer. | |
21033 | 14 str R7, [SP, #4] Store it. | |
21034 | 16 mov R7, LR Get hold of the current return address. | |
21035 | 18 str R7, [SP, #12] Store it. | |
21036 | 20 add R7, SP, #16 Point at the start of the backtrace structure. | |
21037 | 22 mov FP, R7 Put this value into the frame pointer. */ | |
21038 | ||
57934c39 | 21039 | work_register = thumb_find_work_register (live_regs_mask); |
f676971a | 21040 | |
d5fabb58 | 21041 | if (arm_except_unwind_info (&global_options) == UI_TARGET) |
617a1b71 PB |
21042 | asm_fprintf (f, "\t.pad #16\n"); |
21043 | ||
d5b7b3ae RE |
21044 | asm_fprintf |
21045 | (f, "\tsub\t%r, %r, #16\t%@ Create stack backtrace structure\n", | |
21046 | SP_REGNUM, SP_REGNUM); | |
980e61bb DJ |
21047 | |
21048 | if (dwarf2out_do_frame ()) | |
21049 | { | |
d342c045 | 21050 | char *l = dwarf2out_cfi_label (false); |
b279b20a | 21051 | |
980e61bb DJ |
21052 | cfa_offset = cfa_offset + 16; |
21053 | dwarf2out_def_cfa (l, SP_REGNUM, cfa_offset); | |
21054 | } | |
21055 | ||
57934c39 PB |
21056 | if (l_mask) |
21057 | { | |
21058 | thumb_pushpop (f, l_mask, 1, &cfa_offset, l_mask); | |
1a59548b | 21059 | offset = bit_count (l_mask) * UNITS_PER_WORD; |
57934c39 PB |
21060 | } |
21061 | else | |
21062 | offset = 0; | |
f676971a | 21063 | |
d5b7b3ae | 21064 | asm_fprintf (f, "\tadd\t%r, %r, #%d\n", work_register, SP_REGNUM, |
38173d38 | 21065 | offset + 16 + crtl->args.pretend_args_size); |
f676971a | 21066 | |
d5b7b3ae RE |
21067 | asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM, |
21068 | offset + 4); | |
21069 | ||
21070 | /* Make sure that the instruction fetching the PC is in the right place | |
21071 | to calculate "start of backtrace creation code + 12". */ | |
57934c39 | 21072 | if (l_mask) |
d5b7b3ae RE |
21073 | { |
21074 | asm_fprintf (f, "\tmov\t%r, %r\n", work_register, PC_REGNUM); | |
21075 | asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM, | |
21076 | offset + 12); | |
21077 | asm_fprintf (f, "\tmov\t%r, %r\n", work_register, | |
21078 | ARM_HARD_FRAME_POINTER_REGNUM); | |
21079 | asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM, | |
21080 | offset); | |
21081 | } | |
21082 | else | |
21083 | { | |
21084 | asm_fprintf (f, "\tmov\t%r, %r\n", work_register, | |
21085 | ARM_HARD_FRAME_POINTER_REGNUM); | |
21086 | asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM, | |
21087 | offset); | |
21088 | asm_fprintf (f, "\tmov\t%r, %r\n", work_register, PC_REGNUM); | |
21089 | asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM, | |
21090 | offset + 12); | |
21091 | } | |
f676971a | 21092 | |
d5b7b3ae RE |
21093 | asm_fprintf (f, "\tmov\t%r, %r\n", work_register, LR_REGNUM); |
21094 | asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM, | |
21095 | offset + 8); | |
21096 | asm_fprintf (f, "\tadd\t%r, %r, #%d\n", work_register, SP_REGNUM, | |
21097 | offset + 12); | |
21098 | asm_fprintf (f, "\tmov\t%r, %r\t\t%@ Backtrace structure created\n", | |
21099 | ARM_HARD_FRAME_POINTER_REGNUM, work_register); | |
21100 | } | |
0fa2e4df | 21101 | /* Optimization: If we are not pushing any low registers but we are going |
b279b20a NC |
21102 | to push some high registers then delay our first push. This will just |
21103 | be a push of LR and we can combine it with the push of the first high | |
21104 | register. */ | |
21105 | else if ((l_mask & 0xff) != 0 | |
21106 | || (high_regs_pushed == 0 && l_mask)) | |
cb751cbd BS |
21107 | { |
21108 | unsigned long mask = l_mask; | |
e784c52c | 21109 | mask |= (1 << thumb1_extra_regs_pushed (offsets, true)) - 1; |
cb751cbd BS |
21110 | thumb_pushpop (f, mask, 1, &cfa_offset, mask); |
21111 | } | |
d5b7b3ae | 21112 | |
d5b7b3ae RE |
21113 | if (high_regs_pushed) |
21114 | { | |
b279b20a NC |
21115 | unsigned pushable_regs; |
21116 | unsigned next_hi_reg; | |
d5b7b3ae RE |
21117 | |
21118 | for (next_hi_reg = 12; next_hi_reg > LAST_LO_REGNUM; next_hi_reg--) | |
57934c39 | 21119 | if (live_regs_mask & (1 << next_hi_reg)) |
e26053d1 | 21120 | break; |
d5b7b3ae | 21121 | |
57934c39 | 21122 | pushable_regs = l_mask & 0xff; |
d5b7b3ae RE |
21123 | |
21124 | if (pushable_regs == 0) | |
57934c39 | 21125 | pushable_regs = 1 << thumb_find_work_register (live_regs_mask); |
d5b7b3ae RE |
21126 | |
21127 | while (high_regs_pushed > 0) | |
21128 | { | |
b279b20a | 21129 | unsigned long real_regs_mask = 0; |
980e61bb | 21130 | |
b279b20a | 21131 | for (regno = LAST_LO_REGNUM; regno >= 0; regno --) |
d5b7b3ae | 21132 | { |
57934c39 | 21133 | if (pushable_regs & (1 << regno)) |
d5b7b3ae RE |
21134 | { |
21135 | asm_fprintf (f, "\tmov\t%r, %r\n", regno, next_hi_reg); | |
f676971a | 21136 | |
b279b20a | 21137 | high_regs_pushed --; |
980e61bb | 21138 | real_regs_mask |= (1 << next_hi_reg); |
f676971a | 21139 | |
d5b7b3ae | 21140 | if (high_regs_pushed) |
aeaf4d25 | 21141 | { |
b279b20a NC |
21142 | for (next_hi_reg --; next_hi_reg > LAST_LO_REGNUM; |
21143 | next_hi_reg --) | |
57934c39 | 21144 | if (live_regs_mask & (1 << next_hi_reg)) |
d5b7b3ae | 21145 | break; |
aeaf4d25 | 21146 | } |
d5b7b3ae RE |
21147 | else |
21148 | { | |
57934c39 | 21149 | pushable_regs &= ~((1 << regno) - 1); |
d5b7b3ae RE |
21150 | break; |
21151 | } | |
21152 | } | |
21153 | } | |
980e61bb | 21154 | |
b279b20a NC |
21155 | /* If we had to find a work register and we have not yet |
21156 | saved the LR then add it to the list of regs to push. */ | |
21157 | if (l_mask == (1 << LR_REGNUM)) | |
21158 | { | |
21159 | thumb_pushpop (f, pushable_regs | (1 << LR_REGNUM), | |
21160 | 1, &cfa_offset, | |
21161 | real_regs_mask | (1 << LR_REGNUM)); | |
21162 | l_mask = 0; | |
21163 | } | |
21164 | else | |
21165 | thumb_pushpop (f, pushable_regs, 1, &cfa_offset, real_regs_mask); | |
d5b7b3ae | 21166 | } |
d5b7b3ae RE |
21167 | } |
21168 | } | |
21169 | ||
21170 | /* Handle the case of a double word load into a low register from | |
21171 | a computed memory address. The computed address may involve a | |
21172 | register which is overwritten by the load. */ | |
cd2b33d0 | 21173 | const char * |
e32bac5b | 21174 | thumb_load_double_from_address (rtx *operands) |
d5b7b3ae RE |
21175 | { |
21176 | rtx addr; | |
21177 | rtx base; | |
21178 | rtx offset; | |
21179 | rtx arg1; | |
21180 | rtx arg2; | |
f676971a | 21181 | |
e6d29d15 NS |
21182 | gcc_assert (GET_CODE (operands[0]) == REG); |
21183 | gcc_assert (GET_CODE (operands[1]) == MEM); | |
d5b7b3ae RE |
21184 | |
21185 | /* Get the memory address. */ | |
21186 | addr = XEXP (operands[1], 0); | |
f676971a | 21187 | |
d5b7b3ae RE |
21188 | /* Work out how the memory address is computed. */ |
21189 | switch (GET_CODE (addr)) | |
21190 | { | |
21191 | case REG: | |
31fa16b6 | 21192 | operands[2] = adjust_address (operands[1], SImode, 4); |
e0b92319 | 21193 | |
d5b7b3ae RE |
21194 | if (REGNO (operands[0]) == REGNO (addr)) |
21195 | { | |
21196 | output_asm_insn ("ldr\t%H0, %2", operands); | |
21197 | output_asm_insn ("ldr\t%0, %1", operands); | |
21198 | } | |
21199 | else | |
21200 | { | |
21201 | output_asm_insn ("ldr\t%0, %1", operands); | |
21202 | output_asm_insn ("ldr\t%H0, %2", operands); | |
21203 | } | |
21204 | break; | |
f676971a | 21205 | |
d5b7b3ae RE |
21206 | case CONST: |
21207 | /* Compute <address> + 4 for the high order load. */ | |
31fa16b6 | 21208 | operands[2] = adjust_address (operands[1], SImode, 4); |
e0b92319 | 21209 | |
d5b7b3ae RE |
21210 | output_asm_insn ("ldr\t%0, %1", operands); |
21211 | output_asm_insn ("ldr\t%H0, %2", operands); | |
21212 | break; | |
f676971a | 21213 | |
d5b7b3ae RE |
21214 | case PLUS: |
21215 | arg1 = XEXP (addr, 0); | |
21216 | arg2 = XEXP (addr, 1); | |
f676971a | 21217 | |
d5b7b3ae RE |
21218 | if (CONSTANT_P (arg1)) |
21219 | base = arg2, offset = arg1; | |
21220 | else | |
21221 | base = arg1, offset = arg2; | |
f676971a | 21222 | |
e6d29d15 | 21223 | gcc_assert (GET_CODE (base) == REG); |
d5b7b3ae RE |
21224 | |
21225 | /* Catch the case of <address> = <reg> + <reg> */ | |
21226 | if (GET_CODE (offset) == REG) | |
21227 | { | |
21228 | int reg_offset = REGNO (offset); | |
21229 | int reg_base = REGNO (base); | |
21230 | int reg_dest = REGNO (operands[0]); | |
f676971a | 21231 | |
d5b7b3ae RE |
21232 | /* Add the base and offset registers together into the |
21233 | higher destination register. */ | |
21234 | asm_fprintf (asm_out_file, "\tadd\t%r, %r, %r", | |
21235 | reg_dest + 1, reg_base, reg_offset); | |
f676971a | 21236 | |
d5b7b3ae RE |
21237 | /* Load the lower destination register from the address in |
21238 | the higher destination register. */ | |
21239 | asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #0]", | |
21240 | reg_dest, reg_dest + 1); | |
f676971a | 21241 | |
d5b7b3ae RE |
21242 | /* Load the higher destination register from its own address |
21243 | plus 4. */ | |
21244 | asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #4]", | |
21245 | reg_dest + 1, reg_dest + 1); | |
21246 | } | |
21247 | else | |
21248 | { | |
21249 | /* Compute <address> + 4 for the high order load. */ | |
31fa16b6 | 21250 | operands[2] = adjust_address (operands[1], SImode, 4); |
f676971a | 21251 | |
d5b7b3ae RE |
21252 | /* If the computed address is held in the low order register |
21253 | then load the high order register first, otherwise always | |
21254 | load the low order register first. */ | |
21255 | if (REGNO (operands[0]) == REGNO (base)) | |
21256 | { | |
21257 | output_asm_insn ("ldr\t%H0, %2", operands); | |
21258 | output_asm_insn ("ldr\t%0, %1", operands); | |
21259 | } | |
21260 | else | |
21261 | { | |
21262 | output_asm_insn ("ldr\t%0, %1", operands); | |
21263 | output_asm_insn ("ldr\t%H0, %2", operands); | |
21264 | } | |
21265 | } | |
21266 | break; | |
21267 | ||
21268 | case LABEL_REF: | |
21269 | /* With no registers to worry about we can just load the value | |
21270 | directly. */ | |
31fa16b6 | 21271 | operands[2] = adjust_address (operands[1], SImode, 4); |
f676971a | 21272 | |
d5b7b3ae RE |
21273 | output_asm_insn ("ldr\t%H0, %2", operands); |
21274 | output_asm_insn ("ldr\t%0, %1", operands); | |
21275 | break; | |
f676971a | 21276 | |
d5b7b3ae | 21277 | default: |
e6d29d15 | 21278 | gcc_unreachable (); |
d5b7b3ae | 21279 | } |
f676971a | 21280 | |
d5b7b3ae RE |
21281 | return ""; |
21282 | } | |
21283 | ||
cd2b33d0 | 21284 | const char * |
e32bac5b | 21285 | thumb_output_move_mem_multiple (int n, rtx *operands) |
d5b7b3ae RE |
21286 | { |
21287 | rtx tmp; | |
21288 | ||
21289 | switch (n) | |
21290 | { | |
21291 | case 2: | |
ca356f3a | 21292 | if (REGNO (operands[4]) > REGNO (operands[5])) |
d5b7b3ae | 21293 | { |
ca356f3a RE |
21294 | tmp = operands[4]; |
21295 | operands[4] = operands[5]; | |
21296 | operands[5] = tmp; | |
d5b7b3ae | 21297 | } |
ca356f3a RE |
21298 | output_asm_insn ("ldmia\t%1!, {%4, %5}", operands); |
21299 | output_asm_insn ("stmia\t%0!, {%4, %5}", operands); | |
d5b7b3ae RE |
21300 | break; |
21301 | ||
21302 | case 3: | |
ca356f3a | 21303 | if (REGNO (operands[4]) > REGNO (operands[5])) |
d5b7b3ae | 21304 | { |
ca356f3a RE |
21305 | tmp = operands[4]; |
21306 | operands[4] = operands[5]; | |
21307 | operands[5] = tmp; | |
d5b7b3ae | 21308 | } |
ca356f3a | 21309 | if (REGNO (operands[5]) > REGNO (operands[6])) |
d5b7b3ae | 21310 | { |
ca356f3a RE |
21311 | tmp = operands[5]; |
21312 | operands[5] = operands[6]; | |
21313 | operands[6] = tmp; | |
d5b7b3ae | 21314 | } |
ca356f3a | 21315 | if (REGNO (operands[4]) > REGNO (operands[5])) |
d5b7b3ae | 21316 | { |
ca356f3a RE |
21317 | tmp = operands[4]; |
21318 | operands[4] = operands[5]; | |
21319 | operands[5] = tmp; | |
d5b7b3ae | 21320 | } |
f676971a | 21321 | |
ca356f3a RE |
21322 | output_asm_insn ("ldmia\t%1!, {%4, %5, %6}", operands); |
21323 | output_asm_insn ("stmia\t%0!, {%4, %5, %6}", operands); | |
d5b7b3ae RE |
21324 | break; |
21325 | ||
21326 | default: | |
e6d29d15 | 21327 | gcc_unreachable (); |
d5b7b3ae RE |
21328 | } |
21329 | ||
21330 | return ""; | |
21331 | } | |
21332 | ||
b12a00f1 RE |
21333 | /* Output a call-via instruction for thumb state. */ |
21334 | const char * | |
21335 | thumb_call_via_reg (rtx reg) | |
21336 | { | |
21337 | int regno = REGNO (reg); | |
21338 | rtx *labelp; | |
21339 | ||
57ecec57 | 21340 | gcc_assert (regno < LR_REGNUM); |
b12a00f1 RE |
21341 | |
21342 | /* If we are in the normal text section we can use a single instance | |
21343 | per compilation unit. If we are doing function sections, then we need | |
21344 | an entry per section, since we can't rely on reachability. */ | |
d6b5193b | 21345 | if (in_section == text_section) |
b12a00f1 RE |
21346 | { |
21347 | thumb_call_reg_needed = 1; | |
21348 | ||
21349 | if (thumb_call_via_label[regno] == NULL) | |
21350 | thumb_call_via_label[regno] = gen_label_rtx (); | |
21351 | labelp = thumb_call_via_label + regno; | |
21352 | } | |
21353 | else | |
21354 | { | |
21355 | if (cfun->machine->call_via[regno] == NULL) | |
21356 | cfun->machine->call_via[regno] = gen_label_rtx (); | |
21357 | labelp = cfun->machine->call_via + regno; | |
21358 | } | |
21359 | ||
21360 | output_asm_insn ("bl\t%a0", labelp); | |
21361 | return ""; | |
21362 | } | |
21363 | ||
1d6e90ac | 21364 | /* Routines for generating rtl. */ |
d5b7b3ae | 21365 | void |
70128ad9 | 21366 | thumb_expand_movmemqi (rtx *operands) |
d5b7b3ae RE |
21367 | { |
21368 | rtx out = copy_to_mode_reg (SImode, XEXP (operands[0], 0)); | |
21369 | rtx in = copy_to_mode_reg (SImode, XEXP (operands[1], 0)); | |
21370 | HOST_WIDE_INT len = INTVAL (operands[2]); | |
21371 | HOST_WIDE_INT offset = 0; | |
21372 | ||
21373 | while (len >= 12) | |
21374 | { | |
ca356f3a | 21375 | emit_insn (gen_movmem12b (out, in, out, in)); |
d5b7b3ae RE |
21376 | len -= 12; |
21377 | } | |
f676971a | 21378 | |
d5b7b3ae RE |
21379 | if (len >= 8) |
21380 | { | |
ca356f3a | 21381 | emit_insn (gen_movmem8b (out, in, out, in)); |
d5b7b3ae RE |
21382 | len -= 8; |
21383 | } | |
f676971a | 21384 | |
d5b7b3ae RE |
21385 | if (len >= 4) |
21386 | { | |
21387 | rtx reg = gen_reg_rtx (SImode); | |
f1c25d3b KH |
21388 | emit_insn (gen_movsi (reg, gen_rtx_MEM (SImode, in))); |
21389 | emit_insn (gen_movsi (gen_rtx_MEM (SImode, out), reg)); | |
d5b7b3ae RE |
21390 | len -= 4; |
21391 | offset += 4; | |
21392 | } | |
f676971a | 21393 | |
d5b7b3ae RE |
21394 | if (len >= 2) |
21395 | { | |
21396 | rtx reg = gen_reg_rtx (HImode); | |
f676971a | 21397 | emit_insn (gen_movhi (reg, gen_rtx_MEM (HImode, |
f1c25d3b KH |
21398 | plus_constant (in, offset)))); |
21399 | emit_insn (gen_movhi (gen_rtx_MEM (HImode, plus_constant (out, offset)), | |
d5b7b3ae RE |
21400 | reg)); |
21401 | len -= 2; | |
21402 | offset += 2; | |
21403 | } | |
f676971a | 21404 | |
d5b7b3ae RE |
21405 | if (len) |
21406 | { | |
21407 | rtx reg = gen_reg_rtx (QImode); | |
f1c25d3b KH |
21408 | emit_insn (gen_movqi (reg, gen_rtx_MEM (QImode, |
21409 | plus_constant (in, offset)))); | |
21410 | emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (out, offset)), | |
d5b7b3ae RE |
21411 | reg)); |
21412 | } | |
21413 | } | |
21414 | ||
d5b7b3ae | 21415 | void |
e32bac5b | 21416 | thumb_reload_out_hi (rtx *operands) |
d5b7b3ae RE |
21417 | { |
21418 | emit_insn (gen_thumb_movhi_clobber (operands[0], operands[1], operands[2])); | |
21419 | } | |
21420 | ||
f676971a | 21421 | /* Handle reading a half-word from memory during reload. */ |
d5b7b3ae | 21422 | void |
e32bac5b | 21423 | thumb_reload_in_hi (rtx *operands ATTRIBUTE_UNUSED) |
d5b7b3ae | 21424 | { |
e6d29d15 | 21425 | gcc_unreachable (); |
d5b7b3ae RE |
21426 | } |
21427 | ||
c27ba912 DM |
21428 | /* Return the length of a function name prefix |
21429 | that starts with the character 'c'. */ | |
21430 | static int | |
e32bac5b | 21431 | arm_get_strip_length (int c) |
c27ba912 DM |
21432 | { |
21433 | switch (c) | |
21434 | { | |
21435 | ARM_NAME_ENCODING_LENGTHS | |
f676971a | 21436 | default: return 0; |
c27ba912 DM |
21437 | } |
21438 | } | |
21439 | ||
21440 | /* Return a pointer to a function's name with any | |
21441 | and all prefix encodings stripped from it. */ | |
21442 | const char * | |
e32bac5b | 21443 | arm_strip_name_encoding (const char *name) |
c27ba912 DM |
21444 | { |
21445 | int skip; | |
f676971a | 21446 | |
c27ba912 DM |
21447 | while ((skip = arm_get_strip_length (* name))) |
21448 | name += skip; | |
21449 | ||
21450 | return name; | |
21451 | } | |
21452 | ||
e1944073 KW |
21453 | /* If there is a '*' anywhere in the name's prefix, then |
21454 | emit the stripped name verbatim, otherwise prepend an | |
21455 | underscore if leading underscores are being used. */ | |
e1944073 | 21456 | void |
e32bac5b | 21457 | arm_asm_output_labelref (FILE *stream, const char *name) |
e1944073 KW |
21458 | { |
21459 | int skip; | |
21460 | int verbatim = 0; | |
21461 | ||
21462 | while ((skip = arm_get_strip_length (* name))) | |
21463 | { | |
21464 | verbatim |= (*name == '*'); | |
21465 | name += skip; | |
21466 | } | |
21467 | ||
21468 | if (verbatim) | |
21469 | fputs (name, stream); | |
21470 | else | |
21471 | asm_fprintf (stream, "%U%s", name); | |
21472 | } | |
21473 | ||
6c6aa1af PB |
21474 | static void |
21475 | arm_file_start (void) | |
21476 | { | |
21477 | int val; | |
21478 | ||
5b3e6663 PB |
21479 | if (TARGET_UNIFIED_ASM) |
21480 | asm_fprintf (asm_out_file, "\t.syntax unified\n"); | |
21481 | ||
6c6aa1af PB |
21482 | if (TARGET_BPABI) |
21483 | { | |
21484 | const char *fpu_name; | |
12a0a4d4 PB |
21485 | if (arm_selected_arch) |
21486 | asm_fprintf (asm_out_file, "\t.arch %s\n", arm_selected_arch->name); | |
6c6aa1af | 21487 | else |
12a0a4d4 | 21488 | asm_fprintf (asm_out_file, "\t.cpu %s\n", arm_selected_cpu->name); |
6c6aa1af PB |
21489 | |
21490 | if (TARGET_SOFT_FLOAT) | |
21491 | { | |
21492 | if (TARGET_VFP) | |
21493 | fpu_name = "softvfp"; | |
21494 | else | |
21495 | fpu_name = "softfpa"; | |
21496 | } | |
21497 | else | |
21498 | { | |
d79f3032 PB |
21499 | fpu_name = arm_fpu_desc->name; |
21500 | if (arm_fpu_desc->model == ARM_FP_MODEL_VFP) | |
f1adb0a9 JB |
21501 | { |
21502 | if (TARGET_HARD_FLOAT) | |
21503 | asm_fprintf (asm_out_file, "\t.eabi_attribute 27, 3\n"); | |
21504 | if (TARGET_HARD_FLOAT_ABI) | |
21505 | asm_fprintf (asm_out_file, "\t.eabi_attribute 28, 1\n"); | |
21506 | } | |
6c6aa1af PB |
21507 | } |
21508 | asm_fprintf (asm_out_file, "\t.fpu %s\n", fpu_name); | |
21509 | ||
21510 | /* Some of these attributes only apply when the corresponding features | |
21511 | are used. However we don't have any easy way of figuring this out. | |
21512 | Conservatively record the setting that would have been used. */ | |
21513 | ||
6c6aa1af PB |
21514 | /* Tag_ABI_FP_rounding. */ |
21515 | if (flag_rounding_math) | |
21516 | asm_fprintf (asm_out_file, "\t.eabi_attribute 19, 1\n"); | |
21517 | if (!flag_unsafe_math_optimizations) | |
21518 | { | |
21519 | /* Tag_ABI_FP_denomal. */ | |
21520 | asm_fprintf (asm_out_file, "\t.eabi_attribute 20, 1\n"); | |
21521 | /* Tag_ABI_FP_exceptions. */ | |
21522 | asm_fprintf (asm_out_file, "\t.eabi_attribute 21, 1\n"); | |
21523 | } | |
21524 | /* Tag_ABI_FP_user_exceptions. */ | |
21525 | if (flag_signaling_nans) | |
21526 | asm_fprintf (asm_out_file, "\t.eabi_attribute 22, 1\n"); | |
21527 | /* Tag_ABI_FP_number_model. */ | |
21528 | asm_fprintf (asm_out_file, "\t.eabi_attribute 23, %d\n", | |
21529 | flag_finite_math_only ? 1 : 3); | |
21530 | ||
21531 | /* Tag_ABI_align8_needed. */ | |
21532 | asm_fprintf (asm_out_file, "\t.eabi_attribute 24, 1\n"); | |
21533 | /* Tag_ABI_align8_preserved. */ | |
21534 | asm_fprintf (asm_out_file, "\t.eabi_attribute 25, 1\n"); | |
21535 | /* Tag_ABI_enum_size. */ | |
21536 | asm_fprintf (asm_out_file, "\t.eabi_attribute 26, %d\n", | |
21537 | flag_short_enums ? 1 : 2); | |
21538 | ||
21539 | /* Tag_ABI_optimization_goals. */ | |
21540 | if (optimize_size) | |
21541 | val = 4; | |
21542 | else if (optimize >= 2) | |
21543 | val = 2; | |
21544 | else if (optimize) | |
21545 | val = 1; | |
21546 | else | |
21547 | val = 6; | |
21548 | asm_fprintf (asm_out_file, "\t.eabi_attribute 30, %d\n", val); | |
b76c3c4b | 21549 | |
0fd8c3ad SL |
21550 | /* Tag_ABI_FP_16bit_format. */ |
21551 | if (arm_fp16_format) | |
21552 | asm_fprintf (asm_out_file, "\t.eabi_attribute 38, %d\n", | |
21553 | (int)arm_fp16_format); | |
21554 | ||
b76c3c4b PB |
21555 | if (arm_lang_output_object_attributes_hook) |
21556 | arm_lang_output_object_attributes_hook(); | |
6c6aa1af PB |
21557 | } |
21558 | default_file_start(); | |
21559 | } | |
21560 | ||
b12a00f1 RE |
21561 | static void |
21562 | arm_file_end (void) | |
21563 | { | |
21564 | int regno; | |
21565 | ||
978e411f CD |
21566 | if (NEED_INDICATE_EXEC_STACK) |
21567 | /* Add .note.GNU-stack. */ | |
21568 | file_end_indicate_exec_stack (); | |
21569 | ||
b12a00f1 RE |
21570 | if (! thumb_call_reg_needed) |
21571 | return; | |
21572 | ||
d6b5193b | 21573 | switch_to_section (text_section); |
b12a00f1 RE |
21574 | asm_fprintf (asm_out_file, "\t.code 16\n"); |
21575 | ASM_OUTPUT_ALIGN (asm_out_file, 1); | |
21576 | ||
57ecec57 | 21577 | for (regno = 0; regno < LR_REGNUM; regno++) |
b12a00f1 RE |
21578 | { |
21579 | rtx label = thumb_call_via_label[regno]; | |
21580 | ||
21581 | if (label != 0) | |
21582 | { | |
21583 | targetm.asm_out.internal_label (asm_out_file, "L", | |
21584 | CODE_LABEL_NUMBER (label)); | |
21585 | asm_fprintf (asm_out_file, "\tbx\t%r\n", regno); | |
21586 | } | |
21587 | } | |
21588 | } | |
21589 | ||
fb49053f RH |
21590 | #ifndef ARM_PE |
21591 | /* Symbols in the text segment can be accessed without indirecting via the | |
21592 | constant pool; it may take an extra binary operation, but this is still | |
21593 | faster than indirecting via memory. Don't do this when not optimizing, | |
21594 | since we won't be calculating al of the offsets necessary to do this | |
21595 | simplification. */ | |
21596 | ||
21597 | static void | |
e32bac5b | 21598 | arm_encode_section_info (tree decl, rtx rtl, int first) |
fb49053f | 21599 | { |
3521b33c | 21600 | if (optimize > 0 && TREE_CONSTANT (decl)) |
c6a2438a | 21601 | SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1; |
fb49053f | 21602 | |
d3585b76 | 21603 | default_encode_section_info (decl, rtl, first); |
fb49053f RH |
21604 | } |
21605 | #endif /* !ARM_PE */ | |
483ab821 | 21606 | |
4977bab6 | 21607 | static void |
e32bac5b | 21608 | arm_internal_label (FILE *stream, const char *prefix, unsigned long labelno) |
4977bab6 ZW |
21609 | { |
21610 | if (arm_ccfsm_state == 3 && (unsigned) arm_target_label == labelno | |
21611 | && !strcmp (prefix, "L")) | |
21612 | { | |
21613 | arm_ccfsm_state = 0; | |
21614 | arm_target_insn = NULL; | |
21615 | } | |
21616 | default_internal_label (stream, prefix, labelno); | |
21617 | } | |
21618 | ||
c590b625 RH |
21619 | /* Output code to add DELTA to the first argument, and then jump |
21620 | to FUNCTION. Used for C++ multiple inheritance. */ | |
c590b625 | 21621 | static void |
e32bac5b RE |
21622 | arm_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED, |
21623 | HOST_WIDE_INT delta, | |
21624 | HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED, | |
21625 | tree function) | |
483ab821 | 21626 | { |
9b66ebb1 PB |
21627 | static int thunk_label = 0; |
21628 | char label[256]; | |
54b9e939 | 21629 | char labelpc[256]; |
483ab821 MM |
21630 | int mi_delta = delta; |
21631 | const char *const mi_op = mi_delta < 0 ? "sub" : "add"; | |
21632 | int shift = 0; | |
61f71b34 | 21633 | int this_regno = (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function) |
483ab821 MM |
21634 | ? 1 : 0); |
21635 | if (mi_delta < 0) | |
21636 | mi_delta = - mi_delta; | |
bf98ec6c | 21637 | |
5b3e6663 | 21638 | if (TARGET_THUMB1) |
9b66ebb1 PB |
21639 | { |
21640 | int labelno = thunk_label++; | |
21641 | ASM_GENERATE_INTERNAL_LABEL (label, "LTHUMBFUNC", labelno); | |
bf98ec6c PB |
21642 | /* Thunks are entered in arm mode when avaiable. */ |
21643 | if (TARGET_THUMB1_ONLY) | |
21644 | { | |
21645 | /* push r3 so we can use it as a temporary. */ | |
21646 | /* TODO: Omit this save if r3 is not used. */ | |
21647 | fputs ("\tpush {r3}\n", file); | |
21648 | fputs ("\tldr\tr3, ", file); | |
21649 | } | |
21650 | else | |
21651 | { | |
21652 | fputs ("\tldr\tr12, ", file); | |
21653 | } | |
9b66ebb1 PB |
21654 | assemble_name (file, label); |
21655 | fputc ('\n', file); | |
54b9e939 KH |
21656 | if (flag_pic) |
21657 | { | |
21658 | /* If we are generating PIC, the ldr instruction below loads | |
21659 | "(target - 7) - .LTHUNKPCn" into r12. The pc reads as | |
21660 | the address of the add + 8, so we have: | |
21661 | ||
21662 | r12 = (target - 7) - .LTHUNKPCn + (.LTHUNKPCn + 8) | |
21663 | = target + 1. | |
21664 | ||
21665 | Note that we have "+ 1" because some versions of GNU ld | |
21666 | don't set the low bit of the result for R_ARM_REL32 | |
bf98ec6c PB |
21667 | relocations against thumb function symbols. |
21668 | On ARMv6M this is +4, not +8. */ | |
54b9e939 KH |
21669 | ASM_GENERATE_INTERNAL_LABEL (labelpc, "LTHUNKPC", labelno); |
21670 | assemble_name (file, labelpc); | |
21671 | fputs (":\n", file); | |
bf98ec6c PB |
21672 | if (TARGET_THUMB1_ONLY) |
21673 | { | |
21674 | /* This is 2 insns after the start of the thunk, so we know it | |
21675 | is 4-byte aligned. */ | |
21676 | fputs ("\tadd\tr3, pc, r3\n", file); | |
21677 | fputs ("\tmov r12, r3\n", file); | |
21678 | } | |
21679 | else | |
21680 | fputs ("\tadd\tr12, pc, r12\n", file); | |
54b9e939 | 21681 | } |
bf98ec6c PB |
21682 | else if (TARGET_THUMB1_ONLY) |
21683 | fputs ("\tmov r12, r3\n", file); | |
9b66ebb1 | 21684 | } |
bf98ec6c | 21685 | if (TARGET_THUMB1_ONLY) |
483ab821 | 21686 | { |
bf98ec6c PB |
21687 | if (mi_delta > 255) |
21688 | { | |
21689 | fputs ("\tldr\tr3, ", file); | |
21690 | assemble_name (file, label); | |
21691 | fputs ("+4\n", file); | |
21692 | asm_fprintf (file, "\t%s\t%r, %r, r3\n", | |
21693 | mi_op, this_regno, this_regno); | |
21694 | } | |
21695 | else if (mi_delta != 0) | |
21696 | { | |
21697 | asm_fprintf (file, "\t%s\t%r, %r, #%d\n", | |
21698 | mi_op, this_regno, this_regno, | |
21699 | mi_delta); | |
21700 | } | |
21701 | } | |
21702 | else | |
21703 | { | |
21704 | /* TODO: Use movw/movt for large constants when available. */ | |
21705 | while (mi_delta != 0) | |
21706 | { | |
21707 | if ((mi_delta & (3 << shift)) == 0) | |
21708 | shift += 2; | |
21709 | else | |
21710 | { | |
21711 | asm_fprintf (file, "\t%s\t%r, %r, #%d\n", | |
21712 | mi_op, this_regno, this_regno, | |
21713 | mi_delta & (0xff << shift)); | |
21714 | mi_delta &= ~(0xff << shift); | |
21715 | shift += 8; | |
21716 | } | |
21717 | } | |
483ab821 | 21718 | } |
5b3e6663 | 21719 | if (TARGET_THUMB1) |
9b66ebb1 | 21720 | { |
bf98ec6c PB |
21721 | if (TARGET_THUMB1_ONLY) |
21722 | fputs ("\tpop\t{r3}\n", file); | |
21723 | ||
9b66ebb1 PB |
21724 | fprintf (file, "\tbx\tr12\n"); |
21725 | ASM_OUTPUT_ALIGN (file, 2); | |
21726 | assemble_name (file, label); | |
21727 | fputs (":\n", file); | |
54b9e939 KH |
21728 | if (flag_pic) |
21729 | { | |
21730 | /* Output ".word .LTHUNKn-7-.LTHUNKPCn". */ | |
21731 | rtx tem = XEXP (DECL_RTL (function), 0); | |
21732 | tem = gen_rtx_PLUS (GET_MODE (tem), tem, GEN_INT (-7)); | |
21733 | tem = gen_rtx_MINUS (GET_MODE (tem), | |
21734 | tem, | |
21735 | gen_rtx_SYMBOL_REF (Pmode, | |
21736 | ggc_strdup (labelpc))); | |
21737 | assemble_integer (tem, 4, BITS_PER_WORD, 1); | |
21738 | } | |
21739 | else | |
21740 | /* Output ".word .LTHUNKn". */ | |
21741 | assemble_integer (XEXP (DECL_RTL (function), 0), 4, BITS_PER_WORD, 1); | |
bf98ec6c PB |
21742 | |
21743 | if (TARGET_THUMB1_ONLY && mi_delta > 255) | |
21744 | assemble_integer (GEN_INT(mi_delta), 4, BITS_PER_WORD, 1); | |
9b66ebb1 PB |
21745 | } |
21746 | else | |
21747 | { | |
21748 | fputs ("\tb\t", file); | |
21749 | assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0)); | |
21750 | if (NEED_PLT_RELOC) | |
21751 | fputs ("(PLT)", file); | |
21752 | fputc ('\n', file); | |
21753 | } | |
483ab821 | 21754 | } |
5a9335ef NC |
21755 | |
21756 | int | |
6f5f2481 | 21757 | arm_emit_vector_const (FILE *file, rtx x) |
5a9335ef NC |
21758 | { |
21759 | int i; | |
21760 | const char * pattern; | |
21761 | ||
e6d29d15 | 21762 | gcc_assert (GET_CODE (x) == CONST_VECTOR); |
5a9335ef NC |
21763 | |
21764 | switch (GET_MODE (x)) | |
21765 | { | |
21766 | case V2SImode: pattern = "%08x"; break; | |
21767 | case V4HImode: pattern = "%04x"; break; | |
21768 | case V8QImode: pattern = "%02x"; break; | |
e6d29d15 | 21769 | default: gcc_unreachable (); |
5a9335ef NC |
21770 | } |
21771 | ||
21772 | fprintf (file, "0x"); | |
21773 | for (i = CONST_VECTOR_NUNITS (x); i--;) | |
21774 | { | |
21775 | rtx element; | |
21776 | ||
21777 | element = CONST_VECTOR_ELT (x, i); | |
21778 | fprintf (file, pattern, INTVAL (element)); | |
21779 | } | |
21780 | ||
21781 | return 1; | |
21782 | } | |
21783 | ||
0fd8c3ad SL |
21784 | /* Emit a fp16 constant appropriately padded to occupy a 4-byte word. |
21785 | HFmode constant pool entries are actually loaded with ldr. */ | |
21786 | void | |
21787 | arm_emit_fp16_const (rtx c) | |
21788 | { | |
21789 | REAL_VALUE_TYPE r; | |
21790 | long bits; | |
21791 | ||
21792 | REAL_VALUE_FROM_CONST_DOUBLE (r, c); | |
21793 | bits = real_to_target (NULL, &r, HFmode); | |
21794 | if (WORDS_BIG_ENDIAN) | |
21795 | assemble_zeros (2); | |
21796 | assemble_integer (GEN_INT (bits), 2, BITS_PER_WORD, 1); | |
21797 | if (!WORDS_BIG_ENDIAN) | |
21798 | assemble_zeros (2); | |
21799 | } | |
21800 | ||
5a9335ef | 21801 | const char * |
6f5f2481 | 21802 | arm_output_load_gr (rtx *operands) |
5a9335ef NC |
21803 | { |
21804 | rtx reg; | |
21805 | rtx offset; | |
21806 | rtx wcgr; | |
21807 | rtx sum; | |
f676971a | 21808 | |
5a9335ef NC |
21809 | if (GET_CODE (operands [1]) != MEM |
21810 | || GET_CODE (sum = XEXP (operands [1], 0)) != PLUS | |
21811 | || GET_CODE (reg = XEXP (sum, 0)) != REG | |
21812 | || GET_CODE (offset = XEXP (sum, 1)) != CONST_INT | |
21813 | || ((INTVAL (offset) < 1024) && (INTVAL (offset) > -1024))) | |
21814 | return "wldrw%?\t%0, %1"; | |
f676971a EC |
21815 | |
21816 | /* Fix up an out-of-range load of a GR register. */ | |
5a9335ef NC |
21817 | output_asm_insn ("str%?\t%0, [sp, #-4]!\t@ Start of GR load expansion", & reg); |
21818 | wcgr = operands[0]; | |
21819 | operands[0] = reg; | |
21820 | output_asm_insn ("ldr%?\t%0, %1", operands); | |
21821 | ||
21822 | operands[0] = wcgr; | |
21823 | operands[1] = reg; | |
21824 | output_asm_insn ("tmcr%?\t%0, %1", operands); | |
21825 | output_asm_insn ("ldr%?\t%0, [sp], #4\t@ End of GR load expansion", & reg); | |
21826 | ||
21827 | return ""; | |
21828 | } | |
f9ba5949 | 21829 | |
1cc9f5f5 KH |
21830 | /* Worker function for TARGET_SETUP_INCOMING_VARARGS. |
21831 | ||
21832 | On the ARM, PRETEND_SIZE is set in order to have the prologue push the last | |
21833 | named arg and all anonymous args onto the stack. | |
21834 | XXX I know the prologue shouldn't be pushing registers, but it is faster | |
21835 | that way. */ | |
21836 | ||
21837 | static void | |
390b17c2 | 21838 | arm_setup_incoming_varargs (CUMULATIVE_ARGS *pcum, |
22ccaaee JJ |
21839 | enum machine_mode mode, |
21840 | tree type, | |
1cc9f5f5 KH |
21841 | int *pretend_size, |
21842 | int second_time ATTRIBUTE_UNUSED) | |
21843 | { | |
390b17c2 RE |
21844 | int nregs; |
21845 | ||
1cc9f5f5 | 21846 | cfun->machine->uses_anonymous_args = 1; |
390b17c2 RE |
21847 | if (pcum->pcs_variant <= ARM_PCS_AAPCS_LOCAL) |
21848 | { | |
21849 | nregs = pcum->aapcs_ncrn; | |
21850 | if ((nregs & 1) && arm_needs_doubleword_align (mode, type)) | |
21851 | nregs++; | |
21852 | } | |
21853 | else | |
21854 | nregs = pcum->nregs; | |
21855 | ||
22ccaaee JJ |
21856 | if (nregs < NUM_ARG_REGS) |
21857 | *pretend_size = (NUM_ARG_REGS - nregs) * UNITS_PER_WORD; | |
1cc9f5f5 | 21858 | } |
9b66ebb1 | 21859 | |
59b9a953 | 21860 | /* Return nonzero if the CONSUMER instruction (a store) does not need |
9b66ebb1 PB |
21861 | PRODUCER's value to calculate the address. */ |
21862 | ||
21863 | int | |
21864 | arm_no_early_store_addr_dep (rtx producer, rtx consumer) | |
21865 | { | |
21866 | rtx value = PATTERN (producer); | |
21867 | rtx addr = PATTERN (consumer); | |
21868 | ||
21869 | if (GET_CODE (value) == COND_EXEC) | |
21870 | value = COND_EXEC_CODE (value); | |
21871 | if (GET_CODE (value) == PARALLEL) | |
21872 | value = XVECEXP (value, 0, 0); | |
21873 | value = XEXP (value, 0); | |
21874 | if (GET_CODE (addr) == COND_EXEC) | |
21875 | addr = COND_EXEC_CODE (addr); | |
21876 | if (GET_CODE (addr) == PARALLEL) | |
21877 | addr = XVECEXP (addr, 0, 0); | |
21878 | addr = XEXP (addr, 0); | |
f676971a | 21879 | |
9b66ebb1 PB |
21880 | return !reg_overlap_mentioned_p (value, addr); |
21881 | } | |
21882 | ||
47d8f18d JZ |
21883 | /* Return nonzero if the CONSUMER instruction (a store) does need |
21884 | PRODUCER's value to calculate the address. */ | |
21885 | ||
21886 | int | |
21887 | arm_early_store_addr_dep (rtx producer, rtx consumer) | |
21888 | { | |
21889 | return !arm_no_early_store_addr_dep (producer, consumer); | |
21890 | } | |
21891 | ||
21892 | /* Return nonzero if the CONSUMER instruction (a load) does need | |
21893 | PRODUCER's value to calculate the address. */ | |
21894 | ||
21895 | int | |
21896 | arm_early_load_addr_dep (rtx producer, rtx consumer) | |
21897 | { | |
21898 | rtx value = PATTERN (producer); | |
21899 | rtx addr = PATTERN (consumer); | |
21900 | ||
21901 | if (GET_CODE (value) == COND_EXEC) | |
21902 | value = COND_EXEC_CODE (value); | |
21903 | if (GET_CODE (value) == PARALLEL) | |
21904 | value = XVECEXP (value, 0, 0); | |
21905 | value = XEXP (value, 0); | |
21906 | if (GET_CODE (addr) == COND_EXEC) | |
21907 | addr = COND_EXEC_CODE (addr); | |
21908 | if (GET_CODE (addr) == PARALLEL) | |
21909 | addr = XVECEXP (addr, 0, 0); | |
21910 | addr = XEXP (addr, 1); | |
21911 | ||
21912 | return reg_overlap_mentioned_p (value, addr); | |
21913 | } | |
21914 | ||
59b9a953 | 21915 | /* Return nonzero if the CONSUMER instruction (an ALU op) does not |
9b66ebb1 PB |
21916 | have an early register shift value or amount dependency on the |
21917 | result of PRODUCER. */ | |
21918 | ||
21919 | int | |
21920 | arm_no_early_alu_shift_dep (rtx producer, rtx consumer) | |
21921 | { | |
21922 | rtx value = PATTERN (producer); | |
21923 | rtx op = PATTERN (consumer); | |
21924 | rtx early_op; | |
21925 | ||
21926 | if (GET_CODE (value) == COND_EXEC) | |
21927 | value = COND_EXEC_CODE (value); | |
21928 | if (GET_CODE (value) == PARALLEL) | |
21929 | value = XVECEXP (value, 0, 0); | |
21930 | value = XEXP (value, 0); | |
21931 | if (GET_CODE (op) == COND_EXEC) | |
21932 | op = COND_EXEC_CODE (op); | |
21933 | if (GET_CODE (op) == PARALLEL) | |
21934 | op = XVECEXP (op, 0, 0); | |
21935 | op = XEXP (op, 1); | |
f676971a | 21936 | |
9b66ebb1 PB |
21937 | early_op = XEXP (op, 0); |
21938 | /* This is either an actual independent shift, or a shift applied to | |
21939 | the first operand of another operation. We want the whole shift | |
21940 | operation. */ | |
21941 | if (GET_CODE (early_op) == REG) | |
21942 | early_op = op; | |
21943 | ||
21944 | return !reg_overlap_mentioned_p (value, early_op); | |
21945 | } | |
21946 | ||
59b9a953 | 21947 | /* Return nonzero if the CONSUMER instruction (an ALU op) does not |
9b66ebb1 PB |
21948 | have an early register shift value dependency on the result of |
21949 | PRODUCER. */ | |
21950 | ||
21951 | int | |
21952 | arm_no_early_alu_shift_value_dep (rtx producer, rtx consumer) | |
21953 | { | |
21954 | rtx value = PATTERN (producer); | |
21955 | rtx op = PATTERN (consumer); | |
21956 | rtx early_op; | |
21957 | ||
21958 | if (GET_CODE (value) == COND_EXEC) | |
21959 | value = COND_EXEC_CODE (value); | |
21960 | if (GET_CODE (value) == PARALLEL) | |
21961 | value = XVECEXP (value, 0, 0); | |
21962 | value = XEXP (value, 0); | |
21963 | if (GET_CODE (op) == COND_EXEC) | |
21964 | op = COND_EXEC_CODE (op); | |
21965 | if (GET_CODE (op) == PARALLEL) | |
21966 | op = XVECEXP (op, 0, 0); | |
21967 | op = XEXP (op, 1); | |
f676971a | 21968 | |
9b66ebb1 PB |
21969 | early_op = XEXP (op, 0); |
21970 | ||
21971 | /* This is either an actual independent shift, or a shift applied to | |
21972 | the first operand of another operation. We want the value being | |
21973 | shifted, in either case. */ | |
21974 | if (GET_CODE (early_op) != REG) | |
21975 | early_op = XEXP (early_op, 0); | |
f676971a | 21976 | |
9b66ebb1 PB |
21977 | return !reg_overlap_mentioned_p (value, early_op); |
21978 | } | |
21979 | ||
59b9a953 | 21980 | /* Return nonzero if the CONSUMER (a mul or mac op) does not |
9b66ebb1 PB |
21981 | have an early register mult dependency on the result of |
21982 | PRODUCER. */ | |
21983 | ||
21984 | int | |
21985 | arm_no_early_mul_dep (rtx producer, rtx consumer) | |
21986 | { | |
21987 | rtx value = PATTERN (producer); | |
21988 | rtx op = PATTERN (consumer); | |
21989 | ||
21990 | if (GET_CODE (value) == COND_EXEC) | |
21991 | value = COND_EXEC_CODE (value); | |
21992 | if (GET_CODE (value) == PARALLEL) | |
21993 | value = XVECEXP (value, 0, 0); | |
21994 | value = XEXP (value, 0); | |
21995 | if (GET_CODE (op) == COND_EXEC) | |
21996 | op = COND_EXEC_CODE (op); | |
21997 | if (GET_CODE (op) == PARALLEL) | |
21998 | op = XVECEXP (op, 0, 0); | |
21999 | op = XEXP (op, 1); | |
f676971a | 22000 | |
756f763b PB |
22001 | if (GET_CODE (op) == PLUS || GET_CODE (op) == MINUS) |
22002 | { | |
22003 | if (GET_CODE (XEXP (op, 0)) == MULT) | |
22004 | return !reg_overlap_mentioned_p (value, XEXP (op, 0)); | |
22005 | else | |
22006 | return !reg_overlap_mentioned_p (value, XEXP (op, 1)); | |
22007 | } | |
22008 | ||
22009 | return 0; | |
9b66ebb1 PB |
22010 | } |
22011 | ||
70301b45 PB |
22012 | /* We can't rely on the caller doing the proper promotion when |
22013 | using APCS or ATPCS. */ | |
22014 | ||
22015 | static bool | |
586de218 | 22016 | arm_promote_prototypes (const_tree t ATTRIBUTE_UNUSED) |
70301b45 | 22017 | { |
b6685939 | 22018 | return !TARGET_AAPCS_BASED; |
70301b45 PB |
22019 | } |
22020 | ||
cde0f3fd PB |
22021 | static enum machine_mode |
22022 | arm_promote_function_mode (const_tree type ATTRIBUTE_UNUSED, | |
22023 | enum machine_mode mode, | |
22024 | int *punsignedp ATTRIBUTE_UNUSED, | |
22025 | const_tree fntype ATTRIBUTE_UNUSED, | |
22026 | int for_return ATTRIBUTE_UNUSED) | |
22027 | { | |
22028 | if (GET_MODE_CLASS (mode) == MODE_INT | |
22029 | && GET_MODE_SIZE (mode) < 4) | |
22030 | return SImode; | |
22031 | ||
22032 | return mode; | |
22033 | } | |
6b045785 PB |
22034 | |
22035 | /* AAPCS based ABIs use short enums by default. */ | |
22036 | ||
22037 | static bool | |
22038 | arm_default_short_enums (void) | |
22039 | { | |
077fc835 | 22040 | return TARGET_AAPCS_BASED && arm_abi != ARM_ABI_AAPCS_LINUX; |
6b045785 | 22041 | } |
13c1cd82 PB |
22042 | |
22043 | ||
22044 | /* AAPCS requires that anonymous bitfields affect structure alignment. */ | |
22045 | ||
22046 | static bool | |
22047 | arm_align_anon_bitfield (void) | |
22048 | { | |
22049 | return TARGET_AAPCS_BASED; | |
22050 | } | |
4185ae53 PB |
22051 | |
22052 | ||
22053 | /* The generic C++ ABI says 64-bit (long long). The EABI says 32-bit. */ | |
22054 | ||
22055 | static tree | |
22056 | arm_cxx_guard_type (void) | |
22057 | { | |
22058 | return TARGET_AAPCS_BASED ? integer_type_node : long_long_integer_type_node; | |
22059 | } | |
22060 | ||
c956e102 MS |
22061 | /* Return non-zero if the consumer (a multiply-accumulate instruction) |
22062 | has an accumulator dependency on the result of the producer (a | |
22063 | multiplication instruction) and no other dependency on that result. */ | |
22064 | int | |
22065 | arm_mac_accumulator_is_mul_result (rtx producer, rtx consumer) | |
22066 | { | |
22067 | rtx mul = PATTERN (producer); | |
22068 | rtx mac = PATTERN (consumer); | |
22069 | rtx mul_result; | |
22070 | rtx mac_op0, mac_op1, mac_acc; | |
22071 | ||
22072 | if (GET_CODE (mul) == COND_EXEC) | |
22073 | mul = COND_EXEC_CODE (mul); | |
22074 | if (GET_CODE (mac) == COND_EXEC) | |
22075 | mac = COND_EXEC_CODE (mac); | |
22076 | ||
22077 | /* Check that mul is of the form (set (...) (mult ...)) | |
22078 | and mla is of the form (set (...) (plus (mult ...) (...))). */ | |
22079 | if ((GET_CODE (mul) != SET || GET_CODE (XEXP (mul, 1)) != MULT) | |
22080 | || (GET_CODE (mac) != SET || GET_CODE (XEXP (mac, 1)) != PLUS | |
22081 | || GET_CODE (XEXP (XEXP (mac, 1), 0)) != MULT)) | |
22082 | return 0; | |
22083 | ||
22084 | mul_result = XEXP (mul, 0); | |
22085 | mac_op0 = XEXP (XEXP (XEXP (mac, 1), 0), 0); | |
22086 | mac_op1 = XEXP (XEXP (XEXP (mac, 1), 0), 1); | |
22087 | mac_acc = XEXP (XEXP (mac, 1), 1); | |
22088 | ||
22089 | return (reg_overlap_mentioned_p (mul_result, mac_acc) | |
22090 | && !reg_overlap_mentioned_p (mul_result, mac_op0) | |
22091 | && !reg_overlap_mentioned_p (mul_result, mac_op1)); | |
22092 | } | |
22093 | ||
4185ae53 | 22094 | |
0fa2e4df | 22095 | /* The EABI says test the least significant bit of a guard variable. */ |
4185ae53 PB |
22096 | |
22097 | static bool | |
22098 | arm_cxx_guard_mask_bit (void) | |
22099 | { | |
22100 | return TARGET_AAPCS_BASED; | |
22101 | } | |
46e995e0 PB |
22102 | |
22103 | ||
22104 | /* The EABI specifies that all array cookies are 8 bytes long. */ | |
22105 | ||
22106 | static tree | |
22107 | arm_get_cookie_size (tree type) | |
22108 | { | |
22109 | tree size; | |
22110 | ||
22111 | if (!TARGET_AAPCS_BASED) | |
22112 | return default_cxx_get_cookie_size (type); | |
22113 | ||
7d60be94 | 22114 | size = build_int_cst (sizetype, 8); |
46e995e0 PB |
22115 | return size; |
22116 | } | |
22117 | ||
22118 | ||
22119 | /* The EABI says that array cookies should also contain the element size. */ | |
22120 | ||
22121 | static bool | |
22122 | arm_cookie_has_size (void) | |
22123 | { | |
22124 | return TARGET_AAPCS_BASED; | |
22125 | } | |
44d10c10 PB |
22126 | |
22127 | ||
22128 | /* The EABI says constructors and destructors should return a pointer to | |
22129 | the object constructed/destroyed. */ | |
22130 | ||
22131 | static bool | |
22132 | arm_cxx_cdtor_returns_this (void) | |
22133 | { | |
22134 | return TARGET_AAPCS_BASED; | |
22135 | } | |
c9ca9b88 | 22136 | |
505970fc MM |
22137 | /* The EABI says that an inline function may never be the key |
22138 | method. */ | |
22139 | ||
22140 | static bool | |
22141 | arm_cxx_key_method_may_be_inline (void) | |
22142 | { | |
22143 | return !TARGET_AAPCS_BASED; | |
22144 | } | |
22145 | ||
1e731102 MM |
22146 | static void |
22147 | arm_cxx_determine_class_data_visibility (tree decl) | |
22148 | { | |
711b2998 JB |
22149 | if (!TARGET_AAPCS_BASED |
22150 | || !TARGET_DLLIMPORT_DECL_ATTRIBUTES) | |
1e731102 | 22151 | return; |
505970fc | 22152 | |
1e731102 MM |
22153 | /* In general, \S 3.2.5.5 of the ARM EABI requires that class data |
22154 | is exported. However, on systems without dynamic vague linkage, | |
22155 | \S 3.2.5.6 says that COMDAT class data has hidden linkage. */ | |
22156 | if (!TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P && DECL_COMDAT (decl)) | |
22157 | DECL_VISIBILITY (decl) = VISIBILITY_HIDDEN; | |
22158 | else | |
22159 | DECL_VISIBILITY (decl) = VISIBILITY_DEFAULT; | |
22160 | DECL_VISIBILITY_SPECIFIED (decl) = 1; | |
22161 | } | |
e0b92319 | 22162 | |
505970fc | 22163 | static bool |
1e731102 | 22164 | arm_cxx_class_data_always_comdat (void) |
505970fc | 22165 | { |
1e731102 MM |
22166 | /* \S 3.2.5.4 of the ARM C++ ABI says that class data only have |
22167 | vague linkage if the class has no key function. */ | |
22168 | return !TARGET_AAPCS_BASED; | |
505970fc | 22169 | } |
c9ca9b88 | 22170 | |
9f62c3e3 PB |
22171 | |
22172 | /* The EABI says __aeabi_atexit should be used to register static | |
22173 | destructors. */ | |
22174 | ||
22175 | static bool | |
22176 | arm_cxx_use_aeabi_atexit (void) | |
22177 | { | |
22178 | return TARGET_AAPCS_BASED; | |
22179 | } | |
22180 | ||
22181 | ||
c9ca9b88 PB |
22182 | void |
22183 | arm_set_return_address (rtx source, rtx scratch) | |
22184 | { | |
22185 | arm_stack_offsets *offsets; | |
22186 | HOST_WIDE_INT delta; | |
22187 | rtx addr; | |
22188 | unsigned long saved_regs; | |
22189 | ||
954954d1 PB |
22190 | offsets = arm_get_frame_offsets (); |
22191 | saved_regs = offsets->saved_regs_mask; | |
c9ca9b88 PB |
22192 | |
22193 | if ((saved_regs & (1 << LR_REGNUM)) == 0) | |
22194 | emit_move_insn (gen_rtx_REG (Pmode, LR_REGNUM), source); | |
22195 | else | |
22196 | { | |
22197 | if (frame_pointer_needed) | |
22198 | addr = plus_constant(hard_frame_pointer_rtx, -4); | |
22199 | else | |
22200 | { | |
22201 | /* LR will be the first saved register. */ | |
c9ca9b88 PB |
22202 | delta = offsets->outgoing_args - (offsets->frame + 4); |
22203 | ||
f676971a | 22204 | |
c9ca9b88 PB |
22205 | if (delta >= 4096) |
22206 | { | |
22207 | emit_insn (gen_addsi3 (scratch, stack_pointer_rtx, | |
22208 | GEN_INT (delta & ~4095))); | |
22209 | addr = scratch; | |
22210 | delta &= 4095; | |
22211 | } | |
22212 | else | |
22213 | addr = stack_pointer_rtx; | |
22214 | ||
22215 | addr = plus_constant (addr, delta); | |
22216 | } | |
31fa16b6 | 22217 | emit_move_insn (gen_frame_mem (Pmode, addr), source); |
c9ca9b88 PB |
22218 | } |
22219 | } | |
22220 | ||
22221 | ||
22222 | void | |
22223 | thumb_set_return_address (rtx source, rtx scratch) | |
22224 | { | |
22225 | arm_stack_offsets *offsets; | |
c9ca9b88 | 22226 | HOST_WIDE_INT delta; |
5b3e6663 | 22227 | HOST_WIDE_INT limit; |
c9ca9b88 PB |
22228 | int reg; |
22229 | rtx addr; | |
57934c39 | 22230 | unsigned long mask; |
c9ca9b88 | 22231 | |
c41c1387 | 22232 | emit_use (source); |
c9ca9b88 | 22233 | |
954954d1 PB |
22234 | offsets = arm_get_frame_offsets (); |
22235 | mask = offsets->saved_regs_mask; | |
57934c39 | 22236 | if (mask & (1 << LR_REGNUM)) |
c9ca9b88 | 22237 | { |
5b3e6663 | 22238 | limit = 1024; |
c9ca9b88 PB |
22239 | /* Find the saved regs. */ |
22240 | if (frame_pointer_needed) | |
22241 | { | |
22242 | delta = offsets->soft_frame - offsets->saved_args; | |
22243 | reg = THUMB_HARD_FRAME_POINTER_REGNUM; | |
5b3e6663 PB |
22244 | if (TARGET_THUMB1) |
22245 | limit = 128; | |
c9ca9b88 PB |
22246 | } |
22247 | else | |
22248 | { | |
22249 | delta = offsets->outgoing_args - offsets->saved_args; | |
22250 | reg = SP_REGNUM; | |
22251 | } | |
22252 | /* Allow for the stack frame. */ | |
5b3e6663 | 22253 | if (TARGET_THUMB1 && TARGET_BACKTRACE) |
c9ca9b88 PB |
22254 | delta -= 16; |
22255 | /* The link register is always the first saved register. */ | |
22256 | delta -= 4; | |
f676971a | 22257 | |
c9ca9b88 PB |
22258 | /* Construct the address. */ |
22259 | addr = gen_rtx_REG (SImode, reg); | |
5b3e6663 | 22260 | if (delta > limit) |
c9ca9b88 PB |
22261 | { |
22262 | emit_insn (gen_movsi (scratch, GEN_INT (delta))); | |
22263 | emit_insn (gen_addsi3 (scratch, scratch, stack_pointer_rtx)); | |
22264 | addr = scratch; | |
22265 | } | |
22266 | else | |
22267 | addr = plus_constant (addr, delta); | |
22268 | ||
31fa16b6 | 22269 | emit_move_insn (gen_frame_mem (Pmode, addr), source); |
c9ca9b88 PB |
22270 | } |
22271 | else | |
22272 | emit_move_insn (gen_rtx_REG (Pmode, LR_REGNUM), source); | |
22273 | } | |
22274 | ||
f676971a EC |
22275 | /* Implements target hook vector_mode_supported_p. */ |
22276 | bool | |
22277 | arm_vector_mode_supported_p (enum machine_mode mode) | |
22278 | { | |
88f77cba JB |
22279 | /* Neon also supports V2SImode, etc. listed in the clause below. */ |
22280 | if (TARGET_NEON && (mode == V2SFmode || mode == V4SImode || mode == V8HImode | |
22281 | || mode == V16QImode || mode == V4SFmode || mode == V2DImode)) | |
22282 | return true; | |
22283 | ||
390b17c2 RE |
22284 | if ((TARGET_NEON || TARGET_IWMMXT) |
22285 | && ((mode == V2SImode) | |
22286 | || (mode == V4HImode) | |
22287 | || (mode == V8QImode))) | |
f676971a EC |
22288 | return true; |
22289 | ||
22290 | return false; | |
22291 | } | |
273a2526 | 22292 | |
26983c22 L |
22293 | /* Use the option -mvectorize-with-neon-quad to override the use of doubleword |
22294 | registers when autovectorizing for Neon, at least until multiple vector | |
22295 | widths are supported properly by the middle-end. */ | |
22296 | ||
cc4b5170 RG |
22297 | static enum machine_mode |
22298 | arm_preferred_simd_mode (enum machine_mode mode) | |
26983c22 | 22299 | { |
cc4b5170 RG |
22300 | if (TARGET_NEON) |
22301 | switch (mode) | |
22302 | { | |
22303 | case SFmode: | |
22304 | return TARGET_NEON_VECTORIZE_QUAD ? V4SFmode : V2SFmode; | |
22305 | case SImode: | |
22306 | return TARGET_NEON_VECTORIZE_QUAD ? V4SImode : V2SImode; | |
22307 | case HImode: | |
22308 | return TARGET_NEON_VECTORIZE_QUAD ? V8HImode : V4HImode; | |
22309 | case QImode: | |
22310 | return TARGET_NEON_VECTORIZE_QUAD ? V16QImode : V8QImode; | |
22311 | case DImode: | |
22312 | if (TARGET_NEON_VECTORIZE_QUAD) | |
22313 | return V2DImode; | |
22314 | break; | |
22315 | ||
22316 | default:; | |
22317 | } | |
22318 | ||
22319 | if (TARGET_REALLY_IWMMXT) | |
22320 | switch (mode) | |
22321 | { | |
22322 | case SImode: | |
22323 | return V2SImode; | |
22324 | case HImode: | |
22325 | return V4HImode; | |
22326 | case QImode: | |
22327 | return V8QImode; | |
22328 | ||
22329 | default:; | |
22330 | } | |
22331 | ||
22332 | return word_mode; | |
26983c22 L |
22333 | } |
22334 | ||
d163e655 AS |
22335 | /* Implement TARGET_CLASS_LIKELY_SPILLED_P. |
22336 | ||
22337 | We need to define this for LO_REGS on thumb. Otherwise we can end up | |
22338 | using r0-r4 for function arguments, r7 for the stack frame and don't | |
22339 | have enough left over to do doubleword arithmetic. */ | |
22340 | ||
22341 | static bool | |
22342 | arm_class_likely_spilled_p (reg_class_t rclass) | |
22343 | { | |
22344 | if ((TARGET_THUMB && rclass == LO_REGS) | |
22345 | || rclass == CC_REG) | |
22346 | return true; | |
22347 | ||
22348 | return false; | |
22349 | } | |
22350 | ||
42db504c SB |
22351 | /* Implements target hook small_register_classes_for_mode_p. */ |
22352 | bool | |
22353 | arm_small_register_classes_for_mode_p (enum machine_mode mode ATTRIBUTE_UNUSED) | |
22354 | { | |
22355 | return TARGET_THUMB1; | |
22356 | } | |
22357 | ||
273a2526 RS |
22358 | /* Implement TARGET_SHIFT_TRUNCATION_MASK. SImode shifts use normal |
22359 | ARM insns and therefore guarantee that the shift count is modulo 256. | |
22360 | DImode shifts (those implemented by lib1funcs.asm or by optabs.c) | |
22361 | guarantee no particular behavior for out-of-range counts. */ | |
22362 | ||
22363 | static unsigned HOST_WIDE_INT | |
22364 | arm_shift_truncation_mask (enum machine_mode mode) | |
22365 | { | |
22366 | return mode == SImode ? 255 : 0; | |
22367 | } | |
2fa330b2 PB |
22368 | |
22369 | ||
22370 | /* Map internal gcc register numbers to DWARF2 register numbers. */ | |
22371 | ||
22372 | unsigned int | |
22373 | arm_dbx_register_number (unsigned int regno) | |
22374 | { | |
22375 | if (regno < 16) | |
22376 | return regno; | |
22377 | ||
22378 | /* TODO: Legacy targets output FPA regs as registers 16-23 for backwards | |
22379 | compatibility. The EABI defines them as registers 96-103. */ | |
22380 | if (IS_FPA_REGNUM (regno)) | |
22381 | return (TARGET_AAPCS_BASED ? 96 : 16) + regno - FIRST_FPA_REGNUM; | |
22382 | ||
22383 | if (IS_VFP_REGNUM (regno)) | |
854b8a40 JB |
22384 | { |
22385 | /* See comment in arm_dwarf_register_span. */ | |
22386 | if (VFP_REGNO_OK_FOR_SINGLE (regno)) | |
22387 | return 64 + regno - FIRST_VFP_REGNUM; | |
22388 | else | |
22389 | return 256 + (regno - FIRST_VFP_REGNUM) / 2; | |
22390 | } | |
2fa330b2 PB |
22391 | |
22392 | if (IS_IWMMXT_GR_REGNUM (regno)) | |
22393 | return 104 + regno - FIRST_IWMMXT_GR_REGNUM; | |
22394 | ||
22395 | if (IS_IWMMXT_REGNUM (regno)) | |
22396 | return 112 + regno - FIRST_IWMMXT_REGNUM; | |
22397 | ||
e6d29d15 | 22398 | gcc_unreachable (); |
2fa330b2 PB |
22399 | } |
22400 | ||
854b8a40 JB |
22401 | /* Dwarf models VFPv3 registers as 32 64-bit registers. |
22402 | GCC models tham as 64 32-bit registers, so we need to describe this to | |
22403 | the DWARF generation code. Other registers can use the default. */ | |
22404 | static rtx | |
22405 | arm_dwarf_register_span (rtx rtl) | |
22406 | { | |
22407 | unsigned regno; | |
22408 | int nregs; | |
22409 | int i; | |
22410 | rtx p; | |
22411 | ||
22412 | regno = REGNO (rtl); | |
22413 | if (!IS_VFP_REGNUM (regno)) | |
22414 | return NULL_RTX; | |
22415 | ||
22416 | /* XXX FIXME: The EABI defines two VFP register ranges: | |
22417 | 64-95: Legacy VFPv2 numbering for S0-S31 (obsolescent) | |
22418 | 256-287: D0-D31 | |
22419 | The recommended encoding for S0-S31 is a DW_OP_bit_piece of the | |
22420 | corresponding D register. Until GDB supports this, we shall use the | |
22421 | legacy encodings. We also use these encodings for D0-D15 for | |
22422 | compatibility with older debuggers. */ | |
22423 | if (VFP_REGNO_OK_FOR_SINGLE (regno)) | |
22424 | return NULL_RTX; | |
22425 | ||
22426 | nregs = GET_MODE_SIZE (GET_MODE (rtl)) / 8; | |
22427 | p = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nregs)); | |
22428 | regno = (regno - FIRST_VFP_REGNUM) / 2; | |
22429 | for (i = 0; i < nregs; i++) | |
22430 | XVECEXP (p, 0, i) = gen_rtx_REG (DImode, 256 + regno + i); | |
22431 | ||
22432 | return p; | |
22433 | } | |
617a1b71 | 22434 | |
f0a0390e | 22435 | #if ARM_UNWIND_INFO |
5b3e6663 PB |
22436 | /* Emit unwind directives for a store-multiple instruction or stack pointer |
22437 | push during alignment. | |
22438 | These should only ever be generated by the function prologue code, so | |
22439 | expect them to have a particular form. */ | |
617a1b71 PB |
22440 | |
22441 | static void | |
5b3e6663 | 22442 | arm_unwind_emit_sequence (FILE * asm_out_file, rtx p) |
617a1b71 PB |
22443 | { |
22444 | int i; | |
22445 | HOST_WIDE_INT offset; | |
22446 | HOST_WIDE_INT nregs; | |
22447 | int reg_size; | |
22448 | unsigned reg; | |
22449 | unsigned lastreg; | |
22450 | rtx e; | |
22451 | ||
617a1b71 | 22452 | e = XVECEXP (p, 0, 0); |
5b3e6663 PB |
22453 | if (GET_CODE (e) != SET) |
22454 | abort (); | |
22455 | ||
22456 | /* First insn will adjust the stack pointer. */ | |
617a1b71 PB |
22457 | if (GET_CODE (e) != SET |
22458 | || GET_CODE (XEXP (e, 0)) != REG | |
22459 | || REGNO (XEXP (e, 0)) != SP_REGNUM | |
22460 | || GET_CODE (XEXP (e, 1)) != PLUS) | |
22461 | abort (); | |
22462 | ||
22463 | offset = -INTVAL (XEXP (XEXP (e, 1), 1)); | |
22464 | nregs = XVECLEN (p, 0) - 1; | |
22465 | ||
22466 | reg = REGNO (XEXP (XVECEXP (p, 0, 1), 1)); | |
22467 | if (reg < 16) | |
22468 | { | |
22469 | /* The function prologue may also push pc, but not annotate it as it is | |
569b7f6a | 22470 | never restored. We turn this into a stack pointer adjustment. */ |
617a1b71 PB |
22471 | if (nregs * 4 == offset - 4) |
22472 | { | |
22473 | fprintf (asm_out_file, "\t.pad #4\n"); | |
22474 | offset -= 4; | |
22475 | } | |
22476 | reg_size = 4; | |
8edfc4cc | 22477 | fprintf (asm_out_file, "\t.save {"); |
617a1b71 PB |
22478 | } |
22479 | else if (IS_VFP_REGNUM (reg)) | |
22480 | { | |
617a1b71 | 22481 | reg_size = 8; |
8edfc4cc | 22482 | fprintf (asm_out_file, "\t.vsave {"); |
617a1b71 PB |
22483 | } |
22484 | else if (reg >= FIRST_FPA_REGNUM && reg <= LAST_FPA_REGNUM) | |
22485 | { | |
22486 | /* FPA registers are done differently. */ | |
ea40ba9c | 22487 | asm_fprintf (asm_out_file, "\t.save %r, %wd\n", reg, nregs); |
617a1b71 PB |
22488 | return; |
22489 | } | |
22490 | else | |
22491 | /* Unknown register type. */ | |
22492 | abort (); | |
22493 | ||
22494 | /* If the stack increment doesn't match the size of the saved registers, | |
22495 | something has gone horribly wrong. */ | |
22496 | if (offset != nregs * reg_size) | |
22497 | abort (); | |
22498 | ||
617a1b71 PB |
22499 | offset = 0; |
22500 | lastreg = 0; | |
22501 | /* The remaining insns will describe the stores. */ | |
22502 | for (i = 1; i <= nregs; i++) | |
22503 | { | |
22504 | /* Expect (set (mem <addr>) (reg)). | |
22505 | Where <addr> is (reg:SP) or (plus (reg:SP) (const_int)). */ | |
22506 | e = XVECEXP (p, 0, i); | |
22507 | if (GET_CODE (e) != SET | |
22508 | || GET_CODE (XEXP (e, 0)) != MEM | |
22509 | || GET_CODE (XEXP (e, 1)) != REG) | |
22510 | abort (); | |
e0b92319 | 22511 | |
617a1b71 PB |
22512 | reg = REGNO (XEXP (e, 1)); |
22513 | if (reg < lastreg) | |
22514 | abort (); | |
e0b92319 | 22515 | |
617a1b71 PB |
22516 | if (i != 1) |
22517 | fprintf (asm_out_file, ", "); | |
22518 | /* We can't use %r for vfp because we need to use the | |
22519 | double precision register names. */ | |
22520 | if (IS_VFP_REGNUM (reg)) | |
22521 | asm_fprintf (asm_out_file, "d%d", (reg - FIRST_VFP_REGNUM) / 2); | |
22522 | else | |
22523 | asm_fprintf (asm_out_file, "%r", reg); | |
22524 | ||
22525 | #ifdef ENABLE_CHECKING | |
22526 | /* Check that the addresses are consecutive. */ | |
22527 | e = XEXP (XEXP (e, 0), 0); | |
22528 | if (GET_CODE (e) == PLUS) | |
22529 | { | |
22530 | offset += reg_size; | |
22531 | if (GET_CODE (XEXP (e, 0)) != REG | |
22532 | || REGNO (XEXP (e, 0)) != SP_REGNUM | |
22533 | || GET_CODE (XEXP (e, 1)) != CONST_INT | |
22534 | || offset != INTVAL (XEXP (e, 1))) | |
22535 | abort (); | |
22536 | } | |
22537 | else if (i != 1 | |
22538 | || GET_CODE (e) != REG | |
22539 | || REGNO (e) != SP_REGNUM) | |
22540 | abort (); | |
22541 | #endif | |
22542 | } | |
22543 | fprintf (asm_out_file, "}\n"); | |
22544 | } | |
22545 | ||
22546 | /* Emit unwind directives for a SET. */ | |
22547 | ||
22548 | static void | |
22549 | arm_unwind_emit_set (FILE * asm_out_file, rtx p) | |
22550 | { | |
22551 | rtx e0; | |
22552 | rtx e1; | |
5b3e6663 | 22553 | unsigned reg; |
617a1b71 PB |
22554 | |
22555 | e0 = XEXP (p, 0); | |
22556 | e1 = XEXP (p, 1); | |
22557 | switch (GET_CODE (e0)) | |
22558 | { | |
22559 | case MEM: | |
22560 | /* Pushing a single register. */ | |
22561 | if (GET_CODE (XEXP (e0, 0)) != PRE_DEC | |
22562 | || GET_CODE (XEXP (XEXP (e0, 0), 0)) != REG | |
22563 | || REGNO (XEXP (XEXP (e0, 0), 0)) != SP_REGNUM) | |
22564 | abort (); | |
22565 | ||
22566 | asm_fprintf (asm_out_file, "\t.save "); | |
22567 | if (IS_VFP_REGNUM (REGNO (e1))) | |
22568 | asm_fprintf(asm_out_file, "{d%d}\n", | |
22569 | (REGNO (e1) - FIRST_VFP_REGNUM) / 2); | |
22570 | else | |
22571 | asm_fprintf(asm_out_file, "{%r}\n", REGNO (e1)); | |
22572 | break; | |
22573 | ||
22574 | case REG: | |
22575 | if (REGNO (e0) == SP_REGNUM) | |
22576 | { | |
22577 | /* A stack increment. */ | |
22578 | if (GET_CODE (e1) != PLUS | |
22579 | || GET_CODE (XEXP (e1, 0)) != REG | |
22580 | || REGNO (XEXP (e1, 0)) != SP_REGNUM | |
22581 | || GET_CODE (XEXP (e1, 1)) != CONST_INT) | |
22582 | abort (); | |
22583 | ||
ea40ba9c | 22584 | asm_fprintf (asm_out_file, "\t.pad #%wd\n", |
617a1b71 PB |
22585 | -INTVAL (XEXP (e1, 1))); |
22586 | } | |
22587 | else if (REGNO (e0) == HARD_FRAME_POINTER_REGNUM) | |
22588 | { | |
22589 | HOST_WIDE_INT offset; | |
e0b92319 | 22590 | |
617a1b71 PB |
22591 | if (GET_CODE (e1) == PLUS) |
22592 | { | |
22593 | if (GET_CODE (XEXP (e1, 0)) != REG | |
22594 | || GET_CODE (XEXP (e1, 1)) != CONST_INT) | |
22595 | abort (); | |
22596 | reg = REGNO (XEXP (e1, 0)); | |
22597 | offset = INTVAL (XEXP (e1, 1)); | |
ea40ba9c | 22598 | asm_fprintf (asm_out_file, "\t.setfp %r, %r, #%wd\n", |
617a1b71 | 22599 | HARD_FRAME_POINTER_REGNUM, reg, |
80d56d04 | 22600 | offset); |
617a1b71 PB |
22601 | } |
22602 | else if (GET_CODE (e1) == REG) | |
22603 | { | |
22604 | reg = REGNO (e1); | |
22605 | asm_fprintf (asm_out_file, "\t.setfp %r, %r\n", | |
22606 | HARD_FRAME_POINTER_REGNUM, reg); | |
22607 | } | |
22608 | else | |
22609 | abort (); | |
22610 | } | |
22611 | else if (GET_CODE (e1) == REG && REGNO (e1) == SP_REGNUM) | |
22612 | { | |
22613 | /* Move from sp to reg. */ | |
22614 | asm_fprintf (asm_out_file, "\t.movsp %r\n", REGNO (e0)); | |
22615 | } | |
758ed9b2 PB |
22616 | else if (GET_CODE (e1) == PLUS |
22617 | && GET_CODE (XEXP (e1, 0)) == REG | |
22618 | && REGNO (XEXP (e1, 0)) == SP_REGNUM | |
22619 | && GET_CODE (XEXP (e1, 1)) == CONST_INT) | |
22620 | { | |
22621 | /* Set reg to offset from sp. */ | |
22622 | asm_fprintf (asm_out_file, "\t.movsp %r, #%d\n", | |
22623 | REGNO (e0), (int)INTVAL(XEXP (e1, 1))); | |
22624 | } | |
5b3e6663 PB |
22625 | else if (GET_CODE (e1) == UNSPEC && XINT (e1, 1) == UNSPEC_STACK_ALIGN) |
22626 | { | |
22627 | /* Stack pointer save before alignment. */ | |
22628 | reg = REGNO (e0); | |
22629 | asm_fprintf (asm_out_file, "\t.unwind_raw 0, 0x%x @ vsp = r%d\n", | |
22630 | reg + 0x90, reg); | |
22631 | } | |
617a1b71 PB |
22632 | else |
22633 | abort (); | |
22634 | break; | |
22635 | ||
22636 | default: | |
22637 | abort (); | |
22638 | } | |
22639 | } | |
22640 | ||
22641 | ||
22642 | /* Emit unwind directives for the given insn. */ | |
22643 | ||
22644 | static void | |
22645 | arm_unwind_emit (FILE * asm_out_file, rtx insn) | |
22646 | { | |
22647 | rtx pat; | |
22648 | ||
d5fabb58 | 22649 | if (arm_except_unwind_info (&global_options) != UI_TARGET) |
617a1b71 PB |
22650 | return; |
22651 | ||
e3b5732b | 22652 | if (!(flag_unwind_tables || crtl->uses_eh_lsda) |
80efdb6a | 22653 | && (TREE_NOTHROW (current_function_decl) |
ad516a74 | 22654 | || crtl->all_throwers_are_sibcalls)) |
80efdb6a PB |
22655 | return; |
22656 | ||
617a1b71 PB |
22657 | if (GET_CODE (insn) == NOTE || !RTX_FRAME_RELATED_P (insn)) |
22658 | return; | |
22659 | ||
22660 | pat = find_reg_note (insn, REG_FRAME_RELATED_EXPR, NULL_RTX); | |
22661 | if (pat) | |
22662 | pat = XEXP (pat, 0); | |
22663 | else | |
22664 | pat = PATTERN (insn); | |
22665 | ||
22666 | switch (GET_CODE (pat)) | |
22667 | { | |
22668 | case SET: | |
22669 | arm_unwind_emit_set (asm_out_file, pat); | |
22670 | break; | |
22671 | ||
22672 | case SEQUENCE: | |
22673 | /* Store multiple. */ | |
5b3e6663 | 22674 | arm_unwind_emit_sequence (asm_out_file, pat); |
617a1b71 PB |
22675 | break; |
22676 | ||
22677 | default: | |
22678 | abort(); | |
22679 | } | |
22680 | } | |
22681 | ||
22682 | ||
22683 | /* Output a reference from a function exception table to the type_info | |
22684 | object X. The EABI specifies that the symbol should be relocated by | |
22685 | an R_ARM_TARGET2 relocation. */ | |
22686 | ||
22687 | static bool | |
22688 | arm_output_ttype (rtx x) | |
22689 | { | |
22690 | fputs ("\t.word\t", asm_out_file); | |
22691 | output_addr_const (asm_out_file, x); | |
22692 | /* Use special relocations for symbol references. */ | |
22693 | if (GET_CODE (x) != CONST_INT) | |
22694 | fputs ("(TARGET2)", asm_out_file); | |
22695 | fputc ('\n', asm_out_file); | |
22696 | ||
22697 | return TRUE; | |
22698 | } | |
a68b5e52 RH |
22699 | |
22700 | /* Implement TARGET_ASM_EMIT_EXCEPT_PERSONALITY. */ | |
22701 | ||
22702 | static void | |
22703 | arm_asm_emit_except_personality (rtx personality) | |
22704 | { | |
22705 | fputs ("\t.personality\t", asm_out_file); | |
22706 | output_addr_const (asm_out_file, personality); | |
22707 | fputc ('\n', asm_out_file); | |
22708 | } | |
22709 | ||
22710 | /* Implement TARGET_ASM_INITIALIZE_SECTIONS. */ | |
22711 | ||
22712 | static void | |
22713 | arm_asm_init_sections (void) | |
22714 | { | |
22715 | exception_section = get_unnamed_section (0, output_section_asm_op, | |
22716 | "\t.handlerdata"); | |
22717 | } | |
f0a0390e RH |
22718 | #endif /* ARM_UNWIND_INFO */ |
22719 | ||
22720 | /* Implement TARGET_EXCEPT_UNWIND_INFO. */ | |
22721 | ||
22722 | static enum unwind_info_type | |
d5fabb58 | 22723 | arm_except_unwind_info (struct gcc_options *opts) |
f0a0390e RH |
22724 | { |
22725 | /* Honor the --enable-sjlj-exceptions configure switch. */ | |
22726 | #ifdef CONFIG_SJLJ_EXCEPTIONS | |
22727 | if (CONFIG_SJLJ_EXCEPTIONS) | |
22728 | return UI_SJLJ; | |
22729 | #endif | |
22730 | ||
22731 | /* If not using ARM EABI unwind tables... */ | |
22732 | if (ARM_UNWIND_INFO) | |
22733 | { | |
22734 | /* For simplicity elsewhere in this file, indicate that all unwind | |
22735 | info is disabled if we're not emitting unwind tables. */ | |
d5fabb58 | 22736 | if (!opts->x_flag_exceptions && !opts->x_flag_unwind_tables) |
f0a0390e RH |
22737 | return UI_NONE; |
22738 | else | |
22739 | return UI_TARGET; | |
22740 | } | |
22741 | ||
22742 | /* ... we use sjlj exceptions for backwards compatibility. */ | |
22743 | return UI_SJLJ; | |
22744 | } | |
617a1b71 PB |
22745 | |
22746 | ||
5b3e6663 PB |
22747 | /* Handle UNSPEC DWARF call frame instructions. These are needed for dynamic |
22748 | stack alignment. */ | |
22749 | ||
22750 | static void | |
22751 | arm_dwarf_handle_frame_unspec (const char *label, rtx pattern, int index) | |
22752 | { | |
22753 | rtx unspec = SET_SRC (pattern); | |
22754 | gcc_assert (GET_CODE (unspec) == UNSPEC); | |
22755 | ||
22756 | switch (index) | |
22757 | { | |
22758 | case UNSPEC_STACK_ALIGN: | |
22759 | /* ??? We should set the CFA = (SP & ~7). At this point we haven't | |
22760 | put anything on the stack, so hopefully it won't matter. | |
22761 | CFA = SP will be correct after alignment. */ | |
22762 | dwarf2out_reg_save_reg (label, stack_pointer_rtx, | |
22763 | SET_DEST (pattern)); | |
22764 | break; | |
22765 | default: | |
22766 | gcc_unreachable (); | |
22767 | } | |
22768 | } | |
22769 | ||
22770 | ||
617a1b71 PB |
22771 | /* Output unwind directives for the start/end of a function. */ |
22772 | ||
22773 | void | |
22774 | arm_output_fn_unwind (FILE * f, bool prologue) | |
22775 | { | |
d5fabb58 | 22776 | if (arm_except_unwind_info (&global_options) != UI_TARGET) |
617a1b71 PB |
22777 | return; |
22778 | ||
22779 | if (prologue) | |
22780 | fputs ("\t.fnstart\n", f); | |
22781 | else | |
80efdb6a PB |
22782 | { |
22783 | /* If this function will never be unwound, then mark it as such. | |
22784 | The came condition is used in arm_unwind_emit to suppress | |
22785 | the frame annotations. */ | |
e3b5732b | 22786 | if (!(flag_unwind_tables || crtl->uses_eh_lsda) |
80efdb6a | 22787 | && (TREE_NOTHROW (current_function_decl) |
ad516a74 | 22788 | || crtl->all_throwers_are_sibcalls)) |
80efdb6a PB |
22789 | fputs("\t.cantunwind\n", f); |
22790 | ||
22791 | fputs ("\t.fnend\n", f); | |
22792 | } | |
617a1b71 | 22793 | } |
d3585b76 DJ |
22794 | |
22795 | static bool | |
22796 | arm_emit_tls_decoration (FILE *fp, rtx x) | |
22797 | { | |
22798 | enum tls_reloc reloc; | |
22799 | rtx val; | |
22800 | ||
22801 | val = XVECEXP (x, 0, 0); | |
32e8bb8e | 22802 | reloc = (enum tls_reloc) INTVAL (XVECEXP (x, 0, 1)); |
d3585b76 DJ |
22803 | |
22804 | output_addr_const (fp, val); | |
22805 | ||
22806 | switch (reloc) | |
22807 | { | |
22808 | case TLS_GD32: | |
22809 | fputs ("(tlsgd)", fp); | |
22810 | break; | |
22811 | case TLS_LDM32: | |
22812 | fputs ("(tlsldm)", fp); | |
22813 | break; | |
22814 | case TLS_LDO32: | |
22815 | fputs ("(tlsldo)", fp); | |
22816 | break; | |
22817 | case TLS_IE32: | |
22818 | fputs ("(gottpoff)", fp); | |
22819 | break; | |
22820 | case TLS_LE32: | |
22821 | fputs ("(tpoff)", fp); | |
22822 | break; | |
22823 | default: | |
22824 | gcc_unreachable (); | |
22825 | } | |
22826 | ||
22827 | switch (reloc) | |
22828 | { | |
22829 | case TLS_GD32: | |
22830 | case TLS_LDM32: | |
22831 | case TLS_IE32: | |
22832 | fputs (" + (. - ", fp); | |
22833 | output_addr_const (fp, XVECEXP (x, 0, 2)); | |
22834 | fputs (" - ", fp); | |
22835 | output_addr_const (fp, XVECEXP (x, 0, 3)); | |
22836 | fputc (')', fp); | |
22837 | break; | |
22838 | default: | |
22839 | break; | |
22840 | } | |
22841 | ||
22842 | return TRUE; | |
22843 | } | |
22844 | ||
afcc986d JM |
22845 | /* ARM implementation of TARGET_ASM_OUTPUT_DWARF_DTPREL. */ |
22846 | ||
22847 | static void | |
22848 | arm_output_dwarf_dtprel (FILE *file, int size, rtx x) | |
22849 | { | |
22850 | gcc_assert (size == 4); | |
22851 | fputs ("\t.word\t", file); | |
22852 | output_addr_const (file, x); | |
22853 | fputs ("(tlsldo)", file); | |
22854 | } | |
22855 | ||
ffda8a0d AS |
22856 | /* Implement TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */ |
22857 | ||
22858 | static bool | |
d3585b76 DJ |
22859 | arm_output_addr_const_extra (FILE *fp, rtx x) |
22860 | { | |
22861 | if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLS) | |
22862 | return arm_emit_tls_decoration (fp, x); | |
f16fe45f DJ |
22863 | else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_PIC_LABEL) |
22864 | { | |
22865 | char label[256]; | |
22866 | int labelno = INTVAL (XVECEXP (x, 0, 0)); | |
22867 | ||
22868 | ASM_GENERATE_INTERNAL_LABEL (label, "LPIC", labelno); | |
22869 | assemble_name_raw (fp, label); | |
22870 | ||
f9bd1a89 RS |
22871 | return TRUE; |
22872 | } | |
22873 | else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_GOTSYM_OFF) | |
22874 | { | |
22875 | assemble_name (fp, "_GLOBAL_OFFSET_TABLE_"); | |
22876 | if (GOT_PCREL) | |
22877 | fputs ("+.", fp); | |
22878 | fputs ("-(", fp); | |
22879 | output_addr_const (fp, XVECEXP (x, 0, 0)); | |
22880 | fputc (')', fp); | |
f16fe45f DJ |
22881 | return TRUE; |
22882 | } | |
85c9bcd4 WG |
22883 | else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_SYMBOL_OFFSET) |
22884 | { | |
22885 | output_addr_const (fp, XVECEXP (x, 0, 0)); | |
22886 | if (GOT_PCREL) | |
22887 | fputs ("+.", fp); | |
22888 | fputs ("-(", fp); | |
22889 | output_addr_const (fp, XVECEXP (x, 0, 1)); | |
22890 | fputc (')', fp); | |
22891 | return TRUE; | |
22892 | } | |
d3585b76 DJ |
22893 | else if (GET_CODE (x) == CONST_VECTOR) |
22894 | return arm_emit_vector_const (fp, x); | |
22895 | ||
22896 | return FALSE; | |
22897 | } | |
22898 | ||
5b3e6663 PB |
22899 | /* Output assembly for a shift instruction. |
22900 | SET_FLAGS determines how the instruction modifies the condition codes. | |
7a085dce | 22901 | 0 - Do not set condition codes. |
5b3e6663 PB |
22902 | 1 - Set condition codes. |
22903 | 2 - Use smallest instruction. */ | |
22904 | const char * | |
22905 | arm_output_shift(rtx * operands, int set_flags) | |
22906 | { | |
22907 | char pattern[100]; | |
22908 | static const char flag_chars[3] = {'?', '.', '!'}; | |
22909 | const char *shift; | |
22910 | HOST_WIDE_INT val; | |
22911 | char c; | |
22912 | ||
22913 | c = flag_chars[set_flags]; | |
22914 | if (TARGET_UNIFIED_ASM) | |
22915 | { | |
22916 | shift = shift_op(operands[3], &val); | |
22917 | if (shift) | |
22918 | { | |
22919 | if (val != -1) | |
22920 | operands[2] = GEN_INT(val); | |
22921 | sprintf (pattern, "%s%%%c\t%%0, %%1, %%2", shift, c); | |
22922 | } | |
22923 | else | |
22924 | sprintf (pattern, "mov%%%c\t%%0, %%1", c); | |
22925 | } | |
22926 | else | |
22927 | sprintf (pattern, "mov%%%c\t%%0, %%1%%S3", c); | |
22928 | output_asm_insn (pattern, operands); | |
22929 | return ""; | |
22930 | } | |
22931 | ||
907dd0c7 RE |
22932 | /* Output a Thumb-1 casesi dispatch sequence. */ |
22933 | const char * | |
22934 | thumb1_output_casesi (rtx *operands) | |
22935 | { | |
22936 | rtx diff_vec = PATTERN (next_real_insn (operands[0])); | |
907dd0c7 RE |
22937 | |
22938 | gcc_assert (GET_CODE (diff_vec) == ADDR_DIFF_VEC); | |
22939 | ||
907dd0c7 RE |
22940 | switch (GET_MODE(diff_vec)) |
22941 | { | |
22942 | case QImode: | |
22943 | return (ADDR_DIFF_VEC_FLAGS (diff_vec).offset_unsigned ? | |
22944 | "bl\t%___gnu_thumb1_case_uqi" : "bl\t%___gnu_thumb1_case_sqi"); | |
22945 | case HImode: | |
22946 | return (ADDR_DIFF_VEC_FLAGS (diff_vec).offset_unsigned ? | |
22947 | "bl\t%___gnu_thumb1_case_uhi" : "bl\t%___gnu_thumb1_case_shi"); | |
22948 | case SImode: | |
22949 | return "bl\t%___gnu_thumb1_case_si"; | |
22950 | default: | |
22951 | gcc_unreachable (); | |
22952 | } | |
22953 | } | |
22954 | ||
5b3e6663 PB |
22955 | /* Output a Thumb-2 casesi instruction. */ |
22956 | const char * | |
22957 | thumb2_output_casesi (rtx *operands) | |
22958 | { | |
22959 | rtx diff_vec = PATTERN (next_real_insn (operands[2])); | |
22960 | ||
22961 | gcc_assert (GET_CODE (diff_vec) == ADDR_DIFF_VEC); | |
22962 | ||
22963 | output_asm_insn ("cmp\t%0, %1", operands); | |
22964 | output_asm_insn ("bhi\t%l3", operands); | |
22965 | switch (GET_MODE(diff_vec)) | |
22966 | { | |
22967 | case QImode: | |
22968 | return "tbb\t[%|pc, %0]"; | |
22969 | case HImode: | |
22970 | return "tbh\t[%|pc, %0, lsl #1]"; | |
22971 | case SImode: | |
22972 | if (flag_pic) | |
22973 | { | |
22974 | output_asm_insn ("adr\t%4, %l2", operands); | |
22975 | output_asm_insn ("ldr\t%5, [%4, %0, lsl #2]", operands); | |
22976 | output_asm_insn ("add\t%4, %4, %5", operands); | |
22977 | return "bx\t%4"; | |
22978 | } | |
22979 | else | |
22980 | { | |
22981 | output_asm_insn ("adr\t%4, %l2", operands); | |
22982 | return "ldr\t%|pc, [%4, %0, lsl #2]"; | |
22983 | } | |
22984 | default: | |
22985 | gcc_unreachable (); | |
22986 | } | |
22987 | } | |
22988 | ||
bd4dc3cd PB |
22989 | /* Most ARM cores are single issue, but some newer ones can dual issue. |
22990 | The scheduler descriptions rely on this being correct. */ | |
22991 | static int | |
22992 | arm_issue_rate (void) | |
22993 | { | |
22994 | switch (arm_tune) | |
22995 | { | |
22996 | case cortexr4: | |
51c69ddb | 22997 | case cortexr4f: |
d8099dd8 | 22998 | case cortexa5: |
bd4dc3cd | 22999 | case cortexa8: |
7612f14d | 23000 | case cortexa9: |
c02a5ccb | 23001 | case fa726te: |
bd4dc3cd PB |
23002 | return 2; |
23003 | ||
23004 | default: | |
23005 | return 1; | |
23006 | } | |
23007 | } | |
23008 | ||
608063c3 JB |
23009 | /* A table and a function to perform ARM-specific name mangling for |
23010 | NEON vector types in order to conform to the AAPCS (see "Procedure | |
23011 | Call Standard for the ARM Architecture", Appendix A). To qualify | |
23012 | for emission with the mangled names defined in that document, a | |
23013 | vector type must not only be of the correct mode but also be | |
23014 | composed of NEON vector element types (e.g. __builtin_neon_qi). */ | |
23015 | typedef struct | |
23016 | { | |
23017 | enum machine_mode mode; | |
23018 | const char *element_type_name; | |
23019 | const char *aapcs_name; | |
23020 | } arm_mangle_map_entry; | |
23021 | ||
23022 | static arm_mangle_map_entry arm_mangle_map[] = { | |
23023 | /* 64-bit containerized types. */ | |
23024 | { V8QImode, "__builtin_neon_qi", "15__simd64_int8_t" }, | |
23025 | { V8QImode, "__builtin_neon_uqi", "16__simd64_uint8_t" }, | |
23026 | { V4HImode, "__builtin_neon_hi", "16__simd64_int16_t" }, | |
23027 | { V4HImode, "__builtin_neon_uhi", "17__simd64_uint16_t" }, | |
23028 | { V2SImode, "__builtin_neon_si", "16__simd64_int32_t" }, | |
23029 | { V2SImode, "__builtin_neon_usi", "17__simd64_uint32_t" }, | |
23030 | { V2SFmode, "__builtin_neon_sf", "18__simd64_float32_t" }, | |
23031 | { V8QImode, "__builtin_neon_poly8", "16__simd64_poly8_t" }, | |
23032 | { V4HImode, "__builtin_neon_poly16", "17__simd64_poly16_t" }, | |
23033 | /* 128-bit containerized types. */ | |
23034 | { V16QImode, "__builtin_neon_qi", "16__simd128_int8_t" }, | |
23035 | { V16QImode, "__builtin_neon_uqi", "17__simd128_uint8_t" }, | |
23036 | { V8HImode, "__builtin_neon_hi", "17__simd128_int16_t" }, | |
23037 | { V8HImode, "__builtin_neon_uhi", "18__simd128_uint16_t" }, | |
23038 | { V4SImode, "__builtin_neon_si", "17__simd128_int32_t" }, | |
23039 | { V4SImode, "__builtin_neon_usi", "18__simd128_uint32_t" }, | |
23040 | { V4SFmode, "__builtin_neon_sf", "19__simd128_float32_t" }, | |
23041 | { V16QImode, "__builtin_neon_poly8", "17__simd128_poly8_t" }, | |
23042 | { V8HImode, "__builtin_neon_poly16", "18__simd128_poly16_t" }, | |
23043 | { VOIDmode, NULL, NULL } | |
23044 | }; | |
23045 | ||
23046 | const char * | |
3101faab | 23047 | arm_mangle_type (const_tree type) |
608063c3 JB |
23048 | { |
23049 | arm_mangle_map_entry *pos = arm_mangle_map; | |
23050 | ||
07d8efe3 MM |
23051 | /* The ARM ABI documents (10th October 2008) say that "__va_list" |
23052 | has to be managled as if it is in the "std" namespace. */ | |
23053 | if (TARGET_AAPCS_BASED | |
ae46a823 | 23054 | && lang_hooks.types_compatible_p (CONST_CAST_TREE (type), va_list_type)) |
07d8efe3 MM |
23055 | { |
23056 | static bool warned; | |
d147cbd9 | 23057 | if (!warned && warn_psabi && !in_system_header) |
07d8efe3 MM |
23058 | { |
23059 | warned = true; | |
23060 | inform (input_location, | |
23061 | "the mangling of %<va_list%> has changed in GCC 4.4"); | |
23062 | } | |
23063 | return "St9__va_list"; | |
23064 | } | |
23065 | ||
0fd8c3ad SL |
23066 | /* Half-precision float. */ |
23067 | if (TREE_CODE (type) == REAL_TYPE && TYPE_PRECISION (type) == 16) | |
23068 | return "Dh"; | |
23069 | ||
608063c3 JB |
23070 | if (TREE_CODE (type) != VECTOR_TYPE) |
23071 | return NULL; | |
23072 | ||
23073 | /* Check the mode of the vector type, and the name of the vector | |
23074 | element type, against the table. */ | |
23075 | while (pos->mode != VOIDmode) | |
23076 | { | |
23077 | tree elt_type = TREE_TYPE (type); | |
23078 | ||
23079 | if (pos->mode == TYPE_MODE (type) | |
23080 | && TREE_CODE (TYPE_NAME (elt_type)) == TYPE_DECL | |
23081 | && !strcmp (IDENTIFIER_POINTER (DECL_NAME (TYPE_NAME (elt_type))), | |
23082 | pos->element_type_name)) | |
23083 | return pos->aapcs_name; | |
23084 | ||
23085 | pos++; | |
23086 | } | |
23087 | ||
23088 | /* Use the default mangling for unrecognized (possibly user-defined) | |
23089 | vector types. */ | |
23090 | return NULL; | |
23091 | } | |
23092 | ||
795dc4fc PB |
23093 | /* Order of allocation of core registers for Thumb: this allocation is |
23094 | written over the corresponding initial entries of the array | |
23095 | initialized with REG_ALLOC_ORDER. We allocate all low registers | |
23096 | first. Saving and restoring a low register is usually cheaper than | |
23097 | using a call-clobbered high register. */ | |
23098 | ||
23099 | static const int thumb_core_reg_alloc_order[] = | |
23100 | { | |
23101 | 3, 2, 1, 0, 4, 5, 6, 7, | |
23102 | 14, 12, 8, 9, 10, 11, 13, 15 | |
23103 | }; | |
23104 | ||
23105 | /* Adjust register allocation order when compiling for Thumb. */ | |
23106 | ||
23107 | void | |
23108 | arm_order_regs_for_local_alloc (void) | |
23109 | { | |
23110 | const int arm_reg_alloc_order[] = REG_ALLOC_ORDER; | |
23111 | memcpy(reg_alloc_order, arm_reg_alloc_order, sizeof (reg_alloc_order)); | |
23112 | if (TARGET_THUMB) | |
23113 | memcpy (reg_alloc_order, thumb_core_reg_alloc_order, | |
23114 | sizeof (thumb_core_reg_alloc_order)); | |
23115 | } | |
23116 | ||
b52b1749 AS |
23117 | /* Implement TARGET_FRAME_POINTER_REQUIRED. */ |
23118 | ||
23119 | bool | |
23120 | arm_frame_pointer_required (void) | |
23121 | { | |
23122 | return (cfun->has_nonlocal_label | |
23123 | || SUBTARGET_FRAME_POINTER_REQUIRED | |
23124 | || (TARGET_ARM && TARGET_APCS_FRAME && ! leaf_function_p ())); | |
23125 | } | |
23126 | ||
2929029c WG |
23127 | /* Only thumb1 can't support conditional execution, so return true if |
23128 | the target is not thumb1. */ | |
23129 | static bool | |
23130 | arm_have_conditional_execution (void) | |
23131 | { | |
23132 | return !TARGET_THUMB1; | |
23133 | } | |
23134 | ||
029e79eb MS |
23135 | /* Legitimize a memory reference for sync primitive implemented using |
23136 | ldrex / strex. We currently force the form of the reference to be | |
23137 | indirect without offset. We do not yet support the indirect offset | |
23138 | addressing supported by some ARM targets for these | |
23139 | instructions. */ | |
23140 | static rtx | |
23141 | arm_legitimize_sync_memory (rtx memory) | |
23142 | { | |
23143 | rtx addr = force_reg (Pmode, XEXP (memory, 0)); | |
23144 | rtx legitimate_memory = gen_rtx_MEM (GET_MODE (memory), addr); | |
23145 | ||
23146 | set_mem_alias_set (legitimate_memory, ALIAS_SET_MEMORY_BARRIER); | |
23147 | MEM_VOLATILE_P (legitimate_memory) = MEM_VOLATILE_P (memory); | |
23148 | return legitimate_memory; | |
23149 | } | |
23150 | ||
23151 | /* An instruction emitter. */ | |
23152 | typedef void (* emit_f) (int label, const char *, rtx *); | |
23153 | ||
23154 | /* An instruction emitter that emits via the conventional | |
23155 | output_asm_insn. */ | |
23156 | static void | |
23157 | arm_emit (int label ATTRIBUTE_UNUSED, const char *pattern, rtx *operands) | |
23158 | { | |
23159 | output_asm_insn (pattern, operands); | |
23160 | } | |
23161 | ||
23162 | /* Count the number of emitted synchronization instructions. */ | |
23163 | static unsigned arm_insn_count; | |
23164 | ||
23165 | /* An emitter that counts emitted instructions but does not actually | |
23166 | emit instruction into the the instruction stream. */ | |
23167 | static void | |
23168 | arm_count (int label, | |
23169 | const char *pattern ATTRIBUTE_UNUSED, | |
23170 | rtx *operands ATTRIBUTE_UNUSED) | |
23171 | { | |
23172 | if (! label) | |
23173 | ++ arm_insn_count; | |
23174 | } | |
23175 | ||
23176 | /* Construct a pattern using conventional output formatting and feed | |
23177 | it to output_asm_insn. Provides a mechanism to construct the | |
23178 | output pattern on the fly. Note the hard limit on the pattern | |
23179 | buffer size. */ | |
21272a45 | 23180 | static void ATTRIBUTE_PRINTF_4 |
029e79eb MS |
23181 | arm_output_asm_insn (emit_f emit, int label, rtx *operands, |
23182 | const char *pattern, ...) | |
23183 | { | |
23184 | va_list ap; | |
23185 | char buffer[256]; | |
23186 | ||
23187 | va_start (ap, pattern); | |
23188 | vsprintf (buffer, pattern, ap); | |
23189 | va_end (ap); | |
23190 | emit (label, buffer, operands); | |
23191 | } | |
23192 | ||
23193 | /* Emit the memory barrier instruction, if any, provided by this | |
23194 | target to a specified emitter. */ | |
23195 | static void | |
23196 | arm_process_output_memory_barrier (emit_f emit, rtx *operands) | |
23197 | { | |
23198 | if (TARGET_HAVE_DMB) | |
23199 | { | |
23200 | /* Note we issue a system level barrier. We should consider | |
23201 | issuing a inner shareabilty zone barrier here instead, ie. | |
23202 | "DMB ISH". */ | |
23203 | emit (0, "dmb\tsy", operands); | |
23204 | return; | |
23205 | } | |
23206 | ||
23207 | if (TARGET_HAVE_DMB_MCR) | |
23208 | { | |
23209 | emit (0, "mcr\tp15, 0, r0, c7, c10, 5", operands); | |
23210 | return; | |
23211 | } | |
23212 | ||
23213 | gcc_unreachable (); | |
23214 | } | |
23215 | ||
23216 | /* Emit the memory barrier instruction, if any, provided by this | |
23217 | target. */ | |
23218 | const char * | |
23219 | arm_output_memory_barrier (rtx *operands) | |
23220 | { | |
23221 | arm_process_output_memory_barrier (arm_emit, operands); | |
23222 | return ""; | |
23223 | } | |
23224 | ||
23225 | /* Helper to figure out the instruction suffix required on ldrex/strex | |
23226 | for operations on an object of the specified mode. */ | |
23227 | static const char * | |
23228 | arm_ldrex_suffix (enum machine_mode mode) | |
23229 | { | |
23230 | switch (mode) | |
23231 | { | |
23232 | case QImode: return "b"; | |
23233 | case HImode: return "h"; | |
23234 | case SImode: return ""; | |
23235 | case DImode: return "d"; | |
23236 | default: | |
23237 | gcc_unreachable (); | |
23238 | } | |
23239 | return ""; | |
23240 | } | |
23241 | ||
23242 | /* Emit an ldrex{b,h,d, } instruction appropriate for the specified | |
23243 | mode. */ | |
23244 | static void | |
23245 | arm_output_ldrex (emit_f emit, | |
23246 | enum machine_mode mode, | |
23247 | rtx target, | |
23248 | rtx memory) | |
23249 | { | |
23250 | const char *suffix = arm_ldrex_suffix (mode); | |
23251 | rtx operands[2]; | |
23252 | ||
23253 | operands[0] = target; | |
23254 | operands[1] = memory; | |
23255 | arm_output_asm_insn (emit, 0, operands, "ldrex%s\t%%0, %%C1", suffix); | |
23256 | } | |
23257 | ||
23258 | /* Emit a strex{b,h,d, } instruction appropriate for the specified | |
23259 | mode. */ | |
23260 | static void | |
23261 | arm_output_strex (emit_f emit, | |
23262 | enum machine_mode mode, | |
23263 | const char *cc, | |
23264 | rtx result, | |
23265 | rtx value, | |
23266 | rtx memory) | |
23267 | { | |
23268 | const char *suffix = arm_ldrex_suffix (mode); | |
23269 | rtx operands[3]; | |
23270 | ||
23271 | operands[0] = result; | |
23272 | operands[1] = value; | |
23273 | operands[2] = memory; | |
23274 | arm_output_asm_insn (emit, 0, operands, "strex%s%s\t%%0, %%1, %%C2", suffix, | |
23275 | cc); | |
23276 | } | |
23277 | ||
23278 | /* Helper to emit a two operand instruction. */ | |
23279 | static void | |
23280 | arm_output_op2 (emit_f emit, const char *mnemonic, rtx d, rtx s) | |
23281 | { | |
23282 | rtx operands[2]; | |
23283 | ||
23284 | operands[0] = d; | |
23285 | operands[1] = s; | |
23286 | arm_output_asm_insn (emit, 0, operands, "%s\t%%0, %%1", mnemonic); | |
23287 | } | |
23288 | ||
23289 | /* Helper to emit a three operand instruction. */ | |
23290 | static void | |
23291 | arm_output_op3 (emit_f emit, const char *mnemonic, rtx d, rtx a, rtx b) | |
23292 | { | |
23293 | rtx operands[3]; | |
23294 | ||
23295 | operands[0] = d; | |
23296 | operands[1] = a; | |
23297 | operands[2] = b; | |
23298 | arm_output_asm_insn (emit, 0, operands, "%s\t%%0, %%1, %%2", mnemonic); | |
23299 | } | |
23300 | ||
23301 | /* Emit a load store exclusive synchronization loop. | |
23302 | ||
23303 | do | |
23304 | old_value = [mem] | |
23305 | if old_value != required_value | |
23306 | break; | |
23307 | t1 = sync_op (old_value, new_value) | |
23308 | [mem] = t1, t2 = [0|1] | |
23309 | while ! t2 | |
23310 | ||
23311 | Note: | |
23312 | t1 == t2 is not permitted | |
23313 | t1 == old_value is permitted | |
23314 | ||
23315 | required_value: | |
23316 | ||
23317 | RTX register or const_int representing the required old_value for | |
23318 | the modify to continue, if NULL no comparsion is performed. */ | |
23319 | static void | |
23320 | arm_output_sync_loop (emit_f emit, | |
23321 | enum machine_mode mode, | |
23322 | rtx old_value, | |
23323 | rtx memory, | |
23324 | rtx required_value, | |
23325 | rtx new_value, | |
23326 | rtx t1, | |
23327 | rtx t2, | |
23328 | enum attr_sync_op sync_op, | |
23329 | int early_barrier_required) | |
23330 | { | |
23331 | rtx operands[1]; | |
23332 | ||
23333 | gcc_assert (t1 != t2); | |
23334 | ||
23335 | if (early_barrier_required) | |
23336 | arm_process_output_memory_barrier (emit, NULL); | |
23337 | ||
23338 | arm_output_asm_insn (emit, 1, operands, "%sLSYT%%=:", LOCAL_LABEL_PREFIX); | |
23339 | ||
23340 | arm_output_ldrex (emit, mode, old_value, memory); | |
23341 | ||
23342 | if (required_value) | |
23343 | { | |
23344 | rtx operands[2]; | |
23345 | ||
23346 | operands[0] = old_value; | |
23347 | operands[1] = required_value; | |
23348 | arm_output_asm_insn (emit, 0, operands, "cmp\t%%0, %%1"); | |
23349 | arm_output_asm_insn (emit, 0, operands, "bne\t%sLSYB%%=", LOCAL_LABEL_PREFIX); | |
23350 | } | |
23351 | ||
23352 | switch (sync_op) | |
23353 | { | |
23354 | case SYNC_OP_ADD: | |
23355 | arm_output_op3 (emit, "add", t1, old_value, new_value); | |
23356 | break; | |
23357 | ||
23358 | case SYNC_OP_SUB: | |
23359 | arm_output_op3 (emit, "sub", t1, old_value, new_value); | |
23360 | break; | |
23361 | ||
23362 | case SYNC_OP_IOR: | |
23363 | arm_output_op3 (emit, "orr", t1, old_value, new_value); | |
23364 | break; | |
23365 | ||
23366 | case SYNC_OP_XOR: | |
23367 | arm_output_op3 (emit, "eor", t1, old_value, new_value); | |
23368 | break; | |
23369 | ||
23370 | case SYNC_OP_AND: | |
23371 | arm_output_op3 (emit,"and", t1, old_value, new_value); | |
23372 | break; | |
23373 | ||
23374 | case SYNC_OP_NAND: | |
23375 | arm_output_op3 (emit, "and", t1, old_value, new_value); | |
23376 | arm_output_op2 (emit, "mvn", t1, t1); | |
23377 | break; | |
23378 | ||
23379 | case SYNC_OP_NONE: | |
23380 | t1 = new_value; | |
23381 | break; | |
23382 | } | |
23383 | ||
b7b79b54 KW |
23384 | if (t2) |
23385 | { | |
23386 | arm_output_strex (emit, mode, "", t2, t1, memory); | |
23387 | operands[0] = t2; | |
23388 | arm_output_asm_insn (emit, 0, operands, "teq\t%%0, #0"); | |
23389 | arm_output_asm_insn (emit, 0, operands, "bne\t%sLSYT%%=", | |
23390 | LOCAL_LABEL_PREFIX); | |
23391 | } | |
23392 | else | |
23393 | { | |
23394 | /* Use old_value for the return value because for some operations | |
23395 | the old_value can easily be restored. This saves one register. */ | |
23396 | arm_output_strex (emit, mode, "", old_value, t1, memory); | |
23397 | operands[0] = old_value; | |
23398 | arm_output_asm_insn (emit, 0, operands, "teq\t%%0, #0"); | |
23399 | arm_output_asm_insn (emit, 0, operands, "bne\t%sLSYT%%=", | |
23400 | LOCAL_LABEL_PREFIX); | |
23401 | ||
23402 | switch (sync_op) | |
23403 | { | |
23404 | case SYNC_OP_ADD: | |
23405 | arm_output_op3 (emit, "sub", old_value, t1, new_value); | |
23406 | break; | |
23407 | ||
23408 | case SYNC_OP_SUB: | |
23409 | arm_output_op3 (emit, "add", old_value, t1, new_value); | |
23410 | break; | |
23411 | ||
23412 | case SYNC_OP_XOR: | |
23413 | arm_output_op3 (emit, "eor", old_value, t1, new_value); | |
23414 | break; | |
23415 | ||
23416 | case SYNC_OP_NONE: | |
23417 | arm_output_op2 (emit, "mov", old_value, required_value); | |
23418 | break; | |
23419 | ||
23420 | default: | |
23421 | gcc_unreachable (); | |
23422 | } | |
23423 | } | |
029e79eb MS |
23424 | |
23425 | arm_process_output_memory_barrier (emit, NULL); | |
23426 | arm_output_asm_insn (emit, 1, operands, "%sLSYB%%=:", LOCAL_LABEL_PREFIX); | |
23427 | } | |
23428 | ||
23429 | static rtx | |
23430 | arm_get_sync_operand (rtx *operands, int index, rtx default_value) | |
23431 | { | |
23432 | if (index > 0) | |
23433 | default_value = operands[index - 1]; | |
23434 | ||
23435 | return default_value; | |
23436 | } | |
23437 | ||
23438 | #define FETCH_SYNC_OPERAND(NAME, DEFAULT) \ | |
23439 | arm_get_sync_operand (operands, (int) get_attr_sync_##NAME (insn), DEFAULT); | |
23440 | ||
23441 | /* Extract the operands for a synchroniztion instruction from the | |
23442 | instructions attributes and emit the instruction. */ | |
23443 | static void | |
23444 | arm_process_output_sync_insn (emit_f emit, rtx insn, rtx *operands) | |
23445 | { | |
23446 | rtx result, memory, required_value, new_value, t1, t2; | |
23447 | int early_barrier; | |
23448 | enum machine_mode mode; | |
23449 | enum attr_sync_op sync_op; | |
23450 | ||
23451 | result = FETCH_SYNC_OPERAND(result, 0); | |
23452 | memory = FETCH_SYNC_OPERAND(memory, 0); | |
23453 | required_value = FETCH_SYNC_OPERAND(required_value, 0); | |
23454 | new_value = FETCH_SYNC_OPERAND(new_value, 0); | |
23455 | t1 = FETCH_SYNC_OPERAND(t1, 0); | |
23456 | t2 = FETCH_SYNC_OPERAND(t2, 0); | |
23457 | early_barrier = | |
23458 | get_attr_sync_release_barrier (insn) == SYNC_RELEASE_BARRIER_YES; | |
23459 | sync_op = get_attr_sync_op (insn); | |
23460 | mode = GET_MODE (memory); | |
23461 | ||
23462 | arm_output_sync_loop (emit, mode, result, memory, required_value, | |
23463 | new_value, t1, t2, sync_op, early_barrier); | |
23464 | } | |
23465 | ||
23466 | /* Emit a synchronization instruction loop. */ | |
23467 | const char * | |
23468 | arm_output_sync_insn (rtx insn, rtx *operands) | |
23469 | { | |
23470 | arm_process_output_sync_insn (arm_emit, insn, operands); | |
23471 | return ""; | |
23472 | } | |
23473 | ||
23474 | /* Count the number of machine instruction that will be emitted for a | |
23475 | synchronization instruction. Note that the emitter used does not | |
23476 | emit instructions, it just counts instructions being carefull not | |
23477 | to count labels. */ | |
23478 | unsigned int | |
23479 | arm_sync_loop_insns (rtx insn, rtx *operands) | |
23480 | { | |
23481 | arm_insn_count = 0; | |
23482 | arm_process_output_sync_insn (arm_count, insn, operands); | |
23483 | return arm_insn_count; | |
23484 | } | |
23485 | ||
23486 | /* Helper to call a target sync instruction generator, dealing with | |
23487 | the variation in operands required by the different generators. */ | |
23488 | static rtx | |
23489 | arm_call_generator (struct arm_sync_generator *generator, rtx old_value, | |
23490 | rtx memory, rtx required_value, rtx new_value) | |
23491 | { | |
23492 | switch (generator->op) | |
23493 | { | |
23494 | case arm_sync_generator_omn: | |
23495 | gcc_assert (! required_value); | |
23496 | return generator->u.omn (old_value, memory, new_value); | |
23497 | ||
23498 | case arm_sync_generator_omrn: | |
23499 | gcc_assert (required_value); | |
23500 | return generator->u.omrn (old_value, memory, required_value, new_value); | |
23501 | } | |
23502 | ||
23503 | return NULL; | |
23504 | } | |
23505 | ||
23506 | /* Expand a synchronization loop. The synchronization loop is expanded | |
23507 | as an opaque block of instructions in order to ensure that we do | |
23508 | not subsequently get extraneous memory accesses inserted within the | |
23509 | critical region. The exclusive access property of ldrex/strex is | |
23510 | only guaranteed in there are no intervening memory accesses. */ | |
23511 | void | |
23512 | arm_expand_sync (enum machine_mode mode, | |
23513 | struct arm_sync_generator *generator, | |
23514 | rtx target, rtx memory, rtx required_value, rtx new_value) | |
23515 | { | |
23516 | if (target == NULL) | |
23517 | target = gen_reg_rtx (mode); | |
23518 | ||
23519 | memory = arm_legitimize_sync_memory (memory); | |
23520 | if (mode != SImode) | |
23521 | { | |
23522 | rtx load_temp = gen_reg_rtx (SImode); | |
23523 | ||
23524 | if (required_value) | |
23525 | required_value = convert_modes (SImode, mode, required_value, true); | |
23526 | ||
23527 | new_value = convert_modes (SImode, mode, new_value, true); | |
23528 | emit_insn (arm_call_generator (generator, load_temp, memory, | |
23529 | required_value, new_value)); | |
23530 | emit_move_insn (target, gen_lowpart (mode, load_temp)); | |
23531 | } | |
23532 | else | |
23533 | { | |
23534 | emit_insn (arm_call_generator (generator, target, memory, required_value, | |
23535 | new_value)); | |
23536 | } | |
23537 | } | |
23538 | ||
c452684d JB |
23539 | static bool |
23540 | arm_vector_alignment_reachable (const_tree type, bool is_packed) | |
23541 | { | |
23542 | /* Vectors which aren't in packed structures will not be less aligned than | |
23543 | the natural alignment of their element type, so this is safe. */ | |
23544 | if (TARGET_NEON && !BYTES_BIG_ENDIAN) | |
23545 | return !is_packed; | |
23546 | ||
23547 | return default_builtin_vector_alignment_reachable (type, is_packed); | |
23548 | } | |
23549 | ||
23550 | static bool | |
23551 | arm_builtin_support_vector_misalignment (enum machine_mode mode, | |
23552 | const_tree type, int misalignment, | |
23553 | bool is_packed) | |
23554 | { | |
23555 | if (TARGET_NEON && !BYTES_BIG_ENDIAN) | |
23556 | { | |
23557 | HOST_WIDE_INT align = TYPE_ALIGN_UNIT (type); | |
23558 | ||
23559 | if (is_packed) | |
23560 | return align == 1; | |
23561 | ||
23562 | /* If the misalignment is unknown, we should be able to handle the access | |
23563 | so long as it is not to a member of a packed data structure. */ | |
23564 | if (misalignment == -1) | |
23565 | return true; | |
23566 | ||
23567 | /* Return true if the misalignment is a multiple of the natural alignment | |
23568 | of the vector's element type. This is probably always going to be | |
23569 | true in practice, since we've already established that this isn't a | |
23570 | packed access. */ | |
23571 | return ((misalignment % align) == 0); | |
23572 | } | |
23573 | ||
23574 | return default_builtin_support_vector_misalignment (mode, type, misalignment, | |
23575 | is_packed); | |
23576 | } | |
23577 | ||
5efd84c5 NF |
23578 | static void |
23579 | arm_conditional_register_usage (void) | |
23580 | { | |
23581 | int regno; | |
23582 | ||
23583 | if (TARGET_SOFT_FLOAT || TARGET_THUMB1 || !TARGET_FPA) | |
23584 | { | |
23585 | for (regno = FIRST_FPA_REGNUM; | |
23586 | regno <= LAST_FPA_REGNUM; ++regno) | |
23587 | fixed_regs[regno] = call_used_regs[regno] = 1; | |
23588 | } | |
23589 | ||
23590 | if (TARGET_THUMB1 && optimize_size) | |
23591 | { | |
23592 | /* When optimizing for size on Thumb-1, it's better not | |
23593 | to use the HI regs, because of the overhead of | |
23594 | stacking them. */ | |
23595 | for (regno = FIRST_HI_REGNUM; | |
23596 | regno <= LAST_HI_REGNUM; ++regno) | |
23597 | fixed_regs[regno] = call_used_regs[regno] = 1; | |
23598 | } | |
23599 | ||
23600 | /* The link register can be clobbered by any branch insn, | |
23601 | but we have no way to track that at present, so mark | |
23602 | it as unavailable. */ | |
23603 | if (TARGET_THUMB1) | |
23604 | fixed_regs[LR_REGNUM] = call_used_regs[LR_REGNUM] = 1; | |
23605 | ||
23606 | if (TARGET_32BIT && TARGET_HARD_FLOAT) | |
23607 | { | |
23608 | if (TARGET_MAVERICK) | |
23609 | { | |
23610 | for (regno = FIRST_FPA_REGNUM; | |
23611 | regno <= LAST_FPA_REGNUM; ++ regno) | |
23612 | fixed_regs[regno] = call_used_regs[regno] = 1; | |
23613 | for (regno = FIRST_CIRRUS_FP_REGNUM; | |
23614 | regno <= LAST_CIRRUS_FP_REGNUM; ++ regno) | |
23615 | { | |
23616 | fixed_regs[regno] = 0; | |
23617 | call_used_regs[regno] = regno < FIRST_CIRRUS_FP_REGNUM + 4; | |
23618 | } | |
23619 | } | |
23620 | if (TARGET_VFP) | |
23621 | { | |
23622 | /* VFPv3 registers are disabled when earlier VFP | |
23623 | versions are selected due to the definition of | |
23624 | LAST_VFP_REGNUM. */ | |
23625 | for (regno = FIRST_VFP_REGNUM; | |
23626 | regno <= LAST_VFP_REGNUM; ++ regno) | |
23627 | { | |
23628 | fixed_regs[regno] = 0; | |
23629 | call_used_regs[regno] = regno < FIRST_VFP_REGNUM + 16 | |
23630 | || regno >= FIRST_VFP_REGNUM + 32; | |
23631 | } | |
23632 | } | |
23633 | } | |
23634 | ||
23635 | if (TARGET_REALLY_IWMMXT) | |
23636 | { | |
23637 | regno = FIRST_IWMMXT_GR_REGNUM; | |
23638 | /* The 2002/10/09 revision of the XScale ABI has wCG0 | |
23639 | and wCG1 as call-preserved registers. The 2002/11/21 | |
23640 | revision changed this so that all wCG registers are | |
23641 | scratch registers. */ | |
23642 | for (regno = FIRST_IWMMXT_GR_REGNUM; | |
23643 | regno <= LAST_IWMMXT_GR_REGNUM; ++ regno) | |
23644 | fixed_regs[regno] = 0; | |
23645 | /* The XScale ABI has wR0 - wR9 as scratch registers, | |
23646 | the rest as call-preserved registers. */ | |
23647 | for (regno = FIRST_IWMMXT_REGNUM; | |
23648 | regno <= LAST_IWMMXT_REGNUM; ++ regno) | |
23649 | { | |
23650 | fixed_regs[regno] = 0; | |
23651 | call_used_regs[regno] = regno < FIRST_IWMMXT_REGNUM + 10; | |
23652 | } | |
23653 | } | |
23654 | ||
23655 | if ((unsigned) PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) | |
23656 | { | |
23657 | fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; | |
23658 | call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; | |
23659 | } | |
23660 | else if (TARGET_APCS_STACK) | |
23661 | { | |
23662 | fixed_regs[10] = 1; | |
23663 | call_used_regs[10] = 1; | |
23664 | } | |
23665 | /* -mcaller-super-interworking reserves r11 for calls to | |
23666 | _interwork_r11_call_via_rN(). Making the register global | |
23667 | is an easy way of ensuring that it remains valid for all | |
23668 | calls. */ | |
23669 | if (TARGET_APCS_FRAME || TARGET_CALLER_INTERWORKING | |
23670 | || TARGET_TPCS_FRAME || TARGET_TPCS_LEAF_FRAME) | |
23671 | { | |
23672 | fixed_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; | |
23673 | call_used_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; | |
23674 | if (TARGET_CALLER_INTERWORKING) | |
23675 | global_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; | |
23676 | } | |
23677 | SUBTARGET_CONDITIONAL_REGISTER_USAGE | |
23678 | } | |
23679 | ||
74e32076 | 23680 | static reg_class_t |
6d3fbe2f | 23681 | arm_preferred_rename_class (reg_class_t rclass) |
74e32076 YQ |
23682 | { |
23683 | /* Thumb-2 instructions using LO_REGS may be smaller than instructions | |
23684 | using GENERIC_REGS. During register rename pass, we prefer LO_REGS, | |
23685 | and code size can be reduced. */ | |
6d3fbe2f | 23686 | if (TARGET_THUMB2 && rclass == GENERAL_REGS) |
74e32076 YQ |
23687 | return LO_REGS; |
23688 | else | |
23689 | return NO_REGS; | |
23690 | } | |
23691 | ||
d3585b76 | 23692 | #include "gt-arm.h" |