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129a2fe4 1/* Output routines for GCC for ARM.
a941568e 2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
25f905c2 3 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
8cd42699 4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
ad87de1e 5 and Martin Simmons (@harleqn.co.uk).
129a2fe4 6 More major hacks by Richard Earnshaw (rearnsha@arm.com).
8cd42699 7
acf6ed70 8 This file is part of GCC.
8cd42699 9
acf6ed70 10 GCC is free software; you can redistribute it and/or modify it
11 under the terms of the GNU General Public License as published
12 by the Free Software Foundation; either version 2, or (at your
13 option) any later version.
8cd42699 14
acf6ed70 15 GCC is distributed in the hope that it will be useful, but WITHOUT
16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
18 License for more details.
8cd42699 19
acf6ed70 20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING. If not, write to
dbddc6c4 22 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
23 Boston, MA 02110-1301, USA. */
9e7454d0 24
6019008a 25#include "config.h"
76676c8e 26#include "system.h"
805e22b2 27#include "coretypes.h"
28#include "tm.h"
8cd42699 29#include "rtl.h"
cffb2a26 30#include "tree.h"
a220ccce 31#include "obstack.h"
8cd42699 32#include "regs.h"
33#include "hard-reg-set.h"
34#include "real.h"
35#include "insn-config.h"
36#include "conditions.h"
8cd42699 37#include "output.h"
38#include "insn-attr.h"
39#include "flags.h"
9c1b36a9 40#include "reload.h"
0a893c29 41#include "function.h"
411b0ddb 42#include "expr.h"
d8fc4d0b 43#include "optabs.h"
ecd3fcc7 44#include "toplev.h"
82ec49ae 45#include "recog.h"
db80f614 46#include "ggc.h"
cffb2a26 47#include "except.h"
1fcd08b1 48#include "c-pragma.h"
2d9065d3 49#include "integrate.h"
78fe751b 50#include "tm_p.h"
a767736d 51#include "target.h"
52#include "target-def.h"
37826745 53#include "debug.h"
e60d3615 54#include "langhooks.h"
3072d30e 55#include "df.h"
8cd42699 56
cffb2a26 57/* Forward definitions of types. */
58typedef struct minipool_node Mnode;
59typedef struct minipool_fixup Mfix;
60
a12be13c 61const struct attribute_spec arm_attribute_table[];
62
cffb2a26 63/* Forward function declarations. */
f9273c43 64static arm_stack_offsets *arm_get_frame_offsets (void);
ebd88a36 65static void arm_add_gc_roots (void);
96f57e36 66static int arm_gen_constant (enum rtx_code, enum machine_mode, rtx,
67 HOST_WIDE_INT, rtx, rtx, int, int);
ebd88a36 68static unsigned bit_count (unsigned long);
69static int arm_address_register_rtx_p (rtx, int);
b4e8a300 70static int arm_legitimate_index_p (enum machine_mode, rtx, RTX_CODE, int);
25f905c2 71static int thumb2_legitimate_index_p (enum machine_mode, rtx, int);
72static int thumb1_base_register_rtx_p (rtx, enum machine_mode, int);
73inline static int thumb1_index_register_rtx_p (rtx, int);
f9273c43 74static int thumb_far_jump_used_p (void);
237533cc 75static bool thumb_force_lr_save (void);
25f905c2 76static unsigned long thumb1_compute_save_reg_mask (void);
ebd88a36 77static int const_ok_for_op (HOST_WIDE_INT, enum rtx_code);
ebd88a36 78static rtx emit_sfm (int, int);
0858d94e 79static int arm_size_return_regs (void);
58356836 80#ifndef AOF_ASSEMBLER
ebd88a36 81static bool arm_assemble_integer (rtx, unsigned int, int);
58356836 82#endif
ebd88a36 83static const char *fp_const_from_val (REAL_VALUE_TYPE *);
84static arm_cc get_arm_condition_code (rtx);
ebd88a36 85static HOST_WIDE_INT int_log2 (HOST_WIDE_INT);
86static rtx is_jump_table (rtx);
87static const char *output_multi_immediate (rtx *, const char *, const char *,
88 int, HOST_WIDE_INT);
ebd88a36 89static const char *shift_op (rtx, HOST_WIDE_INT *);
90static struct machine_function *arm_init_machine_status (void);
4c44712e 91static void thumb_exit (FILE *, int);
ebd88a36 92static rtx is_jump_table (rtx);
93static HOST_WIDE_INT get_jump_table_size (rtx);
94static Mnode *move_minipool_fix_forward_ref (Mnode *, Mnode *, HOST_WIDE_INT);
95static Mnode *add_minipool_forward_ref (Mfix *);
96static Mnode *move_minipool_fix_backward_ref (Mnode *, Mnode *, HOST_WIDE_INT);
97static Mnode *add_minipool_backward_ref (Mfix *);
98static void assign_minipool_offsets (Mfix *);
99static void arm_print_value (FILE *, rtx);
100static void dump_minipool (rtx);
101static int arm_barrier_cost (rtx);
102static Mfix *create_fix_barrier (Mfix *, HOST_WIDE_INT);
103static void push_minipool_barrier (rtx, HOST_WIDE_INT);
104static void push_minipool_fix (rtx, HOST_WIDE_INT, rtx *, enum machine_mode,
105 rtx);
106static void arm_reorg (void);
107static bool note_invalid_constants (rtx, HOST_WIDE_INT, int);
ebd88a36 108static unsigned long arm_compute_save_reg0_reg12_mask (void);
109static unsigned long arm_compute_save_reg_mask (void);
110static unsigned long arm_isr_value (tree);
111static unsigned long arm_compute_func_type (void);
112static tree arm_handle_fndecl_attribute (tree *, tree, tree, int, bool *);
113static tree arm_handle_isr_attribute (tree *, tree, tree, int, bool *);
56826b58 114#if TARGET_DLLIMPORT_DECL_ATTRIBUTES
a79b1d93 115static tree arm_handle_notshared_attribute (tree *, tree, tree, int, bool *);
56826b58 116#endif
ebd88a36 117static void arm_output_function_epilogue (FILE *, HOST_WIDE_INT);
118static void arm_output_function_prologue (FILE *, HOST_WIDE_INT);
25f905c2 119static void thumb1_output_function_prologue (FILE *, HOST_WIDE_INT);
ebd88a36 120static int arm_comp_type_attributes (tree, tree);
121static void arm_set_default_type_attributes (tree);
122static int arm_adjust_cost (rtx, rtx, rtx, int);
ebd88a36 123static int count_insns_for_constant (HOST_WIDE_INT, int);
124static int arm_get_strip_length (int);
125static bool arm_function_ok_for_sibcall (tree, tree);
126static void arm_internal_label (FILE *, const char *, unsigned long);
127static void arm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT,
128 tree);
129static int arm_rtx_costs_1 (rtx, enum rtx_code, enum rtx_code);
c1877da8 130static bool arm_size_rtx_costs (rtx, int, int, int *);
a2cd141b 131static bool arm_slowmul_rtx_costs (rtx, int, int, int *);
132static bool arm_fastmul_rtx_costs (rtx, int, int, int *);
133static bool arm_xscale_rtx_costs (rtx, int, int, int *);
134static bool arm_9e_rtx_costs (rtx, int, int, int *);
ebd88a36 135static int arm_address_cost (rtx);
136static bool arm_memory_load_p (rtx);
137static bool arm_cirrus_insn_p (rtx);
138static void cirrus_reorg (rtx);
755eb2b4 139static void arm_init_builtins (void);
140static rtx arm_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
141static void arm_init_iwmmxt_builtins (void);
142static rtx safe_vector_operand (rtx, enum machine_mode);
143static rtx arm_expand_binop_builtin (enum insn_code, tree, rtx);
144static rtx arm_expand_unop_builtin (enum insn_code, tree, rtx, int);
145static rtx arm_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
96f57e36 146static void emit_constant_insn (rtx cond, rtx pattern);
0083a3b9 147static rtx emit_set_insn (rtx, rtx);
f054eb3c 148static int arm_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
149 tree, bool);
755eb2b4 150
d24bc145 151#ifdef OBJECT_FORMAT_ELF
bac7fc85 152static void arm_elf_asm_constructor (rtx, int) ATTRIBUTE_UNUSED;
153static void arm_elf_asm_destructor (rtx, int) ATTRIBUTE_UNUSED;
d24bc145 154#endif
7811991d 155#ifndef ARM_PE
ebd88a36 156static void arm_encode_section_info (tree, rtx, int);
7811991d 157#endif
afe27f3b 158
159static void arm_file_end (void);
5fad5123 160static void arm_file_start (void);
afe27f3b 161
67c1e638 162#ifdef AOF_ASSEMBLER
ebd88a36 163static void aof_globalize_label (FILE *, const char *);
164static void aof_dump_imports (FILE *);
165static void aof_dump_pic_table (FILE *);
92c473b8 166static void aof_file_start (void);
ebd88a36 167static void aof_file_end (void);
2f14b1f9 168static void aof_asm_init_sections (void);
67c1e638 169#endif
4c66acf1 170static void arm_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode,
171 tree, int *, int);
b981d932 172static bool arm_pass_by_reference (CUMULATIVE_ARGS *,
173 enum machine_mode, tree, bool);
72f1246c 174static bool arm_promote_prototypes (tree);
7faec15f 175static bool arm_default_short_enums (void);
25ba5be6 176static bool arm_align_anon_bitfield (void);
46b5d878 177static bool arm_return_in_msb (tree);
178static bool arm_must_pass_in_stack (enum machine_mode, tree);
1774763d 179#ifdef TARGET_UNWIND_INFO
180static void arm_unwind_emit (FILE *, rtx);
181static bool arm_output_ttype (rtx);
182#endif
25f905c2 183static void arm_dwarf_handle_frame_unspec (const char *, rtx, int);
747af5e7 184
c1dc02de 185static tree arm_cxx_guard_type (void);
186static bool arm_cxx_guard_mask_bit (void);
600f4be7 187static tree arm_get_cookie_size (tree);
188static bool arm_cookie_has_size (void);
853b7640 189static bool arm_cxx_cdtor_returns_this (void);
4fc9a8ec 190static bool arm_cxx_key_method_may_be_inline (void);
7908506d 191static void arm_cxx_determine_class_data_visibility (tree);
192static bool arm_cxx_class_data_always_comdat (void);
46b9ff5e 193static bool arm_cxx_use_aeabi_atexit (void);
30e9913f 194static void arm_init_libfuncs (void);
81f6de2f 195static bool arm_handle_option (size_t, const char *, int);
154ee3b8 196static void arm_target_help (void);
c49547c4 197static unsigned HOST_WIDE_INT arm_shift_truncation_mask (enum machine_mode);
f655717d 198static bool arm_cannot_copy_insn_p (rtx);
199static bool arm_tls_symbol_p (rtx x);
4471a482 200static void arm_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
f655717d 201
a767736d 202\f
203/* Initialize the GCC target structure. */
3aa0c315 204#if TARGET_DLLIMPORT_DECL_ATTRIBUTES
a12be13c 205#undef TARGET_MERGE_DECL_ATTRIBUTES
a767736d 206#define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
207#endif
a690ede2 208
a12be13c 209#undef TARGET_ATTRIBUTE_TABLE
e3c541f0 210#define TARGET_ATTRIBUTE_TABLE arm_attribute_table
a767736d 211
5fad5123 212#undef TARGET_ASM_FILE_START
213#define TARGET_ASM_FILE_START arm_file_start
afe27f3b 214#undef TARGET_ASM_FILE_END
215#define TARGET_ASM_FILE_END arm_file_end
216
58356836 217#ifdef AOF_ASSEMBLER
a12be13c 218#undef TARGET_ASM_BYTE_OP
58356836 219#define TARGET_ASM_BYTE_OP "\tDCB\t"
a12be13c 220#undef TARGET_ASM_ALIGNED_HI_OP
58356836 221#define TARGET_ASM_ALIGNED_HI_OP "\tDCW\t"
a12be13c 222#undef TARGET_ASM_ALIGNED_SI_OP
58356836 223#define TARGET_ASM_ALIGNED_SI_OP "\tDCD\t"
67c1e638 224#undef TARGET_ASM_GLOBALIZE_LABEL
225#define TARGET_ASM_GLOBALIZE_LABEL aof_globalize_label
92c473b8 226#undef TARGET_ASM_FILE_START
227#define TARGET_ASM_FILE_START aof_file_start
f6940372 228#undef TARGET_ASM_FILE_END
229#define TARGET_ASM_FILE_END aof_file_end
58356836 230#else
a12be13c 231#undef TARGET_ASM_ALIGNED_SI_OP
58356836 232#define TARGET_ASM_ALIGNED_SI_OP NULL
a12be13c 233#undef TARGET_ASM_INTEGER
58356836 234#define TARGET_ASM_INTEGER arm_assemble_integer
235#endif
236
a12be13c 237#undef TARGET_ASM_FUNCTION_PROLOGUE
17d9b0c3 238#define TARGET_ASM_FUNCTION_PROLOGUE arm_output_function_prologue
239
a12be13c 240#undef TARGET_ASM_FUNCTION_EPILOGUE
17d9b0c3 241#define TARGET_ASM_FUNCTION_EPILOGUE arm_output_function_epilogue
242
81f6de2f 243#undef TARGET_DEFAULT_TARGET_FLAGS
244#define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | MASK_SCHED_PROLOG)
245#undef TARGET_HANDLE_OPTION
246#define TARGET_HANDLE_OPTION arm_handle_option
154ee3b8 247#undef TARGET_HELP
248#define TARGET_HELP arm_target_help
81f6de2f 249
a12be13c 250#undef TARGET_COMP_TYPE_ATTRIBUTES
f32321da 251#define TARGET_COMP_TYPE_ATTRIBUTES arm_comp_type_attributes
252
a12be13c 253#undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
f32321da 254#define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES arm_set_default_type_attributes
255
a12be13c 256#undef TARGET_SCHED_ADJUST_COST
747af5e7 257#define TARGET_SCHED_ADJUST_COST arm_adjust_cost
258
7811991d 259#undef TARGET_ENCODE_SECTION_INFO
260#ifdef ARM_PE
261#define TARGET_ENCODE_SECTION_INFO arm_pe_encode_section_info
262#else
263#define TARGET_ENCODE_SECTION_INFO arm_encode_section_info
264#endif
265
755eb2b4 266#undef TARGET_STRIP_NAME_ENCODING
7b4a38a6 267#define TARGET_STRIP_NAME_ENCODING arm_strip_name_encoding
268
755eb2b4 269#undef TARGET_ASM_INTERNAL_LABEL
805e22b2 270#define TARGET_ASM_INTERNAL_LABEL arm_internal_label
271
755eb2b4 272#undef TARGET_FUNCTION_OK_FOR_SIBCALL
805e22b2 273#define TARGET_FUNCTION_OK_FOR_SIBCALL arm_function_ok_for_sibcall
274
755eb2b4 275#undef TARGET_ASM_OUTPUT_MI_THUNK
6988553d 276#define TARGET_ASM_OUTPUT_MI_THUNK arm_output_mi_thunk
755eb2b4 277#undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
eb344f43 278#define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
6988553d 279
a2cd141b 280/* This will be overridden in arm_override_options. */
755eb2b4 281#undef TARGET_RTX_COSTS
a2cd141b 282#define TARGET_RTX_COSTS arm_slowmul_rtx_costs
755eb2b4 283#undef TARGET_ADDRESS_COST
ec0457a8 284#define TARGET_ADDRESS_COST arm_address_cost
fab7adbf 285
c49547c4 286#undef TARGET_SHIFT_TRUNCATION_MASK
287#define TARGET_SHIFT_TRUNCATION_MASK arm_shift_truncation_mask
9e7454d0 288#undef TARGET_VECTOR_MODE_SUPPORTED_P
289#define TARGET_VECTOR_MODE_SUPPORTED_P arm_vector_mode_supported_p
290
755eb2b4 291#undef TARGET_MACHINE_DEPENDENT_REORG
2efea8c0 292#define TARGET_MACHINE_DEPENDENT_REORG arm_reorg
293
755eb2b4 294#undef TARGET_INIT_BUILTINS
295#define TARGET_INIT_BUILTINS arm_init_builtins
296#undef TARGET_EXPAND_BUILTIN
297#define TARGET_EXPAND_BUILTIN arm_expand_builtin
298
30e9913f 299#undef TARGET_INIT_LIBFUNCS
300#define TARGET_INIT_LIBFUNCS arm_init_libfuncs
301
f2eb2b4d 302#undef TARGET_PROMOTE_FUNCTION_ARGS
303#define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
19347327 304#undef TARGET_PROMOTE_FUNCTION_RETURN
305#define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
f2eb2b4d 306#undef TARGET_PROMOTE_PROTOTYPES
72f1246c 307#define TARGET_PROMOTE_PROTOTYPES arm_promote_prototypes
b981d932 308#undef TARGET_PASS_BY_REFERENCE
309#define TARGET_PASS_BY_REFERENCE arm_pass_by_reference
f054eb3c 310#undef TARGET_ARG_PARTIAL_BYTES
311#define TARGET_ARG_PARTIAL_BYTES arm_arg_partial_bytes
f2eb2b4d 312
4c66acf1 313#undef TARGET_SETUP_INCOMING_VARARGS
314#define TARGET_SETUP_INCOMING_VARARGS arm_setup_incoming_varargs
315
7faec15f 316#undef TARGET_DEFAULT_SHORT_ENUMS
317#define TARGET_DEFAULT_SHORT_ENUMS arm_default_short_enums
318
25ba5be6 319#undef TARGET_ALIGN_ANON_BITFIELD
320#define TARGET_ALIGN_ANON_BITFIELD arm_align_anon_bitfield
321
5f458503 322#undef TARGET_NARROW_VOLATILE_BITFIELD
323#define TARGET_NARROW_VOLATILE_BITFIELD hook_bool_void_false
324
c1dc02de 325#undef TARGET_CXX_GUARD_TYPE
326#define TARGET_CXX_GUARD_TYPE arm_cxx_guard_type
327
328#undef TARGET_CXX_GUARD_MASK_BIT
329#define TARGET_CXX_GUARD_MASK_BIT arm_cxx_guard_mask_bit
330
600f4be7 331#undef TARGET_CXX_GET_COOKIE_SIZE
332#define TARGET_CXX_GET_COOKIE_SIZE arm_get_cookie_size
333
334#undef TARGET_CXX_COOKIE_HAS_SIZE
335#define TARGET_CXX_COOKIE_HAS_SIZE arm_cookie_has_size
336
853b7640 337#undef TARGET_CXX_CDTOR_RETURNS_THIS
338#define TARGET_CXX_CDTOR_RETURNS_THIS arm_cxx_cdtor_returns_this
339
4fc9a8ec 340#undef TARGET_CXX_KEY_METHOD_MAY_BE_INLINE
341#define TARGET_CXX_KEY_METHOD_MAY_BE_INLINE arm_cxx_key_method_may_be_inline
342
46b9ff5e 343#undef TARGET_CXX_USE_AEABI_ATEXIT
344#define TARGET_CXX_USE_AEABI_ATEXIT arm_cxx_use_aeabi_atexit
345
7908506d 346#undef TARGET_CXX_DETERMINE_CLASS_DATA_VISIBILITY
347#define TARGET_CXX_DETERMINE_CLASS_DATA_VISIBILITY \
348 arm_cxx_determine_class_data_visibility
349
350#undef TARGET_CXX_CLASS_DATA_ALWAYS_COMDAT
351#define TARGET_CXX_CLASS_DATA_ALWAYS_COMDAT arm_cxx_class_data_always_comdat
4fc9a8ec 352
46b5d878 353#undef TARGET_RETURN_IN_MSB
354#define TARGET_RETURN_IN_MSB arm_return_in_msb
355
356#undef TARGET_MUST_PASS_IN_STACK
357#define TARGET_MUST_PASS_IN_STACK arm_must_pass_in_stack
358
1774763d 359#ifdef TARGET_UNWIND_INFO
360#undef TARGET_UNWIND_EMIT
361#define TARGET_UNWIND_EMIT arm_unwind_emit
362
363/* EABI unwinding tables use a different format for the typeinfo tables. */
364#undef TARGET_ASM_TTYPE
365#define TARGET_ASM_TTYPE arm_output_ttype
366
367#undef TARGET_ARM_EABI_UNWINDER
368#define TARGET_ARM_EABI_UNWINDER true
369#endif /* TARGET_UNWIND_INFO */
370
25f905c2 371#undef TARGET_DWARF_HANDLE_FRAME_UNSPEC
372#define TARGET_DWARF_HANDLE_FRAME_UNSPEC arm_dwarf_handle_frame_unspec
373
f655717d 374#undef TARGET_CANNOT_COPY_INSN_P
375#define TARGET_CANNOT_COPY_INSN_P arm_cannot_copy_insn_p
376
377#ifdef HAVE_AS_TLS
378#undef TARGET_HAVE_TLS
379#define TARGET_HAVE_TLS true
380#endif
381
382#undef TARGET_CANNOT_FORCE_CONST_MEM
e348ff3e 383#define TARGET_CANNOT_FORCE_CONST_MEM arm_cannot_force_const_mem
f655717d 384
eddcdde1 385#undef TARGET_MANGLE_TYPE
386#define TARGET_MANGLE_TYPE arm_mangle_type
387
4471a482 388#ifdef HAVE_AS_TLS
389#undef TARGET_ASM_OUTPUT_DWARF_DTPREL
390#define TARGET_ASM_OUTPUT_DWARF_DTPREL arm_output_dwarf_dtprel
391#endif
392
57e4bbfb 393struct gcc_target targetm = TARGET_INITIALIZER;
a767736d 394\f
a220ccce 395/* Obstack for minipool constant handling. */
396static struct obstack minipool_obstack;
a12be13c 397static char * minipool_startobj;
a220ccce 398
a12be13c 399/* The maximum number of insns skipped which
400 will be conditionalised if possible. */
78fe751b 401static int max_insns_skipped = 5;
402
403extern FILE * asm_out_file;
404
66aacf41 405/* True if we are currently building a constant table. */
c9ba03f2 406int making_const_table;
407
2485f877 408/* Define the information needed to generate branch insns. This is
66aacf41 409 stored from the compare operation. */
9c08d1fa 410rtx arm_compare_op0, arm_compare_op1;
9c08d1fa 411
a2cd141b 412/* The processor for which instructions should be scheduled. */
413enum processor_type arm_tune = arm_none;
414
fa7637bd 415/* The default processor used if not overridden by commandline. */
5fad5123 416static enum processor_type arm_default_cpu = arm_none;
417
a2cd141b 418/* Which floating point model to use. */
419enum arm_fp_model arm_fp_model;
411b0ddb 420
a2cd141b 421/* Which floating point hardware is available. */
c7f506fd 422enum fputype arm_fpu_arch;
f21249d5 423
a2cd141b 424/* Which floating point hardware to schedule for. */
425enum fputype arm_fpu_tune;
426
427/* Whether to use floating point hardware. */
428enum float_abi_type arm_float_abi;
429
f9273c43 430/* Which ABI to use. */
431enum arm_abi_type arm_abi;
432
f655717d 433/* Which thread pointer model to use. */
434enum arm_tp_type target_thread_pointer = TP_AUTO;
435
6cd47762 436/* Used to parse -mstructure_size_boundary command line option. */
8fa0c55d 437int arm_structure_size_boundary = DEFAULT_STRUCTURE_SIZE_BOUNDARY;
6cd47762 438
afe27f3b 439/* Used for Thumb call_via trampolines. */
a52972b8 440rtx thumb_call_via_label[14];
afe27f3b 441static int thumb_call_reg_needed;
442
82ec49ae 443/* Bit values used to identify processor capabilities. */
bba10fb8 444#define FL_CO_PROC (1 << 0) /* Has external co-processor bus */
a2cd141b 445#define FL_ARCH3M (1 << 1) /* Extended multiply */
bba10fb8 446#define FL_MODE26 (1 << 2) /* 26-bit mode support */
447#define FL_MODE32 (1 << 3) /* 32-bit mode support */
448#define FL_ARCH4 (1 << 4) /* Architecture rel 4 */
449#define FL_ARCH5 (1 << 5) /* Architecture rel 5 */
450#define FL_THUMB (1 << 6) /* Thumb aware */
451#define FL_LDSCHED (1 << 7) /* Load scheduling necessary */
452#define FL_STRONG (1 << 8) /* StrongARM */
b89db9a7 453#define FL_ARCH5E (1 << 9) /* DSP extensions to v5 */
331beb1a 454#define FL_XSCALE (1 << 10) /* XScale */
7d57ec45 455#define FL_CIRRUS (1 << 11) /* Cirrus/DSP. */
a2cd141b 456#define FL_ARCH6 (1 << 12) /* Architecture rel 6. Adds
2515f61d 457 media instructions. */
458#define FL_VFPV2 (1 << 13) /* Vector Floating Point V2. */
74a71f7d 459#define FL_WBUF (1 << 14) /* Schedule for write buffer ops.
460 Note: ARM6 & 7 derivatives only. */
f655717d 461#define FL_ARCH6K (1 << 15) /* Architecture rel 6 K extensions. */
25f905c2 462#define FL_THUMB2 (1 << 16) /* Thumb-2. */
463#define FL_NOTM (1 << 17) /* Instructions not present in the 'M'
464 profile. */
542d5028 465#define FL_DIV (1 << 18) /* Hardware divide. */
b5a0636d 466#define FL_VFPV3 (1 << 19) /* Vector Floating Point V3. */
d98a3884 467#define FL_NEON (1 << 20) /* Neon instructions. */
82ec49ae 468
a2cd141b 469#define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */
470
25f905c2 471#define FL_FOR_ARCH2 FL_NOTM
472#define FL_FOR_ARCH3 (FL_FOR_ARCH2 | FL_MODE32)
e65e4284 473#define FL_FOR_ARCH3M (FL_FOR_ARCH3 | FL_ARCH3M)
474#define FL_FOR_ARCH4 (FL_FOR_ARCH3M | FL_ARCH4)
475#define FL_FOR_ARCH4T (FL_FOR_ARCH4 | FL_THUMB)
476#define FL_FOR_ARCH5 (FL_FOR_ARCH4 | FL_ARCH5)
477#define FL_FOR_ARCH5T (FL_FOR_ARCH5 | FL_THUMB)
478#define FL_FOR_ARCH5E (FL_FOR_ARCH5 | FL_ARCH5E)
479#define FL_FOR_ARCH5TE (FL_FOR_ARCH5E | FL_THUMB)
480#define FL_FOR_ARCH5TEJ FL_FOR_ARCH5TE
481#define FL_FOR_ARCH6 (FL_FOR_ARCH5TE | FL_ARCH6)
482#define FL_FOR_ARCH6J FL_FOR_ARCH6
f655717d 483#define FL_FOR_ARCH6K (FL_FOR_ARCH6 | FL_ARCH6K)
6b4d6063 484#define FL_FOR_ARCH6Z FL_FOR_ARCH6
f655717d 485#define FL_FOR_ARCH6ZK FL_FOR_ARCH6K
25f905c2 486#define FL_FOR_ARCH6T2 (FL_FOR_ARCH6 | FL_THUMB2)
487#define FL_FOR_ARCH7 (FL_FOR_ARCH6T2 &~ FL_NOTM)
488#define FL_FOR_ARCH7A (FL_FOR_ARCH7 | FL_NOTM)
489#define FL_FOR_ARCH7R (FL_FOR_ARCH7A | FL_DIV)
490#define FL_FOR_ARCH7M (FL_FOR_ARCH7 | FL_DIV)
e65e4284 491
a12be13c 492/* The bits in this mask specify which
493 instructions we are allowed to generate. */
a7712927 494static unsigned long insn_flags = 0;
cffb2a26 495
82ec49ae 496/* The bits in this mask specify which instruction scheduling options should
a2cd141b 497 be used. */
a7712927 498static unsigned long tune_flags = 0;
82ec49ae 499
500/* The following are used in the arm.md file as equivalents to bits
501 in the above two flag variables. */
502
a2cd141b 503/* Nonzero if this chip supports the ARM Architecture 3M extensions. */
504int arm_arch3m = 0;
64266206 505
66aacf41 506/* Nonzero if this chip supports the ARM Architecture 4 extensions. */
64266206 507int arm_arch4 = 0;
508
f1039640 509/* Nonzero if this chip supports the ARM Architecture 4t extensions. */
510int arm_arch4t = 0;
511
66aacf41 512/* Nonzero if this chip supports the ARM Architecture 5 extensions. */
bba10fb8 513int arm_arch5 = 0;
514
e1159bbe 515/* Nonzero if this chip supports the ARM Architecture 5E extensions. */
516int arm_arch5e = 0;
517
a2cd141b 518/* Nonzero if this chip supports the ARM Architecture 6 extensions. */
519int arm_arch6 = 0;
520
f655717d 521/* Nonzero if this chip supports the ARM 6K extensions. */
522int arm_arch6k = 0;
523
25f905c2 524/* Nonzero if instructions not present in the 'M' profile can be used. */
525int arm_arch_notm = 0;
526
82ec49ae 527/* Nonzero if this chip can benefit from load scheduling. */
9888ad6d 528int arm_ld_sched = 0;
529
530/* Nonzero if this chip is a StrongARM. */
74a71f7d 531int arm_tune_strongarm = 0;
9888ad6d 532
e65e4284 533/* Nonzero if this chip is a Cirrus variant. */
534int arm_arch_cirrus = 0;
535
755eb2b4 536/* Nonzero if this chip supports Intel Wireless MMX technology. */
537int arm_arch_iwmmxt = 0;
538
331beb1a 539/* Nonzero if this chip is an XScale. */
f8e17552 540int arm_arch_xscale = 0;
541
542/* Nonzero if tuning for XScale */
543int arm_tune_xscale = 0;
331beb1a 544
a60f1840 545/* Nonzero if we want to tune for stores that access the write-buffer.
bf2fbc3d 546 This typically means an ARM6 or ARM7 with MMU or MPU. */
74a71f7d 547int arm_tune_wbuf = 0;
f21249d5 548
1c494086 549/* Nonzero if generating Thumb instructions. */
550int thumb_code = 0;
551
80b6339a 552/* Nonzero if we should define __THUMB_INTERWORK__ in the
9e7454d0 553 preprocessor.
80b6339a 554 XXX This is a bit of a hack, it's intended to help work around
555 problems in GLD which doesn't understand that armv5t code is
556 interworking clean. */
557int arm_cpp_interwork = 0;
558
25f905c2 559/* Nonzero if chip supports Thumb 2. */
560int arm_arch_thumb2;
561
562/* Nonzero if chip supports integer division instruction. */
563int arm_arch_hwdiv;
564
8cd42699 565/* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we
566 must report the mode of the memory reference from PRINT_OPERAND to
567 PRINT_OPERAND_ADDRESS. */
a690ede2 568enum machine_mode output_memory_reference_mode;
8cd42699 569
69120d26 570/* The register number to be used for the PIC offset register. */
2cb7d577 571unsigned arm_pic_register = INVALID_REGNUM;
69120d26 572
9c08d1fa 573/* Set to 1 when a return insn is output, this means that the epilogue
66aacf41 574 is not needed. */
cffb2a26 575int return_used_this_function;
9c08d1fa 576
82ec49ae 577/* Set to 1 after arm_reorg has started. Reset to start at the start of
578 the next function. */
11de4c7f 579static int after_arm_reorg = 0;
580
82ec49ae 581/* The maximum number of insns to be used when loading a constant. */
64266206 582static int arm_constant_limit = 3;
583
8cd42699 584/* For an explanation of these variables, see final_prescan_insn below. */
585int arm_ccfsm_state;
25f905c2 586/* arm_current_cc is also used for Thumb-2 cond_exec blocks. */
1275b964 587enum arm_cond_code arm_current_cc;
8cd42699 588rtx arm_target_insn;
589int arm_target_label;
25f905c2 590/* The number of conditionally executed insns, including the current insn. */
591int arm_condexec_count = 0;
592/* A bitmask specifying the patterns for the IT block.
593 Zero means do not output an IT block before this insn. */
594int arm_condexec_mask = 0;
595/* The number of bits used in arm_condexec_mask. */
596int arm_condexec_masklen = 0;
f6b01912 597
598/* The condition codes of the ARM, and the inverse function. */
a12be13c 599static const char * const arm_condition_codes[] =
f6b01912 600{
601 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
602 "hi", "ls", "ge", "lt", "gt", "le", "al", "nv"
603};
604
25f905c2 605#define ARM_LSL_NAME (TARGET_UNIFIED_ASM ? "lsl" : "asl")
9888ad6d 606#define streq(string1, string2) (strcmp (string1, string2) == 0)
25f905c2 607
608#define THUMB2_WORK_REGS (0xff & ~( (1 << THUMB_HARD_FRAME_POINTER_REGNUM) \
609 | (1 << SP_REGNUM) | (1 << PC_REGNUM) \
610 | (1 << PIC_OFFSET_TABLE_REGNUM)))
64266206 611\f
66aacf41 612/* Initialization code. */
64266206 613
64266206 614struct processors
615{
e99c3a1d 616 const char *const name;
a2cd141b 617 enum processor_type core;
e65e4284 618 const char *arch;
a7712927 619 const unsigned long flags;
a2cd141b 620 bool (* rtx_costs) (rtx, int, int, int *);
64266206 621};
622
623/* Not all of these give usefully different compilation alternatives,
624 but there is no simple way of generalizing them. */
e99c3a1d 625static const struct processors all_cores[] =
9888ad6d 626{
627 /* ARM Cores */
61b58075 628#define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
629 {NAME, arm_none, #ARCH, FLAGS | FL_FOR_ARCH##ARCH, arm_##COSTS##_rtx_costs},
a2cd141b 630#include "arm-cores.def"
631#undef ARM_CORE
e65e4284 632 {NULL, arm_none, NULL, 0, NULL}
9888ad6d 633};
634
e99c3a1d 635static const struct processors all_architectures[] =
64266206 636{
9888ad6d 637 /* ARM Architectures */
a2cd141b 638 /* We don't specify rtx_costs here as it will be figured out
639 from the core. */
9e7454d0 640
e65e4284 641 {"armv2", arm2, "2", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2, NULL},
642 {"armv2a", arm2, "2", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2, NULL},
643 {"armv3", arm6, "3", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3, NULL},
644 {"armv3m", arm7m, "3M", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3M, NULL},
645 {"armv4", arm7tdmi, "4", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH4, NULL},
f21249d5 646 /* Strictly, FL_MODE26 is a permitted option for v4t, but there are no
647 implementations that support it, so we will leave it out for now. */
e65e4284 648 {"armv4t", arm7tdmi, "4T", FL_CO_PROC | FL_FOR_ARCH4T, NULL},
649 {"armv5", arm10tdmi, "5", FL_CO_PROC | FL_FOR_ARCH5, NULL},
650 {"armv5t", arm10tdmi, "5T", FL_CO_PROC | FL_FOR_ARCH5T, NULL},
651 {"armv5e", arm1026ejs, "5E", FL_CO_PROC | FL_FOR_ARCH5E, NULL},
652 {"armv5te", arm1026ejs, "5TE", FL_CO_PROC | FL_FOR_ARCH5TE, NULL},
653 {"armv6", arm1136js, "6", FL_CO_PROC | FL_FOR_ARCH6, NULL},
654 {"armv6j", arm1136js, "6J", FL_CO_PROC | FL_FOR_ARCH6J, NULL},
6b4d6063 655 {"armv6k", mpcore, "6K", FL_CO_PROC | FL_FOR_ARCH6K, NULL},
656 {"armv6z", arm1176jzs, "6Z", FL_CO_PROC | FL_FOR_ARCH6Z, NULL},
657 {"armv6zk", arm1176jzs, "6ZK", FL_CO_PROC | FL_FOR_ARCH6ZK, NULL},
25f905c2 658 {"armv6t2", arm1156t2s, "6T2", FL_CO_PROC | FL_FOR_ARCH6T2, NULL},
659 {"armv7", cortexa8, "7", FL_CO_PROC | FL_FOR_ARCH7, NULL},
660 {"armv7-a", cortexa8, "7A", FL_CO_PROC | FL_FOR_ARCH7A, NULL},
661 {"armv7-r", cortexr4, "7R", FL_CO_PROC | FL_FOR_ARCH7R, NULL},
662 {"armv7-m", cortexm3, "7M", FL_CO_PROC | FL_FOR_ARCH7M, NULL},
e65e4284 663 {"ep9312", ep9312, "4T", FL_LDSCHED | FL_CIRRUS | FL_FOR_ARCH4, NULL},
664 {"iwmmxt", iwmmxt, "5TE", FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT , NULL},
665 {NULL, arm_none, NULL, 0 , NULL}
9888ad6d 666};
667
81f6de2f 668struct arm_cpu_select
669{
670 const char * string;
671 const char * name;
672 const struct processors * processors;
673};
674
8d232dc7 675/* This is a magic structure. The 'string' field is magically filled in
9888ad6d 676 with a pointer to the value specified by the user on the command line
677 assuming that the user has specified such a value. */
678
81f6de2f 679static struct arm_cpu_select arm_select[] =
9888ad6d 680{
9e7454d0 681 /* string name processors */
9888ad6d 682 { NULL, "-mcpu=", all_cores },
683 { NULL, "-march=", all_architectures },
684 { NULL, "-mtune=", all_cores }
64266206 685};
686
c37752cc 687/* Defines representing the indexes into the above table. */
688#define ARM_OPT_SET_CPU 0
689#define ARM_OPT_SET_ARCH 1
690#define ARM_OPT_SET_TUNE 2
e65e4284 691
15b00d63 692/* The name of the preprocessor macro to define for this architecture. */
e65e4284 693
694char arm_arch_name[] = "__ARM_ARCH_0UNK__";
695
a2cd141b 696struct fpu_desc
697{
698 const char * name;
699 enum fputype fpu;
700};
701
702
cb4213cd 703/* Available values for -mfpu=. */
a2cd141b 704
705static const struct fpu_desc all_fpus[] =
706{
707 {"fpa", FPUTYPE_FPA},
708 {"fpe2", FPUTYPE_FPA_EMU2},
709 {"fpe3", FPUTYPE_FPA_EMU2},
710 {"maverick", FPUTYPE_MAVERICK},
b5a0636d 711 {"vfp", FPUTYPE_VFP},
712 {"vfp3", FPUTYPE_VFP3},
d98a3884 713 {"neon", FPUTYPE_NEON}
a2cd141b 714};
715
716
717/* Floating point models used by the different hardware.
718 See fputype in arm.h. */
719
720static const enum fputype fp_model_for_fpu[] =
721{
722 /* No FP hardware. */
723 ARM_FP_MODEL_UNKNOWN, /* FPUTYPE_NONE */
724 ARM_FP_MODEL_FPA, /* FPUTYPE_FPA */
725 ARM_FP_MODEL_FPA, /* FPUTYPE_FPA_EMU2 */
726 ARM_FP_MODEL_FPA, /* FPUTYPE_FPA_EMU3 */
727 ARM_FP_MODEL_MAVERICK, /* FPUTYPE_MAVERICK */
b5a0636d 728 ARM_FP_MODEL_VFP, /* FPUTYPE_VFP */
d98a3884 729 ARM_FP_MODEL_VFP, /* FPUTYPE_VFP3 */
730 ARM_FP_MODEL_VFP /* FPUTYPE_NEON */
a2cd141b 731};
732
733
734struct float_abi
735{
736 const char * name;
737 enum float_abi_type abi_type;
738};
739
740
741/* Available values for -mfloat-abi=. */
742
743static const struct float_abi all_float_abis[] =
744{
745 {"soft", ARM_FLOAT_ABI_SOFT},
746 {"softfp", ARM_FLOAT_ABI_SOFTFP},
747 {"hard", ARM_FLOAT_ABI_HARD}
748};
749
750
f9273c43 751struct abi_name
752{
753 const char *name;
754 enum arm_abi_type abi_type;
755};
756
757
758/* Available values for -mabi=. */
759
760static const struct abi_name arm_all_abis[] =
761{
762 {"apcs-gnu", ARM_ABI_APCS},
763 {"atpcs", ARM_ABI_ATPCS},
764 {"aapcs", ARM_ABI_AAPCS},
6783d878 765 {"iwmmxt", ARM_ABI_IWMMXT},
766 {"aapcs-linux", ARM_ABI_AAPCS_LINUX}
f9273c43 767};
768
f655717d 769/* Supported TLS relocations. */
770
771enum tls_reloc {
772 TLS_GD32,
773 TLS_LDM32,
774 TLS_LDO32,
775 TLS_IE32,
776 TLS_LE32
777};
778
0083a3b9 779/* Emit an insn that's a simple single-set. Both the operands must be known
780 to be valid. */
781inline static rtx
782emit_set_insn (rtx x, rtx y)
783{
784 return emit_insn (gen_rtx_SET (VOIDmode, x, y));
785}
786
a7712927 787/* Return the number of bits set in VALUE. */
788static unsigned
ebd88a36 789bit_count (unsigned long value)
82ec49ae 790{
cffb2a26 791 unsigned long count = 0;
9e7454d0 792
82ec49ae 793 while (value)
794 {
a7712927 795 count++;
796 value &= value - 1; /* Clear the least-significant set bit. */
82ec49ae 797 }
798
799 return count;
800}
801
84cbcde5 802/* Set up library functions unique to ARM. */
30e9913f 803
804static void
805arm_init_libfuncs (void)
806{
807 /* There are no special library functions unless we are using the
808 ARM BPABI. */
809 if (!TARGET_BPABI)
810 return;
811
812 /* The functions below are described in Section 4 of the "Run-Time
813 ABI for the ARM architecture", Version 1.0. */
814
815 /* Double-precision floating-point arithmetic. Table 2. */
816 set_optab_libfunc (add_optab, DFmode, "__aeabi_dadd");
817 set_optab_libfunc (sdiv_optab, DFmode, "__aeabi_ddiv");
818 set_optab_libfunc (smul_optab, DFmode, "__aeabi_dmul");
819 set_optab_libfunc (neg_optab, DFmode, "__aeabi_dneg");
820 set_optab_libfunc (sub_optab, DFmode, "__aeabi_dsub");
821
84cbcde5 822 /* Double-precision comparisons. Table 3. */
30e9913f 823 set_optab_libfunc (eq_optab, DFmode, "__aeabi_dcmpeq");
824 set_optab_libfunc (ne_optab, DFmode, NULL);
825 set_optab_libfunc (lt_optab, DFmode, "__aeabi_dcmplt");
826 set_optab_libfunc (le_optab, DFmode, "__aeabi_dcmple");
827 set_optab_libfunc (ge_optab, DFmode, "__aeabi_dcmpge");
828 set_optab_libfunc (gt_optab, DFmode, "__aeabi_dcmpgt");
829 set_optab_libfunc (unord_optab, DFmode, "__aeabi_dcmpun");
830
831 /* Single-precision floating-point arithmetic. Table 4. */
832 set_optab_libfunc (add_optab, SFmode, "__aeabi_fadd");
833 set_optab_libfunc (sdiv_optab, SFmode, "__aeabi_fdiv");
834 set_optab_libfunc (smul_optab, SFmode, "__aeabi_fmul");
835 set_optab_libfunc (neg_optab, SFmode, "__aeabi_fneg");
836 set_optab_libfunc (sub_optab, SFmode, "__aeabi_fsub");
9e7454d0 837
84cbcde5 838 /* Single-precision comparisons. Table 5. */
30e9913f 839 set_optab_libfunc (eq_optab, SFmode, "__aeabi_fcmpeq");
840 set_optab_libfunc (ne_optab, SFmode, NULL);
841 set_optab_libfunc (lt_optab, SFmode, "__aeabi_fcmplt");
842 set_optab_libfunc (le_optab, SFmode, "__aeabi_fcmple");
843 set_optab_libfunc (ge_optab, SFmode, "__aeabi_fcmpge");
844 set_optab_libfunc (gt_optab, SFmode, "__aeabi_fcmpgt");
845 set_optab_libfunc (unord_optab, SFmode, "__aeabi_fcmpun");
846
847 /* Floating-point to integer conversions. Table 6. */
848 set_conv_libfunc (sfix_optab, SImode, DFmode, "__aeabi_d2iz");
849 set_conv_libfunc (ufix_optab, SImode, DFmode, "__aeabi_d2uiz");
850 set_conv_libfunc (sfix_optab, DImode, DFmode, "__aeabi_d2lz");
851 set_conv_libfunc (ufix_optab, DImode, DFmode, "__aeabi_d2ulz");
852 set_conv_libfunc (sfix_optab, SImode, SFmode, "__aeabi_f2iz");
853 set_conv_libfunc (ufix_optab, SImode, SFmode, "__aeabi_f2uiz");
854 set_conv_libfunc (sfix_optab, DImode, SFmode, "__aeabi_f2lz");
855 set_conv_libfunc (ufix_optab, DImode, SFmode, "__aeabi_f2ulz");
856
857 /* Conversions between floating types. Table 7. */
858 set_conv_libfunc (trunc_optab, SFmode, DFmode, "__aeabi_d2f");
859 set_conv_libfunc (sext_optab, DFmode, SFmode, "__aeabi_f2d");
860
84cbcde5 861 /* Integer to floating-point conversions. Table 8. */
30e9913f 862 set_conv_libfunc (sfloat_optab, DFmode, SImode, "__aeabi_i2d");
863 set_conv_libfunc (ufloat_optab, DFmode, SImode, "__aeabi_ui2d");
864 set_conv_libfunc (sfloat_optab, DFmode, DImode, "__aeabi_l2d");
865 set_conv_libfunc (ufloat_optab, DFmode, DImode, "__aeabi_ul2d");
866 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__aeabi_i2f");
867 set_conv_libfunc (ufloat_optab, SFmode, SImode, "__aeabi_ui2f");
868 set_conv_libfunc (sfloat_optab, SFmode, DImode, "__aeabi_l2f");
869 set_conv_libfunc (ufloat_optab, SFmode, DImode, "__aeabi_ul2f");
870
871 /* Long long. Table 9. */
872 set_optab_libfunc (smul_optab, DImode, "__aeabi_lmul");
873 set_optab_libfunc (sdivmod_optab, DImode, "__aeabi_ldivmod");
874 set_optab_libfunc (udivmod_optab, DImode, "__aeabi_uldivmod");
875 set_optab_libfunc (ashl_optab, DImode, "__aeabi_llsl");
876 set_optab_libfunc (lshr_optab, DImode, "__aeabi_llsr");
877 set_optab_libfunc (ashr_optab, DImode, "__aeabi_lasr");
878 set_optab_libfunc (cmp_optab, DImode, "__aeabi_lcmp");
879 set_optab_libfunc (ucmp_optab, DImode, "__aeabi_ulcmp");
880
881 /* Integer (32/32->32) division. \S 4.3.1. */
882 set_optab_libfunc (sdivmod_optab, SImode, "__aeabi_idivmod");
883 set_optab_libfunc (udivmod_optab, SImode, "__aeabi_uidivmod");
884
885 /* The divmod functions are designed so that they can be used for
886 plain division, even though they return both the quotient and the
887 remainder. The quotient is returned in the usual location (i.e.,
888 r0 for SImode, {r0, r1} for DImode), just as would be expected
889 for an ordinary division routine. Because the AAPCS calling
890 conventions specify that all of { r0, r1, r2, r3 } are
891 callee-saved registers, there is no need to tell the compiler
892 explicitly that those registers are clobbered by these
893 routines. */
894 set_optab_libfunc (sdiv_optab, DImode, "__aeabi_ldivmod");
895 set_optab_libfunc (udiv_optab, DImode, "__aeabi_uldivmod");
3da35908 896
897 /* For SImode division the ABI provides div-without-mod routines,
898 which are faster. */
899 set_optab_libfunc (sdiv_optab, SImode, "__aeabi_idiv");
900 set_optab_libfunc (udiv_optab, SImode, "__aeabi_uidiv");
b027ddbf 901
902 /* We don't have mod libcalls. Fortunately gcc knows how to use the
903 divmod libcalls instead. */
904 set_optab_libfunc (smod_optab, DImode, NULL);
905 set_optab_libfunc (umod_optab, DImode, NULL);
906 set_optab_libfunc (smod_optab, SImode, NULL);
907 set_optab_libfunc (umod_optab, SImode, NULL);
30e9913f 908}
909
81f6de2f 910/* Implement TARGET_HANDLE_OPTION. */
911
912static bool
913arm_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
914{
915 switch (code)
916 {
81f6de2f 917 case OPT_march_:
918 arm_select[1].string = arg;
919 return true;
920
921 case OPT_mcpu_:
922 arm_select[0].string = arg;
923 return true;
924
81f6de2f 925 case OPT_mhard_float:
926 target_float_abi_name = "hard";
927 return true;
928
81f6de2f 929 case OPT_msoft_float:
930 target_float_abi_name = "soft";
931 return true;
932
81f6de2f 933 case OPT_mtune_:
934 arm_select[2].string = arg;
935 return true;
936
937 default:
938 return true;
939 }
940}
941
154ee3b8 942static void
943arm_target_help (void)
944{
945 int i;
946 static int columns = 0;
947 int remaining;
948
949 /* If we have not done so already, obtain the desired maximum width of
950 the output. Note - this is a duplication of the code at the start of
951 gcc/opts.c:print_specific_help() - the two copies should probably be
952 replaced by a single function. */
953 if (columns == 0)
954 {
955 const char *p;
956
957 GET_ENVIRONMENT (p, "COLUMNS");
958 if (p != NULL)
959 {
960 int value = atoi (p);
961
962 if (value > 0)
963 columns = value;
964 }
965
966 if (columns == 0)
967 /* Use a reasonable default. */
968 columns = 80;
969 }
970
971 printf (" Known ARM CPUs (for use with the -mcpu= and -mtune= options):\n");
972
973 /* The - 2 is because we know that the last entry in the array is NULL. */
974 i = ARRAY_SIZE (all_cores) - 2;
975 gcc_assert (i > 0);
976 printf (" %s", all_cores[i].name);
977 remaining = columns - (strlen (all_cores[i].name) + 4);
978 gcc_assert (remaining >= 0);
979
980 while (i--)
981 {
982 int len = strlen (all_cores[i].name);
983
984 if (remaining > len + 2)
985 {
986 printf (", %s", all_cores[i].name);
987 remaining -= len + 2;
988 }
989 else
990 {
991 if (remaining > 0)
992 printf (",");
993 printf ("\n %s", all_cores[i].name);
994 remaining = columns - (len + 4);
995 }
996 }
997
998 printf ("\n\n Known ARM architectures (for use with the -march= option):\n");
999
1000 i = ARRAY_SIZE (all_architectures) - 2;
1001 gcc_assert (i > 0);
1002
1003 printf (" %s", all_architectures[i].name);
1004 remaining = columns - (strlen (all_architectures[i].name) + 4);
1005 gcc_assert (remaining >= 0);
1006
1007 while (i--)
1008 {
1009 int len = strlen (all_architectures[i].name);
1010
1011 if (remaining > len + 2)
1012 {
1013 printf (", %s", all_architectures[i].name);
1014 remaining -= len + 2;
1015 }
1016 else
1017 {
1018 if (remaining > 0)
1019 printf (",");
1020 printf ("\n %s", all_architectures[i].name);
1021 remaining = columns - (len + 4);
1022 }
1023 }
1024 printf ("\n");
1025
1026}
1027
64266206 1028/* Fix up any incompatible options that the user has specified.
1029 This has now turned into a maze. */
1030void
ebd88a36 1031arm_override_options (void)
64266206 1032{
ae175e8f 1033 unsigned i;
c37752cc 1034 enum processor_type target_arch_cpu = arm_none;
a2cd141b 1035
9888ad6d 1036 /* Set up the flags based on the cpu/architecture selected by the user. */
3098b2d3 1037 for (i = ARRAY_SIZE (arm_select); i--;)
9480e6c7 1038 {
9888ad6d 1039 struct arm_cpu_select * ptr = arm_select + i;
9e7454d0 1040
9888ad6d 1041 if (ptr->string != NULL && ptr->string[0] != '\0')
9480e6c7 1042 {
c9ba03f2 1043 const struct processors * sel;
9480e6c7 1044
215b30b3 1045 for (sel = ptr->processors; sel->name != NULL; sel++)
9888ad6d 1046 if (streq (ptr->string, sel->name))
9480e6c7 1047 {
e65e4284 1048 /* Set the architecture define. */
c37752cc 1049 if (i != ARM_OPT_SET_TUNE)
e65e4284 1050 sprintf (arm_arch_name, "__ARM_ARCH_%s__", sel->arch);
1051
a2cd141b 1052 /* Determine the processor core for which we should
1053 tune code-generation. */
1054 if (/* -mcpu= is a sensible default. */
c37752cc 1055 i == ARM_OPT_SET_CPU
a2cd141b 1056 /* -mtune= overrides -mcpu= and -march=. */
c37752cc 1057 || i == ARM_OPT_SET_TUNE)
a2cd141b 1058 arm_tune = (enum processor_type) (sel - ptr->processors);
1059
c37752cc 1060 /* Remember the CPU associated with this architecture.
1061 If no other option is used to set the CPU type,
1062 we'll use this to guess the most suitable tuning
1063 options. */
1064 if (i == ARM_OPT_SET_ARCH)
1065 target_arch_cpu = sel->core;
a60f1840 1066
c37752cc 1067 if (i != ARM_OPT_SET_TUNE)
f21249d5 1068 {
82ec49ae 1069 /* If we have been given an architecture and a processor
1070 make sure that they are compatible. We only generate
1071 a warning though, and we prefer the CPU over the
66aacf41 1072 architecture. */
82ec49ae 1073 if (insn_flags != 0 && (insn_flags ^ sel->flags))
c3ceba8e 1074 warning (0, "switch -mcpu=%s conflicts with -march= switch",
82ec49ae 1075 ptr->string);
9e7454d0 1076
82ec49ae 1077 insn_flags = sel->flags;
f21249d5 1078 }
9e7454d0 1079
9480e6c7 1080 break;
1081 }
1082
1083 if (sel->name == NULL)
1084 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
1085 }
1086 }
9e7454d0 1087
c37752cc 1088 /* Guess the tuning options from the architecture if necessary. */
1089 if (arm_tune == arm_none)
1090 arm_tune = target_arch_cpu;
1091
9888ad6d 1092 /* If the user did not specify a processor, choose one for them. */
82ec49ae 1093 if (insn_flags == 0)
9888ad6d 1094 {
e99c3a1d 1095 const struct processors * sel;
82ec49ae 1096 unsigned int sought;
e65e4284 1097 enum processor_type cpu;
82ec49ae 1098
e65e4284 1099 cpu = TARGET_CPU_DEFAULT;
1100 if (cpu == arm_none)
1101 {
1102#ifdef SUBTARGET_CPU_DEFAULT
1103 /* Use the subtarget default CPU if none was specified by
1104 configure. */
1105 cpu = SUBTARGET_CPU_DEFAULT;
1106#endif
1107 /* Default to ARM6. */
1108 if (cpu == arm_none)
1109 cpu = arm6;
1110 }
1111 sel = &all_cores[cpu];
82ec49ae 1112
1113 insn_flags = sel->flags;
a2cd141b 1114
82ec49ae 1115 /* Now check to see if the user has specified some command line
1116 switch that require certain abilities from the cpu. */
1117 sought = 0;
9e7454d0 1118
cffb2a26 1119 if (TARGET_INTERWORK || TARGET_THUMB)
9888ad6d 1120 {
82ec49ae 1121 sought |= (FL_THUMB | FL_MODE32);
9e7454d0 1122
cffb2a26 1123 /* There are no ARM processors that support both APCS-26 and
82ec49ae 1124 interworking. Therefore we force FL_MODE26 to be removed
1125 from insn_flags here (if it was set), so that the search
1126 below will always be able to find a compatible processor. */
215b30b3 1127 insn_flags &= ~FL_MODE26;
9888ad6d 1128 }
9e7454d0 1129
82ec49ae 1130 if (sought != 0 && ((sought & insn_flags) != sought))
9888ad6d 1131 {
82ec49ae 1132 /* Try to locate a CPU type that supports all of the abilities
1133 of the default CPU, plus the extra abilities requested by
1134 the user. */
215b30b3 1135 for (sel = all_cores; sel->name != NULL; sel++)
82ec49ae 1136 if ((sel->flags & sought) == (sought | insn_flags))
9888ad6d 1137 break;
1138
1139 if (sel->name == NULL)
82ec49ae 1140 {
a7712927 1141 unsigned current_bit_count = 0;
e99c3a1d 1142 const struct processors * best_fit = NULL;
9e7454d0 1143
82ec49ae 1144 /* Ideally we would like to issue an error message here
1145 saying that it was not possible to find a CPU compatible
1146 with the default CPU, but which also supports the command
1147 line options specified by the programmer, and so they
1148 ought to use the -mcpu=<name> command line option to
1149 override the default CPU type.
1150
c1a66faf 1151 If we cannot find a cpu that has both the
1152 characteristics of the default cpu and the given
1153 command line options we scan the array again looking
1154 for a best match. */
215b30b3 1155 for (sel = all_cores; sel->name != NULL; sel++)
82ec49ae 1156 if ((sel->flags & sought) == sought)
1157 {
a7712927 1158 unsigned count;
82ec49ae 1159
1160 count = bit_count (sel->flags & insn_flags);
1161
1162 if (count >= current_bit_count)
1163 {
1164 best_fit = sel;
1165 current_bit_count = count;
1166 }
1167 }
9888ad6d 1168
ed29c566 1169 gcc_assert (best_fit);
1170 sel = best_fit;
82ec49ae 1171 }
1172
1173 insn_flags = sel->flags;
9888ad6d 1174 }
e65e4284 1175 sprintf (arm_arch_name, "__ARM_ARCH_%s__", sel->arch);
5fad5123 1176 arm_default_cpu = (enum processor_type) (sel - all_cores);
a2cd141b 1177 if (arm_tune == arm_none)
5fad5123 1178 arm_tune = arm_default_cpu;
9888ad6d 1179 }
9e7454d0 1180
a2cd141b 1181 /* The processor for which we should tune should now have been
1182 chosen. */
ed29c566 1183 gcc_assert (arm_tune != arm_none);
9e7454d0 1184
a2cd141b 1185 tune_flags = all_cores[(int)arm_tune].flags;
c1877da8 1186 if (optimize_size)
1187 targetm.rtx_costs = arm_size_rtx_costs;
1188 else
1189 targetm.rtx_costs = all_cores[(int)arm_tune].rtx_costs;
9f468b67 1190
9888ad6d 1191 /* Make sure that the processor choice does not conflict with any of the
1192 other command line choices. */
25f905c2 1193 if (TARGET_ARM && !(insn_flags & FL_NOTM))
1194 error ("target CPU does not support ARM mode");
1195
96576951 1196 if (TARGET_INTERWORK && !(insn_flags & FL_THUMB))
9888ad6d 1197 {
c3ceba8e 1198 warning (0, "target CPU does not support interworking" );
81f6de2f 1199 target_flags &= ~MASK_INTERWORK;
9888ad6d 1200 }
9e7454d0 1201
cffb2a26 1202 if (TARGET_THUMB && !(insn_flags & FL_THUMB))
1203 {
c3ceba8e 1204 warning (0, "target CPU does not support THUMB instructions");
81f6de2f 1205 target_flags &= ~MASK_THUMB;
cffb2a26 1206 }
1207
1208 if (TARGET_APCS_FRAME && TARGET_THUMB)
1209 {
c3ceba8e 1210 /* warning (0, "ignoring -mapcs-frame because -mthumb was used"); */
81f6de2f 1211 target_flags &= ~MASK_APCS_FRAME;
cffb2a26 1212 }
331beb1a 1213
551836e5 1214 /* Callee super interworking implies thumb interworking. Adding
1215 this to the flags here simplifies the logic elsewhere. */
1216 if (TARGET_THUMB && TARGET_CALLEE_INTERWORKING)
1217 target_flags |= MASK_INTERWORK;
1218
cffb2a26 1219 /* TARGET_BACKTRACE calls leaf_function_p, which causes a crash if done
1220 from here where no function is being compiled currently. */
81f6de2f 1221 if ((TARGET_TPCS_FRAME || TARGET_TPCS_LEAF_FRAME) && TARGET_ARM)
c3ceba8e 1222 warning (0, "enabling backtrace support is only meaningful when compiling for the Thumb");
cffb2a26 1223
1224 if (TARGET_ARM && TARGET_CALLEE_INTERWORKING)
c3ceba8e 1225 warning (0, "enabling callee interworking support is only meaningful when compiling for the Thumb");
cffb2a26 1226
1227 if (TARGET_ARM && TARGET_CALLER_INTERWORKING)
c3ceba8e 1228 warning (0, "enabling caller interworking support is only meaningful when compiling for the Thumb");
cffb2a26 1229
215b30b3 1230 if (TARGET_APCS_STACK && !TARGET_APCS_FRAME)
9888ad6d 1231 {
c3ceba8e 1232 warning (0, "-mapcs-stack-check incompatible with -mno-apcs-frame");
81f6de2f 1233 target_flags |= MASK_APCS_FRAME;
9888ad6d 1234 }
9e7454d0 1235
64266206 1236 if (TARGET_POKE_FUNCTION_NAME)
81f6de2f 1237 target_flags |= MASK_APCS_FRAME;
9e7454d0 1238
64266206 1239 if (TARGET_APCS_REENT && flag_pic)
f060a027 1240 error ("-fpic and -mapcs-reent are incompatible");
9e7454d0 1241
64266206 1242 if (TARGET_APCS_REENT)
c3ceba8e 1243 warning (0, "APCS reentrant code not supported. Ignored");
9e7454d0 1244
cffb2a26 1245 /* If this target is normally configured to use APCS frames, warn if they
1246 are turned off and debugging is turned on. */
1247 if (TARGET_ARM
1248 && write_symbols != NO_DEBUG
215b30b3 1249 && !TARGET_APCS_FRAME
81f6de2f 1250 && (TARGET_DEFAULT & MASK_APCS_FRAME))
c3ceba8e 1251 warning (0, "-g with -mno-apcs-frame may not give sensible debugging");
9e7454d0 1252
64266206 1253 if (TARGET_APCS_FLOAT)
c3ceba8e 1254 warning (0, "passing floating point arguments in fp regs not yet supported");
9e7454d0 1255
457275b6 1256 /* Initialize boolean versions of the flags, for use in the arm.md file. */
a2cd141b 1257 arm_arch3m = (insn_flags & FL_ARCH3M) != 0;
1258 arm_arch4 = (insn_flags & FL_ARCH4) != 0;
f1039640 1259 arm_arch4t = arm_arch4 & ((insn_flags & FL_THUMB) != 0);
a2cd141b 1260 arm_arch5 = (insn_flags & FL_ARCH5) != 0;
1261 arm_arch5e = (insn_flags & FL_ARCH5E) != 0;
1262 arm_arch6 = (insn_flags & FL_ARCH6) != 0;
f655717d 1263 arm_arch6k = (insn_flags & FL_ARCH6K) != 0;
25f905c2 1264 arm_arch_notm = (insn_flags & FL_NOTM) != 0;
1265 arm_arch_thumb2 = (insn_flags & FL_THUMB2) != 0;
a2cd141b 1266 arm_arch_xscale = (insn_flags & FL_XSCALE) != 0;
e65e4284 1267 arm_arch_cirrus = (insn_flags & FL_CIRRUS) != 0;
a2cd141b 1268
1269 arm_ld_sched = (tune_flags & FL_LDSCHED) != 0;
74a71f7d 1270 arm_tune_strongarm = (tune_flags & FL_STRONG) != 0;
a2cd141b 1271 thumb_code = (TARGET_ARM == 0);
74a71f7d 1272 arm_tune_wbuf = (tune_flags & FL_WBUF) != 0;
a2cd141b 1273 arm_tune_xscale = (tune_flags & FL_XSCALE) != 0;
1274 arm_arch_iwmmxt = (insn_flags & FL_IWMMXT) != 0;
25f905c2 1275 arm_arch_hwdiv = (insn_flags & FL_DIV) != 0;
755eb2b4 1276
f1039640 1277 /* V5 code we generate is completely interworking capable, so we turn off
1278 TARGET_INTERWORK here to avoid many tests later on. */
80b6339a 1279
1280 /* XXX However, we must pass the right pre-processor defines to CPP
1281 or GLD can get confused. This is a hack. */
1282 if (TARGET_INTERWORK)
1283 arm_cpp_interwork = 1;
1284
f1039640 1285 if (arm_arch5)
81f6de2f 1286 target_flags &= ~MASK_INTERWORK;
f1039640 1287
f9273c43 1288 if (target_abi_name)
1289 {
1290 for (i = 0; i < ARRAY_SIZE (arm_all_abis); i++)
1291 {
1292 if (streq (arm_all_abis[i].name, target_abi_name))
1293 {
1294 arm_abi = arm_all_abis[i].abi_type;
1295 break;
1296 }
1297 }
1298 if (i == ARRAY_SIZE (arm_all_abis))
1299 error ("invalid ABI option: -mabi=%s", target_abi_name);
1300 }
1301 else
13a46000 1302 arm_abi = ARM_DEFAULT_ABI;
f9273c43 1303
1304 if (TARGET_IWMMXT && !ARM_DOUBLEWORD_ALIGN)
1305 error ("iwmmxt requires an AAPCS compatible ABI for proper operation");
1306
1307 if (TARGET_IWMMXT_ABI && !TARGET_IWMMXT)
1308 error ("iwmmxt abi requires an iwmmxt capable cpu");
89b30d75 1309
a2cd141b 1310 arm_fp_model = ARM_FP_MODEL_UNKNOWN;
1311 if (target_fpu_name == NULL && target_fpe_name != NULL)
7d57ec45 1312 {
a2cd141b 1313 if (streq (target_fpe_name, "2"))
1314 target_fpu_name = "fpe2";
1315 else if (streq (target_fpe_name, "3"))
1316 target_fpu_name = "fpe3";
1317 else
1318 error ("invalid floating point emulation option: -mfpe=%s",
1319 target_fpe_name);
1320 }
1321 if (target_fpu_name != NULL)
1322 {
1323 /* The user specified a FPU. */
1324 for (i = 0; i < ARRAY_SIZE (all_fpus); i++)
1325 {
1326 if (streq (all_fpus[i].name, target_fpu_name))
1327 {
1328 arm_fpu_arch = all_fpus[i].fpu;
1329 arm_fpu_tune = arm_fpu_arch;
1330 arm_fp_model = fp_model_for_fpu[arm_fpu_arch];
1331 break;
1332 }
1333 }
1334 if (arm_fp_model == ARM_FP_MODEL_UNKNOWN)
1335 error ("invalid floating point option: -mfpu=%s", target_fpu_name);
7d57ec45 1336 }
1337 else
64266206 1338 {
a2cd141b 1339#ifdef FPUTYPE_DEFAULT
e65e4284 1340 /* Use the default if it is specified for this platform. */
a2cd141b 1341 arm_fpu_arch = FPUTYPE_DEFAULT;
1342 arm_fpu_tune = FPUTYPE_DEFAULT;
1343#else
1344 /* Pick one based on CPU type. */
e65e4284 1345 /* ??? Some targets assume FPA is the default.
a2cd141b 1346 if ((insn_flags & FL_VFP) != 0)
1347 arm_fpu_arch = FPUTYPE_VFP;
e65e4284 1348 else
1349 */
1350 if (arm_arch_cirrus)
a2cd141b 1351 arm_fpu_arch = FPUTYPE_MAVERICK;
1352 else
c7f506fd 1353 arm_fpu_arch = FPUTYPE_FPA_EMU2;
a2cd141b 1354#endif
1355 if (tune_flags & FL_CO_PROC && arm_fpu_arch == FPUTYPE_FPA_EMU2)
1356 arm_fpu_tune = FPUTYPE_FPA;
64266206 1357 else
a2cd141b 1358 arm_fpu_tune = arm_fpu_arch;
1359 arm_fp_model = fp_model_for_fpu[arm_fpu_arch];
ed29c566 1360 gcc_assert (arm_fp_model != ARM_FP_MODEL_UNKNOWN);
a2cd141b 1361 }
1362
1363 if (target_float_abi_name != NULL)
1364 {
1365 /* The user specified a FP ABI. */
1366 for (i = 0; i < ARRAY_SIZE (all_float_abis); i++)
1367 {
1368 if (streq (all_float_abis[i].name, target_float_abi_name))
1369 {
1370 arm_float_abi = all_float_abis[i].abi_type;
1371 break;
1372 }
1373 }
1374 if (i == ARRAY_SIZE (all_float_abis))
1375 error ("invalid floating point abi: -mfloat-abi=%s",
1376 target_float_abi_name);
64266206 1377 }
87f8017f 1378 else
1379 arm_float_abi = TARGET_DEFAULT_FLOAT_ABI;
a2cd141b 1380
eb03dcf8 1381 if (arm_float_abi == ARM_FLOAT_ABI_HARD && TARGET_VFP)
1382 sorry ("-mfloat-abi=hard and VFP");
1383
7f5997af 1384 /* FPA and iWMMXt are incompatible because the insn encodings overlap.
1385 VFP and iWMMXt can theoretically coexist, but it's unlikely such silicon
1386 will ever exist. GCC makes no attempt to support this combination. */
1387 if (TARGET_IWMMXT && !TARGET_SOFT_FLOAT)
1388 sorry ("iWMMXt and hardware floating point");
1389
25f905c2 1390 /* ??? iWMMXt insn patterns need auditing for Thumb-2. */
1391 if (TARGET_THUMB2 && TARGET_IWMMXT)
1392 sorry ("Thumb-2 iWMMXt");
1393
a2cd141b 1394 /* If soft-float is specified then don't use FPU. */
1395 if (TARGET_SOFT_FLOAT)
1396 arm_fpu_arch = FPUTYPE_NONE;
9e7454d0 1397
9888ad6d 1398 /* For arm2/3 there is no need to do any scheduling if there is only
1399 a floating point emulator, or we are doing software floating-point. */
a2cd141b 1400 if ((TARGET_SOFT_FLOAT
1401 || arm_fpu_tune == FPUTYPE_FPA_EMU2
1402 || arm_fpu_tune == FPUTYPE_FPA_EMU3)
55c1e470 1403 && (tune_flags & FL_MODE32) == 0)
9888ad6d 1404 flag_schedule_insns = flag_schedule_insns_after_reload = 0;
9e7454d0 1405
f655717d 1406 if (target_thread_switch)
1407 {
1408 if (strcmp (target_thread_switch, "soft") == 0)
1409 target_thread_pointer = TP_SOFT;
1410 else if (strcmp (target_thread_switch, "auto") == 0)
1411 target_thread_pointer = TP_AUTO;
1412 else if (strcmp (target_thread_switch, "cp15") == 0)
1413 target_thread_pointer = TP_CP15;
1414 else
1415 error ("invalid thread pointer option: -mtp=%s", target_thread_switch);
1416 }
1417
1418 /* Use the cp15 method if it is available. */
1419 if (target_thread_pointer == TP_AUTO)
1420 {
1421 if (arm_arch6k && !TARGET_THUMB)
1422 target_thread_pointer = TP_CP15;
1423 else
1424 target_thread_pointer = TP_SOFT;
1425 }
1426
25f905c2 1427 if (TARGET_HARD_TP && TARGET_THUMB1)
1428 error ("can not use -mtp=cp15 with 16-bit Thumb");
f655717d 1429
f9273c43 1430 /* Override the default structure alignment for AAPCS ABI. */
6783d878 1431 if (TARGET_AAPCS_BASED)
f9273c43 1432 arm_structure_size_boundary = 8;
1433
6cd47762 1434 if (structure_size_string != NULL)
1435 {
1436 int size = strtol (structure_size_string, NULL, 0);
f9273c43 1437
1438 if (size == 8 || size == 32
1439 || (ARM_DOUBLEWORD_ALIGN && size == 64))
6cd47762 1440 arm_structure_size_boundary = size;
1441 else
c3ceba8e 1442 warning (0, "structure size boundary can only be set to %s",
f9273c43 1443 ARM_DOUBLEWORD_ALIGN ? "8, 32 or 64": "8 or 32");
6cd47762 1444 }
55c1e470 1445
bac7fc85 1446 if (!TARGET_ARM && TARGET_VXWORKS_RTP && flag_pic)
1447 {
1448 error ("RTP PIC is incompatible with Thumb");
1449 flag_pic = 0;
1450 }
1451
1ad38120 1452 /* If stack checking is disabled, we can use r10 as the PIC register,
1453 which keeps r9 available. The EABI specifies r9 as the PIC register. */
1454 if (flag_pic && TARGET_SINGLE_PIC_BASE)
bac7fc85 1455 {
1456 if (TARGET_VXWORKS_RTP)
1457 warning (0, "RTP PIC is incompatible with -msingle-pic-base");
1458 arm_pic_register = (TARGET_APCS_STACK || TARGET_AAPCS_BASED) ? 9 : 10;
1459 }
1460
1461 if (flag_pic && TARGET_VXWORKS_RTP)
1462 arm_pic_register = 9;
1ad38120 1463
55c1e470 1464 if (arm_pic_register_string != NULL)
1465 {
df9f5cf8 1466 int pic_register = decode_reg_name (arm_pic_register_string);
9f468b67 1467
215b30b3 1468 if (!flag_pic)
c3ceba8e 1469 warning (0, "-mpic-register= is useless without -fpic");
55c1e470 1470
55c1e470 1471 /* Prevent the user from choosing an obviously stupid PIC register. */
df9f5cf8 1472 else if (pic_register < 0 || call_used_regs[pic_register]
1473 || pic_register == HARD_FRAME_POINTER_REGNUM
1474 || pic_register == STACK_POINTER_REGNUM
bac7fc85 1475 || pic_register >= PC_REGNUM
1476 || (TARGET_VXWORKS_RTP
1477 && (unsigned int) pic_register != arm_pic_register))
68435912 1478 error ("unable to use '%s' for PIC register", arm_pic_register_string);
55c1e470 1479 else
1480 arm_pic_register = pic_register;
1481 }
cffb2a26 1482
25f905c2 1483 /* ??? We might want scheduling for thumb2. */
cffb2a26 1484 if (TARGET_THUMB && flag_schedule_insns)
1485 {
1486 /* Don't warn since it's on by default in -O2. */
1487 flag_schedule_insns = 0;
1488 }
1489
9888ad6d 1490 if (optimize_size)
dde5cb68 1491 {
7e28d849 1492 arm_constant_limit = 1;
dde5cb68 1493
1494 /* If optimizing for size, bump the number of instructions that we
674a8f0b 1495 are prepared to conditionally execute (even on a StrongARM). */
dde5cb68 1496 max_insns_skipped = 6;
1497 }
1498 else
1499 {
1500 /* For processors with load scheduling, it never costs more than
1501 2 cycles to load a constant, and the load scheduler may well
1502 reduce that to 1. */
359a6e9f 1503 if (arm_ld_sched)
dde5cb68 1504 arm_constant_limit = 1;
1505
1506 /* On XScale the longer latency of a load makes it more difficult
1507 to achieve a good schedule, so it's faster to synthesize
674a8f0b 1508 constants that can be done in two insns. */
dde5cb68 1509 if (arm_tune_xscale)
1510 arm_constant_limit = 2;
1511
1512 /* StrongARM has early execution of branches, so a sequence
1513 that is worth skipping is shorter. */
74a71f7d 1514 if (arm_tune_strongarm)
dde5cb68 1515 max_insns_skipped = 3;
1516 }
db80f614 1517
1518 /* Register global variables with the garbage collector. */
1519 arm_add_gc_roots ();
1520}
1521
1522static void
ebd88a36 1523arm_add_gc_roots (void)
db80f614 1524{
a220ccce 1525 gcc_obstack_init(&minipool_obstack);
1526 minipool_startobj = (char *) obstack_alloc (&minipool_obstack, 0);
64266206 1527}
8cd42699 1528\f
e27ad2d5 1529/* A table of known ARM exception types.
1530 For use with the interrupt function attribute. */
1531
1532typedef struct
1533{
e99c3a1d 1534 const char *const arg;
1535 const unsigned long return_value;
e27ad2d5 1536}
1537isr_attribute_arg;
1538
e99c3a1d 1539static const isr_attribute_arg isr_attribute_args [] =
e27ad2d5 1540{
1541 { "IRQ", ARM_FT_ISR },
1542 { "irq", ARM_FT_ISR },
1543 { "FIQ", ARM_FT_FIQ },
1544 { "fiq", ARM_FT_FIQ },
1545 { "ABORT", ARM_FT_ISR },
1546 { "abort", ARM_FT_ISR },
1547 { "ABORT", ARM_FT_ISR },
1548 { "abort", ARM_FT_ISR },
1549 { "UNDEF", ARM_FT_EXCEPTION },
1550 { "undef", ARM_FT_EXCEPTION },
1551 { "SWI", ARM_FT_EXCEPTION },
1552 { "swi", ARM_FT_EXCEPTION },
1553 { NULL, ARM_FT_NORMAL }
1554};
1555
1556/* Returns the (interrupt) function type of the current
1557 function, or ARM_FT_UNKNOWN if the type cannot be determined. */
1558
1559static unsigned long
ebd88a36 1560arm_isr_value (tree argument)
e27ad2d5 1561{
e99c3a1d 1562 const isr_attribute_arg * ptr;
a12be13c 1563 const char * arg;
e27ad2d5 1564
25f905c2 1565 if (!arm_arch_notm)
1566 return ARM_FT_NORMAL | ARM_FT_STACKALIGN;
1567
e27ad2d5 1568 /* No argument - default to IRQ. */
1569 if (argument == NULL_TREE)
1570 return ARM_FT_ISR;
1571
1572 /* Get the value of the argument. */
1573 if (TREE_VALUE (argument) == NULL_TREE
1574 || TREE_CODE (TREE_VALUE (argument)) != STRING_CST)
1575 return ARM_FT_UNKNOWN;
1576
1577 arg = TREE_STRING_POINTER (TREE_VALUE (argument));
1578
1579 /* Check it against the list of known arguments. */
755eb2b4 1580 for (ptr = isr_attribute_args; ptr->arg != NULL; ptr++)
a12be13c 1581 if (streq (arg, ptr->arg))
1582 return ptr->return_value;
e27ad2d5 1583
a2f10574 1584 /* An unrecognized interrupt type. */
e27ad2d5 1585 return ARM_FT_UNKNOWN;
1586}
1587
1588/* Computes the type of the current function. */
1589
1590static unsigned long
ebd88a36 1591arm_compute_func_type (void)
e27ad2d5 1592{
1593 unsigned long type = ARM_FT_UNKNOWN;
1594 tree a;
1595 tree attr;
9e7454d0 1596
ed29c566 1597 gcc_assert (TREE_CODE (current_function_decl) == FUNCTION_DECL);
e27ad2d5 1598
1599 /* Decide if the current function is volatile. Such functions
1600 never return, and many memory cycles can be saved by not storing
1601 register values that will never be needed again. This optimization
1602 was added to speed up context switching in a kernel application. */
1603 if (optimize > 0
c4d51de2 1604 && (TREE_NOTHROW (current_function_decl)
1605 || !(flag_unwind_tables
1606 || (flag_exceptions && !USING_SJLJ_EXCEPTIONS)))
e27ad2d5 1607 && TREE_THIS_VOLATILE (current_function_decl))
1608 type |= ARM_FT_VOLATILE;
9e7454d0 1609
4ee9c684 1610 if (cfun->static_chain_decl != NULL)
e27ad2d5 1611 type |= ARM_FT_NESTED;
1612
e3c541f0 1613 attr = DECL_ATTRIBUTES (current_function_decl);
9e7454d0 1614
e27ad2d5 1615 a = lookup_attribute ("naked", attr);
1616 if (a != NULL_TREE)
1617 type |= ARM_FT_NAKED;
1618
4c44712e 1619 a = lookup_attribute ("isr", attr);
1620 if (a == NULL_TREE)
1621 a = lookup_attribute ("interrupt", attr);
9e7454d0 1622
4c44712e 1623 if (a == NULL_TREE)
1624 type |= TARGET_INTERWORK ? ARM_FT_INTERWORKED : ARM_FT_NORMAL;
e27ad2d5 1625 else
4c44712e 1626 type |= arm_isr_value (TREE_VALUE (a));
9e7454d0 1627
e27ad2d5 1628 return type;
1629}
1630
1631/* Returns the type of the current function. */
1632
1633unsigned long
ebd88a36 1634arm_current_func_type (void)
e27ad2d5 1635{
1636 if (ARM_FUNC_TYPE (cfun->machine->func_type) == ARM_FT_UNKNOWN)
1637 cfun->machine->func_type = arm_compute_func_type ();
1638
1639 return cfun->machine->func_type;
1640}
1641\f
9e7454d0 1642/* Return 1 if it is possible to return using a single instruction.
ffc9d00c 1643 If SIBLING is non-null, this is a test for a return before a sibling
1644 call. SIBLING is the call insn, so we can examine its register usage. */
e27ad2d5 1645
9c08d1fa 1646int
ffc9d00c 1647use_return_insn (int iscond, rtx sibling)
9c08d1fa 1648{
1649 int regno;
5cf3595a 1650 unsigned int func_type;
50368af8 1651 unsigned long saved_int_regs;
ffc9d00c 1652 unsigned HOST_WIDE_INT stack_adjust;
f9273c43 1653 arm_stack_offsets *offsets;
9c08d1fa 1654
cffb2a26 1655 /* Never use a return instruction before reload has run. */
e27ad2d5 1656 if (!reload_completed)
1657 return 0;
01c5c234 1658
5cf3595a 1659 func_type = arm_current_func_type ();
1660
25f905c2 1661 /* Naked, volatile and stack alignment functions need special
4a5f62e2 1662 consideration. */
25f905c2 1663 if (func_type & (ARM_FT_VOLATILE | ARM_FT_NAKED | ARM_FT_STACKALIGN))
e27ad2d5 1664 return 0;
000c5098 1665
8b438b4f 1666 /* So do interrupt functions that use the frame pointer and Thumb
1667 interrupt functions. */
1668 if (IS_INTERRUPT (func_type) && (frame_pointer_needed || TARGET_THUMB))
000c5098 1669 return 0;
ffc9d00c 1670
f9273c43 1671 offsets = arm_get_frame_offsets ();
1672 stack_adjust = offsets->outgoing_args - offsets->saved_regs;
ffc9d00c 1673
e27ad2d5 1674 /* As do variadic functions. */
1675 if (current_function_pretend_args_size
71904594 1676 || cfun->machine->uses_anonymous_args
8d69f2ad 1677 /* Or if the function calls __builtin_eh_return () */
4c44712e 1678 || current_function_calls_eh_return
8d69f2ad 1679 /* Or if the function calls alloca */
1680 || current_function_calls_alloca
ffc9d00c 1681 /* Or if there is a stack adjustment. However, if the stack pointer
1682 is saved on the stack, we can use a pre-incrementing stack load. */
1683 || !(stack_adjust == 0 || (frame_pointer_needed && stack_adjust == 4)))
9c08d1fa 1684 return 0;
1685
50368af8 1686 saved_int_regs = arm_compute_save_reg_mask ();
1687
ffc9d00c 1688 /* Unfortunately, the insn
1689
1690 ldmib sp, {..., sp, ...}
1691
1692 triggers a bug on most SA-110 based devices, such that the stack
1693 pointer won't be correctly restored if the instruction takes a
efee20da 1694 page fault. We work around this problem by popping r3 along with
ffc9d00c 1695 the other registers, since that is never slower than executing
9e7454d0 1696 another instruction.
ffc9d00c 1697
1698 We test for !arm_arch5 here, because code for any architecture
1699 less than this could potentially be run on one of the buggy
1700 chips. */
25f905c2 1701 if (stack_adjust == 4 && !arm_arch5 && TARGET_ARM)
ffc9d00c 1702 {
1703 /* Validate that r3 is a call-clobbered register (always true in
674a8f0b 1704 the default abi) ... */
ffc9d00c 1705 if (!call_used_regs[3])
1706 return 0;
1707
0858d94e 1708 /* ... that it isn't being used for a return value ... */
1709 if (arm_size_return_regs () >= (4 * UNITS_PER_WORD))
1710 return 0;
1711
1712 /* ... or for a tail-call argument ... */
ffc9d00c 1713 if (sibling)
1714 {
ed29c566 1715 gcc_assert (GET_CODE (sibling) == CALL_INSN);
ffc9d00c 1716
1717 if (find_regno_fusage (sibling, USE, 3))
1718 return 0;
1719 }
1720
1721 /* ... and that there are no call-saved registers in r0-r2
1722 (always true in the default ABI). */
1723 if (saved_int_regs & 0x7)
1724 return 0;
1725 }
1726
f21249d5 1727 /* Can't be done if interworking with Thumb, and any registers have been
50368af8 1728 stacked. */
8b438b4f 1729 if (TARGET_INTERWORK && saved_int_regs != 0 && !IS_INTERRUPT(func_type))
129a2fe4 1730 return 0;
50368af8 1731
1732 /* On StrongARM, conditional returns are expensive if they aren't
1733 taken and multiple registers have been stacked. */
74a71f7d 1734 if (iscond && arm_tune_strongarm)
0eb4b5ff 1735 {
9e7454d0 1736 /* Conditional return when just the LR is stored is a simple
50368af8 1737 conditional-load instruction, that's not expensive. */
1738 if (saved_int_regs != 0 && saved_int_regs != (1 << LR_REGNUM))
1739 return 0;
0eb4b5ff 1740
2cb7d577 1741 if (flag_pic
1742 && arm_pic_register != INVALID_REGNUM
3072d30e 1743 && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM))
f21249d5 1744 return 0;
0eb4b5ff 1745 }
50368af8 1746
1747 /* If there are saved registers but the LR isn't saved, then we need
1748 two instructions for the return. */
1749 if (saved_int_regs && !(saved_int_regs & (1 << LR_REGNUM)))
1750 return 0;
1751
e8ff69a4 1752 /* Can't be done if any of the FPA regs are pushed,
e27ad2d5 1753 since this also requires an insn. */
a2cd141b 1754 if (TARGET_HARD_FLOAT && TARGET_FPA)
1755 for (regno = FIRST_FPA_REGNUM; regno <= LAST_FPA_REGNUM; regno++)
3072d30e 1756 if (df_regs_ever_live_p (regno) && !call_used_regs[regno])
a2cd141b 1757 return 0;
1758
1759 /* Likewise VFP regs. */
1760 if (TARGET_HARD_FLOAT && TARGET_VFP)
1761 for (regno = FIRST_VFP_REGNUM; regno <= LAST_VFP_REGNUM; regno++)
3072d30e 1762 if (df_regs_ever_live_p (regno) && !call_used_regs[regno])
cffb2a26 1763 return 0;
9c08d1fa 1764
755eb2b4 1765 if (TARGET_REALLY_IWMMXT)
1766 for (regno = FIRST_IWMMXT_REGNUM; regno <= LAST_IWMMXT_REGNUM; regno++)
3072d30e 1767 if (df_regs_ever_live_p (regno) && ! call_used_regs[regno])
755eb2b4 1768 return 0;
1769
9c08d1fa 1770 return 1;
1771}
1772
8cd42699 1773/* Return TRUE if int I is a valid immediate ARM constant. */
1774
1775int
ebd88a36 1776const_ok_for_arm (HOST_WIDE_INT i)
8cd42699 1777{
eaae9d8c 1778 int lowbit;
a60f1840 1779
9e7454d0 1780 /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must
6019008a 1781 be all zero, or all one. */
35cea10c 1782 if ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff) != 0
1783 && ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff)
1784 != ((~(unsigned HOST_WIDE_INT) 0)
1785 & ~(unsigned HOST_WIDE_INT) 0xffffffff)))
6019008a 1786 return FALSE;
9e7454d0 1787
eaae9d8c 1788 i &= (unsigned HOST_WIDE_INT) 0xffffffff;
a60f1840 1789
eaae9d8c 1790 /* Fast return for 0 and small values. We must do this for zero, since
1791 the code below can't handle that one case. */
1792 if ((i & ~(unsigned HOST_WIDE_INT) 0xff) == 0)
4b6897e9 1793 return TRUE;
1794
25f905c2 1795 /* Get the number of trailing zeros. */
1796 lowbit = ffs((int) i) - 1;
1797
1798 /* Only even shifts are allowed in ARM mode so round down to the
1799 nearest even number. */
1800 if (TARGET_ARM)
1801 lowbit &= ~1;
eaae9d8c 1802
1803 if ((i & ~(((unsigned HOST_WIDE_INT) 0xff) << lowbit)) == 0)
1804 return TRUE;
25f905c2 1805
1806 if (TARGET_ARM)
1807 {
1808 /* Allow rotated constants in ARM mode. */
1809 if (lowbit <= 4
eaae9d8c 1810 && ((i & ~0xc000003f) == 0
1811 || (i & ~0xf000000f) == 0
1812 || (i & ~0xfc000003) == 0))
25f905c2 1813 return TRUE;
1814 }
1815 else
1816 {
1817 HOST_WIDE_INT v;
1818
1819 /* Allow repeated pattern. */
1820 v = i & 0xff;
1821 v |= v << 16;
1822 if (i == v || i == (v | (v << 8)))
1823 return TRUE;
1824 }
8cd42699 1825
a690ede2 1826 return FALSE;
1827}
8cd42699 1828
66aacf41 1829/* Return true if I is a valid constant for the operation CODE. */
016696d4 1830static int
ebd88a36 1831const_ok_for_op (HOST_WIDE_INT i, enum rtx_code code)
4b6897e9 1832{
1833 if (const_ok_for_arm (i))
1834 return 1;
1835
1836 switch (code)
1837 {
1838 case PLUS:
1839 return const_ok_for_arm (ARM_SIGN_EXTEND (-i));
1840
1841 case MINUS: /* Should only occur with (MINUS I reg) => rsb */
1842 case XOR:
1843 case IOR:
1844 return 0;
1845
1846 case AND:
1847 return const_ok_for_arm (ARM_SIGN_EXTEND (~i));
1848
1849 default:
ed29c566 1850 gcc_unreachable ();
4b6897e9 1851 }
1852}
1853
1854/* Emit a sequence of insns to handle a large constant.
1855 CODE is the code of the operation required, it can be any of SET, PLUS,
1856 IOR, AND, XOR, MINUS;
1857 MODE is the mode in which the operation is being performed;
1858 VAL is the integer to operate on;
1859 SOURCE is the other operand (a register, or a null-pointer for SET);
1860 SUBTARGETS means it is safe to create scratch registers if that will
64266206 1861 either produce a simpler sequence, or we will want to cse the values.
1862 Return value is the number of insns emitted. */
4b6897e9 1863
25f905c2 1864/* ??? Tweak this for thumb2. */
4b6897e9 1865int
96f57e36 1866arm_split_constant (enum rtx_code code, enum machine_mode mode, rtx insn,
ebd88a36 1867 HOST_WIDE_INT val, rtx target, rtx source, int subtargets)
64266206 1868{
96f57e36 1869 rtx cond;
1870
1871 if (insn && GET_CODE (PATTERN (insn)) == COND_EXEC)
1872 cond = COND_EXEC_TEST (PATTERN (insn));
1873 else
1874 cond = NULL_RTX;
1875
64266206 1876 if (subtargets || code == SET
1877 || (GET_CODE (target) == REG && GET_CODE (source) == REG
1878 && REGNO (target) != REGNO (source)))
1879 {
11de4c7f 1880 /* After arm_reorg has been called, we can't fix up expensive
a2f10574 1881 constants by pushing them into memory so we must synthesize
11de4c7f 1882 them in-line, regardless of the cost. This is only likely to
1883 be more costly on chips that have load delay slots and we are
1884 compiling without running the scheduler (so no splitting
82ec49ae 1885 occurred before the final instruction emission).
1886
1887 Ref: gcc -O1 -mcpu=strongarm gcc.c-torture/compile/980506-2.c
82ec49ae 1888 */
215b30b3 1889 if (!after_arm_reorg
96f57e36 1890 && !cond
9e7454d0 1891 && (arm_gen_constant (code, mode, NULL_RTX, val, target, source,
96f57e36 1892 1, 0)
11de4c7f 1893 > arm_constant_limit + (code != SET)))
64266206 1894 {
1895 if (code == SET)
1896 {
1897 /* Currently SET is the only monadic value for CODE, all
1898 the rest are diadic. */
0083a3b9 1899 emit_set_insn (target, GEN_INT (val));
64266206 1900 return 1;
1901 }
1902 else
1903 {
1904 rtx temp = subtargets ? gen_reg_rtx (mode) : target;
1905
0083a3b9 1906 emit_set_insn (temp, GEN_INT (val));
64266206 1907 /* For MINUS, the value is subtracted from, since we never
1908 have subtraction of a constant. */
1909 if (code == MINUS)
0083a3b9 1910 emit_set_insn (target, gen_rtx_MINUS (mode, temp, source));
64266206 1911 else
0083a3b9 1912 emit_set_insn (target,
1913 gen_rtx_fmt_ee (code, mode, source, temp));
64266206 1914 return 2;
1915 }
1916 }
1917 }
1918
9e7454d0 1919 return arm_gen_constant (code, mode, cond, val, target, source, subtargets,
96f57e36 1920 1);
64266206 1921}
1922
25f905c2 1923/* Return the number of ARM instructions required to synthesize the given
1924 constant. */
cd8df93e 1925static int
ebd88a36 1926count_insns_for_constant (HOST_WIDE_INT remainder, int i)
cd8df93e 1927{
1928 HOST_WIDE_INT temp1;
1929 int num_insns = 0;
1930 do
1931 {
1932 int end;
9e7454d0 1933
cd8df93e 1934 if (i <= 0)
1935 i += 32;
1936 if (remainder & (3 << (i - 2)))
1937 {
1938 end = i - 8;
1939 if (end < 0)
1940 end += 32;
1941 temp1 = remainder & ((0x0ff << end)
1942 | ((i < end) ? (0xff >> (32 - end)) : 0));
1943 remainder &= ~temp1;
1944 num_insns++;
1945 i -= 6;
1946 }
1947 i -= 2;
1948 } while (remainder);
1949 return num_insns;
1950}
1951
96f57e36 1952/* Emit an instruction with the indicated PATTERN. If COND is
1953 non-NULL, conditionalize the execution of the instruction on COND
1954 being true. */
1955
1956static void
1957emit_constant_insn (rtx cond, rtx pattern)
1958{
1959 if (cond)
1960 pattern = gen_rtx_COND_EXEC (VOIDmode, copy_rtx (cond), pattern);
1961 emit_insn (pattern);
1962}
1963
64266206 1964/* As above, but extra parameter GENERATE which, if clear, suppresses
1965 RTL generation. */
25f905c2 1966/* ??? This needs more work for thumb2. */
a12be13c 1967
cffb2a26 1968static int
96f57e36 1969arm_gen_constant (enum rtx_code code, enum machine_mode mode, rtx cond,
ebd88a36 1970 HOST_WIDE_INT val, rtx target, rtx source, int subtargets,
1971 int generate)
4b6897e9 1972{
4b6897e9 1973 int can_invert = 0;
1974 int can_negate = 0;
1975 int can_negate_initial = 0;
1976 int can_shift = 0;
1977 int i;
1978 int num_bits_set = 0;
1979 int set_sign_bit_copies = 0;
1980 int clear_sign_bit_copies = 0;
1981 int clear_zero_bit_copies = 0;
1982 int set_zero_bit_copies = 0;
1983 int insns = 0;
4b6897e9 1984 unsigned HOST_WIDE_INT temp1, temp2;
35cea10c 1985 unsigned HOST_WIDE_INT remainder = val & 0xffffffff;
4b6897e9 1986
cffb2a26 1987 /* Find out which operations are safe for a given CODE. Also do a quick
4b6897e9 1988 check for degenerate cases; these can occur when DImode operations
1989 are split. */
1990 switch (code)
1991 {
1992 case SET:
1993 can_invert = 1;
1994 can_shift = 1;
1995 can_negate = 1;
1996 break;
1997
1998 case PLUS:
1999 can_negate = 1;
2000 can_negate_initial = 1;
2001 break;
2002
2003 case IOR:
35cea10c 2004 if (remainder == 0xffffffff)
4b6897e9 2005 {
64266206 2006 if (generate)
96f57e36 2007 emit_constant_insn (cond,
2008 gen_rtx_SET (VOIDmode, target,
2009 GEN_INT (ARM_SIGN_EXTEND (val))));
4b6897e9 2010 return 1;
2011 }
2012 if (remainder == 0)
2013 {
2014 if (reload_completed && rtx_equal_p (target, source))
2015 return 0;
64266206 2016 if (generate)
96f57e36 2017 emit_constant_insn (cond,
2018 gen_rtx_SET (VOIDmode, target, source));
4b6897e9 2019 return 1;
2020 }
2021 break;
2022
2023 case AND:
2024 if (remainder == 0)
2025 {
64266206 2026 if (generate)
96f57e36 2027 emit_constant_insn (cond,
2028 gen_rtx_SET (VOIDmode, target, const0_rtx));
4b6897e9 2029 return 1;
2030 }
35cea10c 2031 if (remainder == 0xffffffff)
4b6897e9 2032 {
2033 if (reload_completed && rtx_equal_p (target, source))
2034 return 0;
64266206 2035 if (generate)
96f57e36 2036 emit_constant_insn (cond,
2037 gen_rtx_SET (VOIDmode, target, source));
4b6897e9 2038 return 1;
2039 }
2040 can_invert = 1;
2041 break;
2042
2043 case XOR:
2044 if (remainder == 0)
2045 {
2046 if (reload_completed && rtx_equal_p (target, source))
2047 return 0;
64266206 2048 if (generate)
96f57e36 2049 emit_constant_insn (cond,
2050 gen_rtx_SET (VOIDmode, target, source));
4b6897e9 2051 return 1;
2052 }
a60f1840 2053
ed29c566 2054 /* We don't know how to handle other cases yet. */
2055 gcc_assert (remainder == 0xffffffff);
a60f1840 2056
ed29c566 2057 if (generate)
2058 emit_constant_insn (cond,
2059 gen_rtx_SET (VOIDmode, target,
2060 gen_rtx_NOT (mode, source)));
2061 return 1;
4b6897e9 2062
2063 case MINUS:
2064 /* We treat MINUS as (val - source), since (source - val) is always
2065 passed as (source + (-val)). */
2066 if (remainder == 0)
2067 {
64266206 2068 if (generate)
96f57e36 2069 emit_constant_insn (cond,
2070 gen_rtx_SET (VOIDmode, target,
2071 gen_rtx_NEG (mode, source)));
4b6897e9 2072 return 1;
2073 }
2074 if (const_ok_for_arm (val))
2075 {
64266206 2076 if (generate)
96f57e36 2077 emit_constant_insn (cond,
9e7454d0 2078 gen_rtx_SET (VOIDmode, target,
96f57e36 2079 gen_rtx_MINUS (mode, GEN_INT (val),
2080 source)));
4b6897e9 2081 return 1;
2082 }
2083 can_negate = 1;
2084
2085 break;
2086
2087 default:
ed29c566 2088 gcc_unreachable ();
4b6897e9 2089 }
2090
66aacf41 2091 /* If we can do it in one insn get out quickly. */
4b6897e9 2092 if (const_ok_for_arm (val)
2093 || (can_negate_initial && const_ok_for_arm (-val))
2094 || (can_invert && const_ok_for_arm (~val)))
2095 {
64266206 2096 if (generate)
96f57e36 2097 emit_constant_insn (cond,
2098 gen_rtx_SET (VOIDmode, target,
9e7454d0 2099 (source
96f57e36 2100 ? gen_rtx_fmt_ee (code, mode, source,
2101 GEN_INT (val))
2102 : GEN_INT (val))));
4b6897e9 2103 return 1;
2104 }
2105
4b6897e9 2106 /* Calculate a few attributes that may be useful for specific
66aacf41 2107 optimizations. */
4b6897e9 2108 for (i = 31; i >= 0; i--)
2109 {
2110 if ((remainder & (1 << i)) == 0)
2111 clear_sign_bit_copies++;
2112 else
2113 break;
2114 }
2115
2116 for (i = 31; i >= 0; i--)
2117 {
2118 if ((remainder & (1 << i)) != 0)
2119 set_sign_bit_copies++;
2120 else
2121 break;
2122 }
2123
2124 for (i = 0; i <= 31; i++)
2125 {
2126 if ((remainder & (1 << i)) == 0)
2127 clear_zero_bit_copies++;
2128 else
2129 break;
2130 }
2131
2132 for (i = 0; i <= 31; i++)
2133 {
2134 if ((remainder & (1 << i)) != 0)
2135 set_zero_bit_copies++;
2136 else
2137 break;
2138 }
2139
2140 switch (code)
2141 {
2142 case SET:
25f905c2 2143 /* See if we can use movw. */
2144 if (arm_arch_thumb2 && (remainder & 0xffff0000) == 0)
2145 {
2146 if (generate)
2147 emit_constant_insn (cond, gen_rtx_SET (VOIDmode, target,
2148 GEN_INT (val)));
2149 return 1;
2150 }
2151
4b6897e9 2152 /* See if we can do this by sign_extending a constant that is known
2153 to be negative. This is a good, way of doing it, since the shift
2154 may well merge into a subsequent insn. */
2155 if (set_sign_bit_copies > 1)
2156 {
2157 if (const_ok_for_arm
9e7454d0 2158 (temp1 = ARM_SIGN_EXTEND (remainder
4b6897e9 2159 << (set_sign_bit_copies - 1))))
2160 {
64266206 2161 if (generate)
2162 {
997e4174 2163 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
96f57e36 2164 emit_constant_insn (cond,
9e7454d0 2165 gen_rtx_SET (VOIDmode, new_src,
96f57e36 2166 GEN_INT (temp1)));
2167 emit_constant_insn (cond,
9e7454d0 2168 gen_ashrsi3 (target, new_src,
96f57e36 2169 GEN_INT (set_sign_bit_copies - 1)));
64266206 2170 }
4b6897e9 2171 return 2;
2172 }
2173 /* For an inverted constant, we will need to set the low bits,
2174 these will be shifted out of harm's way. */
2175 temp1 |= (1 << (set_sign_bit_copies - 1)) - 1;
2176 if (const_ok_for_arm (~temp1))
2177 {
64266206 2178 if (generate)
2179 {
997e4174 2180 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
96f57e36 2181 emit_constant_insn (cond,
2182 gen_rtx_SET (VOIDmode, new_src,
2183 GEN_INT (temp1)));
2184 emit_constant_insn (cond,
9e7454d0 2185 gen_ashrsi3 (target, new_src,
96f57e36 2186 GEN_INT (set_sign_bit_copies - 1)));
64266206 2187 }
4b6897e9 2188 return 2;
2189 }
2190 }
2191
d430cffb 2192 /* See if we can calculate the value as the difference between two
2193 valid immediates. */
2194 if (clear_sign_bit_copies + clear_zero_bit_copies <= 16)
2195 {
2196 int topshift = clear_sign_bit_copies & ~1;
2197
3b85fd4d 2198 temp1 = ARM_SIGN_EXTEND ((remainder + (0x00800000 >> topshift))
2199 & (0xff000000 >> topshift));
d430cffb 2200
2201 /* If temp1 is zero, then that means the 9 most significant
2202 bits of remainder were 1 and we've caused it to overflow.
2203 When topshift is 0 we don't need to do anything since we
2204 can borrow from 'bit 32'. */
2205 if (temp1 == 0 && topshift != 0)
2206 temp1 = 0x80000000 >> (topshift - 1);
2207
3b85fd4d 2208 temp2 = ARM_SIGN_EXTEND (temp1 - remainder);
a60f1840 2209
d430cffb 2210 if (const_ok_for_arm (temp2))
2211 {
2212 if (generate)
2213 {
2214 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
2215 emit_constant_insn (cond,
2216 gen_rtx_SET (VOIDmode, new_src,
2217 GEN_INT (temp1)));
2218 emit_constant_insn (cond,
2219 gen_addsi3 (target, new_src,
2220 GEN_INT (-temp2)));
2221 }
2222
2223 return 2;
2224 }
2225 }
2226
4b6897e9 2227 /* See if we can generate this by setting the bottom (or the top)
2228 16 bits, and then shifting these into the other half of the
2229 word. We only look for the simplest cases, to do more would cost
2230 too much. Be careful, however, not to generate this when the
2231 alternative would take fewer insns. */
35cea10c 2232 if (val & 0xffff0000)
4b6897e9 2233 {
35cea10c 2234 temp1 = remainder & 0xffff0000;
4b6897e9 2235 temp2 = remainder & 0x0000ffff;
2236
66aacf41 2237 /* Overlaps outside this range are best done using other methods. */
4b6897e9 2238 for (i = 9; i < 24; i++)
2239 {
35cea10c 2240 if ((((temp2 | (temp2 << i)) & 0xffffffff) == remainder)
215b30b3 2241 && !const_ok_for_arm (temp2))
4b6897e9 2242 {
997e4174 2243 rtx new_src = (subtargets
2244 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)
2245 : target);
96f57e36 2246 insns = arm_gen_constant (code, mode, cond, temp2, new_src,
64266206 2247 source, subtargets, generate);
4b6897e9 2248 source = new_src;
64266206 2249 if (generate)
9e7454d0 2250 emit_constant_insn
96f57e36 2251 (cond,
2252 gen_rtx_SET
2253 (VOIDmode, target,
2254 gen_rtx_IOR (mode,
2255 gen_rtx_ASHIFT (mode, source,
2256 GEN_INT (i)),
2257 source)));
4b6897e9 2258 return insns + 1;
2259 }
2260 }
2261
66aacf41 2262 /* Don't duplicate cases already considered. */
4b6897e9 2263 for (i = 17; i < 24; i++)
2264 {
2265 if (((temp1 | (temp1 >> i)) == remainder)
215b30b3 2266 && !const_ok_for_arm (temp1))
4b6897e9 2267 {
997e4174 2268 rtx new_src = (subtargets
2269 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)
2270 : target);
96f57e36 2271 insns = arm_gen_constant (code, mode, cond, temp1, new_src,
64266206 2272 source, subtargets, generate);
4b6897e9 2273 source = new_src;
64266206 2274 if (generate)
96f57e36 2275 emit_constant_insn
2276 (cond,
2277 gen_rtx_SET (VOIDmode, target,
76676c8e 2278 gen_rtx_IOR
2279 (mode,
2280 gen_rtx_LSHIFTRT (mode, source,
2281 GEN_INT (i)),
2282 source)));
4b6897e9 2283 return insns + 1;
2284 }
2285 }
2286 }
2287 break;
2288
2289 case IOR:
2290 case XOR:
57f96f27 2291 /* If we have IOR or XOR, and the constant can be loaded in a
2292 single instruction, and we can find a temporary to put it in,
4b6897e9 2293 then this can be done in two instructions instead of 3-4. */
2294 if (subtargets
997e4174 2295 /* TARGET can't be NULL if SUBTARGETS is 0 */
215b30b3 2296 || (reload_completed && !reg_mentioned_p (target, source)))
4b6897e9 2297 {
215b30b3 2298 if (const_ok_for_arm (ARM_SIGN_EXTEND (~val)))
4b6897e9 2299 {
64266206 2300 if (generate)
2301 {
2302 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
4b6897e9 2303
96f57e36 2304 emit_constant_insn (cond,
9e7454d0 2305 gen_rtx_SET (VOIDmode, sub,
96f57e36 2306 GEN_INT (val)));
2307 emit_constant_insn (cond,
9e7454d0 2308 gen_rtx_SET (VOIDmode, target,
96f57e36 2309 gen_rtx_fmt_ee (code, mode,
2310 source, sub)));
64266206 2311 }
4b6897e9 2312 return 2;
2313 }
2314 }
2315
2316 if (code == XOR)
2317 break;
2318
2319 if (set_sign_bit_copies > 8
2320 && (val & (-1 << (32 - set_sign_bit_copies))) == val)
2321 {
64266206 2322 if (generate)
2323 {
2324 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
2325 rtx shift = GEN_INT (set_sign_bit_copies);
2326
9e7454d0 2327 emit_constant_insn
96f57e36 2328 (cond,
2329 gen_rtx_SET (VOIDmode, sub,
9e7454d0 2330 gen_rtx_NOT (mode,
96f57e36 2331 gen_rtx_ASHIFT (mode,
9e7454d0 2332 source,
96f57e36 2333 shift))));
9e7454d0 2334 emit_constant_insn
96f57e36 2335 (cond,
2336 gen_rtx_SET (VOIDmode, target,
2337 gen_rtx_NOT (mode,
2338 gen_rtx_LSHIFTRT (mode, sub,
2339 shift))));
64266206 2340 }
4b6897e9 2341 return 2;
2342 }
2343
2344 if (set_zero_bit_copies > 8
2345 && (remainder & ((1 << set_zero_bit_copies) - 1)) == remainder)
2346 {
64266206 2347 if (generate)
2348 {
2349 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
2350 rtx shift = GEN_INT (set_zero_bit_copies);
2351
96f57e36 2352 emit_constant_insn
2353 (cond,
2354 gen_rtx_SET (VOIDmode, sub,
2355 gen_rtx_NOT (mode,
2356 gen_rtx_LSHIFTRT (mode,
2357 source,
2358 shift))));
9e7454d0 2359 emit_constant_insn
96f57e36 2360 (cond,
2361 gen_rtx_SET (VOIDmode, target,
2362 gen_rtx_NOT (mode,
2363 gen_rtx_ASHIFT (mode, sub,
2364 shift))));
64266206 2365 }
4b6897e9 2366 return 2;
2367 }
2368
215b30b3 2369 if (const_ok_for_arm (temp1 = ARM_SIGN_EXTEND (~val)))
4b6897e9 2370 {
64266206 2371 if (generate)
2372 {
2373 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
96f57e36 2374 emit_constant_insn (cond,
2375 gen_rtx_SET (VOIDmode, sub,
2376 gen_rtx_NOT (mode, source)));
64266206 2377 source = sub;
2378 if (subtargets)
2379 sub = gen_reg_rtx (mode);
96f57e36 2380 emit_constant_insn (cond,
2381 gen_rtx_SET (VOIDmode, sub,
9e7454d0 2382 gen_rtx_AND (mode, source,
96f57e36 2383 GEN_INT (temp1))));
2384 emit_constant_insn (cond,
2385 gen_rtx_SET (VOIDmode, target,
2386 gen_rtx_NOT (mode, sub)));
64266206 2387 }
4b6897e9 2388 return 3;
2389 }
2390 break;
2391
2392 case AND:
2393 /* See if two shifts will do 2 or more insn's worth of work. */
2394 if (clear_sign_bit_copies >= 16 && clear_sign_bit_copies < 24)
2395 {
35cea10c 2396 HOST_WIDE_INT shift_mask = ((0xffffffff
4b6897e9 2397 << (32 - clear_sign_bit_copies))
35cea10c 2398 & 0xffffffff);
4b6897e9 2399
35cea10c 2400 if ((remainder | shift_mask) != 0xffffffff)
4b6897e9 2401 {
64266206 2402 if (generate)
2403 {
997e4174 2404 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
9e7454d0 2405 insns = arm_gen_constant (AND, mode, cond,
96f57e36 2406 remainder | shift_mask,
997e4174 2407 new_src, source, subtargets, 1);
2408 source = new_src;
64266206 2409 }
2410 else
997e4174 2411 {
2412 rtx targ = subtargets ? NULL_RTX : target;
96f57e36 2413 insns = arm_gen_constant (AND, mode, cond,
2414 remainder | shift_mask,
997e4174 2415 targ, source, subtargets, 0);
2416 }
64266206 2417 }
2418
2419 if (generate)
2420 {
997e4174 2421 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
2422 rtx shift = GEN_INT (clear_sign_bit_copies);
2423
2424 emit_insn (gen_ashlsi3 (new_src, source, shift));
2425 emit_insn (gen_lshrsi3 (target, new_src, shift));
4b6897e9 2426 }
2427
4b6897e9 2428 return insns + 2;
2429 }
2430
2431 if (clear_zero_bit_copies >= 16 && clear_zero_bit_copies < 24)
2432 {
2433 HOST_WIDE_INT shift_mask = (1 << clear_zero_bit_copies) - 1;
9e7454d0 2434
35cea10c 2435 if ((remainder | shift_mask) != 0xffffffff)
4b6897e9 2436 {
64266206 2437 if (generate)
2438 {
997e4174 2439 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
2440
96f57e36 2441 insns = arm_gen_constant (AND, mode, cond,
2442 remainder | shift_mask,
997e4174 2443 new_src, source, subtargets, 1);
2444 source = new_src;
64266206 2445 }
2446 else
997e4174 2447 {
2448 rtx targ = subtargets ? NULL_RTX : target;
2449
96f57e36 2450 insns = arm_gen_constant (AND, mode, cond,
2451 remainder | shift_mask,
997e4174 2452 targ, source, subtargets, 0);
2453 }
64266206 2454 }
2455
2456 if (generate)
2457 {
997e4174 2458 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
2459 rtx shift = GEN_INT (clear_zero_bit_copies);
2460
2461 emit_insn (gen_lshrsi3 (new_src, source, shift));
2462 emit_insn (gen_ashlsi3 (target, new_src, shift));
4b6897e9 2463 }
2464
4b6897e9 2465 return insns + 2;
2466 }
2467
2468 break;
2469
2470 default:
2471 break;
2472 }
2473
2474 for (i = 0; i < 32; i++)
2475 if (remainder & (1 << i))
2476 num_bits_set++;
2477
2478 if (code == AND || (can_invert && num_bits_set > 16))
35cea10c 2479 remainder = (~remainder) & 0xffffffff;
4b6897e9 2480 else if (code == PLUS && num_bits_set > 16)
35cea10c 2481 remainder = (-remainder) & 0xffffffff;
4b6897e9 2482 else
2483 {
2484 can_invert = 0;
2485 can_negate = 0;
2486 }
2487
2488 /* Now try and find a way of doing the job in either two or three
2489 instructions.
2490 We start by looking for the largest block of zeros that are aligned on
2491 a 2-bit boundary, we then fill up the temps, wrapping around to the
2492 top of the word when we drop off the bottom.
25f905c2 2493 In the worst case this code should produce no more than four insns.
2494 Thumb-2 constants are shifted, not rotated, so the MSB is always the
2495 best place to start. */
2496
2497 /* ??? Use thumb2 replicated constants when the high and low halfwords are
2498 the same. */
4b6897e9 2499 {
2500 int best_start = 0;
25f905c2 2501 if (!TARGET_THUMB2)
4b6897e9 2502 {
25f905c2 2503 int best_consecutive_zeros = 0;
4b6897e9 2504
25f905c2 2505 for (i = 0; i < 32; i += 2)
4b6897e9 2506 {
25f905c2 2507 int consecutive_zeros = 0;
2508
2509 if (!(remainder & (3 << i)))
4b6897e9 2510 {
25f905c2 2511 while ((i < 32) && !(remainder & (3 << i)))
2512 {
2513 consecutive_zeros += 2;
2514 i += 2;
2515 }
2516 if (consecutive_zeros > best_consecutive_zeros)
2517 {
2518 best_consecutive_zeros = consecutive_zeros;
2519 best_start = i - consecutive_zeros;
2520 }
2521 i -= 2;
4b6897e9 2522 }
4b6897e9 2523 }
cd8df93e 2524
25f905c2 2525 /* So long as it won't require any more insns to do so, it's
2526 desirable to emit a small constant (in bits 0...9) in the last
2527 insn. This way there is more chance that it can be combined with
2528 a later addressing insn to form a pre-indexed load or store
2529 operation. Consider:
2530
2531 *((volatile int *)0xe0000100) = 1;
2532 *((volatile int *)0xe0000110) = 2;
2533
2534 We want this to wind up as:
2535
2536 mov rA, #0xe0000000
2537 mov rB, #1
2538 str rB, [rA, #0x100]
2539 mov rB, #2
2540 str rB, [rA, #0x110]
2541
2542 rather than having to synthesize both large constants from scratch.
2543
2544 Therefore, we calculate how many insns would be required to emit
2545 the constant starting from `best_start', and also starting from
2546 zero (i.e. with bit 31 first to be output). If `best_start' doesn't
2547 yield a shorter sequence, we may as well use zero. */
2548 if (best_start != 0
2549 && ((((unsigned HOST_WIDE_INT) 1) << best_start) < remainder)
2550 && (count_insns_for_constant (remainder, 0) <=
2551 count_insns_for_constant (remainder, best_start)))
2552 best_start = 0;
2553 }
cd8df93e 2554
2555 /* Now start emitting the insns. */
4b6897e9 2556 i = best_start;
2557 do
2558 {
2559 int end;
2560
2561 if (i <= 0)
2562 i += 32;
2563 if (remainder & (3 << (i - 2)))
2564 {
2565 end = i - 8;
2566 if (end < 0)
2567 end += 32;
2568 temp1 = remainder & ((0x0ff << end)
2569 | ((i < end) ? (0xff >> (32 - end)) : 0));
2570 remainder &= ~temp1;
2571
997e4174 2572 if (generate)
4b6897e9 2573 {
6382d316 2574 rtx new_src, temp1_rtx;
2575
2576 if (code == SET || code == MINUS)
2577 {
2578 new_src = (subtargets ? gen_reg_rtx (mode) : target);
b6557085 2579 if (can_invert && code != MINUS)
6382d316 2580 temp1 = ~temp1;
2581 }
2582 else
2583 {
b6557085 2584 if (remainder && subtargets)
6382d316 2585 new_src = gen_reg_rtx (mode);
b6557085 2586 else
2587 new_src = target;
6382d316 2588 if (can_invert)
2589 temp1 = ~temp1;
2590 else if (can_negate)
2591 temp1 = -temp1;
2592 }
2593
2594 temp1 = trunc_int_for_mode (temp1, mode);
2595 temp1_rtx = GEN_INT (temp1);
997e4174 2596
2597 if (code == SET)
6382d316 2598 ;
997e4174 2599 else if (code == MINUS)
6382d316 2600 temp1_rtx = gen_rtx_MINUS (mode, temp1_rtx, source);
997e4174 2601 else
6382d316 2602 temp1_rtx = gen_rtx_fmt_ee (code, mode, source, temp1_rtx);
2603
96f57e36 2604 emit_constant_insn (cond,
9e7454d0 2605 gen_rtx_SET (VOIDmode, new_src,
96f57e36 2606 temp1_rtx));
997e4174 2607 source = new_src;
4b6897e9 2608 }
2609
997e4174 2610 if (code == SET)
2611 {
2612 can_invert = 0;
2613 code = PLUS;
2614 }
2615 else if (code == MINUS)
2616 code = PLUS;
2617
4b6897e9 2618 insns++;
25f905c2 2619 if (TARGET_ARM)
2620 i -= 6;
2621 else
2622 i -= 7;
4b6897e9 2623 }
542d5028 2624 /* Arm allows rotates by a multiple of two. Thumb-2 allows arbitrary
25f905c2 2625 shifts. */
2626 if (TARGET_ARM)
2627 i -= 2;
2628 else
2629 i--;
a12be13c 2630 }
2631 while (remainder);
4b6897e9 2632 }
a12be13c 2633
4b6897e9 2634 return insns;
2635}
2636
9480e6c7 2637/* Canonicalize a comparison so that we are more likely to recognize it.
2638 This can be done for a few constant compares, where we can make the
2639 immediate value easier to load. */
a12be13c 2640
9480e6c7 2641enum rtx_code
aa3c2d40 2642arm_canonicalize_comparison (enum rtx_code code, enum machine_mode mode,
2643 rtx * op1)
9480e6c7 2644{
ecd3fcc7 2645 unsigned HOST_WIDE_INT i = INTVAL (*op1);
aa3c2d40 2646 unsigned HOST_WIDE_INT maxval;
2647 maxval = (((unsigned HOST_WIDE_INT) 1) << (GET_MODE_BITSIZE(mode) - 1)) - 1;
9480e6c7 2648
2649 switch (code)
2650 {
2651 case EQ:
2652 case NE:
2653 return code;
2654
2655 case GT:
2656 case LE:
aa3c2d40 2657 if (i != maxval
215b30b3 2658 && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1))))
9480e6c7 2659 {
215b30b3 2660 *op1 = GEN_INT (i + 1);
9480e6c7 2661 return code == GT ? GE : LT;
2662 }
2663 break;
2664
2665 case GE:
2666 case LT:
aa3c2d40 2667 if (i != ~maxval
215b30b3 2668 && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1))))
9480e6c7 2669 {
215b30b3 2670 *op1 = GEN_INT (i - 1);
9480e6c7 2671 return code == GE ? GT : LE;
2672 }
2673 break;
2674
2675 case GTU:
2676 case LEU:
35cea10c 2677 if (i != ~((unsigned HOST_WIDE_INT) 0)
215b30b3 2678 && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1))))
9480e6c7 2679 {
2680 *op1 = GEN_INT (i + 1);
2681 return code == GTU ? GEU : LTU;
2682 }
2683 break;
2684
2685 case GEU:
2686 case LTU:
2687 if (i != 0
215b30b3 2688 && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1))))
9480e6c7 2689 {
2690 *op1 = GEN_INT (i - 1);
2691 return code == GEU ? GTU : LEU;
2692 }
2693 break;
2694
2695 default:
ed29c566 2696 gcc_unreachable ();
9480e6c7 2697 }
2698
2699 return code;
2700}
9480e6c7 2701
19347327 2702
2703/* Define how to find the value returned by a function. */
2704
ccd90aaa 2705rtx
2706arm_function_value(tree type, tree func ATTRIBUTE_UNUSED)
19347327 2707{
2708 enum machine_mode mode;
2709 int unsignedp ATTRIBUTE_UNUSED;
2710 rtx r ATTRIBUTE_UNUSED;
2711
19347327 2712 mode = TYPE_MODE (type);
2713 /* Promote integer types. */
2714 if (INTEGRAL_TYPE_P (type))
2715 PROMOTE_FUNCTION_MODE (mode, unsignedp, type);
46b5d878 2716
2717 /* Promotes small structs returned in a register to full-word size
2718 for big-endian AAPCS. */
2719 if (arm_return_in_msb (type))
2720 {
2721 HOST_WIDE_INT size = int_size_in_bytes (type);
2722 if (size % UNITS_PER_WORD != 0)
2723 {
2724 size += UNITS_PER_WORD - size % UNITS_PER_WORD;
2725 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
2726 }
2727 }
a60f1840 2728
19347327 2729 return LIBCALL_VALUE(mode);
2730}
2731
a60f1840 2732/* Determine the amount of memory needed to store the possible return
ccd90aaa 2733 registers of an untyped call. */
2734int
2735arm_apply_result_size (void)
2736{
2737 int size = 16;
2738
2739 if (TARGET_ARM)
2740 {
2741 if (TARGET_HARD_FLOAT_ABI)
2742 {
2743 if (TARGET_FPA)
2744 size += 12;
2745 if (TARGET_MAVERICK)
2746 size += 8;
2747 }
2748 if (TARGET_IWMMXT_ABI)
2749 size += 8;
2750 }
2751
2752 return size;
2753}
19347327 2754
9888ad6d 2755/* Decide whether a type should be returned in memory (true)
2756 or in a register (false). This is called by the macro
2757 RETURN_IN_MEMORY. */
64266206 2758int
ebd88a36 2759arm_return_in_memory (tree type)
64266206 2760{
1e00c159 2761 HOST_WIDE_INT size;
2762
d98a3884 2763 size = int_size_in_bytes (type);
2764
2765 /* Vector values should be returned using ARM registers, not memory (unless
2766 they're over 16 bytes, which will break since we only have four
2767 call-clobbered registers to play with). */
2768 if (TREE_CODE (type) == VECTOR_TYPE)
2769 return (size < 0 || size > (4 * UNITS_PER_WORD));
2770
1a3ba46f 2771 if (!AGGREGATE_TYPE_P (type) &&
2772 !(TARGET_AAPCS_BASED && TREE_CODE (type) == COMPLEX_TYPE))
2773 /* All simple types are returned in registers.
2774 For AAPCS, complex types are treated the same as aggregates. */
29a6fe51 2775 return 0;
1e00c159 2776
f9273c43 2777 if (arm_abi != ARM_ABI_APCS)
1e00c159 2778 {
f9273c43 2779 /* ATPCS and later return aggregate types in memory only if they are
1e00c159 2780 larger than a word (or are variable size). */
2781 return (size < 0 || size > UNITS_PER_WORD);
2782 }
9e7454d0 2783
b89db9a7 2784 /* For the arm-wince targets we choose to be compatible with Microsoft's
cffb2a26 2785 ARM and Thumb compilers, which always return aggregates in memory. */
2786#ifndef ARM_WINCE
b7e2e8e6 2787 /* All structures/unions bigger than one word are returned in memory.
2788 Also catch the case where int_size_in_bytes returns -1. In this case
b89db9a7 2789 the aggregate is either huge or of variable size, and in either case
b7e2e8e6 2790 we will want to return it via memory and not in a register. */
1e00c159 2791 if (size < 0 || size > UNITS_PER_WORD)
29a6fe51 2792 return 1;
9e7454d0 2793
29a6fe51 2794 if (TREE_CODE (type) == RECORD_TYPE)
64266206 2795 {
2796 tree field;
2797
3accc59a 2798 /* For a struct the APCS says that we only return in a register
2799 if the type is 'integer like' and every addressable element
2800 has an offset of zero. For practical purposes this means
2801 that the structure can have at most one non bit-field element
2802 and that this element must be the first one in the structure. */
9e7454d0 2803
9888ad6d 2804 /* Find the first field, ignoring non FIELD_DECL things which will
2805 have been created by C++. */
2806 for (field = TYPE_FIELDS (type);
2807 field && TREE_CODE (field) != FIELD_DECL;
2808 field = TREE_CHAIN (field))
2809 continue;
9e7454d0 2810
9888ad6d 2811 if (field == NULL)
f5daaea4 2812 return 0; /* An empty structure. Allowed by an extension to ANSI C. */
9888ad6d 2813
cffb2a26 2814 /* Check that the first field is valid for returning in a register. */
2815
2816 /* ... Floats are not allowed */
f5daaea4 2817 if (FLOAT_TYPE_P (TREE_TYPE (field)))
3accc59a 2818 return 1;
2819
cffb2a26 2820 /* ... Aggregates that are not themselves valid for returning in
2821 a register are not allowed. */
f5daaea4 2822 if (RETURN_IN_MEMORY (TREE_TYPE (field)))
3accc59a 2823 return 1;
89b30d75 2824
3accc59a 2825 /* Now check the remaining fields, if any. Only bitfields are allowed,
2826 since they are not addressable. */
9888ad6d 2827 for (field = TREE_CHAIN (field);
2828 field;
2829 field = TREE_CHAIN (field))
2830 {
2831 if (TREE_CODE (field) != FIELD_DECL)
2832 continue;
9e7454d0 2833
215b30b3 2834 if (!DECL_BIT_FIELD_TYPE (field))
9888ad6d 2835 return 1;
2836 }
64266206 2837
2838 return 0;
2839 }
9e7454d0 2840
29a6fe51 2841 if (TREE_CODE (type) == UNION_TYPE)
64266206 2842 {
2843 tree field;
2844
2845 /* Unions can be returned in registers if every element is
2846 integral, or can be returned in an integer register. */
9888ad6d 2847 for (field = TYPE_FIELDS (type);
2848 field;
2849 field = TREE_CHAIN (field))
64266206 2850 {
9888ad6d 2851 if (TREE_CODE (field) != FIELD_DECL)
2852 continue;
2853
7bd8ccc9 2854 if (FLOAT_TYPE_P (TREE_TYPE (field)))
2855 return 1;
9e7454d0 2856
9888ad6d 2857 if (RETURN_IN_MEMORY (TREE_TYPE (field)))
64266206 2858 return 1;
2859 }
9e7454d0 2860
64266206 2861 return 0;
2862 }
9e7454d0 2863#endif /* not ARM_WINCE */
2864
cffb2a26 2865 /* Return all other types in memory. */
64266206 2866 return 1;
2867}
2868
674a8f0b 2869/* Indicate whether or not words of a double are in big-endian order. */
3d94d3fa 2870
2871int
ebd88a36 2872arm_float_words_big_endian (void)
3d94d3fa 2873{
a2cd141b 2874 if (TARGET_MAVERICK)
7d57ec45 2875 return 0;
3d94d3fa 2876
2877 /* For FPA, float words are always big-endian. For VFP, floats words
2878 follow the memory system mode. */
2879
a2cd141b 2880 if (TARGET_FPA)
3d94d3fa 2881 {
3d94d3fa 2882 return 1;
2883 }
2884
2885 if (TARGET_VFP)
2886 return (TARGET_BIG_END ? 1 : 0);
2887
2888 return 1;
2889}
2890
a52eca60 2891/* Initialize a variable CUM of type CUMULATIVE_ARGS
2892 for a call to a function whose data type is FNTYPE.
2893 For a library call, FNTYPE is NULL. */
2894void
9e7454d0 2895arm_init_cumulative_args (CUMULATIVE_ARGS *pcum, tree fntype,
ebd88a36 2896 rtx libname ATTRIBUTE_UNUSED,
2897 tree fndecl ATTRIBUTE_UNUSED)
a52eca60 2898{
2899 /* On the ARM, the offset starts at 0. */
f2be8f2b 2900 pcum->nregs = 0;
755eb2b4 2901 pcum->iwmmxt_nregs = 0;
f9273c43 2902 pcum->can_split = true;
9e7454d0 2903
755eb2b4 2904 /* Varargs vectors are treated the same as long long.
2905 named_count avoids having to change the way arm handles 'named' */
2906 pcum->named_count = 0;
2907 pcum->nargs = 0;
2908
2909 if (TARGET_REALLY_IWMMXT && fntype)
2910 {
2911 tree fn_arg;
2912
2913 for (fn_arg = TYPE_ARG_TYPES (fntype);
2914 fn_arg;
2915 fn_arg = TREE_CHAIN (fn_arg))
2916 pcum->named_count += 1;
2917
2918 if (! pcum->named_count)
2919 pcum->named_count = INT_MAX;
2920 }
a52eca60 2921}
2922
f9273c43 2923
2924/* Return true if mode/type need doubleword alignment. */
2925bool
2926arm_needs_doubleword_align (enum machine_mode mode, tree type)
2927{
9c291064 2928 return (GET_MODE_ALIGNMENT (mode) > PARM_BOUNDARY
2929 || (type && TYPE_ALIGN (type) > PARM_BOUNDARY));
f9273c43 2930}
2931
2932
a52eca60 2933/* Determine where to put an argument to a function.
2934 Value is zero to push the argument on the stack,
2935 or a hard register in which to store the argument.
2936
2937 MODE is the argument's machine mode.
2938 TYPE is the data type of the argument (as a tree).
2939 This is null for libcalls where that information may
2940 not be available.
2941 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2942 the preceding args and about the function being called.
2943 NAMED is nonzero if this argument is a named parameter
2944 (otherwise it is an extra parameter matching an ellipsis). */
a12be13c 2945
a52eca60 2946rtx
ebd88a36 2947arm_function_arg (CUMULATIVE_ARGS *pcum, enum machine_mode mode,
f9273c43 2948 tree type, int named)
a52eca60 2949{
f9273c43 2950 int nregs;
2951
2952 /* Varargs vectors are treated the same as long long.
2953 named_count avoids having to change the way arm handles 'named' */
2954 if (TARGET_IWMMXT_ABI
9e7454d0 2955 && arm_vector_mode_supported_p (mode)
f9273c43 2956 && pcum->named_count > pcum->nargs + 1)
755eb2b4 2957 {
f9273c43 2958 if (pcum->iwmmxt_nregs <= 9)
2959 return gen_rtx_REG (mode, pcum->iwmmxt_nregs + FIRST_IWMMXT_REGNUM);
2960 else
755eb2b4 2961 {
f9273c43 2962 pcum->can_split = false;
2963 return NULL_RTX;
755eb2b4 2964 }
755eb2b4 2965 }
2966
f9273c43 2967 /* Put doubleword aligned quantities in even register pairs. */
2968 if (pcum->nregs & 1
2969 && ARM_DOUBLEWORD_ALIGN
2970 && arm_needs_doubleword_align (mode, type))
2971 pcum->nregs++;
2972
a52eca60 2973 if (mode == VOIDmode)
de55252a 2974 /* Pick an arbitrary value for operand 2 of the call insn. */
2975 return const0_rtx;
f9273c43 2976
af6ed417 2977 /* Only allow splitting an arg between regs and memory if all preceding
f9273c43 2978 args were allocated to regs. For args passed by reference we only count
2979 the reference pointer. */
2980 if (pcum->can_split)
2981 nregs = 1;
2982 else
2983 nregs = ARM_NUM_REGS2 (mode, type);
2984
2985 if (!named || pcum->nregs + nregs > NUM_ARG_REGS)
a52eca60 2986 return NULL_RTX;
9e7454d0 2987
a52eca60 2988 return gen_rtx_REG (mode, pcum->nregs);
2989}
78aea6a2 2990
f054eb3c 2991static int
2992arm_arg_partial_bytes (CUMULATIVE_ARGS *pcum, enum machine_mode mode,
2993 tree type, bool named ATTRIBUTE_UNUSED)
2994{
2995 int nregs = pcum->nregs;
2996
d98a3884 2997 if (TARGET_IWMMXT_ABI && arm_vector_mode_supported_p (mode))
f054eb3c 2998 return 0;
2999
3000 if (NUM_ARG_REGS > nregs
3001 && (NUM_ARG_REGS < nregs + ARM_NUM_REGS2 (mode, type))
3002 && pcum->can_split)
3003 return (NUM_ARG_REGS - nregs) * UNITS_PER_WORD;
3004
3005 return 0;
3006}
3007
78aea6a2 3008/* Variable sized types are passed by reference. This is a GCC
3009 extension to the ARM ABI. */
3010
b981d932 3011static bool
3012arm_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
3013 enum machine_mode mode ATTRIBUTE_UNUSED,
3014 tree type, bool named ATTRIBUTE_UNUSED)
78aea6a2 3015{
3016 return type && TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST;
3017}
a52eca60 3018\f
78fe751b 3019/* Encode the current state of the #pragma [no_]long_calls. */
3020typedef enum
a52eca60 3021{
554f2707 3022 OFF, /* No #pragma [no_]long_calls is in effect. */
78fe751b 3023 LONG, /* #pragma long_calls is in effect. */
3024 SHORT /* #pragma no_long_calls is in effect. */
3025} arm_pragma_enum;
a52eca60 3026
78fe751b 3027static arm_pragma_enum arm_pragma_long_calls = OFF;
a52eca60 3028
1fcd08b1 3029void
ebd88a36 3030arm_pr_long_calls (struct cpp_reader * pfile ATTRIBUTE_UNUSED)
a52eca60 3031{
1fcd08b1 3032 arm_pragma_long_calls = LONG;
3033}
3034
3035void
ebd88a36 3036arm_pr_no_long_calls (struct cpp_reader * pfile ATTRIBUTE_UNUSED)
1fcd08b1 3037{
3038 arm_pragma_long_calls = SHORT;
3039}
3040
3041void
ebd88a36 3042arm_pr_long_calls_off (struct cpp_reader * pfile ATTRIBUTE_UNUSED)
1fcd08b1 3043{
3044 arm_pragma_long_calls = OFF;
a52eca60 3045}
3046\f
e3c541f0 3047/* Table of machine attributes. */
3048const struct attribute_spec arm_attribute_table[] =
a52eca60 3049{
e3c541f0 3050 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
a52eca60 3051 /* Function calls made to this symbol must be done indirectly, because
3052 it may lie outside of the 26 bit addressing range of a normal function
3053 call. */
e3c541f0 3054 { "long_call", 0, 0, false, true, true, NULL },
a52eca60 3055 /* Whereas these functions are always known to reside within the 26 bit
3056 addressing range. */
e3c541f0 3057 { "short_call", 0, 0, false, true, true, NULL },
9e7454d0 3058 /* Interrupt Service Routines have special prologue and epilogue requirements. */
e3c541f0 3059 { "isr", 0, 1, false, false, false, arm_handle_isr_attribute },
3060 { "interrupt", 0, 1, false, false, false, arm_handle_isr_attribute },
3061 { "naked", 0, 0, true, false, false, arm_handle_fndecl_attribute },
3062#ifdef ARM_PE
3063 /* ARM/PE has three new attributes:
3064 interfacearm - ?
3065 dllexport - for exporting a function/variable that will live in a dll
3066 dllimport - for importing a function/variable from a dll
3067
3068 Microsoft allows multiple declspecs in one __declspec, separating
3069 them with spaces. We do NOT support this. Instead, use __declspec
3070 multiple times.
3071 */
3072 { "dllimport", 0, 0, true, false, false, NULL },
3073 { "dllexport", 0, 0, true, false, false, NULL },
3074 { "interfacearm", 0, 0, true, false, false, arm_handle_fndecl_attribute },
3aa0c315 3075#elif TARGET_DLLIMPORT_DECL_ATTRIBUTES
3076 { "dllimport", 0, 0, false, false, false, handle_dll_attribute },
3077 { "dllexport", 0, 0, false, false, false, handle_dll_attribute },
a79b1d93 3078 { "notshared", 0, 0, false, true, false, arm_handle_notshared_attribute },
e3c541f0 3079#endif
3080 { NULL, 0, 0, false, false, false, NULL }
3081};
e27ad2d5 3082
e3c541f0 3083/* Handle an attribute requiring a FUNCTION_DECL;
3084 arguments as in struct attribute_spec.handler. */
3085static tree
ebd88a36 3086arm_handle_fndecl_attribute (tree *node, tree name, tree args ATTRIBUTE_UNUSED,
3087 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
e3c541f0 3088{
3089 if (TREE_CODE (*node) != FUNCTION_DECL)
3090 {
9b2d6d13 3091 warning (OPT_Wattributes, "%qs attribute only applies to functions",
e3c541f0 3092 IDENTIFIER_POINTER (name));
3093 *no_add_attrs = true;
3094 }
3095
3096 return NULL_TREE;
3097}
3098
3099/* Handle an "interrupt" or "isr" attribute;
3100 arguments as in struct attribute_spec.handler. */
3101static tree
ebd88a36 3102arm_handle_isr_attribute (tree *node, tree name, tree args, int flags,
3103 bool *no_add_attrs)
e3c541f0 3104{
3105 if (DECL_P (*node))
3106 {
3107 if (TREE_CODE (*node) != FUNCTION_DECL)
3108 {
9b2d6d13 3109 warning (OPT_Wattributes, "%qs attribute only applies to functions",
e3c541f0 3110 IDENTIFIER_POINTER (name));
3111 *no_add_attrs = true;
3112 }
3113 /* FIXME: the argument if any is checked for type attributes;
3114 should it be checked for decl ones? */
3115 }
3116 else
3117 {
3118 if (TREE_CODE (*node) == FUNCTION_TYPE
3119 || TREE_CODE (*node) == METHOD_TYPE)
3120 {
3121 if (arm_isr_value (args) == ARM_FT_UNKNOWN)
3122 {
9b2d6d13 3123 warning (OPT_Wattributes, "%qs attribute ignored",
3124 IDENTIFIER_POINTER (name));
e3c541f0 3125 *no_add_attrs = true;
3126 }
3127 }
3128 else if (TREE_CODE (*node) == POINTER_TYPE
3129 && (TREE_CODE (TREE_TYPE (*node)) == FUNCTION_TYPE
3130 || TREE_CODE (TREE_TYPE (*node)) == METHOD_TYPE)
3131 && arm_isr_value (args) != ARM_FT_UNKNOWN)
3132 {
e086912e 3133 *node = build_variant_type_copy (*node);
a12be13c 3134 TREE_TYPE (*node) = build_type_attribute_variant
3135 (TREE_TYPE (*node),
3136 tree_cons (name, args, TYPE_ATTRIBUTES (TREE_TYPE (*node))));
e3c541f0 3137 *no_add_attrs = true;
3138 }
3139 else
3140 {
3141 /* Possibly pass this attribute on from the type to a decl. */
3142 if (flags & ((int) ATTR_FLAG_DECL_NEXT
3143 | (int) ATTR_FLAG_FUNCTION_NEXT
3144 | (int) ATTR_FLAG_ARRAY_NEXT))
3145 {
3146 *no_add_attrs = true;
3147 return tree_cons (name, args, NULL_TREE);
3148 }
3149 else
3150 {
9b2d6d13 3151 warning (OPT_Wattributes, "%qs attribute ignored",
3152 IDENTIFIER_POINTER (name));
e3c541f0 3153 }
3154 }
3155 }
3156
3157 return NULL_TREE;
a52eca60 3158}
3159
56826b58 3160#if TARGET_DLLIMPORT_DECL_ATTRIBUTES
a79b1d93 3161/* Handle the "notshared" attribute. This attribute is another way of
3162 requesting hidden visibility. ARM's compiler supports
3163 "__declspec(notshared)"; we support the same thing via an
3164 attribute. */
3165
3166static tree
a60f1840 3167arm_handle_notshared_attribute (tree *node,
3168 tree name ATTRIBUTE_UNUSED,
3169 tree args ATTRIBUTE_UNUSED,
3170 int flags ATTRIBUTE_UNUSED,
a79b1d93 3171 bool *no_add_attrs)
3172{
3173 tree decl = TYPE_NAME (*node);
3174
3175 if (decl)
3176 {
3177 DECL_VISIBILITY (decl) = VISIBILITY_HIDDEN;
3178 DECL_VISIBILITY_SPECIFIED (decl) = 1;
3179 *no_add_attrs = false;
3180 }
3181 return NULL_TREE;
3182}
56826b58 3183#endif
a79b1d93 3184
a52eca60 3185/* Return 0 if the attributes for two types are incompatible, 1 if they
3186 are compatible, and 2 if they are nearly compatible (which causes a
3187 warning to be generated). */
f32321da 3188static int
ebd88a36 3189arm_comp_type_attributes (tree type1, tree type2)
a52eca60 3190{
d6c334ee 3191 int l1, l2, s1, s2;
9e7454d0 3192
a52eca60 3193 /* Check for mismatch of non-default calling convention. */
3194 if (TREE_CODE (type1) != FUNCTION_TYPE)
3195 return 1;
3196
3197 /* Check for mismatched call attributes. */
d6c334ee 3198 l1 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type1)) != NULL;
3199 l2 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type2)) != NULL;
3200 s1 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type1)) != NULL;
3201 s2 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type2)) != NULL;
f7387eb0 3202
3203 /* Only bother to check if an attribute is defined. */
3204 if (l1 | l2 | s1 | s2)
3205 {
3206 /* If one type has an attribute, the other must have the same attribute. */
d6c334ee 3207 if ((l1 != l2) || (s1 != s2))
f7387eb0 3208 return 0;
a52eca60 3209
f7387eb0 3210 /* Disallow mixed attributes. */
3211 if ((l1 & s2) || (l2 & s1))
3212 return 0;
3213 }
9e7454d0 3214
e27ad2d5 3215 /* Check for mismatched ISR attribute. */
3216 l1 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type1)) != NULL;
3217 if (! l1)
3218 l1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type1)) != NULL;
3219 l2 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type2)) != NULL;
3220 if (! l2)
3221 l1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type2)) != NULL;
3222 if (l1 != l2)
3223 return 0;
3224
f7387eb0 3225 return 1;
a52eca60 3226}
3227
78fe751b 3228/* Assigns default attributes to newly defined type. This is used to
3229 set short_call/long_call attributes for function types of
3230 functions defined inside corresponding #pragma scopes. */
f32321da 3231static void
ebd88a36 3232arm_set_default_type_attributes (tree type)
78fe751b 3233{
3234 /* Add __attribute__ ((long_call)) to all functions, when
3235 inside #pragma long_calls or __attribute__ ((short_call)),
3236 when inside #pragma no_long_calls. */
3237 if (TREE_CODE (type) == FUNCTION_TYPE || TREE_CODE (type) == METHOD_TYPE)
3238 {
3239 tree type_attr_list, attr_name;
3240 type_attr_list = TYPE_ATTRIBUTES (type);
3241
3242 if (arm_pragma_long_calls == LONG)
3243 attr_name = get_identifier ("long_call");
3244 else if (arm_pragma_long_calls == SHORT)
3245 attr_name = get_identifier ("short_call");
3246 else
3247 return;
3248
3249 type_attr_list = tree_cons (attr_name, NULL_TREE, type_attr_list);
3250 TYPE_ATTRIBUTES (type) = type_attr_list;
3251 }
3252}
3253\f
de55252a 3254/* Return true if DECL is known to be linked into section SECTION. */
3255
3256static bool
3257arm_function_in_section_p (tree decl, section *section)
78fe751b 3258{
de55252a 3259 /* We can only be certain about functions defined in the same
3260 compilation unit. */
3261 if (!TREE_STATIC (decl))
3262 return false;
78fe751b 3263
de55252a 3264 /* Make sure that SYMBOL always binds to the definition in this
3265 compilation unit. */
3266 if (!targetm.binds_local_p (decl))
3267 return false;
78fe751b 3268
de55252a 3269 /* If DECL_SECTION_NAME is set, assume it is trustworthy. */
3270 if (!DECL_SECTION_NAME (decl))
3271 {
3272 /* Only cater for unit-at-a-time mode, where we know that the user
3273 cannot later specify a section for DECL. */
3274 if (!flag_unit_at_a_time)
3275 return false;
3276
3277 /* Make sure that we will not create a unique section for DECL. */
3278 if (flag_function_sections || DECL_ONE_ONLY (decl))
3279 return false;
3280 }
3281
3282 return function_section (decl) == section;
78fe751b 3283}
3284
85c36fd1 3285/* Return nonzero if a 32-bit "long_call" should be generated for
de55252a 3286 a call from the current function to DECL. We generate a long_call
3287 if the function:
78fe751b 3288
3289 a. has an __attribute__((long call))
3290 or b. is within the scope of a #pragma long_calls
3291 or c. the -mlong-calls command line switch has been specified
3292
3293 However we do not generate a long call if the function:
9e7454d0 3294
78fe751b 3295 d. has an __attribute__ ((short_call))
3296 or e. is inside the scope of a #pragma no_long_calls
de55252a 3297 or f. is defined in the same section as the current function. */
78fe751b 3298
de55252a 3299bool
3300arm_is_long_call_p (tree decl)
3301{
3302 tree attrs;
78fe751b 3303
de55252a 3304 if (!decl)
3305 return TARGET_LONG_CALLS;
78fe751b 3306
de55252a 3307 attrs = TYPE_ATTRIBUTES (TREE_TYPE (decl));
3308 if (lookup_attribute ("short_call", attrs))
3309 return false;
78fe751b 3310
de55252a 3311 /* For "f", be conservative, and only cater for cases in which the
3312 whole of the current function is placed in the same section. */
3313 if (!flag_reorder_blocks_and_partition
3314 && arm_function_in_section_p (decl, current_function_section ()))
3315 return false;
a2f6cf84 3316
de55252a 3317 if (lookup_attribute ("long_call", attrs))
3318 return true;
9e7454d0 3319
de55252a 3320 return TARGET_LONG_CALLS;
78fe751b 3321}
9e0922c4 3322
e3e08e7f 3323/* Return nonzero if it is ok to make a tail-call to DECL. */
805e22b2 3324static bool
ebd88a36 3325arm_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
9e0922c4 3326{
25f905c2 3327 unsigned long func_type;
9e0922c4 3328
755eb2b4 3329 if (cfun->machine->sibcall_blocked)
3330 return false;
3331
9e0922c4 3332 /* Never tailcall something for which we have no decl, or if we
3333 are in Thumb mode. */
3334 if (decl == NULL || TARGET_THUMB)
805e22b2 3335 return false;
9e0922c4 3336
bac7fc85 3337 /* The PIC register is live on entry to VxWorks PLT entries, so we
3338 must make the call before restoring the PIC register. */
3339 if (TARGET_VXWORKS_RTP && flag_pic && !targetm.binds_local_p (decl))
3340 return false;
3341
9e0922c4 3342 /* Cannot tail-call to long calls, since these are out of range of
de55252a 3343 a branch instruction. */
3344 if (arm_is_long_call_p (decl))
805e22b2 3345 return false;
9e0922c4 3346
3347 /* If we are interworking and the function is not declared static
9e7454d0 3348 then we can't tail-call it unless we know that it exists in this
9e0922c4 3349 compilation unit (since it might be a Thumb routine). */
215b30b3 3350 if (TARGET_INTERWORK && TREE_PUBLIC (decl) && !TREE_ASM_WRITTEN (decl))
805e22b2 3351 return false;
9e0922c4 3352
25f905c2 3353 func_type = arm_current_func_type ();
e27ad2d5 3354 /* Never tailcall from an ISR routine - it needs a special exit sequence. */
25f905c2 3355 if (IS_INTERRUPT (func_type))
3356 return false;
3357
3358 /* Never tailcall if function may be called with a misaligned SP. */
3359 if (IS_STACKALIGN (func_type))
805e22b2 3360 return false;
e27ad2d5 3361
9e0922c4 3362 /* Everything else is ok. */
805e22b2 3363 return true;
9e0922c4 3364}
3365
a52eca60 3366\f
d32b3557 3367/* Addressing mode support functions. */
3368
bf02170c 3369/* Return nonzero if X is a legitimate immediate operand when compiling
2cb7d577 3370 for PIC. We know that X satisfies CONSTANT_P and flag_pic is true. */
69120d26 3371int
ebd88a36 3372legitimate_pic_operand_p (rtx x)
69120d26 3373{
2cb7d577 3374 if (GET_CODE (x) == SYMBOL_REF
3375 || (GET_CODE (x) == CONST
3376 && GET_CODE (XEXP (x, 0)) == PLUS
3377 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF))
69120d26 3378 return 0;
3379
3380 return 1;
3381}
3382
bac7fc85 3383/* Record that the current function needs a PIC register. Initialize
3384 cfun->machine->pic_reg if we have not already done so. */
3385
3386static void
3387require_pic_register (void)
3388{
3389 /* A lot of the logic here is made obscure by the fact that this
3390 routine gets called as part of the rtx cost estimation process.
3391 We don't want those calls to affect any assumptions about the real
3392 function; and further, we can't call entry_of_function() until we
3393 start the real expansion process. */
3394 if (!current_function_uses_pic_offset_table)
3395 {
e1ba4a27 3396 gcc_assert (can_create_pseudo_p ());
bac7fc85 3397 if (arm_pic_register != INVALID_REGNUM)
3398 {
3399 cfun->machine->pic_reg = gen_rtx_REG (Pmode, arm_pic_register);
3400
3401 /* Play games to avoid marking the function as needing pic
3402 if we are being called as part of the cost-estimation
3403 process. */
3404 if (current_ir_type () != IR_GIMPLE)
3405 current_function_uses_pic_offset_table = 1;
3406 }
3407 else
3408 {
3409 rtx seq;
3410
3411 cfun->machine->pic_reg = gen_reg_rtx (Pmode);
3412
3413 /* Play games to avoid marking the function as needing pic
3414 if we are being called as part of the cost-estimation
3415 process. */
3416 if (current_ir_type () != IR_GIMPLE)
3417 {
3418 current_function_uses_pic_offset_table = 1;
3419 start_sequence ();
3420
3421 arm_load_pic_register (0UL);
3422
3423 seq = get_insns ();
3424 end_sequence ();
3425 emit_insn_after (seq, entry_of_function ());
3426 }
3427 }
3428 }
3429}
3430
69120d26 3431rtx
ebd88a36 3432legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg)
69120d26 3433{
1644aab7 3434 if (GET_CODE (orig) == SYMBOL_REF
3435 || GET_CODE (orig) == LABEL_REF)
69120d26 3436 {
29122112 3437#ifndef AOF_ASSEMBLER
69120d26 3438 rtx pic_ref, address;
29122112 3439#endif
69120d26 3440 rtx insn;
3441 int subregs = 0;
3442
bac7fc85 3443 /* If this function doesn't have a pic register, create one now. */
3444 require_pic_register ();
2cb7d577 3445
69120d26 3446 if (reg == 0)
3447 {
e1ba4a27 3448 gcc_assert (can_create_pseudo_p ());
ed29c566 3449 reg = gen_reg_rtx (Pmode);
69120d26 3450
3451 subregs = 1;
3452 }
3453
3454#ifdef AOF_ASSEMBLER
3455 /* The AOF assembler can generate relocations for these directly, and
66aacf41 3456 understands that the PIC register has to be added into the offset. */
69120d26 3457 insn = emit_insn (gen_pic_load_addr_based (reg, orig));
3458#else
3459 if (subregs)
3460 address = gen_reg_rtx (Pmode);
3461 else
3462 address = reg;
3463
8c4d8060 3464 if (TARGET_ARM)
3465 emit_insn (gen_pic_load_addr_arm (address, orig));
25f905c2 3466 else if (TARGET_THUMB2)
3467 emit_insn (gen_pic_load_addr_thumb2 (address, orig));
3468 else /* TARGET_THUMB1 */
3469 emit_insn (gen_pic_load_addr_thumb1 (address, orig));
69120d26 3470
bac7fc85 3471 /* VxWorks does not impose a fixed gap between segments; the run-time
3472 gap can be different from the object-file gap. We therefore can't
3473 use GOTOFF unless we are absolutely sure that the symbol is in the
3474 same segment as the GOT. Unfortunately, the flexibility of linker
3475 scripts means that we can't be sure of that in general, so assume
3476 that GOTOFF is never valid on VxWorks. */
77744024 3477 if ((GET_CODE (orig) == LABEL_REF
9e7454d0 3478 || (GET_CODE (orig) == SYMBOL_REF &&
e052c34d 3479 SYMBOL_REF_LOCAL_P (orig)))
bac7fc85 3480 && NEED_GOT_RELOC
3481 && !TARGET_VXWORKS_RTP)
2cb7d577 3482 pic_ref = gen_rtx_PLUS (Pmode, cfun->machine->pic_reg, address);
1644aab7 3483 else
3484 {
e265a6da 3485 pic_ref = gen_const_mem (Pmode,
2cb7d577 3486 gen_rtx_PLUS (Pmode, cfun->machine->pic_reg,
e265a6da 3487 address));
1644aab7 3488 }
3489
69120d26 3490 insn = emit_move_insn (reg, pic_ref);
3491#endif
69120d26 3492 /* Put a REG_EQUAL note on this insn, so that it can be optimized
3493 by loop. */
24153880 3494 set_unique_reg_note (insn, REG_EQUAL, orig);
3495
69120d26 3496 return reg;
3497 }
3498 else if (GET_CODE (orig) == CONST)
3499 {
3500 rtx base, offset;
3501
3502 if (GET_CODE (XEXP (orig, 0)) == PLUS
2cb7d577 3503 && XEXP (XEXP (orig, 0), 0) == cfun->machine->pic_reg)
69120d26 3504 return orig;
3505
f655717d 3506 if (GET_CODE (XEXP (orig, 0)) == UNSPEC
3507 && XINT (XEXP (orig, 0), 1) == UNSPEC_TLS)
3508 return orig;
3509
69120d26 3510 if (reg == 0)
3511 {
e1ba4a27 3512 gcc_assert (can_create_pseudo_p ());
ed29c566 3513 reg = gen_reg_rtx (Pmode);
69120d26 3514 }
3515
ed29c566 3516 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
a60f1840 3517
ed29c566 3518 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
3519 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
3520 base == reg ? 0 : reg);
69120d26 3521
3522 if (GET_CODE (offset) == CONST_INT)
3523 {
3524 /* The base register doesn't really matter, we only want to
3525 test the index for the appropriate mode. */
b4e8a300 3526 if (!arm_legitimate_index_p (mode, offset, SET, 0))
d32b3557 3527 {
e1ba4a27 3528 gcc_assert (can_create_pseudo_p ());
ed29c566 3529 offset = force_reg (Pmode, offset);
d32b3557 3530 }
69120d26 3531
69120d26 3532 if (GET_CODE (offset) == CONST_INT)
b244d4c7 3533 return plus_constant (base, INTVAL (offset));
69120d26 3534 }
3535
3536 if (GET_MODE_SIZE (mode) > 4
3537 && (GET_MODE_CLASS (mode) == MODE_INT
3538 || TARGET_SOFT_FLOAT))
3539 {
3540 emit_insn (gen_addsi3 (reg, base, offset));
3541 return reg;
3542 }
3543
76676c8e 3544 return gen_rtx_PLUS (Pmode, base, offset);
69120d26 3545 }
69120d26 3546
3547 return orig;
3548}
3549
237533cc 3550
25f905c2 3551/* Find a spare register to use during the prolog of a function. */
237533cc 3552
3553static int
53f179c0 3554thumb_find_work_register (unsigned long pushed_regs_mask)
237533cc 3555{
3556 int reg;
3557
53f179c0 3558 /* Check the argument registers first as these are call-used. The
3559 register allocation order means that sometimes r3 might be used
3560 but earlier argument registers might not, so check them all. */
3561 for (reg = LAST_ARG_REGNUM; reg >= 0; reg --)
3072d30e 3562 if (!df_regs_ever_live_p (reg))
53f179c0 3563 return reg;
3564
3565 /* Before going on to check the call-saved registers we can try a couple
3566 more ways of deducing that r3 is available. The first is when we are
3567 pushing anonymous arguments onto the stack and we have less than 4
3568 registers worth of fixed arguments(*). In this case r3 will be part of
3569 the variable argument list and so we can be sure that it will be
3570 pushed right at the start of the function. Hence it will be available
3571 for the rest of the prologue.
3572 (*): ie current_function_pretend_args_size is greater than 0. */
3573 if (cfun->machine->uses_anonymous_args
3574 && current_function_pretend_args_size > 0)
237533cc 3575 return LAST_ARG_REGNUM;
3576
53f179c0 3577 /* The other case is when we have fixed arguments but less than 4 registers
3578 worth. In this case r3 might be used in the body of the function, but
3579 it is not being used to convey an argument into the function. In theory
3580 we could just check current_function_args_size to see how many bytes are
3581 being passed in argument registers, but it seems that it is unreliable.
3582 Sometimes it will have the value 0 when in fact arguments are being
3583 passed. (See testcase execute/20021111-1.c for an example). So we also
3584 check the args_info.nregs field as well. The problem with this field is
3585 that it makes no allowances for arguments that are passed to the
3586 function but which are not used. Hence we could miss an opportunity
3587 when a function has an unused argument in r3. But it is better to be
3588 safe than to be sorry. */
3589 if (! cfun->machine->uses_anonymous_args
3590 && current_function_args_size >= 0
3591 && current_function_args_size <= (LAST_ARG_REGNUM * UNITS_PER_WORD)
3592 && cfun->args_info.nregs < 4)
3593 return LAST_ARG_REGNUM;
a60f1840 3594
53f179c0 3595 /* Otherwise look for a call-saved register that is going to be pushed. */
3596 for (reg = LAST_LO_REGNUM; reg > LAST_ARG_REGNUM; reg --)
3597 if (pushed_regs_mask & (1 << reg))
237533cc 3598 return reg;
3599
25f905c2 3600 if (TARGET_THUMB2)
3601 {
3602 /* Thumb-2 can use high regs. */
3603 for (reg = FIRST_HI_REGNUM; reg < 15; reg ++)
3604 if (pushed_regs_mask & (1 << reg))
3605 return reg;
3606 }
53f179c0 3607 /* Something went wrong - thumb_compute_save_reg_mask()
3608 should have arranged for a suitable register to be pushed. */
ed29c566 3609 gcc_unreachable ();
237533cc 3610}
3611
6cdcb15c 3612static GTY(()) int pic_labelno;
ea32a06e 3613
b935b306 3614/* Generate code to load the PIC register. In thumb mode SCRATCH is a
3615 low register. */
ea32a06e 3616
69120d26 3617void
aa6af490 3618arm_load_pic_register (unsigned long saved_regs ATTRIBUTE_UNUSED)
69120d26 3619{
3620#ifndef AOF_ASSEMBLER
bac7fc85 3621 rtx l1, labelno, pic_tmp, pic_tmp2, pic_rtx, pic_reg;
69120d26 3622 rtx global_offset_table;
3623
55c1e470 3624 if (current_function_uses_pic_offset_table == 0 || TARGET_SINGLE_PIC_BASE)
69120d26 3625 return;
3626
ed29c566 3627 gcc_assert (flag_pic);
69120d26 3628
bac7fc85 3629 pic_reg = cfun->machine->pic_reg;
3630 if (TARGET_VXWORKS_RTP)
3631 {
3632 pic_rtx = gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_BASE);
3633 pic_rtx = gen_rtx_CONST (Pmode, pic_rtx);
3634 emit_insn (gen_pic_load_addr_arm (pic_reg, pic_rtx));
76676c8e 3635
bac7fc85 3636 emit_insn (gen_rtx_SET (Pmode, pic_reg, gen_rtx_MEM (Pmode, pic_reg)));
9e7454d0 3637
bac7fc85 3638 pic_tmp = gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_INDEX);
3639 emit_insn (gen_pic_offset_arm (pic_reg, pic_reg, pic_tmp));
8c4d8060 3640 }
bac7fc85 3641 else
25f905c2 3642 {
bac7fc85 3643 /* We use an UNSPEC rather than a LABEL_REF because this label
3644 never appears in the code stream. */
3645
3646 labelno = GEN_INT (pic_labelno++);
3647 l1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, labelno), UNSPEC_PIC_LABEL);
3648 l1 = gen_rtx_CONST (VOIDmode, l1);
3649
3650 global_offset_table
3651 = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3652 /* On the ARM the PC register contains 'dot + 8' at the time of the
3653 addition, on the Thumb it is 'dot + 4'. */
3654 pic_tmp = plus_constant (l1, TARGET_ARM ? 8 : 4);
3655 if (GOT_PCREL)
25f905c2 3656 {
bac7fc85 3657 pic_tmp2 = gen_rtx_PLUS (Pmode, global_offset_table, pc_rtx);
3658 pic_tmp2 = gen_rtx_CONST (VOIDmode, pic_tmp2);
25f905c2 3659 }
3660 else
bac7fc85 3661 pic_tmp2 = gen_rtx_CONST (VOIDmode, global_offset_table);
3662
3663 pic_rtx = gen_rtx_MINUS (Pmode, pic_tmp2, pic_tmp);
3664 pic_rtx = gen_rtx_CONST (Pmode, pic_rtx);
3665
3666 if (TARGET_ARM)
25f905c2 3667 {
bac7fc85 3668 emit_insn (gen_pic_load_addr_arm (pic_reg, pic_rtx));
3669 emit_insn (gen_pic_add_dot_plus_eight (pic_reg, pic_reg, labelno));
25f905c2 3670 }
bac7fc85 3671 else if (TARGET_THUMB2)
3672 {
3673 /* Thumb-2 only allows very limited access to the PC. Calculate the
3674 address in a temporary register. */
3675 if (arm_pic_register != INVALID_REGNUM)
3676 {
3677 pic_tmp = gen_rtx_REG (SImode,
3678 thumb_find_work_register (saved_regs));
3679 }
3680 else
3681 {
e1ba4a27 3682 gcc_assert (can_create_pseudo_p ());
bac7fc85 3683 pic_tmp = gen_reg_rtx (Pmode);
3684 }
25f905c2 3685
bac7fc85 3686 emit_insn (gen_pic_load_addr_thumb2 (pic_reg, pic_rtx));
3687 emit_insn (gen_pic_load_dot_plus_four (pic_tmp, labelno));
3688 emit_insn (gen_addsi3 (pic_reg, pic_reg, pic_tmp));
3689 }
3690 else /* TARGET_THUMB1 */
ea32a06e 3691 {
bac7fc85 3692 if (arm_pic_register != INVALID_REGNUM
3693 && REGNO (pic_reg) > LAST_LO_REGNUM)
3694 {
3695 /* We will have pushed the pic register, so we should always be
3696 able to find a work register. */
3697 pic_tmp = gen_rtx_REG (SImode,
3698 thumb_find_work_register (saved_regs));
3699 emit_insn (gen_pic_load_addr_thumb1 (pic_tmp, pic_rtx));
3700 emit_insn (gen_movsi (pic_offset_table_rtx, pic_tmp));
3701 }
3702 else
3703 emit_insn (gen_pic_load_addr_thumb1 (pic_reg, pic_rtx));
3704 emit_insn (gen_pic_add_dot_plus_four (pic_reg, pic_reg, labelno));
ea32a06e 3705 }
8c4d8060 3706 }
69120d26 3707
69120d26 3708 /* Need to emit this whether or not we obey regdecls,
3709 since setjmp/longjmp can cause life info to screw up. */
bac7fc85 3710 emit_insn (gen_rtx_USE (VOIDmode, pic_reg));
69120d26 3711#endif /* AOF_ASSEMBLER */
3712}
3713
ea32a06e 3714
d32b3557 3715/* Return nonzero if X is valid as an ARM state addressing register. */
3716static int
ebd88a36 3717arm_address_register_rtx_p (rtx x, int strict_p)
d32b3557 3718{
3719 int regno;
3720
3721 if (GET_CODE (x) != REG)
3722 return 0;
3723
3724 regno = REGNO (x);
3725
3726 if (strict_p)
3727 return ARM_REGNO_OK_FOR_BASE_P (regno);
3728
3729 return (regno <= LAST_ARM_REGNUM
3730 || regno >= FIRST_PSEUDO_REGISTER
3731 || regno == FRAME_POINTER_REGNUM
3732 || regno == ARG_POINTER_REGNUM);
3733}
3734
f655717d 3735/* Return TRUE if this rtx is the difference of a symbol and a label,
3736 and will reduce to a PC-relative relocation in the object file.
3737 Expressions like this can be left alone when generating PIC, rather
3738 than forced through the GOT. */
3739static int
3740pcrel_constant_p (rtx x)
3741{
3742 if (GET_CODE (x) == MINUS)
3743 return symbol_mentioned_p (XEXP (x, 0)) && label_mentioned_p (XEXP (x, 1));
3744
3745 return FALSE;
3746}
3747
d32b3557 3748/* Return nonzero if X is a valid ARM state address operand. */
3749int
b4e8a300 3750arm_legitimate_address_p (enum machine_mode mode, rtx x, RTX_CODE outer,
3751 int strict_p)
d32b3557 3752{
a8a3b539 3753 bool use_ldrd;
3754 enum rtx_code code = GET_CODE (x);
9e7454d0 3755
d32b3557 3756 if (arm_address_register_rtx_p (x, strict_p))
3757 return 1;
3758
a8a3b539 3759 use_ldrd = (TARGET_LDRD
3760 && (mode == DImode
3761 || (mode == DFmode && (TARGET_SOFT_FLOAT || TARGET_VFP))));
3762
3763 if (code == POST_INC || code == PRE_DEC
3764 || ((code == PRE_INC || code == POST_DEC)
3765 && (use_ldrd || GET_MODE_SIZE (mode) <= 4)))
d32b3557 3766 return arm_address_register_rtx_p (XEXP (x, 0), strict_p);
3767
a8a3b539 3768 else if ((code == POST_MODIFY || code == PRE_MODIFY)
d32b3557 3769 && arm_address_register_rtx_p (XEXP (x, 0), strict_p)
3770 && GET_CODE (XEXP (x, 1)) == PLUS
0bb91b60 3771 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
a8a3b539 3772 {
3773 rtx addend = XEXP (XEXP (x, 1), 1);
3774
a361b456 3775 /* Don't allow ldrd post increment by register because it's hard
a8a3b539 3776 to fixup invalid register choices. */
3777 if (use_ldrd
3778 && GET_CODE (x) == POST_MODIFY
3779 && GET_CODE (addend) == REG)
3780 return 0;
3781
3782 return ((use_ldrd || GET_MODE_SIZE (mode) <= 4)
3783 && arm_legitimate_index_p (mode, addend, outer, strict_p));
3784 }
d32b3557 3785
3786 /* After reload constants split into minipools will have addresses
3787 from a LABEL_REF. */
e027ee9c 3788 else if (reload_completed
a8a3b539 3789 && (code == LABEL_REF
3790 || (code == CONST
d32b3557 3791 && GET_CODE (XEXP (x, 0)) == PLUS
3792 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF
3793 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)))
3794 return 1;
3795
d98a3884 3796 else if (mode == TImode || (TARGET_NEON && VALID_NEON_STRUCT_MODE (mode)))
d32b3557 3797 return 0;
3798
a8a3b539 3799 else if (code == PLUS)
d32b3557 3800 {
3801 rtx xop0 = XEXP (x, 0);
3802 rtx xop1 = XEXP (x, 1);
3803
3804 return ((arm_address_register_rtx_p (xop0, strict_p)
b4e8a300 3805 && arm_legitimate_index_p (mode, xop1, outer, strict_p))
d32b3557 3806 || (arm_address_register_rtx_p (xop1, strict_p)
b4e8a300 3807 && arm_legitimate_index_p (mode, xop0, outer, strict_p)));
d32b3557 3808 }
3809
3810#if 0
3811 /* Reload currently can't handle MINUS, so disable this for now */
3812 else if (GET_CODE (x) == MINUS)
3813 {
3814 rtx xop0 = XEXP (x, 0);
3815 rtx xop1 = XEXP (x, 1);
3816
3817 return (arm_address_register_rtx_p (xop0, strict_p)
b4e8a300 3818 && arm_legitimate_index_p (mode, xop1, outer, strict_p));
d32b3557 3819 }
3820#endif
3821
3822 else if (GET_MODE_CLASS (mode) != MODE_FLOAT
a8a3b539 3823 && code == SYMBOL_REF
d32b3557 3824 && CONSTANT_POOL_ADDRESS_P (x)
3825 && ! (flag_pic
f655717d 3826 && symbol_mentioned_p (get_pool_constant (x))
3827 && ! pcrel_constant_p (get_pool_constant (x))))
d32b3557 3828 return 1;
3829
d32b3557 3830 return 0;
3831}
3832
25f905c2 3833/* Return nonzero if X is a valid Thumb-2 address operand. */
3834int
3835thumb2_legitimate_address_p (enum machine_mode mode, rtx x, int strict_p)
3836{
3837 bool use_ldrd;
3838 enum rtx_code code = GET_CODE (x);
3839
3840 if (arm_address_register_rtx_p (x, strict_p))
3841 return 1;
3842
3843 use_ldrd = (TARGET_LDRD
3844 && (mode == DImode
3845 || (mode == DFmode && (TARGET_SOFT_FLOAT || TARGET_VFP))));
3846
3847 if (code == POST_INC || code == PRE_DEC
3848 || ((code == PRE_INC || code == POST_DEC)
3849 && (use_ldrd || GET_MODE_SIZE (mode) <= 4)))
3850 return arm_address_register_rtx_p (XEXP (x, 0), strict_p);
3851
3852 else if ((code == POST_MODIFY || code == PRE_MODIFY)
3853 && arm_address_register_rtx_p (XEXP (x, 0), strict_p)
3854 && GET_CODE (XEXP (x, 1)) == PLUS
3855 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
3856 {
3857 /* Thumb-2 only has autoincrement by constant. */
3858 rtx addend = XEXP (XEXP (x, 1), 1);
3859 HOST_WIDE_INT offset;
3860
3861 if (GET_CODE (addend) != CONST_INT)
3862 return 0;
3863
3864 offset = INTVAL(addend);
3865 if (GET_MODE_SIZE (mode) <= 4)
3866 return (offset > -256 && offset < 256);
3867
3868 return (use_ldrd && offset > -1024 && offset < 1024
3869 && (offset & 3) == 0);
3870 }
3871
3872 /* After reload constants split into minipools will have addresses
3873 from a LABEL_REF. */
3874 else if (reload_completed
3875 && (code == LABEL_REF
3876 || (code == CONST
3877 && GET_CODE (XEXP (x, 0)) == PLUS
3878 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF
3879 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)))
3880 return 1;
3881
d98a3884 3882 else if (mode == TImode || (TARGET_NEON && VALID_NEON_STRUCT_MODE (mode)))
25f905c2 3883 return 0;
3884
3885 else if (code == PLUS)
3886 {
3887 rtx xop0 = XEXP (x, 0);
3888 rtx xop1 = XEXP (x, 1);
3889
3890 return ((arm_address_register_rtx_p (xop0, strict_p)
3891 && thumb2_legitimate_index_p (mode, xop1, strict_p))
3892 || (arm_address_register_rtx_p (xop1, strict_p)
3893 && thumb2_legitimate_index_p (mode, xop0, strict_p)));
3894 }
3895
3896 else if (GET_MODE_CLASS (mode) != MODE_FLOAT
3897 && code == SYMBOL_REF
3898 && CONSTANT_POOL_ADDRESS_P (x)
3899 && ! (flag_pic
3900 && symbol_mentioned_p (get_pool_constant (x))
3901 && ! pcrel_constant_p (get_pool_constant (x))))
3902 return 1;
3903
3904 return 0;
3905}
3906
d32b3557 3907/* Return nonzero if INDEX is valid for an address index operand in
3908 ARM state. */
3909static int
b4e8a300 3910arm_legitimate_index_p (enum machine_mode mode, rtx index, RTX_CODE outer,
3911 int strict_p)
d32b3557 3912{
3913 HOST_WIDE_INT range;
3914 enum rtx_code code = GET_CODE (index);
3915
69130f53 3916 /* Standard coprocessor addressing modes. */
3917 if (TARGET_HARD_FLOAT
3918 && (TARGET_FPA || TARGET_MAVERICK)
3919 && (GET_MODE_CLASS (mode) == MODE_FLOAT
3920 || (TARGET_MAVERICK && mode == DImode)))
d32b3557 3921 return (code == CONST_INT && INTVAL (index) < 1024
3922 && INTVAL (index) > -1024
3923 && (INTVAL (index) & 3) == 0);
3924
d98a3884 3925 if (TARGET_NEON
3926 && (VALID_NEON_DREG_MODE (mode) || VALID_NEON_QREG_MODE (mode)))
3927 return (code == CONST_INT
3928 && INTVAL (index) < 1016
3929 && INTVAL (index) > -1024
3930 && (INTVAL (index) & 3) == 0);
3931
755eb2b4 3932 if (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode))
3933 return (code == CONST_INT
7d647a20 3934 && INTVAL (index) < 1024
3935 && INTVAL (index) > -1024
3936 && (INTVAL (index) & 3) == 0);
755eb2b4 3937
a8a3b539 3938 if (arm_address_register_rtx_p (index, strict_p)
3939 && (GET_MODE_SIZE (mode) <= 4))
3940 return 1;
3941
3942 if (mode == DImode || mode == DFmode)
3943 {
3944 if (code == CONST_INT)
3945 {
3946 HOST_WIDE_INT val = INTVAL (index);
3947
3948 if (TARGET_LDRD)
3949 return val > -256 && val < 256;
3950 else
da873b17 3951 return val > -4096 && val < 4092;
a8a3b539 3952 }
3953
3954 return TARGET_LDRD && arm_address_register_rtx_p (index, strict_p);
3955 }
3956
d32b3557 3957 if (GET_MODE_SIZE (mode) <= 4
b4e8a300 3958 && ! (arm_arch4
3959 && (mode == HImode
3960 || (mode == QImode && outer == SIGN_EXTEND))))
d32b3557 3961 {
b4e8a300 3962 if (code == MULT)
3963 {
3964 rtx xiop0 = XEXP (index, 0);
3965 rtx xiop1 = XEXP (index, 1);
3966
3967 return ((arm_address_register_rtx_p (xiop0, strict_p)
3968 && power_of_two_operand (xiop1, SImode))
3969 || (arm_address_register_rtx_p (xiop1, strict_p)
3970 && power_of_two_operand (xiop0, SImode)));
3971 }
3972 else if (code == LSHIFTRT || code == ASHIFTRT
3973 || code == ASHIFT || code == ROTATERT)
3974 {
3975 rtx op = XEXP (index, 1);
d32b3557 3976
b4e8a300 3977 return (arm_address_register_rtx_p (XEXP (index, 0), strict_p)
3978 && GET_CODE (op) == CONST_INT
3979 && INTVAL (op) > 0
3980 && INTVAL (op) <= 31);
3981 }
d32b3557 3982 }
3983
b4e8a300 3984 /* For ARM v4 we may be doing a sign-extend operation during the
3985 load. */
806c15d6 3986 if (arm_arch4)
b4e8a300 3987 {
3988 if (mode == HImode || (outer == SIGN_EXTEND && mode == QImode))
3989 range = 256;
3990 else
3991 range = 4096;
3992 }
806c15d6 3993 else
3994 range = (mode == HImode) ? 4095 : 4096;
d32b3557 3995
3996 return (code == CONST_INT
3997 && INTVAL (index) < range
3998 && INTVAL (index) > -range);
f2989adc 3999}
4000
25f905c2 4001/* Return true if OP is a valid index scaling factor for Thumb-2 address
4002 index operand. i.e. 1, 2, 4 or 8. */
4003static bool
4004thumb2_index_mul_operand (rtx op)
4005{
4006 HOST_WIDE_INT val;
4007
4008 if (GET_CODE(op) != CONST_INT)
4009 return false;
4010
4011 val = INTVAL(op);
4012 return (val == 1 || val == 2 || val == 4 || val == 8);
4013}
4014
4015/* Return nonzero if INDEX is a valid Thumb-2 address index operand. */
4016static int
4017thumb2_legitimate_index_p (enum machine_mode mode, rtx index, int strict_p)
4018{
4019 enum rtx_code code = GET_CODE (index);
4020
4021 /* ??? Combine arm and thumb2 coprocessor addressing modes. */
4022 /* Standard coprocessor addressing modes. */
4023 if (TARGET_HARD_FLOAT
4024 && (TARGET_FPA || TARGET_MAVERICK)
4025 && (GET_MODE_CLASS (mode) == MODE_FLOAT
4026 || (TARGET_MAVERICK && mode == DImode)))
4027 return (code == CONST_INT && INTVAL (index) < 1024
4028 && INTVAL (index) > -1024
4029 && (INTVAL (index) & 3) == 0);
4030
4031 if (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode))
f1225f6f 4032 {
4033 /* For DImode assume values will usually live in core regs
4034 and only allow LDRD addressing modes. */
4035 if (!TARGET_LDRD || mode != DImode)
4036 return (code == CONST_INT
4037 && INTVAL (index) < 1024
4038 && INTVAL (index) > -1024
4039 && (INTVAL (index) & 3) == 0);
4040 }
25f905c2 4041
d98a3884 4042 if (TARGET_NEON
4043 && (VALID_NEON_DREG_MODE (mode) || VALID_NEON_QREG_MODE (mode)))
4044 return (code == CONST_INT
4045 && INTVAL (index) < 1016
4046 && INTVAL (index) > -1024
4047 && (INTVAL (index) & 3) == 0);
4048
25f905c2 4049 if (arm_address_register_rtx_p (index, strict_p)
4050 && (GET_MODE_SIZE (mode) <= 4))
4051 return 1;
4052
4053 if (mode == DImode || mode == DFmode)
4054 {
4055 HOST_WIDE_INT val = INTVAL (index);
4056 /* ??? Can we assume ldrd for thumb2? */
4057 /* Thumb-2 ldrd only has reg+const addressing modes. */
4058 if (code != CONST_INT)
4059 return 0;
4060
4061 /* ldrd supports offsets of +-1020.
4062 However the ldr fallback does not. */
4063 return val > -256 && val < 256 && (val & 3) == 0;
4064 }
4065
4066 if (code == MULT)
4067 {
4068 rtx xiop0 = XEXP (index, 0);
4069 rtx xiop1 = XEXP (index, 1);
4070
4071 return ((arm_address_register_rtx_p (xiop0, strict_p)
4072 && thumb2_index_mul_operand (xiop1))
4073 || (arm_address_register_rtx_p (xiop1, strict_p)
4074 && thumb2_index_mul_operand (xiop0)));
4075 }
4076 else if (code == ASHIFT)
4077 {
4078 rtx op = XEXP (index, 1);
4079
4080 return (arm_address_register_rtx_p (XEXP (index, 0), strict_p)
4081 && GET_CODE (op) == CONST_INT
4082 && INTVAL (op) > 0
4083 && INTVAL (op) <= 3);
4084 }
4085
4086 return (code == CONST_INT
4087 && INTVAL (index) < 4096
4088 && INTVAL (index) > -256);
4089}
4090
4091/* Return nonzero if X is valid as a 16-bit Thumb state base register. */
f2989adc 4092static int
25f905c2 4093thumb1_base_register_rtx_p (rtx x, enum machine_mode mode, int strict_p)
f2989adc 4094{
4095 int regno;
4096
4097 if (GET_CODE (x) != REG)
4098 return 0;
4099
4100 regno = REGNO (x);
4101
4102 if (strict_p)
25f905c2 4103 return THUMB1_REGNO_MODE_OK_FOR_BASE_P (regno, mode);
f2989adc 4104
4105 return (regno <= LAST_LO_REGNUM
221038d3 4106 || regno > LAST_VIRTUAL_REGISTER
f2989adc 4107 || regno == FRAME_POINTER_REGNUM
4108 || (GET_MODE_SIZE (mode) >= 4
4109 && (regno == STACK_POINTER_REGNUM
11e7c7fd 4110 || regno >= FIRST_PSEUDO_REGISTER
f2989adc 4111 || x == hard_frame_pointer_rtx
4112 || x == arg_pointer_rtx)));
4113}
4114
4115/* Return nonzero if x is a legitimate index register. This is the case
4116 for any base register that can access a QImode object. */
4117inline static int
25f905c2 4118thumb1_index_register_rtx_p (rtx x, int strict_p)
f2989adc 4119{
25f905c2 4120 return thumb1_base_register_rtx_p (x, QImode, strict_p);
f2989adc 4121}
4122
25f905c2 4123/* Return nonzero if x is a legitimate 16-bit Thumb-state address.
9e7454d0 4124
f2989adc 4125 The AP may be eliminated to either the SP or the FP, so we use the
4126 least common denominator, e.g. SImode, and offsets from 0 to 64.
4127
4128 ??? Verify whether the above is the right approach.
4129
4130 ??? Also, the FP may be eliminated to the SP, so perhaps that
4131 needs special handling also.
4132
4133 ??? Look at how the mips16 port solves this problem. It probably uses
4134 better ways to solve some of these problems.
4135
4136 Although it is not incorrect, we don't accept QImode and HImode
4137 addresses based on the frame pointer or arg pointer until the
4138 reload pass starts. This is so that eliminating such addresses
4139 into stack based ones won't produce impossible code. */
4140int
25f905c2 4141thumb1_legitimate_address_p (enum machine_mode mode, rtx x, int strict_p)
f2989adc 4142{
4143 /* ??? Not clear if this is right. Experiment. */
4144 if (GET_MODE_SIZE (mode) < 4
4145 && !(reload_in_progress || reload_completed)
4146 && (reg_mentioned_p (frame_pointer_rtx, x)
4147 || reg_mentioned_p (arg_pointer_rtx, x)
4148 || reg_mentioned_p (virtual_incoming_args_rtx, x)
4149 || reg_mentioned_p (virtual_outgoing_args_rtx, x)
4150 || reg_mentioned_p (virtual_stack_dynamic_rtx, x)
4151 || reg_mentioned_p (virtual_stack_vars_rtx, x)))
4152 return 0;
4153
4154 /* Accept any base register. SP only in SImode or larger. */
25f905c2 4155 else if (thumb1_base_register_rtx_p (x, mode, strict_p))
f2989adc 4156 return 1;
4157
2efea8c0 4158 /* This is PC relative data before arm_reorg runs. */
f2989adc 4159 else if (GET_MODE_SIZE (mode) >= 4 && CONSTANT_P (x)
4160 && GET_CODE (x) == SYMBOL_REF
2cb7d577 4161 && CONSTANT_POOL_ADDRESS_P (x) && !flag_pic)
f2989adc 4162 return 1;
4163
2efea8c0 4164 /* This is PC relative data after arm_reorg runs. */
f2989adc 4165 else if (GET_MODE_SIZE (mode) >= 4 && reload_completed
4166 && (GET_CODE (x) == LABEL_REF
4167 || (GET_CODE (x) == CONST
4168 && GET_CODE (XEXP (x, 0)) == PLUS
4169 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF
4170 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)))
4171 return 1;
4172
4173 /* Post-inc indexing only supported for SImode and larger. */
4174 else if (GET_CODE (x) == POST_INC && GET_MODE_SIZE (mode) >= 4
25f905c2 4175 && thumb1_index_register_rtx_p (XEXP (x, 0), strict_p))
f2989adc 4176 return 1;
4177
4178 else if (GET_CODE (x) == PLUS)
4179 {
4180 /* REG+REG address can be any two index registers. */
4181 /* We disallow FRAME+REG addressing since we know that FRAME
4182 will be replaced with STACK, and SP relative addressing only
4183 permits SP+OFFSET. */
4184 if (GET_MODE_SIZE (mode) <= 4
4185 && XEXP (x, 0) != frame_pointer_rtx
4186 && XEXP (x, 1) != frame_pointer_rtx
25f905c2 4187 && thumb1_index_register_rtx_p (XEXP (x, 0), strict_p)
4188 && thumb1_index_register_rtx_p (XEXP (x, 1), strict_p))
f2989adc 4189 return 1;
4190
4191 /* REG+const has 5-7 bit offset for non-SP registers. */
25f905c2 4192 else if ((thumb1_index_register_rtx_p (XEXP (x, 0), strict_p)
f2989adc 4193 || XEXP (x, 0) == arg_pointer_rtx)
4194 && GET_CODE (XEXP (x, 1)) == CONST_INT
4195 && thumb_legitimate_offset_p (mode, INTVAL (XEXP (x, 1))))
4196 return 1;
4197
85c36fd1 4198 /* REG+const has 10-bit offset for SP, but only SImode and
f2989adc 4199 larger is supported. */
4200 /* ??? Should probably check for DI/DFmode overflow here
4201 just like GO_IF_LEGITIMATE_OFFSET does. */
4202 else if (GET_CODE (XEXP (x, 0)) == REG
4203 && REGNO (XEXP (x, 0)) == STACK_POINTER_REGNUM
4204 && GET_MODE_SIZE (mode) >= 4
4205 && GET_CODE (XEXP (x, 1)) == CONST_INT
4206 && INTVAL (XEXP (x, 1)) >= 0
4207 && INTVAL (XEXP (x, 1)) + GET_MODE_SIZE (mode) <= 1024
4208 && (INTVAL (XEXP (x, 1)) & 3) == 0)
4209 return 1;
4210
4211 else if (GET_CODE (XEXP (x, 0)) == REG
2e9ff3c0 4212 && (REGNO (XEXP (x, 0)) == FRAME_POINTER_REGNUM
4213 || REGNO (XEXP (x, 0)) == ARG_POINTER_REGNUM
4214 || (REGNO (XEXP (x, 0)) >= FIRST_VIRTUAL_REGISTER
4215 && REGNO (XEXP (x, 0)) <= LAST_VIRTUAL_REGISTER))
f2989adc 4216 && GET_MODE_SIZE (mode) >= 4
4217 && GET_CODE (XEXP (x, 1)) == CONST_INT
4218 && (INTVAL (XEXP (x, 1)) & 3) == 0)
4219 return 1;
4220 }
4221
4222 else if (GET_MODE_CLASS (mode) != MODE_FLOAT
a941568e 4223 && GET_MODE_SIZE (mode) == 4
f2989adc 4224 && GET_CODE (x) == SYMBOL_REF
4225 && CONSTANT_POOL_ADDRESS_P (x)
f655717d 4226 && ! (flag_pic
4227 && symbol_mentioned_p (get_pool_constant (x))
4228 && ! pcrel_constant_p (get_pool_constant (x))))
f2989adc 4229 return 1;
4230
4231 return 0;
4232}
4233
4234/* Return nonzero if VAL can be used as an offset in a Thumb-state address
4235 instruction of mode MODE. */
4236int
ebd88a36 4237thumb_legitimate_offset_p (enum machine_mode mode, HOST_WIDE_INT val)
f2989adc 4238{
4239 switch (GET_MODE_SIZE (mode))
4240 {
4241 case 1:
4242 return val >= 0 && val < 32;
4243
4244 case 2:
4245 return val >= 0 && val < 64 && (val & 1) == 0;
4246
4247 default:
4248 return (val >= 0
4249 && (val + GET_MODE_SIZE (mode)) <= 128
4250 && (val & 3) == 0);
4251 }
4252}
4253
f655717d 4254/* Build the SYMBOL_REF for __tls_get_addr. */
4255
4256static GTY(()) rtx tls_get_addr_libfunc;
4257
4258static rtx
4259get_tls_get_addr (void)
4260{
4261 if (!tls_get_addr_libfunc)
4262 tls_get_addr_libfunc = init_one_libfunc ("__tls_get_addr");
4263 return tls_get_addr_libfunc;
4264}
4265
4266static rtx
4267arm_load_tp (rtx target)
4268{
4269 if (!target)
4270 target = gen_reg_rtx (SImode);
4271
4272 if (TARGET_HARD_TP)
4273 {
4274 /* Can return in any reg. */
4275 emit_insn (gen_load_tp_hard (target));
4276 }
4277 else
4278 {
4279 /* Always returned in r0. Immediately copy the result into a pseudo,
4280 otherwise other uses of r0 (e.g. setting up function arguments) may
4281 clobber the value. */
4282
4283 rtx tmp;
4284
4285 emit_insn (gen_load_tp_soft ());
4286
4287 tmp = gen_rtx_REG (SImode, 0);
4288 emit_move_insn (target, tmp);
4289 }
4290 return target;
4291}
4292
4293static rtx
4294load_tls_operand (rtx x, rtx reg)
4295{
4296 rtx tmp;
4297
4298 if (reg == NULL_RTX)
4299 reg = gen_reg_rtx (SImode);
4300
4301 tmp = gen_rtx_CONST (SImode, x);
4302
4303 emit_move_insn (reg, tmp);
4304
4305 return reg;
4306}
4307
4308static rtx
4309arm_call_tls_get_addr (rtx x, rtx reg, rtx *valuep, int reloc)
4310{
6cdcb15c 4311 rtx insns, label, labelno, sum;
f655717d 4312
4313 start_sequence ();
4314
6cdcb15c 4315 labelno = GEN_INT (pic_labelno++);
4316 label = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, labelno), UNSPEC_PIC_LABEL);
4317 label = gen_rtx_CONST (VOIDmode, label);
4318
f655717d 4319 sum = gen_rtx_UNSPEC (Pmode,
6cdcb15c 4320 gen_rtvec (4, x, GEN_INT (reloc), label,
f655717d 4321 GEN_INT (TARGET_ARM ? 8 : 4)),
4322 UNSPEC_TLS);
4323 reg = load_tls_operand (sum, reg);
4324
4325 if (TARGET_ARM)
6cdcb15c 4326 emit_insn (gen_pic_add_dot_plus_eight (reg, reg, labelno));
25f905c2 4327 else if (TARGET_THUMB2)
4328 {
4329 rtx tmp;
4330 /* Thumb-2 only allows very limited access to the PC. Calculate
4331 the address in a temporary register. */
4332 tmp = gen_reg_rtx (SImode);
4333 emit_insn (gen_pic_load_dot_plus_four (tmp, labelno));
4334 emit_insn (gen_addsi3(reg, reg, tmp));
4335 }
4336 else /* TARGET_THUMB1 */
6cdcb15c 4337 emit_insn (gen_pic_add_dot_plus_four (reg, reg, labelno));
f655717d 4338
4339 *valuep = emit_library_call_value (get_tls_get_addr (), NULL_RTX, LCT_PURE, /* LCT_CONST? */
4340 Pmode, 1, reg, Pmode);
4341
4342 insns = get_insns ();
4343 end_sequence ();
4344
4345 return insns;
4346}
4347
4348rtx
4349legitimize_tls_address (rtx x, rtx reg)
4350{
6cdcb15c 4351 rtx dest, tp, label, labelno, sum, insns, ret, eqv, addend;
f655717d 4352 unsigned int model = SYMBOL_REF_TLS_MODEL (x);
4353
4354 switch (model)
4355 {
4356 case TLS_MODEL_GLOBAL_DYNAMIC:
4357 insns = arm_call_tls_get_addr (x, reg, &ret, TLS_GD32);
4358 dest = gen_reg_rtx (Pmode);
4359 emit_libcall_block (insns, dest, ret, x);
4360 return dest;
4361
4362 case TLS_MODEL_LOCAL_DYNAMIC:
4363 insns = arm_call_tls_get_addr (x, reg, &ret, TLS_LDM32);
4364
4365 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
4366 share the LDM result with other LD model accesses. */
4367 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const1_rtx),
4368 UNSPEC_TLS);
4369 dest = gen_reg_rtx (Pmode);
e307d75d 4370 emit_libcall_block (insns, dest, ret, eqv);
f655717d 4371
4372 /* Load the addend. */
4373 addend = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, x, GEN_INT (TLS_LDO32)),
4374 UNSPEC_TLS);
4375 addend = force_reg (SImode, gen_rtx_CONST (SImode, addend));
4376 return gen_rtx_PLUS (Pmode, dest, addend);
4377
4378 case TLS_MODEL_INITIAL_EXEC:
6cdcb15c 4379 labelno = GEN_INT (pic_labelno++);
4380 label = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, labelno), UNSPEC_PIC_LABEL);
4381 label = gen_rtx_CONST (VOIDmode, label);
f655717d 4382 sum = gen_rtx_UNSPEC (Pmode,
6cdcb15c 4383 gen_rtvec (4, x, GEN_INT (TLS_IE32), label,
f655717d 4384 GEN_INT (TARGET_ARM ? 8 : 4)),
4385 UNSPEC_TLS);
4386 reg = load_tls_operand (sum, reg);
4387
4388 if (TARGET_ARM)
6cdcb15c 4389 emit_insn (gen_tls_load_dot_plus_eight (reg, reg, labelno));
25f905c2 4390 else if (TARGET_THUMB2)
4391 {
4392 rtx tmp;
4393 /* Thumb-2 only allows very limited access to the PC. Calculate
4394 the address in a temporary register. */
4395 tmp = gen_reg_rtx (SImode);
4396 emit_insn (gen_pic_load_dot_plus_four (tmp, labelno));
4397 emit_insn (gen_addsi3(reg, reg, tmp));
4398 emit_move_insn (reg, gen_const_mem (SImode, reg));
4399 }
f655717d 4400 else
4401 {
6cdcb15c 4402 emit_insn (gen_pic_add_dot_plus_four (reg, reg, labelno));
f655717d 4403 emit_move_insn (reg, gen_const_mem (SImode, reg));
4404 }
4405
4406 tp = arm_load_tp (NULL_RTX);
4407
4408 return gen_rtx_PLUS (Pmode, tp, reg);
4409
4410 case TLS_MODEL_LOCAL_EXEC:
4411 tp = arm_load_tp (NULL_RTX);
4412
4413 reg = gen_rtx_UNSPEC (Pmode,
4414 gen_rtvec (2, x, GEN_INT (TLS_LE32)),
4415 UNSPEC_TLS);
4416 reg = force_reg (SImode, gen_rtx_CONST (SImode, reg));
4417
4418 return gen_rtx_PLUS (Pmode, tp, reg);
4419
4420 default:
4421 abort ();
4422 }
4423}
4424
1ff79d84 4425/* Try machine-dependent ways of modifying an illegitimate address
4426 to be legitimate. If we find one, return the new, valid address. */
1ff79d84 4427rtx
ebd88a36 4428arm_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode)
1ff79d84 4429{
f655717d 4430 if (arm_tls_symbol_p (x))
4431 return legitimize_tls_address (x, NULL_RTX);
4432
1ff79d84 4433 if (GET_CODE (x) == PLUS)
4434 {
4435 rtx xop0 = XEXP (x, 0);
4436 rtx xop1 = XEXP (x, 1);
4437
4438 if (CONSTANT_P (xop0) && !symbol_mentioned_p (xop0))
4439 xop0 = force_reg (SImode, xop0);
4440
4441 if (CONSTANT_P (xop1) && !symbol_mentioned_p (xop1))
4442 xop1 = force_reg (SImode, xop1);
4443
4444 if (ARM_BASE_REGISTER_RTX_P (xop0)
4445 && GET_CODE (xop1) == CONST_INT)
4446 {
4447 HOST_WIDE_INT n, low_n;
4448 rtx base_reg, val;
4449 n = INTVAL (xop1);
4450
a2cd141b 4451 /* VFP addressing modes actually allow greater offsets, but for
4452 now we just stick with the lowest common denominator. */
4453 if (mode == DImode
4454 || ((TARGET_SOFT_FLOAT || TARGET_VFP) && mode == DFmode))
1ff79d84 4455 {
4456 low_n = n & 0x0f;
4457 n &= ~0x0f;
4458 if (low_n > 4)
4459 {
4460 n += 16;
4461 low_n -= 16;
4462 }
4463 }
4464 else
4465 {
4466 low_n = ((mode) == TImode ? 0
4467 : n >= 0 ? (n & 0xfff) : -((-n) & 0xfff));
4468 n -= low_n;
4469 }
4470
4471 base_reg = gen_reg_rtx (SImode);
0083a3b9 4472 val = force_operand (plus_constant (xop0, n), NULL_RTX);
1ff79d84 4473 emit_move_insn (base_reg, val);
0083a3b9 4474 x = plus_constant (base_reg, low_n);
1ff79d84 4475 }
4476 else if (xop0 != XEXP (x, 0) || xop1 != XEXP (x, 1))
4477 x = gen_rtx_PLUS (SImode, xop0, xop1);
4478 }
4479
4480 /* XXX We don't allow MINUS any more -- see comment in
4481 arm_legitimate_address_p (). */
4482 else if (GET_CODE (x) == MINUS)
4483 {
4484 rtx xop0 = XEXP (x, 0);
4485 rtx xop1 = XEXP (x, 1);
4486
4487 if (CONSTANT_P (xop0))
4488 xop0 = force_reg (SImode, xop0);
4489
4490 if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1))
4491 xop1 = force_reg (SImode, xop1);
4492
4493 if (xop0 != XEXP (x, 0) || xop1 != XEXP (x, 1))
4494 x = gen_rtx_MINUS (SImode, xop0, xop1);
4495 }
4496
61e6ce01 4497 /* Make sure to take full advantage of the pre-indexed addressing mode
4498 with absolute addresses which often allows for the base register to
4499 be factorized for multiple adjacent memory references, and it might
4500 even allows for the mini pool to be avoided entirely. */
4501 else if (GET_CODE (x) == CONST_INT && optimize > 0)
4502 {
4503 unsigned int bits;
4504 HOST_WIDE_INT mask, base, index;
4505 rtx base_reg;
4506
85c36fd1 4507 /* ldr and ldrb can use a 12-bit index, ldrsb and the rest can only
4508 use a 8-bit index. So let's use a 12-bit index for SImode only and
61e6ce01 4509 hope that arm_gen_constant will enable ldrb to use more bits. */
4510 bits = (mode == SImode) ? 12 : 8;
4511 mask = (1 << bits) - 1;
4512 base = INTVAL (x) & ~mask;
4513 index = INTVAL (x) & mask;
4c527b3e 4514 if (bit_count (base & 0xffffffff) > (32 - bits)/2)
61e6ce01 4515 {
4516 /* It'll most probably be more efficient to generate the base
4517 with more bits set and use a negative index instead. */
4518 base |= mask;
4519 index -= mask;
4520 }
4521 base_reg = force_reg (SImode, GEN_INT (base));
0083a3b9 4522 x = plus_constant (base_reg, index);
61e6ce01 4523 }
4524
1ff79d84 4525 if (flag_pic)
4526 {
4527 /* We need to find and carefully transform any SYMBOL and LABEL
4528 references; so go back to the original address expression. */
4529 rtx new_x = legitimize_pic_address (orig_x, mode, NULL_RTX);
4530
4531 if (new_x != orig_x)
4532 x = new_x;
4533 }
4534
4535 return x;
4536}
4537
bca653c5 4538
4539/* Try machine-dependent ways of modifying an illegitimate Thumb address
4540 to be legitimate. If we find one, return the new, valid address. */
4541rtx
4542thumb_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode)
4543{
f655717d 4544 if (arm_tls_symbol_p (x))
4545 return legitimize_tls_address (x, NULL_RTX);
4546
bca653c5 4547 if (GET_CODE (x) == PLUS
4548 && GET_CODE (XEXP (x, 1)) == CONST_INT
4549 && (INTVAL (XEXP (x, 1)) >= 32 * GET_MODE_SIZE (mode)
4550 || INTVAL (XEXP (x, 1)) < 0))
4551 {
4552 rtx xop0 = XEXP (x, 0);
4553 rtx xop1 = XEXP (x, 1);
4554 HOST_WIDE_INT offset = INTVAL (xop1);
4555
4556 /* Try and fold the offset into a biasing of the base register and
4557 then offsetting that. Don't do this when optimizing for space
4558 since it can cause too many CSEs. */
4559 if (optimize_size && offset >= 0
4560 && offset < 256 + 31 * GET_MODE_SIZE (mode))
4561 {
4562 HOST_WIDE_INT delta;
4563
4564 if (offset >= 256)
4565 delta = offset - (256 - GET_MODE_SIZE (mode));
4566 else if (offset < 32 * GET_MODE_SIZE (mode) + 8)
4567 delta = 31 * GET_MODE_SIZE (mode);
4568 else
4569 delta = offset & (~31 * GET_MODE_SIZE (mode));
4570
4571 xop0 = force_operand (plus_constant (xop0, offset - delta),
4572 NULL_RTX);
4573 x = plus_constant (xop0, delta);
4574 }
4575 else if (offset < 0 && offset > -256)
4576 /* Small negative offsets are best done with a subtract before the
4577 dereference, forcing these into a register normally takes two
4578 instructions. */
4579 x = force_operand (x, NULL_RTX);
4580 else
4581 {
4582 /* For the remaining cases, force the constant into a register. */
4583 xop1 = force_reg (SImode, xop1);
4584 x = gen_rtx_PLUS (SImode, xop0, xop1);
4585 }
4586 }
4587 else if (GET_CODE (x) == PLUS
4588 && s_register_operand (XEXP (x, 1), SImode)
4589 && !s_register_operand (XEXP (x, 0), SImode))
4590 {
4591 rtx xop0 = force_operand (XEXP (x, 0), NULL_RTX);
4592
4593 x = gen_rtx_PLUS (SImode, xop0, XEXP (x, 1));
4594 }
4595
4596 if (flag_pic)
4597 {
4598 /* We need to find and carefully transform any SYMBOL and LABEL
4599 references; so go back to the original address expression. */
4600 rtx new_x = legitimize_pic_address (orig_x, mode, NULL_RTX);
4601
4602 if (new_x != orig_x)
4603 x = new_x;
4604 }
4605
4606 return x;
4607}
4608
5ede62f6 4609rtx
a60f1840 4610thumb_legitimize_reload_address (rtx *x_p,
4611 enum machine_mode mode,
4612 int opnum, int type,
4613 int ind_levels ATTRIBUTE_UNUSED)
5ede62f6 4614{
4615 rtx x = *x_p;
a60f1840 4616
5ede62f6 4617 if (GET_CODE (x) == PLUS
4618 && GET_MODE_SIZE (mode) < 4
4619 && REG_P (XEXP (x, 0))
4620 && XEXP (x, 0) == stack_pointer_rtx
4621 && GET_CODE (XEXP (x, 1)) == CONST_INT
4622 && !thumb_legitimate_offset_p (mode, INTVAL (XEXP (x, 1))))
4623 {
4624 rtx orig_x = x;
4625
4626 x = copy_rtx (x);
4627 push_reload (orig_x, NULL_RTX, x_p, NULL, MODE_BASE_REG_CLASS (mode),
4628 Pmode, VOIDmode, 0, 0, opnum, type);
4629 return x;
4630 }
4631
4632 /* If both registers are hi-regs, then it's better to reload the
4633 entire expression rather than each register individually. That
4634 only requires one reload register rather than two. */
4635 if (GET_CODE (x) == PLUS
4636 && REG_P (XEXP (x, 0))
4637 && REG_P (XEXP (x, 1))
4638 && !REG_MODE_OK_FOR_REG_BASE_P (XEXP (x, 0), mode)
4639 && !REG_MODE_OK_FOR_REG_BASE_P (XEXP (x, 1), mode))
4640 {
4641 rtx orig_x = x;
4642
4643 x = copy_rtx (x);
4644 push_reload (orig_x, NULL_RTX, x_p, NULL, MODE_BASE_REG_CLASS (mode),
4645 Pmode, VOIDmode, 0, 0, opnum, type);
4646 return x;
4647 }
4648
4649 return NULL;
4650}
f655717d 4651
4652/* Test for various thread-local symbols. */
4653
4654/* Return TRUE if X is a thread-local symbol. */
4655
4656static bool
4657arm_tls_symbol_p (rtx x)
4658{
4659 if (! TARGET_HAVE_TLS)
4660 return false;
4661
4662 if (GET_CODE (x) != SYMBOL_REF)
4663 return false;
4664
4665 return SYMBOL_REF_TLS_MODEL (x) != 0;
4666}
4667
4668/* Helper for arm_tls_referenced_p. */
4669
4670static int
4671arm_tls_operand_p_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
4672{
4673 if (GET_CODE (*x) == SYMBOL_REF)
4674 return SYMBOL_REF_TLS_MODEL (*x) != 0;
4675
4676 /* Don't recurse into UNSPEC_TLS looking for TLS symbols; these are
4677 TLS offsets, not real symbol references. */
4678 if (GET_CODE (*x) == UNSPEC
4679 && XINT (*x, 1) == UNSPEC_TLS)
4680 return -1;
4681
4682 return 0;
4683}
4684
4685/* Return TRUE if X contains any TLS symbol references. */
4686
4687bool
4688arm_tls_referenced_p (rtx x)
4689{
4690 if (! TARGET_HAVE_TLS)
4691 return false;
4692
4693 return for_each_rtx (&x, arm_tls_operand_p_1, NULL);
4694}
e348ff3e 4695
4696/* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
4697
4698bool
4699arm_cannot_force_const_mem (rtx x)
4700{
4701 rtx base, offset;
4702
4703 if (ARM_OFFSETS_MUST_BE_WITHIN_SECTIONS_P)
4704 {
4705 split_const (x, &base, &offset);
4706 if (GET_CODE (base) == SYMBOL_REF
4707 && !offset_within_block_p (base, INTVAL (offset)))
4708 return true;
4709 }
4710 return arm_tls_referenced_p (x);
4711}
d32b3557 4712\f
4b6897e9 4713#define REG_OR_SUBREG_REG(X) \
4714 (GET_CODE (X) == REG \
4715 || (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG))
4716
4717#define REG_OR_SUBREG_RTX(X) \
4718 (GET_CODE (X) == REG ? (X) : SUBREG_REG (X))
4719
cffb2a26 4720#ifndef COSTS_N_INSNS
4721#define COSTS_N_INSNS(N) ((N) * 4 - 2)
4722#endif
fab7adbf 4723static inline int
25f905c2 4724thumb1_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer)
4b6897e9 4725{
4726 enum machine_mode mode = GET_MODE (x);
4b6897e9 4727
a2cd141b 4728 switch (code)
cffb2a26 4729 {
a2cd141b 4730 case ASHIFT:
4731 case ASHIFTRT:
4732 case LSHIFTRT:
9e7454d0 4733 case ROTATERT:
a2cd141b 4734 case PLUS:
4735 case MINUS:
4736 case COMPARE:
4737 case NEG:
9e7454d0 4738 case NOT:
a2cd141b 4739 return COSTS_N_INSNS (1);
9e7454d0 4740
4741 case MULT:
4742 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4743 {
4744 int cycles = 0;
a2cd141b 4745 unsigned HOST_WIDE_INT i = INTVAL (XEXP (x, 1));
9e7454d0 4746
4747 while (i)
4748 {
4749 i >>= 2;
4750 cycles++;
4751 }
4752 return COSTS_N_INSNS (2) + cycles;
a2cd141b 4753 }
4754 return COSTS_N_INSNS (1) + 16;
9e7454d0 4755
4756 case SET:
4757 return (COSTS_N_INSNS (1)
4758 + 4 * ((GET_CODE (SET_SRC (x)) == MEM)
a2cd141b 4759 + GET_CODE (SET_DEST (x)) == MEM));
9e7454d0 4760
4761 case CONST_INT:
4762 if (outer == SET)
4763 {
4764 if ((unsigned HOST_WIDE_INT) INTVAL (x) < 256)
4765 return 0;
4766 if (thumb_shiftable_const (INTVAL (x)))
4767 return COSTS_N_INSNS (2);
4768 return COSTS_N_INSNS (3);
4769 }
a2cd141b 4770 else if ((outer == PLUS || outer == COMPARE)
9e7454d0 4771 && INTVAL (x) < 256 && INTVAL (x) > -256)
a2cd141b 4772 return 0;
4773 else if (outer == AND
4774 && INTVAL (x) < 256 && INTVAL (x) >= -256)
4775 return COSTS_N_INSNS (1);
9e7454d0 4776 else if (outer == ASHIFT || outer == ASHIFTRT
4777 || outer == LSHIFTRT)
4778 return 0;
a2cd141b 4779 return COSTS_N_INSNS (2);
9e7454d0 4780
4781 case CONST:
4782 case CONST_DOUBLE:
4783 case LABEL_REF:
4784 case SYMBOL_REF:
a2cd141b 4785 return COSTS_N_INSNS (3);
9e7454d0 4786
a2cd141b 4787 case UDIV:
4788 case UMOD:
4789 case DIV:
4790 case MOD:
4791 return 100;
cffb2a26 4792
a2cd141b 4793 case TRUNCATE:
4794 return 99;
cffb2a26 4795
a2cd141b 4796 case AND:
4797 case XOR:
9e7454d0 4798 case IOR:
1d60d981 4799 /* XXX guess. */
a2cd141b 4800 return 8;
cffb2a26 4801
a2cd141b 4802 case MEM:
4803 /* XXX another guess. */
4804 /* Memory costs quite a lot for the first word, but subsequent words
4805 load at the equivalent of a single insn each. */
4806 return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD)
4807 + ((GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
4808 ? 4 : 0));
4809
4810 case IF_THEN_ELSE:
1d60d981 4811 /* XXX a guess. */
a2cd141b 4812 if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC)
4813 return 14;
4814 return 2;
4815
4816 case ZERO_EXTEND:
4817 /* XXX still guessing. */
4818 switch (GET_MODE (XEXP (x, 0)))
4819 {
4820 case QImode:
4821 return (1 + (mode == DImode ? 4 : 0)
4822 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
9e7454d0 4823
a2cd141b 4824 case HImode:
4825 return (4 + (mode == DImode ? 4 : 0)
4826 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
9e7454d0 4827
a2cd141b 4828 case SImode:
4829 return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
9e7454d0 4830
cffb2a26 4831 default:
4832 return 99;
cffb2a26 4833 }
9e7454d0 4834
a2cd141b 4835 default:
4836 return 99;
cffb2a26 4837 }
a2cd141b 4838}
4839
4840
4841/* Worker routine for arm_rtx_costs. */
25f905c2 4842/* ??? This needs updating for thumb2. */
a2cd141b 4843static inline int
4844arm_rtx_costs_1 (rtx x, enum rtx_code code, enum rtx_code outer)
4845{
4846 enum machine_mode mode = GET_MODE (x);
4847 enum rtx_code subcode;
4848 int extra_cost;
4849
4b6897e9 4850 switch (code)
4851 {
4852 case MEM:
4853 /* Memory costs quite a lot for the first word, but subsequent words
4854 load at the equivalent of a single insn each. */
4855 return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD)
3ccc58a6 4856 + (GET_CODE (x) == SYMBOL_REF
4857 && CONSTANT_POOL_ADDRESS_P (x) ? 4 : 0));
4b6897e9 4858
4859 case DIV:
4860 case MOD:
6b784824 4861 case UDIV:
4862 case UMOD:
4863 return optimize_size ? COSTS_N_INSNS (2) : 100;
4b6897e9 4864
4865 case ROTATE:
4866 if (mode == SImode && GET_CODE (XEXP (x, 1)) == REG)
4867 return 4;
4868 /* Fall through */
4869 case ROTATERT:
4870 if (mode != SImode)
4871 return 8;
4872 /* Fall through */
4873 case ASHIFT: case LSHIFTRT: case ASHIFTRT:
4874 if (mode == DImode)
4875 return (8 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : 8)
9e7454d0 4876 + ((GET_CODE (XEXP (x, 0)) == REG
4b6897e9 4877 || (GET_CODE (XEXP (x, 0)) == SUBREG
4878 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG))
4879 ? 0 : 8));
4880 return (1 + ((GET_CODE (XEXP (x, 0)) == REG
4881 || (GET_CODE (XEXP (x, 0)) == SUBREG
4882 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG))
4883 ? 0 : 4)
4884 + ((GET_CODE (XEXP (x, 1)) == REG
4885 || (GET_CODE (XEXP (x, 1)) == SUBREG
4886 && GET_CODE (SUBREG_REG (XEXP (x, 1))) == REG)
4887 || (GET_CODE (XEXP (x, 1)) == CONST_INT))
4888 ? 0 : 4));
4889
4890 case MINUS:
89545238 4891 if (GET_CODE (XEXP (x, 1)) == MULT && mode == SImode && arm_arch_thumb2)
4892 {
4893 extra_cost = rtx_cost (XEXP (x, 1), code);
4894 if (!REG_OR_SUBREG_REG (XEXP (x, 0)))
4895 extra_cost += 4 * ARM_NUM_REGS (mode);
4896 return extra_cost;
4897 }
4898
4b6897e9 4899 if (mode == DImode)
4900 return (4 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 8)
4901 + ((REG_OR_SUBREG_REG (XEXP (x, 0))
4902 || (GET_CODE (XEXP (x, 0)) == CONST_INT
4903 && const_ok_for_arm (INTVAL (XEXP (x, 0)))))
4904 ? 0 : 8));
4905
4906 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
4907 return (2 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
4908 || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
a2cd141b 4909 && arm_const_double_rtx (XEXP (x, 1))))
4b6897e9 4910 ? 0 : 8)
4911 + ((REG_OR_SUBREG_REG (XEXP (x, 0))
4912 || (GET_CODE (XEXP (x, 0)) == CONST_DOUBLE
a2cd141b 4913 && arm_const_double_rtx (XEXP (x, 0))))
4b6897e9 4914 ? 0 : 8));
4915
4916 if (((GET_CODE (XEXP (x, 0)) == CONST_INT
4917 && const_ok_for_arm (INTVAL (XEXP (x, 0)))
4918 && REG_OR_SUBREG_REG (XEXP (x, 1))))
4919 || (((subcode = GET_CODE (XEXP (x, 1))) == ASHIFT
4920 || subcode == ASHIFTRT || subcode == LSHIFTRT
4921 || subcode == ROTATE || subcode == ROTATERT
4922 || (subcode == MULT
4923 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4924 && ((INTVAL (XEXP (XEXP (x, 1), 1)) &
4925 (INTVAL (XEXP (XEXP (x, 1), 1)) - 1)) == 0)))
4926 && REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 0))
4927 && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 1))
4928 || GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT)
4929 && REG_OR_SUBREG_REG (XEXP (x, 0))))
4930 return 1;
4931 /* Fall through */
4932
9e7454d0 4933 case PLUS:
bd7a45c4 4934 if (GET_CODE (XEXP (x, 0)) == MULT)
4935 {
4936 extra_cost = rtx_cost (XEXP (x, 0), code);
4937 if (!REG_OR_SUBREG_REG (XEXP (x, 1)))
4938 extra_cost += 4 * ARM_NUM_REGS (mode);
4939 return extra_cost;
4940 }
4941
4b6897e9 4942 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
4943 return (2 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)
4944 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
4945 || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
a2cd141b 4946 && arm_const_double_rtx (XEXP (x, 1))))
4b6897e9 4947 ? 0 : 8));
4948
4949 /* Fall through */
9e7454d0 4950 case AND: case XOR: case IOR:
4b6897e9 4951 extra_cost = 0;
4952
4953 /* Normally the frame registers will be spilt into reg+const during
4954 reload, so it is a bad idea to combine them with other instructions,
4955 since then they might not be moved outside of loops. As a compromise
4956 we allow integration with ops that have a constant as their second
4957 operand. */
4958 if ((REG_OR_SUBREG_REG (XEXP (x, 0))
4959 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))
4960 && GET_CODE (XEXP (x, 1)) != CONST_INT)
4961 || (REG_OR_SUBREG_REG (XEXP (x, 0))
4962 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))))
4963 extra_cost = 4;
4964
4965 if (mode == DImode)
4966 return (4 + extra_cost + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)
4967 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
4968 || (GET_CODE (XEXP (x, 1)) == CONST_INT
016696d4 4969 && const_ok_for_op (INTVAL (XEXP (x, 1)), code)))
4b6897e9 4970 ? 0 : 8));
4971
4972 if (REG_OR_SUBREG_REG (XEXP (x, 0)))
4973 return (1 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : extra_cost)
4974 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
4975 || (GET_CODE (XEXP (x, 1)) == CONST_INT
016696d4 4976 && const_ok_for_op (INTVAL (XEXP (x, 1)), code)))
4b6897e9 4977 ? 0 : 4));
4978
4979 else if (REG_OR_SUBREG_REG (XEXP (x, 1)))
4980 return (1 + extra_cost
4981 + ((((subcode = GET_CODE (XEXP (x, 0))) == ASHIFT
4982 || subcode == LSHIFTRT || subcode == ASHIFTRT
4983 || subcode == ROTATE || subcode == ROTATERT
4984 || (subcode == MULT
4985 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4986 && ((INTVAL (XEXP (XEXP (x, 0), 1)) &
ecd3fcc7 4987 (INTVAL (XEXP (XEXP (x, 0), 1)) - 1)) == 0)))
4b6897e9 4988 && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 0)))
4989 && ((REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 1)))
ecd3fcc7 4990 || GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT))
4b6897e9 4991 ? 0 : 4));
4992
4993 return 8;
4994
4995 case MULT:
a2cd141b 4996 /* This should have been handled by the CPU specific routines. */
ed29c566 4997 gcc_unreachable ();
4b6897e9 4998
6019008a 4999 case TRUNCATE:
a2cd141b 5000 if (arm_arch3m && mode == SImode
6019008a 5001 && GET_CODE (XEXP (x, 0)) == LSHIFTRT
5002 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
5003 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0))
5004 == GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)))
5005 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ZERO_EXTEND
5006 || GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == SIGN_EXTEND))
5007 return 8;
5008 return 99;
5009
4b6897e9 5010 case NEG:
5011 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
5012 return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 6);
5013 /* Fall through */
5014 case NOT:
5015 if (mode == DImode)
5016 return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4);
5017
5018 return 1 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4);
5019
5020 case IF_THEN_ELSE:
5021 if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC)
5022 return 14;
5023 return 2;
5024
5025 case COMPARE:
5026 return 1;
5027
5028 case ABS:
5029 return 4 + (mode == DImode ? 4 : 0);
5030
5031 case SIGN_EXTEND:
25f905c2 5032 /* ??? value extensions are cheaper on armv6. */
4b6897e9 5033 if (GET_MODE (XEXP (x, 0)) == QImode)
5034 return (4 + (mode == DImode ? 4 : 0)
5035 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
5036 /* Fall through */
5037 case ZERO_EXTEND:
5038 switch (GET_MODE (XEXP (x, 0)))
5039 {
5040 case QImode:
5041 return (1 + (mode == DImode ? 4 : 0)
5042 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
5043
5044 case HImode:
5045 return (4 + (mode == DImode ? 4 : 0)
5046 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
5047
5048 case SImode:
5049 return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
ecd3fcc7 5050
755eb2b4 5051 case V8QImode:
5052 case V4HImode:
5053 case V2SImode:
5054 case V4QImode:
5055 case V2HImode:
5056 return 1;
5057
ecd3fcc7 5058 default:
ed29c566 5059 gcc_unreachable ();
4b6897e9 5060 }
ed29c566 5061 gcc_unreachable ();
4b6897e9 5062
9e7454d0 5063 case CONST_INT:
5064 if (const_ok_for_arm (INTVAL (x)))
5065 return outer == SET ? 2 : -1;
5066 else if (outer == AND
5067 && const_ok_for_arm (~INTVAL (x)))
5068 return -1;
5069 else if ((outer == COMPARE
5070 || outer == PLUS || outer == MINUS)
5071 && const_ok_for_arm (-INTVAL (x)))
5072 return -1;
5073 else
cffb2a26 5074 return 5;
9e7454d0 5075
5076 case CONST:
5077 case LABEL_REF:
5078 case SYMBOL_REF:
cffb2a26 5079 return 6;
9e7454d0 5080
5081 case CONST_DOUBLE:
b5a0636d 5082 if (arm_const_double_rtx (x) || vfp3_const_double_rtx (x))
9e7454d0 5083 return outer == SET ? 2 : -1;
5084 else if ((outer == COMPARE || outer == PLUS)
5085 && neg_const_double_rtx_ok_for_fpa (x))
5086 return -1;
cffb2a26 5087 return 7;
9e7454d0 5088
4b6897e9 5089 default:
5090 return 99;
5091 }
5092}
69120d26 5093
c1877da8 5094/* RTX costs when optimizing for size. */
5095static bool
5096arm_size_rtx_costs (rtx x, int code, int outer_code, int *total)
5097{
5098 enum machine_mode mode = GET_MODE (x);
5099
5100 if (TARGET_THUMB)
5101 {
5102 /* XXX TBD. For now, use the standard costs. */
25f905c2 5103 *total = thumb1_rtx_costs (x, code, outer_code);
c1877da8 5104 return true;
5105 }
5106
5107 switch (code)
5108 {
5109 case MEM:
9e7454d0 5110 /* A memory access costs 1 insn if the mode is small, or the address is
c1877da8 5111 a single register, otherwise it costs one insn per word. */
5112 if (REG_P (XEXP (x, 0)))
5113 *total = COSTS_N_INSNS (1);
5114 else
5115 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
5116 return true;
5117
5118 case DIV:
5119 case MOD:
5120 case UDIV:
5121 case UMOD:
5122 /* Needs a libcall, so it costs about this. */
5123 *total = COSTS_N_INSNS (2);
5124 return false;
5125
5126 case ROTATE:
5127 if (mode == SImode && GET_CODE (XEXP (x, 1)) == REG)
5128 {
5129 *total = COSTS_N_INSNS (2) + rtx_cost (XEXP (x, 0), code);
5130 return true;
5131 }
5132 /* Fall through */
5133 case ROTATERT:
5134 case ASHIFT:
5135 case LSHIFTRT:
5136 case ASHIFTRT:
5137 if (mode == DImode && GET_CODE (XEXP (x, 1)) == CONST_INT)
5138 {
5139 *total = COSTS_N_INSNS (3) + rtx_cost (XEXP (x, 0), code);
5140 return true;
5141 }
5142 else if (mode == SImode)
5143 {
5144 *total = COSTS_N_INSNS (1) + rtx_cost (XEXP (x, 0), code);
5145 /* Slightly disparage register shifts, but not by much. */
5146 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
5147 *total += 1 + rtx_cost (XEXP (x, 1), code);
5148 return true;
5149 }
5150
5151 /* Needs a libcall. */
5152 *total = COSTS_N_INSNS (2);
5153 return false;
5154
5155 case MINUS:
5156 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT)
5157 {
5158 *total = COSTS_N_INSNS (1);
5159 return false;
5160 }
5161
5162 if (mode == SImode)
5163 {
5164 enum rtx_code subcode0 = GET_CODE (XEXP (x, 0));
5165 enum rtx_code subcode1 = GET_CODE (XEXP (x, 1));
5166
5167 if (subcode0 == ROTATE || subcode0 == ROTATERT || subcode0 == ASHIFT
5168 || subcode0 == LSHIFTRT || subcode0 == ASHIFTRT
5169 || subcode1 == ROTATE || subcode1 == ROTATERT
5170 || subcode1 == ASHIFT || subcode1 == LSHIFTRT
5171 || subcode1 == ASHIFTRT)
5172 {
5173 /* It's just the cost of the two operands. */
5174 *total = 0;
5175 return false;
5176 }
5177
5178 *total = COSTS_N_INSNS (1);
5179 return false;
5180 }
5181
5182 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
5183 return false;
5184
9e7454d0 5185 case PLUS:
c1877da8 5186 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT)
5187 {
5188 *total = COSTS_N_INSNS (1);
5189 return false;
5190 }
5191
5192 /* Fall through */
5193 case AND: case XOR: case IOR:
5194 if (mode == SImode)
5195 {
5196 enum rtx_code subcode = GET_CODE (XEXP (x, 0));
5197
5198 if (subcode == ROTATE || subcode == ROTATERT || subcode == ASHIFT
5199 || subcode == LSHIFTRT || subcode == ASHIFTRT
5200 || (code == AND && subcode == NOT))
5201 {
5202 /* It's just the cost of the two operands. */
5203 *total = 0;
5204 return false;
5205 }
5206 }
5207
5208 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
5209 return false;
5210
5211 case MULT:
5212 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
5213 return false;
5214
5215 case NEG:
5216 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT)
5217 *total = COSTS_N_INSNS (1);
5218 /* Fall through */
5219 case NOT:
5220 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
5221
5222 return false;
5223
5224 case IF_THEN_ELSE:
5225 *total = 0;
5226 return false;
5227
5228 case COMPARE:
5229 if (cc_register (XEXP (x, 0), VOIDmode))
5230 * total = 0;
5231 else
5232 *total = COSTS_N_INSNS (1);
5233 return false;
5234
5235 case ABS:
5236 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT)
5237 *total = COSTS_N_INSNS (1);
5238 else
5239 *total = COSTS_N_INSNS (1 + ARM_NUM_REGS (mode));
5240 return false;
5241
5242 case SIGN_EXTEND:
5243 *total = 0;
5244 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) < 4)
5245 {
5246 if (!(arm_arch4 && MEM_P (XEXP (x, 0))))
5247 *total += COSTS_N_INSNS (arm_arch6 ? 1 : 2);
5248 }
5249 if (mode == DImode)
5250 *total += COSTS_N_INSNS (1);
5251 return false;
5252
5253 case ZERO_EXTEND:
5254 *total = 0;
5255 if (!(arm_arch4 && MEM_P (XEXP (x, 0))))
5256 {
5257 switch (GET_MODE (XEXP (x, 0)))
5258 {
5259 case QImode:
5260 *total += COSTS_N_INSNS (1);
5261 break;
5262
5263 case HImode:
5264 *total += COSTS_N_INSNS (arm_arch6 ? 1 : 2);
9e7454d0 5265
c1877da8 5266 case SImode:
5267 break;
5268
5269 default:
5270 *total += COSTS_N_INSNS (2);
5271 }
5272 }
5273
5274 if (mode == DImode)
5275 *total += COSTS_N_INSNS (1);
5276
5277 return false;
5278
9e7454d0 5279 case CONST_INT:
5280 if (const_ok_for_arm (INTVAL (x)))
c1877da8 5281 *total = COSTS_N_INSNS (outer_code == SET ? 1 : 0);
5282 else if (const_ok_for_arm (~INTVAL (x)))
5283 *total = COSTS_N_INSNS (outer_code == AND ? 0 : 1);
5284 else if (const_ok_for_arm (-INTVAL (x)))
5285 {
5286 if (outer_code == COMPARE || outer_code == PLUS
5287 || outer_code == MINUS)
5288 *total = 0;
5289 else
5290 *total = COSTS_N_INSNS (1);
5291 }
5292 else
5293 *total = COSTS_N_INSNS (2);
5294 return true;
9e7454d0 5295
5296 case CONST:
5297 case LABEL_REF:
5298 case SYMBOL_REF:
c1877da8 5299 *total = COSTS_N_INSNS (2);
5300 return true;
9e7454d0 5301
c1877da8 5302 case CONST_DOUBLE:
5303 *total = COSTS_N_INSNS (4);
5304 return true;
5305
5306 default:
5307 if (mode != VOIDmode)
5308 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
5309 else
5310 *total = COSTS_N_INSNS (4); /* How knows? */
5311 return false;
5312 }
5313}
5314
25f905c2 5315/* RTX costs for cores with a slow MUL implementation. Thumb-2 is not
5316 supported on any "slowmul" cores, so it can be ignored. */
a2cd141b 5317
fab7adbf 5318static bool
a2cd141b 5319arm_slowmul_rtx_costs (rtx x, int code, int outer_code, int *total)
fab7adbf 5320{
a2cd141b 5321 enum machine_mode mode = GET_MODE (x);
5322
5323 if (TARGET_THUMB)
5324 {
25f905c2 5325 *total = thumb1_rtx_costs (x, code, outer_code);
a2cd141b 5326 return true;
5327 }
9e7454d0 5328
a2cd141b 5329 switch (code)
5330 {
5331 case MULT:
5332 if (GET_MODE_CLASS (mode) == MODE_FLOAT
5333 || mode == DImode)
5334 {
5335 *total = 30;
5336 return true;
5337 }
5338
5339 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
5340 {
5341 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
5342 & (unsigned HOST_WIDE_INT) 0xffffffff);
5343 int cost, const_ok = const_ok_for_arm (i);
5344 int j, booth_unit_size;
5345
9e7454d0 5346 /* Tune as appropriate. */
a2cd141b 5347 cost = const_ok ? 4 : 8;
5348 booth_unit_size = 2;
5349 for (j = 0; i && j < 32; j += booth_unit_size)
5350 {
5351 i >>= booth_unit_size;
5352 cost += 2;
5353 }
5354
5355 *total = cost;
5356 return true;
5357 }
5358
5359 *total = 30 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4)
5360 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4);
5361 return true;
9e7454d0 5362
a2cd141b 5363 default:
5364 *total = arm_rtx_costs_1 (x, code, outer_code);
5365 return true;
5366 }
fab7adbf 5367}
5368
a2cd141b 5369
5370/* RTX cost for cores with a fast multiply unit (M variants). */
5371
5372static bool
5373arm_fastmul_rtx_costs (rtx x, int code, int outer_code, int *total)
5374{
5375 enum machine_mode mode = GET_MODE (x);
5376
25f905c2 5377 if (TARGET_THUMB1)
a2cd141b 5378 {
25f905c2 5379 *total = thumb1_rtx_costs (x, code, outer_code);
a2cd141b 5380 return true;
5381 }
9e7454d0 5382
25f905c2 5383 /* ??? should thumb2 use different costs? */
a2cd141b 5384 switch (code)
5385 {
5386 case MULT:
5387 /* There is no point basing this on the tuning, since it is always the
5388 fast variant if it exists at all. */
5389 if (mode == DImode
5390 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
5391 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
5392 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
5393 {
5394 *total = 8;
5395 return true;
5396 }
9e7454d0 5397
a2cd141b 5398
5399 if (GET_MODE_CLASS (mode) == MODE_FLOAT
5400 || mode == DImode)
5401 {
5402 *total = 30;
5403 return true;
5404 }
5405
5406 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
5407 {
5408 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
5409 & (unsigned HOST_WIDE_INT) 0xffffffff);
5410 int cost, const_ok = const_ok_for_arm (i);
5411 int j, booth_unit_size;
5412
9e7454d0 5413 /* Tune as appropriate. */
a2cd141b 5414 cost = const_ok ? 4 : 8;
5415 booth_unit_size = 8;
5416 for (j = 0; i && j < 32; j += booth_unit_size)
5417 {
5418 i >>= booth_unit_size;
5419 cost += 2;
5420 }
5421
5422 *total = cost;
5423 return true;
5424 }
5425
5426 *total = 8 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4)
5427 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4);
5428 return true;
9e7454d0 5429
a2cd141b 5430 default:
5431 *total = arm_rtx_costs_1 (x, code, outer_code);
5432 return true;
5433 }
5434}
5435
5436
25f905c2 5437/* RTX cost for XScale CPUs. Thumb-2 is not supported on any xscale cores,
5438 so it can be ignored. */
a2cd141b 5439
5440static bool
5441arm_xscale_rtx_costs (rtx x, int code, int outer_code, int *total)
5442{
5443 enum machine_mode mode = GET_MODE (x);
5444
5445 if (TARGET_THUMB)
5446 {
25f905c2 5447 *total = thumb1_rtx_costs (x, code, outer_code);
a2cd141b 5448 return true;
5449 }
9e7454d0 5450
a2cd141b 5451 switch (code)
5452 {
5453 case MULT:
5454 /* There is no point basing this on the tuning, since it is always the
5455 fast variant if it exists at all. */
5456 if (mode == DImode
5457 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
5458 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
5459 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
5460 {
5461 *total = 8;
5462 return true;
5463 }
9e7454d0 5464
a2cd141b 5465
5466 if (GET_MODE_CLASS (mode) == MODE_FLOAT
5467 || mode == DImode)
5468 {
5469 *total = 30;
5470 return true;
5471 }
5472
5473 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
5474 {
5475 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
5476 & (unsigned HOST_WIDE_INT) 0xffffffff);
5477 int cost, const_ok = const_ok_for_arm (i);
5478 unsigned HOST_WIDE_INT masked_const;
5479
5480 /* The cost will be related to two insns.
1d60d981 5481 First a load of the constant (MOV or LDR), then a multiply. */
a2cd141b 5482 cost = 2;
5483 if (! const_ok)
5484 cost += 1; /* LDR is probably more expensive because
1d60d981 5485 of longer result latency. */
a2cd141b 5486 masked_const = i & 0xffff8000;
5487 if (masked_const != 0 && masked_const != 0xffff8000)
5488 {
5489 masked_const = i & 0xf8000000;
5490 if (masked_const == 0 || masked_const == 0xf8000000)
5491 cost += 1;
5492 else
5493 cost += 2;
5494 }
5495 *total = cost;
5496 return true;
5497 }
5498
5499 *total = 8 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4)
5500 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4);
5501 return true;
9e7454d0 5502
e8a4aa75 5503 case COMPARE:
5504 /* A COMPARE of a MULT is slow on XScale; the muls instruction
5505 will stall until the multiplication is complete. */
5506 if (GET_CODE (XEXP (x, 0)) == MULT)
5507 *total = 4 + rtx_cost (XEXP (x, 0), code);
5508 else
5509 *total = arm_rtx_costs_1 (x, code, outer_code);
5510 return true;
5511
a2cd141b 5512 default:
5513 *total = arm_rtx_costs_1 (x, code, outer_code);
5514 return true;
5515 }
5516}
5517
5518
5519/* RTX costs for 9e (and later) cores. */
5520
5521static bool
5522arm_9e_rtx_costs (rtx x, int code, int outer_code, int *total)
5523{
5524 enum machine_mode mode = GET_MODE (x);
5525 int nonreg_cost;
5526 int cost;
9e7454d0 5527
25f905c2 5528 if (TARGET_THUMB1)
a2cd141b 5529 {
5530 switch (code)
5531 {
5532 case MULT:
5533 *total = COSTS_N_INSNS (3);
5534 return true;
9e7454d0 5535
a2cd141b 5536 default:
25f905c2 5537 *total = thumb1_rtx_costs (x, code, outer_code);
a2cd141b 5538 return true;
5539 }
5540 }
9e7454d0 5541
a2cd141b 5542 switch (code)
5543 {
5544 case MULT:
5545 /* There is no point basing this on the tuning, since it is always the
5546 fast variant if it exists at all. */
5547 if (mode == DImode
5548 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
5549 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
5550 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
5551 {
5552 *total = 3;
5553 return true;
5554 }
9e7454d0 5555
a2cd141b 5556
5557 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
5558 {
5559 *total = 30;
5560 return true;
5561 }
5562 if (mode == DImode)
5563 {
5564 cost = 7;
5565 nonreg_cost = 8;
5566 }
5567 else
5568 {
5569 cost = 2;
5570 nonreg_cost = 4;
5571 }
5572
5573
5574 *total = cost + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : nonreg_cost)
5575 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : nonreg_cost);
5576 return true;
9e7454d0 5577
a2cd141b 5578 default:
5579 *total = arm_rtx_costs_1 (x, code, outer_code);
5580 return true;
5581 }
5582}
ec0457a8 5583/* All address computations that can be done are free, but rtx cost returns
5584 the same for practically all of them. So we weight the different types
5585 of address here in the order (most pref first):
674a8f0b 5586 PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */
d0472904 5587static inline int
5588arm_arm_address_cost (rtx x)
5589{
5590 enum rtx_code c = GET_CODE (x);
5591
5592 if (c == PRE_INC || c == PRE_DEC || c == POST_INC || c == POST_DEC)
5593 return 0;
5594 if (c == MEM || c == LABEL_REF || c == SYMBOL_REF)
5595 return 10;
5596
5597 if (c == PLUS || c == MINUS)
5598 {
d0472904 5599 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
5600 return 2;
5601
6720e96c 5602 if (ARITHMETIC_P (XEXP (x, 0)) || ARITHMETIC_P (XEXP (x, 1)))
d0472904 5603 return 3;
5604
5605 return 4;
5606 }
5607
5608 return 6;
5609}
5610
5611static inline int
5612arm_thumb_address_cost (rtx x)
5613{
5614 enum rtx_code c = GET_CODE (x);
5615
5616 if (c == REG)
5617 return 1;
5618 if (c == PLUS
5619 && GET_CODE (XEXP (x, 0)) == REG
5620 && GET_CODE (XEXP (x, 1)) == CONST_INT)
5621 return 1;
5622
5623 return 2;
5624}
5625
ec0457a8 5626static int
ebd88a36 5627arm_address_cost (rtx x)
ec0457a8 5628{
25f905c2 5629 return TARGET_32BIT ? arm_arm_address_cost (x) : arm_thumb_address_cost (x);
ec0457a8 5630}
5631
747af5e7 5632static int
ebd88a36 5633arm_adjust_cost (rtx insn, rtx link, rtx dep, int cost)
69120d26 5634{
5635 rtx i_pat, d_pat;
5636
331beb1a 5637 /* Some true dependencies can have a higher cost depending
5638 on precisely how certain input operands are used. */
f8e17552 5639 if (arm_tune_xscale
331beb1a 5640 && REG_NOTE_KIND (link) == 0
86437b62 5641 && recog_memoized (insn) >= 0
5642 && recog_memoized (dep) >= 0)
331beb1a 5643 {
5644 int shift_opnum = get_attr_shift (insn);
5645 enum attr_type attr_type = get_attr_type (dep);
5646
5647 /* If nonzero, SHIFT_OPNUM contains the operand number of a shifted
5648 operand for INSN. If we have a shifted input operand and the
5649 instruction we depend on is another ALU instruction, then we may
5650 have to account for an additional stall. */
a2cd141b 5651 if (shift_opnum != 0
5652 && (attr_type == TYPE_ALU_SHIFT || attr_type == TYPE_ALU_SHIFT_REG))
331beb1a 5653 {
5654 rtx shifted_operand;
5655 int opno;
9e7454d0 5656
331beb1a 5657 /* Get the shifted operand. */
5658 extract_insn (insn);
5659 shifted_operand = recog_data.operand[shift_opnum];
5660
5661 /* Iterate over all the operands in DEP. If we write an operand
5662 that overlaps with SHIFTED_OPERAND, then we have increase the
5663 cost of this dependency. */
5664 extract_insn (dep);
5665 preprocess_constraints ();
5666 for (opno = 0; opno < recog_data.n_operands; opno++)
5667 {
5668 /* We can ignore strict inputs. */
5669 if (recog_data.operand_type[opno] == OP_IN)
5670 continue;
5671
5672 if (reg_overlap_mentioned_p (recog_data.operand[opno],
5673 shifted_operand))
5674 return 2;
5675 }
5676 }
5677 }
5678
66aacf41 5679 /* XXX This is not strictly true for the FPA. */
cffb2a26 5680 if (REG_NOTE_KIND (link) == REG_DEP_ANTI
5681 || REG_NOTE_KIND (link) == REG_DEP_OUTPUT)
129a2fe4 5682 return 0;
5683
cffb2a26 5684 /* Call insns don't incur a stall, even if they follow a load. */
5685 if (REG_NOTE_KIND (link) == 0
5686 && GET_CODE (insn) == CALL_INSN)
5687 return 1;
5688
69120d26 5689 if ((i_pat = single_set (insn)) != NULL
5690 && GET_CODE (SET_SRC (i_pat)) == MEM
5691 && (d_pat = single_set (dep)) != NULL
5692 && GET_CODE (SET_DEST (d_pat)) == MEM)
5693 {
3ccc58a6 5694 rtx src_mem = XEXP (SET_SRC (i_pat), 0);
69120d26 5695 /* This is a load after a store, there is no conflict if the load reads
5696 from a cached area. Assume that loads from the stack, and from the
9e7454d0 5697 constant pool are cached, and that others will miss. This is a
66aacf41 5698 hack. */
9e7454d0 5699
3ccc58a6 5700 if ((GET_CODE (src_mem) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (src_mem))
5701 || reg_mentioned_p (stack_pointer_rtx, src_mem)
5702 || reg_mentioned_p (frame_pointer_rtx, src_mem)
5703 || reg_mentioned_p (hard_frame_pointer_rtx, src_mem))
56d27660 5704 return 1;
69120d26 5705 }
5706
5707 return cost;
5708}
5709
a2cd141b 5710static int fp_consts_inited = 0;
9c08d1fa 5711
a2cd141b 5712/* Only zero is valid for VFP. Other values are also valid for FPA. */
5713static const char * const strings_fp[8] =
bba10fb8 5714{
64266206 5715 "0", "1", "2", "3",
5716 "4", "5", "0.5", "10"
5717};
9c08d1fa 5718
a2cd141b 5719static REAL_VALUE_TYPE values_fp[8];
9c08d1fa 5720
5721static void
a2cd141b 5722init_fp_table (void)
9c08d1fa 5723{
5724 int i;
5725 REAL_VALUE_TYPE r;
5726
a2cd141b 5727 if (TARGET_VFP)
5728 fp_consts_inited = 1;
5729 else
5730 fp_consts_inited = 8;
5731
5732 for (i = 0; i < fp_consts_inited; i++)
9c08d1fa 5733 {
a2cd141b 5734 r = REAL_VALUE_ATOF (strings_fp[i], DFmode);
5735 values_fp[i] = r;
9c08d1fa 5736 }
9c08d1fa 5737}
5738
a2cd141b 5739/* Return TRUE if rtx X is a valid immediate FP constant. */
8cd42699 5740int
a2cd141b 5741arm_const_double_rtx (rtx x)
8cd42699 5742{
9c08d1fa 5743 REAL_VALUE_TYPE r;
5744 int i;
9e7454d0 5745
a2cd141b 5746 if (!fp_consts_inited)
5747 init_fp_table ();
9e7454d0 5748
9c08d1fa 5749 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
5750 if (REAL_VALUE_MINUS_ZERO (r))
5751 return 0;
a690ede2 5752
a2cd141b 5753 for (i = 0; i < fp_consts_inited; i++)
5754 if (REAL_VALUES_EQUAL (r, values_fp[i]))
9c08d1fa 5755 return 1;
a690ede2 5756
9c08d1fa 5757 return 0;
a690ede2 5758}
9c08d1fa 5759
e8ff69a4 5760/* Return TRUE if rtx X is a valid immediate FPA constant. */
9c08d1fa 5761int
ebd88a36 5762neg_const_double_rtx_ok_for_fpa (rtx x)
9c08d1fa 5763{
5764 REAL_VALUE_TYPE r;
5765 int i;
9e7454d0 5766
a2cd141b 5767 if (!fp_consts_inited)
5768 init_fp_table ();
9e7454d0 5769
9c08d1fa 5770 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
5771 r = REAL_VALUE_NEGATE (r);
5772 if (REAL_VALUE_MINUS_ZERO (r))
5773 return 0;
a690ede2 5774
9c08d1fa 5775 for (i = 0; i < 8; i++)
a2cd141b 5776 if (REAL_VALUES_EQUAL (r, values_fp[i]))
9c08d1fa 5777 return 1;
a690ede2 5778
9c08d1fa 5779 return 0;
a690ede2 5780}
b5a0636d 5781
5782
5783/* VFPv3 has a fairly wide range of representable immediates, formed from
5784 "quarter-precision" floating-point values. These can be evaluated using this
5785 formula (with ^ for exponentiation):
5786
5787 -1^s * n * 2^-r
5788
5789 Where 's' is a sign bit (0/1), 'n' and 'r' are integers such that
5790 16 <= n <= 31 and 0 <= r <= 7.
5791
5792 These values are mapped onto an 8-bit integer ABCDEFGH s.t.
5793
5794 - A (most-significant) is the sign bit.
5795 - BCD are the exponent (encoded as r XOR 3).
5796 - EFGH are the mantissa (encoded as n - 16).
5797*/
5798
5799/* Return an integer index for a VFPv3 immediate operand X suitable for the
5800 fconst[sd] instruction, or -1 if X isn't suitable. */
5801static int
5802vfp3_const_double_index (rtx x)
5803{
5804 REAL_VALUE_TYPE r, m;
5805 int sign, exponent;
5806 unsigned HOST_WIDE_INT mantissa, mant_hi;
5807 unsigned HOST_WIDE_INT mask;
2e5b424c 5808 HOST_WIDE_INT m1, m2;
b5a0636d 5809 int point_pos = 2 * HOST_BITS_PER_WIDE_INT - 1;
5810
5811 if (!TARGET_VFP3 || GET_CODE (x) != CONST_DOUBLE)
5812 return -1;
5813
5814 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
5815
5816 /* We can't represent these things, so detect them first. */
5817 if (REAL_VALUE_ISINF (r) || REAL_VALUE_ISNAN (r) || REAL_VALUE_MINUS_ZERO (r))
5818 return -1;
5819
5820 /* Extract sign, exponent and mantissa. */
5821 sign = REAL_VALUE_NEGATIVE (r) ? 1 : 0;
5822 r = REAL_VALUE_ABS (r);
5823 exponent = REAL_EXP (&r);
5824 /* For the mantissa, we expand into two HOST_WIDE_INTS, apart from the
5825 highest (sign) bit, with a fixed binary point at bit point_pos.
5826 WARNING: If there's ever a VFP version which uses more than 2 * H_W_I - 1
5827 bits for the mantissa, this may fail (low bits would be lost). */
5828 real_ldexp (&m, &r, point_pos - exponent);
2e5b424c 5829 REAL_VALUE_TO_INT (&m1, &m2, m);
5830 mantissa = m1;
5831 mant_hi = m2;
b5a0636d 5832
5833 /* If there are bits set in the low part of the mantissa, we can't
5834 represent this value. */
5835 if (mantissa != 0)
5836 return -1;
5837
5838 /* Now make it so that mantissa contains the most-significant bits, and move
5839 the point_pos to indicate that the least-significant bits have been
5840 discarded. */
5841 point_pos -= HOST_BITS_PER_WIDE_INT;
5842 mantissa = mant_hi;
5843
5844 /* We can permit four significant bits of mantissa only, plus a high bit
5845 which is always 1. */
5846 mask = ((unsigned HOST_WIDE_INT)1 << (point_pos - 5)) - 1;
5847 if ((mantissa & mask) != 0)
5848 return -1;
5849
5850 /* Now we know the mantissa is in range, chop off the unneeded bits. */
5851 mantissa >>= point_pos - 5;
5852
5853 /* The mantissa may be zero. Disallow that case. (It's possible to load the
5854 floating-point immediate zero with Neon using an integer-zero load, but
5855 that case is handled elsewhere.) */
5856 if (mantissa == 0)
5857 return -1;
5858
5859 gcc_assert (mantissa >= 16 && mantissa <= 31);
5860
5861 /* The value of 5 here would be 4 if GCC used IEEE754-like encoding (where
6dfdc153 5862 normalized significands are in the range [1, 2). (Our mantissa is shifted
5863 left 4 places at this point relative to normalized IEEE754 values). GCC
b5a0636d 5864 internally uses [0.5, 1) (see real.c), so the exponent returned from
5865 REAL_EXP must be altered. */
5866 exponent = 5 - exponent;
5867
5868 if (exponent < 0 || exponent > 7)
5869 return -1;
5870
5871 /* Sign, mantissa and exponent are now in the correct form to plug into the
5872 formulae described in the comment above. */
5873 return (sign << 7) | ((exponent ^ 3) << 4) | (mantissa - 16);
5874}
5875
5876/* Return TRUE if rtx X is a valid immediate VFPv3 constant. */
5877int
5878vfp3_const_double_rtx (rtx x)
5879{
5880 if (!TARGET_VFP3)
5881 return 0;
5882
5883 return vfp3_const_double_index (x) != -1;
5884}
5885
d98a3884 5886/* Recognize immediates which can be used in various Neon instructions. Legal
5887 immediates are described by the following table (for VMVN variants, the
5888 bitwise inverse of the constant shown is recognized. In either case, VMOV
5889 is output and the correct instruction to use for a given constant is chosen
5890 by the assembler). The constant shown is replicated across all elements of
5891 the destination vector.
5892
5893 insn elems variant constant (binary)
5894 ---- ----- ------- -----------------
5895 vmov i32 0 00000000 00000000 00000000 abcdefgh
5896 vmov i32 1 00000000 00000000 abcdefgh 00000000
5897 vmov i32 2 00000000 abcdefgh 00000000 00000000
5898 vmov i32 3 abcdefgh 00000000 00000000 00000000
5899 vmov i16 4 00000000 abcdefgh
5900 vmov i16 5 abcdefgh 00000000
5901 vmvn i32 6 00000000 00000000 00000000 abcdefgh
5902 vmvn i32 7 00000000 00000000 abcdefgh 00000000
5903 vmvn i32 8 00000000 abcdefgh 00000000 00000000
5904 vmvn i32 9 abcdefgh 00000000 00000000 00000000
5905 vmvn i16 10 00000000 abcdefgh
5906 vmvn i16 11 abcdefgh 00000000
5907 vmov i32 12 00000000 00000000 abcdefgh 11111111
5908 vmvn i32 13 00000000 00000000 abcdefgh 11111111
5909 vmov i32 14 00000000 abcdefgh 11111111 11111111
5910 vmvn i32 15 00000000 abcdefgh 11111111 11111111
5911 vmov i8 16 abcdefgh
5912 vmov i64 17 aaaaaaaa bbbbbbbb cccccccc dddddddd
5913 eeeeeeee ffffffff gggggggg hhhhhhhh
5914 vmov f32 18 aBbbbbbc defgh000 00000000 00000000
5915
5916 For case 18, B = !b. Representable values are exactly those accepted by
5917 vfp3_const_double_index, but are output as floating-point numbers rather
5918 than indices.
5919
5920 Variants 0-5 (inclusive) may also be used as immediates for the second
5921 operand of VORR/VBIC instructions.
5922
5923 The INVERSE argument causes the bitwise inverse of the given operand to be
5924 recognized instead (used for recognizing legal immediates for the VAND/VORN
5925 pseudo-instructions). If INVERSE is true, the value placed in *MODCONST is
5926 *not* inverted (i.e. the pseudo-instruction forms vand/vorn should still be
5927 output, rather than the real insns vbic/vorr).
5928
5929 INVERSE makes no difference to the recognition of float vectors.
5930
5931 The return value is the variant of immediate as shown in the above table, or
5932 -1 if the given value doesn't match any of the listed patterns.
5933*/
5934static int
5935neon_valid_immediate (rtx op, enum machine_mode mode, int inverse,
5936 rtx *modconst, int *elementwidth)
5937{
5938#define CHECK(STRIDE, ELSIZE, CLASS, TEST) \
5939 matches = 1; \
5940 for (i = 0; i < idx; i += (STRIDE)) \
5941 if (!(TEST)) \
5942 matches = 0; \
5943 if (matches) \
5944 { \
5945 immtype = (CLASS); \
5946 elsize = (ELSIZE); \
5947 break; \
5948 }
5949
5950 unsigned int i, elsize, idx = 0, n_elts = CONST_VECTOR_NUNITS (op);
5951 unsigned int innersize = GET_MODE_SIZE (GET_MODE_INNER (mode));
5952 unsigned char bytes[16];
5953 int immtype = -1, matches;
5954 unsigned int invmask = inverse ? 0xff : 0;
5955
5956 /* Vectors of float constants. */
5957 if (GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
5958 {
5959 rtx el0 = CONST_VECTOR_ELT (op, 0);
5960 REAL_VALUE_TYPE r0;
5961
5962 if (!vfp3_const_double_rtx (el0))
5963 return -1;
5964
5965 REAL_VALUE_FROM_CONST_DOUBLE (r0, el0);
5966
5967 for (i = 1; i < n_elts; i++)
5968 {
5969 rtx elt = CONST_VECTOR_ELT (op, i);
5970 REAL_VALUE_TYPE re;
5971
5972 REAL_VALUE_FROM_CONST_DOUBLE (re, elt);
5973
5974 if (!REAL_VALUES_EQUAL (r0, re))
5975 return -1;
5976 }
5977
5978 if (modconst)
5979 *modconst = CONST_VECTOR_ELT (op, 0);
5980
5981 if (elementwidth)
5982 *elementwidth = 0;
5983
5984 return 18;
5985 }
5986
5987 /* Splat vector constant out into a byte vector. */
5988 for (i = 0; i < n_elts; i++)
5989 {
5990 rtx el = CONST_VECTOR_ELT (op, i);
5991 unsigned HOST_WIDE_INT elpart;
5992 unsigned int part, parts;
5993
5994 if (GET_CODE (el) == CONST_INT)
5995 {
5996 elpart = INTVAL (el);
5997 parts = 1;
5998 }
5999 else if (GET_CODE (el) == CONST_DOUBLE)
6000 {
6001 elpart = CONST_DOUBLE_LOW (el);
6002 parts = 2;
6003 }
6004 else
6005 gcc_unreachable ();
6006
6007 for (part = 0; part < parts; part++)
6008 {
6009 unsigned int byte;
6010 for (byte = 0; byte < innersize; byte++)
6011 {
6012 bytes[idx++] = (elpart & 0xff) ^ invmask;
6013 elpart >>= BITS_PER_UNIT;
6014 }
6015 if (GET_CODE (el) == CONST_DOUBLE)
6016 elpart = CONST_DOUBLE_HIGH (el);
6017 }
6018 }
6019
6020 /* Sanity check. */
6021 gcc_assert (idx == GET_MODE_SIZE (mode));
6022
6023 do
6024 {
6025 CHECK (4, 32, 0, bytes[i] == bytes[0] && bytes[i + 1] == 0
6026 && bytes[i + 2] == 0 && bytes[i + 3] == 0);
6027
6028 CHECK (4, 32, 1, bytes[i] == 0 && bytes[i + 1] == bytes[1]
6029 && bytes[i + 2] == 0 && bytes[i + 3] == 0);
6030
6031 CHECK (4, 32, 2, bytes[i] == 0 && bytes[i + 1] == 0
6032 && bytes[i + 2] == bytes[2] && bytes[i + 3] == 0);
6033
6034 CHECK (4, 32, 3, bytes[i] == 0 && bytes[i + 1] == 0
6035 && bytes[i + 2] == 0 && bytes[i + 3] == bytes[3]);
6036
6037 CHECK (2, 16, 4, bytes[i] == bytes[0] && bytes[i + 1] == 0);
6038
6039 CHECK (2, 16, 5, bytes[i] == 0 && bytes[i + 1] == bytes[1]);
6040
6041 CHECK (4, 32, 6, bytes[i] == bytes[0] && bytes[i + 1] == 0xff
6042 && bytes[i + 2] == 0xff && bytes[i + 3] == 0xff);
6043
6044 CHECK (4, 32, 7, bytes[i] == 0xff && bytes[i + 1] == bytes[1]
6045 && bytes[i + 2] == 0xff && bytes[i + 3] == 0xff);
6046
6047 CHECK (4, 32, 8, bytes[i] == 0xff && bytes[i + 1] == 0xff
6048 && bytes[i + 2] == bytes[2] && bytes[i + 3] == 0xff);
6049
6050 CHECK (4, 32, 9, bytes[i] == 0xff && bytes[i + 1] == 0xff
6051 && bytes[i + 2] == 0xff && bytes[i + 3] == bytes[3]);
6052
6053 CHECK (2, 16, 10, bytes[i] == bytes[0] && bytes[i + 1] == 0xff);
6054
6055 CHECK (2, 16, 11, bytes[i] == 0xff && bytes[i + 1] == bytes[1]);
6056
6057 CHECK (4, 32, 12, bytes[i] == 0xff && bytes[i + 1] == bytes[1]
6058 && bytes[i + 2] == 0 && bytes[i + 3] == 0);
6059
6060 CHECK (4, 32, 13, bytes[i] == 0 && bytes[i + 1] == bytes[1]
6061 && bytes[i + 2] == 0xff && bytes[i + 3] == 0xff);
6062
6063 CHECK (4, 32, 14, bytes[i] == 0xff && bytes[i + 1] == 0xff
6064 && bytes[i + 2] == bytes[2] && bytes[i + 3] == 0);
6065
6066 CHECK (4, 32, 15, bytes[i] == 0 && bytes[i + 1] == 0
6067 && bytes[i + 2] == bytes[2] && bytes[i + 3] == 0xff);
6068
6069 CHECK (1, 8, 16, bytes[i] == bytes[0]);
6070
6071 CHECK (1, 64, 17, (bytes[i] == 0 || bytes[i] == 0xff)
6072 && bytes[i] == bytes[(i + 8) % idx]);
6073 }
6074 while (0);
6075
6076 if (immtype == -1)
6077 return -1;
6078
6079 if (elementwidth)
6080 *elementwidth = elsize;
6081
6082 if (modconst)
6083 {
6084 unsigned HOST_WIDE_INT imm = 0;
6085
6086 /* Un-invert bytes of recognized vector, if neccessary. */
6087 if (invmask != 0)
6088 for (i = 0; i < idx; i++)
6089 bytes[i] ^= invmask;
6090
6091 if (immtype == 17)
6092 {
6093 /* FIXME: Broken on 32-bit H_W_I hosts. */
6094 gcc_assert (sizeof (HOST_WIDE_INT) == 8);
6095
6096 for (i = 0; i < 8; i++)
6097 imm |= (unsigned HOST_WIDE_INT) (bytes[i] ? 0xff : 0)
6098 << (i * BITS_PER_UNIT);
6099
6100 *modconst = GEN_INT (imm);
6101 }
6102 else
6103 {
6104 unsigned HOST_WIDE_INT imm = 0;
6105
6106 for (i = 0; i < elsize / BITS_PER_UNIT; i++)
6107 imm |= (unsigned HOST_WIDE_INT) bytes[i] << (i * BITS_PER_UNIT);
6108
6109 *modconst = GEN_INT (imm);
6110 }
6111 }
6112
6113 return immtype;
6114#undef CHECK
6115}
6116
6117/* Return TRUE if rtx X is legal for use as either a Neon VMOV (or, implicitly,
6118 VMVN) immediate. Write back width per element to *ELEMENTWIDTH (or zero for
6119 float elements), and a modified constant (whatever should be output for a
6120 VMOV) in *MODCONST. */
6121
6122int
6123neon_immediate_valid_for_move (rtx op, enum machine_mode mode,
6124 rtx *modconst, int *elementwidth)
6125{
6126 rtx tmpconst;
6127 int tmpwidth;
6128 int retval = neon_valid_immediate (op, mode, 0, &tmpconst, &tmpwidth);
6129
6130 if (retval == -1)
6131 return 0;
6132
6133 if (modconst)
6134 *modconst = tmpconst;
6135
6136 if (elementwidth)
6137 *elementwidth = tmpwidth;
6138
6139 return 1;
6140}
6141
6142/* Return TRUE if rtx X is legal for use in a VORR or VBIC instruction. If
6143 the immediate is valid, write a constant suitable for using as an operand
6144 to VORR/VBIC/VAND/VORN to *MODCONST and the corresponding element width to
6145 *ELEMENTWIDTH. See neon_valid_immediate for description of INVERSE. */
6146
6147int
6148neon_immediate_valid_for_logic (rtx op, enum machine_mode mode, int inverse,
6149 rtx *modconst, int *elementwidth)
6150{
6151 rtx tmpconst;
6152 int tmpwidth;
6153 int retval = neon_valid_immediate (op, mode, inverse, &tmpconst, &tmpwidth);
6154
6155 if (retval < 0 || retval > 5)
6156 return 0;
6157
6158 if (modconst)
6159 *modconst = tmpconst;
6160
6161 if (elementwidth)
6162 *elementwidth = tmpwidth;
6163
6164 return 1;
6165}
6166
6167/* Return a string suitable for output of Neon immediate logic operation
6168 MNEM. */
6169
6170char *
6171neon_output_logic_immediate (const char *mnem, rtx *op2, enum machine_mode mode,
6172 int inverse, int quad)
6173{
6174 int width, is_valid;
6175 static char templ[40];
6176
6177 is_valid = neon_immediate_valid_for_logic (*op2, mode, inverse, op2, &width);
6178
6179 gcc_assert (is_valid != 0);
6180
6181 if (quad)
6182 sprintf (templ, "%s.i%d\t%%q0, %%2", mnem, width);
6183 else
6184 sprintf (templ, "%s.i%d\t%%P0, %%2", mnem, width);
6185
6186 return templ;
6187}
6188
6189/* Output a sequence of pairwise operations to implement a reduction.
6190 NOTE: We do "too much work" here, because pairwise operations work on two
6191 registers-worth of operands in one go. Unfortunately we can't exploit those
6192 extra calculations to do the full operation in fewer steps, I don't think.
6193 Although all vector elements of the result but the first are ignored, we
6194 actually calculate the same result in each of the elements. An alternative
6195 such as initially loading a vector with zero to use as each of the second
6196 operands would use up an additional register and take an extra instruction,
6197 for no particular gain. */
6198
6199void
6200neon_pairwise_reduce (rtx op0, rtx op1, enum machine_mode mode,
6201 rtx (*reduc) (rtx, rtx, rtx))
6202{
6203 enum machine_mode inner = GET_MODE_INNER (mode);
6204 unsigned int i, parts = GET_MODE_SIZE (mode) / GET_MODE_SIZE (inner);
6205 rtx tmpsum = op1;
6206
6207 for (i = parts / 2; i >= 1; i /= 2)
6208 {
6209 rtx dest = (i == 1) ? op0 : gen_reg_rtx (mode);
6210 emit_insn (reduc (dest, tmpsum, tmpsum));
6211 tmpsum = dest;
6212 }
6213}
6214
6215/* Initialise a vector with non-constant elements. FIXME: We can do better
6216 than the current implementation (building a vector on the stack and then
6217 loading it) in many cases. See rs6000.c. */
6218
6219void
6220neon_expand_vector_init (rtx target, rtx vals)
6221{
6222 enum machine_mode mode = GET_MODE (target);
6223 enum machine_mode inner = GET_MODE_INNER (mode);
6224 unsigned int i, n_elts = GET_MODE_NUNITS (mode);
6225 rtx mem;
6226
6227 gcc_assert (VECTOR_MODE_P (mode));
6228
6229 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0);
6230 for (i = 0; i < n_elts; i++)
6231 emit_move_insn (adjust_address_nv (mem, inner, i * GET_MODE_SIZE (inner)),
6232 XVECEXP (vals, 0, i));
6233
6234 emit_move_insn (target, mem);
6235}
6236
8cd42699 6237\f
6238/* Predicates for `match_operand' and `match_operator'. */
6239
7d57ec45 6240/* Return nonzero if OP is a valid Cirrus memory address pattern. */
7d57ec45 6241int
ebd88a36 6242cirrus_memory_offset (rtx op)
7d57ec45 6243{
6244 /* Reject eliminable registers. */
6245 if (! (reload_in_progress || reload_completed)
6246 && ( reg_mentioned_p (frame_pointer_rtx, op)
6247 || reg_mentioned_p (arg_pointer_rtx, op)
6248 || reg_mentioned_p (virtual_incoming_args_rtx, op)
6249 || reg_mentioned_p (virtual_outgoing_args_rtx, op)
6250 || reg_mentioned_p (virtual_stack_dynamic_rtx, op)
6251 || reg_mentioned_p (virtual_stack_vars_rtx, op)))
6252 return 0;
6253
6254 if (GET_CODE (op) == MEM)
6255 {
6256 rtx ind;
6257
6258 ind = XEXP (op, 0);
6259
6260 /* Match: (mem (reg)). */
6261 if (GET_CODE (ind) == REG)
6262 return 1;
6263
6264 /* Match:
6265 (mem (plus (reg)
6266 (const))). */
6267 if (GET_CODE (ind) == PLUS
6268 && GET_CODE (XEXP (ind, 0)) == REG
6269 && REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode)
6270 && GET_CODE (XEXP (ind, 1)) == CONST_INT)
6271 return 1;
6272 }
6273
6274 return 0;
6275}
6276
eb38fdf8 6277/* Return TRUE if OP is a valid coprocessor memory address pattern.
25f905c2 6278 WB is true if full writeback address modes are allowed and is false
6279 if limited writeback address modes (POST_INC and PRE_DEC) are
6280 allowed. */
a2cd141b 6281
6282int
a8a3b539 6283arm_coproc_mem_operand (rtx op, bool wb)
a2cd141b 6284{
a8a3b539 6285 rtx ind;
a2cd141b 6286
a8a3b539 6287 /* Reject eliminable registers. */
a2cd141b 6288 if (! (reload_in_progress || reload_completed)
6289 && ( reg_mentioned_p (frame_pointer_rtx, op)
6290 || reg_mentioned_p (arg_pointer_rtx, op)
6291 || reg_mentioned_p (virtual_incoming_args_rtx, op)
6292 || reg_mentioned_p (virtual_outgoing_args_rtx, op)
6293 || reg_mentioned_p (virtual_stack_dynamic_rtx, op)
6294 || reg_mentioned_p (virtual_stack_vars_rtx, op)))
6295 return FALSE;
6296
58552ed0 6297 /* Constants are converted into offsets from labels. */
a8a3b539 6298 if (GET_CODE (op) != MEM)
6299 return FALSE;
a2cd141b 6300
a8a3b539 6301 ind = XEXP (op, 0);
a2cd141b 6302
a8a3b539 6303 if (reload_completed
6304 && (GET_CODE (ind) == LABEL_REF
6305 || (GET_CODE (ind) == CONST
6306 && GET_CODE (XEXP (ind, 0)) == PLUS
6307 && GET_CODE (XEXP (XEXP (ind, 0), 0)) == LABEL_REF
6308 && GET_CODE (XEXP (XEXP (ind, 0), 1)) == CONST_INT)))
6309 return TRUE;
a2cd141b 6310
a8a3b539 6311 /* Match: (mem (reg)). */
6312 if (GET_CODE (ind) == REG)
6313 return arm_address_register_rtx_p (ind, 0);
6314
25f905c2 6315 /* Autoincremment addressing modes. POST_INC and PRE_DEC are
6316 acceptable in any case (subject to verification by
6317 arm_address_register_rtx_p). We need WB to be true to accept
6318 PRE_INC and POST_DEC. */
6319 if (GET_CODE (ind) == POST_INC
6320 || GET_CODE (ind) == PRE_DEC
6321 || (wb
6322 && (GET_CODE (ind) == PRE_INC
6323 || GET_CODE (ind) == POST_DEC)))
a8a3b539 6324 return arm_address_register_rtx_p (XEXP (ind, 0), 0);
6325
6326 if (wb
6327 && (GET_CODE (ind) == POST_MODIFY || GET_CODE (ind) == PRE_MODIFY)
6328 && arm_address_register_rtx_p (XEXP (ind, 0), 0)
6329 && GET_CODE (XEXP (ind, 1)) == PLUS
6330 && rtx_equal_p (XEXP (XEXP (ind, 1), 0), XEXP (ind, 0)))
6331 ind = XEXP (ind, 1);
6332
6333 /* Match:
6334 (plus (reg)
6335 (const)). */
6336 if (GET_CODE (ind) == PLUS
6337 && GET_CODE (XEXP (ind, 0)) == REG
6338 && REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode)
6339 && GET_CODE (XEXP (ind, 1)) == CONST_INT
6340 && INTVAL (XEXP (ind, 1)) > -1024
6341 && INTVAL (XEXP (ind, 1)) < 1024
6342 && (INTVAL (XEXP (ind, 1)) & 3) == 0)
6343 return TRUE;
a2cd141b 6344
6345 return FALSE;
6346}
6347
d98a3884 6348/* Return TRUE if OP is a memory operand which we can load or store a vector
6349 to/from. If CORE is true, we're moving from ARM registers not Neon
6350 registers. */
6351int
6352neon_vector_mem_operand (rtx op, bool core)
6353{
6354 rtx ind;
6355
6356 /* Reject eliminable registers. */
6357 if (! (reload_in_progress || reload_completed)
6358 && ( reg_mentioned_p (frame_pointer_rtx, op)
6359 || reg_mentioned_p (arg_pointer_rtx, op)
6360 || reg_mentioned_p (virtual_incoming_args_rtx, op)
6361 || reg_mentioned_p (virtual_outgoing_args_rtx, op)
6362 || reg_mentioned_p (virtual_stack_dynamic_rtx, op)
6363 || reg_mentioned_p (virtual_stack_vars_rtx, op)))
6364 return FALSE;
6365
6366 /* Constants are converted into offsets from labels. */
6367 if (GET_CODE (op) != MEM)
6368 return FALSE;
6369
6370 ind = XEXP (op, 0);
6371
6372 if (reload_completed
6373 && (GET_CODE (ind) == LABEL_REF
6374 || (GET_CODE (ind) == CONST
6375 && GET_CODE (XEXP (ind, 0)) == PLUS
6376 && GET_CODE (XEXP (XEXP (ind, 0), 0)) == LABEL_REF
6377 && GET_CODE (XEXP (XEXP (ind, 0), 1)) == CONST_INT)))
6378 return TRUE;
6379
6380 /* Match: (mem (reg)). */
6381 if (GET_CODE (ind) == REG)
6382 return arm_address_register_rtx_p (ind, 0);
6383
6384 /* Allow post-increment with Neon registers. */
6385 if (!core && GET_CODE (ind) == POST_INC)
6386 return arm_address_register_rtx_p (XEXP (ind, 0), 0);
6387
6388#if 0
6389 /* FIXME: We can support this too if we use VLD1/VST1. */
6390 if (!core
6391 && GET_CODE (ind) == POST_MODIFY
6392 && arm_address_register_rtx_p (XEXP (ind, 0), 0)
6393 && GET_CODE (XEXP (ind, 1)) == PLUS
6394 && rtx_equal_p (XEXP (XEXP (ind, 1), 0), XEXP (ind, 0)))
6395 ind = XEXP (ind, 1);
6396#endif
6397
6398 /* Match:
6399 (plus (reg)
6400 (const)). */
6401 if (!core
6402 && GET_CODE (ind) == PLUS
6403 && GET_CODE (XEXP (ind, 0)) == REG
6404 && REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode)
6405 && GET_CODE (XEXP (ind, 1)) == CONST_INT
6406 && INTVAL (XEXP (ind, 1)) > -1024
6407 && INTVAL (XEXP (ind, 1)) < 1016
6408 && (INTVAL (XEXP (ind, 1)) & 3) == 0)
6409 return TRUE;
6410
6411 return FALSE;
6412}
6413
6414/* Return TRUE if OP is a mem suitable for loading/storing a Neon struct
6415 type. */
6416int
6417neon_struct_mem_operand (rtx op)
6418{
6419 rtx ind;
6420
6421 /* Reject eliminable registers. */
6422 if (! (reload_in_progress || reload_completed)
6423 && ( reg_mentioned_p (frame_pointer_rtx, op)
6424 || reg_mentioned_p (arg_pointer_rtx, op)
6425 || reg_mentioned_p (virtual_incoming_args_rtx, op)
6426 || reg_mentioned_p (virtual_outgoing_args_rtx, op)
6427 || reg_mentioned_p (virtual_stack_dynamic_rtx, op)
6428 || reg_mentioned_p (virtual_stack_vars_rtx, op)))
6429 return FALSE;
6430
6431 /* Constants are converted into offsets from labels. */
6432 if (GET_CODE (op) != MEM)
6433 return FALSE;
6434
6435 ind = XEXP (op, 0);
6436
6437 if (reload_completed
6438 && (GET_CODE (ind) == LABEL_REF
6439 || (GET_CODE (ind) == CONST
6440 && GET_CODE (XEXP (ind, 0)) == PLUS
6441 && GET_CODE (XEXP (XEXP (ind, 0), 0)) == LABEL_REF
6442 && GET_CODE (XEXP (XEXP (ind, 0), 1)) == CONST_INT)))
6443 return TRUE;
6444
6445 /* Match: (mem (reg)). */
6446 if (GET_CODE (ind) == REG)
6447 return arm_address_register_rtx_p (ind, 0);
6448
6449 return FALSE;
6450}
6451
841b213d 6452/* Return true if X is a register that will be eliminated later on. */
6453int
6454arm_eliminable_register (rtx x)
6455{
6456 return REG_P (x) && (REGNO (x) == FRAME_POINTER_REGNUM
6457 || REGNO (x) == ARG_POINTER_REGNUM
6458 || (REGNO (x) >= FIRST_VIRTUAL_REGISTER
6459 && REGNO (x) <= LAST_VIRTUAL_REGISTER));
6460}
a2cd141b 6461
a2cd141b 6462/* Return GENERAL_REGS if a scratch register required to reload x to/from
f1225f6f 6463 coprocessor registers. Otherwise return NO_REGS. */
a2cd141b 6464
6465enum reg_class
f1225f6f 6466coproc_secondary_reload_class (enum machine_mode mode, rtx x, bool wb)
a2cd141b 6467{
d98a3884 6468 if (TARGET_NEON
6469 && (GET_MODE_CLASS (mode) == MODE_VECTOR_INT
6470 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
6471 && neon_vector_mem_operand (x, FALSE))
6472 return NO_REGS;
6473
f1225f6f 6474 if (arm_coproc_mem_operand (x, wb) || s_register_operand (x, mode))
a2cd141b 6475 return NO_REGS;
6476
6477 return GENERAL_REGS;
6478}
6479
46b5d878 6480/* Values which must be returned in the most-significant end of the return
6481 register. */
6482
6483static bool
6484arm_return_in_msb (tree valtype)
6485{
6486 return (TARGET_AAPCS_BASED
6487 && BYTES_BIG_ENDIAN
6488 && (AGGREGATE_TYPE_P (valtype)
6489 || TREE_CODE (valtype) == COMPLEX_TYPE));
6490}
a2cd141b 6491
2c6c7d8b 6492/* Returns TRUE if INSN is an "LDR REG, ADDR" instruction.
6493 Use by the Cirrus Maverick code which has to workaround
6494 a hardware bug triggered by such instructions. */
2c6c7d8b 6495static bool
ebd88a36 6496arm_memory_load_p (rtx insn)
7d57ec45 6497{
6498 rtx body, lhs, rhs;;
6499
2c6c7d8b 6500 if (insn == NULL_RTX || GET_CODE (insn) != INSN)
6501 return false;
7d57ec45 6502
6503 body = PATTERN (insn);
6504
6505 if (GET_CODE (body) != SET)
2c6c7d8b 6506 return false;
7d57ec45 6507
6508 lhs = XEXP (body, 0);
6509 rhs = XEXP (body, 1);
6510
2c6c7d8b 6511 lhs = REG_OR_SUBREG_RTX (lhs);
6512
6513 /* If the destination is not a general purpose
6514 register we do not have to worry. */
6515 if (GET_CODE (lhs) != REG
6516 || REGNO_REG_CLASS (REGNO (lhs)) != GENERAL_REGS)
6517 return false;
6518
6519 /* As well as loads from memory we also have to react
6520 to loads of invalid constants which will be turned
6521 into loads from the minipool. */
6522 return (GET_CODE (rhs) == MEM
6523 || GET_CODE (rhs) == SYMBOL_REF
6524 || note_invalid_constants (insn, -1, false));
7d57ec45 6525}
6526
2c6c7d8b 6527/* Return TRUE if INSN is a Cirrus instruction. */
2c6c7d8b 6528static bool
ebd88a36 6529arm_cirrus_insn_p (rtx insn)
7d57ec45 6530{
6531 enum attr_cirrus attr;
6532
ed29c566 6533 /* get_attr cannot accept USE or CLOBBER. */
7d57ec45 6534 if (!insn
6535 || GET_CODE (insn) != INSN
6536 || GET_CODE (PATTERN (insn)) == USE
6537 || GET_CODE (PATTERN (insn)) == CLOBBER)
6538 return 0;
6539
6540 attr = get_attr_cirrus (insn);
6541
2c6c7d8b 6542 return attr != CIRRUS_NOT;
7d57ec45 6543}
6544
6545/* Cirrus reorg for invalid instruction combinations. */
7d57ec45 6546static void
ebd88a36 6547cirrus_reorg (rtx first)
7d57ec45 6548{
6549 enum attr_cirrus attr;
6550 rtx body = PATTERN (first);
6551 rtx t;
6552 int nops;
6553
6554 /* Any branch must be followed by 2 non Cirrus instructions. */
6555 if (GET_CODE (first) == JUMP_INSN && GET_CODE (body) != RETURN)
6556 {
6557 nops = 0;
6558 t = next_nonnote_insn (first);
6559
2c6c7d8b 6560 if (arm_cirrus_insn_p (t))
7d57ec45 6561 ++ nops;
6562
2c6c7d8b 6563 if (arm_cirrus_insn_p (next_nonnote_insn (t)))
7d57ec45 6564 ++ nops;
6565
6566 while (nops --)
6567 emit_insn_after (gen_nop (), first);
6568
6569 return;
6570 }
6571
6572 /* (float (blah)) is in parallel with a clobber. */
6573 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0)
6574 body = XVECEXP (body, 0, 0);
6575
6576 if (GET_CODE (body) == SET)
6577 {
6578 rtx lhs = XEXP (body, 0), rhs = XEXP (body, 1);
6579
6580 /* cfldrd, cfldr64, cfstrd, cfstr64 must
6581 be followed by a non Cirrus insn. */
6582 if (get_attr_cirrus (first) == CIRRUS_DOUBLE)
6583 {
2c6c7d8b 6584 if (arm_cirrus_insn_p (next_nonnote_insn (first)))
7d57ec45 6585 emit_insn_after (gen_nop (), first);
6586
6587 return;
6588 }
2c6c7d8b 6589 else if (arm_memory_load_p (first))
7d57ec45 6590 {
6591 unsigned int arm_regno;
6592
6593 /* Any ldr/cfmvdlr, ldr/cfmvdhr, ldr/cfmvsr, ldr/cfmv64lr,
6594 ldr/cfmv64hr combination where the Rd field is the same
6595 in both instructions must be split with a non Cirrus
6596 insn. Example:
6597
6598 ldr r0, blah
6599 nop
6600 cfmvsr mvf0, r0. */
6601
6602 /* Get Arm register number for ldr insn. */
6603 if (GET_CODE (lhs) == REG)
6604 arm_regno = REGNO (lhs);
7d57ec45 6605 else
ed29c566 6606 {
6607 gcc_assert (GET_CODE (rhs) == REG);
6608 arm_regno = REGNO (rhs);
6609 }
7d57ec45 6610
6611 /* Next insn. */
6612 first = next_nonnote_insn (first);
6613
2c6c7d8b 6614 if (! arm_cirrus_insn_p (first))
7d57ec45 6615 return;
6616
6617 body = PATTERN (first);
6618
6619 /* (float (blah)) is in parallel with a clobber. */
6620 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0))
6621 body = XVECEXP (body, 0, 0);
6622
6623 if (GET_CODE (body) == FLOAT)
6624 body = XEXP (body, 0);
6625
6626 if (get_attr_cirrus (first) == CIRRUS_MOVE
6627 && GET_CODE (XEXP (body, 1)) == REG
6628 && arm_regno == REGNO (XEXP (body, 1)))
6629 emit_insn_after (gen_nop (), first);
6630
6631 return;
6632 }
6633 }
6634
ed29c566 6635 /* get_attr cannot accept USE or CLOBBER. */
7d57ec45 6636 if (!first
6637 || GET_CODE (first) != INSN
6638 || GET_CODE (PATTERN (first)) == USE
6639 || GET_CODE (PATTERN (first)) == CLOBBER)
6640 return;
6641
6642 attr = get_attr_cirrus (first);
6643
6644 /* Any coprocessor compare instruction (cfcmps, cfcmpd, ...)
6645 must be followed by a non-coprocessor instruction. */
6646 if (attr == CIRRUS_COMPARE)
6647 {
6648 nops = 0;
6649
6650 t = next_nonnote_insn (first);
6651
2c6c7d8b 6652 if (arm_cirrus_insn_p (t))
7d57ec45 6653 ++ nops;
6654
2c6c7d8b 6655 if (arm_cirrus_insn_p (next_nonnote_insn (t)))
7d57ec45 6656 ++ nops;
6657
6658 while (nops --)
6659 emit_insn_after (gen_nop (), first);
6660
6661 return;
6662 }
6663}
6664
64266206 6665/* Return TRUE if X references a SYMBOL_REF. */
6666int
ebd88a36 6667symbol_mentioned_p (rtx x)
64266206 6668{
a12be13c 6669 const char * fmt;
6670 int i;
64266206 6671
6672 if (GET_CODE (x) == SYMBOL_REF)
6673 return 1;
6674
f655717d 6675 /* UNSPEC_TLS entries for a symbol include the SYMBOL_REF, but they
6676 are constant offsets, not symbols. */
6677 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLS)
6678 return 0;
6679
64266206 6680 fmt = GET_RTX_FORMAT (GET_CODE (x));
9e7454d0 6681
64266206 6682 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
6683 {
6684 if (fmt[i] == 'E')
6685 {
a12be13c 6686 int j;
64266206 6687
6688 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
6689 if (symbol_mentioned_p (XVECEXP (x, i, j)))
6690 return 1;
6691 }
6692 else if (fmt[i] == 'e' && symbol_mentioned_p (XEXP (x, i)))
6693 return 1;
6694 }
6695
6696 return 0;
6697}
6698
6699/* Return TRUE if X references a LABEL_REF. */
6700int
ebd88a36 6701label_mentioned_p (rtx x)
64266206 6702{
a12be13c 6703 const char * fmt;
6704 int i;
64266206 6705
6706 if (GET_CODE (x) == LABEL_REF)
6707 return 1;
6708
f655717d 6709 /* UNSPEC_TLS entries for a symbol include a LABEL_REF for the referencing
6710 instruction, but they are constant offsets, not symbols. */
6711 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLS)
6712 return 0;
6713
64266206 6714 fmt = GET_RTX_FORMAT (GET_CODE (x));
6715 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
6716 {
6717 if (fmt[i] == 'E')
6718 {
a12be13c 6719 int j;
64266206 6720
6721 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
6722 if (label_mentioned_p (XVECEXP (x, i, j)))
6723 return 1;
6724 }
6725 else if (fmt[i] == 'e' && label_mentioned_p (XEXP (x, i)))
6726 return 1;
6727 }
6728
6729 return 0;
6730}
6731
f655717d 6732int
6733tls_mentioned_p (rtx x)
6734{
6735 switch (GET_CODE (x))
6736 {
6737 case CONST:
6738 return tls_mentioned_p (XEXP (x, 0));
6739
6740 case UNSPEC:
6741 if (XINT (x, 1) == UNSPEC_TLS)
6742 return 1;
6743
6744 default:
6745 return 0;
6746 }
6747}
6748
6749/* Must not copy a SET whose source operand is PC-relative. */
6750
6751static bool
6752arm_cannot_copy_insn_p (rtx insn)
6753{
6754 rtx pat = PATTERN (insn);
6755
beef0fb5 6756 if (GET_CODE (pat) == SET)
f655717d 6757 {
beef0fb5 6758 rtx rhs = SET_SRC (pat);
f655717d 6759
6760 if (GET_CODE (rhs) == UNSPEC
6761 && XINT (rhs, 1) == UNSPEC_PIC_BASE)
6762 return TRUE;
6763
6764 if (GET_CODE (rhs) == MEM
6765 && GET_CODE (XEXP (rhs, 0)) == UNSPEC
6766 && XINT (XEXP (rhs, 0), 1) == UNSPEC_PIC_BASE)
6767 return TRUE;
6768 }
6769
6770 return FALSE;
6771}
6772
9c08d1fa 6773enum rtx_code
ebd88a36 6774minmax_code (rtx x)
9c08d1fa 6775{
6776 enum rtx_code code = GET_CODE (x);
6777
ed29c566 6778 switch (code)
6779 {
6780 case SMAX:
6781 return GE;
6782 case SMIN:
6783 return LE;
6784 case UMIN:
6785 return LEU;
6786 case UMAX:
6787 return GEU;
6788 default:
6789 gcc_unreachable ();
6790 }
9c08d1fa 6791}
6792
66aacf41 6793/* Return 1 if memory locations are adjacent. */
a690ede2 6794int
ebd88a36 6795adjacent_mem_locations (rtx a, rtx b)
9c08d1fa 6796{
94dee231 6797 /* We don't guarantee to preserve the order of these memory refs. */
6798 if (volatile_refs_p (a) || volatile_refs_p (b))
6799 return 0;
6800
9c08d1fa 6801 if ((GET_CODE (XEXP (a, 0)) == REG
6802 || (GET_CODE (XEXP (a, 0)) == PLUS
6803 && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT))
6804 && (GET_CODE (XEXP (b, 0)) == REG
6805 || (GET_CODE (XEXP (b, 0)) == PLUS
6806 && GET_CODE (XEXP (XEXP (b, 0), 1)) == CONST_INT)))
6807 {
841b213d 6808 HOST_WIDE_INT val0 = 0, val1 = 0;
6809 rtx reg0, reg1;
6810 int val_diff;
9e7454d0 6811
9c08d1fa 6812 if (GET_CODE (XEXP (a, 0)) == PLUS)
6813 {
841b213d 6814 reg0 = XEXP (XEXP (a, 0), 0);
9c08d1fa 6815 val0 = INTVAL (XEXP (XEXP (a, 0), 1));
6816 }
6817 else
841b213d 6818 reg0 = XEXP (a, 0);
a12be13c 6819
9c08d1fa 6820 if (GET_CODE (XEXP (b, 0)) == PLUS)
6821 {
841b213d 6822 reg1 = XEXP (XEXP (b, 0), 0);
9c08d1fa 6823 val1 = INTVAL (XEXP (XEXP (b, 0), 1));
6824 }
6825 else
841b213d 6826 reg1 = XEXP (b, 0);
a12be13c 6827
ebd88a36 6828 /* Don't accept any offset that will require multiple
6829 instructions to handle, since this would cause the
6830 arith_adjacentmem pattern to output an overlong sequence. */
ce8e2d2d 6831 if (!const_ok_for_op (PLUS, val0) || !const_ok_for_op (PLUS, val1))
6832 return 0;
9e7454d0 6833
841b213d 6834 /* Don't allow an eliminable register: register elimination can make
6835 the offset too large. */
6836 if (arm_eliminable_register (reg0))
6837 return 0;
6838
6839 val_diff = val1 - val0;
94dee231 6840
6841 if (arm_ld_sched)
6842 {
6843 /* If the target has load delay slots, then there's no benefit
6844 to using an ldm instruction unless the offset is zero and
6845 we are optimizing for size. */
6846 return (optimize_size && (REGNO (reg0) == REGNO (reg1))
6847 && (val0 == 0 || val1 == 0 || val0 == 4 || val1 == 4)
6848 && (val_diff == 4 || val_diff == -4));
6849 }
6850
841b213d 6851 return ((REGNO (reg0) == REGNO (reg1))
6852 && (val_diff == 4 || val_diff == -4));
9c08d1fa 6853 }
841b213d 6854
9c08d1fa 6855 return 0;
6856}
6857
1275b964 6858int
ebd88a36 6859load_multiple_sequence (rtx *operands, int nops, int *regs, int *base,
6860 HOST_WIDE_INT *load_offset)
1275b964 6861{
6862 int unsorted_regs[4];
6863 HOST_WIDE_INT unsorted_offsets[4];
6864 int order[4];
ecd3fcc7 6865 int base_reg = -1;
1275b964 6866 int i;
6867
a12be13c 6868 /* Can only handle 2, 3, or 4 insns at present,
6869 though could be easily extended if required. */
ed29c566 6870 gcc_assert (nops >= 2 && nops <= 4);
1275b964 6871
6872 /* Loop over the operands and check that the memory references are
a361b456 6873 suitable (i.e. immediate offsets from the same base register). At
1275b964 6874 the same time, extract the target register, and the memory
6875 offsets. */
6876 for (i = 0; i < nops; i++)
6877 {
6878 rtx reg;
6879 rtx offset;
6880
6019008a 6881 /* Convert a subreg of a mem into the mem itself. */
6882 if (GET_CODE (operands[nops + i]) == SUBREG)
f2dd364c 6883 operands[nops + i] = alter_subreg (operands + (nops + i));
6019008a 6884
ed29c566 6885 gcc_assert (GET_CODE (operands[nops + i]) == MEM);
1275b964 6886
6887 /* Don't reorder volatile memory references; it doesn't seem worth
6888 looking for the case where the order is ok anyway. */
6889 if (MEM_VOLATILE_P (operands[nops + i]))
6890 return 0;
6891
6892 offset = const0_rtx;
6893
6894 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
6895 || (GET_CODE (reg) == SUBREG
6896 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
6897 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
6898 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
6899 == REG)
6900 || (GET_CODE (reg) == SUBREG
6901 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
6902 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
6903 == CONST_INT)))
6904 {
6905 if (i == 0)
6906 {
cffb2a26 6907 base_reg = REGNO (reg);
1275b964 6908 unsorted_regs[0] = (GET_CODE (operands[i]) == REG
6909 ? REGNO (operands[i])
6910 : REGNO (SUBREG_REG (operands[i])));
6911 order[0] = 0;
6912 }
9e7454d0 6913 else
1275b964 6914 {
66aacf41 6915 if (base_reg != (int) REGNO (reg))
1275b964 6916 /* Not addressed from the same base register. */
6917 return 0;
6918
6919 unsorted_regs[i] = (GET_CODE (operands[i]) == REG
6920 ? REGNO (operands[i])
6921 : REGNO (SUBREG_REG (operands[i])));
6922 if (unsorted_regs[i] < unsorted_regs[order[0]])
6923 order[0] = i;
6924 }
6925
6926 /* If it isn't an integer register, or if it overwrites the
6927 base register but isn't the last insn in the list, then
6928 we can't do this. */
6929 if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14
6930 || (i != nops - 1 && unsorted_regs[i] == base_reg))
6931 return 0;
6932
6933 unsorted_offsets[i] = INTVAL (offset);
6934 }
6935 else
6936 /* Not a suitable memory address. */
6937 return 0;
6938 }
6939
6940 /* All the useful information has now been extracted from the
6941 operands into unsorted_regs and unsorted_offsets; additionally,
6942 order[0] has been set to the lowest numbered register in the
6943 list. Sort the registers into order, and check that the memory
6944 offsets are ascending and adjacent. */
6945
6946 for (i = 1; i < nops; i++)
6947 {
6948 int j;
6949
6950 order[i] = order[i - 1];
6951 for (j = 0; j < nops; j++)
6952 if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
6953 && (order[i] == order[i - 1]
6954 || unsorted_regs[j] < unsorted_regs[order[i]]))
6955 order[i] = j;
6956
6957 /* Have we found a suitable register? if not, one must be used more
6958 than once. */
6959 if (order[i] == order[i - 1])
6960 return 0;
6961
6962 /* Is the memory address adjacent and ascending? */
6963 if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
6964 return 0;
6965 }
6966
6967 if (base)
6968 {
6969 *base = base_reg;
6970
6971 for (i = 0; i < nops; i++)
6972 regs[i] = unsorted_regs[order[i]];
6973
6974 *load_offset = unsorted_offsets[order[0]];
6975 }
6976
6977 if (unsorted_offsets[order[0]] == 0)
6978 return 1; /* ldmia */
6979
25f905c2 6980 if (TARGET_ARM && unsorted_offsets[order[0]] == 4)
1275b964 6981 return 2; /* ldmib */
6982
25f905c2 6983 if (TARGET_ARM && unsorted_offsets[order[nops - 1]] == 0)
1275b964 6984 return 3; /* ldmda */
6985
6986 if (unsorted_offsets[order[nops - 1]] == -4)
6987 return 4; /* ldmdb */
6988
56d27660 6989 /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm
6990 if the offset isn't small enough. The reason 2 ldrs are faster
6991 is because these ARMs are able to do more than one cache access
6992 in a single cycle. The ARM9 and StrongARM have Harvard caches,
6993 whilst the ARM8 has a double bandwidth cache. This means that
6994 these cores can do both an instruction fetch and a data fetch in
6995 a single cycle, so the trick of calculating the address into a
6996 scratch register (one of the result regs) and then doing a load
6997 multiple actually becomes slower (and no smaller in code size).
6998 That is the transformation
9e7454d0 6999
7bd8ccc9 7000 ldr rd1, [rbase + offset]
7001 ldr rd2, [rbase + offset + 4]
9e7454d0 7002
7bd8ccc9 7003 to
9e7454d0 7004
7bd8ccc9 7005 add rd1, rbase, offset
7006 ldmia rd1, {rd1, rd2}
9e7454d0 7007
56d27660 7008 produces worse code -- '3 cycles + any stalls on rd2' instead of
7009 '2 cycles + any stalls on rd2'. On ARMs with only one cache
7010 access per cycle, the first sequence could never complete in less
7011 than 6 cycles, whereas the ldm sequence would only take 5 and
7012 would make better use of sequential accesses if not hitting the
7013 cache.
7014
7015 We cheat here and test 'arm_ld_sched' which we currently know to
7016 only be true for the ARM8, ARM9 and StrongARM. If this ever
7017 changes, then the test below needs to be reworked. */
9888ad6d 7018 if (nops == 2 && arm_ld_sched)
129a2fe4 7019 return 0;
7020
1275b964 7021 /* Can't do it without setting up the offset, only do this if it takes
7022 no more than one insn. */
9e7454d0 7023 return (const_ok_for_arm (unsorted_offsets[order[0]])
1275b964 7024 || const_ok_for_arm (-unsorted_offsets[order[0]])) ? 5 : 0;
7025}
7026
0bd59681 7027const char *
ebd88a36 7028emit_ldm_seq (rtx *operands, int nops)
1275b964 7029{
7030 int regs[4];
7031 int base_reg;
7032 HOST_WIDE_INT offset;
7033 char buf[100];
7034 int i;
7035
7036 switch (load_multiple_sequence (operands, nops, regs, &base_reg, &offset))
7037 {
7038 case 1:
25f905c2 7039 strcpy (buf, "ldm%(ia%)\t");
1275b964 7040 break;
7041
7042 case 2:
25f905c2 7043 strcpy (buf, "ldm%(ib%)\t");
1275b964 7044 break;
7045
7046 case 3:
25f905c2 7047 strcpy (buf, "ldm%(da%)\t");
1275b964 7048 break;
7049
7050 case 4:
25f905c2 7051 strcpy (buf, "ldm%(db%)\t");
1275b964 7052 break;
7053
7054 case 5:
7055 if (offset >= 0)
7056 sprintf (buf, "add%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
7057 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],
7058 (long) offset);
7059 else
7060 sprintf (buf, "sub%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
7061 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],
7062 (long) -offset);
7063 output_asm_insn (buf, operands);
7064 base_reg = regs[0];
25f905c2 7065 strcpy (buf, "ldm%(ia%)\t");
1275b964 7066 break;
7067
7068 default:
ed29c566 7069 gcc_unreachable ();
1275b964 7070 }
7071
9e7454d0 7072 sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
1275b964 7073 reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
7074
7075 for (i = 1; i < nops; i++)
7076 sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
7077 reg_names[regs[i]]);
7078
7079 strcat (buf, "}\t%@ phole ldm");
7080
7081 output_asm_insn (buf, operands);
7082 return "";
7083}
7084
7085int
ebd88a36 7086store_multiple_sequence (rtx *operands, int nops, int *regs, int *base,
7087 HOST_WIDE_INT * load_offset)
1275b964 7088{
7089 int unsorted_regs[4];
7090 HOST_WIDE_INT unsorted_offsets[4];
7091 int order[4];
ecd3fcc7 7092 int base_reg = -1;
1275b964 7093 int i;
7094
7095 /* Can only handle 2, 3, or 4 insns at present, though could be easily
7096 extended if required. */
ed29c566 7097 gcc_assert (nops >= 2 && nops <= 4);
1275b964 7098
7099 /* Loop over the operands and check that the memory references are
a361b456 7100 suitable (i.e. immediate offsets from the same base register). At
1275b964 7101 the same time, extract the target register, and the memory
7102 offsets. */
7103 for (i = 0; i < nops; i++)
7104 {
7105 rtx reg;
7106 rtx offset;
7107
6019008a 7108 /* Convert a subreg of a mem into the mem itself. */
7109 if (GET_CODE (operands[nops + i]) == SUBREG)
f2dd364c 7110 operands[nops + i] = alter_subreg (operands + (nops + i));
6019008a 7111
ed29c566 7112 gcc_assert (GET_CODE (operands[nops + i]) == MEM);
1275b964 7113
7114 /* Don't reorder volatile memory references; it doesn't seem worth
7115 looking for the case where the order is ok anyway. */
7116 if (MEM_VOLATILE_P (operands[nops + i]))
7117 return 0;
7118
7119 offset = const0_rtx;
7120
7121 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
7122 || (GET_CODE (reg) == SUBREG
7123 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
7124 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
7125 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
7126 == REG)
7127 || (GET_CODE (reg) == SUBREG
7128 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
7129 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
7130 == CONST_INT)))
7131 {
7132 if (i == 0)
7133 {
bba10fb8 7134 base_reg = REGNO (reg);
1275b964 7135 unsorted_regs[0] = (GET_CODE (operands[i]) == REG
7136 ? REGNO (operands[i])
7137 : REGNO (SUBREG_REG (operands[i])));
7138 order[0] = 0;
7139 }
9e7454d0 7140 else
1275b964 7141 {
66aacf41 7142 if (base_reg != (int) REGNO (reg))
1275b964 7143 /* Not addressed from the same base register. */
7144 return 0;
7145
7146 unsorted_regs[i] = (GET_CODE (operands[i]) == REG
7147 ? REGNO (operands[i])
7148 : REGNO (SUBREG_REG (operands[i])));
7149 if (unsorted_regs[i] < unsorted_regs[order[0]])
7150 order[0] = i;
7151 }
7152
7153 /* If it isn't an integer register, then we can't do this. */
7154 if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14)
7155 return 0;
7156
7157 unsorted_offsets[i] = INTVAL (offset);
7158 }
7159 else
7160 /* Not a suitable memory address. */
7161 return 0;
7162 }
7163
7164 /* All the useful information has now been extracted from the
7165 operands into unsorted_regs and unsorted_offsets; additionally,
7166 order[0] has been set to the lowest numbered register in the
7167 list. Sort the registers into order, and check that the memory
7168 offsets are ascending and adjacent. */
7169
7170 for (i = 1; i < nops; i++)
7171 {
7172 int j;
7173
7174 order[i] = order[i - 1];
7175 for (j = 0; j < nops; j++)
7176 if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
7177 && (order[i] == order[i - 1]
7178 || unsorted_regs[j] < unsorted_regs[order[i]]))
7179 order[i] = j;
7180
7181 /* Have we found a suitable register? if not, one must be used more
7182 than once. */
7183 if (order[i] == order[i - 1])
7184 return 0;
7185
7186 /* Is the memory address adjacent and ascending? */
7187 if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
7188 return 0;
7189 }
7190
7191 if (base)
7192 {
7193 *base = base_reg;
7194
7195 for (i = 0; i < nops; i++)
7196 regs[i] = unsorted_regs[order[i]];
7197
7198 *load_offset = unsorted_offsets[order[0]];
7199 }
7200
7201 if (unsorted_offsets[order[0]] == 0)
7202 return 1; /* stmia */
7203
7204 if (unsorted_offsets[order[0]] == 4)
7205 return 2; /* stmib */
7206
7207 if (unsorted_offsets[order[nops - 1]] == 0)
7208 return 3; /* stmda */
7209
7210 if (unsorted_offsets[order[nops - 1]] == -4)
7211 return 4; /* stmdb */
7212
7213 return 0;
7214}
7215
0bd59681 7216const char *
ebd88a36 7217emit_stm_seq (rtx *operands, int nops)
1275b964 7218{
7219 int regs[4];
7220 int base_reg;
7221 HOST_WIDE_INT offset;
7222 char buf[100];
7223 int i;
7224
7225 switch (store_multiple_sequence (operands, nops, regs, &base_reg, &offset))
7226 {
7227 case 1:
25f905c2 7228 strcpy (buf, "stm%(ia%)\t");
1275b964 7229 break;
7230
7231 case 2:
25f905c2 7232 strcpy (buf, "stm%(ib%)\t");
1275b964 7233 break;
7234
7235 case 3:
25f905c2 7236 strcpy (buf, "stm%(da%)\t");
1275b964 7237 break;
7238
7239 case 4:
25f905c2 7240 strcpy (buf, "stm%(db%)\t");
1275b964 7241 break;
7242
7243 default:
ed29c566 7244 gcc_unreachable ();
1275b964 7245 }
7246
9e7454d0 7247 sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
1275b964 7248 reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
7249
7250 for (i = 1; i < nops; i++)
7251 sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
7252 reg_names[regs[i]]);
7253
7254 strcat (buf, "}\t%@ phole stm");
7255
7256 output_asm_insn (buf, operands);
7257 return "";
7258}
9c08d1fa 7259\f
66aacf41 7260/* Routines for use in generating RTL. */
a12be13c 7261
a690ede2 7262rtx
ebd88a36 7263arm_gen_load_multiple (int base_regno, int count, rtx from, int up,
9580c25f 7264 int write_back, rtx basemem, HOST_WIDE_INT *offsetp)
9c08d1fa 7265{
9580c25f 7266 HOST_WIDE_INT offset = *offsetp;
9c08d1fa 7267 int i = 0, j;
7268 rtx result;
7269 int sign = up ? 1 : -1;
9580c25f 7270 rtx mem, addr;
9c08d1fa 7271
331beb1a 7272 /* XScale has load-store double instructions, but they have stricter
33f88b1c 7273 alignment requirements than load-store multiple, so we cannot
331beb1a 7274 use them.
7275
7276 For XScale ldm requires 2 + NREGS cycles to complete and blocks
7277 the pipeline until completion.
7278
7279 NREGS CYCLES
7280 1 3
7281 2 4
7282 3 5
7283 4 6
7284
7285 An ldr instruction takes 1-3 cycles, but does not block the
7286 pipeline.
7287
7288 NREGS CYCLES
7289 1 1-3
7290 2 2-6
7291 3 3-9
7292 4 4-12
7293
7294 Best case ldr will always win. However, the more ldr instructions
7295 we issue, the less likely we are to be able to schedule them well.
7296 Using ldr instructions also increases code size.
7297
7298 As a compromise, we use ldr for counts of 1 or 2 regs, and ldm
7299 for counts of 3 or 4 regs. */
f8e17552 7300 if (arm_tune_xscale && count <= 2 && ! optimize_size)
331beb1a 7301 {
7302 rtx seq;
9e7454d0 7303
331beb1a 7304 start_sequence ();
9e7454d0 7305
331beb1a 7306 for (i = 0; i < count; i++)
7307 {
9580c25f 7308 addr = plus_constant (from, i * 4 * sign);
7309 mem = adjust_automodify_address (basemem, SImode, addr, offset);
331beb1a 7310 emit_move_insn (gen_rtx_REG (SImode, base_regno + i), mem);
9580c25f 7311 offset += 4 * sign;
331beb1a 7312 }
7313
7314 if (write_back)
9580c25f 7315 {
7316 emit_move_insn (from, plus_constant (from, count * 4 * sign));
7317 *offsetp = offset;
7318 }
331beb1a 7319
31d3e01c 7320 seq = get_insns ();
331beb1a 7321 end_sequence ();
9e7454d0 7322
331beb1a 7323 return seq;
7324 }
7325
76676c8e 7326 result = gen_rtx_PARALLEL (VOIDmode,
dd6d7504 7327 rtvec_alloc (count + (write_back ? 1 : 0)));
9c08d1fa 7328 if (write_back)
a690ede2 7329 {
9c08d1fa 7330 XVECEXP (result, 0, 0)
0083a3b9 7331 = gen_rtx_SET (VOIDmode, from, plus_constant (from, count * 4 * sign));
9c08d1fa 7332 i = 1;
7333 count++;
a690ede2 7334 }
7335
9c08d1fa 7336 for (j = 0; i < count; i++, j++)
a690ede2 7337 {
9580c25f 7338 addr = plus_constant (from, j * 4 * sign);
7339 mem = adjust_automodify_address_nv (basemem, SImode, addr, offset);
76676c8e 7340 XVECEXP (result, 0, i)
7341 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, base_regno + j), mem);
9580c25f 7342 offset += 4 * sign;
a690ede2 7343 }
7344
9580c25f 7345 if (write_back)
7346 *offsetp = offset;
7347
9c08d1fa 7348 return result;
7349}
7350
a690ede2 7351rtx
ebd88a36 7352arm_gen_store_multiple (int base_regno, int count, rtx to, int up,
9580c25f 7353 int write_back, rtx basemem, HOST_WIDE_INT *offsetp)
9c08d1fa 7354{
9580c25f 7355 HOST_WIDE_INT offset = *offsetp;
9c08d1fa 7356 int i = 0, j;
7357 rtx result;
7358 int sign = up ? 1 : -1;
9580c25f 7359 rtx mem, addr;
9c08d1fa 7360
331beb1a 7361 /* See arm_gen_load_multiple for discussion of
7362 the pros/cons of ldm/stm usage for XScale. */
f8e17552 7363 if (arm_tune_xscale && count <= 2 && ! optimize_size)
331beb1a 7364 {
7365 rtx seq;
9e7454d0 7366
331beb1a 7367 start_sequence ();
9e7454d0 7368
331beb1a 7369 for (i = 0; i < count; i++)
7370 {
9580c25f 7371 addr = plus_constant (to, i * 4 * sign);
7372 mem = adjust_automodify_address (basemem, SImode, addr, offset);
331beb1a 7373 emit_move_insn (mem, gen_rtx_REG (SImode, base_regno + i));
9580c25f 7374 offset += 4 * sign;
331beb1a 7375 }
7376
7377 if (write_back)
9580c25f 7378 {
7379 emit_move_insn (to, plus_constant (to, count * 4 * sign));
7380 *offsetp = offset;
7381 }
331beb1a 7382
31d3e01c 7383 seq = get_insns ();
331beb1a 7384 end_sequence ();
9e7454d0 7385
331beb1a 7386 return seq;
7387 }
7388
76676c8e 7389 result = gen_rtx_PARALLEL (VOIDmode,
dd6d7504 7390 rtvec_alloc (count + (write_back ? 1 : 0)));
9c08d1fa 7391 if (write_back)
a690ede2 7392 {
9c08d1fa 7393 XVECEXP (result, 0, 0)
0083a3b9 7394 = gen_rtx_SET (VOIDmode, to,
76676c8e 7395 plus_constant (to, count * 4 * sign));
9c08d1fa 7396 i = 1;
7397 count++;
a690ede2 7398 }
7399
9c08d1fa 7400 for (j = 0; i < count; i++, j++)
a690ede2 7401 {
9580c25f 7402 addr = plus_constant (to, j * 4 * sign);
7403 mem = adjust_automodify_address_nv (basemem, SImode, addr, offset);
76676c8e 7404 XVECEXP (result, 0, i)
7405 = gen_rtx_SET (VOIDmode, mem, gen_rtx_REG (SImode, base_regno + j));
9580c25f 7406 offset += 4 * sign;
a690ede2 7407 }
7408
9580c25f 7409 if (write_back)
7410 *offsetp = offset;
7411
9c08d1fa 7412 return result;
7413}
7414
c29feb68 7415int
008c057d 7416arm_gen_movmemqi (rtx *operands)
c29feb68 7417{
7418 HOST_WIDE_INT in_words_to_go, out_words_to_go, last_bytes;
9580c25f 7419 HOST_WIDE_INT srcoffset, dstoffset;
ecd3fcc7 7420 int i;
9580c25f 7421 rtx src, dst, srcbase, dstbase;
c29feb68 7422 rtx part_bytes_reg = NULL;
6019008a 7423 rtx mem;
c29feb68 7424
7425 if (GET_CODE (operands[2]) != CONST_INT
7426 || GET_CODE (operands[3]) != CONST_INT
7427 || INTVAL (operands[2]) > 64
7428 || INTVAL (operands[3]) & 3)
7429 return 0;
7430
9580c25f 7431 dstbase = operands[0];
7432 srcbase = operands[1];
6019008a 7433
9580c25f 7434 dst = copy_to_mode_reg (SImode, XEXP (dstbase, 0));
7435 src = copy_to_mode_reg (SImode, XEXP (srcbase, 0));
c29feb68 7436
36837fde 7437 in_words_to_go = ARM_NUM_INTS (INTVAL (operands[2]));
c29feb68 7438 out_words_to_go = INTVAL (operands[2]) / 4;
7439 last_bytes = INTVAL (operands[2]) & 3;
9580c25f 7440 dstoffset = srcoffset = 0;
c29feb68 7441
7442 if (out_words_to_go != in_words_to_go && ((in_words_to_go - 1) & 3) != 0)
76676c8e 7443 part_bytes_reg = gen_rtx_REG (SImode, (in_words_to_go - 1) & 3);
c29feb68 7444
7445 for (i = 0; in_words_to_go >= 2; i+=4)
7446 {
9480e6c7 7447 if (in_words_to_go > 4)
6019008a 7448 emit_insn (arm_gen_load_multiple (0, 4, src, TRUE, TRUE,
9580c25f 7449 srcbase, &srcoffset));
9480e6c7 7450 else
9e7454d0 7451 emit_insn (arm_gen_load_multiple (0, in_words_to_go, src, TRUE,
9580c25f 7452 FALSE, srcbase, &srcoffset));
9480e6c7 7453
c29feb68 7454 if (out_words_to_go)
7455 {
9480e6c7 7456 if (out_words_to_go > 4)
6019008a 7457 emit_insn (arm_gen_store_multiple (0, 4, dst, TRUE, TRUE,
9580c25f 7458 dstbase, &dstoffset));
9480e6c7 7459 else if (out_words_to_go != 1)
7460 emit_insn (arm_gen_store_multiple (0, out_words_to_go,
9e7454d0 7461 dst, TRUE,
9480e6c7 7462 (last_bytes == 0
6019008a 7463 ? FALSE : TRUE),
9580c25f 7464 dstbase, &dstoffset));
c29feb68 7465 else
7466 {
9580c25f 7467 mem = adjust_automodify_address (dstbase, SImode, dst, dstoffset);
76676c8e 7468 emit_move_insn (mem, gen_rtx_REG (SImode, 0));
9480e6c7 7469 if (last_bytes != 0)
9580c25f 7470 {
7471 emit_insn (gen_addsi3 (dst, dst, GEN_INT (4)));
7472 dstoffset += 4;
7473 }
c29feb68 7474 }
7475 }
7476
7477 in_words_to_go -= in_words_to_go < 4 ? in_words_to_go : 4;
7478 out_words_to_go -= out_words_to_go < 4 ? out_words_to_go : 4;
7479 }
7480
7481 /* OUT_WORDS_TO_GO will be zero here if there are byte stores to do. */
7482 if (out_words_to_go)
bba10fb8 7483 {
7484 rtx sreg;
9e7454d0 7485
9580c25f 7486 mem = adjust_automodify_address (srcbase, SImode, src, srcoffset);
7487 sreg = copy_to_reg (mem);
7488
7489 mem = adjust_automodify_address (dstbase, SImode, dst, dstoffset);
bba10fb8 7490 emit_move_insn (mem, sreg);
bba10fb8 7491 in_words_to_go--;
9e7454d0 7492
ed29c566 7493 gcc_assert (!in_words_to_go); /* Sanity check */
bba10fb8 7494 }
c29feb68 7495
7496 if (in_words_to_go)
7497 {
ed29c566 7498 gcc_assert (in_words_to_go > 0);
c29feb68 7499
9580c25f 7500 mem = adjust_automodify_address (srcbase, SImode, src, srcoffset);
6019008a 7501 part_bytes_reg = copy_to_mode_reg (SImode, mem);
c29feb68 7502 }
7503
ed29c566 7504 gcc_assert (!last_bytes || part_bytes_reg);
cffb2a26 7505
c29feb68 7506 if (BYTES_BIG_ENDIAN && last_bytes)
7507 {
7508 rtx tmp = gen_reg_rtx (SImode);
7509
66aacf41 7510 /* The bytes we want are in the top end of the word. */
411b0ddb 7511 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg,
7512 GEN_INT (8 * (4 - last_bytes))));
c29feb68 7513 part_bytes_reg = tmp;
9e7454d0 7514
c29feb68 7515 while (last_bytes)
7516 {
9580c25f 7517 mem = adjust_automodify_address (dstbase, QImode,
7518 plus_constant (dst, last_bytes - 1),
7519 dstoffset + last_bytes - 1);
9e8503e6 7520 emit_move_insn (mem, gen_lowpart (QImode, part_bytes_reg));
7521
c29feb68 7522 if (--last_bytes)
7523 {
7524 tmp = gen_reg_rtx (SImode);
7525 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (8)));
7526 part_bytes_reg = tmp;
7527 }
7528 }
9e7454d0 7529
c29feb68 7530 }
7531 else
7532 {
cffb2a26 7533 if (last_bytes > 1)
c29feb68 7534 {
9580c25f 7535 mem = adjust_automodify_address (dstbase, HImode, dst, dstoffset);
9e8503e6 7536 emit_move_insn (mem, gen_lowpart (HImode, part_bytes_reg));
cffb2a26 7537 last_bytes -= 2;
7538 if (last_bytes)
c29feb68 7539 {
7540 rtx tmp = gen_reg_rtx (SImode);
bcd9bd66 7541 emit_insn (gen_addsi3 (dst, dst, const2_rtx));
cffb2a26 7542 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (16)));
c29feb68 7543 part_bytes_reg = tmp;
9580c25f 7544 dstoffset += 2;
c29feb68 7545 }
7546 }
9e7454d0 7547
cffb2a26 7548 if (last_bytes)
7549 {
9580c25f 7550 mem = adjust_automodify_address (dstbase, QImode, dst, dstoffset);
9e8503e6 7551 emit_move_insn (mem, gen_lowpart (QImode, part_bytes_reg));
cffb2a26 7552 }
c29feb68 7553 }
7554
7555 return 1;
7556}
7557
3c5afce6 7558/* Select a dominance comparison mode if possible for a test of the general
7559 form (OP (COND_OR (X) (Y)) (const_int 0)). We support three forms.
9e7454d0 7560 COND_OR == DOM_CC_X_AND_Y => (X && Y)
3c5afce6 7561 COND_OR == DOM_CC_NX_OR_Y => ((! X) || Y)
9e7454d0 7562 COND_OR == DOM_CC_X_OR_Y => (X || Y)
3c5afce6 7563 In all cases OP will be either EQ or NE, but we don't need to know which
9e7454d0 7564 here. If we are unable to support a dominance comparison we return
3c5afce6 7565 CC mode. This will then fail to match for the RTL expressions that
7566 generate this call. */
3c5afce6 7567enum machine_mode
ebd88a36 7568arm_select_dominance_cc_mode (rtx x, rtx y, HOST_WIDE_INT cond_or)
1275b964 7569{
7570 enum rtx_code cond1, cond2;
7571 int swapped = 0;
7572
7573 /* Currently we will probably get the wrong result if the individual
7574 comparisons are not simple. This also ensures that it is safe to
ad87de1e 7575 reverse a comparison if necessary. */
1275b964 7576 if ((arm_select_cc_mode (cond1 = GET_CODE (x), XEXP (x, 0), XEXP (x, 1))
7577 != CCmode)
7578 || (arm_select_cc_mode (cond2 = GET_CODE (y), XEXP (y, 0), XEXP (y, 1))
7579 != CCmode))
7580 return CCmode;
7581
f6c53574 7582 /* The if_then_else variant of this tests the second condition if the
7583 first passes, but is true if the first fails. Reverse the first
7584 condition to get a true "inclusive-or" expression. */
3c5afce6 7585 if (cond_or == DOM_CC_NX_OR_Y)
1275b964 7586 cond1 = reverse_condition (cond1);
7587
7588 /* If the comparisons are not equal, and one doesn't dominate the other,
7589 then we can't do this. */
9e7454d0 7590 if (cond1 != cond2
215b30b3 7591 && !comparison_dominates_p (cond1, cond2)
7592 && (swapped = 1, !comparison_dominates_p (cond2, cond1)))
1275b964 7593 return CCmode;
7594
7595 if (swapped)
7596 {
7597 enum rtx_code temp = cond1;
7598 cond1 = cond2;
7599 cond2 = temp;
7600 }
7601
7602 switch (cond1)
7603 {
7604 case EQ:
ed29c566 7605 if (cond_or == DOM_CC_X_AND_Y)
1275b964 7606 return CC_DEQmode;
7607
7608 switch (cond2)
7609 {
ed29c566 7610 case EQ: return CC_DEQmode;
1275b964 7611 case LE: return CC_DLEmode;
7612 case LEU: return CC_DLEUmode;
7613 case GE: return CC_DGEmode;
7614 case GEU: return CC_DGEUmode;
ed29c566 7615 default: gcc_unreachable ();
1275b964 7616 }
7617
1275b964 7618 case LT:
ed29c566 7619 if (cond_or == DOM_CC_X_AND_Y)
1275b964 7620 return CC_DLTmode;
a60f1840 7621
ed29c566 7622 switch (cond2)
7623 {
7624 case LT:
7625 return CC_DLTmode;
7626 case LE:
7627 return CC_DLEmode;
7628 case NE:
7629 return CC_DNEmode;
7630 default:
7631 gcc_unreachable ();
7632 }
1275b964 7633
7634 case GT:
ed29c566 7635 if (cond_or == DOM_CC_X_AND_Y)
1275b964 7636 return CC_DGTmode;
ed29c566 7637
7638 switch (cond2)
7639 {
7640 case GT:
7641 return CC_DGTmode;
7642 case GE:
7643 return CC_DGEmode;
7644 case NE:
7645 return CC_DNEmode;
7646 default:
7647 gcc_unreachable ();
7648 }
9e7454d0 7649
1275b964 7650 case LTU:
ed29c566 7651 if (cond_or == DOM_CC_X_AND_Y)
1275b964 7652 return CC_DLTUmode;
ed29c566 7653
7654 switch (cond2)
7655 {
7656 case LTU:
7657 return CC_DLTUmode;
7658 case LEU:
7659 return CC_DLEUmode;
7660 case NE:
7661 return CC_DNEmode;
7662 default:
7663 gcc_unreachable ();
7664 }
1275b964 7665
7666 case GTU:
ed29c566 7667 if (cond_or == DOM_CC_X_AND_Y)
1275b964 7668 return CC_DGTUmode;
a60f1840 7669
ed29c566 7670 switch (cond2)
7671 {
7672 case GTU:
7673 return CC_DGTUmode;
7674 case GEU:
7675 return CC_DGEUmode;
7676 case NE:
7677 return CC_DNEmode;
7678 default:
7679 gcc_unreachable ();
7680 }
1275b964 7681
7682 /* The remaining cases only occur when both comparisons are the
7683 same. */
7684 case NE:
ed29c566 7685 gcc_assert (cond1 == cond2);
1275b964 7686 return CC_DNEmode;
7687
7688 case LE:
ed29c566 7689 gcc_assert (cond1 == cond2);
1275b964 7690 return CC_DLEmode;
7691
7692 case GE:
ed29c566 7693 gcc_assert (cond1 == cond2);
1275b964 7694 return CC_DGEmode;
7695
7696 case LEU:
ed29c566 7697 gcc_assert (cond1 == cond2);
1275b964 7698 return CC_DLEUmode;
7699
7700 case GEU:
ed29c566 7701 gcc_assert (cond1 == cond2);
1275b964 7702 return CC_DGEUmode;
ecd3fcc7 7703
7704 default:
ed29c566 7705 gcc_unreachable ();
1275b964 7706 }
1275b964 7707}
7708
7709enum machine_mode
ebd88a36 7710arm_select_cc_mode (enum rtx_code op, rtx x, rtx y)
1275b964 7711{
7712 /* All floating point compares return CCFP if it is an equality
7713 comparison, and CCFPE otherwise. */
7714 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
f3d87a93 7715 {
7716 switch (op)
7717 {
7718 case EQ:
7719 case NE:
7720 case UNORDERED:
7721 case ORDERED:
7722 case UNLT:
7723 case UNLE:
7724 case UNGT:
7725 case UNGE:
7726 case UNEQ:
7727 case LTGT:
7728 return CCFPmode;
7729
7730 case LT:
7731 case LE:
7732 case GT:
7733 case GE:
a2cd141b 7734 if (TARGET_HARD_FLOAT && TARGET_MAVERICK)
7d57ec45 7735 return CCFPmode;
f3d87a93 7736 return CCFPEmode;
7737
7738 default:
ed29c566 7739 gcc_unreachable ();
f3d87a93 7740 }
7741 }
9e7454d0 7742
1275b964 7743 /* A compare with a shifted operand. Because of canonicalization, the
7744 comparison will have to be swapped when we emit the assembler. */
7745 if (GET_MODE (y) == SImode && GET_CODE (y) == REG
7746 && (GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
7747 || GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ROTATE
7748 || GET_CODE (x) == ROTATERT))
7749 return CC_SWPmode;
7750
4c9d8377 7751 /* This operation is performed swapped, but since we only rely on the Z
7752 flag we don't need an additional mode. */
7753 if (GET_MODE (y) == SImode && REG_P (y)
7754 && GET_CODE (x) == NEG
7755 && (op == EQ || op == NE))
7756 return CC_Zmode;
7757
9e7454d0 7758 /* This is a special case that is used by combine to allow a
ad87de1e 7759 comparison of a shifted byte load to be split into a zero-extend
1275b964 7760 followed by a comparison of the shifted integer (only valid for
ad87de1e 7761 equalities and unsigned inequalities). */
1275b964 7762 if (GET_MODE (x) == SImode
7763 && GET_CODE (x) == ASHIFT
7764 && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 24
7765 && GET_CODE (XEXP (x, 0)) == SUBREG
7766 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == MEM
7767 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == QImode
7768 && (op == EQ || op == NE
7769 || op == GEU || op == GTU || op == LTU || op == LEU)
7770 && GET_CODE (y) == CONST_INT)
7771 return CC_Zmode;
7772
f6c53574 7773 /* A construct for a conditional compare, if the false arm contains
7774 0, then both conditions must be true, otherwise either condition
7775 must be true. Not all conditions are possible, so CCmode is
7776 returned if it can't be done. */
7777 if (GET_CODE (x) == IF_THEN_ELSE
7778 && (XEXP (x, 2) == const0_rtx
7779 || XEXP (x, 2) == const1_rtx)
6720e96c 7780 && COMPARISON_P (XEXP (x, 0))
7781 && COMPARISON_P (XEXP (x, 1)))
9e7454d0 7782 return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
3c5afce6 7783 INTVAL (XEXP (x, 2)));
f6c53574 7784
7785 /* Alternate canonicalizations of the above. These are somewhat cleaner. */
7786 if (GET_CODE (x) == AND
6720e96c 7787 && COMPARISON_P (XEXP (x, 0))
7788 && COMPARISON_P (XEXP (x, 1)))
3c5afce6 7789 return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
7790 DOM_CC_X_AND_Y);
f6c53574 7791
7792 if (GET_CODE (x) == IOR
6720e96c 7793 && COMPARISON_P (XEXP (x, 0))
7794 && COMPARISON_P (XEXP (x, 1)))
3c5afce6 7795 return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
7796 DOM_CC_X_OR_Y);
f6c53574 7797
58d6528b 7798 /* An operation (on Thumb) where we want to test for a single bit.
7799 This is done by shifting that bit up into the top bit of a
7800 scratch register; we can then branch on the sign bit. */
25f905c2 7801 if (TARGET_THUMB1
58d6528b 7802 && GET_MODE (x) == SImode
7803 && (op == EQ || op == NE)
86efa74d 7804 && GET_CODE (x) == ZERO_EXTRACT
7805 && XEXP (x, 1) == const1_rtx)
58d6528b 7806 return CC_Nmode;
7807
1275b964 7808 /* An operation that sets the condition codes as a side-effect, the
7809 V flag is not set correctly, so we can only use comparisons where
7810 this doesn't matter. (For LT and GE we can use "mi" and "pl"
58d6528b 7811 instead.) */
25f905c2 7812 /* ??? Does the ZERO_EXTRACT case really apply to thumb2? */
1275b964 7813 if (GET_MODE (x) == SImode
7814 && y == const0_rtx
7815 && (op == EQ || op == NE || op == LT || op == GE)
7816 && (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS
7817 || GET_CODE (x) == AND || GET_CODE (x) == IOR
7818 || GET_CODE (x) == XOR || GET_CODE (x) == MULT
7819 || GET_CODE (x) == NOT || GET_CODE (x) == NEG
7820 || GET_CODE (x) == LSHIFTRT
7821 || GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
58d6528b 7822 || GET_CODE (x) == ROTATERT
25f905c2 7823 || (TARGET_32BIT && GET_CODE (x) == ZERO_EXTRACT)))
1275b964 7824 return CC_NOOVmode;
7825
1275b964 7826 if (GET_MODE (x) == QImode && (op == EQ || op == NE))
7827 return CC_Zmode;
7828
9480e6c7 7829 if (GET_MODE (x) == SImode && (op == LTU || op == GEU)
7830 && GET_CODE (x) == PLUS
7831 && (rtx_equal_p (XEXP (x, 0), y) || rtx_equal_p (XEXP (x, 1), y)))
7832 return CC_Cmode;
7833
1275b964 7834 return CCmode;
7835}
7836
9c08d1fa 7837/* X and Y are two things to compare using CODE. Emit the compare insn and
7838 return the rtx for register 0 in the proper mode. FP means this is a
7839 floating point compare: I don't think that it is needed on the arm. */
9c08d1fa 7840rtx
ebd88a36 7841arm_gen_compare_reg (enum rtx_code code, rtx x, rtx y)
9c08d1fa 7842{
7843 enum machine_mode mode = SELECT_CC_MODE (code, x, y);
cffb2a26 7844 rtx cc_reg = gen_rtx_REG (mode, CC_REGNUM);
9c08d1fa 7845
0083a3b9 7846 emit_set_insn (cc_reg, gen_rtx_COMPARE (mode, x, y));
9c08d1fa 7847
7848 return cc_reg;
7849}
7850
68121397 7851/* Generate a sequence of insns that will generate the correct return
7852 address mask depending on the physical architecture that the program
7853 is running on. */
68121397 7854rtx
ebd88a36 7855arm_gen_return_addr_mask (void)
68121397 7856{
7857 rtx reg = gen_reg_rtx (Pmode);
7858
7859 emit_insn (gen_return_addr_mask (reg));
7860 return reg;
7861}
7862
91fd5a8d 7863void
ebd88a36 7864arm_reload_in_hi (rtx *operands)
91fd5a8d 7865{
bc5c7e08 7866 rtx ref = operands[1];
7867 rtx base, scratch;
7868 HOST_WIDE_INT offset = 0;
7869
7870 if (GET_CODE (ref) == SUBREG)
7871 {
701e46d0 7872 offset = SUBREG_BYTE (ref);
bc5c7e08 7873 ref = SUBREG_REG (ref);
7874 }
7875
7876 if (GET_CODE (ref) == REG)
7877 {
7878 /* We have a pseudo which has been spilt onto the stack; there
7879 are two cases here: the first where there is a simple
7880 stack-slot replacement and a second where the stack-slot is
7881 out of range, or is used as a subreg. */
7882 if (reg_equiv_mem[REGNO (ref)])
7883 {
7884 ref = reg_equiv_mem[REGNO (ref)];
7885 base = find_replacement (&XEXP (ref, 0));
7886 }
7887 else
66aacf41 7888 /* The slot is out of range, or was dressed up in a SUBREG. */
bc5c7e08 7889 base = reg_equiv_address[REGNO (ref)];
7890 }
7891 else
7892 base = find_replacement (&XEXP (ref, 0));
91fd5a8d 7893
997d68fe 7894 /* Handle the case where the address is too complex to be offset by 1. */
7895 if (GET_CODE (base) == MINUS
7896 || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT))
7897 {
bc5c7e08 7898 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
997d68fe 7899
0083a3b9 7900 emit_set_insn (base_plus, base);
997d68fe 7901 base = base_plus;
7902 }
bc5c7e08 7903 else if (GET_CODE (base) == PLUS)
7904 {
66aacf41 7905 /* The addend must be CONST_INT, or we would have dealt with it above. */
bc5c7e08 7906 HOST_WIDE_INT hi, lo;
7907
7908 offset += INTVAL (XEXP (base, 1));
7909 base = XEXP (base, 0);
7910
66aacf41 7911 /* Rework the address into a legal sequence of insns. */
bc5c7e08 7912 /* Valid range for lo is -4095 -> 4095 */
7913 lo = (offset >= 0
7914 ? (offset & 0xfff)
7915 : -((-offset) & 0xfff));
7916
7917 /* Corner case, if lo is the max offset then we would be out of range
7918 once we have added the additional 1 below, so bump the msb into the
7919 pre-loading insn(s). */
7920 if (lo == 4095)
7921 lo &= 0x7ff;
7922
35cea10c 7923 hi = ((((offset - lo) & (HOST_WIDE_INT) 0xffffffff)
7924 ^ (HOST_WIDE_INT) 0x80000000)
7925 - (HOST_WIDE_INT) 0x80000000);
bc5c7e08 7926
ed29c566 7927 gcc_assert (hi + lo == offset);
bc5c7e08 7928
7929 if (hi != 0)
7930 {
7931 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
7932
7933 /* Get the base address; addsi3 knows how to handle constants
66aacf41 7934 that require more than one insn. */
bc5c7e08 7935 emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi)));
7936 base = base_plus;
7937 offset = lo;
7938 }
7939 }
997d68fe 7940
dfb47981 7941 /* Operands[2] may overlap operands[0] (though it won't overlap
7942 operands[1]), that's why we asked for a DImode reg -- so we can
7943 use the bit that does not overlap. */
7944 if (REGNO (operands[2]) == REGNO (operands[0]))
7945 scratch = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
7946 else
7947 scratch = gen_rtx_REG (SImode, REGNO (operands[2]));
7948
bc5c7e08 7949 emit_insn (gen_zero_extendqisi2 (scratch,
7950 gen_rtx_MEM (QImode,
7951 plus_constant (base,
7952 offset))));
76676c8e 7953 emit_insn (gen_zero_extendqisi2 (gen_rtx_SUBREG (SImode, operands[0], 0),
9e7454d0 7954 gen_rtx_MEM (QImode,
bc5c7e08 7955 plus_constant (base,
7956 offset + 1))));
215b30b3 7957 if (!BYTES_BIG_ENDIAN)
0083a3b9 7958 emit_set_insn (gen_rtx_SUBREG (SImode, operands[0], 0),
7959 gen_rtx_IOR (SImode,
7960 gen_rtx_ASHIFT
7961 (SImode,
7962 gen_rtx_SUBREG (SImode, operands[0], 0),
7963 GEN_INT (8)),
7964 scratch));
91fd5a8d 7965 else
0083a3b9 7966 emit_set_insn (gen_rtx_SUBREG (SImode, operands[0], 0),
7967 gen_rtx_IOR (SImode,
7968 gen_rtx_ASHIFT (SImode, scratch,
7969 GEN_INT (8)),
7970 gen_rtx_SUBREG (SImode, operands[0], 0)));
91fd5a8d 7971}
7972
5bd751ff 7973/* Handle storing a half-word to memory during reload by synthesizing as two
bc5c7e08 7974 byte stores. Take care not to clobber the input values until after we
7975 have moved them somewhere safe. This code assumes that if the DImode
7976 scratch in operands[2] overlaps either the input value or output address
7977 in some way, then that value must die in this insn (we absolutely need
7978 two scratch registers for some corner cases). */
a690ede2 7979void
ebd88a36 7980arm_reload_out_hi (rtx *operands)
9c1b36a9 7981{
bc5c7e08 7982 rtx ref = operands[0];
7983 rtx outval = operands[1];
7984 rtx base, scratch;
7985 HOST_WIDE_INT offset = 0;
7986
7987 if (GET_CODE (ref) == SUBREG)
7988 {
701e46d0 7989 offset = SUBREG_BYTE (ref);
bc5c7e08 7990 ref = SUBREG_REG (ref);
7991 }
7992
bc5c7e08 7993 if (GET_CODE (ref) == REG)
7994 {
7995 /* We have a pseudo which has been spilt onto the stack; there
7996 are two cases here: the first where there is a simple
7997 stack-slot replacement and a second where the stack-slot is
7998 out of range, or is used as a subreg. */
7999 if (reg_equiv_mem[REGNO (ref)])
8000 {
8001 ref = reg_equiv_mem[REGNO (ref)];
8002 base = find_replacement (&XEXP (ref, 0));
8003 }
8004 else
66aacf41 8005 /* The slot is out of range, or was dressed up in a SUBREG. */
bc5c7e08 8006 base = reg_equiv_address[REGNO (ref)];
8007 }
8008 else
8009 base = find_replacement (&XEXP (ref, 0));
8010
8011 scratch = gen_rtx_REG (SImode, REGNO (operands[2]));
8012
8013 /* Handle the case where the address is too complex to be offset by 1. */
8014 if (GET_CODE (base) == MINUS
8015 || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT))
8016 {
8017 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
8018
8019 /* Be careful not to destroy OUTVAL. */
8020 if (reg_overlap_mentioned_p (base_plus, outval))
8021 {
8022 /* Updating base_plus might destroy outval, see if we can
8023 swap the scratch and base_plus. */
215b30b3 8024 if (!reg_overlap_mentioned_p (scratch, outval))
bc5c7e08 8025 {
8026 rtx tmp = scratch;
8027 scratch = base_plus;
8028 base_plus = tmp;
8029 }
8030 else
8031 {
8032 rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2]));
8033
8034 /* Be conservative and copy OUTVAL into the scratch now,
8035 this should only be necessary if outval is a subreg
8036 of something larger than a word. */
8037 /* XXX Might this clobber base? I can't see how it can,
8038 since scratch is known to overlap with OUTVAL, and
8039 must be wider than a word. */
8040 emit_insn (gen_movhi (scratch_hi, outval));
8041 outval = scratch_hi;
8042 }
8043 }
8044
0083a3b9 8045 emit_set_insn (base_plus, base);
bc5c7e08 8046 base = base_plus;
8047 }
8048 else if (GET_CODE (base) == PLUS)
8049 {
66aacf41 8050 /* The addend must be CONST_INT, or we would have dealt with it above. */
bc5c7e08 8051 HOST_WIDE_INT hi, lo;
8052
8053 offset += INTVAL (XEXP (base, 1));
8054 base = XEXP (base, 0);
8055
66aacf41 8056 /* Rework the address into a legal sequence of insns. */
bc5c7e08 8057 /* Valid range for lo is -4095 -> 4095 */
8058 lo = (offset >= 0
8059 ? (offset & 0xfff)
8060 : -((-offset) & 0xfff));
8061
8062 /* Corner case, if lo is the max offset then we would be out of range
8063 once we have added the additional 1 below, so bump the msb into the
8064 pre-loading insn(s). */
8065 if (lo == 4095)
8066 lo &= 0x7ff;
8067
35cea10c 8068 hi = ((((offset - lo) & (HOST_WIDE_INT) 0xffffffff)
8069 ^ (HOST_WIDE_INT) 0x80000000)
8070 - (HOST_WIDE_INT) 0x80000000);
bc5c7e08 8071
ed29c566 8072 gcc_assert (hi + lo == offset);
bc5c7e08 8073
8074 if (hi != 0)
8075 {
8076 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
8077
8078 /* Be careful not to destroy OUTVAL. */
8079 if (reg_overlap_mentioned_p (base_plus, outval))
8080 {
8081 /* Updating base_plus might destroy outval, see if we
8082 can swap the scratch and base_plus. */
215b30b3 8083 if (!reg_overlap_mentioned_p (scratch, outval))
bc5c7e08 8084 {
8085 rtx tmp = scratch;
8086 scratch = base_plus;
8087 base_plus = tmp;
8088 }
8089 else
8090 {
8091 rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2]));
8092
8093 /* Be conservative and copy outval into scratch now,
8094 this should only be necessary if outval is a
8095 subreg of something larger than a word. */
8096 /* XXX Might this clobber base? I can't see how it
8097 can, since scratch is known to overlap with
8098 outval. */
8099 emit_insn (gen_movhi (scratch_hi, outval));
8100 outval = scratch_hi;
8101 }
8102 }
8103
8104 /* Get the base address; addsi3 knows how to handle constants
66aacf41 8105 that require more than one insn. */
bc5c7e08 8106 emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi)));
8107 base = base_plus;
8108 offset = lo;
8109 }
8110 }
9c1b36a9 8111
51d172bd 8112 if (BYTES_BIG_ENDIAN)
8113 {
9e7454d0 8114 emit_insn (gen_movqi (gen_rtx_MEM (QImode,
bc5c7e08 8115 plus_constant (base, offset + 1)),
9e8503e6 8116 gen_lowpart (QImode, outval)));
bc5c7e08 8117 emit_insn (gen_lshrsi3 (scratch,
8118 gen_rtx_SUBREG (SImode, outval, 0),
51d172bd 8119 GEN_INT (8)));
bc5c7e08 8120 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)),
9e8503e6 8121 gen_lowpart (QImode, scratch)));
51d172bd 8122 }
8123 else
8124 {
bc5c7e08 8125 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)),
9e8503e6 8126 gen_lowpart (QImode, outval)));
bc5c7e08 8127 emit_insn (gen_lshrsi3 (scratch,
8128 gen_rtx_SUBREG (SImode, outval, 0),
51d172bd 8129 GEN_INT (8)));
bc5c7e08 8130 emit_insn (gen_movqi (gen_rtx_MEM (QImode,
8131 plus_constant (base, offset + 1)),
9e8503e6 8132 gen_lowpart (QImode, scratch)));
51d172bd 8133 }
9c1b36a9 8134}
46b5d878 8135
8136/* Return true if a type must be passed in memory. For AAPCS, small aggregates
8137 (padded to the size of a word) should be passed in a register. */
8138
8139static bool
8140arm_must_pass_in_stack (enum machine_mode mode, tree type)
8141{
8142 if (TARGET_AAPCS_BASED)
8143 return must_pass_in_stack_var_size (mode, type);
8144 else
8145 return must_pass_in_stack_var_size_or_pad (mode, type);
8146}
8147
8148
8149/* For use by FUNCTION_ARG_PADDING (MODE, TYPE).
8150 Return true if an argument passed on the stack should be padded upwards,
a5558ca7 8151 i.e. if the least-significant byte has useful data.
8152 For legacy APCS ABIs we use the default. For AAPCS based ABIs small
8153 aggregate types are placed in the lowest memory address. */
46b5d878 8154
8155bool
8156arm_pad_arg_upward (enum machine_mode mode, tree type)
8157{
8158 if (!TARGET_AAPCS_BASED)
a5558ca7 8159 return DEFAULT_FUNCTION_ARG_PADDING(mode, type) == upward;
46b5d878 8160
8161 if (type && BYTES_BIG_ENDIAN && INTEGRAL_TYPE_P (type))
8162 return false;
8163
8164 return true;
8165}
8166
8167
8168/* Similarly, for use by BLOCK_REG_PADDING (MODE, TYPE, FIRST).
8169 For non-AAPCS, return !BYTES_BIG_ENDIAN if the least significant
8170 byte of the register has useful data, and return the opposite if the
8171 most significant byte does.
8172 For AAPCS, small aggregates and small complex types are always padded
8173 upwards. */
8174
8175bool
8176arm_pad_reg_upward (enum machine_mode mode ATTRIBUTE_UNUSED,
8177 tree type, int first ATTRIBUTE_UNUSED)
8178{
8179 if (TARGET_AAPCS_BASED
8180 && BYTES_BIG_ENDIAN
8181 && (AGGREGATE_TYPE_P (type) || TREE_CODE (type) == COMPLEX_TYPE)
8182 && int_size_in_bytes (type) <= 4)
8183 return true;
8184
8185 /* Otherwise, use default padding. */
8186 return !BYTES_BIG_ENDIAN;
8187}
8188
64266206 8189\f
cffb2a26 8190/* Print a symbolic form of X to the debug file, F. */
8191static void
ebd88a36 8192arm_print_value (FILE *f, rtx x)
cffb2a26 8193{
8194 switch (GET_CODE (x))
8195 {
8196 case CONST_INT:
8197 fprintf (f, HOST_WIDE_INT_PRINT_HEX, INTVAL (x));
8198 return;
8199
8200 case CONST_DOUBLE:
8201 fprintf (f, "<0x%lx,0x%lx>", (long)XWINT (x, 2), (long)XWINT (x, 3));
8202 return;
8203
755eb2b4 8204 case CONST_VECTOR:
8205 {
8206 int i;
8207
8208 fprintf (f, "<");
8209 for (i = 0; i < CONST_VECTOR_NUNITS (x); i++)
8210 {
8211 fprintf (f, HOST_WIDE_INT_PRINT_HEX, INTVAL (CONST_VECTOR_ELT (x, i)));
8212 if (i < (CONST_VECTOR_NUNITS (x) - 1))
8213 fputc (',', f);
8214 }
8215 fprintf (f, ">");
8216 }
8217 return;
8218
cffb2a26 8219 case CONST_STRING:
8220 fprintf (f, "\"%s\"", XSTR (x, 0));
8221 return;
8222
8223 case SYMBOL_REF:
8224 fprintf (f, "`%s'", XSTR (x, 0));
8225 return;
8226
8227 case LABEL_REF:
8228 fprintf (f, "L%d", INSN_UID (XEXP (x, 0)));
8229 return;
8230
8231 case CONST:
8232 arm_print_value (f, XEXP (x, 0));
8233 return;
8234
8235 case PLUS:
8236 arm_print_value (f, XEXP (x, 0));
8237 fprintf (f, "+");
8238 arm_print_value (f, XEXP (x, 1));
8239 return;
8240
8241 case PC:
8242 fprintf (f, "pc");
8243 return;
8244
8245 default:
8246 fprintf (f, "????");
8247 return;
8248 }
8249}
8250\f
64266206 8251/* Routines for manipulation of the constant pool. */
64266206 8252
56d27660 8253/* Arm instructions cannot load a large constant directly into a
8254 register; they have to come from a pc relative load. The constant
8255 must therefore be placed in the addressable range of the pc
8256 relative load. Depending on the precise pc relative load
8257 instruction the range is somewhere between 256 bytes and 4k. This
8258 means that we often have to dump a constant inside a function, and
64266206 8259 generate code to branch around it.
8260
56d27660 8261 It is important to minimize this, since the branches will slow
8262 things down and make the code larger.
64266206 8263
56d27660 8264 Normally we can hide the table after an existing unconditional
8265 branch so that there is no interruption of the flow, but in the
8266 worst case the code looks like this:
64266206 8267
8268 ldr rn, L1
56d27660 8269 ...
64266206 8270 b L2
8271 align
8272 L1: .long value
8273 L2:
56d27660 8274 ...
64266206 8275
64266206 8276 ldr rn, L3
56d27660 8277 ...
64266206 8278 b L4
8279 align
64266206 8280 L3: .long value
8281 L4:
56d27660 8282 ...
8283
8284 We fix this by performing a scan after scheduling, which notices
8285 which instructions need to have their operands fetched from the
8286 constant table and builds the table.
8287
8288 The algorithm starts by building a table of all the constants that
8289 need fixing up and all the natural barriers in the function (places
8290 where a constant table can be dropped without breaking the flow).
8291 For each fixup we note how far the pc-relative replacement will be
8292 able to reach and the offset of the instruction into the function.
8293
8294 Having built the table we then group the fixes together to form
8295 tables that are as large as possible (subject to addressing
8296 constraints) and emit each table of constants after the last
8297 barrier that is within range of all the instructions in the group.
8298 If a group does not contain a barrier, then we forcibly create one
8299 by inserting a jump instruction into the flow. Once the table has
8300 been inserted, the insns are then modified to reference the
8301 relevant entry in the pool.
8302
66aacf41 8303 Possible enhancements to the algorithm (not implemented) are:
56d27660 8304
cffb2a26 8305 1) For some processors and object formats, there may be benefit in
56d27660 8306 aligning the pools to the start of cache lines; this alignment
8307 would need to be taken into account when calculating addressability
66aacf41 8308 of a pool. */
64266206 8309
cffb2a26 8310/* These typedefs are located at the start of this file, so that
8311 they can be used in the prototypes there. This comment is to
8312 remind readers of that fact so that the following structures
8313 can be understood more easily.
8314
8315 typedef struct minipool_node Mnode;
8316 typedef struct minipool_fixup Mfix; */
8317
8318struct minipool_node
8319{
8320 /* Doubly linked chain of entries. */
8321 Mnode * next;
8322 Mnode * prev;
8323 /* The maximum offset into the code that this entry can be placed. While
8324 pushing fixes for forward references, all entries are sorted in order
8325 of increasing max_address. */
8326 HOST_WIDE_INT max_address;
45981c0a 8327 /* Similarly for an entry inserted for a backwards ref. */
cffb2a26 8328 HOST_WIDE_INT min_address;
8329 /* The number of fixes referencing this entry. This can become zero
8330 if we "unpush" an entry. In this case we ignore the entry when we
8331 come to emit the code. */
8332 int refcount;
8333 /* The offset from the start of the minipool. */
8334 HOST_WIDE_INT offset;
8335 /* The value in table. */
8336 rtx value;
8337 /* The mode of value. */
8338 enum machine_mode mode;
755eb2b4 8339 /* The size of the value. With iWMMXt enabled
8340 sizes > 4 also imply an alignment of 8-bytes. */
cffb2a26 8341 int fix_size;
8342};
8343
8344struct minipool_fixup
64266206 8345{
cffb2a26 8346 Mfix * next;
8347 rtx insn;
8348 HOST_WIDE_INT address;
8349 rtx * loc;
8350 enum machine_mode mode;
8351 int fix_size;
8352 rtx value;
8353 Mnode * minipool;
8354 HOST_WIDE_INT forwards;
8355 HOST_WIDE_INT backwards;
8356};
64266206 8357
cffb2a26 8358/* Fixes less than a word need padding out to a word boundary. */
8359#define MINIPOOL_FIX_SIZE(mode) \
8360 (GET_MODE_SIZE ((mode)) >= 4 ? GET_MODE_SIZE ((mode)) : 4)
64266206 8361
cffb2a26 8362static Mnode * minipool_vector_head;
8363static Mnode * minipool_vector_tail;
8364static rtx minipool_vector_label;
acc677e9 8365static int minipool_pad;
61592d0d 8366
cffb2a26 8367/* The linked list of all minipool fixes required for this function. */
8368Mfix * minipool_fix_head;
8369Mfix * minipool_fix_tail;
8370/* The fix entry for the current minipool, once it has been placed. */
8371Mfix * minipool_barrier;
8372
8373/* Determines if INSN is the start of a jump table. Returns the end
8374 of the TABLE or NULL_RTX. */
8375static rtx
ebd88a36 8376is_jump_table (rtx insn)
64266206 8377{
cffb2a26 8378 rtx table;
9e7454d0 8379
cffb2a26 8380 if (GET_CODE (insn) == JUMP_INSN
8381 && JUMP_LABEL (insn) != NULL
8382 && ((table = next_real_insn (JUMP_LABEL (insn)))
8383 == next_real_insn (insn))
8384 && table != NULL
8385 && GET_CODE (table) == JUMP_INSN
8386 && (GET_CODE (PATTERN (table)) == ADDR_VEC
8387 || GET_CODE (PATTERN (table)) == ADDR_DIFF_VEC))
8388 return table;
8389
8390 return NULL_RTX;
64266206 8391}
8392
fd957ef3 8393#ifndef JUMP_TABLES_IN_TEXT_SECTION
8394#define JUMP_TABLES_IN_TEXT_SECTION 0
8395#endif
8396
cffb2a26 8397static HOST_WIDE_INT
ebd88a36 8398get_jump_table_size (rtx insn)
64266206 8399{
fd957ef3 8400 /* ADDR_VECs only take room if read-only data does into the text
8401 section. */
2f14b1f9 8402 if (JUMP_TABLES_IN_TEXT_SECTION || readonly_data_section == text_section)
fd957ef3 8403 {
8404 rtx body = PATTERN (insn);
8405 int elt = GET_CODE (body) == ADDR_DIFF_VEC ? 1 : 0;
25f905c2 8406 HOST_WIDE_INT size;
8407 HOST_WIDE_INT modesize;
64266206 8408
25f905c2 8409 modesize = GET_MODE_SIZE (GET_MODE (body));
8410 size = modesize * XVECLEN (body, elt);
8411 switch (modesize)
8412 {
8413 case 1:
0d424440 8414 /* Round up size of TBB table to a halfword boundary. */
25f905c2 8415 size = (size + 1) & ~(HOST_WIDE_INT)1;
8416 break;
8417 case 2:
542d5028 8418 /* No padding necessary for TBH. */
25f905c2 8419 break;
8420 case 4:
8421 /* Add two bytes for alignment on Thumb. */
8422 if (TARGET_THUMB)
8423 size += 2;
8424 break;
8425 default:
8426 gcc_unreachable ();
8427 }
8428 return size;
fd957ef3 8429 }
8430
8431 return 0;
cffb2a26 8432}
64266206 8433
cffb2a26 8434/* Move a minipool fix MP from its current location to before MAX_MP.
8435 If MAX_MP is NULL, then MP doesn't need moving, but the addressing
5910bb95 8436 constraints may need updating. */
cffb2a26 8437static Mnode *
ebd88a36 8438move_minipool_fix_forward_ref (Mnode *mp, Mnode *max_mp,
8439 HOST_WIDE_INT max_address)
cffb2a26 8440{
ed29c566 8441 /* The code below assumes these are different. */
8442 gcc_assert (mp != max_mp);
cffb2a26 8443
8444 if (max_mp == NULL)
8445 {
8446 if (max_address < mp->max_address)
8447 mp->max_address = max_address;
8448 }
8449 else
64266206 8450 {
cffb2a26 8451 if (max_address > max_mp->max_address - mp->fix_size)
8452 mp->max_address = max_mp->max_address - mp->fix_size;
8453 else
8454 mp->max_address = max_address;
64266206 8455
cffb2a26 8456 /* Unlink MP from its current position. Since max_mp is non-null,
8457 mp->prev must be non-null. */
8458 mp->prev->next = mp->next;
8459 if (mp->next != NULL)
8460 mp->next->prev = mp->prev;
8461 else
8462 minipool_vector_tail = mp->prev;
64266206 8463
cffb2a26 8464 /* Re-insert it before MAX_MP. */
8465 mp->next = max_mp;
8466 mp->prev = max_mp->prev;
8467 max_mp->prev = mp;
9e7454d0 8468
cffb2a26 8469 if (mp->prev != NULL)
8470 mp->prev->next = mp;
8471 else
8472 minipool_vector_head = mp;
8473 }
64266206 8474
cffb2a26 8475 /* Save the new entry. */
8476 max_mp = mp;
8477
cb0ccc1e 8478 /* Scan over the preceding entries and adjust their addresses as
cffb2a26 8479 required. */
8480 while (mp->prev != NULL
8481 && mp->prev->max_address > mp->max_address - mp->prev->fix_size)
8482 {
8483 mp->prev->max_address = mp->max_address - mp->prev->fix_size;
8484 mp = mp->prev;
64266206 8485 }
8486
cffb2a26 8487 return max_mp;
64266206 8488}
8489
cffb2a26 8490/* Add a constant to the minipool for a forward reference. Returns the
8491 node added or NULL if the constant will not fit in this pool. */
8492static Mnode *
ebd88a36 8493add_minipool_forward_ref (Mfix *fix)
cffb2a26 8494{
8495 /* If set, max_mp is the first pool_entry that has a lower
8496 constraint than the one we are trying to add. */
8497 Mnode * max_mp = NULL;
acc677e9 8498 HOST_WIDE_INT max_address = fix->address + fix->forwards - minipool_pad;
cffb2a26 8499 Mnode * mp;
9e7454d0 8500
8f2b909a 8501 /* If the minipool starts before the end of FIX->INSN then this FIX
8502 can not be placed into the current pool. Furthermore, adding the
8503 new constant pool entry may cause the pool to start FIX_SIZE bytes
8504 earlier. */
cffb2a26 8505 if (minipool_vector_head &&
8f2b909a 8506 (fix->address + get_attr_length (fix->insn)
8507 >= minipool_vector_head->max_address - fix->fix_size))
cffb2a26 8508 return NULL;
64266206 8509
cffb2a26 8510 /* Scan the pool to see if a constant with the same value has
8511 already been added. While we are doing this, also note the
8512 location where we must insert the constant if it doesn't already
8513 exist. */
8514 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
8515 {
8516 if (GET_CODE (fix->value) == GET_CODE (mp->value)
8517 && fix->mode == mp->mode
8518 && (GET_CODE (fix->value) != CODE_LABEL
8519 || (CODE_LABEL_NUMBER (fix->value)
8520 == CODE_LABEL_NUMBER (mp->value)))
8521 && rtx_equal_p (fix->value, mp->value))
8522 {
8523 /* More than one fix references this entry. */
8524 mp->refcount++;
8525 return move_minipool_fix_forward_ref (mp, max_mp, max_address);
8526 }
8527
8528 /* Note the insertion point if necessary. */
8529 if (max_mp == NULL
8530 && mp->max_address > max_address)
8531 max_mp = mp;
755eb2b4 8532
8533 /* If we are inserting an 8-bytes aligned quantity and
8534 we have not already found an insertion point, then
8535 make sure that all such 8-byte aligned quantities are
8536 placed at the start of the pool. */
f9273c43 8537 if (ARM_DOUBLEWORD_ALIGN
755eb2b4 8538 && max_mp == NULL
d98a3884 8539 && fix->fix_size >= 8
8540 && mp->fix_size < 8)
755eb2b4 8541 {
8542 max_mp = mp;
8543 max_address = mp->max_address;
8544 }
cffb2a26 8545 }
8546
8547 /* The value is not currently in the minipool, so we need to create
8548 a new entry for it. If MAX_MP is NULL, the entry will be put on
8549 the end of the list since the placement is less constrained than
8550 any existing entry. Otherwise, we insert the new fix before
b89db9a7 8551 MAX_MP and, if necessary, adjust the constraints on the other
cffb2a26 8552 entries. */
4c36ffe6 8553 mp = XNEW (Mnode);
cffb2a26 8554 mp->fix_size = fix->fix_size;
8555 mp->mode = fix->mode;
8556 mp->value = fix->value;
8557 mp->refcount = 1;
8558 /* Not yet required for a backwards ref. */
8559 mp->min_address = -65536;
8560
8561 if (max_mp == NULL)
8562 {
8563 mp->max_address = max_address;
8564 mp->next = NULL;
8565 mp->prev = minipool_vector_tail;
8566
8567 if (mp->prev == NULL)
8568 {
8569 minipool_vector_head = mp;
8570 minipool_vector_label = gen_label_rtx ();
0da499d4 8571 }
64266206 8572 else
cffb2a26 8573 mp->prev->next = mp;
64266206 8574
cffb2a26 8575 minipool_vector_tail = mp;
8576 }
8577 else
8578 {
8579 if (max_address > max_mp->max_address - mp->fix_size)
8580 mp->max_address = max_mp->max_address - mp->fix_size;
8581 else
8582 mp->max_address = max_address;
8583
8584 mp->next = max_mp;
8585 mp->prev = max_mp->prev;
8586 max_mp->prev = mp;
8587 if (mp->prev != NULL)
8588 mp->prev->next = mp;
8589 else
8590 minipool_vector_head = mp;
8591 }
8592
8593 /* Save the new entry. */
8594 max_mp = mp;
8595
cb0ccc1e 8596 /* Scan over the preceding entries and adjust their addresses as
cffb2a26 8597 required. */
8598 while (mp->prev != NULL
8599 && mp->prev->max_address > mp->max_address - mp->prev->fix_size)
8600 {
8601 mp->prev->max_address = mp->max_address - mp->prev->fix_size;
8602 mp = mp->prev;
64266206 8603 }
8604
cffb2a26 8605 return max_mp;
8606}
8607
8608static Mnode *
ebd88a36 8609move_minipool_fix_backward_ref (Mnode *mp, Mnode *min_mp,
8610 HOST_WIDE_INT min_address)
cffb2a26 8611{
8612 HOST_WIDE_INT offset;
8613
ed29c566 8614 /* The code below assumes these are different. */
8615 gcc_assert (mp != min_mp);
cffb2a26 8616
8617 if (min_mp == NULL)
64266206 8618 {
cffb2a26 8619 if (min_address > mp->min_address)
8620 mp->min_address = min_address;
8621 }
8622 else
8623 {
8624 /* We will adjust this below if it is too loose. */
8625 mp->min_address = min_address;
8626
8627 /* Unlink MP from its current position. Since min_mp is non-null,
8628 mp->next must be non-null. */
8629 mp->next->prev = mp->prev;
8630 if (mp->prev != NULL)
8631 mp->prev->next = mp->next;
8632 else
8633 minipool_vector_head = mp->next;
8634
8635 /* Reinsert it after MIN_MP. */
8636 mp->prev = min_mp;
8637 mp->next = min_mp->next;
8638 min_mp->next = mp;
8639 if (mp->next != NULL)
8640 mp->next->prev = mp;
64266206 8641 else
cffb2a26 8642 minipool_vector_tail = mp;
8643 }
8644
8645 min_mp = mp;
8646
8647 offset = 0;
8648 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
8649 {
8650 mp->offset = offset;
8651 if (mp->refcount > 0)
8652 offset += mp->fix_size;
8653
8654 if (mp->next && mp->next->min_address < mp->min_address + mp->fix_size)
8655 mp->next->min_address = mp->min_address + mp->fix_size;
8656 }
8657
8658 return min_mp;
9e7454d0 8659}
cffb2a26 8660
8661/* Add a constant to the minipool for a backward reference. Returns the
9e7454d0 8662 node added or NULL if the constant will not fit in this pool.
cffb2a26 8663
8664 Note that the code for insertion for a backwards reference can be
8665 somewhat confusing because the calculated offsets for each fix do
8666 not take into account the size of the pool (which is still under
8667 construction. */
8668static Mnode *
ebd88a36 8669add_minipool_backward_ref (Mfix *fix)
cffb2a26 8670{
8671 /* If set, min_mp is the last pool_entry that has a lower constraint
8672 than the one we are trying to add. */
ebd88a36 8673 Mnode *min_mp = NULL;
cffb2a26 8674 /* This can be negative, since it is only a constraint. */
8675 HOST_WIDE_INT min_address = fix->address - fix->backwards;
ebd88a36 8676 Mnode *mp;
cffb2a26 8677
8678 /* If we can't reach the current pool from this insn, or if we can't
8679 insert this entry at the end of the pool without pushing other
8680 fixes out of range, then we don't try. This ensures that we
8681 can't fail later on. */
8682 if (min_address >= minipool_barrier->address
8683 || (minipool_vector_tail->min_address + fix->fix_size
8684 >= minipool_barrier->address))
8685 return NULL;
8686
8687 /* Scan the pool to see if a constant with the same value has
8688 already been added. While we are doing this, also note the
8689 location where we must insert the constant if it doesn't already
8690 exist. */
8691 for (mp = minipool_vector_tail; mp != NULL; mp = mp->prev)
8692 {
8693 if (GET_CODE (fix->value) == GET_CODE (mp->value)
8694 && fix->mode == mp->mode
8695 && (GET_CODE (fix->value) != CODE_LABEL
8696 || (CODE_LABEL_NUMBER (fix->value)
8697 == CODE_LABEL_NUMBER (mp->value)))
8698 && rtx_equal_p (fix->value, mp->value)
8699 /* Check that there is enough slack to move this entry to the
8700 end of the table (this is conservative). */
9e7454d0 8701 && (mp->max_address
8702 > (minipool_barrier->address
cffb2a26 8703 + minipool_vector_tail->offset
8704 + minipool_vector_tail->fix_size)))
8705 {
8706 mp->refcount++;
8707 return move_minipool_fix_backward_ref (mp, min_mp, min_address);
8708 }
8709
8710 if (min_mp != NULL)
8711 mp->min_address += fix->fix_size;
8712 else
8713 {
8714 /* Note the insertion point if necessary. */
8715 if (mp->min_address < min_address)
755eb2b4 8716 {
8717 /* For now, we do not allow the insertion of 8-byte alignment
8718 requiring nodes anywhere but at the start of the pool. */
f9273c43 8719 if (ARM_DOUBLEWORD_ALIGN
d98a3884 8720 && fix->fix_size >= 8 && mp->fix_size < 8)
755eb2b4 8721 return NULL;
8722 else
8723 min_mp = mp;
8724 }
cffb2a26 8725 else if (mp->max_address
8726 < minipool_barrier->address + mp->offset + fix->fix_size)
8727 {
8728 /* Inserting before this entry would push the fix beyond
8729 its maximum address (which can happen if we have
8730 re-located a forwards fix); force the new fix to come
8731 after it. */
8732 min_mp = mp;
8733 min_address = mp->min_address + fix->fix_size;
8734 }
755eb2b4 8735 /* If we are inserting an 8-bytes aligned quantity and
8736 we have not already found an insertion point, then
8737 make sure that all such 8-byte aligned quantities are
8738 placed at the start of the pool. */
f9273c43 8739 else if (ARM_DOUBLEWORD_ALIGN
755eb2b4 8740 && min_mp == NULL
d98a3884 8741 && fix->fix_size >= 8
755eb2b4 8742 && mp->fix_size < 8)
8743 {
8744 min_mp = mp;
8745 min_address = mp->min_address + fix->fix_size;
8746 }
cffb2a26 8747 }
8748 }
8749
8750 /* We need to create a new entry. */
4c36ffe6 8751 mp = XNEW (Mnode);
cffb2a26 8752 mp->fix_size = fix->fix_size;
8753 mp->mode = fix->mode;
8754 mp->value = fix->value;
8755 mp->refcount = 1;
8756 mp->max_address = minipool_barrier->address + 65536;
8757
8758 mp->min_address = min_address;
8759
8760 if (min_mp == NULL)
8761 {
8762 mp->prev = NULL;
8763 mp->next = minipool_vector_head;
8764
8765 if (mp->next == NULL)
8766 {
8767 minipool_vector_tail = mp;
8768 minipool_vector_label = gen_label_rtx ();
8769 }
8770 else
8771 mp->next->prev = mp;
8772
8773 minipool_vector_head = mp;
8774 }
8775 else
8776 {
8777 mp->next = min_mp->next;
8778 mp->prev = min_mp;
8779 min_mp->next = mp;
9e7454d0 8780
cffb2a26 8781 if (mp->next != NULL)
8782 mp->next->prev = mp;
8783 else
8784 minipool_vector_tail = mp;
8785 }
8786
8787 /* Save the new entry. */
8788 min_mp = mp;
8789
8790 if (mp->prev)
8791 mp = mp->prev;
8792 else
8793 mp->offset = 0;
8794
8795 /* Scan over the following entries and adjust their offsets. */
8796 while (mp->next != NULL)
8797 {
8798 if (mp->next->min_address < mp->min_address + mp->fix_size)
8799 mp->next->min_address = mp->min_address + mp->fix_size;
8800
8801 if (mp->refcount)
8802 mp->next->offset = mp->offset + mp->fix_size;
8803 else
8804 mp->next->offset = mp->offset;
8805
8806 mp = mp->next;
8807 }
8808
8809 return min_mp;
8810}
8811
8812static void
ebd88a36 8813assign_minipool_offsets (Mfix *barrier)
cffb2a26 8814{
8815 HOST_WIDE_INT offset = 0;
ebd88a36 8816 Mnode *mp;
cffb2a26 8817
8818 minipool_barrier = barrier;
8819
8820 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
8821 {
8822 mp->offset = offset;
9e7454d0 8823
cffb2a26 8824 if (mp->refcount > 0)
8825 offset += mp->fix_size;
8826 }
8827}
8828
8829/* Output the literal table */
8830static void
ebd88a36 8831dump_minipool (rtx scan)
cffb2a26 8832{
755eb2b4 8833 Mnode * mp;
8834 Mnode * nmp;
8835 int align64 = 0;
8836
f9273c43 8837 if (ARM_DOUBLEWORD_ALIGN)
755eb2b4 8838 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
d98a3884 8839 if (mp->refcount > 0 && mp->fix_size >= 8)
755eb2b4 8840 {
8841 align64 = 1;
8842 break;
8843 }
cffb2a26 8844
450d042a 8845 if (dump_file)
8846 fprintf (dump_file,
755eb2b4 8847 ";; Emitting minipool after insn %u; address %ld; align %d (bytes)\n",
8848 INSN_UID (scan), (unsigned long) minipool_barrier->address, align64 ? 8 : 4);
cffb2a26 8849
8850 scan = emit_label_after (gen_label_rtx (), scan);
755eb2b4 8851 scan = emit_insn_after (align64 ? gen_align_8 () : gen_align_4 (), scan);
cffb2a26 8852 scan = emit_label_after (minipool_vector_label, scan);
8853
8854 for (mp = minipool_vector_head; mp != NULL; mp = nmp)
8855 {
8856 if (mp->refcount > 0)
8857 {
450d042a 8858 if (dump_file)
cffb2a26 8859 {
9e7454d0 8860 fprintf (dump_file,
cffb2a26 8861 ";; Offset %u, min %ld, max %ld ",
8862 (unsigned) mp->offset, (unsigned long) mp->min_address,
8863 (unsigned long) mp->max_address);
450d042a 8864 arm_print_value (dump_file, mp->value);
8865 fputc ('\n', dump_file);
cffb2a26 8866 }
8867
8868 switch (mp->fix_size)
8869 {
8870#ifdef HAVE_consttable_1
8871 case 1:
8872 scan = emit_insn_after (gen_consttable_1 (mp->value), scan);
8873 break;
8874
8875#endif
8876#ifdef HAVE_consttable_2
8877 case 2:
8878 scan = emit_insn_after (gen_consttable_2 (mp->value), scan);
8879 break;
8880
8881#endif
8882#ifdef HAVE_consttable_4
8883 case 4:
8884 scan = emit_insn_after (gen_consttable_4 (mp->value), scan);
8885 break;
8886
8887#endif
8888#ifdef HAVE_consttable_8
8889 case 8:
8890 scan = emit_insn_after (gen_consttable_8 (mp->value), scan);
8891 break;
8892
d98a3884 8893#endif
8894#ifdef HAVE_consttable_16
8895 case 16:
8896 scan = emit_insn_after (gen_consttable_16 (mp->value), scan);
8897 break;
8898
cffb2a26 8899#endif
8900 default:
ed29c566 8901 gcc_unreachable ();
cffb2a26 8902 }
8903 }
8904
8905 nmp = mp->next;
8906 free (mp);
64266206 8907 }
8908
cffb2a26 8909 minipool_vector_head = minipool_vector_tail = NULL;
8910 scan = emit_insn_after (gen_consttable_end (), scan);
8911 scan = emit_barrier_after (scan);
64266206 8912}
8913
cffb2a26 8914/* Return the cost of forcibly inserting a barrier after INSN. */
8915static int
ebd88a36 8916arm_barrier_cost (rtx insn)
56d27660 8917{
cffb2a26 8918 /* Basing the location of the pool on the loop depth is preferable,
8919 but at the moment, the basic block information seems to be
8920 corrupt by this stage of the compilation. */
8921 int base_cost = 50;
8922 rtx next = next_nonnote_insn (insn);
8923
8924 if (next != NULL && GET_CODE (next) == CODE_LABEL)
8925 base_cost -= 20;
8926
8927 switch (GET_CODE (insn))
8928 {
8929 case CODE_LABEL:
8930 /* It will always be better to place the table before the label, rather
8931 than after it. */
9e7454d0 8932 return 50;
56d27660 8933
cffb2a26 8934 case INSN:
8935 case CALL_INSN:
8936 return base_cost;
8937
8938 case JUMP_INSN:
8939 return base_cost - 10;
8940
8941 default:
8942 return base_cost + 10;
8943 }
8944}
8945
8946/* Find the best place in the insn stream in the range
8947 (FIX->address,MAX_ADDRESS) to forcibly insert a minipool barrier.
8948 Create the barrier by inserting a jump and add a new fix entry for
8949 it. */
8950static Mfix *
ebd88a36 8951create_fix_barrier (Mfix *fix, HOST_WIDE_INT max_address)
cffb2a26 8952{
8953 HOST_WIDE_INT count = 0;
8954 rtx barrier;
8955 rtx from = fix->insn;
8f2b909a 8956 /* The instruction after which we will insert the jump. */
8957 rtx selected = NULL;
cffb2a26 8958 int selected_cost;
8f2b909a 8959 /* The address at which the jump instruction will be placed. */
cffb2a26 8960 HOST_WIDE_INT selected_address;
8961 Mfix * new_fix;
8962 HOST_WIDE_INT max_count = max_address - fix->address;
8963 rtx label = gen_label_rtx ();
8964
8965 selected_cost = arm_barrier_cost (from);
8966 selected_address = fix->address;
8967
8968 while (from && count < max_count)
8969 {
8970 rtx tmp;
8971 int new_cost;
8972
8973 /* This code shouldn't have been called if there was a natural barrier
8974 within range. */
ed29c566 8975 gcc_assert (GET_CODE (from) != BARRIER);
cffb2a26 8976
8977 /* Count the length of this insn. */
8978 count += get_attr_length (from);
8979
8980 /* If there is a jump table, add its length. */
8981 tmp = is_jump_table (from);
8982 if (tmp != NULL)
8983 {
8984 count += get_jump_table_size (tmp);
8985
8986 /* Jump tables aren't in a basic block, so base the cost on
8987 the dispatch insn. If we select this location, we will
8988 still put the pool after the table. */
8989 new_cost = arm_barrier_cost (from);
8990
8f2b909a 8991 if (count < max_count
8992 && (!selected || new_cost <= selected_cost))
cffb2a26 8993 {
8994 selected = tmp;
8995 selected_cost = new_cost;
8996 selected_address = fix->address + count;
8997 }
8998
8999 /* Continue after the dispatch table. */
9000 from = NEXT_INSN (tmp);
9001 continue;
9002 }
9003
9004 new_cost = arm_barrier_cost (from);
9e7454d0 9005
8f2b909a 9006 if (count < max_count
9007 && (!selected || new_cost <= selected_cost))
cffb2a26 9008 {
9009 selected = from;
9010 selected_cost = new_cost;
9011 selected_address = fix->address + count;
9012 }
9013
9014 from = NEXT_INSN (from);
9015 }
9016
8f2b909a 9017 /* Make sure that we found a place to insert the jump. */
9018 gcc_assert (selected);
9019
cffb2a26 9020 /* Create a new JUMP_INSN that branches around a barrier. */
9021 from = emit_jump_insn_after (gen_jump (label), selected);
9022 JUMP_LABEL (from) = label;
9023 barrier = emit_barrier_after (from);
9024 emit_label_after (label, barrier);
9025
9026 /* Create a minipool barrier entry for the new barrier. */
a220ccce 9027 new_fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* new_fix));
cffb2a26 9028 new_fix->insn = barrier;
9029 new_fix->address = selected_address;
9030 new_fix->next = fix->next;
9031 fix->next = new_fix;
9032
9033 return new_fix;
9034}
9035
9036/* Record that there is a natural barrier in the insn stream at
9037 ADDRESS. */
56d27660 9038static void
ebd88a36 9039push_minipool_barrier (rtx insn, HOST_WIDE_INT address)
64266206 9040{
a220ccce 9041 Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix));
ecd3fcc7 9042
56d27660 9043 fix->insn = insn;
9044 fix->address = address;
64266206 9045
56d27660 9046 fix->next = NULL;
9047 if (minipool_fix_head != NULL)
9048 minipool_fix_tail->next = fix;
9049 else
9050 minipool_fix_head = fix;
9051
9052 minipool_fix_tail = fix;
9053}
64266206 9054
cffb2a26 9055/* Record INSN, which will need fixing up to load a value from the
9056 minipool. ADDRESS is the offset of the insn since the start of the
9057 function; LOC is a pointer to the part of the insn which requires
9058 fixing; VALUE is the constant that must be loaded, which is of type
9059 MODE. */
56d27660 9060static void
ebd88a36 9061push_minipool_fix (rtx insn, HOST_WIDE_INT address, rtx *loc,
9062 enum machine_mode mode, rtx value)
56d27660 9063{
a220ccce 9064 Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix));
56d27660 9065
9066#ifdef AOF_ASSEMBLER
5910bb95 9067 /* PIC symbol references need to be converted into offsets into the
56d27660 9068 based area. */
cffb2a26 9069 /* XXX This shouldn't be done here. */
9070 if (flag_pic && GET_CODE (value) == SYMBOL_REF)
56d27660 9071 value = aof_pic_entry (value);
9072#endif /* AOF_ASSEMBLER */
9073
9074 fix->insn = insn;
9075 fix->address = address;
9076 fix->loc = loc;
9077 fix->mode = mode;
cffb2a26 9078 fix->fix_size = MINIPOOL_FIX_SIZE (mode);
56d27660 9079 fix->value = value;
cffb2a26 9080 fix->forwards = get_attr_pool_range (insn);
9081 fix->backwards = get_attr_neg_pool_range (insn);
9082 fix->minipool = NULL;
56d27660 9083
9084 /* If an insn doesn't have a range defined for it, then it isn't
ed29c566 9085 expecting to be reworked by this code. Better to stop now than
56d27660 9086 to generate duff assembly code. */
ed29c566 9087 gcc_assert (fix->forwards || fix->backwards);
56d27660 9088
acc677e9 9089 /* If an entry requires 8-byte alignment then assume all constant pools
9090 require 4 bytes of padding. Trying to do this later on a per-pool
9ca2c29a 9091 basis is awkward because existing pool entries have to be modified. */
d98a3884 9092 if (ARM_DOUBLEWORD_ALIGN && fix->fix_size >= 8)
acc677e9 9093 minipool_pad = 4;
755eb2b4 9094
450d042a 9095 if (dump_file)
cffb2a26 9096 {
450d042a 9097 fprintf (dump_file,
cffb2a26 9098 ";; %smode fixup for i%d; addr %lu, range (%ld,%ld): ",
9099 GET_MODE_NAME (mode),
9e7454d0 9100 INSN_UID (insn), (unsigned long) address,
cffb2a26 9101 -1 * (long)fix->backwards, (long)fix->forwards);
450d042a 9102 arm_print_value (dump_file, fix->value);
9103 fprintf (dump_file, "\n");
cffb2a26 9104 }
9105
66aacf41 9106 /* Add it to the chain of fixes. */
56d27660 9107 fix->next = NULL;
9e7454d0 9108
56d27660 9109 if (minipool_fix_head != NULL)
9110 minipool_fix_tail->next = fix;
9111 else
9112 minipool_fix_head = fix;
9113
9114 minipool_fix_tail = fix;
9115}
9116
d51f92df 9117/* Return the cost of synthesizing a 64-bit constant VAL inline.
359a6e9f 9118 Returns the number of insns needed, or 99 if we don't know how to
9119 do it. */
9120int
9121arm_const_double_inline_cost (rtx val)
3194bc82 9122{
d51f92df 9123 rtx lowpart, highpart;
9124 enum machine_mode mode;
a60f1840 9125
d51f92df 9126 mode = GET_MODE (val);
3194bc82 9127
d51f92df 9128 if (mode == VOIDmode)
9129 mode = DImode;
9130
9131 gcc_assert (GET_MODE_SIZE (mode) == 8);
a60f1840 9132
d51f92df 9133 lowpart = gen_lowpart (SImode, val);
9134 highpart = gen_highpart_mode (SImode, mode, val);
a60f1840 9135
d51f92df 9136 gcc_assert (GET_CODE (lowpart) == CONST_INT);
9137 gcc_assert (GET_CODE (highpart) == CONST_INT);
9138
9139 return (arm_gen_constant (SET, SImode, NULL_RTX, INTVAL (lowpart),
359a6e9f 9140 NULL_RTX, NULL_RTX, 0, 0)
d51f92df 9141 + arm_gen_constant (SET, SImode, NULL_RTX, INTVAL (highpart),
359a6e9f 9142 NULL_RTX, NULL_RTX, 0, 0));
9143}
9144
20833d12 9145/* Return true if it is worthwhile to split a 64-bit constant into two
e5ba9289 9146 32-bit operations. This is the case if optimizing for size, or
9147 if we have load delay slots, or if one 32-bit part can be done with
9148 a single data operation. */
9149bool
9150arm_const_double_by_parts (rtx val)
9151{
9152 enum machine_mode mode = GET_MODE (val);
9153 rtx part;
9154
9155 if (optimize_size || arm_ld_sched)
9156 return true;
9157
9158 if (mode == VOIDmode)
9159 mode = DImode;
a60f1840 9160
e5ba9289 9161 part = gen_highpart_mode (SImode, mode, val);
a60f1840 9162
e5ba9289 9163 gcc_assert (GET_CODE (part) == CONST_INT);
a60f1840 9164
e5ba9289 9165 if (const_ok_for_arm (INTVAL (part))
9166 || const_ok_for_arm (~INTVAL (part)))
9167 return true;
a60f1840 9168
e5ba9289 9169 part = gen_lowpart (SImode, val);
a60f1840 9170
e5ba9289 9171 gcc_assert (GET_CODE (part) == CONST_INT);
a60f1840 9172
e5ba9289 9173 if (const_ok_for_arm (INTVAL (part))
9174 || const_ok_for_arm (~INTVAL (part)))
9175 return true;
a60f1840 9176
e5ba9289 9177 return false;
9178}
9179
2c6c7d8b 9180/* Scan INSN and note any of its operands that need fixing.
9181 If DO_PUSHES is false we do not actually push any of the fixups
d51f92df 9182 needed. The function returns TRUE if any fixups were needed/pushed.
2c6c7d8b 9183 This is used by arm_memory_load_p() which needs to know about loads
9184 of constants that will be converted into minipool loads. */
2c6c7d8b 9185static bool
ebd88a36 9186note_invalid_constants (rtx insn, HOST_WIDE_INT address, int do_pushes)
56d27660 9187{
2c6c7d8b 9188 bool result = false;
56d27660 9189 int opno;
9190
cffb2a26 9191 extract_insn (insn);
56d27660 9192
215b30b3 9193 if (!constrain_operands (1))
56d27660 9194 fatal_insn_not_found (insn);
9195
97088907 9196 if (recog_data.n_alternatives == 0)
9197 return false;
9198
d51f92df 9199 /* Fill in recog_op_alt with information about the constraints of
9200 this insn. */
56d27660 9201 preprocess_constraints ();
9202
ed420a25 9203 for (opno = 0; opno < recog_data.n_operands; opno++)
56d27660 9204 {
66aacf41 9205 /* Things we need to fix can only occur in inputs. */
31146060 9206 if (recog_data.operand_type[opno] != OP_IN)
56d27660 9207 continue;
9208
9209 /* If this alternative is a memory reference, then any mention
9210 of constants in this alternative is really to fool reload
9211 into allowing us to accept one there. We need to fix them up
9212 now so that we output the right code. */
9213 if (recog_op_alt[opno][which_alternative].memory_ok)
9214 {
ed420a25 9215 rtx op = recog_data.operand[opno];
56d27660 9216
d51f92df 9217 if (CONSTANT_P (op))
2c6c7d8b 9218 {
9219 if (do_pushes)
9220 push_minipool_fix (insn, address, recog_data.operand_loc[opno],
9221 recog_data.operand_mode[opno], op);
9222 result = true;
9223 }
cffb2a26 9224 else if (GET_CODE (op) == MEM
56d27660 9225 && GET_CODE (XEXP (op, 0)) == SYMBOL_REF
9226 && CONSTANT_POOL_ADDRESS_P (XEXP (op, 0)))
2c6c7d8b 9227 {
9228 if (do_pushes)
28fe824a 9229 {
9230 rtx cop = avoid_constant_pool_reference (op);
9231
9232 /* Casting the address of something to a mode narrower
9233 than a word can cause avoid_constant_pool_reference()
9234 to return the pool reference itself. That's no good to
9e7454d0 9235 us here. Lets just hope that we can use the
28fe824a 9236 constant pool value directly. */
9237 if (op == cop)
aeac46d4 9238 cop = get_pool_constant (XEXP (op, 0));
28fe824a 9239
9240 push_minipool_fix (insn, address,
9241 recog_data.operand_loc[opno],
aeac46d4 9242 recog_data.operand_mode[opno], cop);
28fe824a 9243 }
2c6c7d8b 9244
9245 result = true;
9246 }
56d27660 9247 }
64266206 9248 }
2c6c7d8b 9249
9250 return result;
64266206 9251}
9252
2efea8c0 9253/* Gcc puts the pool in the wrong place for ARM, since we can only
9254 load addresses a limited distance around the pc. We do some
9255 special munging to move the constant pool values to the correct
9256 point in the code. */
2efea8c0 9257static void
ebd88a36 9258arm_reorg (void)
64266206 9259{
9260 rtx insn;
cffb2a26 9261 HOST_WIDE_INT address = 0;
9262 Mfix * fix;
ecd3fcc7 9263
56d27660 9264 minipool_fix_head = minipool_fix_tail = NULL;
64266206 9265
56d27660 9266 /* The first insn must always be a note, or the code below won't
9267 scan it properly. */
2efea8c0 9268 insn = get_insns ();
ed29c566 9269 gcc_assert (GET_CODE (insn) == NOTE);
acc677e9 9270 minipool_pad = 0;
56d27660 9271
9272 /* Scan all the insns and record the operands that will need fixing. */
2efea8c0 9273 for (insn = next_nonnote_insn (insn); insn; insn = next_nonnote_insn (insn))
64266206 9274 {
7d57ec45 9275 if (TARGET_CIRRUS_FIX_INVALID_INSNS
2c6c7d8b 9276 && (arm_cirrus_insn_p (insn)
7d57ec45 9277 || GET_CODE (insn) == JUMP_INSN
2c6c7d8b 9278 || arm_memory_load_p (insn)))
7d57ec45 9279 cirrus_reorg (insn);
9280
56d27660 9281 if (GET_CODE (insn) == BARRIER)
cffb2a26 9282 push_minipool_barrier (insn, address);
2c6c7d8b 9283 else if (INSN_P (insn))
56d27660 9284 {
9285 rtx table;
9286
2c6c7d8b 9287 note_invalid_constants (insn, address, true);
56d27660 9288 address += get_attr_length (insn);
cffb2a26 9289
56d27660 9290 /* If the insn is a vector jump, add the size of the table
9291 and skip the table. */
cffb2a26 9292 if ((table = is_jump_table (insn)) != NULL)
64266206 9293 {
cffb2a26 9294 address += get_jump_table_size (table);
56d27660 9295 insn = table;
9296 }
9297 }
9298 }
61592d0d 9299
cffb2a26 9300 fix = minipool_fix_head;
9e7454d0 9301
56d27660 9302 /* Now scan the fixups and perform the required changes. */
cffb2a26 9303 while (fix)
56d27660 9304 {
cffb2a26 9305 Mfix * ftmp;
9306 Mfix * fdel;
9307 Mfix * last_added_fix;
9308 Mfix * last_barrier = NULL;
9309 Mfix * this_fix;
56d27660 9310
9311 /* Skip any further barriers before the next fix. */
9312 while (fix && GET_CODE (fix->insn) == BARRIER)
9313 fix = fix->next;
9314
cffb2a26 9315 /* No more fixes. */
56d27660 9316 if (fix == NULL)
9317 break;
61592d0d 9318
cffb2a26 9319 last_added_fix = NULL;
64266206 9320
cffb2a26 9321 for (ftmp = fix; ftmp; ftmp = ftmp->next)
56d27660 9322 {
56d27660 9323 if (GET_CODE (ftmp->insn) == BARRIER)
56d27660 9324 {
cffb2a26 9325 if (ftmp->address >= minipool_vector_head->max_address)
9326 break;
64266206 9327
cffb2a26 9328 last_barrier = ftmp;
64266206 9329 }
cffb2a26 9330 else if ((ftmp->minipool = add_minipool_forward_ref (ftmp)) == NULL)
9331 break;
9332
9333 last_added_fix = ftmp; /* Keep track of the last fix added. */
64266206 9334 }
56d27660 9335
cffb2a26 9336 /* If we found a barrier, drop back to that; any fixes that we
9337 could have reached but come after the barrier will now go in
9338 the next mini-pool. */
56d27660 9339 if (last_barrier != NULL)
9340 {
9e7454d0 9341 /* Reduce the refcount for those fixes that won't go into this
cffb2a26 9342 pool after all. */
9343 for (fdel = last_barrier->next;
9344 fdel && fdel != ftmp;
9345 fdel = fdel->next)
9346 {
9347 fdel->minipool->refcount--;
9348 fdel->minipool = NULL;
9349 }
9350
56d27660 9351 ftmp = last_barrier;
9352 }
9353 else
6524d6b5 9354 {
cffb2a26 9355 /* ftmp is first fix that we can't fit into this pool and
9356 there no natural barriers that we could use. Insert a
9357 new barrier in the code somewhere between the previous
9358 fix and this one, and arrange to jump around it. */
9359 HOST_WIDE_INT max_address;
9360
9361 /* The last item on the list of fixes must be a barrier, so
9362 we can never run off the end of the list of fixes without
9363 last_barrier being set. */
ed29c566 9364 gcc_assert (ftmp);
cffb2a26 9365
9366 max_address = minipool_vector_head->max_address;
6524d6b5 9367 /* Check that there isn't another fix that is in range that
9368 we couldn't fit into this pool because the pool was
9369 already too large: we need to put the pool before such an
8f2b909a 9370 instruction. The pool itself may come just after the
9371 fix because create_fix_barrier also allows space for a
9372 jump instruction. */
cffb2a26 9373 if (ftmp->address < max_address)
8f2b909a 9374 max_address = ftmp->address + 1;
cffb2a26 9375
9376 last_barrier = create_fix_barrier (last_added_fix, max_address);
9377 }
9378
9379 assign_minipool_offsets (last_barrier);
9380
9381 while (ftmp)
9382 {
9383 if (GET_CODE (ftmp->insn) != BARRIER
9384 && ((ftmp->minipool = add_minipool_backward_ref (ftmp))
9385 == NULL))
9386 break;
6524d6b5 9387
cffb2a26 9388 ftmp = ftmp->next;
6524d6b5 9389 }
56d27660 9390
9391 /* Scan over the fixes we have identified for this pool, fixing them
9392 up and adding the constants to the pool itself. */
cffb2a26 9393 for (this_fix = fix; this_fix && ftmp != this_fix;
56d27660 9394 this_fix = this_fix->next)
9395 if (GET_CODE (this_fix->insn) != BARRIER)
9396 {
56d27660 9397 rtx addr
9e7454d0 9398 = plus_constant (gen_rtx_LABEL_REF (VOIDmode,
56d27660 9399 minipool_vector_label),
cffb2a26 9400 this_fix->minipool->offset);
56d27660 9401 *this_fix->loc = gen_rtx_MEM (this_fix->mode, addr);
9402 }
9403
cffb2a26 9404 dump_minipool (last_barrier->insn);
56d27660 9405 fix = ftmp;
64266206 9406 }
11de4c7f 9407
56d27660 9408 /* From now on we must synthesize any constants that we can't handle
9409 directly. This can happen if the RTL gets split during final
9410 instruction generation. */
11de4c7f 9411 after_arm_reorg = 1;
a220ccce 9412
9413 /* Free the minipool memory. */
9414 obstack_free (&minipool_obstack, minipool_startobj);
64266206 9415}
8cd42699 9416\f
9417/* Routines to output assembly language. */
9418
a690ede2 9419/* If the rtx is the correct value then return the string of the number.
9c08d1fa 9420 In this way we can ensure that valid double constants are generated even
66aacf41 9421 when cross compiling. */
0bd59681 9422const char *
ebd88a36 9423fp_immediate_constant (rtx x)
9c08d1fa 9424{
9425 REAL_VALUE_TYPE r;
9426 int i;
9e7454d0 9427
a2cd141b 9428 if (!fp_consts_inited)
9429 init_fp_table ();
9e7454d0 9430
9c08d1fa 9431 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
9432 for (i = 0; i < 8; i++)
a2cd141b 9433 if (REAL_VALUES_EQUAL (r, values_fp[i]))
9434 return strings_fp[i];
a690ede2 9435
ed29c566 9436 gcc_unreachable ();
9c08d1fa 9437}
9438
f6b01912 9439/* As for fp_immediate_constant, but value is passed directly, not in rtx. */
0bd59681 9440static const char *
ebd88a36 9441fp_const_from_val (REAL_VALUE_TYPE *r)
f6b01912 9442{
9443 int i;
9444
a2cd141b 9445 if (!fp_consts_inited)
9446 init_fp_table ();
f6b01912 9447
9448 for (i = 0; i < 8; i++)
a2cd141b 9449 if (REAL_VALUES_EQUAL (*r, values_fp[i]))
9450 return strings_fp[i];
f6b01912 9451
ed29c566 9452 gcc_unreachable ();
f6b01912 9453}
9c08d1fa 9454
8cd42699 9455/* Output the operands of a LDM/STM instruction to STREAM.
9456 MASK is the ARM register set mask of which only bits 0-15 are important.
e27ad2d5 9457 REG is the base register, either the frame pointer or the stack pointer,
8b438b4f 9458 INSTR is the possibly suffixed load or store instruction.
9459 RFE is nonzero if the instruction should also copy spsr to cpsr. */
53f179c0 9460
cffb2a26 9461static void
53f179c0 9462print_multi_reg (FILE *stream, const char *instr, unsigned reg,
8b438b4f 9463 unsigned long mask, int rfe)
8cd42699 9464{
53f179c0 9465 unsigned i;
9466 bool not_first = FALSE;
8cd42699 9467
8b438b4f 9468 gcc_assert (!rfe || (mask & (1 << PC_REGNUM)));
39d5d2b6 9469 fputc ('\t', stream);
caceeb43 9470 asm_fprintf (stream, instr, reg);
25f905c2 9471 fputc ('{', stream);
9e7454d0 9472
cffb2a26 9473 for (i = 0; i <= LAST_ARM_REGNUM; i++)
8cd42699 9474 if (mask & (1 << i))
9475 {
9476 if (not_first)
9477 fprintf (stream, ", ");
9e7454d0 9478
caceeb43 9479 asm_fprintf (stream, "%r", i);
8cd42699 9480 not_first = TRUE;
9481 }
a690ede2 9482
8b438b4f 9483 if (rfe)
9484 fprintf (stream, "}^\n");
9485 else
9486 fprintf (stream, "}\n");
a690ede2 9487}
8cd42699 9488
a2cd141b 9489
382a2a57 9490/* Output a FLDMD instruction to STREAM.
7b78e739 9491 BASE if the register containing the address.
9492 REG and COUNT specify the register range.
382a2a57 9493 Extra registers may be added to avoid hardware bugs.
9494
9495 We output FLDMD even for ARMv5 VFP implementations. Although
9496 FLDMD is technically not supported until ARMv6, it is believed
9497 that all VFP implementations support its use in this context. */
a2cd141b 9498
9499static void
382a2a57 9500vfp_output_fldmd (FILE * stream, unsigned int base, int reg, int count)
a2cd141b 9501{
9502 int i;
9503
7b78e739 9504 /* Workaround ARM10 VFPr1 bug. */
9505 if (count == 2 && !arm_arch6)
9506 {
9507 if (reg == 15)
9508 reg--;
9509 count++;
9510 }
9511
b5a0636d 9512 /* FLDMD may not load more than 16 doubleword registers at a time. Split the
9513 load into multiple parts if we have to handle more than 16 registers. */
9514 if (count > 16)
9515 {
9516 vfp_output_fldmd (stream, base, reg, 16);
9517 vfp_output_fldmd (stream, base, reg + 16, count - 16);
9518 return;
9519 }
9520
a2cd141b 9521 fputc ('\t', stream);
382a2a57 9522 asm_fprintf (stream, "fldmfdd\t%r!, {", base);
a2cd141b 9523
7b78e739 9524 for (i = reg; i < reg + count; i++)
a2cd141b 9525 {
7b78e739 9526 if (i > reg)
a2cd141b 9527 fputs (", ", stream);
7b78e739 9528 asm_fprintf (stream, "d%d", i);
a2cd141b 9529 }
9530 fputs ("}\n", stream);
7b78e739 9531
a2cd141b 9532}
9533
9534
9535/* Output the assembly for a store multiple. */
9536
9537const char *
382a2a57 9538vfp_output_fstmd (rtx * operands)
a2cd141b 9539{
9540 char pattern[100];
9541 int p;
9542 int base;
9543 int i;
9544
382a2a57 9545 strcpy (pattern, "fstmfdd\t%m0!, {%P1");
a2cd141b 9546 p = strlen (pattern);
9547
ed29c566 9548 gcc_assert (GET_CODE (operands[1]) == REG);
a2cd141b 9549
9550 base = (REGNO (operands[1]) - FIRST_VFP_REGNUM) / 2;
9551 for (i = 1; i < XVECLEN (operands[2], 0); i++)
9552 {
9553 p += sprintf (&pattern[p], ", d%d", base + i);
9554 }
9555 strcpy (&pattern[p], "}");
9556
9557 output_asm_insn (pattern, operands);
9558 return "";
9559}
9560
9561
7b78e739 9562/* Emit RTL to save block of VFP register pairs to the stack. Returns the
9563 number of bytes pushed. */
a2cd141b 9564
7b78e739 9565static int
382a2a57 9566vfp_emit_fstmd (int base_reg, int count)
a2cd141b 9567{
9568 rtx par;
9569 rtx dwarf;
9570 rtx tmp, reg;
9571 int i;
9572
7b78e739 9573 /* Workaround ARM10 VFPr1 bug. Data corruption can occur when exactly two
9574 register pairs are stored by a store multiple insn. We avoid this
9575 by pushing an extra pair. */
9576 if (count == 2 && !arm_arch6)
9577 {
9578 if (base_reg == LAST_VFP_REGNUM - 3)
9579 base_reg -= 2;
9580 count++;
9581 }
9582
b5a0636d 9583 /* FSTMD may not store more than 16 doubleword registers at once. Split
9584 larger stores into multiple parts (up to a maximum of two, in
9585 practice). */
9586 if (count > 16)
9587 {
9588 int saved;
9589 /* NOTE: base_reg is an internal register number, so each D register
9590 counts as 2. */
9591 saved = vfp_emit_fstmd (base_reg + 32, count - 16);
9592 saved += vfp_emit_fstmd (base_reg, 16);
9593 return saved;
9594 }
9595
a2cd141b 9596 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
9597 dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (count + 1));
9598
9599 reg = gen_rtx_REG (DFmode, base_reg);
9600 base_reg += 2;
9601
9602 XVECEXP (par, 0, 0)
9603 = gen_rtx_SET (VOIDmode,
788fcce0 9604 gen_frame_mem (BLKmode,
9605 gen_rtx_PRE_DEC (BLKmode,
9606 stack_pointer_rtx)),
a2cd141b 9607 gen_rtx_UNSPEC (BLKmode,
9608 gen_rtvec (1, reg),
9609 UNSPEC_PUSH_MULT));
9610
9611 tmp = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
382a2a57 9612 plus_constant (stack_pointer_rtx, -(count * 8)));
a2cd141b 9613 RTX_FRAME_RELATED_P (tmp) = 1;
9614 XVECEXP (dwarf, 0, 0) = tmp;
9615
9616 tmp = gen_rtx_SET (VOIDmode,
788fcce0 9617 gen_frame_mem (DFmode, stack_pointer_rtx),
a2cd141b 9618 reg);
9619 RTX_FRAME_RELATED_P (tmp) = 1;
9620 XVECEXP (dwarf, 0, 1) = tmp;
9621
9622 for (i = 1; i < count; i++)
9623 {
9624 reg = gen_rtx_REG (DFmode, base_reg);
9625 base_reg += 2;
9626 XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode, reg);
9627
9628 tmp = gen_rtx_SET (VOIDmode,
788fcce0 9629 gen_frame_mem (DFmode,
0083a3b9 9630 plus_constant (stack_pointer_rtx,
9631 i * 8)),
a2cd141b 9632 reg);
9633 RTX_FRAME_RELATED_P (tmp) = 1;
9634 XVECEXP (dwarf, 0, i + 1) = tmp;
9635 }
9636
9637 par = emit_insn (par);
9638 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
9639 REG_NOTES (par));
7b78e739 9640 RTX_FRAME_RELATED_P (par) = 1;
9641
382a2a57 9642 return count * 8;
a2cd141b 9643}
9644
bac7fc85 9645/* Emit a call instruction with pattern PAT. ADDR is the address of
9646 the call target. */
9647
9648void
9649arm_emit_call_insn (rtx pat, rtx addr)
9650{
9651 rtx insn;
9652
9653 insn = emit_call_insn (pat);
9654
9655 /* The PIC register is live on entry to VxWorks PIC PLT entries.
9656 If the call might use such an entry, add a use of the PIC register
9657 to the instruction's CALL_INSN_FUNCTION_USAGE. */
9658 if (TARGET_VXWORKS_RTP
9659 && flag_pic
9660 && GET_CODE (addr) == SYMBOL_REF
9661 && (SYMBOL_REF_DECL (addr)
9662 ? !targetm.binds_local_p (SYMBOL_REF_DECL (addr))
9663 : !SYMBOL_REF_LOCAL_P (addr)))
9664 {
9665 require_pic_register ();
9666 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), cfun->machine->pic_reg);
9667 }
9668}
a2cd141b 9669
66aacf41 9670/* Output a 'call' insn. */
0bd59681 9671const char *
ebd88a36 9672output_call (rtx *operands)
8cd42699 9673{
ed29c566 9674 gcc_assert (!arm_arch5); /* Patterns should call blx <reg> directly. */
8cd42699 9675
f1039640 9676 /* Handle calls to lr using ip (which may be clobbered in subr anyway). */
bba10fb8 9677 if (REGNO (operands[0]) == LR_REGNUM)
8cd42699 9678 {
bba10fb8 9679 operands[0] = gen_rtx_REG (SImode, IP_REGNUM);
39d5d2b6 9680 output_asm_insn ("mov%?\t%0, %|lr", operands);
8cd42699 9681 }
9e7454d0 9682
39d5d2b6 9683 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
9e7454d0 9684
f1039640 9685 if (TARGET_INTERWORK || arm_arch4t)
99ecc60d 9686 output_asm_insn ("bx%?\t%0", operands);
9687 else
9688 output_asm_insn ("mov%?\t%|pc, %0", operands);
9e7454d0 9689
a690ede2 9690 return "";
9691}
8cd42699 9692
66aacf41 9693/* Output a 'call' insn that is a reference in memory. */
0bd59681 9694const char *
ebd88a36 9695output_call_mem (rtx *operands)
9c08d1fa 9696{
f1039640 9697 if (TARGET_INTERWORK && !arm_arch5)
99ecc60d 9698 {
9699 output_asm_insn ("ldr%?\t%|ip, %0", operands);
9700 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
9701 output_asm_insn ("bx%?\t%|ip", operands);
9702 }
136396e8 9703 else if (regno_use_in (LR_REGNUM, operands[0]))
9704 {
9705 /* LR is used in the memory address. We load the address in the
9706 first instruction. It's safe to use IP as the target of the
9707 load since the call will kill it anyway. */
9708 output_asm_insn ("ldr%?\t%|ip, %0", operands);
f1039640 9709 if (arm_arch5)
9a821292 9710 output_asm_insn ("blx%?\t%|ip", operands);
f1039640 9711 else
9712 {
9713 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
9714 if (arm_arch4t)
9715 output_asm_insn ("bx%?\t%|ip", operands);
9716 else
9717 output_asm_insn ("mov%?\t%|pc, %|ip", operands);
9718 }
136396e8 9719 }
99ecc60d 9720 else
9721 {
9722 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
9723 output_asm_insn ("ldr%?\t%|pc, %0", operands);
9724 }
9725
a690ede2 9726 return "";
9727}
9c08d1fa 9728
9729
e8ff69a4 9730/* Output a move from arm registers to an fpa registers.
9731 OPERANDS[0] is an fpa register.
9c08d1fa 9732 OPERANDS[1] is the first registers of an arm register pair. */
0bd59681 9733const char *
ebd88a36 9734output_mov_long_double_fpa_from_arm (rtx *operands)
9c08d1fa 9735{
9736 int arm_reg0 = REGNO (operands[1]);
9737 rtx ops[3];
9738
ed29c566 9739 gcc_assert (arm_reg0 != IP_REGNUM);
a690ede2 9740
76676c8e 9741 ops[0] = gen_rtx_REG (SImode, arm_reg0);
9742 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
9743 ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0);
9e7454d0 9744
25f905c2 9745 output_asm_insn ("stm%(fd%)\t%|sp!, {%0, %1, %2}", ops);
39d5d2b6 9746 output_asm_insn ("ldf%?e\t%0, [%|sp], #12", operands);
9e7454d0 9747
a690ede2 9748 return "";
9749}
9c08d1fa 9750
e8ff69a4 9751/* Output a move from an fpa register to arm registers.
9c08d1fa 9752 OPERANDS[0] is the first registers of an arm register pair.
e8ff69a4 9753 OPERANDS[1] is an fpa register. */
0bd59681 9754const char *
ebd88a36 9755output_mov_long_double_arm_from_fpa (rtx *operands)
9c08d1fa 9756{
9757 int arm_reg0 = REGNO (operands[0]);
9758 rtx ops[3];
9759
ed29c566 9760 gcc_assert (arm_reg0 != IP_REGNUM);
a690ede2 9761
76676c8e 9762 ops[0] = gen_rtx_REG (SImode, arm_reg0);
9763 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
9764 ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0);
9c08d1fa 9765
39d5d2b6 9766 output_asm_insn ("stf%?e\t%1, [%|sp, #-12]!", operands);
25f905c2 9767 output_asm_insn ("ldm%(fd%)\t%|sp!, {%0, %1, %2}", ops);
a690ede2 9768 return "";
9769}
9c08d1fa 9770
9771/* Output a move from arm registers to arm registers of a long double
9772 OPERANDS[0] is the destination.
9773 OPERANDS[1] is the source. */
0bd59681 9774const char *
ebd88a36 9775output_mov_long_double_arm_from_arm (rtx *operands)
9c08d1fa 9776{
66aacf41 9777 /* We have to be careful here because the two might overlap. */
9c08d1fa 9778 int dest_start = REGNO (operands[0]);
9779 int src_start = REGNO (operands[1]);
9780 rtx ops[2];
9781 int i;
9782
9783 if (dest_start < src_start)
9784 {
9785 for (i = 0; i < 3; i++)
9786 {
76676c8e 9787 ops[0] = gen_rtx_REG (SImode, dest_start + i);
9788 ops[1] = gen_rtx_REG (SImode, src_start + i);
f6b01912 9789 output_asm_insn ("mov%?\t%0, %1", ops);
9c08d1fa 9790 }
9791 }
9792 else
9793 {
9794 for (i = 2; i >= 0; i--)
9795 {
76676c8e 9796 ops[0] = gen_rtx_REG (SImode, dest_start + i);
9797 ops[1] = gen_rtx_REG (SImode, src_start + i);
f6b01912 9798 output_asm_insn ("mov%?\t%0, %1", ops);
9c08d1fa 9799 }
9800 }
a690ede2 9801
9c08d1fa 9802 return "";
9803}
9804
9805
e8ff69a4 9806/* Output a move from arm registers to an fpa registers.
9807 OPERANDS[0] is an fpa register.
8cd42699 9808 OPERANDS[1] is the first registers of an arm register pair. */
0bd59681 9809const char *
ebd88a36 9810output_mov_double_fpa_from_arm (rtx *operands)
8cd42699 9811{
9812 int arm_reg0 = REGNO (operands[1]);
9813 rtx ops[2];
9814
ed29c566 9815 gcc_assert (arm_reg0 != IP_REGNUM);
9e7454d0 9816
76676c8e 9817 ops[0] = gen_rtx_REG (SImode, arm_reg0);
9818 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
25f905c2 9819 output_asm_insn ("stm%(fd%)\t%|sp!, {%0, %1}", ops);
39d5d2b6 9820 output_asm_insn ("ldf%?d\t%0, [%|sp], #8", operands);
a690ede2 9821 return "";
9822}
8cd42699 9823
e8ff69a4 9824/* Output a move from an fpa register to arm registers.
8cd42699 9825 OPERANDS[0] is the first registers of an arm register pair.
e8ff69a4 9826 OPERANDS[1] is an fpa register. */
0bd59681 9827const char *
ebd88a36 9828output_mov_double_arm_from_fpa (rtx *operands)
8cd42699 9829{
9830 int arm_reg0 = REGNO (operands[0]);
9831 rtx ops[2];
9832
ed29c566 9833 gcc_assert (arm_reg0 != IP_REGNUM);
a690ede2 9834
76676c8e 9835 ops[0] = gen_rtx_REG (SImode, arm_reg0);
9836 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
39d5d2b6 9837 output_asm_insn ("stf%?d\t%1, [%|sp, #-8]!", operands);
25f905c2 9838 output_asm_insn ("ldm%(fd%)\t%|sp!, {%0, %1}", ops);
a690ede2 9839 return "";
9840}
8cd42699 9841
9842/* Output a move between double words.
9843 It must be REG<-REG, REG<-CONST_DOUBLE, REG<-CONST_INT, REG<-MEM
9844 or MEM<-REG and all MEMs must be offsettable addresses. */
0bd59681 9845const char *
ebd88a36 9846output_move_double (rtx *operands)
8cd42699 9847{
9848 enum rtx_code code0 = GET_CODE (operands[0]);
9849 enum rtx_code code1 = GET_CODE (operands[1]);
6019008a 9850 rtx otherops[3];
8cd42699 9851
9852 if (code0 == REG)
9853 {
9854 int reg0 = REGNO (operands[0]);
9855
76676c8e 9856 otherops[0] = gen_rtx_REG (SImode, 1 + reg0);
9e7454d0 9857
ed29c566 9858 gcc_assert (code1 == MEM); /* Constraints should ensure this. */
9859
9860 switch (GET_CODE (XEXP (operands[1], 0)))
8cd42699 9861 {
ed29c566 9862 case REG:
25f905c2 9863 output_asm_insn ("ldm%(ia%)\t%m1, %M0", operands);
ed29c566 9864 break;
a60f1840 9865
ed29c566 9866 case PRE_INC:
9867 gcc_assert (TARGET_LDRD);
25f905c2 9868 output_asm_insn ("ldr%(d%)\t%0, [%m1, #8]!", operands);
ed29c566 9869 break;
a60f1840 9870
ed29c566 9871 case PRE_DEC:
25f905c2 9872 if (TARGET_LDRD)
9873 output_asm_insn ("ldr%(d%)\t%0, [%m1, #-8]!", operands);
9874 else
9875 output_asm_insn ("ldm%(db%)\t%m1!, %M0", operands);
ed29c566 9876 break;
a60f1840 9877
ed29c566 9878 case POST_INC:
25f905c2 9879 output_asm_insn ("ldm%(ia%)\t%m1!, %M0", operands);
ed29c566 9880 break;
a60f1840 9881
ed29c566 9882 case POST_DEC:
9883 gcc_assert (TARGET_LDRD);
25f905c2 9884 output_asm_insn ("ldr%(d%)\t%0, [%m1], #-8", operands);
ed29c566 9885 break;
a60f1840 9886
ed29c566 9887 case PRE_MODIFY:
9888 case POST_MODIFY:
9889 otherops[0] = operands[0];
9890 otherops[1] = XEXP (XEXP (XEXP (operands[1], 0), 1), 0);
9891 otherops[2] = XEXP (XEXP (XEXP (operands[1], 0), 1), 1);
a60f1840 9892
ed29c566 9893 if (GET_CODE (XEXP (operands[1], 0)) == PRE_MODIFY)
8cd42699 9894 {
ed29c566 9895 if (reg_overlap_mentioned_p (otherops[0], otherops[2]))
a8a3b539 9896 {
ed29c566 9897 /* Registers overlap so split out the increment. */
9898 output_asm_insn ("add%?\t%1, %1, %2", otherops);
25f905c2 9899 output_asm_insn ("ldr%(d%)\t%0, [%1] @split", otherops);
a8a3b539 9900 }
9901 else
f1225f6f 9902 {
9903 /* IWMMXT allows offsets larger than ldrd can handle,
9904 fix these up with a pair of ldr. */
9905 if (GET_CODE (otherops[2]) == CONST_INT
9906 && (INTVAL(otherops[2]) <= -256
9907 || INTVAL(otherops[2]) >= 256))
9908 {
9909 output_asm_insn ("ldr%?\t%0, [%1, %2]!", otherops);
9910 otherops[0] = gen_rtx_REG (SImode, 1 + reg0);
9911 output_asm_insn ("ldr%?\t%0, [%1, #4]", otherops);
9912 }
9913 else
9914 output_asm_insn ("ldr%(d%)\t%0, [%1, %2]!", otherops);
9915 }
ed29c566 9916 }
9917 else
9918 {
f1225f6f 9919 /* IWMMXT allows offsets larger than ldrd can handle,
9920 fix these up with a pair of ldr. */
9921 if (GET_CODE (otherops[2]) == CONST_INT
9922 && (INTVAL(otherops[2]) <= -256
9923 || INTVAL(otherops[2]) >= 256))
9924 {
9925 otherops[0] = gen_rtx_REG (SImode, 1 + reg0);
9926 output_asm_insn ("ldr%?\t%0, [%1, #4]", otherops);
9927 otherops[0] = operands[0];
9928 output_asm_insn ("ldr%?\t%0, [%1], %2", otherops);
9929 }
9930 else
9931 /* We only allow constant increments, so this is safe. */
9932 output_asm_insn ("ldr%(d%)\t%0, [%1], %2", otherops);
ed29c566 9933 }
9934 break;
a60f1840 9935
ed29c566 9936 case LABEL_REF:
9937 case CONST:
9938 output_asm_insn ("adr%?\t%0, %1", operands);
25f905c2 9939 output_asm_insn ("ldm%(ia%)\t%0, %M0", operands);
ed29c566 9940 break;
a60f1840 9941
25f905c2 9942 /* ??? This needs checking for thumb2. */
ed29c566 9943 default:
9944 if (arm_add_operand (XEXP (XEXP (operands[1], 0), 1),
9945 GET_MODE (XEXP (XEXP (operands[1], 0), 1))))
9946 {
9947 otherops[0] = operands[0];
9948 otherops[1] = XEXP (XEXP (operands[1], 0), 0);
9949 otherops[2] = XEXP (XEXP (operands[1], 0), 1);
a60f1840 9950
ed29c566 9951 if (GET_CODE (XEXP (operands[1], 0)) == PLUS)
a8a3b539 9952 {
ed29c566 9953 if (GET_CODE (otherops[2]) == CONST_INT)
64266206 9954 {
ed29c566 9955 switch ((int) INTVAL (otherops[2]))
64266206 9956 {
ed29c566 9957 case -8:
25f905c2 9958 output_asm_insn ("ldm%(db%)\t%1, %M0", otherops);
ed29c566 9959 return "";
9960 case -4:
25f905c2 9961 if (TARGET_THUMB2)
9962 break;
9963 output_asm_insn ("ldm%(da%)\t%1, %M0", otherops);
ed29c566 9964 return "";
9965 case 4:
25f905c2 9966 if (TARGET_THUMB2)
9967 break;
9968 output_asm_insn ("ldm%(ib%)\t%1, %M0", otherops);
ed29c566 9969 return "";
a8a3b539 9970 }
ed29c566 9971 }
9972 if (TARGET_LDRD
9973 && (GET_CODE (otherops[2]) == REG
9974 || (GET_CODE (otherops[2]) == CONST_INT
9975 && INTVAL (otherops[2]) > -256
9976 && INTVAL (otherops[2]) < 256)))
9977 {
9978 if (reg_overlap_mentioned_p (otherops[0],
9979 otherops[2]))
a8a3b539 9980 {
ed29c566 9981 /* Swap base and index registers over to
9982 avoid a conflict. */
9983 otherops[1] = XEXP (XEXP (operands[1], 0), 1);
9984 otherops[2] = XEXP (XEXP (operands[1], 0), 0);
a8a3b539 9985 }
ed29c566 9986 /* If both registers conflict, it will usually
9987 have been fixed by a splitter. */
9988 if (reg_overlap_mentioned_p (otherops[0], otherops[2]))
a8a3b539 9989 {
ed29c566 9990 output_asm_insn ("add%?\t%1, %1, %2", otherops);
25f905c2 9991 output_asm_insn ("ldr%(d%)\t%0, [%1]",
ed29c566 9992 otherops);
64266206 9993 }
9994 else
25f905c2 9995 output_asm_insn ("ldr%(d%)\t%0, [%1, %2]", otherops);
ed29c566 9996 return "";
64266206 9997 }
a60f1840 9998
ed29c566 9999 if (GET_CODE (otherops[2]) == CONST_INT)
64266206 10000 {
ed29c566 10001 if (!(const_ok_for_arm (INTVAL (otherops[2]))))
10002 output_asm_insn ("sub%?\t%0, %1, #%n2", otherops);
10003 else
10004 output_asm_insn ("add%?\t%0, %1, %2", otherops);
64266206 10005 }
10006 else
ed29c566 10007 output_asm_insn ("add%?\t%0, %1, %2", otherops);
10008 }
10009 else
10010 output_asm_insn ("sub%?\t%0, %1, %2", otherops);
10011
25f905c2 10012 return "ldm%(ia%)\t%0, %M0";
ed29c566 10013 }
10014 else
10015 {
10016 otherops[1] = adjust_address (operands[1], SImode, 4);
10017 /* Take care of overlapping base/data reg. */
10018 if (reg_mentioned_p (operands[0], operands[1]))
10019 {
10020 output_asm_insn ("ldr%?\t%0, %1", otherops);
10021 output_asm_insn ("ldr%?\t%0, %1", operands);
10022 }
10023 else
10024 {
10025 output_asm_insn ("ldr%?\t%0, %1", operands);
10026 output_asm_insn ("ldr%?\t%0, %1", otherops);
8cd42699 10027 }
10028 }
10029 }
8cd42699 10030 }
ed29c566 10031 else
8cd42699 10032 {
ed29c566 10033 /* Constraints should ensure this. */
10034 gcc_assert (code0 == MEM && code1 == REG);
10035 gcc_assert (REGNO (operands[1]) != IP_REGNUM);
64266206 10036
9c08d1fa 10037 switch (GET_CODE (XEXP (operands[0], 0)))
10038 {
10039 case REG:
25f905c2 10040 output_asm_insn ("stm%(ia%)\t%m0, %M1", operands);
9c08d1fa 10041 break;
64266206 10042
9c08d1fa 10043 case PRE_INC:
ed29c566 10044 gcc_assert (TARGET_LDRD);
25f905c2 10045 output_asm_insn ("str%(d%)\t%1, [%m0, #8]!", operands);
9c08d1fa 10046 break;
64266206 10047
9c08d1fa 10048 case PRE_DEC:
25f905c2 10049 if (TARGET_LDRD)
10050 output_asm_insn ("str%(d%)\t%1, [%m0, #-8]!", operands);
10051 else
10052 output_asm_insn ("stm%(db%)\t%m0!, %M1", operands);
9c08d1fa 10053 break;
64266206 10054
9c08d1fa 10055 case POST_INC:
25f905c2 10056 output_asm_insn ("stm%(ia%)\t%m0!, %M1", operands);
9c08d1fa 10057 break;
64266206 10058
9c08d1fa 10059 case POST_DEC:
ed29c566 10060 gcc_assert (TARGET_LDRD);
25f905c2 10061 output_asm_insn ("str%(d%)\t%1, [%m0], #-8", operands);
a8a3b539 10062 break;
10063
10064 case PRE_MODIFY:
10065 case POST_MODIFY:
10066 otherops[0] = operands[1];
10067 otherops[1] = XEXP (XEXP (XEXP (operands[0], 0), 1), 0);
10068 otherops[2] = XEXP (XEXP (XEXP (operands[0], 0), 1), 1);
10069
f1225f6f 10070 /* IWMMXT allows offsets larger than ldrd can handle,
10071 fix these up with a pair of ldr. */
10072 if (GET_CODE (otherops[2]) == CONST_INT
10073 && (INTVAL(otherops[2]) <= -256
10074 || INTVAL(otherops[2]) >= 256))
10075 {
10076 rtx reg1;
10077 reg1 = gen_rtx_REG (SImode, 1 + REGNO (operands[1]));
10078 if (GET_CODE (XEXP (operands[0], 0)) == PRE_MODIFY)
10079 {
10080 output_asm_insn ("ldr%?\t%0, [%1, %2]!", otherops);
10081 otherops[0] = reg1;
10082 output_asm_insn ("ldr%?\t%0, [%1, #4]", otherops);
10083 }
10084 else
10085 {
10086 otherops[0] = reg1;
10087 output_asm_insn ("ldr%?\t%0, [%1, #4]", otherops);
10088 otherops[0] = operands[1];
10089 output_asm_insn ("ldr%?\t%0, [%1], %2", otherops);
10090 }
10091 }
10092 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_MODIFY)
25f905c2 10093 output_asm_insn ("str%(d%)\t%0, [%1, %2]!", otherops);
a8a3b539 10094 else
25f905c2 10095 output_asm_insn ("str%(d%)\t%0, [%1], %2", otherops);
9c08d1fa 10096 break;
64266206 10097
10098 case PLUS:
a8a3b539 10099 otherops[2] = XEXP (XEXP (operands[0], 0), 1);
10100 if (GET_CODE (otherops[2]) == CONST_INT)
64266206 10101 {
000c5098 10102 switch ((int) INTVAL (XEXP (XEXP (operands[0], 0), 1)))
64266206 10103 {
10104 case -8:
25f905c2 10105 output_asm_insn ("stm%(db%)\t%m0, %M1", operands);
64266206 10106 return "";
10107
10108 case -4:
25f905c2 10109 if (TARGET_THUMB2)
10110 break;
10111 output_asm_insn ("stm%(da%)\t%m0, %M1", operands);
64266206 10112 return "";
10113
10114 case 4:
25f905c2 10115 if (TARGET_THUMB2)
10116 break;
10117 output_asm_insn ("stm%(ib%)\t%m0, %M1", operands);
64266206 10118 return "";
10119 }
10120 }
a8a3b539 10121 if (TARGET_LDRD
10122 && (GET_CODE (otherops[2]) == REG
10123 || (GET_CODE (otherops[2]) == CONST_INT
10124 && INTVAL (otherops[2]) > -256
10125 && INTVAL (otherops[2]) < 256)))
10126 {
10127 otherops[0] = operands[1];
10128 otherops[1] = XEXP (XEXP (operands[0], 0), 0);
25f905c2 10129 output_asm_insn ("str%(d%)\t%0, [%1, %2]", otherops);
a8a3b539 10130 return "";
10131 }
64266206 10132 /* Fall through */
10133
9c08d1fa 10134 default:
d35c2d18 10135 otherops[0] = adjust_address (operands[0], SImode, 4);
76676c8e 10136 otherops[1] = gen_rtx_REG (SImode, 1 + REGNO (operands[1]));
f6b01912 10137 output_asm_insn ("str%?\t%1, %0", operands);
10138 output_asm_insn ("str%?\t%1, %0", otherops);
8cd42699 10139 }
10140 }
8cd42699 10141
f6b01912 10142 return "";
10143}
8cd42699 10144
d98a3884 10145/* Output a move, load or store for quad-word vectors in ARM registers. Only
10146 handles MEMs accepted by neon_vector_mem_operand with CORE=true. */
25f905c2 10147
10148const char *
d98a3884 10149output_move_quad (rtx *operands)
25f905c2 10150{
d98a3884 10151 if (REG_P (operands[0]))
10152 {
10153 /* Load, or reg->reg move. */
25f905c2 10154
d98a3884 10155 if (MEM_P (operands[1]))
10156 {
10157 switch (GET_CODE (XEXP (operands[1], 0)))
10158 {
10159 case REG:
10160 output_asm_insn ("ldm%(ia%)\t%m1, %M0", operands);
10161 break;
10162
10163 case LABEL_REF:
10164 case CONST:
10165 output_asm_insn ("adr%?\t%0, %1", operands);
10166 output_asm_insn ("ldm%(ia%)\t%0, %M0", operands);
10167 break;
10168
10169 default:
10170 gcc_unreachable ();
10171 }
10172 }
10173 else
10174 {
10175 rtx ops[2];
10176 int dest, src, i;
25f905c2 10177
d98a3884 10178 gcc_assert (REG_P (operands[1]));
25f905c2 10179
d98a3884 10180 dest = REGNO (operands[0]);
10181 src = REGNO (operands[1]);
25f905c2 10182
d98a3884 10183 /* This seems pretty dumb, but hopefully GCC won't try to do it
10184 very often. */
10185 if (dest < src)
10186 for (i = 0; i < 4; i++)
10187 {
10188 ops[0] = gen_rtx_REG (SImode, dest + i);
10189 ops[1] = gen_rtx_REG (SImode, src + i);
10190 output_asm_insn ("mov%?\t%0, %1", ops);
10191 }
10192 else
10193 for (i = 3; i >= 0; i--)
10194 {
10195 ops[0] = gen_rtx_REG (SImode, dest + i);
10196 ops[1] = gen_rtx_REG (SImode, src + i);
10197 output_asm_insn ("mov%?\t%0, %1", ops);
10198 }
10199 }
10200 }
10201 else
10202 {
10203 gcc_assert (MEM_P (operands[0]));
10204 gcc_assert (REG_P (operands[1]));
10205 gcc_assert (!reg_overlap_mentioned_p (operands[1], operands[0]));
10206
10207 switch (GET_CODE (XEXP (operands[0], 0)))
10208 {
10209 case REG:
10210 output_asm_insn ("stm%(ia%)\t%m0, %M1", operands);
10211 break;
10212
10213 default:
10214 gcc_unreachable ();
10215 }
10216 }
10217
10218 return "";
10219}
10220
10221/* Output a VFP load or store instruction. */
10222
10223const char *
10224output_move_vfp (rtx *operands)
10225{
10226 rtx reg, mem, addr, ops[2];
10227 int load = REG_P (operands[0]);
10228 int dp = GET_MODE_SIZE (GET_MODE (operands[0])) == 8;
10229 int integer_p = GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT;
10230 const char *template;
10231 char buff[50];
10232 enum machine_mode mode;
10233
10234 reg = operands[!load];
10235 mem = operands[load];
10236
10237 mode = GET_MODE (reg);
10238
10239 gcc_assert (REG_P (reg));
10240 gcc_assert (IS_VFP_REGNUM (REGNO (reg)));
10241 gcc_assert (mode == SFmode
10242 || mode == DFmode
10243 || mode == SImode
10244 || mode == DImode
10245 || (TARGET_NEON && VALID_NEON_DREG_MODE (mode)));
10246 gcc_assert (MEM_P (mem));
10247
10248 addr = XEXP (mem, 0);
10249
10250 switch (GET_CODE (addr))
10251 {
10252 case PRE_DEC:
10253 template = "f%smdb%c%%?\t%%0!, {%%%s1}%s";
10254 ops[0] = XEXP (addr, 0);
10255 ops[1] = reg;
25f905c2 10256 break;
10257
10258 case POST_INC:
10259 template = "f%smia%c%%?\t%%0!, {%%%s1}%s";
10260 ops[0] = XEXP (addr, 0);
10261 ops[1] = reg;
10262 break;
10263
10264 default:
10265 template = "f%s%c%%?\t%%%s0, %%1%s";
10266 ops[0] = reg;
10267 ops[1] = mem;
10268 break;
10269 }
10270
10271 sprintf (buff, template,
10272 load ? "ld" : "st",
10273 dp ? 'd' : 's',
10274 dp ? "P" : "",
10275 integer_p ? "\t%@ int" : "");
10276 output_asm_insn (buff, ops);
10277
10278 return "";
10279}
10280
d98a3884 10281/* Output a Neon quad-word load or store, or a load or store for
10282 larger structure modes. We could also support post-modify forms using
10283 VLD1/VST1 (for the vectorizer, and perhaps otherwise), but we don't do that
10284 yet.
10285 WARNING: The ordering of elements in memory is weird in big-endian mode,
10286 because we use VSTM instead of VST1, to make it easy to make vector stores
10287 via ARM registers write values in the same order as stores direct from Neon
10288 registers. For example, the byte ordering of a quadword vector with 16-byte
10289 elements like this:
10290
10291 [e7:e6:e5:e4:e3:e2:e1:e0] (highest-numbered element first)
10292
10293 will be (with lowest address first, h = most-significant byte,
10294 l = least-significant byte of element):
10295
10296 [e3h, e3l, e2h, e2l, e1h, e1l, e0h, e0l,
10297 e7h, e7l, e6h, e6l, e5h, e5l, e4h, e4l]
10298
10299 When necessary, quadword registers (dN, dN+1) are moved to ARM registers from
10300 rN in the order:
10301
10302 dN -> (rN+1, rN), dN+1 -> (rN+3, rN+2)
10303
10304 So that STM/LDM can be used on vectors in ARM registers, and the same memory
10305 layout will result as if VSTM/VLDM were used. */
10306
10307const char *
10308output_move_neon (rtx *operands)
10309{
10310 rtx reg, mem, addr, ops[2];
10311 int regno, load = REG_P (operands[0]);
10312 const char *template;
10313 char buff[50];
10314 enum machine_mode mode;
10315
10316 reg = operands[!load];
10317 mem = operands[load];
10318
10319 mode = GET_MODE (reg);
10320
10321 gcc_assert (REG_P (reg));
10322 regno = REGNO (reg);
10323 gcc_assert (VFP_REGNO_OK_FOR_DOUBLE (regno)
10324 || NEON_REGNO_OK_FOR_QUAD (regno));
10325 gcc_assert (VALID_NEON_DREG_MODE (mode)
10326 || VALID_NEON_QREG_MODE (mode)
10327 || VALID_NEON_STRUCT_MODE (mode));
10328 gcc_assert (MEM_P (mem));
10329
10330 addr = XEXP (mem, 0);
10331
10332 /* Strip off const from addresses like (const (plus (...))). */
10333 if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == PLUS)
10334 addr = XEXP (addr, 0);
10335
10336 switch (GET_CODE (addr))
10337 {
10338 case POST_INC:
10339 template = "v%smia%%?\t%%0!, %%h1";
10340 ops[0] = XEXP (addr, 0);
10341 ops[1] = reg;
10342 break;
10343
10344 case POST_MODIFY:
10345 /* FIXME: Not currently enabled in neon_vector_mem_operand. */
10346 gcc_unreachable ();
10347
10348 case LABEL_REF:
10349 case PLUS:
10350 {
10351 int nregs = HARD_REGNO_NREGS (REGNO (reg), mode) / 2;
10352 int i;
10353 int overlap = -1;
10354 for (i = 0; i < nregs; i++)
10355 {
10356 /* We're only using DImode here because it's a convenient size. */
10357 ops[0] = gen_rtx_REG (DImode, REGNO (reg) + 2 * i);
10358 ops[1] = adjust_address (mem, SImode, 8 * i);
10359 if (reg_overlap_mentioned_p (ops[0], mem))
10360 {
10361 gcc_assert (overlap == -1);
10362 overlap = i;
10363 }
10364 else
10365 {
10366 sprintf (buff, "v%sr%%?\t%%P0, %%1", load ? "ld" : "st");
10367 output_asm_insn (buff, ops);
10368 }
10369 }
10370 if (overlap != -1)
10371 {
10372 ops[0] = gen_rtx_REG (DImode, REGNO (reg) + 2 * overlap);
10373 ops[1] = adjust_address (mem, SImode, 8 * overlap);
10374 sprintf (buff, "v%sr%%?\t%%P0, %%1", load ? "ld" : "st");
10375 output_asm_insn (buff, ops);
10376 }
10377
10378 return "";
10379 }
10380
10381 default:
10382 template = "v%smia%%?\t%%m0, %%h1";
10383 ops[0] = mem;
10384 ops[1] = reg;
10385 }
10386
10387 sprintf (buff, template, load ? "ld" : "st");
10388 output_asm_insn (buff, ops);
10389
10390 return "";
10391}
10392
a12be13c 10393/* Output an ADD r, s, #n where n may be too big for one instruction.
10394 If adding zero to one register, output nothing. */
0bd59681 10395const char *
ebd88a36 10396output_add_immediate (rtx *operands)
8cd42699 10397{
a690ede2 10398 HOST_WIDE_INT n = INTVAL (operands[2]);
8cd42699 10399
10400 if (n != 0 || REGNO (operands[0]) != REGNO (operands[1]))
10401 {
10402 if (n < 0)
10403 output_multi_immediate (operands,
f6b01912 10404 "sub%?\t%0, %1, %2", "sub%?\t%0, %0, %2", 2,
10405 -n);
8cd42699 10406 else
10407 output_multi_immediate (operands,
f6b01912 10408 "add%?\t%0, %1, %2", "add%?\t%0, %0, %2", 2,
10409 n);
8cd42699 10410 }
a690ede2 10411
10412 return "";
10413}
8cd42699 10414
8cd42699 10415/* Output a multiple immediate operation.
10416 OPERANDS is the vector of operands referred to in the output patterns.
10417 INSTR1 is the output pattern to use for the first constant.
10418 INSTR2 is the output pattern to use for subsequent constants.
10419 IMMED_OP is the index of the constant slot in OPERANDS.
10420 N is the constant value. */
0bd59681 10421static const char *
ebd88a36 10422output_multi_immediate (rtx *operands, const char *instr1, const char *instr2,
10423 int immed_op, HOST_WIDE_INT n)
8cd42699 10424{
a690ede2 10425#if HOST_BITS_PER_WIDE_INT > 32
35cea10c 10426 n &= 0xffffffff;
a690ede2 10427#endif
10428
8cd42699 10429 if (n == 0)
10430 {
a12be13c 10431 /* Quick and easy output. */
8cd42699 10432 operands[immed_op] = const0_rtx;
a12be13c 10433 output_asm_insn (instr1, operands);
8cd42699 10434 }
10435 else
10436 {
10437 int i;
0bd59681 10438 const char * instr = instr1;
8cd42699 10439
66aacf41 10440 /* Note that n is never zero here (which would give no output). */
8cd42699 10441 for (i = 0; i < 32; i += 2)
10442 {
10443 if (n & (3 << i))
10444 {
a690ede2 10445 operands[immed_op] = GEN_INT (n & (255 << i));
10446 output_asm_insn (instr, operands);
8cd42699 10447 instr = instr2;
10448 i += 6;
10449 }
10450 }
10451 }
9e7454d0 10452
a690ede2 10453 return "";
f6b01912 10454}
8cd42699 10455
25f905c2 10456/* Return the name of a shifter operation. */
10457static const char *
10458arm_shift_nmem(enum rtx_code code)
10459{
10460 switch (code)
10461 {
10462 case ASHIFT:
10463 return ARM_LSL_NAME;
10464
10465 case ASHIFTRT:
10466 return "asr";
10467
10468 case LSHIFTRT:
10469 return "lsr";
10470
10471 case ROTATERT:
10472 return "ror";
10473
10474 default:
10475 abort();
10476 }
10477}
10478
8cd42699 10479/* Return the appropriate ARM instruction for the operation code.
10480 The returned result should not be overwritten. OP is the rtx of the
10481 operation. SHIFT_FIRST_ARG is TRUE if the first argument of the operator
10482 was shifted. */
0bd59681 10483const char *
ebd88a36 10484arithmetic_instr (rtx op, int shift_first_arg)
8cd42699 10485{
f6b01912 10486 switch (GET_CODE (op))
8cd42699 10487 {
10488 case PLUS:
a690ede2 10489 return "add";
10490
8cd42699 10491 case MINUS:
a690ede2 10492 return shift_first_arg ? "rsb" : "sub";
10493
8cd42699 10494 case IOR:
a690ede2 10495 return "orr";
10496
8cd42699 10497 case XOR:
a690ede2 10498 return "eor";
10499
8cd42699 10500 case AND:
a690ede2 10501 return "and";
10502
25f905c2 10503 case ASHIFT:
10504 case ASHIFTRT:
10505 case LSHIFTRT:
10506 case ROTATERT:
10507 return arm_shift_nmem(GET_CODE(op));
10508
8cd42699 10509 default:
ed29c566 10510 gcc_unreachable ();
8cd42699 10511 }
a690ede2 10512}
8cd42699 10513
8cd42699 10514/* Ensure valid constant shifts and return the appropriate shift mnemonic
10515 for the operation code. The returned result should not be overwritten.
10516 OP is the rtx code of the shift.
f6b01912 10517 On exit, *AMOUNTP will be -1 if the shift is by a register, or a constant
66aacf41 10518 shift. */
0bd59681 10519static const char *
ebd88a36 10520shift_op (rtx op, HOST_WIDE_INT *amountp)
8cd42699 10521{
0bd59681 10522 const char * mnem;
4b6897e9 10523 enum rtx_code code = GET_CODE (op);
8cd42699 10524
ed29c566 10525 switch (GET_CODE (XEXP (op, 1)))
10526 {
10527 case REG:
10528 case SUBREG:
10529 *amountp = -1;
10530 break;
10531
10532 case CONST_INT:
10533 *amountp = INTVAL (XEXP (op, 1));
10534 break;
10535
10536 default:
10537 gcc_unreachable ();
10538 }
f6b01912 10539
4b6897e9 10540 switch (code)
8cd42699 10541 {
9c9db025 10542 case ROTATE:
ed29c566 10543 gcc_assert (*amountp != -1);
9c9db025 10544 *amountp = 32 - *amountp;
25f905c2 10545 code = ROTATERT;
9c9db025 10546
10547 /* Fall through. */
10548
25f905c2 10549 case ASHIFT:
10550 case ASHIFTRT:
10551 case LSHIFTRT:
f6b01912 10552 case ROTATERT:
25f905c2 10553 mnem = arm_shift_nmem(code);
f6b01912 10554 break;
10555
9c08d1fa 10556 case MULT:
4b6897e9 10557 /* We never have to worry about the amount being other than a
10558 power of 2, since this case can never be reloaded from a reg. */
ed29c566 10559 gcc_assert (*amountp != -1);
10560 *amountp = int_log2 (*amountp);
25f905c2 10561 return ARM_LSL_NAME;
a690ede2 10562
8cd42699 10563 default:
ed29c566 10564 gcc_unreachable ();
8cd42699 10565 }
10566
4b6897e9 10567 if (*amountp != -1)
10568 {
10569 /* This is not 100% correct, but follows from the desire to merge
10570 multiplication by a power of 2 with the recognizer for a
25f905c2 10571 shift. >=32 is not a valid shift for "lsl", so we must try and
4b6897e9 10572 output a shift that produces the correct arithmetical result.
01cc3b75 10573 Using lsr #32 is identical except for the fact that the carry bit
9e7454d0 10574 is not set correctly if we set the flags; but we never use the
4b6897e9 10575 carry bit from such an operation, so we can ignore that. */
10576 if (code == ROTATERT)
a12be13c 10577 /* Rotate is just modulo 32. */
10578 *amountp &= 31;
4b6897e9 10579 else if (*amountp != (*amountp & 31))
10580 {
10581 if (code == ASHIFT)
10582 mnem = "lsr";
10583 *amountp = 32;
10584 }
10585
10586 /* Shifts of 0 are no-ops. */
10587 if (*amountp == 0)
10588 return NULL;
9e7454d0 10589 }
4b6897e9 10590
f6b01912 10591 return mnem;
10592}
8cd42699 10593
66aacf41 10594/* Obtain the shift from the POWER of two. */
a12be13c 10595
dca34a8d 10596static HOST_WIDE_INT
ebd88a36 10597int_log2 (HOST_WIDE_INT power)
8cd42699 10598{
a690ede2 10599 HOST_WIDE_INT shift = 0;
8cd42699 10600
35cea10c 10601 while ((((HOST_WIDE_INT) 1 << shift) & power) == 0)
8cd42699 10602 {
ed29c566 10603 gcc_assert (shift <= 31);
ebd88a36 10604 shift++;
8cd42699 10605 }
a690ede2 10606
10607 return shift;
10608}
8cd42699 10609
624d37a6 10610/* Output a .ascii pseudo-op, keeping track of lengths. This is
10611 because /bin/as is horribly restrictive. The judgement about
10612 whether or not each character is 'printable' (and can be output as
10613 is) or not (and must be printed with an octal escape) must be made
10614 with reference to the *host* character set -- the situation is
10615 similar to that discussed in the comments above pp_c_char in
10616 c-pretty-print.c. */
10617
96576951 10618#define MAX_ASCII_LEN 51
8cd42699 10619
10620void
ebd88a36 10621output_ascii_pseudo_op (FILE *stream, const unsigned char *p, int len)
8cd42699 10622{
10623 int i;
96576951 10624 int len_so_far = 0;
8cd42699 10625
96576951 10626 fputs ("\t.ascii\t\"", stream);
9e7454d0 10627
8cd42699 10628 for (i = 0; i < len; i++)
10629 {
a12be13c 10630 int c = p[i];
8cd42699 10631
96576951 10632 if (len_so_far >= MAX_ASCII_LEN)
8cd42699 10633 {
96576951 10634 fputs ("\"\n\t.ascii\t\"", stream);
8cd42699 10635 len_so_far = 0;
8cd42699 10636 }
10637
624d37a6 10638 if (ISPRINT (c))
8cd42699 10639 {
624d37a6 10640 if (c == '\\' || c == '\"')
96576951 10641 {
624d37a6 10642 putc ('\\', stream);
215b30b3 10643 len_so_far++;
96576951 10644 }
624d37a6 10645 putc (c, stream);
10646 len_so_far++;
10647 }
10648 else
10649 {
10650 fprintf (stream, "\\%03o", c);
10651 len_so_far += 4;
8cd42699 10652 }
8cd42699 10653 }
a690ede2 10654
8cd42699 10655 fputs ("\"\n", stream);
a690ede2 10656}
8cd42699 10657\f
4c44712e 10658/* Compute the register save mask for registers 0 through 12
f9273c43 10659 inclusive. This code is used by arm_compute_save_reg_mask. */
53f179c0 10660
e27ad2d5 10661static unsigned long
ebd88a36 10662arm_compute_save_reg0_reg12_mask (void)
e27ad2d5 10663{
aa1ae31c 10664 unsigned long func_type = arm_current_func_type ();
53f179c0 10665 unsigned long save_reg_mask = 0;
e27ad2d5 10666 unsigned int reg;
e27ad2d5 10667
2d9065d3 10668 if (IS_INTERRUPT (func_type))
e27ad2d5 10669 {
2d9065d3 10670 unsigned int max_reg;
2d9065d3 10671 /* Interrupt functions must not corrupt any registers,
10672 even call clobbered ones. If this is a leaf function
10673 we can just examine the registers used by the RTL, but
10674 otherwise we have to assume that whatever function is
10675 called might clobber anything, and so we have to save
10676 all the call-clobbered registers as well. */
10677 if (ARM_FUNC_TYPE (func_type) == ARM_FT_FIQ)
10678 /* FIQ handlers have registers r8 - r12 banked, so
10679 we only need to check r0 - r7, Normal ISRs only
aa1ae31c 10680 bank r14 and r15, so we must check up to r12.
2d9065d3 10681 r13 is the stack pointer which is always preserved,
10682 so we do not need to consider it here. */
10683 max_reg = 7;
10684 else
10685 max_reg = 12;
9e7454d0 10686
2d9065d3 10687 for (reg = 0; reg <= max_reg; reg++)
3072d30e 10688 if (df_regs_ever_live_p (reg)
10689 || (! current_function_is_leaf && call_used_regs[reg]))
e27ad2d5 10690 save_reg_mask |= (1 << reg);
37d5afa3 10691
f933d49b 10692 /* Also save the pic base register if necessary. */
37d5afa3 10693 if (flag_pic
10694 && !TARGET_SINGLE_PIC_BASE
2cb7d577 10695 && arm_pic_register != INVALID_REGNUM
37d5afa3 10696 && current_function_uses_pic_offset_table)
10697 save_reg_mask |= 1 << PIC_OFFSET_TABLE_REGNUM;
e27ad2d5 10698 }
10699 else
10700 {
25f905c2 10701 /* In arm mode we handle r11 (FP) as a special case. */
10702 unsigned last_reg = TARGET_ARM ? 10 : 11;
10703
e27ad2d5 10704 /* In the normal case we only need to save those registers
10705 which are call saved and which are used by this function. */
25f905c2 10706 for (reg = 0; reg <= last_reg; reg++)
3072d30e 10707 if (df_regs_ever_live_p (reg) && ! call_used_regs[reg])
e27ad2d5 10708 save_reg_mask |= (1 << reg);
10709
10710 /* Handle the frame pointer as a special case. */
3072d30e 10711 if (! TARGET_APCS_FRAME
10712 && ! frame_pointer_needed
10713 && df_regs_ever_live_p (HARD_FRAME_POINTER_REGNUM)
10714 && ! call_used_regs[HARD_FRAME_POINTER_REGNUM])
25f905c2 10715 save_reg_mask |= 1 << HARD_FRAME_POINTER_REGNUM;
10716 else if (! TARGET_APCS_FRAME
10717 && ! frame_pointer_needed
3072d30e 10718 && df_regs_ever_live_p (HARD_FRAME_POINTER_REGNUM)
25f905c2 10719 && ! call_used_regs[HARD_FRAME_POINTER_REGNUM])
e27ad2d5 10720 save_reg_mask |= 1 << HARD_FRAME_POINTER_REGNUM;
10721
10722 /* If we aren't loading the PIC register,
10723 don't stack it even though it may be live. */
10724 if (flag_pic
a60f1840 10725 && !TARGET_SINGLE_PIC_BASE
2cb7d577 10726 && arm_pic_register != INVALID_REGNUM
3072d30e 10727 && (df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM)
37d5afa3 10728 || current_function_uses_pic_offset_table))
e27ad2d5 10729 save_reg_mask |= 1 << PIC_OFFSET_TABLE_REGNUM;
25f905c2 10730
10731 /* The prologue will copy SP into R0, so save it. */
10732 if (IS_STACKALIGN (func_type))
10733 save_reg_mask |= 1;
e27ad2d5 10734 }
10735
4c44712e 10736 /* Save registers so the exception handler can modify them. */
10737 if (current_function_calls_eh_return)
10738 {
10739 unsigned int i;
9e7454d0 10740
4c44712e 10741 for (i = 0; ; i++)
10742 {
10743 reg = EH_RETURN_DATA_REGNO (i);
10744 if (reg == INVALID_REGNUM)
10745 break;
10746 save_reg_mask |= 1 << reg;
10747 }
10748 }
10749
aa1ae31c 10750 return save_reg_mask;
10751}
10752
25f905c2 10753
aa1ae31c 10754/* Compute a bit mask of which registers need to be
10755 saved on the stack for the current function. */
10756
10757static unsigned long
ebd88a36 10758arm_compute_save_reg_mask (void)
aa1ae31c 10759{
10760 unsigned int save_reg_mask = 0;
10761 unsigned long func_type = arm_current_func_type ();
25f905c2 10762 unsigned int reg;
aa1ae31c 10763
10764 if (IS_NAKED (func_type))
10765 /* This should never really happen. */
10766 return 0;
10767
10768 /* If we are creating a stack frame, then we must save the frame pointer,
10769 IP (which will hold the old stack pointer), LR and the PC. */
25f905c2 10770 if (frame_pointer_needed && TARGET_ARM)
aa1ae31c 10771 save_reg_mask |=
10772 (1 << ARM_HARD_FRAME_POINTER_REGNUM)
10773 | (1 << IP_REGNUM)
10774 | (1 << LR_REGNUM)
10775 | (1 << PC_REGNUM);
10776
10777 /* Volatile functions do not return, so there
10778 is no need to save any other registers. */
10779 if (IS_VOLATILE (func_type))
10780 return save_reg_mask;
10781
10782 save_reg_mask |= arm_compute_save_reg0_reg12_mask ();
10783
e27ad2d5 10784 /* Decide if we need to save the link register.
10785 Interrupt routines have their own banked link register,
10786 so they never need to save it.
71d934e9 10787 Otherwise if we do not use the link register we do not need to save
e27ad2d5 10788 it. If we are pushing other registers onto the stack however, we
10789 can save an instruction in the epilogue by pushing the link register
10790 now and then popping it back into the PC. This incurs extra memory
5bd751ff 10791 accesses though, so we only do it when optimizing for size, and only
e27ad2d5 10792 if we know that we will not need a fancy return sequence. */
3072d30e 10793 if (df_regs_ever_live_p (LR_REGNUM)
10794 || (save_reg_mask
10795 && optimize_size
10796 && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL
10797 && !current_function_calls_eh_return))
e27ad2d5 10798 save_reg_mask |= 1 << LR_REGNUM;
10799
89b30d75 10800 if (cfun->machine->lr_save_eliminated)
10801 save_reg_mask &= ~ (1 << LR_REGNUM);
10802
755eb2b4 10803 if (TARGET_REALLY_IWMMXT
10804 && ((bit_count (save_reg_mask)
10805 + ARM_NUM_INTS (current_function_pretend_args_size)) % 2) != 0)
10806 {
755eb2b4 10807 /* The total number of registers that are going to be pushed
10808 onto the stack is odd. We need to ensure that the stack
10809 is 64-bit aligned before we start to save iWMMXt registers,
10810 and also before we start to create locals. (A local variable
10811 might be a double or long long which we will load/store using
10812 an iWMMXt instruction). Therefore we need to push another
10813 ARM register, so that the stack will be 64-bit aligned. We
10814 try to avoid using the arg registers (r0 -r3) as they might be
10815 used to pass values in a tail call. */
10816 for (reg = 4; reg <= 12; reg++)
10817 if ((save_reg_mask & (1 << reg)) == 0)
10818 break;
10819
10820 if (reg <= 12)
10821 save_reg_mask |= (1 << reg);
10822 else
10823 {
10824 cfun->machine->sibcall_blocked = 1;
10825 save_reg_mask |= (1 << 3);
10826 }
10827 }
10828
25f905c2 10829 /* We may need to push an additional register for use initializing the
10830 PIC base register. */
10831 if (TARGET_THUMB2 && IS_NESTED (func_type) && flag_pic
10832 && (save_reg_mask & THUMB2_WORK_REGS) == 0)
10833 {
10834 reg = thumb_find_work_register (1 << 4);
10835 if (!call_used_regs[reg])
10836 save_reg_mask |= (1 << reg);
10837 }
10838
e27ad2d5 10839 return save_reg_mask;
10840}
10841
7b78e739 10842
237533cc 10843/* Compute a bit mask of which registers need to be
10844 saved on the stack for the current function. */
10845static unsigned long
25f905c2 10846thumb1_compute_save_reg_mask (void)
237533cc 10847{
10848 unsigned long mask;
53f179c0 10849 unsigned reg;
237533cc 10850
10851 mask = 0;
10852 for (reg = 0; reg < 12; reg ++)
3072d30e 10853 if (df_regs_ever_live_p (reg) && !call_used_regs[reg])
53f179c0 10854 mask |= 1 << reg;
237533cc 10855
bd0b3b57 10856 if (flag_pic
10857 && !TARGET_SINGLE_PIC_BASE
2cb7d577 10858 && arm_pic_register != INVALID_REGNUM
bd0b3b57 10859 && current_function_uses_pic_offset_table)
10860 mask |= 1 << PIC_OFFSET_TABLE_REGNUM;
53f179c0 10861
150502c9 10862 /* See if we might need r11 for calls to _interwork_r11_call_via_rN(). */
10863 if (!frame_pointer_needed && CALLER_INTERWORKING_SLOT_SIZE > 0)
10864 mask |= 1 << ARM_HARD_FRAME_POINTER_REGNUM;
237533cc 10865
53f179c0 10866 /* LR will also be pushed if any lo regs are pushed. */
237533cc 10867 if (mask & 0xff || thumb_force_lr_save ())
10868 mask |= (1 << LR_REGNUM);
10869
53f179c0 10870 /* Make sure we have a low work register if we need one.
10871 We will need one if we are going to push a high register,
10872 but we are not currently intending to push a low register. */
10873 if ((mask & 0xff) == 0
237533cc 10874 && ((mask & 0x0f00) || TARGET_BACKTRACE))
53f179c0 10875 {
10876 /* Use thumb_find_work_register to choose which register
10877 we will use. If the register is live then we will
10878 have to push it. Use LAST_LO_REGNUM as our fallback
10879 choice for the register to select. */
10880 reg = thumb_find_work_register (1 << LAST_LO_REGNUM);
c550a00b 10881 /* Make sure the register returned by thumb_find_work_register is
10882 not part of the return value. */
10883 if (reg * UNITS_PER_WORD <= arm_size_return_regs ())
10884 reg = LAST_LO_REGNUM;
53f179c0 10885
10886 if (! call_used_regs[reg])
10887 mask |= 1 << reg;
10888 }
237533cc 10889
10890 return mask;
10891}
10892
10893
7b78e739 10894/* Return the number of bytes required to save VFP registers. */
10895static int
10896arm_get_vfp_saved_size (void)
10897{
10898 unsigned int regno;
10899 int count;
10900 int saved;
10901
10902 saved = 0;
10903 /* Space for saved VFP registers. */
10904 if (TARGET_HARD_FLOAT && TARGET_VFP)
10905 {
10906 count = 0;
10907 for (regno = FIRST_VFP_REGNUM;
10908 regno < LAST_VFP_REGNUM;
10909 regno += 2)
10910 {
3072d30e 10911 if ((!df_regs_ever_live_p (regno) || call_used_regs[regno])
10912 && (!df_regs_ever_live_p (regno + 1) || call_used_regs[regno + 1]))
7b78e739 10913 {
10914 if (count > 0)
10915 {
10916 /* Workaround ARM10 VFPr1 bug. */
10917 if (count == 2 && !arm_arch6)
10918 count++;
382a2a57 10919 saved += count * 8;
7b78e739 10920 }
10921 count = 0;
10922 }
10923 else
10924 count++;
10925 }
10926 if (count > 0)
10927 {
10928 if (count == 2 && !arm_arch6)
10929 count++;
382a2a57 10930 saved += count * 8;
7b78e739 10931 }
10932 }
10933 return saved;
10934}
10935
10936
8d69f2ad 10937/* Generate a function exit sequence. If REALLY_RETURN is false, then do
e27ad2d5 10938 everything bar the final return instruction. */
0bd59681 10939const char *
ebd88a36 10940output_return_instruction (rtx operand, int really_return, int reverse)
9c08d1fa 10941{
e27ad2d5 10942 char conditional[10];
9c08d1fa 10943 char instr[100];
53f179c0 10944 unsigned reg;
e27ad2d5 10945 unsigned long live_regs_mask;
10946 unsigned long func_type;
f9273c43 10947 arm_stack_offsets *offsets;
9f468b67 10948
e27ad2d5 10949 func_type = arm_current_func_type ();
4b6897e9 10950
e27ad2d5 10951 if (IS_NAKED (func_type))
cffb2a26 10952 return "";
e27ad2d5 10953
10954 if (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN)
4b6897e9 10955 {
8d69f2ad 10956 /* If this function was declared non-returning, and we have
10957 found a tail call, then we have to trust that the called
10958 function won't return. */
ed593f11 10959 if (really_return)
10960 {
10961 rtx ops[2];
9e7454d0 10962
ed593f11 10963 /* Otherwise, trap an attempted return by aborting. */
10964 ops[0] = operand;
9e7454d0 10965 ops[1] = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)"
ed593f11 10966 : "abort");
10967 assemble_external_libcall (ops[1]);
10968 output_asm_insn (reverse ? "bl%D0\t%a1" : "bl%d0\t%a1", ops);
10969 }
9e7454d0 10970
4b6897e9 10971 return "";
10972 }
e27ad2d5 10973
ed29c566 10974 gcc_assert (!current_function_calls_alloca || really_return);
9c08d1fa 10975
11b07ceb 10976 sprintf (conditional, "%%?%%%c0", reverse ? 'D' : 'd');
cffb2a26 10977
e27ad2d5 10978 return_used_this_function = 1;
9c08d1fa 10979
e27ad2d5 10980 live_regs_mask = arm_compute_save_reg_mask ();
9c08d1fa 10981
71d934e9 10982 if (live_regs_mask)
e27ad2d5 10983 {
71d934e9 10984 const char * return_reg;
10985
9e7454d0 10986 /* If we do not have any special requirements for function exit
8b438b4f 10987 (e.g. interworking) then we can load the return address
71d934e9 10988 directly into the PC. Otherwise we must load it into LR. */
10989 if (really_return
8b438b4f 10990 && (IS_INTERRUPT (func_type) || !TARGET_INTERWORK))
71d934e9 10991 return_reg = reg_names[PC_REGNUM];
e27ad2d5 10992 else
71d934e9 10993 return_reg = reg_names[LR_REGNUM];
10994
e27ad2d5 10995 if ((live_regs_mask & (1 << IP_REGNUM)) == (1 << IP_REGNUM))
fa3ae0b9 10996 {
10997 /* There are three possible reasons for the IP register
10998 being saved. 1) a stack frame was created, in which case
10999 IP contains the old stack pointer, or 2) an ISR routine
11000 corrupted it, or 3) it was saved to align the stack on
11001 iWMMXt. In case 1, restore IP into SP, otherwise just
11002 restore IP. */
11003 if (frame_pointer_needed)
11004 {
11005 live_regs_mask &= ~ (1 << IP_REGNUM);
11006 live_regs_mask |= (1 << SP_REGNUM);
11007 }
11008 else
ed29c566 11009 gcc_assert (IS_INTERRUPT (func_type) || TARGET_REALLY_IWMMXT);
fa3ae0b9 11010 }
a690ede2 11011
4a5f62e2 11012 /* On some ARM architectures it is faster to use LDR rather than
11013 LDM to load a single register. On other architectures, the
11014 cost is the same. In 26 bit mode, or for exception handlers,
11015 we have to use LDM to load the PC so that the CPSR is also
11016 restored. */
11017 for (reg = 0; reg <= LAST_ARM_REGNUM; reg++)
53f179c0 11018 if (live_regs_mask == (1U << reg))
11019 break;
11020
4a5f62e2 11021 if (reg <= LAST_ARM_REGNUM
11022 && (reg != LR_REGNUM
9e7454d0 11023 || ! really_return
c1a66faf 11024 || ! IS_INTERRUPT (func_type)))
4a5f62e2 11025 {
9e7454d0 11026 sprintf (instr, "ldr%s\t%%|%s, [%%|sp], #4", conditional,
4a5f62e2 11027 (reg == LR_REGNUM) ? return_reg : reg_names[reg]);
e27ad2d5 11028 }
9c08d1fa 11029 else
39d5d2b6 11030 {
71d934e9 11031 char *p;
11032 int first = 1;
e27ad2d5 11033
8d69f2ad 11034 /* Generate the load multiple instruction to restore the
11035 registers. Note we can get here, even if
11036 frame_pointer_needed is true, but only if sp already
11037 points to the base of the saved core registers. */
11038 if (live_regs_mask & (1 << SP_REGNUM))
ffc9d00c 11039 {
f9273c43 11040 unsigned HOST_WIDE_INT stack_adjust;
11041
11042 offsets = arm_get_frame_offsets ();
11043 stack_adjust = offsets->outgoing_args - offsets->saved_regs;
ed29c566 11044 gcc_assert (stack_adjust == 0 || stack_adjust == 4);
ffc9d00c 11045
25f905c2 11046 if (stack_adjust && arm_arch5 && TARGET_ARM)
ffc9d00c 11047 sprintf (instr, "ldm%sib\t%%|sp, {", conditional);
11048 else
11049 {
53f179c0 11050 /* If we can't use ldmib (SA110 bug),
11051 then try to pop r3 instead. */
ffc9d00c 11052 if (stack_adjust)
11053 live_regs_mask |= 1 << 3;
11054 sprintf (instr, "ldm%sfd\t%%|sp, {", conditional);
11055 }
11056 }
99ecc60d 11057 else
71d934e9 11058 sprintf (instr, "ldm%sfd\t%%|sp!, {", conditional);
11059
11060 p = instr + strlen (instr);
e27ad2d5 11061
71d934e9 11062 for (reg = 0; reg <= SP_REGNUM; reg++)
11063 if (live_regs_mask & (1 << reg))
11064 {
11065 int l = strlen (reg_names[reg]);
11066
11067 if (first)
11068 first = 0;
11069 else
11070 {
11071 memcpy (p, ", ", 2);
11072 p += 2;
11073 }
11074
11075 memcpy (p, "%|", 2);
11076 memcpy (p + 2, reg_names[reg], l);
11077 p += l + 2;
11078 }
9e7454d0 11079
71d934e9 11080 if (live_regs_mask & (1 << LR_REGNUM))
11081 {
f29bf0d0 11082 sprintf (p, "%s%%|%s}", first ? "" : ", ", return_reg);
c1a66faf 11083 /* If returning from an interrupt, restore the CPSR. */
11084 if (IS_INTERRUPT (func_type))
f29bf0d0 11085 strcat (p, "^");
71d934e9 11086 }
11087 else
11088 strcpy (p, "}");
39d5d2b6 11089 }
99ecc60d 11090
71d934e9 11091 output_asm_insn (instr, & operand);
11092
4a5f62e2 11093 /* See if we need to generate an extra instruction to
11094 perform the actual function return. */
11095 if (really_return
11096 && func_type != ARM_FT_INTERWORKED
11097 && (live_regs_mask & (1 << LR_REGNUM)) != 0)
99ecc60d 11098 {
4a5f62e2 11099 /* The return has already been handled
11100 by loading the LR into the PC. */
11101 really_return = 0;
99ecc60d 11102 }
9c08d1fa 11103 }
9f468b67 11104
71d934e9 11105 if (really_return)
9c08d1fa 11106 {
e27ad2d5 11107 switch ((int) ARM_FUNC_TYPE (func_type))
11108 {
11109 case ARM_FT_ISR:
11110 case ARM_FT_FIQ:
25f905c2 11111 /* ??? This is wrong for unified assembly syntax. */
e27ad2d5 11112 sprintf (instr, "sub%ss\t%%|pc, %%|lr, #4", conditional);
11113 break;
11114
11115 case ARM_FT_INTERWORKED:
11116 sprintf (instr, "bx%s\t%%|lr", conditional);
11117 break;
11118
11119 case ARM_FT_EXCEPTION:
25f905c2 11120 /* ??? This is wrong for unified assembly syntax. */
e27ad2d5 11121 sprintf (instr, "mov%ss\t%%|pc, %%|lr", conditional);
11122 break;
11123
11124 default:
f1039640 11125 /* Use bx if it's available. */
11126 if (arm_arch5 || arm_arch4t)
9e7454d0 11127 sprintf (instr, "bx%s\t%%|lr", conditional);
71d934e9 11128 else
c1a66faf 11129 sprintf (instr, "mov%s\t%%|pc, %%|lr", conditional);
e27ad2d5 11130 break;
11131 }
71d934e9 11132
11133 output_asm_insn (instr, & operand);
9c08d1fa 11134 }
a690ede2 11135
9c08d1fa 11136 return "";
11137}
11138
c00597d1 11139/* Write the function name into the code section, directly preceding
11140 the function prologue.
11141
11142 Code will be output similar to this:
11143 t0
11144 .ascii "arm_poke_function_name", 0
11145 .align
11146 t1
11147 .word 0xff000000 + (t1 - t0)
11148 arm_poke_function_name
11149 mov ip, sp
11150 stmfd sp!, {fp, ip, lr, pc}
11151 sub fp, ip, #4
11152
11153 When performing a stack backtrace, code can inspect the value
11154 of 'pc' stored at 'fp' + 0. If the trace function then looks
11155 at location pc - 12 and the top 8 bits are set, then we know
11156 that there is a function name embedded immediately preceding this
11157 location and has length ((pc[-3]) & 0xff000000).
11158
11159 We assume that pc is declared as a pointer to an unsigned long.
11160
11161 It is of no benefit to output the function name if we are assembling
11162 a leaf function. These function types will not contain a stack
11163 backtrace structure, therefore it is not possible to determine the
11164 function name. */
c00597d1 11165void
ebd88a36 11166arm_poke_function_name (FILE *stream, const char *name)
c00597d1 11167{
11168 unsigned long alignlength;
11169 unsigned long length;
11170 rtx x;
11171
cffb2a26 11172 length = strlen (name) + 1;
068e6db6 11173 alignlength = ROUND_UP_WORD (length);
9e7454d0 11174
56d27660 11175 ASM_OUTPUT_ASCII (stream, name, length);
c00597d1 11176 ASM_OUTPUT_ALIGN (stream, 2);
35cea10c 11177 x = GEN_INT ((unsigned HOST_WIDE_INT) 0xff000000 + alignlength);
58356836 11178 assemble_aligned_integer (UNITS_PER_WORD, x);
c00597d1 11179}
11180
e27ad2d5 11181/* Place some comments into the assembler stream
11182 describing the current function. */
17d9b0c3 11183static void
ebd88a36 11184arm_output_function_prologue (FILE *f, HOST_WIDE_INT frame_size)
8cd42699 11185{
e27ad2d5 11186 unsigned long func_type;
17d9b0c3 11187
25f905c2 11188 if (TARGET_THUMB1)
17d9b0c3 11189 {
25f905c2 11190 thumb1_output_function_prologue (f, frame_size);
17d9b0c3 11191 return;
11192 }
9e7454d0 11193
e27ad2d5 11194 /* Sanity check. */
ed29c566 11195 gcc_assert (!arm_ccfsm_state && !arm_target_insn);
9011416b 11196
e27ad2d5 11197 func_type = arm_current_func_type ();
9e7454d0 11198
e27ad2d5 11199 switch ((int) ARM_FUNC_TYPE (func_type))
11200 {
11201 default:
11202 case ARM_FT_NORMAL:
11203 break;
11204 case ARM_FT_INTERWORKED:
11205 asm_fprintf (f, "\t%@ Function supports interworking.\n");
11206 break;
e27ad2d5 11207 case ARM_FT_ISR:
11208 asm_fprintf (f, "\t%@ Interrupt Service Routine.\n");
11209 break;
11210 case ARM_FT_FIQ:
11211 asm_fprintf (f, "\t%@ Fast Interrupt Service Routine.\n");
11212 break;
11213 case ARM_FT_EXCEPTION:
11214 asm_fprintf (f, "\t%@ ARM Exception Handler.\n");
11215 break;
11216 }
9e7454d0 11217
e27ad2d5 11218 if (IS_NAKED (func_type))
11219 asm_fprintf (f, "\t%@ Naked Function: prologue and epilogue provided by programmer.\n");
11220
11221 if (IS_VOLATILE (func_type))
11222 asm_fprintf (f, "\t%@ Volatile: function does not return.\n");
11223
11224 if (IS_NESTED (func_type))
11225 asm_fprintf (f, "\t%@ Nested: function declared inside another function.\n");
25f905c2 11226 if (IS_STACKALIGN (func_type))
11227 asm_fprintf (f, "\t%@ Stack Align: May be called with mis-aligned SP.\n");
9e7454d0 11228
4d1bb299 11229 asm_fprintf (f, "\t%@ args = %d, pretend = %d, frame = %wd\n",
caceeb43 11230 current_function_args_size,
11231 current_function_pretend_args_size, frame_size);
e27ad2d5 11232
71904594 11233 asm_fprintf (f, "\t%@ frame_needed = %d, uses_anonymous_args = %d\n",
caceeb43 11234 frame_pointer_needed,
71904594 11235 cfun->machine->uses_anonymous_args);
8cd42699 11236
89b30d75 11237 if (cfun->machine->lr_save_eliminated)
11238 asm_fprintf (f, "\t%@ link register save eliminated.\n");
11239
4c44712e 11240 if (current_function_calls_eh_return)
11241 asm_fprintf (f, "\t@ Calls __builtin_eh_return.\n");
11242
69120d26 11243#ifdef AOF_ASSEMBLER
11244 if (flag_pic)
caceeb43 11245 asm_fprintf (f, "\tmov\t%r, %r\n", IP_REGNUM, PIC_OFFSET_TABLE_REGNUM);
69120d26 11246#endif
e27ad2d5 11247
9e7454d0 11248 return_used_this_function = 0;
a690ede2 11249}
8cd42699 11250
0bd59681 11251const char *
ffc9d00c 11252arm_output_epilogue (rtx sibling)
8cd42699 11253{
56d27660 11254 int reg;
89b30d75 11255 unsigned long saved_regs_mask;
e27ad2d5 11256 unsigned long func_type;
9e7454d0 11257 /* Floats_offset is the offset from the "virtual" frame. In an APCS
73dd1c00 11258 frame that is $fp + 4 for a non-variadic function. */
11259 int floats_offset = 0;
8cd42699 11260 rtx operands[3];
cffb2a26 11261 FILE * f = asm_out_file;
755eb2b4 11262 unsigned int lrm_count = 0;
ffc9d00c 11263 int really_return = (sibling == NULL);
a2cd141b 11264 int start_reg;
f9273c43 11265 arm_stack_offsets *offsets;
8cd42699 11266
e27ad2d5 11267 /* If we have already generated the return instruction
11268 then it is futile to generate anything else. */
ffc9d00c 11269 if (use_return_insn (FALSE, sibling) && return_used_this_function)
56d27660 11270 return "";
8cd42699 11271
e27ad2d5 11272 func_type = arm_current_func_type ();
cffb2a26 11273
e27ad2d5 11274 if (IS_NAKED (func_type))
11275 /* Naked functions don't have epilogues. */
11276 return "";
1c494086 11277
e27ad2d5 11278 if (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN)
4b6897e9 11279 {
6ebaa29d 11280 rtx op;
9e7454d0 11281
e27ad2d5 11282 /* A volatile function should never return. Call abort. */
55c1e470 11283 op = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)" : "abort");
64266206 11284 assemble_external_libcall (op);
4b6897e9 11285 output_asm_insn ("bl\t%a0", &op);
9e7454d0 11286
56d27660 11287 return "";
4b6897e9 11288 }
11289
ed29c566 11290 /* If we are throwing an exception, then we really must be doing a
11291 return, so we can't tail-call. */
11292 gcc_assert (!current_function_calls_eh_return || really_return);
9e7454d0 11293
f9273c43 11294 offsets = arm_get_frame_offsets ();
89b30d75 11295 saved_regs_mask = arm_compute_save_reg_mask ();
755eb2b4 11296
11297 if (TARGET_IWMMXT)
11298 lrm_count = bit_count (saved_regs_mask);
11299
f9273c43 11300 floats_offset = offsets->saved_args;
e27ad2d5 11301 /* Compute how far away the floats will be. */
755eb2b4 11302 for (reg = 0; reg <= LAST_ARM_REGNUM; reg++)
89b30d75 11303 if (saved_regs_mask & (1 << reg))
0eb4b5ff 11304 floats_offset += 4;
9e7454d0 11305
25f905c2 11306 if (frame_pointer_needed && TARGET_ARM)
8cd42699 11307 {
a2cd141b 11308 /* This variable is for the Virtual Frame Pointer, not VFP regs. */
f9273c43 11309 int vfp_offset = offsets->frame;
73dd1c00 11310
c7f506fd 11311 if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
f21249d5 11312 {
a2cd141b 11313 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
3072d30e 11314 if (df_regs_ever_live_p (reg) && !call_used_regs[reg])
f21249d5 11315 {
11316 floats_offset += 12;
9e7454d0 11317 asm_fprintf (f, "\tldfe\t%r, [%r, #-%d]\n",
73dd1c00 11318 reg, FP_REGNUM, floats_offset - vfp_offset);
f21249d5 11319 }
11320 }
11321 else
11322 {
a2cd141b 11323 start_reg = LAST_FPA_REGNUM;
f21249d5 11324
a2cd141b 11325 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
f21249d5 11326 {
3072d30e 11327 if (df_regs_ever_live_p (reg) && !call_used_regs[reg])
f21249d5 11328 {
11329 floats_offset += 12;
9e7454d0 11330
66aacf41 11331 /* We can't unstack more than four registers at once. */
f21249d5 11332 if (start_reg - reg == 3)
11333 {
caceeb43 11334 asm_fprintf (f, "\tlfm\t%r, 4, [%r, #-%d]\n",
73dd1c00 11335 reg, FP_REGNUM, floats_offset - vfp_offset);
f21249d5 11336 start_reg = reg - 1;
11337 }
11338 }
11339 else
11340 {
11341 if (reg != start_reg)
caceeb43 11342 asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n",
11343 reg + 1, start_reg - reg,
73dd1c00 11344 FP_REGNUM, floats_offset - vfp_offset);
f21249d5 11345 start_reg = reg - 1;
11346 }
11347 }
11348
11349 /* Just in case the last register checked also needs unstacking. */
11350 if (reg != start_reg)
caceeb43 11351 asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n",
11352 reg + 1, start_reg - reg,
73dd1c00 11353 FP_REGNUM, floats_offset - vfp_offset);
f21249d5 11354 }
e27ad2d5 11355
a2cd141b 11356 if (TARGET_HARD_FLOAT && TARGET_VFP)
11357 {
7b78e739 11358 int saved_size;
a2cd141b 11359
382a2a57 11360 /* The fldmd insns do not have base+offset addressing
11361 modes, so we use IP to hold the address. */
7b78e739 11362 saved_size = arm_get_vfp_saved_size ();
a2cd141b 11363
7b78e739 11364 if (saved_size > 0)
a2cd141b 11365 {
7b78e739 11366 floats_offset += saved_size;
a2cd141b 11367 asm_fprintf (f, "\tsub\t%r, %r, #%d\n", IP_REGNUM,
11368 FP_REGNUM, floats_offset - vfp_offset);
11369 }
11370 start_reg = FIRST_VFP_REGNUM;
11371 for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2)
11372 {
3072d30e 11373 if ((!df_regs_ever_live_p (reg) || call_used_regs[reg])
11374 && (!df_regs_ever_live_p (reg + 1) || call_used_regs[reg + 1]))
a2cd141b 11375 {
11376 if (start_reg != reg)
382a2a57 11377 vfp_output_fldmd (f, IP_REGNUM,
7b78e739 11378 (start_reg - FIRST_VFP_REGNUM) / 2,
11379 (reg - start_reg) / 2);
a2cd141b 11380 start_reg = reg + 2;
11381 }
11382 }
11383 if (start_reg != reg)
382a2a57 11384 vfp_output_fldmd (f, IP_REGNUM,
7b78e739 11385 (start_reg - FIRST_VFP_REGNUM) / 2,
11386 (reg - start_reg) / 2);
a2cd141b 11387 }
11388
755eb2b4 11389 if (TARGET_IWMMXT)
11390 {
11391 /* The frame pointer is guaranteed to be non-double-word aligned.
11392 This is because it is set to (old_stack_pointer - 4) and the
11393 old_stack_pointer was double word aligned. Thus the offset to
11394 the iWMMXt registers to be loaded must also be non-double-word
11395 sized, so that the resultant address *is* double-word aligned.
11396 We can ignore floats_offset since that was already included in
11397 the live_regs_mask. */
11398 lrm_count += (lrm_count % 2 ? 2 : 1);
9e7454d0 11399
9d63835d 11400 for (reg = LAST_IWMMXT_REGNUM; reg >= FIRST_IWMMXT_REGNUM; reg--)
3072d30e 11401 if (df_regs_ever_live_p (reg) && !call_used_regs[reg])
755eb2b4 11402 {
9e7454d0 11403 asm_fprintf (f, "\twldrd\t%r, [%r, #-%d]\n",
755eb2b4 11404 reg, FP_REGNUM, lrm_count * 4);
9e7454d0 11405 lrm_count += 2;
755eb2b4 11406 }
11407 }
11408
89b30d75 11409 /* saved_regs_mask should contain the IP, which at the time of stack
e27ad2d5 11410 frame generation actually contains the old stack pointer. So a
11411 quick way to unwind the stack is just pop the IP register directly
11412 into the stack pointer. */
ed29c566 11413 gcc_assert (saved_regs_mask & (1 << IP_REGNUM));
89b30d75 11414 saved_regs_mask &= ~ (1 << IP_REGNUM);
11415 saved_regs_mask |= (1 << SP_REGNUM);
e27ad2d5 11416
89b30d75 11417 /* There are two registers left in saved_regs_mask - LR and PC. We
e27ad2d5 11418 only need to restore the LR register (the return address), but to
11419 save time we can load it directly into the PC, unless we need a
11420 special function exit sequence, or we are not really returning. */
4c44712e 11421 if (really_return
11422 && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL
11423 && !current_function_calls_eh_return)
e27ad2d5 11424 /* Delete the LR from the register mask, so that the LR on
11425 the stack is loaded into the PC in the register mask. */
89b30d75 11426 saved_regs_mask &= ~ (1 << LR_REGNUM);
f21249d5 11427 else
89b30d75 11428 saved_regs_mask &= ~ (1 << PC_REGNUM);
01c5c234 11429
11430 /* We must use SP as the base register, because SP is one of the
11431 registers being restored. If an interrupt or page fault
11432 happens in the ldm instruction, the SP might or might not
11433 have been restored. That would be bad, as then SP will no
11434 longer indicate the safe area of stack, and we can get stack
11435 corruption. Using SP as the base register means that it will
11436 be reset correctly to the original value, should an interrupt
8d69f2ad 11437 occur. If the stack pointer already points at the right
11438 place, then omit the subtraction. */
f9273c43 11439 if (offsets->outgoing_args != (1 + (int) bit_count (saved_regs_mask))
8d69f2ad 11440 || current_function_calls_alloca)
11441 asm_fprintf (f, "\tsub\t%r, %r, #%d\n", SP_REGNUM, FP_REGNUM,
11442 4 * bit_count (saved_regs_mask));
8b438b4f 11443 print_multi_reg (f, "ldmfd\t%r, ", SP_REGNUM, saved_regs_mask, 0);
2d9065d3 11444
11445 if (IS_INTERRUPT (func_type))
11446 /* Interrupt handlers will have pushed the
11447 IP onto the stack, so restore it now. */
8b438b4f 11448 print_multi_reg (f, "ldmfd\t%r!, ", SP_REGNUM, 1 << IP_REGNUM, 0);
8cd42699 11449 }
11450 else
11451 {
25f905c2 11452 HOST_WIDE_INT amount;
8b438b4f 11453 int rfe;
093305b1 11454 /* Restore stack pointer if necessary. */
25f905c2 11455 if (frame_pointer_needed)
093305b1 11456 {
25f905c2 11457 /* For Thumb-2 restore sp from the frame pointer.
542d5028 11458 Operand restrictions mean we have to increment FP, then copy
25f905c2 11459 to SP. */
11460 amount = offsets->locals_base - offsets->saved_regs;
11461 operands[0] = hard_frame_pointer_rtx;
11462 }
11463 else
11464 {
11465 operands[0] = stack_pointer_rtx;
11466 amount = offsets->outgoing_args - offsets->saved_regs;
11467 }
11468
11469 if (amount)
11470 {
11471 operands[1] = operands[0];
11472 operands[2] = GEN_INT (amount);
093305b1 11473 output_add_immediate (operands);
11474 }
25f905c2 11475 if (frame_pointer_needed)
11476 asm_fprintf (f, "\tmov\t%r, %r\n",
11477 SP_REGNUM, HARD_FRAME_POINTER_REGNUM);
093305b1 11478
c7f506fd 11479 if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
f21249d5 11480 {
a2cd141b 11481 for (reg = FIRST_FPA_REGNUM; reg <= LAST_FPA_REGNUM; reg++)
3072d30e 11482 if (df_regs_ever_live_p (reg) && !call_used_regs[reg])
caceeb43 11483 asm_fprintf (f, "\tldfe\t%r, [%r], #12\n",
11484 reg, SP_REGNUM);
f21249d5 11485 }
11486 else
11487 {
a2cd141b 11488 start_reg = FIRST_FPA_REGNUM;
f21249d5 11489
a2cd141b 11490 for (reg = FIRST_FPA_REGNUM; reg <= LAST_FPA_REGNUM; reg++)
f21249d5 11491 {
3072d30e 11492 if (df_regs_ever_live_p (reg) && !call_used_regs[reg])
f21249d5 11493 {
11494 if (reg - start_reg == 3)
11495 {
caceeb43 11496 asm_fprintf (f, "\tlfmfd\t%r, 4, [%r]!\n",
11497 start_reg, SP_REGNUM);
f21249d5 11498 start_reg = reg + 1;
11499 }
11500 }
11501 else
11502 {
11503 if (reg != start_reg)
caceeb43 11504 asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n",
11505 start_reg, reg - start_reg,
11506 SP_REGNUM);
9e7454d0 11507
f21249d5 11508 start_reg = reg + 1;
11509 }
11510 }
11511
11512 /* Just in case the last register checked also needs unstacking. */
11513 if (reg != start_reg)
caceeb43 11514 asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n",
11515 start_reg, reg - start_reg, SP_REGNUM);
f21249d5 11516 }
11517
a2cd141b 11518 if (TARGET_HARD_FLOAT && TARGET_VFP)
11519 {
11520 start_reg = FIRST_VFP_REGNUM;
11521 for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2)
11522 {
3072d30e 11523 if ((!df_regs_ever_live_p (reg) || call_used_regs[reg])
11524 && (!df_regs_ever_live_p (reg + 1) || call_used_regs[reg + 1]))
a2cd141b 11525 {
11526 if (start_reg != reg)
382a2a57 11527 vfp_output_fldmd (f, SP_REGNUM,
7b78e739 11528 (start_reg - FIRST_VFP_REGNUM) / 2,
11529 (reg - start_reg) / 2);
a2cd141b 11530 start_reg = reg + 2;
11531 }
11532 }
11533 if (start_reg != reg)
382a2a57 11534 vfp_output_fldmd (f, SP_REGNUM,
7b78e739 11535 (start_reg - FIRST_VFP_REGNUM) / 2,
11536 (reg - start_reg) / 2);
a2cd141b 11537 }
755eb2b4 11538 if (TARGET_IWMMXT)
11539 for (reg = FIRST_IWMMXT_REGNUM; reg <= LAST_IWMMXT_REGNUM; reg++)
3072d30e 11540 if (df_regs_ever_live_p (reg) && !call_used_regs[reg])
9d63835d 11541 asm_fprintf (f, "\twldrd\t%r, [%r], #8\n", reg, SP_REGNUM);
755eb2b4 11542
e27ad2d5 11543 /* If we can, restore the LR into the PC. */
8b438b4f 11544 if (ARM_FUNC_TYPE (func_type) != ARM_FT_INTERWORKED
11545 && (TARGET_ARM || ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL)
25f905c2 11546 && !IS_STACKALIGN (func_type)
e27ad2d5 11547 && really_return
11548 && current_function_pretend_args_size == 0
4c44712e 11549 && saved_regs_mask & (1 << LR_REGNUM)
11550 && !current_function_calls_eh_return)
8cd42699 11551 {
89b30d75 11552 saved_regs_mask &= ~ (1 << LR_REGNUM);
11553 saved_regs_mask |= (1 << PC_REGNUM);
8b438b4f 11554 rfe = IS_INTERRUPT (func_type);
e27ad2d5 11555 }
8b438b4f 11556 else
11557 rfe = 0;
cffb2a26 11558
e27ad2d5 11559 /* Load the registers off the stack. If we only have one register
25f905c2 11560 to load use the LDR instruction - it is faster. For Thumb-2
11561 always use pop and the assembler will pick the best instruction.*/
8b438b4f 11562 if (TARGET_ARM && saved_regs_mask == (1 << LR_REGNUM)
11563 && !IS_INTERRUPT(func_type))
e27ad2d5 11564 {
4c44712e 11565 asm_fprintf (f, "\tldr\t%r, [%r], #4\n", LR_REGNUM, SP_REGNUM);
8cd42699 11566 }
89b30d75 11567 else if (saved_regs_mask)
8cc5c6da 11568 {
11569 if (saved_regs_mask & (1 << SP_REGNUM))
11570 /* Note - write back to the stack register is not enabled
a361b456 11571 (i.e. "ldmfd sp!..."). We know that the stack pointer is
8cc5c6da 11572 in the list of registers and if we add writeback the
11573 instruction becomes UNPREDICTABLE. */
8b438b4f 11574 print_multi_reg (f, "ldmfd\t%r, ", SP_REGNUM, saved_regs_mask,
11575 rfe);
25f905c2 11576 else if (TARGET_ARM)
8b438b4f 11577 print_multi_reg (f, "ldmfd\t%r!, ", SP_REGNUM, saved_regs_mask,
11578 rfe);
8cc5c6da 11579 else
8b438b4f 11580 print_multi_reg (f, "pop\t", SP_REGNUM, saved_regs_mask, 0);
8cc5c6da 11581 }
e27ad2d5 11582
11583 if (current_function_pretend_args_size)
8cd42699 11584 {
e27ad2d5 11585 /* Unwind the pre-pushed regs. */
11586 operands[0] = operands[1] = stack_pointer_rtx;
11587 operands[2] = GEN_INT (current_function_pretend_args_size);
11588 output_add_immediate (operands);
11589 }
11590 }
69120d26 11591
cdf460bd 11592 /* We may have already restored PC directly from the stack. */
025e633f 11593 if (!really_return || saved_regs_mask & (1 << PC_REGNUM))
e27ad2d5 11594 return "";
cffb2a26 11595
4c44712e 11596 /* Stack adjustment for exception handler. */
11597 if (current_function_calls_eh_return)
9e7454d0 11598 asm_fprintf (f, "\tadd\t%r, %r, %r\n", SP_REGNUM, SP_REGNUM,
4c44712e 11599 ARM_EH_STACKADJ_REGNUM);
11600
e27ad2d5 11601 /* Generate the return instruction. */
11602 switch ((int) ARM_FUNC_TYPE (func_type))
11603 {
e27ad2d5 11604 case ARM_FT_ISR:
11605 case ARM_FT_FIQ:
11606 asm_fprintf (f, "\tsubs\t%r, %r, #4\n", PC_REGNUM, LR_REGNUM);
11607 break;
11608
11609 case ARM_FT_EXCEPTION:
11610 asm_fprintf (f, "\tmovs\t%r, %r\n", PC_REGNUM, LR_REGNUM);
11611 break;
11612
11613 case ARM_FT_INTERWORKED:
11614 asm_fprintf (f, "\tbx\t%r\n", LR_REGNUM);
11615 break;
11616
11617 default:
25f905c2 11618 if (IS_STACKALIGN (func_type))
11619 {
11620 /* See comment in arm_expand_prologue. */
11621 asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, 0);
11622 }
f1039640 11623 if (arm_arch5 || arm_arch4t)
11624 asm_fprintf (f, "\tbx\t%r\n", LR_REGNUM);
11625 else
11626 asm_fprintf (f, "\tmov\t%r, %r\n", PC_REGNUM, LR_REGNUM);
e27ad2d5 11627 break;
8cd42699 11628 }
a690ede2 11629
56d27660 11630 return "";
11631}
11632
17d9b0c3 11633static void
ebd88a36 11634arm_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
f9273c43 11635 HOST_WIDE_INT frame_size ATTRIBUTE_UNUSED)
56d27660 11636{
f9273c43 11637 arm_stack_offsets *offsets;
11638
25f905c2 11639 if (TARGET_THUMB1)
cffb2a26 11640 {
afe27f3b 11641 int regno;
11642
11643 /* Emit any call-via-reg trampolines that are needed for v4t support
11644 of call_reg and call_value_reg type insns. */
a52972b8 11645 for (regno = 0; regno < LR_REGNUM; regno++)
afe27f3b 11646 {
11647 rtx label = cfun->machine->call_via[regno];
11648
11649 if (label != NULL)
11650 {
2f14b1f9 11651 switch_to_section (function_section (current_function_decl));
afe27f3b 11652 targetm.asm_out.internal_label (asm_out_file, "L",
11653 CODE_LABEL_NUMBER (label));
11654 asm_fprintf (asm_out_file, "\tbx\t%r\n", regno);
11655 }
11656 }
11657
cffb2a26 11658 /* ??? Probably not safe to set this here, since it assumes that a
11659 function will be emitted as assembly immediately after we generate
11660 RTL for it. This does not happen for inline functions. */
11661 return_used_this_function = 0;
11662 }
25f905c2 11663 else /* TARGET_32BIT */
cffb2a26 11664 {
a7712927 11665 /* We need to take into account any stack-frame rounding. */
f9273c43 11666 offsets = arm_get_frame_offsets ();
a7712927 11667
ed29c566 11668 gcc_assert (!use_return_insn (FALSE, NULL)
11669 || !return_used_this_function
11670 || offsets->saved_regs == offsets->outgoing_args
11671 || frame_pointer_needed);
a690ede2 11672
cffb2a26 11673 /* Reset the ARM-specific per-function variables. */
cffb2a26 11674 after_arm_reorg = 0;
11675 }
a690ede2 11676}
4b6897e9 11677
220d204b 11678/* Generate and emit an insn that we will recognize as a push_multi.
11679 Unfortunately, since this insn does not reflect very well the actual
11680 semantics of the operation, we need to annotate the insn for the benefit
11681 of DWARF2 frame unwind information. */
220d204b 11682static rtx
53f179c0 11683emit_multi_reg_push (unsigned long mask)
4b6897e9 11684{
11685 int num_regs = 0;
5cf3595a 11686 int num_dwarf_regs;
4b6897e9 11687 int i, j;
11688 rtx par;
220d204b 11689 rtx dwarf;
c17534c2 11690 int dwarf_par_index;
220d204b 11691 rtx tmp, reg;
4b6897e9 11692
cffb2a26 11693 for (i = 0; i <= LAST_ARM_REGNUM; i++)
4b6897e9 11694 if (mask & (1 << i))
215b30b3 11695 num_regs++;
4b6897e9 11696
ed29c566 11697 gcc_assert (num_regs && num_regs <= 16);
4b6897e9 11698
5cf3595a 11699 /* We don't record the PC in the dwarf frame information. */
11700 num_dwarf_regs = num_regs;
11701 if (mask & (1 << PC_REGNUM))
11702 num_dwarf_regs--;
11703
c17534c2 11704 /* For the body of the insn we are going to generate an UNSPEC in
a2f10574 11705 parallel with several USEs. This allows the insn to be recognized
c17534c2 11706 by the push_multi pattern in the arm.md file. The insn looks
11707 something like this:
11708
9e7454d0 11709 (parallel [
e1159bbe 11710 (set (mem:BLK (pre_dec:BLK (reg:SI sp)))
11711 (unspec:BLK [(reg:SI r4)] UNSPEC_PUSH_MULT))
c17534c2 11712 (use (reg:SI 11 fp))
11713 (use (reg:SI 12 ip))
11714 (use (reg:SI 14 lr))
11715 (use (reg:SI 15 pc))
11716 ])
11717
11718 For the frame note however, we try to be more explicit and actually
11719 show each register being stored into the stack frame, plus a (single)
11720 decrement of the stack pointer. We do it this way in order to be
11721 friendly to the stack unwinding code, which only wants to see a single
11722 stack decrement per instruction. The RTL we generate for the note looks
11723 something like this:
11724
9e7454d0 11725 (sequence [
c17534c2 11726 (set (reg:SI sp) (plus:SI (reg:SI sp) (const_int -20)))
11727 (set (mem:SI (reg:SI sp)) (reg:SI r4))
11728 (set (mem:SI (plus:SI (reg:SI sp) (const_int 4))) (reg:SI fp))
11729 (set (mem:SI (plus:SI (reg:SI sp) (const_int 8))) (reg:SI ip))
11730 (set (mem:SI (plus:SI (reg:SI sp) (const_int 12))) (reg:SI lr))
c17534c2 11731 ])
11732
11733 This sequence is used both by the code to support stack unwinding for
11734 exceptions handlers and the code to generate dwarf2 frame debugging. */
9e7454d0 11735
76676c8e 11736 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (num_regs));
5cf3595a 11737 dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (num_dwarf_regs + 1));
c17534c2 11738 dwarf_par_index = 1;
4b6897e9 11739
cffb2a26 11740 for (i = 0; i <= LAST_ARM_REGNUM; i++)
4b6897e9 11741 {
11742 if (mask & (1 << i))
11743 {
220d204b 11744 reg = gen_rtx_REG (SImode, i);
11745
4b6897e9 11746 XVECEXP (par, 0, 0)
76676c8e 11747 = gen_rtx_SET (VOIDmode,
788fcce0 11748 gen_frame_mem (BLKmode,
11749 gen_rtx_PRE_DEC (BLKmode,
11750 stack_pointer_rtx)),
76676c8e 11751 gen_rtx_UNSPEC (BLKmode,
220d204b 11752 gen_rtvec (1, reg),
5cf3595a 11753 UNSPEC_PUSH_MULT));
220d204b 11754
5cf3595a 11755 if (i != PC_REGNUM)
11756 {
11757 tmp = gen_rtx_SET (VOIDmode,
788fcce0 11758 gen_frame_mem (SImode, stack_pointer_rtx),
5cf3595a 11759 reg);
11760 RTX_FRAME_RELATED_P (tmp) = 1;
11761 XVECEXP (dwarf, 0, dwarf_par_index) = tmp;
11762 dwarf_par_index++;
11763 }
220d204b 11764
4b6897e9 11765 break;
11766 }
11767 }
11768
11769 for (j = 1, i++; j < num_regs; i++)
11770 {
11771 if (mask & (1 << i))
11772 {
220d204b 11773 reg = gen_rtx_REG (SImode, i);
11774
11775 XVECEXP (par, 0, j) = gen_rtx_USE (VOIDmode, reg);
11776
5cf3595a 11777 if (i != PC_REGNUM)
11778 {
788fcce0 11779 tmp
11780 = gen_rtx_SET (VOIDmode,
11781 gen_frame_mem (SImode,
5cf3595a 11782 plus_constant (stack_pointer_rtx,
11783 4 * j)),
788fcce0 11784 reg);
5cf3595a 11785 RTX_FRAME_RELATED_P (tmp) = 1;
11786 XVECEXP (dwarf, 0, dwarf_par_index++) = tmp;
11787 }
11788
4b6897e9 11789 j++;
11790 }
11791 }
f21249d5 11792
220d204b 11793 par = emit_insn (par);
9e7454d0 11794
0083a3b9 11795 tmp = gen_rtx_SET (VOIDmode,
c17534c2 11796 stack_pointer_rtx,
0083a3b9 11797 plus_constant (stack_pointer_rtx, -4 * num_regs));
c17534c2 11798 RTX_FRAME_RELATED_P (tmp) = 1;
11799 XVECEXP (dwarf, 0, 0) = tmp;
9e7454d0 11800
220d204b 11801 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
11802 REG_NOTES (par));
11803 return par;
f21249d5 11804}
11805
0858d94e 11806/* Calculate the size of the return value that is passed in registers. */
11807static int
11808arm_size_return_regs (void)
11809{
11810 enum machine_mode mode;
11811
11812 if (current_function_return_rtx != 0)
11813 mode = GET_MODE (current_function_return_rtx);
11814 else
11815 mode = DECL_MODE (DECL_RESULT (current_function_decl));
11816
11817 return GET_MODE_SIZE (mode);
11818}
11819
220d204b 11820static rtx
ebd88a36 11821emit_sfm (int base_reg, int count)
f21249d5 11822{
11823 rtx par;
220d204b 11824 rtx dwarf;
11825 rtx tmp, reg;
f21249d5 11826 int i;
11827
76676c8e 11828 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
4cde8e57 11829 dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (count + 1));
220d204b 11830
11831 reg = gen_rtx_REG (XFmode, base_reg++);
76676c8e 11832
11833 XVECEXP (par, 0, 0)
9e7454d0 11834 = gen_rtx_SET (VOIDmode,
788fcce0 11835 gen_frame_mem (BLKmode,
11836 gen_rtx_PRE_DEC (BLKmode,
11837 stack_pointer_rtx)),
76676c8e 11838 gen_rtx_UNSPEC (BLKmode,
220d204b 11839 gen_rtvec (1, reg),
e1159bbe 11840 UNSPEC_PUSH_MULT));
9e7454d0 11841 tmp = gen_rtx_SET (VOIDmode,
788fcce0 11842 gen_frame_mem (XFmode, stack_pointer_rtx), reg);
220d204b 11843 RTX_FRAME_RELATED_P (tmp) = 1;
9e7454d0 11844 XVECEXP (dwarf, 0, 1) = tmp;
11845
f21249d5 11846 for (i = 1; i < count; i++)
220d204b 11847 {
11848 reg = gen_rtx_REG (XFmode, base_reg++);
11849 XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode, reg);
11850
9e7454d0 11851 tmp = gen_rtx_SET (VOIDmode,
788fcce0 11852 gen_frame_mem (XFmode,
11853 plus_constant (stack_pointer_rtx,
11854 i * 12)),
220d204b 11855 reg);
11856 RTX_FRAME_RELATED_P (tmp) = 1;
9e7454d0 11857 XVECEXP (dwarf, 0, i + 1) = tmp;
220d204b 11858 }
f21249d5 11859
4cde8e57 11860 tmp = gen_rtx_SET (VOIDmode,
11861 stack_pointer_rtx,
0083a3b9 11862 plus_constant (stack_pointer_rtx, -12 * count));
11863
4cde8e57 11864 RTX_FRAME_RELATED_P (tmp) = 1;
11865 XVECEXP (dwarf, 0, 0) = tmp;
11866
220d204b 11867 par = emit_insn (par);
11868 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
11869 REG_NOTES (par));
11870 return par;
4b6897e9 11871}
11872
a2cd141b 11873
ef5bbe67 11874/* Return true if the current function needs to save/restore LR. */
11875
11876static bool
11877thumb_force_lr_save (void)
11878{
11879 return !cfun->machine->lr_save_eliminated
11880 && (!leaf_function_p ()
11881 || thumb_far_jump_used_p ()
3072d30e 11882 || df_regs_ever_live_p (LR_REGNUM));
ef5bbe67 11883}
11884
11885
9966e02f 11886/* Compute the distance from register FROM to register TO.
11887 These can be the arg pointer (26), the soft frame pointer (25),
11888 the stack pointer (13) or the hard frame pointer (11).
4c44712e 11889 In thumb mode r7 is used as the soft frame pointer, if needed.
9966e02f 11890 Typical stack layout looks like this:
11891
11892 old stack pointer -> | |
11893 ----
11894 | | \
11895 | | saved arguments for
11896 | | vararg functions
11897 | | /
11898 --
11899 hard FP & arg pointer -> | | \
11900 | | stack
11901 | | frame
11902 | | /
11903 --
11904 | | \
11905 | | call saved
11906 | | registers
11907 soft frame pointer -> | | /
11908 --
11909 | | \
11910 | | local
11911 | | variables
f90b51f1 11912 locals base pointer -> | | /
9966e02f 11913 --
11914 | | \
11915 | | outgoing
11916 | | arguments
11917 current stack pointer -> | | /
11918 --
11919
28c2d844 11920 For a given function some or all of these stack components
9966e02f 11921 may not be needed, giving rise to the possibility of
11922 eliminating some of the registers.
11923
e3e08e7f 11924 The values returned by this function must reflect the behavior
9966e02f 11925 of arm_expand_prologue() and arm_compute_save_reg_mask().
11926
11927 The sign of the number returned reflects the direction of stack
11928 growth, so the values are positive for all eliminations except
f9273c43 11929 from the soft frame pointer to the hard frame pointer.
11930
11931 SFP may point just inside the local variables block to ensure correct
11932 alignment. */
11933
11934
11935/* Calculate stack offsets. These are used to calculate register elimination
11936 offsets and in prologue/epilogue code. */
11937
11938static arm_stack_offsets *
11939arm_get_frame_offsets (void)
9966e02f 11940{
f9273c43 11941 struct arm_stack_offsets *offsets;
9966e02f 11942 unsigned long func_type;
f9273c43 11943 int leaf;
f9273c43 11944 int saved;
11945 HOST_WIDE_INT frame_size;
11946
11947 offsets = &cfun->machine->stack_offsets;
9e7454d0 11948
f9273c43 11949 /* We need to know if we are a leaf function. Unfortunately, it
11950 is possible to be called after start_sequence has been called,
11951 which causes get_insns to return the insns for the sequence,
11952 not the function, which will cause leaf_function_p to return
11953 the incorrect result.
9966e02f 11954
f9273c43 11955 to know about leaf functions once reload has completed, and the
11956 frame size cannot be changed after that time, so we can safely
11957 use the cached value. */
11958
11959 if (reload_completed)
11960 return offsets;
11961
af6ed417 11962 /* Initially this is the size of the local variables. It will translated
11963 into an offset once we have determined the size of preceding data. */
f9273c43 11964 frame_size = ROUND_UP_WORD (get_frame_size ());
11965
11966 leaf = leaf_function_p ();
11967
11968 /* Space for variadic functions. */
11969 offsets->saved_args = current_function_pretend_args_size;
11970
25f905c2 11971 /* In Thumb mode this is incorrect, but never used. */
f9273c43 11972 offsets->frame = offsets->saved_args + (frame_pointer_needed ? 4 : 0);
11973
25f905c2 11974 if (TARGET_32BIT)
9966e02f 11975 {
f9273c43 11976 unsigned int regno;
ba3d677f 11977
f9273c43 11978 saved = bit_count (arm_compute_save_reg_mask ()) * 4;
755eb2b4 11979
f9273c43 11980 /* We know that SP will be doubleword aligned on entry, and we must
11981 preserve that condition at any subroutine call. We also require the
11982 soft frame pointer to be doubleword aligned. */
11983
11984 if (TARGET_REALLY_IWMMXT)
a2cd141b 11985 {
f9273c43 11986 /* Check for the call-saved iWMMXt registers. */
11987 for (regno = FIRST_IWMMXT_REGNUM;
11988 regno <= LAST_IWMMXT_REGNUM;
11989 regno++)
3072d30e 11990 if (df_regs_ever_live_p (regno) && ! call_used_regs[regno])
f9273c43 11991 saved += 8;
11992 }
11993
11994 func_type = arm_current_func_type ();
11995 if (! IS_VOLATILE (func_type))
11996 {
11997 /* Space for saved FPA registers. */
11998 for (regno = FIRST_FPA_REGNUM; regno <= LAST_FPA_REGNUM; regno++)
3072d30e 11999 if (df_regs_ever_live_p (regno) && ! call_used_regs[regno])
f9273c43 12000 saved += 12;
12001
12002 /* Space for saved VFP registers. */
12003 if (TARGET_HARD_FLOAT && TARGET_VFP)
7b78e739 12004 saved += arm_get_vfp_saved_size ();
a2cd141b 12005 }
f9273c43 12006 }
25f905c2 12007 else /* TARGET_THUMB1 */
f9273c43 12008 {
25f905c2 12009 saved = bit_count (thumb1_compute_save_reg_mask ()) * 4;
f9273c43 12010 if (TARGET_BACKTRACE)
237533cc 12011 saved += 16;
f9273c43 12012 }
a2cd141b 12013
f9273c43 12014 /* Saved registers include the stack frame. */
12015 offsets->saved_regs = offsets->saved_args + saved;
150502c9 12016 offsets->soft_frame = offsets->saved_regs + CALLER_INTERWORKING_SLOT_SIZE;
f9273c43 12017 /* A leaf function does not need any stack alignment if it has nothing
12018 on the stack. */
12019 if (leaf && frame_size == 0)
12020 {
12021 offsets->outgoing_args = offsets->soft_frame;
a650636a 12022 offsets->locals_base = offsets->soft_frame;
f9273c43 12023 return offsets;
12024 }
12025
12026 /* Ensure SFP has the correct alignment. */
12027 if (ARM_DOUBLEWORD_ALIGN
12028 && (offsets->soft_frame & 7))
12029 offsets->soft_frame += 4;
12030
f90b51f1 12031 offsets->locals_base = offsets->soft_frame + frame_size;
12032 offsets->outgoing_args = (offsets->locals_base
12033 + current_function_outgoing_args_size);
f9273c43 12034
12035 if (ARM_DOUBLEWORD_ALIGN)
12036 {
12037 /* Ensure SP remains doubleword aligned. */
12038 if (offsets->outgoing_args & 7)
12039 offsets->outgoing_args += 4;
ed29c566 12040 gcc_assert (!(offsets->outgoing_args & 7));
9966e02f 12041 }
12042
f9273c43 12043 return offsets;
12044}
12045
12046
af6ed417 12047/* Calculate the relative offsets for the different stack pointers. Positive
f9273c43 12048 offsets are in the direction of stack growth. */
12049
30e9913f 12050HOST_WIDE_INT
f9273c43 12051arm_compute_initial_elimination_offset (unsigned int from, unsigned int to)
12052{
12053 arm_stack_offsets *offsets;
12054
12055 offsets = arm_get_frame_offsets ();
9966e02f 12056
9966e02f 12057 /* OK, now we have enough information to compute the distances.
12058 There must be an entry in these switch tables for each pair
12059 of registers in ELIMINABLE_REGS, even if some of the entries
12060 seem to be redundant or useless. */
12061 switch (from)
12062 {
12063 case ARG_POINTER_REGNUM:
12064 switch (to)
12065 {
12066 case THUMB_HARD_FRAME_POINTER_REGNUM:
12067 return 0;
12068
12069 case FRAME_POINTER_REGNUM:
12070 /* This is the reverse of the soft frame pointer
12071 to hard frame pointer elimination below. */
f9273c43 12072 return offsets->soft_frame - offsets->saved_args;
9966e02f 12073
12074 case ARM_HARD_FRAME_POINTER_REGNUM:
12075 /* If there is no stack frame then the hard
12076 frame pointer and the arg pointer coincide. */
f9273c43 12077 if (offsets->frame == offsets->saved_regs)
9966e02f 12078 return 0;
4ee9c684 12079 /* FIXME: Not sure about this. Maybe we should always return 0 ? */
12080 return (frame_pointer_needed
12081 && cfun->static_chain_decl != NULL
12082 && ! cfun->machine->uses_anonymous_args) ? 4 : 0;
9966e02f 12083
12084 case STACK_POINTER_REGNUM:
12085 /* If nothing has been pushed on the stack at all
12086 then this will return -4. This *is* correct! */
f9273c43 12087 return offsets->outgoing_args - (offsets->saved_args + 4);
9966e02f 12088
12089 default:
ed29c566 12090 gcc_unreachable ();
9966e02f 12091 }
ed29c566 12092 gcc_unreachable ();
9966e02f 12093
12094 case FRAME_POINTER_REGNUM:
12095 switch (to)
12096 {
12097 case THUMB_HARD_FRAME_POINTER_REGNUM:
12098 return 0;
12099
12100 case ARM_HARD_FRAME_POINTER_REGNUM:
12101 /* The hard frame pointer points to the top entry in the
12102 stack frame. The soft frame pointer to the bottom entry
12103 in the stack frame. If there is no stack frame at all,
12104 then they are identical. */
f9273c43 12105
12106 return offsets->frame - offsets->soft_frame;
9966e02f 12107
12108 case STACK_POINTER_REGNUM:
f9273c43 12109 return offsets->outgoing_args - offsets->soft_frame;
9966e02f 12110
12111 default:
ed29c566 12112 gcc_unreachable ();
9966e02f 12113 }
ed29c566 12114 gcc_unreachable ();
9966e02f 12115
12116 default:
12117 /* You cannot eliminate from the stack pointer.
12118 In theory you could eliminate from the hard frame
12119 pointer to the stack pointer, but this will never
12120 happen, since if a stack frame is not needed the
12121 hard frame pointer will never be used. */
ed29c566 12122 gcc_unreachable ();
9966e02f 12123 }
12124}
12125
a7712927 12126
542d5028 12127/* Emit RTL to save coprocessor registers on function entry. Returns the
25f905c2 12128 number of bytes pushed. */
12129
12130static int
12131arm_save_coproc_regs(void)
12132{
12133 int saved_size = 0;
12134 unsigned reg;
12135 unsigned start_reg;
12136 rtx insn;
12137
12138 for (reg = LAST_IWMMXT_REGNUM; reg >= FIRST_IWMMXT_REGNUM; reg--)
3072d30e 12139 if (df_regs_ever_live_p (reg) && ! call_used_regs[reg])
25f905c2 12140 {
12141 insn = gen_rtx_PRE_DEC (V2SImode, stack_pointer_rtx);
12142 insn = gen_rtx_MEM (V2SImode, insn);
12143 insn = emit_set_insn (insn, gen_rtx_REG (V2SImode, reg));
12144 RTX_FRAME_RELATED_P (insn) = 1;
12145 saved_size += 8;
12146 }
12147
12148 /* Save any floating point call-saved registers used by this
12149 function. */
12150 if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
12151 {
12152 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
3072d30e 12153 if (df_regs_ever_live_p (reg) && !call_used_regs[reg])
25f905c2 12154 {
12155 insn = gen_rtx_PRE_DEC (XFmode, stack_pointer_rtx);
12156 insn = gen_rtx_MEM (XFmode, insn);
12157 insn = emit_set_insn (insn, gen_rtx_REG (XFmode, reg));
12158 RTX_FRAME_RELATED_P (insn) = 1;
12159 saved_size += 12;
12160 }
12161 }
12162 else
12163 {
12164 start_reg = LAST_FPA_REGNUM;
12165
12166 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
12167 {
3072d30e 12168 if (df_regs_ever_live_p (reg) && !call_used_regs[reg])
25f905c2 12169 {
12170 if (start_reg - reg == 3)
12171 {
12172 insn = emit_sfm (reg, 4);
12173 RTX_FRAME_RELATED_P (insn) = 1;
12174 saved_size += 48;
12175 start_reg = reg - 1;
12176 }
12177 }
12178 else
12179 {
12180 if (start_reg != reg)
12181 {
12182 insn = emit_sfm (reg + 1, start_reg - reg);
12183 RTX_FRAME_RELATED_P (insn) = 1;
12184 saved_size += (start_reg - reg) * 12;
12185 }
12186 start_reg = reg - 1;
12187 }
12188 }
12189
12190 if (start_reg != reg)
12191 {
12192 insn = emit_sfm (reg + 1, start_reg - reg);
12193 saved_size += (start_reg - reg) * 12;
12194 RTX_FRAME_RELATED_P (insn) = 1;
12195 }
12196 }
12197 if (TARGET_HARD_FLOAT && TARGET_VFP)
12198 {
12199 start_reg = FIRST_VFP_REGNUM;
12200
12201 for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2)
12202 {
3072d30e 12203 if ((!df_regs_ever_live_p (reg) || call_used_regs[reg])
12204 && (!df_regs_ever_live_p (reg + 1) || call_used_regs[reg + 1]))
25f905c2 12205 {
12206 if (start_reg != reg)
12207 saved_size += vfp_emit_fstmd (start_reg,
12208 (reg - start_reg) / 2);
12209 start_reg = reg + 2;
12210 }
12211 }
12212 if (start_reg != reg)
12213 saved_size += vfp_emit_fstmd (start_reg,
12214 (reg - start_reg) / 2);
12215 }
12216 return saved_size;
12217}
12218
12219
12220/* Set the Thumb frame pointer from the stack pointer. */
12221
12222static void
12223thumb_set_frame_pointer (arm_stack_offsets *offsets)
12224{
12225 HOST_WIDE_INT amount;
12226 rtx insn, dwarf;
12227
12228 amount = offsets->outgoing_args - offsets->locals_base;
12229 if (amount < 1024)
12230 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
12231 stack_pointer_rtx, GEN_INT (amount)));
12232 else
12233 {
12234 emit_insn (gen_movsi (hard_frame_pointer_rtx, GEN_INT (amount)));
12235 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
12236 hard_frame_pointer_rtx,
12237 stack_pointer_rtx));
12238 dwarf = gen_rtx_SET (VOIDmode, hard_frame_pointer_rtx,
12239 plus_constant (stack_pointer_rtx, amount));
12240 RTX_FRAME_RELATED_P (dwarf) = 1;
12241 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
12242 REG_NOTES (insn));
12243 }
12244
12245 RTX_FRAME_RELATED_P (insn) = 1;
12246}
12247
12248/* Generate the prologue instructions for entry into an ARM or Thumb-2
12249 function. */
4b6897e9 12250void
ebd88a36 12251arm_expand_prologue (void)
4b6897e9 12252{
e27ad2d5 12253 rtx amount;
220d204b 12254 rtx insn;
209368fd 12255 rtx ip_rtx;
e27ad2d5 12256 unsigned long live_regs_mask;
12257 unsigned long func_type;
209368fd 12258 int fp_offset = 0;
9966e02f 12259 int saved_pretend_args = 0;
f9273c43 12260 int saved_regs = 0;
816c161a 12261 unsigned HOST_WIDE_INT args_to_push;
f9273c43 12262 arm_stack_offsets *offsets;
dd3c06e0 12263
e27ad2d5 12264 func_type = arm_current_func_type ();
4b6897e9 12265
9011416b 12266 /* Naked functions don't have prologues. */
e27ad2d5 12267 if (IS_NAKED (func_type))
9011416b 12268 return;
12269
9966e02f 12270 /* Make a copy of c_f_p_a_s as we may need to modify it locally. */
12271 args_to_push = current_function_pretend_args_size;
9e7454d0 12272
e27ad2d5 12273 /* Compute which register we will have to save onto the stack. */
12274 live_regs_mask = arm_compute_save_reg_mask ();
4b6897e9 12275
209368fd 12276 ip_rtx = gen_rtx_REG (SImode, IP_REGNUM);
dd3c06e0 12277
25f905c2 12278 if (IS_STACKALIGN (func_type))
12279 {
12280 rtx dwarf;
12281 rtx r0;
12282 rtx r1;
12283 /* Handle a word-aligned stack pointer. We generate the following:
12284
12285 mov r0, sp
12286 bic r1, r0, #7
12287 mov sp, r1
12288 <save and restore r0 in normal prologue/epilogue>
12289 mov sp, r0
12290 bx lr
12291
12292 The unwinder doesn't need to know about the stack realignment.
12293 Just tell it we saved SP in r0. */
12294 gcc_assert (TARGET_THUMB2 && !arm_arch_notm && args_to_push == 0);
12295
12296 r0 = gen_rtx_REG (SImode, 0);
12297 r1 = gen_rtx_REG (SImode, 1);
12298 dwarf = gen_rtx_UNSPEC (SImode, NULL_RTVEC, UNSPEC_STACK_ALIGN);
12299 dwarf = gen_rtx_SET (VOIDmode, r0, dwarf);
12300 insn = gen_movsi (r0, stack_pointer_rtx);
12301 RTX_FRAME_RELATED_P (insn) = 1;
12302 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
12303 dwarf, REG_NOTES (insn));
12304 emit_insn (insn);
12305 emit_insn (gen_andsi3 (r1, r0, GEN_INT (~(HOST_WIDE_INT)7)));
12306 emit_insn (gen_movsi (stack_pointer_rtx, r1));
12307 }
12308
12309 if (frame_pointer_needed && TARGET_ARM)
4b6897e9 12310 {
2d9065d3 12311 if (IS_INTERRUPT (func_type))
12312 {
12313 /* Interrupt functions must not corrupt any registers.
12314 Creating a frame pointer however, corrupts the IP
12315 register, so we must push it first. */
12316 insn = emit_multi_reg_push (1 << IP_REGNUM);
aa1ae31c 12317
12318 /* Do not set RTX_FRAME_RELATED_P on this insn.
12319 The dwarf stack unwinding code only wants to see one
12320 stack decrement per function, and this is not it. If
12321 this instruction is labeled as being part of the frame
12322 creation sequence then dwarf2out_frame_debug_expr will
ed29c566 12323 die when it encounters the assignment of IP to FP
aa1ae31c 12324 later on, since the use of SP here establishes SP as
12325 the CFA register and not IP.
12326
12327 Anyway this instruction is not really part of the stack
12328 frame creation although it is part of the prologue. */
2d9065d3 12329 }
12330 else if (IS_NESTED (func_type))
209368fd 12331 {
12332 /* The Static chain register is the same as the IP register
12333 used as a scratch register during stack frame creation.
12334 To get around this need to find somewhere to store IP
12335 whilst the frame is being created. We try the following
12336 places in order:
9e7454d0 12337
e27ad2d5 12338 1. The last argument register.
209368fd 12339 2. A slot on the stack above the frame. (This only
12340 works if the function is not a varargs function).
9966e02f 12341 3. Register r3, after pushing the argument registers
12342 onto the stack.
e27ad2d5 12343
9b536fa6 12344 Note - we only need to tell the dwarf2 backend about the SP
12345 adjustment in the second variant; the static chain register
12346 doesn't need to be unwound, as it doesn't contain a value
12347 inherited from the caller. */
dd3c06e0 12348
3072d30e 12349 if (df_regs_ever_live_p (3) == false)
0083a3b9 12350 insn = emit_set_insn (gen_rtx_REG (SImode, 3), ip_rtx);
9966e02f 12351 else if (args_to_push == 0)
209368fd 12352 {
9b536fa6 12353 rtx dwarf;
9b536fa6 12354
0083a3b9 12355 insn = gen_rtx_PRE_DEC (SImode, stack_pointer_rtx);
12356 insn = emit_set_insn (gen_frame_mem (SImode, insn), ip_rtx);
209368fd 12357 fp_offset = 4;
9b536fa6 12358
12359 /* Just tell the dwarf backend that we adjusted SP. */
12360 dwarf = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
0083a3b9 12361 plus_constant (stack_pointer_rtx,
12362 -fp_offset));
9b536fa6 12363 RTX_FRAME_RELATED_P (insn) = 1;
12364 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
12365 dwarf, REG_NOTES (insn));
209368fd 12366 }
12367 else
9966e02f 12368 {
12369 /* Store the args on the stack. */
71904594 12370 if (cfun->machine->uses_anonymous_args)
9966e02f 12371 insn = emit_multi_reg_push
12372 ((0xf0 >> (args_to_push / 4)) & 0xf);
12373 else
12374 insn = emit_insn
9e7454d0 12375 (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
9966e02f 12376 GEN_INT (- args_to_push)));
12377
12378 RTX_FRAME_RELATED_P (insn) = 1;
12379
12380 saved_pretend_args = 1;
12381 fp_offset = args_to_push;
12382 args_to_push = 0;
12383
12384 /* Now reuse r3 to preserve IP. */
0083a3b9 12385 emit_set_insn (gen_rtx_REG (SImode, 3), ip_rtx);
9966e02f 12386 }
209368fd 12387 }
12388
0083a3b9 12389 insn = emit_set_insn (ip_rtx,
12390 plus_constant (stack_pointer_rtx, fp_offset));
5209dc22 12391 RTX_FRAME_RELATED_P (insn) = 1;
4b6897e9 12392 }
12393
9966e02f 12394 if (args_to_push)
4b6897e9 12395 {
e27ad2d5 12396 /* Push the argument registers, or reserve space for them. */
71904594 12397 if (cfun->machine->uses_anonymous_args)
220d204b 12398 insn = emit_multi_reg_push
9966e02f 12399 ((0xf0 >> (args_to_push / 4)) & 0xf);
4b6897e9 12400 else
220d204b 12401 insn = emit_insn
9e7454d0 12402 (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
9966e02f 12403 GEN_INT (- args_to_push)));
220d204b 12404 RTX_FRAME_RELATED_P (insn) = 1;
4b6897e9 12405 }
12406
000c5098 12407 /* If this is an interrupt service routine, and the link register
12408 is going to be pushed, and we are not creating a stack frame,
12409 (which would involve an extra push of IP and a pop in the epilogue)
12410 subtracting four from LR now will mean that the function return
12411 can be done with a single instruction. */
4a5f62e2 12412 if ((func_type == ARM_FT_ISR || func_type == ARM_FT_FIQ)
000c5098 12413 && (live_regs_mask & (1 << LR_REGNUM)) != 0
8b438b4f 12414 && ! frame_pointer_needed
12415 && TARGET_ARM)
0083a3b9 12416 {
12417 rtx lr = gen_rtx_REG (SImode, LR_REGNUM);
12418
12419 emit_set_insn (lr, plus_constant (lr, -4));
12420 }
4a5f62e2 12421
4b6897e9 12422 if (live_regs_mask)
12423 {
220d204b 12424 insn = emit_multi_reg_push (live_regs_mask);
f9273c43 12425 saved_regs += bit_count (live_regs_mask) * 4;
220d204b 12426 RTX_FRAME_RELATED_P (insn) = 1;
4b6897e9 12427 }
cffb2a26 12428
e27ad2d5 12429 if (! IS_VOLATILE (func_type))
25f905c2 12430 saved_regs += arm_save_coproc_regs ();
f21249d5 12431
25f905c2 12432 if (frame_pointer_needed && TARGET_ARM)
12433 {
12434 /* Create the new frame pointer. */
a2cd141b 12435 {
25f905c2 12436 insn = GEN_INT (-(4 + args_to_push + fp_offset));
12437 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx, ip_rtx, insn));
12438 RTX_FRAME_RELATED_P (insn) = 1;
a2cd141b 12439
25f905c2 12440 if (IS_NESTED (func_type))
a2cd141b 12441 {
25f905c2 12442 /* Recover the static chain register. */
3072d30e 12443 if (!df_regs_ever_live_p (3)
25f905c2 12444 || saved_pretend_args)
12445 insn = gen_rtx_REG (SImode, 3);
12446 else /* if (current_function_pretend_args_size == 0) */
a2cd141b 12447 {
25f905c2 12448 insn = plus_constant (hard_frame_pointer_rtx, 4);
12449 insn = gen_frame_mem (SImode, insn);
a2cd141b 12450 }
25f905c2 12451 emit_set_insn (ip_rtx, insn);
12452 /* Add a USE to stop propagate_one_insn() from barfing. */
12453 emit_insn (gen_prologue_use (ip_rtx));
a2cd141b 12454 }
209368fd 12455 }
220d204b 12456 }
4b6897e9 12457
f9273c43 12458 offsets = arm_get_frame_offsets ();
12459 if (offsets->outgoing_args != offsets->saved_args + saved_regs)
4b6897e9 12460 {
4f8f8a17 12461 /* This add can produce multiple insns for a large constant, so we
12462 need to get tricky. */
12463 rtx last = get_last_insn ();
f9273c43 12464
12465 amount = GEN_INT (offsets->saved_args + saved_regs
12466 - offsets->outgoing_args);
12467
220d204b 12468 insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
12469 amount));
4f8f8a17 12470 do
12471 {
12472 last = last ? NEXT_INSN (last) : get_insns ();
12473 RTX_FRAME_RELATED_P (last) = 1;
12474 }
12475 while (last != insn);
3060ab98 12476
12477 /* If the frame pointer is needed, emit a special barrier that
12478 will prevent the scheduler from moving stores to the frame
12479 before the stack adjustment. */
12480 if (frame_pointer_needed)
4c58c898 12481 insn = emit_insn (gen_stack_tie (stack_pointer_rtx,
12482 hard_frame_pointer_rtx));
4b6897e9 12483 }
12484
ea32a06e 12485
25f905c2 12486 if (frame_pointer_needed && TARGET_THUMB2)
12487 thumb_set_frame_pointer (offsets);
12488
2cb7d577 12489 if (flag_pic && arm_pic_register != INVALID_REGNUM)
25f905c2 12490 {
12491 unsigned long mask;
12492
12493 mask = live_regs_mask;
12494 mask &= THUMB2_WORK_REGS;
12495 if (!IS_NESTED (func_type))
12496 mask |= (1 << IP_REGNUM);
12497 arm_load_pic_register (mask);
12498 }
ea32a06e 12499
4b6897e9 12500 /* If we are profiling, make sure no instructions are scheduled before
9888ad6d 12501 the call to mcount. Similarly if the user has requested no
363d487e 12502 scheduling in the prolog. Similarly if we want non-call exceptions
12503 using the EABI unwinder, to prevent faulting instructions from being
12504 swapped with a stack adjustment. */
12505 if (current_function_profile || !TARGET_SCHED_PROLOG
12506 || (ARM_EABI_UNWIND_TABLES && flag_non_call_exceptions))
4b6897e9 12507 emit_insn (gen_blockage ());
89b30d75 12508
12509 /* If the link register is being kept alive, with the return address in it,
12510 then make sure that it does not get reused by the ce2 pass. */
12511 if ((live_regs_mask & (1 << LR_REGNUM)) == 0)
3072d30e 12512 cfun->machine->lr_save_eliminated = 1;
4b6897e9 12513}
8cd42699 12514\f
25f905c2 12515/* Print condition code to STREAM. Helper function for arm_print_operand. */
12516static void
12517arm_print_condition (FILE *stream)
12518{
12519 if (arm_ccfsm_state == 3 || arm_ccfsm_state == 4)
12520 {
12521 /* Branch conversion is not implemented for Thumb-2. */
12522 if (TARGET_THUMB)
12523 {
12524 output_operand_lossage ("predicated Thumb instruction");
12525 return;
12526 }
12527 if (current_insn_predicate != NULL)
12528 {
12529 output_operand_lossage
12530 ("predicated instruction in conditional sequence");
12531 return;
12532 }
12533
12534 fputs (arm_condition_codes[arm_current_cc], stream);
12535 }
12536 else if (current_insn_predicate)
12537 {
12538 enum arm_cond_code code;
12539
12540 if (TARGET_THUMB1)
12541 {
12542 output_operand_lossage ("predicated Thumb instruction");
12543 return;
12544 }
12545
12546 code = get_arm_condition_code (current_insn_predicate);
12547 fputs (arm_condition_codes[code], stream);
12548 }
12549}
12550
12551
f6b01912 12552/* If CODE is 'd', then the X is a condition operand and the instruction
12553 should only be executed if the condition is true.
01cc3b75 12554 if CODE is 'D', then the X is a condition operand and the instruction
f6b01912 12555 should only be executed if the condition is false: however, if the mode
12556 of the comparison is CCFPEmode, then always execute the instruction -- we
12557 do this because in these circumstances !GE does not necessarily imply LT;
12558 in these cases the instruction pattern will take care to make sure that
12559 an instruction containing %d will follow, thereby undoing the effects of
01cc3b75 12560 doing this instruction unconditionally.
f6b01912 12561 If CODE is 'N' then X is a floating point operand that must be negated
12562 before output.
12563 If CODE is 'B' then output a bitwise inverted value of X (a const int).
12564 If X is a REG and CODE is `M', output a ldm/stm style multi-reg. */
f6b01912 12565void
ebd88a36 12566arm_print_operand (FILE *stream, rtx x, int code)
f6b01912 12567{
12568 switch (code)
12569 {
12570 case '@':
fdb4a2ea 12571 fputs (ASM_COMMENT_START, stream);
f6b01912 12572 return;
12573
cffb2a26 12574 case '_':
12575 fputs (user_label_prefix, stream);
12576 return;
9e7454d0 12577
f6b01912 12578 case '|':
fdb4a2ea 12579 fputs (REGISTER_PREFIX, stream);
f6b01912 12580 return;
12581
12582 case '?':
25f905c2 12583 arm_print_condition (stream);
12584 return;
0d66636f 12585
25f905c2 12586 case '(':
12587 /* Nothing in unified syntax, otherwise the current condition code. */
12588 if (!TARGET_UNIFIED_ASM)
12589 arm_print_condition (stream);
12590 break;
12591
12592 case ')':
12593 /* The current condition code in unified syntax, otherwise nothing. */
12594 if (TARGET_UNIFIED_ASM)
12595 arm_print_condition (stream);
12596 break;
12597
12598 case '.':
12599 /* The current condition code for a condition code setting instruction.
542d5028 12600 Preceded by 's' in unified syntax, otherwise followed by 's'. */
25f905c2 12601 if (TARGET_UNIFIED_ASM)
12602 {
12603 fputc('s', stream);
12604 arm_print_condition (stream);
0d66636f 12605 }
25f905c2 12606 else
0d66636f 12607 {
25f905c2 12608 arm_print_condition (stream);
12609 fputc('s', stream);
0d66636f 12610 }
f6b01912 12611 return;
12612
25f905c2 12613 case '!':
12614 /* If the instruction is conditionally executed then print
12615 the current condition code, otherwise print 's'. */
12616 gcc_assert (TARGET_THUMB2 && TARGET_UNIFIED_ASM);
12617 if (current_insn_predicate)
12618 arm_print_condition (stream);
12619 else
12620 fputc('s', stream);
12621 break;
12622
d98a3884 12623 /* %# is a "break" sequence. It doesn't output anything, but is used to
12624 seperate e.g. operand numbers from following text, if that text consists
12625 of further digits which we don't want to be part of the operand
12626 number. */
12627 case '#':
12628 return;
12629
f6b01912 12630 case 'N':
12631 {
12632 REAL_VALUE_TYPE r;
12633 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
12634 r = REAL_VALUE_NEGATE (r);
12635 fprintf (stream, "%s", fp_const_from_val (&r));
12636 }
12637 return;
12638
d98a3884 12639 /* An integer without a preceding # sign. */
12640 case 'c':
12641 gcc_assert (GET_CODE (x) == CONST_INT);
12642 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
12643 return;
12644
f6b01912 12645 case 'B':
12646 if (GET_CODE (x) == CONST_INT)
f13e56bb 12647 {
12648 HOST_WIDE_INT val;
215b30b3 12649 val = ARM_SIGN_EXTEND (~INTVAL (x));
b7ecc820 12650 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, val);
f13e56bb 12651 }
f6b01912 12652 else
12653 {
12654 putc ('~', stream);
12655 output_addr_const (stream, x);
12656 }
12657 return;
12658
25f905c2 12659 case 'L':
12660 /* The low 16 bits of an immediate constant. */
12661 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, INTVAL(x) & 0xffff);
12662 return;
12663
f6b01912 12664 case 'i':
12665 fprintf (stream, "%s", arithmetic_instr (x, 1));
12666 return;
12667
7d57ec45 12668 /* Truncate Cirrus shift counts. */
12669 case 's':
12670 if (GET_CODE (x) == CONST_INT)
12671 {
12672 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0x3f);
12673 return;
12674 }
12675 arm_print_operand (stream, x, 0);
12676 return;
12677
f6b01912 12678 case 'I':
12679 fprintf (stream, "%s", arithmetic_instr (x, 0));
12680 return;
12681
12682 case 'S':
12683 {
12684 HOST_WIDE_INT val;
26dff611 12685 const char *shift;
12686
12687 if (!shift_operator (x, SImode))
12688 {
12689 output_operand_lossage ("invalid shift operand");
12690 break;
12691 }
12692
12693 shift = shift_op (x, &val);
f6b01912 12694
4b6897e9 12695 if (shift)
12696 {
26dff611 12697 fprintf (stream, ", %s ", shift);
4b6897e9 12698 if (val == -1)
12699 arm_print_operand (stream, XEXP (x, 1), 0);
12700 else
4840a03a 12701 fprintf (stream, "#" HOST_WIDE_INT_PRINT_DEC, val);
4b6897e9 12702 }
f6b01912 12703 }
12704 return;
12705
cffb2a26 12706 /* An explanation of the 'Q', 'R' and 'H' register operands:
9e7454d0 12707
cffb2a26 12708 In a pair of registers containing a DI or DF value the 'Q'
12709 operand returns the register number of the register containing
5910bb95 12710 the least significant part of the value. The 'R' operand returns
cffb2a26 12711 the register number of the register containing the most
12712 significant part of the value.
9e7454d0 12713
cffb2a26 12714 The 'H' operand returns the higher of the two register numbers.
12715 On a run where WORDS_BIG_ENDIAN is true the 'H' operand is the
5910bb95 12716 same as the 'Q' operand, since the most significant part of the
cffb2a26 12717 value is held in the lower number register. The reverse is true
12718 on systems where WORDS_BIG_ENDIAN is false.
9e7454d0 12719
cffb2a26 12720 The purpose of these operands is to distinguish between cases
12721 where the endian-ness of the values is important (for example
12722 when they are added together), and cases where the endian-ness
12723 is irrelevant, but the order of register operations is important.
12724 For example when loading a value from memory into a register
12725 pair, the endian-ness does not matter. Provided that the value
12726 from the lower memory address is put into the lower numbered
12727 register, and the value from the higher address is put into the
12728 higher numbered register, the load will work regardless of whether
12729 the value being loaded is big-wordian or little-wordian. The
12730 order of the two register loads can matter however, if the address
12731 of the memory location is actually held in one of the registers
12732 being overwritten by the load. */
cb88963f 12733 case 'Q':
47378eff 12734 if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM)
12735 {
12736 output_operand_lossage ("invalid operand for code '%c'", code);
12737 return;
12738 }
12739
cffb2a26 12740 asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 1 : 0));
cb88963f 12741 return;
12742
f6b01912 12743 case 'R':
47378eff 12744 if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM)
12745 {
12746 output_operand_lossage ("invalid operand for code '%c'", code);
12747 return;
12748 }
12749
cffb2a26 12750 asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 0 : 1));
12751 return;
12752
12753 case 'H':
47378eff 12754 if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM)
12755 {
12756 output_operand_lossage ("invalid operand for code '%c'", code);
12757 return;
12758 }
12759
cffb2a26 12760 asm_fprintf (stream, "%r", REGNO (x) + 1);
f6b01912 12761 return;
12762
d98a3884 12763 case 'J':
12764 if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM)
12765 {
12766 output_operand_lossage ("invalid operand for code '%c'", code);
12767 return;
12768 }
12769
12770 asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 3 : 2));
12771 return;
12772
12773 case 'K':
12774 if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM)
12775 {
12776 output_operand_lossage ("invalid operand for code '%c'", code);
12777 return;
12778 }
12779
12780 asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 2 : 3));
12781 return;
12782
f6b01912 12783 case 'm':
9e7454d0 12784 asm_fprintf (stream, "%r",
cffb2a26 12785 GET_CODE (XEXP (x, 0)) == REG
12786 ? REGNO (XEXP (x, 0)) : REGNO (XEXP (XEXP (x, 0), 0)));
f6b01912 12787 return;
12788
12789 case 'M':
caceeb43 12790 asm_fprintf (stream, "{%r-%r}",
cffb2a26 12791 REGNO (x),
36837fde 12792 REGNO (x) + ARM_NUM_REGS (GET_MODE (x)) - 1);
f6b01912 12793 return;
12794
d98a3884 12795 /* Like 'M', but writing doubleword vector registers, for use by Neon
12796 insns. */
12797 case 'h':
12798 {
12799 int regno = (REGNO (x) - FIRST_VFP_REGNUM) / 2;
12800 int numregs = ARM_NUM_REGS (GET_MODE (x)) / 2;
12801 if (numregs == 1)
12802 asm_fprintf (stream, "{d%d}", regno);
12803 else
12804 asm_fprintf (stream, "{d%d-d%d}", regno, regno + numregs - 1);
12805 }
12806 return;
12807
f6b01912 12808 case 'd':
5db468b7 12809 /* CONST_TRUE_RTX means always -- that's the default. */
12810 if (x == const_true_rtx)
cffb2a26 12811 return;
9e7454d0 12812
47378eff 12813 if (!COMPARISON_P (x))
12814 {
12815 output_operand_lossage ("invalid operand for code '%c'", code);
12816 return;
12817 }
12818
58d6528b 12819 fputs (arm_condition_codes[get_arm_condition_code (x)],
12820 stream);
f6b01912 12821 return;
12822
12823 case 'D':
a361b456 12824 /* CONST_TRUE_RTX means not always -- i.e. never. We shouldn't ever
5db468b7 12825 want to do that. */
12826 if (x == const_true_rtx)
47378eff 12827 {
666137bc 12828 output_operand_lossage ("instruction never executed");
47378eff 12829 return;
12830 }
12831 if (!COMPARISON_P (x))
12832 {
12833 output_operand_lossage ("invalid operand for code '%c'", code);
12834 return;
12835 }
cffb2a26 12836
58d6528b 12837 fputs (arm_condition_codes[ARM_INVERSE_CONDITION_CODE
12838 (get_arm_condition_code (x))],
12839 stream);
f6b01912 12840 return;
12841
7d57ec45 12842 /* Cirrus registers can be accessed in a variety of ways:
12843 single floating point (f)
12844 double floating point (d)
12845 32bit integer (fx)
12846 64bit integer (dx). */
12847 case 'W': /* Cirrus register in F mode. */
12848 case 'X': /* Cirrus register in D mode. */
12849 case 'Y': /* Cirrus register in FX mode. */
12850 case 'Z': /* Cirrus register in DX mode. */
ed29c566 12851 gcc_assert (GET_CODE (x) == REG
12852 && REGNO_REG_CLASS (REGNO (x)) == CIRRUS_REGS);
7d57ec45 12853
12854 fprintf (stream, "mv%s%s",
12855 code == 'W' ? "f"
12856 : code == 'X' ? "d"
12857 : code == 'Y' ? "fx" : "dx", reg_names[REGNO (x)] + 2);
12858
12859 return;
12860
12861 /* Print cirrus register in the mode specified by the register's mode. */
12862 case 'V':
12863 {
12864 int mode = GET_MODE (x);
12865
12866 if (GET_CODE (x) != REG || REGNO_REG_CLASS (REGNO (x)) != CIRRUS_REGS)
47378eff 12867 {
12868 output_operand_lossage ("invalid operand for code '%c'", code);
12869 return;
12870 }
7d57ec45 12871
12872 fprintf (stream, "mv%s%s",
12873 mode == DFmode ? "d"
12874 : mode == SImode ? "fx"
12875 : mode == DImode ? "dx"
12876 : "f", reg_names[REGNO (x)] + 2);
12877
12878 return;
12879 }
12880
755eb2b4 12881 case 'U':
12882 if (GET_CODE (x) != REG
12883 || REGNO (x) < FIRST_IWMMXT_GR_REGNUM
12884 || REGNO (x) > LAST_IWMMXT_GR_REGNUM)
12885 /* Bad value for wCG register number. */
47378eff 12886 {
12887 output_operand_lossage ("invalid operand for code '%c'", code);
12888 return;
12889 }
12890
755eb2b4 12891 else
12892 fprintf (stream, "%d", REGNO (x) - FIRST_IWMMXT_GR_REGNUM);
12893 return;
12894
12895 /* Print an iWMMXt control register name. */
12896 case 'w':
12897 if (GET_CODE (x) != CONST_INT
12898 || INTVAL (x) < 0
12899 || INTVAL (x) >= 16)
12900 /* Bad value for wC register number. */
47378eff 12901 {
12902 output_operand_lossage ("invalid operand for code '%c'", code);
12903 return;
12904 }
12905
755eb2b4 12906 else
12907 {
12908 static const char * wc_reg_names [16] =
12909 {
12910 "wCID", "wCon", "wCSSF", "wCASF",
12911 "wC4", "wC5", "wC6", "wC7",
12912 "wCGR0", "wCGR1", "wCGR2", "wCGR3",
12913 "wC12", "wC13", "wC14", "wC15"
12914 };
9e7454d0 12915
755eb2b4 12916 fprintf (stream, wc_reg_names [INTVAL (x)]);
12917 }
12918 return;
12919
d98a3884 12920 /* Print a VFP/Neon double precision or quad precision register name. */
a2cd141b 12921 case 'P':
d98a3884 12922 case 'q':
a2cd141b 12923 {
12924 int mode = GET_MODE (x);
d98a3884 12925 int is_quad = (code == 'q');
12926 int regno;
a2cd141b 12927
d98a3884 12928 if (GET_MODE_SIZE (mode) != (is_quad ? 16 : 8))
47378eff 12929 {
12930 output_operand_lossage ("invalid operand for code '%c'", code);
12931 return;
12932 }
a2cd141b 12933
12934 if (GET_CODE (x) != REG
12935 || !IS_VFP_REGNUM (REGNO (x)))
47378eff 12936 {
12937 output_operand_lossage ("invalid operand for code '%c'", code);
12938 return;
12939 }
a2cd141b 12940
d98a3884 12941 regno = REGNO (x);
12942 if ((is_quad && !NEON_REGNO_OK_FOR_QUAD (regno))
12943 || (!is_quad && !VFP_REGNO_OK_FOR_DOUBLE (regno)))
47378eff 12944 {
12945 output_operand_lossage ("invalid operand for code '%c'", code);
12946 return;
12947 }
a2cd141b 12948
d98a3884 12949 fprintf (stream, "%c%d", is_quad ? 'q' : 'd',
12950 (regno - FIRST_VFP_REGNUM) >> (is_quad ? 2 : 1));
12951 }
12952 return;
12953
12954 /* These two codes print the low/high doubleword register of a Neon quad
12955 register, respectively. For pair-structure types, can also print
12956 low/high quadword registers. */
12957 case 'e':
12958 case 'f':
12959 {
12960 int mode = GET_MODE (x);
12961 int regno;
12962
12963 if ((GET_MODE_SIZE (mode) != 16
12964 && GET_MODE_SIZE (mode) != 32) || GET_CODE (x) != REG)
12965 {
12966 output_operand_lossage ("invalid operand for code '%c'", code);
12967 return;
12968 }
12969
12970 regno = REGNO (x);
12971 if (!NEON_REGNO_OK_FOR_QUAD (regno))
12972 {
12973 output_operand_lossage ("invalid operand for code '%c'", code);
12974 return;
12975 }
12976
12977 if (GET_MODE_SIZE (mode) == 16)
12978 fprintf (stream, "d%d", ((regno - FIRST_VFP_REGNUM) >> 1)
12979 + (code == 'f' ? 1 : 0));
12980 else
12981 fprintf (stream, "q%d", ((regno - FIRST_VFP_REGNUM) >> 2)
12982 + (code == 'f' ? 1 : 0));
a2cd141b 12983 }
12984 return;
12985
b5a0636d 12986 /* Print a VFPv3 floating-point constant, represented as an integer
12987 index. */
12988 case 'G':
12989 {
12990 int index = vfp3_const_double_index (x);
12991 gcc_assert (index != -1);
12992 fprintf (stream, "%d", index);
12993 }
12994 return;
12995
d98a3884 12996 /* Print bits representing opcode features for Neon.
12997
12998 Bit 0 is 1 for signed, 0 for unsigned. Floats count as signed
12999 and polynomials as unsigned.
13000
13001 Bit 1 is 1 for floats and polynomials, 0 for ordinary integers.
13002
13003 Bit 2 is 1 for rounding functions, 0 otherwise. */
13004
13005 /* Identify the type as 's', 'u', 'p' or 'f'. */
13006 case 'T':
13007 {
13008 HOST_WIDE_INT bits = INTVAL (x);
13009 fputc ("uspf"[bits & 3], stream);
13010 }
13011 return;
13012
13013 /* Likewise, but signed and unsigned integers are both 'i'. */
13014 case 'F':
13015 {
13016 HOST_WIDE_INT bits = INTVAL (x);
13017 fputc ("iipf"[bits & 3], stream);
13018 }
13019 return;
13020
13021 /* As for 'T', but emit 'u' instead of 'p'. */
13022 case 't':
13023 {
13024 HOST_WIDE_INT bits = INTVAL (x);
13025 fputc ("usuf"[bits & 3], stream);
13026 }
13027 return;
13028
13029 /* Bit 2: rounding (vs none). */
13030 case 'O':
13031 {
13032 HOST_WIDE_INT bits = INTVAL (x);
13033 fputs ((bits & 4) != 0 ? "r" : "", stream);
13034 }
13035 return;
13036
f6b01912 13037 default:
13038 if (x == 0)
47378eff 13039 {
13040 output_operand_lossage ("missing operand");
13041 return;
13042 }
f6b01912 13043
ed29c566 13044 switch (GET_CODE (x))
f6b01912 13045 {
ed29c566 13046 case REG:
13047 asm_fprintf (stream, "%r", REGNO (x));
13048 break;
13049
13050 case MEM:
f6b01912 13051 output_memory_reference_mode = GET_MODE (x);
13052 output_address (XEXP (x, 0));
ed29c566 13053 break;
13054
13055 case CONST_DOUBLE:
d98a3884 13056 if (TARGET_NEON)
13057 {
13058 char fpstr[20];
13059 real_to_decimal (fpstr, CONST_DOUBLE_REAL_VALUE (x),
13060 sizeof (fpstr), 0, 1);
13061 fprintf (stream, "#%s", fpstr);
13062 }
13063 else
13064 fprintf (stream, "#%s", fp_immediate_constant (x));
ed29c566 13065 break;
13066
13067 default:
13068 gcc_assert (GET_CODE (x) != NEG);
f6b01912 13069 fputc ('#', stream);
13070 output_addr_const (stream, x);
ed29c566 13071 break;
f6b01912 13072 }
13073 }
13074}
8cd42699 13075\f
58356836 13076#ifndef AOF_ASSEMBLER
13077/* Target hook for assembling integer objects. The ARM version needs to
13078 handle word-sized values specially. */
58356836 13079static bool
ebd88a36 13080arm_assemble_integer (rtx x, unsigned int size, int aligned_p)
58356836 13081{
d98a3884 13082 enum machine_mode mode;
13083
58356836 13084 if (size == UNITS_PER_WORD && aligned_p)
13085 {
13086 fputs ("\t.word\t", asm_out_file);
13087 output_addr_const (asm_out_file, x);
13088
13089 /* Mark symbols as position independent. We only do this in the
674a8f0b 13090 .text segment, not in the .data segment. */
58356836 13091 if (NEED_GOT_RELOC && flag_pic && making_const_table &&
13092 (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF))
13093 {
bac7fc85 13094 /* See legitimize_pic_address for an explanation of the
13095 TARGET_VXWORKS_RTP check. */
13096 if (TARGET_VXWORKS_RTP
13097 || (GET_CODE (x) == SYMBOL_REF && !SYMBOL_REF_LOCAL_P (x)))
58356836 13098 fputs ("(GOT)", asm_out_file);
bac7fc85 13099 else
13100 fputs ("(GOTOFF)", asm_out_file);
58356836 13101 }
13102 fputc ('\n', asm_out_file);
13103 return true;
13104 }
a12be13c 13105
d98a3884 13106 mode = GET_MODE (x);
13107
13108 if (arm_vector_mode_supported_p (mode))
755eb2b4 13109 {
13110 int i, units;
d98a3884 13111 unsigned int invmask = 0, parts_per_word;
755eb2b4 13112
ed29c566 13113 gcc_assert (GET_CODE (x) == CONST_VECTOR);
755eb2b4 13114
13115 units = CONST_VECTOR_NUNITS (x);
d98a3884 13116 size = GET_MODE_SIZE (GET_MODE_INNER (mode));
755eb2b4 13117
d98a3884 13118 /* For big-endian Neon vectors, we must permute the vector to the form
13119 which, when loaded by a VLDR or VLDM instruction, will give a vector
13120 with the elements in the right order. */
13121 if (TARGET_NEON && WORDS_BIG_ENDIAN)
13122 {
13123 parts_per_word = UNITS_PER_WORD / size;
13124 /* FIXME: This might be wrong for 64-bit vector elements, but we don't
13125 support those anywhere yet. */
13126 invmask = (parts_per_word == 0) ? 0 : (1 << (parts_per_word - 1)) - 1;
13127 }
755eb2b4 13128
d98a3884 13129 if (GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
13130 for (i = 0; i < units; i++)
13131 {
13132 rtx elt = CONST_VECTOR_ELT (x, i ^ invmask);
13133 assemble_integer
13134 (elt, size, i == 0 ? BIGGEST_ALIGNMENT : size * BITS_PER_UNIT, 1);
13135 }
13136 else
13137 for (i = 0; i < units; i++)
13138 {
13139 rtx elt = CONST_VECTOR_ELT (x, i);
13140 REAL_VALUE_TYPE rval;
755eb2b4 13141
d98a3884 13142 REAL_VALUE_FROM_CONST_DOUBLE (rval, elt);
13143
13144 assemble_real
13145 (rval, GET_MODE_INNER (mode),
13146 i == 0 ? BIGGEST_ALIGNMENT : size * BITS_PER_UNIT);
13147 }
755eb2b4 13148
13149 return true;
13150 }
13151
58356836 13152 return default_assemble_integer (x, size, aligned_p);
13153}
d24bc145 13154
d24bc145 13155static void
a457f9f8 13156arm_elf_asm_cdtor (rtx symbol, int priority, bool is_ctor)
d24bc145 13157{
df816ae6 13158 section *s;
13159
d24bc145 13160 if (!TARGET_AAPCS_BASED)
13161 {
a457f9f8 13162 (is_ctor ?
13163 default_named_section_asm_out_constructor
13164 : default_named_section_asm_out_destructor) (symbol, priority);
d24bc145 13165 return;
13166 }
13167
13168 /* Put these in the .init_array section, using a special relocation. */
df816ae6 13169 if (priority != DEFAULT_INIT_PRIORITY)
13170 {
13171 char buf[18];
a457f9f8 13172 sprintf (buf, "%s.%.5u",
13173 is_ctor ? ".init_array" : ".fini_array",
13174 priority);
df816ae6 13175 s = get_section (buf, SECTION_WRITE, NULL_TREE);
13176 }
a457f9f8 13177 else if (is_ctor)
df816ae6 13178 s = ctors_section;
a457f9f8 13179 else
13180 s = dtors_section;
df816ae6 13181
13182 switch_to_section (s);
d24bc145 13183 assemble_align (POINTER_SIZE);
13184 fputs ("\t.word\t", asm_out_file);
13185 output_addr_const (asm_out_file, symbol);
13186 fputs ("(target1)\n", asm_out_file);
13187}
a457f9f8 13188
13189/* Add a function to the list of static constructors. */
13190
13191static void
13192arm_elf_asm_constructor (rtx symbol, int priority)
13193{
13194 arm_elf_asm_cdtor (symbol, priority, /*is_ctor=*/true);
13195}
13196
13197/* Add a function to the list of static destructors. */
13198
13199static void
13200arm_elf_asm_destructor (rtx symbol, int priority)
13201{
13202 arm_elf_asm_cdtor (symbol, priority, /*is_ctor=*/false);
13203}
58356836 13204#endif
13205\f
8cd42699 13206/* A finite state machine takes care of noticing whether or not instructions
13207 can be conditionally executed, and thus decrease execution time and code
13208 size by deleting branch instructions. The fsm is controlled by
13209 final_prescan_insn, and controls the actions of ASM_OUTPUT_OPCODE. */
13210
13211/* The state of the fsm controlling condition codes are:
13212 0: normal, do nothing special
13213 1: make ASM_OUTPUT_OPCODE not output this instruction
13214 2: make ASM_OUTPUT_OPCODE not output this instruction
13215 3: make instructions conditional
13216 4: make instructions conditional
13217
13218 State transitions (state->state by whom under condition):
13219 0 -> 1 final_prescan_insn if the `target' is a label
13220 0 -> 2 final_prescan_insn if the `target' is an unconditional branch
13221 1 -> 3 ASM_OUTPUT_OPCODE after not having output the conditional branch
13222 2 -> 4 ASM_OUTPUT_OPCODE after not having output the conditional branch
805e22b2 13223 3 -> 0 (*targetm.asm_out.internal_label) if the `target' label is reached
8cd42699 13224 (the target label has CODE_LABEL_NUMBER equal to arm_target_label).
13225 4 -> 0 final_prescan_insn if the `target' unconditional branch is reached
13226 (the target insn is arm_target_insn).
13227
9c08d1fa 13228 If the jump clobbers the conditions then we use states 2 and 4.
13229
13230 A similar thing can be done with conditional return insns.
13231
8cd42699 13232 XXX In case the `target' is an unconditional branch, this conditionalising
13233 of the instructions always reduces code size, but not always execution
13234 time. But then, I want to reduce the code size to somewhere near what
13235 /bin/cc produces. */
13236
25f905c2 13237/* In addition to this, state is maintained for Thumb-2 COND_EXEC
13238 instructions. When a COND_EXEC instruction is seen the subsequent
13239 instructions are scanned so that multiple conditional instructions can be
13240 combined into a single IT block. arm_condexec_count and arm_condexec_mask
13241 specify the length and true/false mask for the IT block. These will be
13242 decremented/zeroed by arm_asm_output_opcode as the insns are output. */
13243
8cd42699 13244/* Returns the index of the ARM condition code string in
13245 `arm_condition_codes'. COMPARISON should be an rtx like
13246 `(eq (...) (...))'. */
1275b964 13247static enum arm_cond_code
ebd88a36 13248get_arm_condition_code (rtx comparison)
8cd42699 13249{
ac577012 13250 enum machine_mode mode = GET_MODE (XEXP (comparison, 0));
a12be13c 13251 int code;
13252 enum rtx_code comp_code = GET_CODE (comparison);
ac577012 13253
13254 if (GET_MODE_CLASS (mode) != MODE_CC)
1275b964 13255 mode = SELECT_CC_MODE (comp_code, XEXP (comparison, 0),
ac577012 13256 XEXP (comparison, 1));
13257
13258 switch (mode)
8cd42699 13259 {
1275b964 13260 case CC_DNEmode: code = ARM_NE; goto dominance;
13261 case CC_DEQmode: code = ARM_EQ; goto dominance;
13262 case CC_DGEmode: code = ARM_GE; goto dominance;
13263 case CC_DGTmode: code = ARM_GT; goto dominance;
13264 case CC_DLEmode: code = ARM_LE; goto dominance;
13265 case CC_DLTmode: code = ARM_LT; goto dominance;
13266 case CC_DGEUmode: code = ARM_CS; goto dominance;
13267 case CC_DGTUmode: code = ARM_HI; goto dominance;
13268 case CC_DLEUmode: code = ARM_LS; goto dominance;
13269 case CC_DLTUmode: code = ARM_CC;
13270
13271 dominance:
ed29c566 13272 gcc_assert (comp_code == EQ || comp_code == NE);
1275b964 13273
13274 if (comp_code == EQ)
13275 return ARM_INVERSE_CONDITION_CODE (code);
13276 return code;
13277
ac577012 13278 case CC_NOOVmode:
1275b964 13279 switch (comp_code)
ac577012 13280 {
1275b964 13281 case NE: return ARM_NE;
13282 case EQ: return ARM_EQ;
13283 case GE: return ARM_PL;
13284 case LT: return ARM_MI;
ed29c566 13285 default: gcc_unreachable ();
ac577012 13286 }
13287
13288 case CC_Zmode:
1275b964 13289 switch (comp_code)
ac577012 13290 {
1275b964 13291 case NE: return ARM_NE;
13292 case EQ: return ARM_EQ;
ed29c566 13293 default: gcc_unreachable ();
ac577012 13294 }
13295
58d6528b 13296 case CC_Nmode:
13297 switch (comp_code)
13298 {
13299 case NE: return ARM_MI;
13300 case EQ: return ARM_PL;
ed29c566 13301 default: gcc_unreachable ();
58d6528b 13302 }
13303
ac577012 13304 case CCFPEmode:
f3d87a93 13305 case CCFPmode:
13306 /* These encodings assume that AC=1 in the FPA system control
13307 byte. This allows us to handle all cases except UNEQ and
13308 LTGT. */
1275b964 13309 switch (comp_code)
13310 {
13311 case GE: return ARM_GE;
13312 case GT: return ARM_GT;
13313 case LE: return ARM_LS;
13314 case LT: return ARM_MI;
f3d87a93 13315 case NE: return ARM_NE;
13316 case EQ: return ARM_EQ;
13317 case ORDERED: return ARM_VC;
13318 case UNORDERED: return ARM_VS;
13319 case UNLT: return ARM_LT;
13320 case UNLE: return ARM_LE;
13321 case UNGT: return ARM_HI;
13322 case UNGE: return ARM_PL;
13323 /* UNEQ and LTGT do not have a representation. */
13324 case UNEQ: /* Fall through. */
13325 case LTGT: /* Fall through. */
ed29c566 13326 default: gcc_unreachable ();
1275b964 13327 }
13328
13329 case CC_SWPmode:
13330 switch (comp_code)
13331 {
13332 case NE: return ARM_NE;
13333 case EQ: return ARM_EQ;
13334 case GE: return ARM_LE;
13335 case GT: return ARM_LT;
13336 case LE: return ARM_GE;
13337 case LT: return ARM_GT;
13338 case GEU: return ARM_LS;
13339 case GTU: return ARM_CC;
13340 case LEU: return ARM_CS;
13341 case LTU: return ARM_HI;
ed29c566 13342 default: gcc_unreachable ();
1275b964 13343 }
13344
9480e6c7 13345 case CC_Cmode:
13346 switch (comp_code)
13347 {
13348 case LTU: return ARM_CS;
13349 case GEU: return ARM_CC;
ed29c566 13350 default: gcc_unreachable ();
9480e6c7 13351 }
9e7454d0 13352
ac577012 13353 case CCmode:
1275b964 13354 switch (comp_code)
ac577012 13355 {
1275b964 13356 case NE: return ARM_NE;
13357 case EQ: return ARM_EQ;
13358 case GE: return ARM_GE;
13359 case GT: return ARM_GT;
13360 case LE: return ARM_LE;
13361 case LT: return ARM_LT;
13362 case GEU: return ARM_CS;
13363 case GTU: return ARM_HI;
13364 case LEU: return ARM_LS;
13365 case LTU: return ARM_CC;
ed29c566 13366 default: gcc_unreachable ();
ac577012 13367 }
13368
ed29c566 13369 default: gcc_unreachable ();
8cd42699 13370 }
a690ede2 13371}
8cd42699 13372
f6a0d06f 13373/* Tell arm_asm_output_opcode to output IT blocks for conditionally executed
25f905c2 13374 instructions. */
13375void
13376thumb2_final_prescan_insn (rtx insn)
13377{
13378 rtx first_insn = insn;
13379 rtx body = PATTERN (insn);
13380 rtx predicate;
13381 enum arm_cond_code code;
13382 int n;
13383 int mask;
13384
13385 /* Remove the previous insn from the count of insns to be output. */
13386 if (arm_condexec_count)
13387 arm_condexec_count--;
13388
13389 /* Nothing to do if we are already inside a conditional block. */
13390 if (arm_condexec_count)
13391 return;
13392
13393 if (GET_CODE (body) != COND_EXEC)
13394 return;
13395
13396 /* Conditional jumps are implemented directly. */
13397 if (GET_CODE (insn) == JUMP_INSN)
13398 return;
13399
13400 predicate = COND_EXEC_TEST (body);
13401 arm_current_cc = get_arm_condition_code (predicate);
13402
13403 n = get_attr_ce_count (insn);
13404 arm_condexec_count = 1;
13405 arm_condexec_mask = (1 << n) - 1;
13406 arm_condexec_masklen = n;
13407 /* See if subsequent instructions can be combined into the same block. */
13408 for (;;)
13409 {
13410 insn = next_nonnote_insn (insn);
13411
13412 /* Jumping into the middle of an IT block is illegal, so a label or
13413 barrier terminates the block. */
13414 if (GET_CODE (insn) != INSN && GET_CODE(insn) != JUMP_INSN)
13415 break;
13416
13417 body = PATTERN (insn);
13418 /* USE and CLOBBER aren't really insns, so just skip them. */
13419 if (GET_CODE (body) == USE
13420 || GET_CODE (body) == CLOBBER)
7dd28afd 13421 continue;
25f905c2 13422
542d5028 13423 /* ??? Recognize conditional jumps, and combine them with IT blocks. */
25f905c2 13424 if (GET_CODE (body) != COND_EXEC)
13425 break;
13426 /* Allow up to 4 conditionally executed instructions in a block. */
13427 n = get_attr_ce_count (insn);
13428 if (arm_condexec_masklen + n > 4)
13429 break;
13430
13431 predicate = COND_EXEC_TEST (body);
13432 code = get_arm_condition_code (predicate);
13433 mask = (1 << n) - 1;
13434 if (arm_current_cc == code)
13435 arm_condexec_mask |= (mask << arm_condexec_masklen);
13436 else if (arm_current_cc != ARM_INVERSE_CONDITION_CODE(code))
13437 break;
13438
13439 arm_condexec_count++;
13440 arm_condexec_masklen += n;
13441
13442 /* A jump must be the last instruction in a conditional block. */
13443 if (GET_CODE(insn) == JUMP_INSN)
13444 break;
13445 }
13446 /* Restore recog_data (getting the attributes of other insns can
13447 destroy this array, but final.c assumes that it remains intact
13448 across this call). */
13449 extract_constrain_insn_cached (first_insn);
13450}
13451
8cd42699 13452void
ebd88a36 13453arm_final_prescan_insn (rtx insn)
8cd42699 13454{
13455 /* BODY will hold the body of INSN. */
a12be13c 13456 rtx body = PATTERN (insn);
8cd42699 13457
13458 /* This will be 1 if trying to repeat the trick, and things need to be
13459 reversed if it appears to fail. */
13460 int reverse = 0;
13461
9c08d1fa 13462 /* JUMP_CLOBBERS will be one implies that the conditions if a branch is
13463 taken are clobbered, even if the rtl suggests otherwise. It also
13464 means that we have to grub around within the jump expression to find
13465 out what the conditions are when the jump isn't taken. */
13466 int jump_clobbers = 0;
9e7454d0 13467
66aacf41 13468 /* If we start with a return insn, we only succeed if we find another one. */
9c08d1fa 13469 int seeking_return = 0;
9e7454d0 13470
8cd42699 13471 /* START_INSN will hold the insn from where we start looking. This is the
13472 first insn after the following code_label if REVERSE is true. */
13473 rtx start_insn = insn;
13474
13475 /* If in state 4, check if the target branch is reached, in order to
13476 change back to state 0. */
13477 if (arm_ccfsm_state == 4)
13478 {
13479 if (insn == arm_target_insn)
9888ad6d 13480 {
13481 arm_target_insn = NULL;
13482 arm_ccfsm_state = 0;
13483 }
8cd42699 13484 return;
13485 }
13486
13487 /* If in state 3, it is possible to repeat the trick, if this insn is an
13488 unconditional branch to a label, and immediately following this branch
13489 is the previous target label which is only used once, and the label this
13490 branch jumps to is not too far off. */
13491 if (arm_ccfsm_state == 3)
13492 {
13493 if (simplejump_p (insn))
13494 {
13495 start_insn = next_nonnote_insn (start_insn);
13496 if (GET_CODE (start_insn) == BARRIER)
13497 {
13498 /* XXX Isn't this always a barrier? */
13499 start_insn = next_nonnote_insn (start_insn);
13500 }
13501 if (GET_CODE (start_insn) == CODE_LABEL
13502 && CODE_LABEL_NUMBER (start_insn) == arm_target_label
13503 && LABEL_NUSES (start_insn) == 1)
13504 reverse = TRUE;
13505 else
13506 return;
13507 }
9c08d1fa 13508 else if (GET_CODE (body) == RETURN)
13509 {
13510 start_insn = next_nonnote_insn (start_insn);
13511 if (GET_CODE (start_insn) == BARRIER)
13512 start_insn = next_nonnote_insn (start_insn);
13513 if (GET_CODE (start_insn) == CODE_LABEL
13514 && CODE_LABEL_NUMBER (start_insn) == arm_target_label
13515 && LABEL_NUSES (start_insn) == 1)
13516 {
13517 reverse = TRUE;
13518 seeking_return = 1;
13519 }
13520 else
13521 return;
13522 }
8cd42699 13523 else
13524 return;
13525 }
13526
ed29c566 13527 gcc_assert (!arm_ccfsm_state || reverse);
8cd42699 13528 if (GET_CODE (insn) != JUMP_INSN)
13529 return;
13530
9e7454d0 13531 /* This jump might be paralleled with a clobber of the condition codes
9c08d1fa 13532 the jump should always come first */
13533 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0)
13534 body = XVECEXP (body, 0, 0);
13535
8cd42699 13536 if (reverse
13537 || (GET_CODE (body) == SET && GET_CODE (SET_DEST (body)) == PC
13538 && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE))
13539 {
9480e6c7 13540 int insns_skipped;
13541 int fail = FALSE, succeed = FALSE;
8cd42699 13542 /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */
13543 int then_not_else = TRUE;
9c08d1fa 13544 rtx this_insn = start_insn, label = 0;
8cd42699 13545
9e7454d0 13546 /* If the jump cannot be done with one instruction, we cannot
f3d87a93 13547 conditionally execute the instruction in the inverse case. */
9c08d1fa 13548 if (get_attr_conds (insn) == CONDS_JUMP_CLOB)
81380c80 13549 {
81380c80 13550 jump_clobbers = 1;
13551 return;
13552 }
9e7454d0 13553
8cd42699 13554 /* Register the insn jumped to. */
13555 if (reverse)
9c08d1fa 13556 {
13557 if (!seeking_return)
13558 label = XEXP (SET_SRC (body), 0);
13559 }
8cd42699 13560 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == LABEL_REF)
13561 label = XEXP (XEXP (SET_SRC (body), 1), 0);
13562 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == LABEL_REF)
13563 {
13564 label = XEXP (XEXP (SET_SRC (body), 2), 0);
13565 then_not_else = FALSE;
13566 }
9c08d1fa 13567 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == RETURN)
13568 seeking_return = 1;
13569 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == RETURN)
13570 {
13571 seeking_return = 1;
13572 then_not_else = FALSE;
13573 }
8cd42699 13574 else
ed29c566 13575 gcc_unreachable ();
8cd42699 13576
13577 /* See how many insns this branch skips, and what kind of insns. If all
13578 insns are okay, and the label or unconditional branch to the same
13579 label is not too far away, succeed. */
13580 for (insns_skipped = 0;
129a2fe4 13581 !fail && !succeed && insns_skipped++ < max_insns_skipped;)
8cd42699 13582 {
13583 rtx scanbody;
13584
13585 this_insn = next_nonnote_insn (this_insn);
13586 if (!this_insn)
13587 break;
13588
8cd42699 13589 switch (GET_CODE (this_insn))
13590 {
13591 case CODE_LABEL:
13592 /* Succeed if it is the target label, otherwise fail since
13593 control falls in from somewhere else. */
13594 if (this_insn == label)
13595 {
9c08d1fa 13596 if (jump_clobbers)
13597 {
13598 arm_ccfsm_state = 2;
13599 this_insn = next_nonnote_insn (this_insn);
13600 }
13601 else
13602 arm_ccfsm_state = 1;
8cd42699 13603 succeed = TRUE;
13604 }
13605 else
13606 fail = TRUE;
13607 break;
13608
9c08d1fa 13609 case BARRIER:
8cd42699 13610 /* Succeed if the following insn is the target label.
9e7454d0 13611 Otherwise fail.
13612 If return insns are used then the last insn in a function
66aacf41 13613 will be a barrier. */
8cd42699 13614 this_insn = next_nonnote_insn (this_insn);
9c08d1fa 13615 if (this_insn && this_insn == label)
8cd42699 13616 {
9c08d1fa 13617 if (jump_clobbers)
13618 {
13619 arm_ccfsm_state = 2;
13620 this_insn = next_nonnote_insn (this_insn);
13621 }
13622 else
13623 arm_ccfsm_state = 1;
8cd42699 13624 succeed = TRUE;
13625 }
13626 else
13627 fail = TRUE;
13628 break;
13629
9c08d1fa 13630 case CALL_INSN:
f1039640 13631 /* The AAPCS says that conditional calls should not be
13632 used since they make interworking inefficient (the
13633 linker can't transform BL<cond> into BLX). That's
13634 only a problem if the machine has BLX. */
13635 if (arm_arch5)
13636 {
13637 fail = TRUE;
13638 break;
13639 }
13640
c1a66faf 13641 /* Succeed if the following insn is the target label, or
13642 if the following two insns are a barrier and the
13643 target label. */
13644 this_insn = next_nonnote_insn (this_insn);
13645 if (this_insn && GET_CODE (this_insn) == BARRIER)
13646 this_insn = next_nonnote_insn (this_insn);
9480e6c7 13647
c1a66faf 13648 if (this_insn && this_insn == label
13649 && insns_skipped < max_insns_skipped)
13650 {
13651 if (jump_clobbers)
9480e6c7 13652 {
c1a66faf 13653 arm_ccfsm_state = 2;
13654 this_insn = next_nonnote_insn (this_insn);
9480e6c7 13655 }
13656 else
c1a66faf 13657 arm_ccfsm_state = 1;
13658 succeed = TRUE;
9480e6c7 13659 }
c1a66faf 13660 else
13661 fail = TRUE;
9c08d1fa 13662 break;
64266206 13663
8cd42699 13664 case JUMP_INSN:
13665 /* If this is an unconditional branch to the same label, succeed.
13666 If it is to another label, do nothing. If it is conditional,
13667 fail. */
ebd88a36 13668 /* XXX Probably, the tests for SET and the PC are
13669 unnecessary. */
8cd42699 13670
ae175e8f 13671 scanbody = PATTERN (this_insn);
9c08d1fa 13672 if (GET_CODE (scanbody) == SET
13673 && GET_CODE (SET_DEST (scanbody)) == PC)
8cd42699 13674 {
13675 if (GET_CODE (SET_SRC (scanbody)) == LABEL_REF
13676 && XEXP (SET_SRC (scanbody), 0) == label && !reverse)
13677 {
13678 arm_ccfsm_state = 2;
13679 succeed = TRUE;
13680 }
13681 else if (GET_CODE (SET_SRC (scanbody)) == IF_THEN_ELSE)
13682 fail = TRUE;
13683 }
a361b456 13684 /* Fail if a conditional return is undesirable (e.g. on a
129a2fe4 13685 StrongARM), but still allow this if optimizing for size. */
13686 else if (GET_CODE (scanbody) == RETURN
ffc9d00c 13687 && !use_return_insn (TRUE, NULL)
215b30b3 13688 && !optimize_size)
129a2fe4 13689 fail = TRUE;
9c08d1fa 13690 else if (GET_CODE (scanbody) == RETURN
13691 && seeking_return)
13692 {
13693 arm_ccfsm_state = 2;
13694 succeed = TRUE;
13695 }
13696 else if (GET_CODE (scanbody) == PARALLEL)
13697 {
13698 switch (get_attr_conds (this_insn))
13699 {
13700 case CONDS_NOCOND:
13701 break;
13702 default:
13703 fail = TRUE;
13704 break;
13705 }
13706 }
5e3840e1 13707 else
a361b456 13708 fail = TRUE; /* Unrecognized jump (e.g. epilogue). */
5e3840e1 13709
8cd42699 13710 break;
13711
13712 case INSN:
9c08d1fa 13713 /* Instructions using or affecting the condition codes make it
13714 fail. */
ae175e8f 13715 scanbody = PATTERN (this_insn);
215b30b3 13716 if (!(GET_CODE (scanbody) == SET
13717 || GET_CODE (scanbody) == PARALLEL)
3acc3606 13718 || get_attr_conds (this_insn) != CONDS_NOCOND)
8cd42699 13719 fail = TRUE;
7d57ec45 13720
13721 /* A conditional cirrus instruction must be followed by
13722 a non Cirrus instruction. However, since we
13723 conditionalize instructions in this function and by
13724 the time we get here we can't add instructions
13725 (nops), because shorten_branches() has already been
13726 called, we will disable conditionalizing Cirrus
13727 instructions to be safe. */
13728 if (GET_CODE (scanbody) != USE
13729 && GET_CODE (scanbody) != CLOBBER
2c6c7d8b 13730 && get_attr_cirrus (this_insn) != CIRRUS_NOT)
7d57ec45 13731 fail = TRUE;
8cd42699 13732 break;
13733
13734 default:
13735 break;
13736 }
13737 }
13738 if (succeed)
13739 {
9c08d1fa 13740 if ((!seeking_return) && (arm_ccfsm_state == 1 || reverse))
8cd42699 13741 arm_target_label = CODE_LABEL_NUMBER (label);
ed29c566 13742 else
9c08d1fa 13743 {
ed29c566 13744 gcc_assert (seeking_return || arm_ccfsm_state == 2);
a60f1840 13745
9c08d1fa 13746 while (this_insn && GET_CODE (PATTERN (this_insn)) == USE)
13747 {
13748 this_insn = next_nonnote_insn (this_insn);
ed29c566 13749 gcc_assert (!this_insn
13750 || (GET_CODE (this_insn) != BARRIER
13751 && GET_CODE (this_insn) != CODE_LABEL));
9c08d1fa 13752 }
13753 if (!this_insn)
13754 {
674a8f0b 13755 /* Oh, dear! we ran off the end.. give up. */
25f905c2 13756 extract_constrain_insn_cached (insn);
9c08d1fa 13757 arm_ccfsm_state = 0;
48af475c 13758 arm_target_insn = NULL;
9c08d1fa 13759 return;
13760 }
13761 arm_target_insn = this_insn;
13762 }
9c08d1fa 13763 if (jump_clobbers)
13764 {
ed29c566 13765 gcc_assert (!reverse);
9e7454d0 13766 arm_current_cc =
9c08d1fa 13767 get_arm_condition_code (XEXP (XEXP (XEXP (SET_SRC (body),
13768 0), 0), 1));
13769 if (GET_CODE (XEXP (XEXP (SET_SRC (body), 0), 0)) == AND)
13770 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
13771 if (GET_CODE (XEXP (SET_SRC (body), 0)) == NE)
13772 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
13773 }
13774 else
13775 {
13776 /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from
13777 what it was. */
13778 if (!reverse)
13779 arm_current_cc = get_arm_condition_code (XEXP (SET_SRC (body),
13780 0));
13781 }
8cd42699 13782
8cd42699 13783 if (reverse || then_not_else)
13784 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
13785 }
9e7454d0 13786
ed420a25 13787 /* Restore recog_data (getting the attributes of other insns can
9c08d1fa 13788 destroy this array, but final.c assumes that it remains intact
25f905c2 13789 across this call. */
13790 extract_constrain_insn_cached (insn);
13791 }
13792}
13793
13794/* Output IT instructions. */
13795void
13796thumb2_asm_output_opcode (FILE * stream)
13797{
13798 char buff[5];
13799 int n;
13800
13801 if (arm_condexec_mask)
13802 {
13803 for (n = 0; n < arm_condexec_masklen; n++)
13804 buff[n] = (arm_condexec_mask & (1 << n)) ? 't' : 'e';
13805 buff[n] = 0;
13806 asm_fprintf(stream, "i%s\t%s\n\t", buff,
13807 arm_condition_codes[arm_current_cc]);
13808 arm_condexec_mask = 0;
8cd42699 13809 }
a690ede2 13810}
8cd42699 13811
d19ef66f 13812/* Returns true if REGNO is a valid register
c1877da8 13813 for holding a quantity of type MODE. */
d19ef66f 13814int
ebd88a36 13815arm_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode)
d19ef66f 13816{
13817 if (GET_MODE_CLASS (mode) == MODE_CC)
8901ae22 13818 return (regno == CC_REGNUM
13819 || (TARGET_HARD_FLOAT && TARGET_VFP
13820 && regno == VFPCC_REGNUM));
9e7454d0 13821
25f905c2 13822 if (TARGET_THUMB1)
d19ef66f 13823 /* For the Thumb we only allow values bigger than SImode in
13824 registers 0 - 6, so that there is always a second low
13825 register available to hold the upper part of the value.
13826 We probably we ought to ensure that the register is the
13827 start of an even numbered register pair. */
36837fde 13828 return (ARM_NUM_REGS (mode) < 2) || (regno < LAST_LO_REGNUM);
d19ef66f 13829
8901ae22 13830 if (TARGET_HARD_FLOAT && TARGET_MAVERICK
13831 && IS_CIRRUS_REGNUM (regno))
7d57ec45 13832 /* We have outlawed SI values in Cirrus registers because they
13833 reside in the lower 32 bits, but SF values reside in the
13834 upper 32 bits. This causes gcc all sorts of grief. We can't
13835 even split the registers into pairs because Cirrus SI values
13836 get sign extended to 64bits-- aldyh. */
13837 return (GET_MODE_CLASS (mode) == MODE_FLOAT) || (mode == DImode);
13838
8901ae22 13839 if (TARGET_HARD_FLOAT && TARGET_VFP
13840 && IS_VFP_REGNUM (regno))
a2cd141b 13841 {
13842 if (mode == SFmode || mode == SImode)
b5a0636d 13843 return VFP_REGNO_OK_FOR_SINGLE (regno);
a2cd141b 13844
a2cd141b 13845 if (mode == DFmode)
b5a0636d 13846 return VFP_REGNO_OK_FOR_DOUBLE (regno);
d98a3884 13847
13848 if (TARGET_NEON)
13849 return (VALID_NEON_DREG_MODE (mode) && VFP_REGNO_OK_FOR_DOUBLE (regno))
13850 || (VALID_NEON_QREG_MODE (mode)
13851 && NEON_REGNO_OK_FOR_QUAD (regno))
13852 || (mode == TImode && NEON_REGNO_OK_FOR_NREGS (regno, 2))
13853 || (mode == EImode && NEON_REGNO_OK_FOR_NREGS (regno, 3))
13854 || (mode == OImode && NEON_REGNO_OK_FOR_NREGS (regno, 4))
13855 || (mode == CImode && NEON_REGNO_OK_FOR_NREGS (regno, 6))
13856 || (mode == XImode && NEON_REGNO_OK_FOR_NREGS (regno, 8));
13857
a2cd141b 13858 return FALSE;
13859 }
13860
8901ae22 13861 if (TARGET_REALLY_IWMMXT)
13862 {
13863 if (IS_IWMMXT_GR_REGNUM (regno))
13864 return mode == SImode;
755eb2b4 13865
8901ae22 13866 if (IS_IWMMXT_REGNUM (regno))
13867 return VALID_IWMMXT_REG_MODE (mode);
13868 }
13869
a8a3b539 13870 /* We allow any value to be stored in the general registers.
13871 Restrict doubleword quantities to even register pairs so that we can
d98a3884 13872 use ldrd. Do not allow Neon structure opaque modes in general registers;
13873 they would use too many. */
d19ef66f 13874 if (regno <= LAST_ARM_REGNUM)
d98a3884 13875 return !(TARGET_LDRD && GET_MODE_SIZE (mode) > 4 && (regno & 1) != 0)
13876 && !VALID_NEON_STRUCT_MODE (mode);
d19ef66f 13877
8901ae22 13878 if (regno == FRAME_POINTER_REGNUM
d19ef66f 13879 || regno == ARG_POINTER_REGNUM)
13880 /* We only allow integers in the fake hard registers. */
13881 return GET_MODE_CLASS (mode) == MODE_INT;
13882
e8ff69a4 13883 /* The only registers left are the FPA registers
d19ef66f 13884 which we only allow to hold FP values. */
8901ae22 13885 return (TARGET_HARD_FLOAT && TARGET_FPA
13886 && GET_MODE_CLASS (mode) == MODE_FLOAT
13887 && regno >= FIRST_FPA_REGNUM
13888 && regno <= LAST_FPA_REGNUM);
d19ef66f 13889}
13890
25f905c2 13891/* For efficiency and historical reasons LO_REGS, HI_REGS and CC_REGS are
13892 not used in arm mode. */
cffb2a26 13893int
ebd88a36 13894arm_regno_class (int regno)
cffb2a26 13895{
25f905c2 13896 if (TARGET_THUMB1)
cffb2a26 13897 {
13898 if (regno == STACK_POINTER_REGNUM)
13899 return STACK_REG;
13900 if (regno == CC_REGNUM)
13901 return CC_REG;
13902 if (regno < 8)
13903 return LO_REGS;
13904 return HI_REGS;
13905 }
13906
25f905c2 13907 if (TARGET_THUMB2 && regno < 8)
13908 return LO_REGS;
13909
cffb2a26 13910 if ( regno <= LAST_ARM_REGNUM
13911 || regno == FRAME_POINTER_REGNUM
13912 || regno == ARG_POINTER_REGNUM)
25f905c2 13913 return TARGET_THUMB2 ? HI_REGS : GENERAL_REGS;
9e7454d0 13914
a2cd141b 13915 if (regno == CC_REGNUM || regno == VFPCC_REGNUM)
25f905c2 13916 return TARGET_THUMB2 ? CC_REG : NO_REGS;
cffb2a26 13917
7d57ec45 13918 if (IS_CIRRUS_REGNUM (regno))
13919 return CIRRUS_REGS;
13920
a2cd141b 13921 if (IS_VFP_REGNUM (regno))
b5a0636d 13922 {
13923 if (regno <= D7_VFP_REGNUM)
13924 return VFP_D0_D7_REGS;
13925 else if (regno <= LAST_LO_VFP_REGNUM)
13926 return VFP_LO_REGS;
13927 else
13928 return VFP_HI_REGS;
13929 }
a2cd141b 13930
755eb2b4 13931 if (IS_IWMMXT_REGNUM (regno))
13932 return IWMMXT_REGS;
13933
6ee861f1 13934 if (IS_IWMMXT_GR_REGNUM (regno))
13935 return IWMMXT_GR_REGS;
13936
e8ff69a4 13937 return FPA_REGS;
cffb2a26 13938}
13939
13940/* Handle a special case when computing the offset
13941 of an argument from the frame pointer. */
13942int
ebd88a36 13943arm_debugger_arg_offset (int value, rtx addr)
cffb2a26 13944{
13945 rtx insn;
13946
13947 /* We are only interested if dbxout_parms() failed to compute the offset. */
13948 if (value != 0)
13949 return 0;
13950
13951 /* We can only cope with the case where the address is held in a register. */
13952 if (GET_CODE (addr) != REG)
13953 return 0;
13954
13955 /* If we are using the frame pointer to point at the argument, then
13956 an offset of 0 is correct. */
0bd59681 13957 if (REGNO (addr) == (unsigned) HARD_FRAME_POINTER_REGNUM)
cffb2a26 13958 return 0;
9e7454d0 13959
cffb2a26 13960 /* If we are using the stack pointer to point at the
13961 argument, then an offset of 0 is correct. */
25f905c2 13962 /* ??? Check this is consistent with thumb2 frame layout. */
215b30b3 13963 if ((TARGET_THUMB || !frame_pointer_needed)
cffb2a26 13964 && REGNO (addr) == SP_REGNUM)
13965 return 0;
9e7454d0 13966
cffb2a26 13967 /* Oh dear. The argument is pointed to by a register rather
13968 than being held in a register, or being stored at a known
13969 offset from the frame pointer. Since GDB only understands
13970 those two kinds of argument we must translate the address
13971 held in the register into an offset from the frame pointer.
13972 We do this by searching through the insns for the function
13973 looking to see where this register gets its value. If the
457275b6 13974 register is initialized from the frame pointer plus an offset
cffb2a26 13975 then we are in luck and we can continue, otherwise we give up.
9e7454d0 13976
cffb2a26 13977 This code is exercised by producing debugging information
13978 for a function with arguments like this:
9e7454d0 13979
cffb2a26 13980 double func (double a, double b, int c, double d) {return d;}
9e7454d0 13981
cffb2a26 13982 Without this code the stab for parameter 'd' will be set to
13983 an offset of 0 from the frame pointer, rather than 8. */
13984
13985 /* The if() statement says:
13986
13987 If the insn is a normal instruction
13988 and if the insn is setting the value in a register
13989 and if the register being set is the register holding the address of the argument
13990 and if the address is computing by an addition
13991 that involves adding to a register
13992 which is the frame pointer
13993 a constant integer
13994
674a8f0b 13995 then... */
9e7454d0 13996
cffb2a26 13997 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
13998 {
9e7454d0 13999 if ( GET_CODE (insn) == INSN
cffb2a26 14000 && GET_CODE (PATTERN (insn)) == SET
14001 && REGNO (XEXP (PATTERN (insn), 0)) == REGNO (addr)
14002 && GET_CODE (XEXP (PATTERN (insn), 1)) == PLUS
14003 && GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 0)) == REG
0bd59681 14004 && REGNO (XEXP (XEXP (PATTERN (insn), 1), 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
cffb2a26 14005 && GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 1)) == CONST_INT
14006 )
14007 {
14008 value = INTVAL (XEXP (XEXP (PATTERN (insn), 1), 1));
9e7454d0 14009
cffb2a26 14010 break;
14011 }
14012 }
9e7454d0 14013
cffb2a26 14014 if (value == 0)
14015 {
14016 debug_rtx (addr);
c3ceba8e 14017 warning (0, "unable to compute real location of stacked parameter");
cffb2a26 14018 value = 8; /* XXX magic hack */
14019 }
14020
14021 return value;
14022}
cffb2a26 14023\f
755eb2b4 14024#define def_mbuiltin(MASK, NAME, TYPE, CODE) \
14025 do \
14026 { \
14027 if ((MASK) & insn_flags) \
54be5d7e 14028 add_builtin_function ((NAME), (TYPE), (CODE), \
14029 BUILT_IN_MD, NULL, NULL_TREE); \
755eb2b4 14030 } \
14031 while (0)
14032
14033struct builtin_description
14034{
14035 const unsigned int mask;
14036 const enum insn_code icode;
14037 const char * const name;
14038 const enum arm_builtins code;
14039 const enum rtx_code comparison;
14040 const unsigned int flag;
14041};
14042
14043static const struct builtin_description bdesc_2arg[] =
14044{
14045#define IWMMXT_BUILTIN(code, string, builtin) \
14046 { FL_IWMMXT, CODE_FOR_##code, "__builtin_arm_" string, \
14047 ARM_BUILTIN_##builtin, 0, 0 },
14048
14049 IWMMXT_BUILTIN (addv8qi3, "waddb", WADDB)
14050 IWMMXT_BUILTIN (addv4hi3, "waddh", WADDH)
14051 IWMMXT_BUILTIN (addv2si3, "waddw", WADDW)
14052 IWMMXT_BUILTIN (subv8qi3, "wsubb", WSUBB)
14053 IWMMXT_BUILTIN (subv4hi3, "wsubh", WSUBH)
14054 IWMMXT_BUILTIN (subv2si3, "wsubw", WSUBW)
14055 IWMMXT_BUILTIN (ssaddv8qi3, "waddbss", WADDSSB)
14056 IWMMXT_BUILTIN (ssaddv4hi3, "waddhss", WADDSSH)
14057 IWMMXT_BUILTIN (ssaddv2si3, "waddwss", WADDSSW)
14058 IWMMXT_BUILTIN (sssubv8qi3, "wsubbss", WSUBSSB)
14059 IWMMXT_BUILTIN (sssubv4hi3, "wsubhss", WSUBSSH)
14060 IWMMXT_BUILTIN (sssubv2si3, "wsubwss", WSUBSSW)
14061 IWMMXT_BUILTIN (usaddv8qi3, "waddbus", WADDUSB)
14062 IWMMXT_BUILTIN (usaddv4hi3, "waddhus", WADDUSH)
14063 IWMMXT_BUILTIN (usaddv2si3, "waddwus", WADDUSW)
14064 IWMMXT_BUILTIN (ussubv8qi3, "wsubbus", WSUBUSB)
14065 IWMMXT_BUILTIN (ussubv4hi3, "wsubhus", WSUBUSH)
14066 IWMMXT_BUILTIN (ussubv2si3, "wsubwus", WSUBUSW)
14067 IWMMXT_BUILTIN (mulv4hi3, "wmulul", WMULUL)
08476a09 14068 IWMMXT_BUILTIN (smulv4hi3_highpart, "wmulsm", WMULSM)
14069 IWMMXT_BUILTIN (umulv4hi3_highpart, "wmulum", WMULUM)
755eb2b4 14070 IWMMXT_BUILTIN (eqv8qi3, "wcmpeqb", WCMPEQB)
14071 IWMMXT_BUILTIN (eqv4hi3, "wcmpeqh", WCMPEQH)
14072 IWMMXT_BUILTIN (eqv2si3, "wcmpeqw", WCMPEQW)
14073 IWMMXT_BUILTIN (gtuv8qi3, "wcmpgtub", WCMPGTUB)
14074 IWMMXT_BUILTIN (gtuv4hi3, "wcmpgtuh", WCMPGTUH)
14075 IWMMXT_BUILTIN (gtuv2si3, "wcmpgtuw", WCMPGTUW)
14076 IWMMXT_BUILTIN (gtv8qi3, "wcmpgtsb", WCMPGTSB)
14077 IWMMXT_BUILTIN (gtv4hi3, "wcmpgtsh", WCMPGTSH)
14078 IWMMXT_BUILTIN (gtv2si3, "wcmpgtsw", WCMPGTSW)
14079 IWMMXT_BUILTIN (umaxv8qi3, "wmaxub", WMAXUB)
14080 IWMMXT_BUILTIN (smaxv8qi3, "wmaxsb", WMAXSB)
14081 IWMMXT_BUILTIN (umaxv4hi3, "wmaxuh", WMAXUH)
14082 IWMMXT_BUILTIN (smaxv4hi3, "wmaxsh", WMAXSH)
14083 IWMMXT_BUILTIN (umaxv2si3, "wmaxuw", WMAXUW)
14084 IWMMXT_BUILTIN (smaxv2si3, "wmaxsw", WMAXSW)
14085 IWMMXT_BUILTIN (uminv8qi3, "wminub", WMINUB)
14086 IWMMXT_BUILTIN (sminv8qi3, "wminsb", WMINSB)
14087 IWMMXT_BUILTIN (uminv4hi3, "wminuh", WMINUH)
14088 IWMMXT_BUILTIN (sminv4hi3, "wminsh", WMINSH)
14089 IWMMXT_BUILTIN (uminv2si3, "wminuw", WMINUW)
14090 IWMMXT_BUILTIN (sminv2si3, "wminsw", WMINSW)
14091 IWMMXT_BUILTIN (iwmmxt_anddi3, "wand", WAND)
14092 IWMMXT_BUILTIN (iwmmxt_nanddi3, "wandn", WANDN)
14093 IWMMXT_BUILTIN (iwmmxt_iordi3, "wor", WOR)
14094 IWMMXT_BUILTIN (iwmmxt_xordi3, "wxor", WXOR)
14095 IWMMXT_BUILTIN (iwmmxt_uavgv8qi3, "wavg2b", WAVG2B)
14096 IWMMXT_BUILTIN (iwmmxt_uavgv4hi3, "wavg2h", WAVG2H)
14097 IWMMXT_BUILTIN (iwmmxt_uavgrndv8qi3, "wavg2br", WAVG2BR)
14098 IWMMXT_BUILTIN (iwmmxt_uavgrndv4hi3, "wavg2hr", WAVG2HR)
14099 IWMMXT_BUILTIN (iwmmxt_wunpckilb, "wunpckilb", WUNPCKILB)
14100 IWMMXT_BUILTIN (iwmmxt_wunpckilh, "wunpckilh", WUNPCKILH)
14101 IWMMXT_BUILTIN (iwmmxt_wunpckilw, "wunpckilw", WUNPCKILW)
14102 IWMMXT_BUILTIN (iwmmxt_wunpckihb, "wunpckihb", WUNPCKIHB)
14103 IWMMXT_BUILTIN (iwmmxt_wunpckihh, "wunpckihh", WUNPCKIHH)
14104 IWMMXT_BUILTIN (iwmmxt_wunpckihw, "wunpckihw", WUNPCKIHW)
14105 IWMMXT_BUILTIN (iwmmxt_wmadds, "wmadds", WMADDS)
14106 IWMMXT_BUILTIN (iwmmxt_wmaddu, "wmaddu", WMADDU)
14107
14108#define IWMMXT_BUILTIN2(code, builtin) \
14109 { FL_IWMMXT, CODE_FOR_##code, NULL, ARM_BUILTIN_##builtin, 0, 0 },
9e7454d0 14110
755eb2b4 14111 IWMMXT_BUILTIN2 (iwmmxt_wpackhss, WPACKHSS)
14112 IWMMXT_BUILTIN2 (iwmmxt_wpackwss, WPACKWSS)
14113 IWMMXT_BUILTIN2 (iwmmxt_wpackdss, WPACKDSS)
14114 IWMMXT_BUILTIN2 (iwmmxt_wpackhus, WPACKHUS)
14115 IWMMXT_BUILTIN2 (iwmmxt_wpackwus, WPACKWUS)
14116 IWMMXT_BUILTIN2 (iwmmxt_wpackdus, WPACKDUS)
14117 IWMMXT_BUILTIN2 (ashlv4hi3_di, WSLLH)
d98a3884 14118 IWMMXT_BUILTIN2 (ashlv4hi3_iwmmxt, WSLLHI)
755eb2b4 14119 IWMMXT_BUILTIN2 (ashlv2si3_di, WSLLW)
d98a3884 14120 IWMMXT_BUILTIN2 (ashlv2si3_iwmmxt, WSLLWI)
755eb2b4 14121 IWMMXT_BUILTIN2 (ashldi3_di, WSLLD)
14122 IWMMXT_BUILTIN2 (ashldi3_iwmmxt, WSLLDI)
14123 IWMMXT_BUILTIN2 (lshrv4hi3_di, WSRLH)
d98a3884 14124 IWMMXT_BUILTIN2 (lshrv4hi3_iwmmxt, WSRLHI)
755eb2b4 14125 IWMMXT_BUILTIN2 (lshrv2si3_di, WSRLW)
d98a3884 14126 IWMMXT_BUILTIN2 (lshrv2si3_iwmmxt, WSRLWI)
755eb2b4 14127 IWMMXT_BUILTIN2 (lshrdi3_di, WSRLD)
a2cd141b 14128 IWMMXT_BUILTIN2 (lshrdi3_iwmmxt, WSRLDI)
755eb2b4 14129 IWMMXT_BUILTIN2 (ashrv4hi3_di, WSRAH)
d98a3884 14130 IWMMXT_BUILTIN2 (ashrv4hi3_iwmmxt, WSRAHI)
755eb2b4 14131 IWMMXT_BUILTIN2 (ashrv2si3_di, WSRAW)
d98a3884 14132 IWMMXT_BUILTIN2 (ashrv2si3_iwmmxt, WSRAWI)
755eb2b4 14133 IWMMXT_BUILTIN2 (ashrdi3_di, WSRAD)
a2cd141b 14134 IWMMXT_BUILTIN2 (ashrdi3_iwmmxt, WSRADI)
755eb2b4 14135 IWMMXT_BUILTIN2 (rorv4hi3_di, WRORH)
14136 IWMMXT_BUILTIN2 (rorv4hi3, WRORHI)
14137 IWMMXT_BUILTIN2 (rorv2si3_di, WRORW)
14138 IWMMXT_BUILTIN2 (rorv2si3, WRORWI)
14139 IWMMXT_BUILTIN2 (rordi3_di, WRORD)
14140 IWMMXT_BUILTIN2 (rordi3, WRORDI)
14141 IWMMXT_BUILTIN2 (iwmmxt_wmacuz, WMACUZ)
14142 IWMMXT_BUILTIN2 (iwmmxt_wmacsz, WMACSZ)
14143};
14144
14145static const struct builtin_description bdesc_1arg[] =
14146{
14147 IWMMXT_BUILTIN (iwmmxt_tmovmskb, "tmovmskb", TMOVMSKB)
14148 IWMMXT_BUILTIN (iwmmxt_tmovmskh, "tmovmskh", TMOVMSKH)
14149 IWMMXT_BUILTIN (iwmmxt_tmovmskw, "tmovmskw", TMOVMSKW)
14150 IWMMXT_BUILTIN (iwmmxt_waccb, "waccb", WACCB)
14151 IWMMXT_BUILTIN (iwmmxt_wacch, "wacch", WACCH)
14152 IWMMXT_BUILTIN (iwmmxt_waccw, "waccw", WACCW)
14153 IWMMXT_BUILTIN (iwmmxt_wunpckehub, "wunpckehub", WUNPCKEHUB)
14154 IWMMXT_BUILTIN (iwmmxt_wunpckehuh, "wunpckehuh", WUNPCKEHUH)
14155 IWMMXT_BUILTIN (iwmmxt_wunpckehuw, "wunpckehuw", WUNPCKEHUW)
14156 IWMMXT_BUILTIN (iwmmxt_wunpckehsb, "wunpckehsb", WUNPCKEHSB)
14157 IWMMXT_BUILTIN (iwmmxt_wunpckehsh, "wunpckehsh", WUNPCKEHSH)
14158 IWMMXT_BUILTIN (iwmmxt_wunpckehsw, "wunpckehsw", WUNPCKEHSW)
14159 IWMMXT_BUILTIN (iwmmxt_wunpckelub, "wunpckelub", WUNPCKELUB)
14160 IWMMXT_BUILTIN (iwmmxt_wunpckeluh, "wunpckeluh", WUNPCKELUH)
14161 IWMMXT_BUILTIN (iwmmxt_wunpckeluw, "wunpckeluw", WUNPCKELUW)
14162 IWMMXT_BUILTIN (iwmmxt_wunpckelsb, "wunpckelsb", WUNPCKELSB)
14163 IWMMXT_BUILTIN (iwmmxt_wunpckelsh, "wunpckelsh", WUNPCKELSH)
14164 IWMMXT_BUILTIN (iwmmxt_wunpckelsw, "wunpckelsw", WUNPCKELSW)
14165};
14166
14167/* Set up all the iWMMXt builtins. This is
14168 not called if TARGET_IWMMXT is zero. */
14169
14170static void
14171arm_init_iwmmxt_builtins (void)
14172{
14173 const struct builtin_description * d;
14174 size_t i;
14175 tree endlink = void_list_node;
14176
4917c376 14177 tree V2SI_type_node = build_vector_type_for_mode (intSI_type_node, V2SImode);
14178 tree V4HI_type_node = build_vector_type_for_mode (intHI_type_node, V4HImode);
14179 tree V8QI_type_node = build_vector_type_for_mode (intQI_type_node, V8QImode);
14180
755eb2b4 14181 tree int_ftype_int
14182 = build_function_type (integer_type_node,
14183 tree_cons (NULL_TREE, integer_type_node, endlink));
14184 tree v8qi_ftype_v8qi_v8qi_int
14185 = build_function_type (V8QI_type_node,
14186 tree_cons (NULL_TREE, V8QI_type_node,
14187 tree_cons (NULL_TREE, V8QI_type_node,
14188 tree_cons (NULL_TREE,
14189 integer_type_node,
14190 endlink))));
14191 tree v4hi_ftype_v4hi_int
14192 = build_function_type (V4HI_type_node,
14193 tree_cons (NULL_TREE, V4HI_type_node,
14194 tree_cons (NULL_TREE, integer_type_node,
14195 endlink)));
14196 tree v2si_ftype_v2si_int
14197 = build_function_type (V2SI_type_node,
14198 tree_cons (NULL_TREE, V2SI_type_node,
14199 tree_cons (NULL_TREE, integer_type_node,
14200 endlink)));
14201 tree v2si_ftype_di_di
14202 = build_function_type (V2SI_type_node,
14203 tree_cons (NULL_TREE, long_long_integer_type_node,
14204 tree_cons (NULL_TREE, long_long_integer_type_node,
14205 endlink)));
14206 tree di_ftype_di_int
14207 = build_function_type (long_long_integer_type_node,
14208 tree_cons (NULL_TREE, long_long_integer_type_node,
14209 tree_cons (NULL_TREE, integer_type_node,
14210 endlink)));
14211 tree di_ftype_di_int_int
14212 = build_function_type (long_long_integer_type_node,
14213 tree_cons (NULL_TREE, long_long_integer_type_node,
14214 tree_cons (NULL_TREE, integer_type_node,
14215 tree_cons (NULL_TREE,
14216 integer_type_node,
14217 endlink))));
14218 tree int_ftype_v8qi
14219 = build_function_type (integer_type_node,
14220 tree_cons (NULL_TREE, V8QI_type_node,
14221 endlink));
14222 tree int_ftype_v4hi
14223 = build_function_type (integer_type_node,
14224 tree_cons (NULL_TREE, V4HI_type_node,
14225 endlink));
14226 tree int_ftype_v2si
14227 = build_function_type (integer_type_node,
14228 tree_cons (NULL_TREE, V2SI_type_node,
14229 endlink));
14230 tree int_ftype_v8qi_int
14231 = build_function_type (integer_type_node,
14232 tree_cons (NULL_TREE, V8QI_type_node,
14233 tree_cons (NULL_TREE, integer_type_node,
14234 endlink)));
14235 tree int_ftype_v4hi_int
14236 = build_function_type (integer_type_node,
14237 tree_cons (NULL_TREE, V4HI_type_node,
14238 tree_cons (NULL_TREE, integer_type_node,
14239 endlink)));
14240 tree int_ftype_v2si_int
14241 = build_function_type (integer_type_node,
14242 tree_cons (NULL_TREE, V2SI_type_node,
14243 tree_cons (NULL_TREE, integer_type_node,
14244 endlink)));
14245 tree v8qi_ftype_v8qi_int_int
14246 = build_function_type (V8QI_type_node,
14247 tree_cons (NULL_TREE, V8QI_type_node,
14248 tree_cons (NULL_TREE, integer_type_node,
14249 tree_cons (NULL_TREE,
14250 integer_type_node,
14251 endlink))));
14252 tree v4hi_ftype_v4hi_int_int
14253 = build_function_type (V4HI_type_node,
14254 tree_cons (NULL_TREE, V4HI_type_node,
14255 tree_cons (NULL_TREE, integer_type_node,
14256 tree_cons (NULL_TREE,
14257 integer_type_node,
14258 endlink))));
14259 tree v2si_ftype_v2si_int_int
14260 = build_function_type (V2SI_type_node,
14261 tree_cons (NULL_TREE, V2SI_type_node,
14262 tree_cons (NULL_TREE, integer_type_node,
14263 tree_cons (NULL_TREE,
14264 integer_type_node,
14265 endlink))));
14266 /* Miscellaneous. */
14267 tree v8qi_ftype_v4hi_v4hi
14268 = build_function_type (V8QI_type_node,
14269 tree_cons (NULL_TREE, V4HI_type_node,
14270 tree_cons (NULL_TREE, V4HI_type_node,
14271 endlink)));
14272 tree v4hi_ftype_v2si_v2si
14273 = build_function_type (V4HI_type_node,
14274 tree_cons (NULL_TREE, V2SI_type_node,
14275 tree_cons (NULL_TREE, V2SI_type_node,
14276 endlink)));
14277 tree v2si_ftype_v4hi_v4hi
14278 = build_function_type (V2SI_type_node,
14279 tree_cons (NULL_TREE, V4HI_type_node,
14280 tree_cons (NULL_TREE, V4HI_type_node,
14281 endlink)));
14282 tree v2si_ftype_v8qi_v8qi
14283 = build_function_type (V2SI_type_node,
14284 tree_cons (NULL_TREE, V8QI_type_node,
14285 tree_cons (NULL_TREE, V8QI_type_node,
14286 endlink)));
14287 tree v4hi_ftype_v4hi_di
14288 = build_function_type (V4HI_type_node,
14289 tree_cons (NULL_TREE, V4HI_type_node,
14290 tree_cons (NULL_TREE,
14291 long_long_integer_type_node,
14292 endlink)));
14293 tree v2si_ftype_v2si_di
14294 = build_function_type (V2SI_type_node,
14295 tree_cons (NULL_TREE, V2SI_type_node,
14296 tree_cons (NULL_TREE,
14297 long_long_integer_type_node,
14298 endlink)));
14299 tree void_ftype_int_int
14300 = build_function_type (void_type_node,
14301 tree_cons (NULL_TREE, integer_type_node,
14302 tree_cons (NULL_TREE, integer_type_node,
14303 endlink)));
14304 tree di_ftype_void
14305 = build_function_type (long_long_unsigned_type_node, endlink);
14306 tree di_ftype_v8qi
14307 = build_function_type (long_long_integer_type_node,
14308 tree_cons (NULL_TREE, V8QI_type_node,
14309 endlink));
14310 tree di_ftype_v4hi
14311 = build_function_type (long_long_integer_type_node,
14312 tree_cons (NULL_TREE, V4HI_type_node,
14313 endlink));
14314 tree di_ftype_v2si
14315 = build_function_type (long_long_integer_type_node,
14316 tree_cons (NULL_TREE, V2SI_type_node,
14317 endlink));
14318 tree v2si_ftype_v4hi
14319 = build_function_type (V2SI_type_node,
14320 tree_cons (NULL_TREE, V4HI_type_node,
14321 endlink));
14322 tree v4hi_ftype_v8qi
14323 = build_function_type (V4HI_type_node,
14324 tree_cons (NULL_TREE, V8QI_type_node,
14325 endlink));
14326
14327 tree di_ftype_di_v4hi_v4hi
14328 = build_function_type (long_long_unsigned_type_node,
14329 tree_cons (NULL_TREE,
14330 long_long_unsigned_type_node,
14331 tree_cons (NULL_TREE, V4HI_type_node,
14332 tree_cons (NULL_TREE,
14333 V4HI_type_node,
14334 endlink))));
14335
14336 tree di_ftype_v4hi_v4hi
14337 = build_function_type (long_long_unsigned_type_node,
14338 tree_cons (NULL_TREE, V4HI_type_node,
14339 tree_cons (NULL_TREE, V4HI_type_node,
14340 endlink)));
14341
14342 /* Normal vector binops. */
14343 tree v8qi_ftype_v8qi_v8qi
14344 = build_function_type (V8QI_type_node,
14345 tree_cons (NULL_TREE, V8QI_type_node,
14346 tree_cons (NULL_TREE, V8QI_type_node,
14347 endlink)));
14348 tree v4hi_ftype_v4hi_v4hi
14349 = build_function_type (V4HI_type_node,
14350 tree_cons (NULL_TREE, V4HI_type_node,
14351 tree_cons (NULL_TREE, V4HI_type_node,
14352 endlink)));
14353 tree v2si_ftype_v2si_v2si
14354 = build_function_type (V2SI_type_node,
14355 tree_cons (NULL_TREE, V2SI_type_node,
14356 tree_cons (NULL_TREE, V2SI_type_node,
14357 endlink)));
14358 tree di_ftype_di_di
14359 = build_function_type (long_long_unsigned_type_node,
14360 tree_cons (NULL_TREE, long_long_unsigned_type_node,
14361 tree_cons (NULL_TREE,
14362 long_long_unsigned_type_node,
14363 endlink)));
14364
14365 /* Add all builtins that are more or less simple operations on two
14366 operands. */
3b9d9482 14367 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
755eb2b4 14368 {
14369 /* Use one of the operands; the target can have a different mode for
14370 mask-generating compares. */
14371 enum machine_mode mode;
14372 tree type;
14373
14374 if (d->name == 0)
14375 continue;
14376
14377 mode = insn_data[d->icode].operand[1].mode;
14378
14379 switch (mode)
14380 {
14381 case V8QImode:
14382 type = v8qi_ftype_v8qi_v8qi;
14383 break;
14384 case V4HImode:
14385 type = v4hi_ftype_v4hi_v4hi;
14386 break;
14387 case V2SImode:
14388 type = v2si_ftype_v2si_v2si;
14389 break;
14390 case DImode:
14391 type = di_ftype_di_di;
14392 break;
14393
14394 default:
ed29c566 14395 gcc_unreachable ();
755eb2b4 14396 }
14397
14398 def_mbuiltin (d->mask, d->name, type, d->code);
14399 }
14400
14401 /* Add the remaining MMX insns with somewhat more complicated types. */
14402 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wzero", di_ftype_void, ARM_BUILTIN_WZERO);
14403 def_mbuiltin (FL_IWMMXT, "__builtin_arm_setwcx", void_ftype_int_int, ARM_BUILTIN_SETWCX);
14404 def_mbuiltin (FL_IWMMXT, "__builtin_arm_getwcx", int_ftype_int, ARM_BUILTIN_GETWCX);
14405
14406 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSLLH);
14407 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllw", v2si_ftype_v2si_di, ARM_BUILTIN_WSLLW);
14408 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wslld", di_ftype_di_di, ARM_BUILTIN_WSLLD);
14409 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSLLHI);
14410 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllwi", v2si_ftype_v2si_int, ARM_BUILTIN_WSLLWI);
14411 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wslldi", di_ftype_di_int, ARM_BUILTIN_WSLLDI);
14412
14413 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSRLH);
14414 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlw", v2si_ftype_v2si_di, ARM_BUILTIN_WSRLW);
14415 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrld", di_ftype_di_di, ARM_BUILTIN_WSRLD);
14416 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSRLHI);
14417 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlwi", v2si_ftype_v2si_int, ARM_BUILTIN_WSRLWI);
14418 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrldi", di_ftype_di_int, ARM_BUILTIN_WSRLDI);
14419
14420 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrah", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSRAH);
14421 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsraw", v2si_ftype_v2si_di, ARM_BUILTIN_WSRAW);
14422 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrad", di_ftype_di_di, ARM_BUILTIN_WSRAD);
14423 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrahi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSRAHI);
14424 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrawi", v2si_ftype_v2si_int, ARM_BUILTIN_WSRAWI);
14425 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsradi", di_ftype_di_int, ARM_BUILTIN_WSRADI);
14426
14427 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WRORH);
14428 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorw", v2si_ftype_v2si_di, ARM_BUILTIN_WRORW);
14429 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrord", di_ftype_di_di, ARM_BUILTIN_WRORD);
14430 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WRORHI);
14431 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorwi", v2si_ftype_v2si_int, ARM_BUILTIN_WRORWI);
14432 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrordi", di_ftype_di_int, ARM_BUILTIN_WRORDI);
14433
14434 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wshufh", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSHUFH);
14435
14436 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadb", v2si_ftype_v8qi_v8qi, ARM_BUILTIN_WSADB);
14437 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadh", v2si_ftype_v4hi_v4hi, ARM_BUILTIN_WSADH);
14438 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadbz", v2si_ftype_v8qi_v8qi, ARM_BUILTIN_WSADBZ);
14439 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadhz", v2si_ftype_v4hi_v4hi, ARM_BUILTIN_WSADHZ);
14440
14441 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsb", int_ftype_v8qi_int, ARM_BUILTIN_TEXTRMSB);
14442 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsh", int_ftype_v4hi_int, ARM_BUILTIN_TEXTRMSH);
14443 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsw", int_ftype_v2si_int, ARM_BUILTIN_TEXTRMSW);
14444 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmub", int_ftype_v8qi_int, ARM_BUILTIN_TEXTRMUB);
14445 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmuh", int_ftype_v4hi_int, ARM_BUILTIN_TEXTRMUH);
14446 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmuw", int_ftype_v2si_int, ARM_BUILTIN_TEXTRMUW);
14447 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrb", v8qi_ftype_v8qi_int_int, ARM_BUILTIN_TINSRB);
14448 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrh", v4hi_ftype_v4hi_int_int, ARM_BUILTIN_TINSRH);
14449 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrw", v2si_ftype_v2si_int_int, ARM_BUILTIN_TINSRW);
14450
14451 def_mbuiltin (FL_IWMMXT, "__builtin_arm_waccb", di_ftype_v8qi, ARM_BUILTIN_WACCB);
14452 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wacch", di_ftype_v4hi, ARM_BUILTIN_WACCH);
14453 def_mbuiltin (FL_IWMMXT, "__builtin_arm_waccw", di_ftype_v2si, ARM_BUILTIN_WACCW);
14454
14455 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskb", int_ftype_v8qi, ARM_BUILTIN_TMOVMSKB);
14456 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskh", int_ftype_v4hi, ARM_BUILTIN_TMOVMSKH);
14457 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskw", int_ftype_v2si, ARM_BUILTIN_TMOVMSKW);
14458
14459 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackhss", v8qi_ftype_v4hi_v4hi, ARM_BUILTIN_WPACKHSS);
14460 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackhus", v8qi_ftype_v4hi_v4hi, ARM_BUILTIN_WPACKHUS);
14461 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackwus", v4hi_ftype_v2si_v2si, ARM_BUILTIN_WPACKWUS);
14462 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackwss", v4hi_ftype_v2si_v2si, ARM_BUILTIN_WPACKWSS);
14463 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackdus", v2si_ftype_di_di, ARM_BUILTIN_WPACKDUS);
14464 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackdss", v2si_ftype_di_di, ARM_BUILTIN_WPACKDSS);
14465
14466 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehub", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKEHUB);
14467 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehuh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKEHUH);
14468 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehuw", di_ftype_v2si, ARM_BUILTIN_WUNPCKEHUW);
14469 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsb", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKEHSB);
14470 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKEHSH);
14471 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsw", di_ftype_v2si, ARM_BUILTIN_WUNPCKEHSW);
14472 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelub", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKELUB);
14473 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckeluh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKELUH);
14474 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckeluw", di_ftype_v2si, ARM_BUILTIN_WUNPCKELUW);
14475 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsb", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKELSB);
14476 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKELSH);
14477 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsw", di_ftype_v2si, ARM_BUILTIN_WUNPCKELSW);
14478
14479 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacs", di_ftype_di_v4hi_v4hi, ARM_BUILTIN_WMACS);
14480 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacsz", di_ftype_v4hi_v4hi, ARM_BUILTIN_WMACSZ);
14481 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacu", di_ftype_di_v4hi_v4hi, ARM_BUILTIN_WMACU);
14482 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacuz", di_ftype_v4hi_v4hi, ARM_BUILTIN_WMACUZ);
14483
14484 def_mbuiltin (FL_IWMMXT, "__builtin_arm_walign", v8qi_ftype_v8qi_v8qi_int, ARM_BUILTIN_WALIGN);
14485 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmia", di_ftype_di_int_int, ARM_BUILTIN_TMIA);
14486 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiaph", di_ftype_di_int_int, ARM_BUILTIN_TMIAPH);
14487 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiabb", di_ftype_di_int_int, ARM_BUILTIN_TMIABB);
14488 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiabt", di_ftype_di_int_int, ARM_BUILTIN_TMIABT);
14489 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiatb", di_ftype_di_int_int, ARM_BUILTIN_TMIATB);
14490 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiatt", di_ftype_di_int_int, ARM_BUILTIN_TMIATT);
14491}
14492
f655717d 14493static void
14494arm_init_tls_builtins (void)
14495{
14496 tree ftype;
14497 tree nothrow = tree_cons (get_identifier ("nothrow"), NULL, NULL);
14498 tree const_nothrow = tree_cons (get_identifier ("const"), NULL, nothrow);
14499
14500 ftype = build_function_type (ptr_type_node, void_list_node);
54be5d7e 14501 add_builtin_function ("__builtin_thread_pointer", ftype,
14502 ARM_BUILTIN_THREAD_POINTER, BUILT_IN_MD,
14503 NULL, const_nothrow);
f655717d 14504}
14505
d98a3884 14506typedef enum {
14507 T_V8QI = 0x0001,
14508 T_V4HI = 0x0002,
14509 T_V2SI = 0x0004,
14510 T_V2SF = 0x0008,
14511 T_DI = 0x0010,
14512 T_V16QI = 0x0020,
14513 T_V8HI = 0x0040,
14514 T_V4SI = 0x0080,
14515 T_V4SF = 0x0100,
14516 T_V2DI = 0x0200,
14517 T_TI = 0x0400,
14518 T_EI = 0x0800,
14519 T_OI = 0x1000
14520} neon_builtin_type_bits;
14521
14522#define v8qi_UP T_V8QI
14523#define v4hi_UP T_V4HI
14524#define v2si_UP T_V2SI
14525#define v2sf_UP T_V2SF
14526#define di_UP T_DI
14527#define v16qi_UP T_V16QI
14528#define v8hi_UP T_V8HI
14529#define v4si_UP T_V4SI
14530#define v4sf_UP T_V4SF
14531#define v2di_UP T_V2DI
14532#define ti_UP T_TI
14533#define ei_UP T_EI
14534#define oi_UP T_OI
14535
14536#define UP(X) X##_UP
14537
14538#define T_MAX 13
14539
14540typedef enum {
14541 NEON_BINOP,
14542 NEON_TERNOP,
14543 NEON_UNOP,
14544 NEON_GETLANE,
14545 NEON_SETLANE,
14546 NEON_CREATE,
14547 NEON_DUP,
14548 NEON_DUPLANE,
14549 NEON_COMBINE,
14550 NEON_SPLIT,
14551 NEON_LANEMUL,
14552 NEON_LANEMULL,
14553 NEON_LANEMULH,
14554 NEON_LANEMAC,
14555 NEON_SCALARMUL,
14556 NEON_SCALARMULL,
14557 NEON_SCALARMULH,
14558 NEON_SCALARMAC,
14559 NEON_CONVERT,
14560 NEON_FIXCONV,
14561 NEON_SELECT,
14562 NEON_RESULTPAIR,
14563 NEON_REINTERP,
14564 NEON_VTBL,
14565 NEON_VTBX,
14566 NEON_LOAD1,
14567 NEON_LOAD1LANE,
14568 NEON_STORE1,
14569 NEON_STORE1LANE,
14570 NEON_LOADSTRUCT,
14571 NEON_LOADSTRUCTLANE,
14572 NEON_STORESTRUCT,
14573 NEON_STORESTRUCTLANE,
14574 NEON_LOGICBINOP,
14575 NEON_SHIFTINSERT,
14576 NEON_SHIFTIMM,
14577 NEON_SHIFTACC
14578} neon_itype;
14579
14580typedef struct {
14581 const char *name;
14582 const neon_itype itype;
14583 const neon_builtin_type_bits bits;
14584 const enum insn_code codes[T_MAX];
14585 const unsigned int num_vars;
14586 unsigned int base_fcode;
14587} neon_builtin_datum;
14588
14589#define CF(N,X) CODE_FOR_neon_##N##X
14590
14591#define VAR1(T, N, A) \
14592 #N, NEON_##T, UP (A), { CF (N, A) }, 1, 0
14593#define VAR2(T, N, A, B) \
14594 #N, NEON_##T, UP (A) | UP (B), { CF (N, A), CF (N, B) }, 2, 0
14595#define VAR3(T, N, A, B, C) \
14596 #N, NEON_##T, UP (A) | UP (B) | UP (C), \
14597 { CF (N, A), CF (N, B), CF (N, C) }, 3, 0
14598#define VAR4(T, N, A, B, C, D) \
14599 #N, NEON_##T, UP (A) | UP (B) | UP (C) | UP (D), \
14600 { CF (N, A), CF (N, B), CF (N, C), CF (N, D) }, 4, 0
14601#define VAR5(T, N, A, B, C, D, E) \
14602 #N, NEON_##T, UP (A) | UP (B) | UP (C) | UP (D) | UP (E), \
14603 { CF (N, A), CF (N, B), CF (N, C), CF (N, D), CF (N, E) }, 5, 0
14604#define VAR6(T, N, A, B, C, D, E, F) \
14605 #N, NEON_##T, UP (A) | UP (B) | UP (C) | UP (D) | UP (E) | UP (F), \
14606 { CF (N, A), CF (N, B), CF (N, C), CF (N, D), CF (N, E), CF (N, F) }, 6, 0
14607#define VAR7(T, N, A, B, C, D, E, F, G) \
14608 #N, NEON_##T, UP (A) | UP (B) | UP (C) | UP (D) | UP (E) | UP (F) | UP (G), \
14609 { CF (N, A), CF (N, B), CF (N, C), CF (N, D), CF (N, E), CF (N, F), \
14610 CF (N, G) }, 7, 0
14611#define VAR8(T, N, A, B, C, D, E, F, G, H) \
14612 #N, NEON_##T, UP (A) | UP (B) | UP (C) | UP (D) | UP (E) | UP (F) | UP (G) \
14613 | UP (H), \
14614 { CF (N, A), CF (N, B), CF (N, C), CF (N, D), CF (N, E), CF (N, F), \
14615 CF (N, G), CF (N, H) }, 8, 0
14616#define VAR9(T, N, A, B, C, D, E, F, G, H, I) \
14617 #N, NEON_##T, UP (A) | UP (B) | UP (C) | UP (D) | UP (E) | UP (F) | UP (G) \
14618 | UP (H) | UP (I), \
14619 { CF (N, A), CF (N, B), CF (N, C), CF (N, D), CF (N, E), CF (N, F), \
14620 CF (N, G), CF (N, H), CF (N, I) }, 9, 0
14621#define VAR10(T, N, A, B, C, D, E, F, G, H, I, J) \
14622 #N, NEON_##T, UP (A) | UP (B) | UP (C) | UP (D) | UP (E) | UP (F) | UP (G) \
14623 | UP (H) | UP (I) | UP (J), \
14624 { CF (N, A), CF (N, B), CF (N, C), CF (N, D), CF (N, E), CF (N, F), \
14625 CF (N, G), CF (N, H), CF (N, I), CF (N, J) }, 10, 0
14626
14627/* The mode entries in the following table correspond to the "key" type of the
14628 instruction variant, i.e. equivalent to that which would be specified after
14629 the assembler mnemonic, which usually refers to the last vector operand.
14630 (Signed/unsigned/polynomial types are not differentiated between though, and
14631 are all mapped onto the same mode for a given element size.) The modes
14632 listed per instruction should be the same as those defined for that
14633 instruction's pattern in neon.md.
14634 WARNING: Variants should be listed in the same increasing order as
14635 neon_builtin_type_bits. */
14636
14637static neon_builtin_datum neon_builtin_data[] =
14638{
14639 { VAR10 (BINOP, vadd,
14640 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) },
14641 { VAR3 (BINOP, vaddl, v8qi, v4hi, v2si) },
14642 { VAR3 (BINOP, vaddw, v8qi, v4hi, v2si) },
14643 { VAR6 (BINOP, vhadd, v8qi, v4hi, v2si, v16qi, v8hi, v4si) },
14644 { VAR8 (BINOP, vqadd, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) },
14645 { VAR3 (BINOP, vaddhn, v8hi, v4si, v2di) },
14646 { VAR8 (BINOP, vmul, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) },
14647 { VAR8 (TERNOP, vmla, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) },
14648 { VAR3 (TERNOP, vmlal, v8qi, v4hi, v2si) },
14649 { VAR8 (TERNOP, vmls, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) },
14650 { VAR3 (TERNOP, vmlsl, v8qi, v4hi, v2si) },
14651 { VAR4 (BINOP, vqdmulh, v4hi, v2si, v8hi, v4si) },
14652 { VAR2 (TERNOP, vqdmlal, v4hi, v2si) },
14653 { VAR2 (TERNOP, vqdmlsl, v4hi, v2si) },
14654 { VAR3 (BINOP, vmull, v8qi, v4hi, v2si) },
14655 { VAR2 (SCALARMULL, vmull_n, v4hi, v2si) },
14656 { VAR2 (LANEMULL, vmull_lane, v4hi, v2si) },
14657 { VAR2 (SCALARMULL, vqdmull_n, v4hi, v2si) },
14658 { VAR2 (LANEMULL, vqdmull_lane, v4hi, v2si) },
14659 { VAR4 (SCALARMULH, vqdmulh_n, v4hi, v2si, v8hi, v4si) },
14660 { VAR4 (LANEMULH, vqdmulh_lane, v4hi, v2si, v8hi, v4si) },
14661 { VAR2 (BINOP, vqdmull, v4hi, v2si) },
14662 { VAR8 (BINOP, vshl, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) },
14663 { VAR8 (BINOP, vqshl, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) },
14664 { VAR8 (SHIFTIMM, vshr_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) },
14665 { VAR3 (SHIFTIMM, vshrn_n, v8hi, v4si, v2di) },
14666 { VAR3 (SHIFTIMM, vqshrn_n, v8hi, v4si, v2di) },
14667 { VAR3 (SHIFTIMM, vqshrun_n, v8hi, v4si, v2di) },
14668 { VAR8 (SHIFTIMM, vshl_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) },
14669 { VAR8 (SHIFTIMM, vqshl_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) },
14670 { VAR8 (SHIFTIMM, vqshlu_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) },
14671 { VAR3 (SHIFTIMM, vshll_n, v8qi, v4hi, v2si) },
14672 { VAR8 (SHIFTACC, vsra_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) },
14673 { VAR10 (BINOP, vsub,
14674 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) },
14675 { VAR3 (BINOP, vsubl, v8qi, v4hi, v2si) },
14676 { VAR3 (BINOP, vsubw, v8qi, v4hi, v2si) },
14677 { VAR8 (BINOP, vqsub, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) },
14678 { VAR6 (BINOP, vhsub, v8qi, v4hi, v2si, v16qi, v8hi, v4si) },
14679 { VAR3 (BINOP, vsubhn, v8hi, v4si, v2di) },
14680 { VAR8 (BINOP, vceq, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) },
14681 { VAR8 (BINOP, vcge, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) },
14682 { VAR8 (BINOP, vcgt, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) },
14683 { VAR2 (BINOP, vcage, v2sf, v4sf) },
14684 { VAR2 (BINOP, vcagt, v2sf, v4sf) },
14685 { VAR6 (BINOP, vtst, v8qi, v4hi, v2si, v16qi, v8hi, v4si) },
14686 { VAR8 (BINOP, vabd, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) },
14687 { VAR3 (BINOP, vabdl, v8qi, v4hi, v2si) },
14688 { VAR6 (TERNOP, vaba, v8qi, v4hi, v2si, v16qi, v8hi, v4si) },
14689 { VAR3 (TERNOP, vabal, v8qi, v4hi, v2si) },
14690 { VAR8 (BINOP, vmax, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) },
14691 { VAR8 (BINOP, vmin, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) },
14692 { VAR4 (BINOP, vpadd, v8qi, v4hi, v2si, v2sf) },
14693 { VAR6 (UNOP, vpaddl, v8qi, v4hi, v2si, v16qi, v8hi, v4si) },
14694 { VAR6 (BINOP, vpadal, v8qi, v4hi, v2si, v16qi, v8hi, v4si) },
14695 { VAR4 (BINOP, vpmax, v8qi, v4hi, v2si, v2sf) },
14696 { VAR4 (BINOP, vpmin, v8qi, v4hi, v2si, v2sf) },
14697 { VAR2 (BINOP, vrecps, v2sf, v4sf) },
14698 { VAR2 (BINOP, vrsqrts, v2sf, v4sf) },
14699 { VAR8 (SHIFTINSERT, vsri_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) },
14700 { VAR8 (SHIFTINSERT, vsli_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) },
14701 { VAR8 (UNOP, vabs, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) },
14702 { VAR6 (UNOP, vqabs, v8qi, v4hi, v2si, v16qi, v8hi, v4si) },
14703 { VAR8 (UNOP, vneg, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) },
14704 { VAR6 (UNOP, vqneg, v8qi, v4hi, v2si, v16qi, v8hi, v4si) },
14705 { VAR6 (UNOP, vcls, v8qi, v4hi, v2si, v16qi, v8hi, v4si) },
14706 { VAR6 (UNOP, vclz, v8qi, v4hi, v2si, v16qi, v8hi, v4si) },
14707 { VAR2 (UNOP, vcnt, v8qi, v16qi) },
14708 { VAR4 (UNOP, vrecpe, v2si, v2sf, v4si, v4sf) },
14709 { VAR4 (UNOP, vrsqrte, v2si, v2sf, v4si, v4sf) },
14710 { VAR6 (UNOP, vmvn, v8qi, v4hi, v2si, v16qi, v8hi, v4si) },
14711 /* FIXME: vget_lane supports more variants than this! */
14712 { VAR10 (GETLANE, vget_lane,
14713 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) },
14714 { VAR10 (SETLANE, vset_lane,
14715 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) },
14716 { VAR5 (CREATE, vcreate, v8qi, v4hi, v2si, v2sf, di) },
14717 { VAR10 (DUP, vdup_n,
14718 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) },
14719 { VAR10 (DUPLANE, vdup_lane,
14720 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) },
14721 { VAR5 (COMBINE, vcombine, v8qi, v4hi, v2si, v2sf, di) },
14722 { VAR5 (SPLIT, vget_high, v16qi, v8hi, v4si, v4sf, v2di) },
14723 { VAR5 (SPLIT, vget_low, v16qi, v8hi, v4si, v4sf, v2di) },
14724 { VAR3 (UNOP, vmovn, v8hi, v4si, v2di) },
14725 { VAR3 (UNOP, vqmovn, v8hi, v4si, v2di) },
14726 { VAR3 (UNOP, vqmovun, v8hi, v4si, v2di) },
14727 { VAR3 (UNOP, vmovl, v8qi, v4hi, v2si) },
14728 { VAR6 (LANEMUL, vmul_lane, v4hi, v2si, v2sf, v8hi, v4si, v4sf) },
14729 { VAR6 (LANEMAC, vmla_lane, v4hi, v2si, v2sf, v8hi, v4si, v4sf) },
14730 { VAR2 (LANEMAC, vmlal_lane, v4hi, v2si) },
14731 { VAR2 (LANEMAC, vqdmlal_lane, v4hi, v2si) },
14732 { VAR6 (LANEMAC, vmls_lane, v4hi, v2si, v2sf, v8hi, v4si, v4sf) },
14733 { VAR2 (LANEMAC, vmlsl_lane, v4hi, v2si) },
14734 { VAR2 (LANEMAC, vqdmlsl_lane, v4hi, v2si) },
14735 { VAR6 (SCALARMUL, vmul_n, v4hi, v2si, v2sf, v8hi, v4si, v4sf) },
14736 { VAR6 (SCALARMAC, vmla_n, v4hi, v2si, v2sf, v8hi, v4si, v4sf) },
14737 { VAR2 (SCALARMAC, vmlal_n, v4hi, v2si) },
14738 { VAR2 (SCALARMAC, vqdmlal_n, v4hi, v2si) },
14739 { VAR6 (SCALARMAC, vmls_n, v4hi, v2si, v2sf, v8hi, v4si, v4sf) },
14740 { VAR2 (SCALARMAC, vmlsl_n, v4hi, v2si) },
14741 { VAR2 (SCALARMAC, vqdmlsl_n, v4hi, v2si) },
14742 { VAR10 (BINOP, vext,
14743 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) },
14744 { VAR8 (UNOP, vrev64, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) },
14745 { VAR4 (UNOP, vrev32, v8qi, v4hi, v16qi, v8hi) },
14746 { VAR2 (UNOP, vrev16, v8qi, v16qi) },
14747 { VAR4 (CONVERT, vcvt, v2si, v2sf, v4si, v4sf) },
14748 { VAR4 (FIXCONV, vcvt_n, v2si, v2sf, v4si, v4sf) },
14749 { VAR10 (SELECT, vbsl,
14750 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) },
14751 { VAR1 (VTBL, vtbl1, v8qi) },
14752 { VAR1 (VTBL, vtbl2, v8qi) },
14753 { VAR1 (VTBL, vtbl3, v8qi) },
14754 { VAR1 (VTBL, vtbl4, v8qi) },
14755 { VAR1 (VTBX, vtbx1, v8qi) },
14756 { VAR1 (VTBX, vtbx2, v8qi) },
14757 { VAR1 (VTBX, vtbx3, v8qi) },
14758 { VAR1 (VTBX, vtbx4, v8qi) },
14759 { VAR8 (RESULTPAIR, vtrn, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) },
14760 { VAR8 (RESULTPAIR, vzip, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) },
14761 { VAR8 (RESULTPAIR, vuzp, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) },
14762 { VAR5 (REINTERP, vreinterpretv8qi, v8qi, v4hi, v2si, v2sf, di) },
14763 { VAR5 (REINTERP, vreinterpretv4hi, v8qi, v4hi, v2si, v2sf, di) },
14764 { VAR5 (REINTERP, vreinterpretv2si, v8qi, v4hi, v2si, v2sf, di) },
14765 { VAR5 (REINTERP, vreinterpretv2sf, v8qi, v4hi, v2si, v2sf, di) },
14766 { VAR5 (REINTERP, vreinterpretdi, v8qi, v4hi, v2si, v2sf, di) },
14767 { VAR5 (REINTERP, vreinterpretv16qi, v16qi, v8hi, v4si, v4sf, v2di) },
14768 { VAR5 (REINTERP, vreinterpretv8hi, v16qi, v8hi, v4si, v4sf, v2di) },
14769 { VAR5 (REINTERP, vreinterpretv4si, v16qi, v8hi, v4si, v4sf, v2di) },
14770 { VAR5 (REINTERP, vreinterpretv4sf, v16qi, v8hi, v4si, v4sf, v2di) },
14771 { VAR5 (REINTERP, vreinterpretv2di, v16qi, v8hi, v4si, v4sf, v2di) },
14772 { VAR10 (LOAD1, vld1,
14773 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) },
14774 { VAR10 (LOAD1LANE, vld1_lane,
14775 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) },
14776 { VAR10 (LOAD1, vld1_dup,
14777 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) },
14778 { VAR10 (STORE1, vst1,
14779 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) },
14780 { VAR10 (STORE1LANE, vst1_lane,
14781 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) },
14782 { VAR9 (LOADSTRUCT,
14783 vld2, v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf) },
14784 { VAR7 (LOADSTRUCTLANE, vld2_lane,
14785 v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf) },
14786 { VAR5 (LOADSTRUCT, vld2_dup, v8qi, v4hi, v2si, v2sf, di) },
14787 { VAR9 (STORESTRUCT, vst2,
14788 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf) },
14789 { VAR7 (STORESTRUCTLANE, vst2_lane,
14790 v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf) },
14791 { VAR9 (LOADSTRUCT,
14792 vld3, v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf) },
14793 { VAR7 (LOADSTRUCTLANE, vld3_lane,
14794 v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf) },
14795 { VAR5 (LOADSTRUCT, vld3_dup, v8qi, v4hi, v2si, v2sf, di) },
14796 { VAR9 (STORESTRUCT, vst3,
14797 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf) },
14798 { VAR7 (STORESTRUCTLANE, vst3_lane,
14799 v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf) },
14800 { VAR9 (LOADSTRUCT, vld4,
14801 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf) },
14802 { VAR7 (LOADSTRUCTLANE, vld4_lane,
14803 v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf) },
14804 { VAR5 (LOADSTRUCT, vld4_dup, v8qi, v4hi, v2si, v2sf, di) },
14805 { VAR9 (STORESTRUCT, vst4,
14806 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf) },
14807 { VAR7 (STORESTRUCTLANE, vst4_lane,
14808 v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf) },
14809 { VAR10 (LOGICBINOP, vand,
14810 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) },
14811 { VAR10 (LOGICBINOP, vorr,
14812 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) },
14813 { VAR10 (BINOP, veor,
14814 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) },
14815 { VAR10 (LOGICBINOP, vbic,
14816 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) },
14817 { VAR10 (LOGICBINOP, vorn,
14818 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }
14819};
14820
14821#undef CF
14822#undef VAR1
14823#undef VAR2
14824#undef VAR3
14825#undef VAR4
14826#undef VAR5
14827#undef VAR6
14828#undef VAR7
14829#undef VAR8
14830#undef VAR9
14831#undef VAR10
14832
14833static void
14834arm_init_neon_builtins (void)
14835{
14836 unsigned int i, fcode = ARM_BUILTIN_NEON_BASE;
14837
14838 /* Create distinguished type nodes for NEON vector element types,
14839 and pointers to values of such types, so we can detect them later. */
14840 tree neon_intQI_type_node = make_signed_type (GET_MODE_PRECISION (QImode));
14841 tree neon_intHI_type_node = make_signed_type (GET_MODE_PRECISION (HImode));
14842 tree neon_polyQI_type_node = make_signed_type (GET_MODE_PRECISION (QImode));
14843 tree neon_polyHI_type_node = make_signed_type (GET_MODE_PRECISION (HImode));
14844 tree neon_intSI_type_node = make_signed_type (GET_MODE_PRECISION (SImode));
14845 tree neon_intDI_type_node = make_signed_type (GET_MODE_PRECISION (DImode));
14846 tree neon_float_type_node = make_node (REAL_TYPE);
14847 TYPE_PRECISION (neon_float_type_node) = FLOAT_TYPE_SIZE;
14848 layout_type (neon_float_type_node);
14849
14850 /* Define typedefs which exactly correspond to the modes we are basing vector
14851 types on. If you change these names you'll need to change
eddcdde1 14852 the table used by arm_mangle_type too. */
d98a3884 14853 (*lang_hooks.types.register_builtin_type) (neon_intQI_type_node,
14854 "__builtin_neon_qi");
14855 (*lang_hooks.types.register_builtin_type) (neon_intHI_type_node,
14856 "__builtin_neon_hi");
14857 (*lang_hooks.types.register_builtin_type) (neon_intSI_type_node,
14858 "__builtin_neon_si");
14859 (*lang_hooks.types.register_builtin_type) (neon_float_type_node,
14860 "__builtin_neon_sf");
14861 (*lang_hooks.types.register_builtin_type) (neon_intDI_type_node,
14862 "__builtin_neon_di");
14863
14864 (*lang_hooks.types.register_builtin_type) (neon_polyQI_type_node,
14865 "__builtin_neon_poly8");
14866 (*lang_hooks.types.register_builtin_type) (neon_polyHI_type_node,
14867 "__builtin_neon_poly16");
14868
14869 tree intQI_pointer_node = build_pointer_type (neon_intQI_type_node);
14870 tree intHI_pointer_node = build_pointer_type (neon_intHI_type_node);
14871 tree intSI_pointer_node = build_pointer_type (neon_intSI_type_node);
14872 tree intDI_pointer_node = build_pointer_type (neon_intDI_type_node);
14873 tree float_pointer_node = build_pointer_type (neon_float_type_node);
14874
14875 /* Next create constant-qualified versions of the above types. */
14876 tree const_intQI_node = build_qualified_type (neon_intQI_type_node,
14877 TYPE_QUAL_CONST);
14878 tree const_intHI_node = build_qualified_type (neon_intHI_type_node,
14879 TYPE_QUAL_CONST);
14880 tree const_intSI_node = build_qualified_type (neon_intSI_type_node,
14881 TYPE_QUAL_CONST);
14882 tree const_intDI_node = build_qualified_type (neon_intDI_type_node,
14883 TYPE_QUAL_CONST);
14884 tree const_float_node = build_qualified_type (neon_float_type_node,
14885 TYPE_QUAL_CONST);
14886
14887 tree const_intQI_pointer_node = build_pointer_type (const_intQI_node);
14888 tree const_intHI_pointer_node = build_pointer_type (const_intHI_node);
14889 tree const_intSI_pointer_node = build_pointer_type (const_intSI_node);
14890 tree const_intDI_pointer_node = build_pointer_type (const_intDI_node);
14891 tree const_float_pointer_node = build_pointer_type (const_float_node);
14892
14893 /* Now create vector types based on our NEON element types. */
14894 /* 64-bit vectors. */
14895 tree V8QI_type_node =
14896 build_vector_type_for_mode (neon_intQI_type_node, V8QImode);
14897 tree V4HI_type_node =
14898 build_vector_type_for_mode (neon_intHI_type_node, V4HImode);
14899 tree V2SI_type_node =
14900 build_vector_type_for_mode (neon_intSI_type_node, V2SImode);
14901 tree V2SF_type_node =
14902 build_vector_type_for_mode (neon_float_type_node, V2SFmode);
14903 /* 128-bit vectors. */
14904 tree V16QI_type_node =
14905 build_vector_type_for_mode (neon_intQI_type_node, V16QImode);
14906 tree V8HI_type_node =
14907 build_vector_type_for_mode (neon_intHI_type_node, V8HImode);
14908 tree V4SI_type_node =
14909 build_vector_type_for_mode (neon_intSI_type_node, V4SImode);
14910 tree V4SF_type_node =
14911 build_vector_type_for_mode (neon_float_type_node, V4SFmode);
14912 tree V2DI_type_node =
14913 build_vector_type_for_mode (neon_intDI_type_node, V2DImode);
14914
14915 /* Unsigned integer types for various mode sizes. */
14916 tree intUQI_type_node = make_unsigned_type (GET_MODE_PRECISION (QImode));
14917 tree intUHI_type_node = make_unsigned_type (GET_MODE_PRECISION (HImode));
14918 tree intUSI_type_node = make_unsigned_type (GET_MODE_PRECISION (SImode));
14919 tree intUDI_type_node = make_unsigned_type (GET_MODE_PRECISION (DImode));
14920
14921 (*lang_hooks.types.register_builtin_type) (intUQI_type_node,
14922 "__builtin_neon_uqi");
14923 (*lang_hooks.types.register_builtin_type) (intUHI_type_node,
14924 "__builtin_neon_uhi");
14925 (*lang_hooks.types.register_builtin_type) (intUSI_type_node,
14926 "__builtin_neon_usi");
14927 (*lang_hooks.types.register_builtin_type) (intUDI_type_node,
14928 "__builtin_neon_udi");
14929
14930 /* Opaque integer types for structures of vectors. */
14931 tree intEI_type_node = make_signed_type (GET_MODE_PRECISION (EImode));
14932 tree intOI_type_node = make_signed_type (GET_MODE_PRECISION (OImode));
14933 tree intCI_type_node = make_signed_type (GET_MODE_PRECISION (CImode));
14934 tree intXI_type_node = make_signed_type (GET_MODE_PRECISION (XImode));
14935
14936 (*lang_hooks.types.register_builtin_type) (intTI_type_node,
14937 "__builtin_neon_ti");
14938 (*lang_hooks.types.register_builtin_type) (intEI_type_node,
14939 "__builtin_neon_ei");
14940 (*lang_hooks.types.register_builtin_type) (intOI_type_node,
14941 "__builtin_neon_oi");
14942 (*lang_hooks.types.register_builtin_type) (intCI_type_node,
14943 "__builtin_neon_ci");
14944 (*lang_hooks.types.register_builtin_type) (intXI_type_node,
14945 "__builtin_neon_xi");
14946
14947 /* Pointers to vector types. */
14948 tree V8QI_pointer_node = build_pointer_type (V8QI_type_node);
14949 tree V4HI_pointer_node = build_pointer_type (V4HI_type_node);
14950 tree V2SI_pointer_node = build_pointer_type (V2SI_type_node);
14951 tree V2SF_pointer_node = build_pointer_type (V2SF_type_node);
14952 tree V16QI_pointer_node = build_pointer_type (V16QI_type_node);
14953 tree V8HI_pointer_node = build_pointer_type (V8HI_type_node);
14954 tree V4SI_pointer_node = build_pointer_type (V4SI_type_node);
14955 tree V4SF_pointer_node = build_pointer_type (V4SF_type_node);
14956 tree V2DI_pointer_node = build_pointer_type (V2DI_type_node);
14957
14958 /* Operations which return results as pairs. */
14959 tree void_ftype_pv8qi_v8qi_v8qi =
14960 build_function_type_list (void_type_node, V8QI_pointer_node, V8QI_type_node,
14961 V8QI_type_node, NULL);
14962 tree void_ftype_pv4hi_v4hi_v4hi =
14963 build_function_type_list (void_type_node, V4HI_pointer_node, V4HI_type_node,
14964 V4HI_type_node, NULL);
14965 tree void_ftype_pv2si_v2si_v2si =
14966 build_function_type_list (void_type_node, V2SI_pointer_node, V2SI_type_node,
14967 V2SI_type_node, NULL);
14968 tree void_ftype_pv2sf_v2sf_v2sf =
14969 build_function_type_list (void_type_node, V2SF_pointer_node, V2SF_type_node,
14970 V2SF_type_node, NULL);
14971 tree void_ftype_pdi_di_di =
14972 build_function_type_list (void_type_node, intDI_pointer_node,
14973 neon_intDI_type_node, neon_intDI_type_node, NULL);
14974 tree void_ftype_pv16qi_v16qi_v16qi =
14975 build_function_type_list (void_type_node, V16QI_pointer_node,
14976 V16QI_type_node, V16QI_type_node, NULL);
14977 tree void_ftype_pv8hi_v8hi_v8hi =
14978 build_function_type_list (void_type_node, V8HI_pointer_node, V8HI_type_node,
14979 V8HI_type_node, NULL);
14980 tree void_ftype_pv4si_v4si_v4si =
14981 build_function_type_list (void_type_node, V4SI_pointer_node, V4SI_type_node,
14982 V4SI_type_node, NULL);
14983 tree void_ftype_pv4sf_v4sf_v4sf =
14984 build_function_type_list (void_type_node, V4SF_pointer_node, V4SF_type_node,
14985 V4SF_type_node, NULL);
14986 tree void_ftype_pv2di_v2di_v2di =
14987 build_function_type_list (void_type_node, V2DI_pointer_node, V2DI_type_node,
14988 V2DI_type_node, NULL);
14989
14990 tree reinterp_ftype_dreg[5][5];
14991 tree reinterp_ftype_qreg[5][5];
14992 tree dreg_types[5], qreg_types[5];
14993
14994 dreg_types[0] = V8QI_type_node;
14995 dreg_types[1] = V4HI_type_node;
14996 dreg_types[2] = V2SI_type_node;
14997 dreg_types[3] = V2SF_type_node;
14998 dreg_types[4] = neon_intDI_type_node;
14999
15000 qreg_types[0] = V16QI_type_node;
15001 qreg_types[1] = V8HI_type_node;
15002 qreg_types[2] = V4SI_type_node;
15003 qreg_types[3] = V4SF_type_node;
15004 qreg_types[4] = V2DI_type_node;
15005
15006 for (i = 0; i < 5; i++)
15007 {
15008 int j;
15009 for (j = 0; j < 5; j++)
15010 {
15011 reinterp_ftype_dreg[i][j]
15012 = build_function_type_list (dreg_types[i], dreg_types[j], NULL);
15013 reinterp_ftype_qreg[i][j]
15014 = build_function_type_list (qreg_types[i], qreg_types[j], NULL);
15015 }
15016 }
15017
15018 for (i = 0; i < ARRAY_SIZE (neon_builtin_data); i++)
15019 {
15020 neon_builtin_datum *d = &neon_builtin_data[i];
15021 unsigned int j, codeidx = 0;
15022
15023 d->base_fcode = fcode;
15024
15025 for (j = 0; j < T_MAX; j++)
15026 {
15027 const char* const modenames[] = {
15028 "v8qi", "v4hi", "v2si", "v2sf", "di",
15029 "v16qi", "v8hi", "v4si", "v4sf", "v2di"
15030 };
15031 char namebuf[60];
15032 tree ftype = NULL;
15033 enum insn_code icode;
15034 int is_load = 0, is_store = 0;
15035
15036 if ((d->bits & (1 << j)) == 0)
15037 continue;
15038
15039 icode = d->codes[codeidx++];
15040
15041 switch (d->itype)
15042 {
15043 case NEON_LOAD1:
15044 case NEON_LOAD1LANE:
15045 case NEON_LOADSTRUCT:
15046 case NEON_LOADSTRUCTLANE:
15047 is_load = 1;
15048 /* Fall through. */
15049 case NEON_STORE1:
15050 case NEON_STORE1LANE:
15051 case NEON_STORESTRUCT:
15052 case NEON_STORESTRUCTLANE:
15053 if (!is_load)
15054 is_store = 1;
15055 /* Fall through. */
15056 case NEON_UNOP:
15057 case NEON_BINOP:
15058 case NEON_LOGICBINOP:
15059 case NEON_SHIFTINSERT:
15060 case NEON_TERNOP:
15061 case NEON_GETLANE:
15062 case NEON_SETLANE:
15063 case NEON_CREATE:
15064 case NEON_DUP:
15065 case NEON_DUPLANE:
15066 case NEON_SHIFTIMM:
15067 case NEON_SHIFTACC:
15068 case NEON_COMBINE:
15069 case NEON_SPLIT:
15070 case NEON_CONVERT:
15071 case NEON_FIXCONV:
15072 case NEON_LANEMUL:
15073 case NEON_LANEMULL:
15074 case NEON_LANEMULH:
15075 case NEON_LANEMAC:
15076 case NEON_SCALARMUL:
15077 case NEON_SCALARMULL:
15078 case NEON_SCALARMULH:
15079 case NEON_SCALARMAC:
15080 case NEON_SELECT:
15081 case NEON_VTBL:
15082 case NEON_VTBX:
15083 {
15084 int k;
15085 tree return_type = void_type_node, args = void_list_node;
15086
15087 /* Build a function type directly from the insn_data for this
15088 builtin. The build_function_type() function takes care of
15089 removing duplicates for us. */
15090 for (k = insn_data[icode].n_operands - 1; k >= 0; k--)
15091 {
15092 tree eltype;
15093
15094 if (is_load && k == 1)
15095 {
15096 /* Neon load patterns always have the memory operand
15097 (a SImode pointer) in the operand 1 position. We
15098 want a const pointer to the element type in that
15099 position. */
15100 gcc_assert (insn_data[icode].operand[k].mode == SImode);
15101
15102 switch (1 << j)
15103 {
15104 case T_V8QI:
15105 case T_V16QI:
15106 eltype = const_intQI_pointer_node;
15107 break;
15108
15109 case T_V4HI:
15110 case T_V8HI:
15111 eltype = const_intHI_pointer_node;
15112 break;
15113
15114 case T_V2SI:
15115 case T_V4SI:
15116 eltype = const_intSI_pointer_node;
15117 break;
15118
15119 case T_V2SF:
15120 case T_V4SF:
15121 eltype = const_float_pointer_node;
15122 break;
15123
15124 case T_DI:
15125 case T_V2DI:
15126 eltype = const_intDI_pointer_node;
15127 break;
15128
15129 default: gcc_unreachable ();
15130 }
15131 }
15132 else if (is_store && k == 0)
15133 {
15134 /* Similarly, Neon store patterns use operand 0 as
15135 the memory location to store to (a SImode pointer).
15136 Use a pointer to the element type of the store in
15137 that position. */
15138 gcc_assert (insn_data[icode].operand[k].mode == SImode);
15139
15140 switch (1 << j)
15141 {
15142 case T_V8QI:
15143 case T_V16QI:
15144 eltype = intQI_pointer_node;
15145 break;
15146
15147 case T_V4HI:
15148 case T_V8HI:
15149 eltype = intHI_pointer_node;
15150 break;
15151
15152 case T_V2SI:
15153 case T_V4SI:
15154 eltype = intSI_pointer_node;
15155 break;
15156
15157 case T_V2SF:
15158 case T_V4SF:
15159 eltype = float_pointer_node;
15160 break;
15161
15162 case T_DI:
15163 case T_V2DI:
15164 eltype = intDI_pointer_node;
15165 break;
15166
15167 default: gcc_unreachable ();
15168 }
15169 }
15170 else
15171 {
15172 switch (insn_data[icode].operand[k].mode)
15173 {
15174 case VOIDmode: eltype = void_type_node; break;
15175 /* Scalars. */
15176 case QImode: eltype = neon_intQI_type_node; break;
15177 case HImode: eltype = neon_intHI_type_node; break;
15178 case SImode: eltype = neon_intSI_type_node; break;
15179 case SFmode: eltype = neon_float_type_node; break;
15180 case DImode: eltype = neon_intDI_type_node; break;
15181 case TImode: eltype = intTI_type_node; break;
15182 case EImode: eltype = intEI_type_node; break;
15183 case OImode: eltype = intOI_type_node; break;
15184 case CImode: eltype = intCI_type_node; break;
15185 case XImode: eltype = intXI_type_node; break;
15186 /* 64-bit vectors. */
15187 case V8QImode: eltype = V8QI_type_node; break;
15188 case V4HImode: eltype = V4HI_type_node; break;
15189 case V2SImode: eltype = V2SI_type_node; break;
15190 case V2SFmode: eltype = V2SF_type_node; break;
15191 /* 128-bit vectors. */
15192 case V16QImode: eltype = V16QI_type_node; break;
15193 case V8HImode: eltype = V8HI_type_node; break;
15194 case V4SImode: eltype = V4SI_type_node; break;
15195 case V4SFmode: eltype = V4SF_type_node; break;
15196 case V2DImode: eltype = V2DI_type_node; break;
15197 default: gcc_unreachable ();
15198 }
15199 }
15200
15201 if (k == 0 && !is_store)
15202 return_type = eltype;
15203 else
15204 args = tree_cons (NULL_TREE, eltype, args);
15205 }
15206
15207 ftype = build_function_type (return_type, args);
15208 }
15209 break;
15210
15211 case NEON_RESULTPAIR:
15212 {
15213 switch (insn_data[icode].operand[1].mode)
15214 {
15215 case V8QImode: ftype = void_ftype_pv8qi_v8qi_v8qi; break;
15216 case V4HImode: ftype = void_ftype_pv4hi_v4hi_v4hi; break;
15217 case V2SImode: ftype = void_ftype_pv2si_v2si_v2si; break;
15218 case V2SFmode: ftype = void_ftype_pv2sf_v2sf_v2sf; break;
15219 case DImode: ftype = void_ftype_pdi_di_di; break;
15220 case V16QImode: ftype = void_ftype_pv16qi_v16qi_v16qi; break;
15221 case V8HImode: ftype = void_ftype_pv8hi_v8hi_v8hi; break;
15222 case V4SImode: ftype = void_ftype_pv4si_v4si_v4si; break;
15223 case V4SFmode: ftype = void_ftype_pv4sf_v4sf_v4sf; break;
15224 case V2DImode: ftype = void_ftype_pv2di_v2di_v2di; break;
15225 default: gcc_unreachable ();
15226 }
15227 }
15228 break;
15229
15230 case NEON_REINTERP:
15231 {
15232 /* We iterate over 5 doubleword types, then 5 quadword
15233 types. */
15234 int rhs = j % 5;
15235 switch (insn_data[icode].operand[0].mode)
15236 {
15237 case V8QImode: ftype = reinterp_ftype_dreg[0][rhs]; break;
15238 case V4HImode: ftype = reinterp_ftype_dreg[1][rhs]; break;
15239 case V2SImode: ftype = reinterp_ftype_dreg[2][rhs]; break;
15240 case V2SFmode: ftype = reinterp_ftype_dreg[3][rhs]; break;
15241 case DImode: ftype = reinterp_ftype_dreg[4][rhs]; break;
15242 case V16QImode: ftype = reinterp_ftype_qreg[0][rhs]; break;
15243 case V8HImode: ftype = reinterp_ftype_qreg[1][rhs]; break;
15244 case V4SImode: ftype = reinterp_ftype_qreg[2][rhs]; break;
15245 case V4SFmode: ftype = reinterp_ftype_qreg[3][rhs]; break;
15246 case V2DImode: ftype = reinterp_ftype_qreg[4][rhs]; break;
15247 default: gcc_unreachable ();
15248 }
15249 }
15250 break;
15251
15252 default:
15253 gcc_unreachable ();
15254 }
15255
15256 gcc_assert (ftype != NULL);
15257
15258 sprintf (namebuf, "__builtin_neon_%s%s", d->name, modenames[j]);
15259
15260 add_builtin_function (namebuf, ftype, fcode++, BUILT_IN_MD, NULL,
15261 NULL_TREE);
15262 }
15263 }
15264}
15265
755eb2b4 15266static void
15267arm_init_builtins (void)
15268{
f655717d 15269 arm_init_tls_builtins ();
15270
755eb2b4 15271 if (TARGET_REALLY_IWMMXT)
15272 arm_init_iwmmxt_builtins ();
d98a3884 15273
15274 if (TARGET_NEON)
15275 arm_init_neon_builtins ();
755eb2b4 15276}
15277
15278/* Errors in the source file can cause expand_expr to return const0_rtx
15279 where we expect a vector. To avoid crashing, use one of the vector
15280 clear instructions. */
15281
15282static rtx
15283safe_vector_operand (rtx x, enum machine_mode mode)
15284{
15285 if (x != const0_rtx)
15286 return x;
15287 x = gen_reg_rtx (mode);
15288
15289 emit_insn (gen_iwmmxt_clrdi (mode == DImode ? x
15290 : gen_rtx_SUBREG (DImode, x, 0)));
15291 return x;
15292}
15293
15294/* Subroutine of arm_expand_builtin to take care of binop insns. */
15295
15296static rtx
15297arm_expand_binop_builtin (enum insn_code icode,
c2f47e15 15298 tree exp, rtx target)
755eb2b4 15299{
15300 rtx pat;
c2f47e15 15301 tree arg0 = CALL_EXPR_ARG (exp, 0);
15302 tree arg1 = CALL_EXPR_ARG (exp, 1);
8ec3c5c2 15303 rtx op0 = expand_normal (arg0);
15304 rtx op1 = expand_normal (arg1);
755eb2b4 15305 enum machine_mode tmode = insn_data[icode].operand[0].mode;
15306 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
15307 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
15308
15309 if (VECTOR_MODE_P (mode0))
15310 op0 = safe_vector_operand (op0, mode0);
15311 if (VECTOR_MODE_P (mode1))
15312 op1 = safe_vector_operand (op1, mode1);
15313
15314 if (! target
15315 || GET_MODE (target) != tmode
15316 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
15317 target = gen_reg_rtx (tmode);
15318
ed29c566 15319 gcc_assert (GET_MODE (op0) == mode0 && GET_MODE (op1) == mode1);
755eb2b4 15320
15321 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
15322 op0 = copy_to_mode_reg (mode0, op0);
15323 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
15324 op1 = copy_to_mode_reg (mode1, op1);
15325
15326 pat = GEN_FCN (icode) (target, op0, op1);
15327 if (! pat)
15328 return 0;
15329 emit_insn (pat);
15330 return target;
15331}
15332
15333/* Subroutine of arm_expand_builtin to take care of unop insns. */
15334
15335static rtx
15336arm_expand_unop_builtin (enum insn_code icode,
c2f47e15 15337 tree exp, rtx target, int do_load)
755eb2b4 15338{
15339 rtx pat;
c2f47e15 15340 tree arg0 = CALL_EXPR_ARG (exp, 0);
8ec3c5c2 15341 rtx op0 = expand_normal (arg0);
755eb2b4 15342 enum machine_mode tmode = insn_data[icode].operand[0].mode;
15343 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
15344
15345 if (! target
15346 || GET_MODE (target) != tmode
15347 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
15348 target = gen_reg_rtx (tmode);
15349 if (do_load)
15350 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
15351 else
15352 {
15353 if (VECTOR_MODE_P (mode0))
15354 op0 = safe_vector_operand (op0, mode0);
15355
15356 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
15357 op0 = copy_to_mode_reg (mode0, op0);
15358 }
15359
15360 pat = GEN_FCN (icode) (target, op0);
15361 if (! pat)
15362 return 0;
15363 emit_insn (pat);
15364 return target;
15365}
15366
d98a3884 15367static int
15368neon_builtin_compare (const void *a, const void *b)
15369{
15370 const neon_builtin_datum *key = a;
15371 const neon_builtin_datum *memb = b;
15372 unsigned int soughtcode = key->base_fcode;
15373
15374 if (soughtcode >= memb->base_fcode
15375 && soughtcode < memb->base_fcode + memb->num_vars)
15376 return 0;
15377 else if (soughtcode < memb->base_fcode)
15378 return -1;
15379 else
15380 return 1;
15381}
15382
15383static enum insn_code
15384locate_neon_builtin_icode (int fcode, neon_itype *itype)
15385{
15386 neon_builtin_datum key, *found;
15387 int idx;
15388
15389 key.base_fcode = fcode;
15390 found = bsearch (&key, &neon_builtin_data[0], ARRAY_SIZE (neon_builtin_data),
15391 sizeof (neon_builtin_data[0]), neon_builtin_compare);
15392 gcc_assert (found);
15393 idx = fcode - (int) found->base_fcode;
15394 gcc_assert (idx >= 0 && idx < T_MAX && idx < (int)found->num_vars);
15395
15396 if (itype)
15397 *itype = found->itype;
15398
15399 return found->codes[idx];
15400}
15401
15402typedef enum {
15403 NEON_ARG_COPY_TO_REG,
15404 NEON_ARG_CONSTANT,
15405 NEON_ARG_STOP
15406} builtin_arg;
15407
15408#define NEON_MAX_BUILTIN_ARGS 5
15409
15410/* Expand a Neon builtin. */
15411static rtx
15412arm_expand_neon_args (rtx target, int icode, int have_retval,
15413 tree exp, ...)
15414{
15415 va_list ap;
15416 rtx pat;
15417 tree arg[NEON_MAX_BUILTIN_ARGS];
15418 rtx op[NEON_MAX_BUILTIN_ARGS];
15419 enum machine_mode tmode = insn_data[icode].operand[0].mode;
15420 enum machine_mode mode[NEON_MAX_BUILTIN_ARGS];
15421 int argc = 0;
15422
15423 if (have_retval
15424 && (!target
15425 || GET_MODE (target) != tmode
15426 || !(*insn_data[icode].operand[0].predicate) (target, tmode)))
15427 target = gen_reg_rtx (tmode);
15428
15429 va_start (ap, exp);
15430
15431 for (;;)
15432 {
15433 builtin_arg thisarg = va_arg (ap, int);
15434
15435 if (thisarg == NEON_ARG_STOP)
15436 break;
15437 else
15438 {
15439 arg[argc] = CALL_EXPR_ARG (exp, argc);
15440 op[argc] = expand_normal (arg[argc]);
15441 mode[argc] = insn_data[icode].operand[argc + have_retval].mode;
15442
15443 switch (thisarg)
15444 {
15445 case NEON_ARG_COPY_TO_REG:
15446 /*gcc_assert (GET_MODE (op[argc]) == mode[argc]);*/
15447 if (!(*insn_data[icode].operand[argc + have_retval].predicate)
15448 (op[argc], mode[argc]))
15449 op[argc] = copy_to_mode_reg (mode[argc], op[argc]);
15450 break;
15451
15452 case NEON_ARG_CONSTANT:
15453 /* FIXME: This error message is somewhat unhelpful. */
15454 if (!(*insn_data[icode].operand[argc + have_retval].predicate)
15455 (op[argc], mode[argc]))
15456 error ("argument must be a constant");
15457 break;
15458
15459 case NEON_ARG_STOP:
15460 gcc_unreachable ();
15461 }
15462
15463 argc++;
15464 }
15465 }
15466
15467 va_end (ap);
15468
15469 if (have_retval)
15470 switch (argc)
15471 {
15472 case 1:
15473 pat = GEN_FCN (icode) (target, op[0]);
15474 break;
15475
15476 case 2:
15477 pat = GEN_FCN (icode) (target, op[0], op[1]);
15478 break;
15479
15480 case 3:
15481 pat = GEN_FCN (icode) (target, op[0], op[1], op[2]);
15482 break;
15483
15484 case 4:
15485 pat = GEN_FCN (icode) (target, op[0], op[1], op[2], op[3]);
15486 break;
15487
15488 case 5:
15489 pat = GEN_FCN (icode) (target, op[0], op[1], op[2], op[3], op[4]);
15490 break;
15491
15492 default:
15493 gcc_unreachable ();
15494 }
15495 else
15496 switch (argc)
15497 {
15498 case 1:
15499 pat = GEN_FCN (icode) (op[0]);
15500 break;
15501
15502 case 2:
15503 pat = GEN_FCN (icode) (op[0], op[1]);
15504 break;
15505
15506 case 3:
15507 pat = GEN_FCN (icode) (op[0], op[1], op[2]);
15508 break;
15509
15510 case 4:
15511 pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3]);
15512 break;
15513
15514 case 5:
15515 pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3], op[4]);
15516 break;
15517
15518 default:
15519 gcc_unreachable ();
15520 }
15521
15522 if (!pat)
15523 return 0;
15524
15525 emit_insn (pat);
15526
15527 return target;
15528}
15529
15530/* Expand a Neon builtin. These are "special" because they don't have symbolic
15531 constants defined per-instruction or per instruction-variant. Instead, the
15532 required info is looked up in the table neon_builtin_data. */
15533static rtx
15534arm_expand_neon_builtin (int fcode, tree exp, rtx target)
15535{
15536 neon_itype itype;
15537 enum insn_code icode = locate_neon_builtin_icode (fcode, &itype);
15538
15539 switch (itype)
15540 {
15541 case NEON_UNOP:
15542 case NEON_CONVERT:
15543 case NEON_DUPLANE:
15544 return arm_expand_neon_args (target, icode, 1, exp,
15545 NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, NEON_ARG_STOP);
15546
15547 case NEON_BINOP:
15548 case NEON_SETLANE:
15549 case NEON_SCALARMUL:
15550 case NEON_SCALARMULL:
15551 case NEON_SCALARMULH:
15552 case NEON_SHIFTINSERT:
15553 case NEON_LOGICBINOP:
15554 return arm_expand_neon_args (target, icode, 1, exp,
15555 NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT,
15556 NEON_ARG_STOP);
15557
15558 case NEON_TERNOP:
15559 return arm_expand_neon_args (target, icode, 1, exp,
15560 NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG,
15561 NEON_ARG_CONSTANT, NEON_ARG_STOP);
15562
15563 case NEON_GETLANE:
15564 case NEON_FIXCONV:
15565 case NEON_SHIFTIMM:
15566 return arm_expand_neon_args (target, icode, 1, exp,
15567 NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, NEON_ARG_CONSTANT,
15568 NEON_ARG_STOP);
15569
15570 case NEON_CREATE:
15571 return arm_expand_neon_args (target, icode, 1, exp,
15572 NEON_ARG_COPY_TO_REG, NEON_ARG_STOP);
15573
15574 case NEON_DUP:
15575 case NEON_SPLIT:
15576 case NEON_REINTERP:
15577 return arm_expand_neon_args (target, icode, 1, exp,
15578 NEON_ARG_COPY_TO_REG, NEON_ARG_STOP);
15579
15580 case NEON_COMBINE:
15581 case NEON_VTBL:
15582 return arm_expand_neon_args (target, icode, 1, exp,
15583 NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_STOP);
15584
15585 case NEON_RESULTPAIR:
15586 return arm_expand_neon_args (target, icode, 0, exp,
15587 NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG,
15588 NEON_ARG_STOP);
15589
15590 case NEON_LANEMUL:
15591 case NEON_LANEMULL:
15592 case NEON_LANEMULH:
15593 return arm_expand_neon_args (target, icode, 1, exp,
15594 NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT,
15595 NEON_ARG_CONSTANT, NEON_ARG_STOP);
15596
15597 case NEON_LANEMAC:
15598 return arm_expand_neon_args (target, icode, 1, exp,
15599 NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG,
15600 NEON_ARG_CONSTANT, NEON_ARG_CONSTANT, NEON_ARG_STOP);
15601
15602 case NEON_SHIFTACC:
15603 return arm_expand_neon_args (target, icode, 1, exp,
15604 NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT,
15605 NEON_ARG_CONSTANT, NEON_ARG_STOP);
15606
15607 case NEON_SCALARMAC:
15608 return arm_expand_neon_args (target, icode, 1, exp,
15609 NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG,
15610 NEON_ARG_CONSTANT, NEON_ARG_STOP);
15611
15612 case NEON_SELECT:
15613 case NEON_VTBX:
15614 return arm_expand_neon_args (target, icode, 1, exp,
15615 NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG,
15616 NEON_ARG_STOP);
15617
15618 case NEON_LOAD1:
15619 case NEON_LOADSTRUCT:
15620 return arm_expand_neon_args (target, icode, 1, exp,
15621 NEON_ARG_COPY_TO_REG, NEON_ARG_STOP);
15622
15623 case NEON_LOAD1LANE:
15624 case NEON_LOADSTRUCTLANE:
15625 return arm_expand_neon_args (target, icode, 1, exp,
15626 NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT,
15627 NEON_ARG_STOP);
15628
15629 case NEON_STORE1:
15630 case NEON_STORESTRUCT:
15631 return arm_expand_neon_args (target, icode, 0, exp,
15632 NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_STOP);
15633
15634 case NEON_STORE1LANE:
15635 case NEON_STORESTRUCTLANE:
15636 return arm_expand_neon_args (target, icode, 0, exp,
15637 NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT,
15638 NEON_ARG_STOP);
15639 }
15640
15641 gcc_unreachable ();
15642}
15643
15644/* Emit code to reinterpret one Neon type as another, without altering bits. */
15645void
15646neon_reinterpret (rtx dest, rtx src)
15647{
15648 emit_move_insn (dest, gen_lowpart (GET_MODE (dest), src));
15649}
15650
15651/* Emit code to place a Neon pair result in memory locations (with equal
15652 registers). */
15653void
15654neon_emit_pair_result_insn (enum machine_mode mode,
15655 rtx (*intfn) (rtx, rtx, rtx, rtx), rtx destaddr,
15656 rtx op1, rtx op2)
15657{
15658 rtx mem = gen_rtx_MEM (mode, destaddr);
15659 rtx tmp1 = gen_reg_rtx (mode);
15660 rtx tmp2 = gen_reg_rtx (mode);
15661
15662 emit_insn (intfn (tmp1, op1, tmp2, op2));
15663
15664 emit_move_insn (mem, tmp1);
15665 mem = adjust_address (mem, mode, GET_MODE_SIZE (mode));
15666 emit_move_insn (mem, tmp2);
15667}
15668
15669/* Set up operands for a register copy from src to dest, taking care not to
15670 clobber registers in the process.
15671 FIXME: This has rather high polynomial complexity (O(n^3)?) but shouldn't
15672 be called with a large N, so that should be OK. */
15673
15674void
15675neon_disambiguate_copy (rtx *operands, rtx *dest, rtx *src, unsigned int count)
15676{
15677 unsigned int copied = 0, opctr = 0;
15678 unsigned int done = (1 << count) - 1;
15679 unsigned int i, j;
15680
15681 while (copied != done)
15682 {
15683 for (i = 0; i < count; i++)
15684 {
15685 int good = 1;
15686
15687 for (j = 0; good && j < count; j++)
15688 if (i != j && (copied & (1 << j)) == 0
15689 && reg_overlap_mentioned_p (src[j], dest[i]))
15690 good = 0;
15691
15692 if (good)
15693 {
15694 operands[opctr++] = dest[i];
15695 operands[opctr++] = src[i];
15696 copied |= 1 << i;
15697 }
15698 }
15699 }
15700
15701 gcc_assert (opctr == count * 2);
15702}
15703
755eb2b4 15704/* Expand an expression EXP that calls a built-in function,
15705 with result going to TARGET if that's convenient
15706 (and in mode MODE if that's convenient).
15707 SUBTARGET may be used as the target for computing one of EXP's operands.
15708 IGNORE is nonzero if the value is to be ignored. */
15709
15710static rtx
15711arm_expand_builtin (tree exp,
15712 rtx target,
15713 rtx subtarget ATTRIBUTE_UNUSED,
15714 enum machine_mode mode ATTRIBUTE_UNUSED,
15715 int ignore ATTRIBUTE_UNUSED)
15716{
15717 const struct builtin_description * d;
15718 enum insn_code icode;
c2f47e15 15719 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
755eb2b4 15720 tree arg0;
15721 tree arg1;
15722 tree arg2;
15723 rtx op0;
15724 rtx op1;
15725 rtx op2;
15726 rtx pat;
15727 int fcode = DECL_FUNCTION_CODE (fndecl);
15728 size_t i;
15729 enum machine_mode tmode;
15730 enum machine_mode mode0;
15731 enum machine_mode mode1;
15732 enum machine_mode mode2;
15733
d98a3884 15734 if (fcode >= ARM_BUILTIN_NEON_BASE)
15735 return arm_expand_neon_builtin (fcode, exp, target);
15736
755eb2b4 15737 switch (fcode)
15738 {
15739 case ARM_BUILTIN_TEXTRMSB:
15740 case ARM_BUILTIN_TEXTRMUB:
15741 case ARM_BUILTIN_TEXTRMSH:
15742 case ARM_BUILTIN_TEXTRMUH:
15743 case ARM_BUILTIN_TEXTRMSW:
15744 case ARM_BUILTIN_TEXTRMUW:
15745 icode = (fcode == ARM_BUILTIN_TEXTRMSB ? CODE_FOR_iwmmxt_textrmsb
15746 : fcode == ARM_BUILTIN_TEXTRMUB ? CODE_FOR_iwmmxt_textrmub
15747 : fcode == ARM_BUILTIN_TEXTRMSH ? CODE_FOR_iwmmxt_textrmsh
15748 : fcode == ARM_BUILTIN_TEXTRMUH ? CODE_FOR_iwmmxt_textrmuh
15749 : CODE_FOR_iwmmxt_textrmw);
15750
c2f47e15 15751 arg0 = CALL_EXPR_ARG (exp, 0);
15752 arg1 = CALL_EXPR_ARG (exp, 1);
8ec3c5c2 15753 op0 = expand_normal (arg0);
15754 op1 = expand_normal (arg1);
755eb2b4 15755 tmode = insn_data[icode].operand[0].mode;
15756 mode0 = insn_data[icode].operand[1].mode;
15757 mode1 = insn_data[icode].operand[2].mode;
15758
15759 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
15760 op0 = copy_to_mode_reg (mode0, op0);
15761 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
15762 {
15763 /* @@@ better error message */
15764 error ("selector must be an immediate");
15765 return gen_reg_rtx (tmode);
15766 }
15767 if (target == 0
15768 || GET_MODE (target) != tmode
15769 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
15770 target = gen_reg_rtx (tmode);
15771 pat = GEN_FCN (icode) (target, op0, op1);
15772 if (! pat)
15773 return 0;
15774 emit_insn (pat);
15775 return target;
15776
15777 case ARM_BUILTIN_TINSRB:
15778 case ARM_BUILTIN_TINSRH:
15779 case ARM_BUILTIN_TINSRW:
15780 icode = (fcode == ARM_BUILTIN_TINSRB ? CODE_FOR_iwmmxt_tinsrb
15781 : fcode == ARM_BUILTIN_TINSRH ? CODE_FOR_iwmmxt_tinsrh
15782 : CODE_FOR_iwmmxt_tinsrw);
c2f47e15 15783 arg0 = CALL_EXPR_ARG (exp, 0);
15784 arg1 = CALL_EXPR_ARG (exp, 1);
15785 arg2 = CALL_EXPR_ARG (exp, 2);
8ec3c5c2 15786 op0 = expand_normal (arg0);
15787 op1 = expand_normal (arg1);
15788 op2 = expand_normal (arg2);
755eb2b4 15789 tmode = insn_data[icode].operand[0].mode;
15790 mode0 = insn_data[icode].operand[1].mode;
15791 mode1 = insn_data[icode].operand[2].mode;
15792 mode2 = insn_data[icode].operand[3].mode;
15793
15794 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
15795 op0 = copy_to_mode_reg (mode0, op0);
15796 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
15797 op1 = copy_to_mode_reg (mode1, op1);
15798 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
15799 {
15800 /* @@@ better error message */
15801 error ("selector must be an immediate");
15802 return const0_rtx;
15803 }
15804 if (target == 0
15805 || GET_MODE (target) != tmode
15806 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
15807 target = gen_reg_rtx (tmode);
15808 pat = GEN_FCN (icode) (target, op0, op1, op2);
15809 if (! pat)
15810 return 0;
15811 emit_insn (pat);
15812 return target;
15813
15814 case ARM_BUILTIN_SETWCX:
c2f47e15 15815 arg0 = CALL_EXPR_ARG (exp, 0);
15816 arg1 = CALL_EXPR_ARG (exp, 1);
8ec3c5c2 15817 op0 = force_reg (SImode, expand_normal (arg0));
15818 op1 = expand_normal (arg1);
08476a09 15819 emit_insn (gen_iwmmxt_tmcr (op1, op0));
755eb2b4 15820 return 0;
15821
15822 case ARM_BUILTIN_GETWCX:
c2f47e15 15823 arg0 = CALL_EXPR_ARG (exp, 0);
8ec3c5c2 15824 op0 = expand_normal (arg0);
755eb2b4 15825 target = gen_reg_rtx (SImode);
15826 emit_insn (gen_iwmmxt_tmrc (target, op0));
15827 return target;
15828
15829 case ARM_BUILTIN_WSHUFH:
15830 icode = CODE_FOR_iwmmxt_wshufh;
c2f47e15 15831 arg0 = CALL_EXPR_ARG (exp, 0);
15832 arg1 = CALL_EXPR_ARG (exp, 1);
8ec3c5c2 15833 op0 = expand_normal (arg0);
15834 op1 = expand_normal (arg1);
755eb2b4 15835 tmode = insn_data[icode].operand[0].mode;
15836 mode1 = insn_data[icode].operand[1].mode;
15837 mode2 = insn_data[icode].operand[2].mode;
15838
15839 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
15840 op0 = copy_to_mode_reg (mode1, op0);
15841 if (! (*insn_data[icode].operand[2].predicate) (op1, mode2))
15842 {
15843 /* @@@ better error message */
15844 error ("mask must be an immediate");
15845 return const0_rtx;
15846 }
15847 if (target == 0
15848 || GET_MODE (target) != tmode
15849 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
15850 target = gen_reg_rtx (tmode);
15851 pat = GEN_FCN (icode) (target, op0, op1);
15852 if (! pat)
15853 return 0;
15854 emit_insn (pat);
15855 return target;
15856
15857 case ARM_BUILTIN_WSADB:
c2f47e15 15858 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadb, exp, target);
755eb2b4 15859 case ARM_BUILTIN_WSADH:
c2f47e15 15860 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadh, exp, target);
755eb2b4 15861 case ARM_BUILTIN_WSADBZ:
c2f47e15 15862 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadbz, exp, target);
755eb2b4 15863 case ARM_BUILTIN_WSADHZ:
c2f47e15 15864 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadhz, exp, target);
755eb2b4 15865
15866 /* Several three-argument builtins. */
15867 case ARM_BUILTIN_WMACS:
15868 case ARM_BUILTIN_WMACU:
15869 case ARM_BUILTIN_WALIGN:
15870 case ARM_BUILTIN_TMIA:
15871 case ARM_BUILTIN_TMIAPH:
15872 case ARM_BUILTIN_TMIATT:
15873 case ARM_BUILTIN_TMIATB:
15874 case ARM_BUILTIN_TMIABT:
15875 case ARM_BUILTIN_TMIABB:
15876 icode = (fcode == ARM_BUILTIN_WMACS ? CODE_FOR_iwmmxt_wmacs
15877 : fcode == ARM_BUILTIN_WMACU ? CODE_FOR_iwmmxt_wmacu
15878 : fcode == ARM_BUILTIN_TMIA ? CODE_FOR_iwmmxt_tmia
15879 : fcode == ARM_BUILTIN_TMIAPH ? CODE_FOR_iwmmxt_tmiaph
15880 : fcode == ARM_BUILTIN_TMIABB ? CODE_FOR_iwmmxt_tmiabb
15881 : fcode == ARM_BUILTIN_TMIABT ? CODE_FOR_iwmmxt_tmiabt
15882 : fcode == ARM_BUILTIN_TMIATB ? CODE_FOR_iwmmxt_tmiatb
15883 : fcode == ARM_BUILTIN_TMIATT ? CODE_FOR_iwmmxt_tmiatt
15884 : CODE_FOR_iwmmxt_walign);
c2f47e15 15885 arg0 = CALL_EXPR_ARG (exp, 0);
15886 arg1 = CALL_EXPR_ARG (exp, 1);
15887 arg2 = CALL_EXPR_ARG (exp, 2);
8ec3c5c2 15888 op0 = expand_normal (arg0);
15889 op1 = expand_normal (arg1);
15890 op2 = expand_normal (arg2);
755eb2b4 15891 tmode = insn_data[icode].operand[0].mode;
15892 mode0 = insn_data[icode].operand[1].mode;
15893 mode1 = insn_data[icode].operand[2].mode;
15894 mode2 = insn_data[icode].operand[3].mode;
15895
15896 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
15897 op0 = copy_to_mode_reg (mode0, op0);
15898 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
15899 op1 = copy_to_mode_reg (mode1, op1);
15900 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
15901 op2 = copy_to_mode_reg (mode2, op2);
15902 if (target == 0
15903 || GET_MODE (target) != tmode
15904 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
15905 target = gen_reg_rtx (tmode);
15906 pat = GEN_FCN (icode) (target, op0, op1, op2);
15907 if (! pat)
15908 return 0;
15909 emit_insn (pat);
15910 return target;
9e7454d0 15911
755eb2b4 15912 case ARM_BUILTIN_WZERO:
15913 target = gen_reg_rtx (DImode);
15914 emit_insn (gen_iwmmxt_clrdi (target));
15915 return target;
15916
f655717d 15917 case ARM_BUILTIN_THREAD_POINTER:
15918 return arm_load_tp (target);
15919
755eb2b4 15920 default:
15921 break;
15922 }
15923
3b9d9482 15924 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
755eb2b4 15925 if (d->code == (const enum arm_builtins) fcode)
c2f47e15 15926 return arm_expand_binop_builtin (d->icode, exp, target);
755eb2b4 15927
3b9d9482 15928 for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
755eb2b4 15929 if (d->code == (const enum arm_builtins) fcode)
c2f47e15 15930 return arm_expand_unop_builtin (d->icode, exp, target, 0);
755eb2b4 15931
15932 /* @@@ Should really do something sensible here. */
15933 return NULL_RTX;
15934}
15935\f
a12be13c 15936/* Return the number (counting from 0) of
15937 the least significant set bit in MASK. */
15938
ebd88a36 15939inline static int
53f179c0 15940number_of_first_bit_set (unsigned mask)
cffb2a26 15941{
15942 int bit;
15943
15944 for (bit = 0;
15945 (mask & (1 << bit)) == 0;
215b30b3 15946 ++bit)
cffb2a26 15947 continue;
15948
15949 return bit;
15950}
15951
53f179c0 15952/* Emit code to push or pop registers to or from the stack. F is the
15953 assembly file. MASK is the registers to push or pop. PUSH is
15954 nonzero if we should push, and zero if we should pop. For debugging
15955 output, if pushing, adjust CFA_OFFSET by the amount of space added
15956 to the stack. REAL_REGS should have the same number of bits set as
15957 MASK, and will be used instead (in the same order) to describe which
15958 registers were saved - this is used to mark the save slots when we
15959 push high registers after moving them to low registers. */
15960static void
15961thumb_pushpop (FILE *f, unsigned long mask, int push, int *cfa_offset,
15962 unsigned long real_regs)
15963{
15964 int regno;
15965 int lo_mask = mask & 0xFF;
15966 int pushed_words = 0;
15967
ed29c566 15968 gcc_assert (mask);
53f179c0 15969
15970 if (lo_mask == 0 && !push && (mask & (1 << PC_REGNUM)))
15971 {
15972 /* Special case. Do not generate a POP PC statement here, do it in
15973 thumb_exit() */
15974 thumb_exit (f, -1);
15975 return;
15976 }
15977
1774763d 15978 if (ARM_EABI_UNWIND_TABLES && push)
15979 {
15980 fprintf (f, "\t.save\t{");
15981 for (regno = 0; regno < 15; regno++)
15982 {
15983 if (real_regs & (1 << regno))
15984 {
15985 if (real_regs & ((1 << regno) -1))
15986 fprintf (f, ", ");
15987 asm_fprintf (f, "%r", regno);
15988 }
15989 }
15990 fprintf (f, "}\n");
15991 }
15992
53f179c0 15993 fprintf (f, "\t%s\t{", push ? "push" : "pop");
15994
15995 /* Look at the low registers first. */
15996 for (regno = 0; regno <= LAST_LO_REGNUM; regno++, lo_mask >>= 1)
15997 {
15998 if (lo_mask & 1)
15999 {
16000 asm_fprintf (f, "%r", regno);
16001
16002 if ((lo_mask & ~1) != 0)
16003 fprintf (f, ", ");
16004
16005 pushed_words++;
16006 }
16007 }
16008
16009 if (push && (mask & (1 << LR_REGNUM)))
16010 {
16011 /* Catch pushing the LR. */
16012 if (mask & 0xFF)
16013 fprintf (f, ", ");
16014
16015 asm_fprintf (f, "%r", LR_REGNUM);
16016
16017 pushed_words++;
16018 }
16019 else if (!push && (mask & (1 << PC_REGNUM)))
16020 {
16021 /* Catch popping the PC. */
16022 if (TARGET_INTERWORK || TARGET_BACKTRACE
16023 || current_function_calls_eh_return)
16024 {
16025 /* The PC is never poped directly, instead
16026 it is popped into r3 and then BX is used. */
16027 fprintf (f, "}\n");
16028
16029 thumb_exit (f, -1);
16030
16031 return;
16032 }
16033 else
16034 {
16035 if (mask & 0xFF)
16036 fprintf (f, ", ");
16037
16038 asm_fprintf (f, "%r", PC_REGNUM);
16039 }
16040 }
16041
16042 fprintf (f, "}\n");
16043
16044 if (push && pushed_words && dwarf2out_do_frame ())
16045 {
16046 char *l = dwarf2out_cfi_label ();
16047 int pushed_mask = real_regs;
16048
16049 *cfa_offset += pushed_words * 4;
16050 dwarf2out_def_cfa (l, SP_REGNUM, *cfa_offset);
16051
16052 pushed_words = 0;
16053 pushed_mask = real_regs;
16054 for (regno = 0; regno <= 14; regno++, pushed_mask >>= 1)
16055 {
16056 if (pushed_mask & 1)
16057 dwarf2out_reg_save (l, regno, 4 * pushed_words++ - *cfa_offset);
16058 }
16059 }
16060}
16061
cffb2a26 16062/* Generate code to return from a thumb function.
16063 If 'reg_containing_return_addr' is -1, then the return address is
16064 actually on the stack, at the stack pointer. */
16065static void
4c44712e 16066thumb_exit (FILE *f, int reg_containing_return_addr)
cffb2a26 16067{
16068 unsigned regs_available_for_popping;
16069 unsigned regs_to_pop;
16070 int pops_needed;
16071 unsigned available;
16072 unsigned required;
16073 int mode;
16074 int size;
16075 int restore_a4 = FALSE;
16076
16077 /* Compute the registers we need to pop. */
16078 regs_to_pop = 0;
16079 pops_needed = 0;
16080
4c44712e 16081 if (reg_containing_return_addr == -1)
cffb2a26 16082 {
cffb2a26 16083 regs_to_pop |= 1 << LR_REGNUM;
215b30b3 16084 ++pops_needed;
cffb2a26 16085 }
16086
16087 if (TARGET_BACKTRACE)
16088 {
16089 /* Restore the (ARM) frame pointer and stack pointer. */
16090 regs_to_pop |= (1 << ARM_HARD_FRAME_POINTER_REGNUM) | (1 << SP_REGNUM);
16091 pops_needed += 2;
16092 }
16093
16094 /* If there is nothing to pop then just emit the BX instruction and
16095 return. */
16096 if (pops_needed == 0)
16097 {
4c44712e 16098 if (current_function_calls_eh_return)
16099 asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, ARM_EH_STACKADJ_REGNUM);
cffb2a26 16100
16101 asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
16102 return;
16103 }
16104 /* Otherwise if we are not supporting interworking and we have not created
16105 a backtrace structure and the function was not entered in ARM mode then
16106 just pop the return address straight into the PC. */
215b30b3 16107 else if (!TARGET_INTERWORK
16108 && !TARGET_BACKTRACE
4c44712e 16109 && !is_called_in_ARM_mode (current_function_decl)
16110 && !current_function_calls_eh_return)
cffb2a26 16111 {
4c44712e 16112 asm_fprintf (f, "\tpop\t{%r}\n", PC_REGNUM);
cffb2a26 16113 return;
16114 }
16115
16116 /* Find out how many of the (return) argument registers we can corrupt. */
16117 regs_available_for_popping = 0;
16118
16119 /* If returning via __builtin_eh_return, the bottom three registers
16120 all contain information needed for the return. */
4c44712e 16121 if (current_function_calls_eh_return)
cffb2a26 16122 size = 12;
16123 else
16124 {
cffb2a26 16125 /* If we can deduce the registers used from the function's
16126 return value. This is more reliable that examining
3072d30e 16127 df_regs_ever_live_p () because that will be set if the register is
cffb2a26 16128 ever used in the function, not just if the register is used
16129 to hold a return value. */
16130
16131 if (current_function_return_rtx != 0)
16132 mode = GET_MODE (current_function_return_rtx);
16133 else
cffb2a26 16134 mode = DECL_MODE (DECL_RESULT (current_function_decl));
16135
16136 size = GET_MODE_SIZE (mode);
16137
16138 if (size == 0)
16139 {
16140 /* In a void function we can use any argument register.
16141 In a function that returns a structure on the stack
16142 we can use the second and third argument registers. */
16143 if (mode == VOIDmode)
16144 regs_available_for_popping =
16145 (1 << ARG_REGISTER (1))
16146 | (1 << ARG_REGISTER (2))
16147 | (1 << ARG_REGISTER (3));
16148 else
16149 regs_available_for_popping =
16150 (1 << ARG_REGISTER (2))
16151 | (1 << ARG_REGISTER (3));
16152 }
16153 else if (size <= 4)
16154 regs_available_for_popping =
16155 (1 << ARG_REGISTER (2))
16156 | (1 << ARG_REGISTER (3));
16157 else if (size <= 8)
16158 regs_available_for_popping =
16159 (1 << ARG_REGISTER (3));
16160 }
16161
16162 /* Match registers to be popped with registers into which we pop them. */
16163 for (available = regs_available_for_popping,
16164 required = regs_to_pop;
16165 required != 0 && available != 0;
16166 available &= ~(available & - available),
16167 required &= ~(required & - required))
16168 -- pops_needed;
16169
16170 /* If we have any popping registers left over, remove them. */
16171 if (available > 0)
215b30b3 16172 regs_available_for_popping &= ~available;
9e7454d0 16173
cffb2a26 16174 /* Otherwise if we need another popping register we can use
16175 the fourth argument register. */
16176 else if (pops_needed)
16177 {
16178 /* If we have not found any free argument registers and
16179 reg a4 contains the return address, we must move it. */
16180 if (regs_available_for_popping == 0
16181 && reg_containing_return_addr == LAST_ARG_REGNUM)
16182 {
16183 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, LAST_ARG_REGNUM);
16184 reg_containing_return_addr = LR_REGNUM;
16185 }
16186 else if (size > 12)
16187 {
16188 /* Register a4 is being used to hold part of the return value,
16189 but we have dire need of a free, low register. */
16190 restore_a4 = TRUE;
9e7454d0 16191
cffb2a26 16192 asm_fprintf (f, "\tmov\t%r, %r\n",IP_REGNUM, LAST_ARG_REGNUM);
16193 }
9e7454d0 16194
cffb2a26 16195 if (reg_containing_return_addr != LAST_ARG_REGNUM)
16196 {
16197 /* The fourth argument register is available. */
16198 regs_available_for_popping |= 1 << LAST_ARG_REGNUM;
9e7454d0 16199
215b30b3 16200 --pops_needed;
cffb2a26 16201 }
16202 }
16203
16204 /* Pop as many registers as we can. */
37826745 16205 thumb_pushpop (f, regs_available_for_popping, FALSE, NULL,
16206 regs_available_for_popping);
cffb2a26 16207
16208 /* Process the registers we popped. */
16209 if (reg_containing_return_addr == -1)
16210 {
16211 /* The return address was popped into the lowest numbered register. */
215b30b3 16212 regs_to_pop &= ~(1 << LR_REGNUM);
9e7454d0 16213
cffb2a26 16214 reg_containing_return_addr =
16215 number_of_first_bit_set (regs_available_for_popping);
16216
16217 /* Remove this register for the mask of available registers, so that
b89db9a7 16218 the return address will not be corrupted by further pops. */
215b30b3 16219 regs_available_for_popping &= ~(1 << reg_containing_return_addr);
cffb2a26 16220 }
16221
16222 /* If we popped other registers then handle them here. */
16223 if (regs_available_for_popping)
16224 {
16225 int frame_pointer;
9e7454d0 16226
cffb2a26 16227 /* Work out which register currently contains the frame pointer. */
16228 frame_pointer = number_of_first_bit_set (regs_available_for_popping);
16229
16230 /* Move it into the correct place. */
16231 asm_fprintf (f, "\tmov\t%r, %r\n",
16232 ARM_HARD_FRAME_POINTER_REGNUM, frame_pointer);
16233
16234 /* (Temporarily) remove it from the mask of popped registers. */
215b30b3 16235 regs_available_for_popping &= ~(1 << frame_pointer);
16236 regs_to_pop &= ~(1 << ARM_HARD_FRAME_POINTER_REGNUM);
9e7454d0 16237
cffb2a26 16238 if (regs_available_for_popping)
16239 {
16240 int stack_pointer;
9e7454d0 16241
cffb2a26 16242 /* We popped the stack pointer as well,
16243 find the register that contains it. */
16244 stack_pointer = number_of_first_bit_set (regs_available_for_popping);
16245
16246 /* Move it into the stack register. */
16247 asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, stack_pointer);
9e7454d0 16248
cffb2a26 16249 /* At this point we have popped all necessary registers, so
16250 do not worry about restoring regs_available_for_popping
16251 to its correct value:
16252
16253 assert (pops_needed == 0)
16254 assert (regs_available_for_popping == (1 << frame_pointer))
16255 assert (regs_to_pop == (1 << STACK_POINTER)) */
16256 }
16257 else
16258 {
16259 /* Since we have just move the popped value into the frame
16260 pointer, the popping register is available for reuse, and
16261 we know that we still have the stack pointer left to pop. */
16262 regs_available_for_popping |= (1 << frame_pointer);
16263 }
16264 }
9e7454d0 16265
cffb2a26 16266 /* If we still have registers left on the stack, but we no longer have
16267 any registers into which we can pop them, then we must move the return
16268 address into the link register and make available the register that
16269 contained it. */
16270 if (regs_available_for_popping == 0 && pops_needed > 0)
16271 {
16272 regs_available_for_popping |= 1 << reg_containing_return_addr;
9e7454d0 16273
cffb2a26 16274 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM,
16275 reg_containing_return_addr);
9e7454d0 16276
cffb2a26 16277 reg_containing_return_addr = LR_REGNUM;
16278 }
16279
16280 /* If we have registers left on the stack then pop some more.
16281 We know that at most we will want to pop FP and SP. */
16282 if (pops_needed > 0)
16283 {
16284 int popped_into;
16285 int move_to;
9e7454d0 16286
37826745 16287 thumb_pushpop (f, regs_available_for_popping, FALSE, NULL,
16288 regs_available_for_popping);
cffb2a26 16289
16290 /* We have popped either FP or SP.
16291 Move whichever one it is into the correct register. */
16292 popped_into = number_of_first_bit_set (regs_available_for_popping);
16293 move_to = number_of_first_bit_set (regs_to_pop);
16294
16295 asm_fprintf (f, "\tmov\t%r, %r\n", move_to, popped_into);
16296
215b30b3 16297 regs_to_pop &= ~(1 << move_to);
cffb2a26 16298
215b30b3 16299 --pops_needed;
cffb2a26 16300 }
9e7454d0 16301
cffb2a26 16302 /* If we still have not popped everything then we must have only
16303 had one register available to us and we are now popping the SP. */
16304 if (pops_needed > 0)
16305 {
16306 int popped_into;
9e7454d0 16307
37826745 16308 thumb_pushpop (f, regs_available_for_popping, FALSE, NULL,
16309 regs_available_for_popping);
cffb2a26 16310
16311 popped_into = number_of_first_bit_set (regs_available_for_popping);
16312
16313 asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, popped_into);
16314 /*
16315 assert (regs_to_pop == (1 << STACK_POINTER))
16316 assert (pops_needed == 1)
16317 */
16318 }
16319
16320 /* If necessary restore the a4 register. */
16321 if (restore_a4)
16322 {
16323 if (reg_containing_return_addr != LR_REGNUM)
16324 {
16325 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, LAST_ARG_REGNUM);
16326 reg_containing_return_addr = LR_REGNUM;
16327 }
9e7454d0 16328
cffb2a26 16329 asm_fprintf (f, "\tmov\t%r, %r\n", LAST_ARG_REGNUM, IP_REGNUM);
16330 }
16331
4c44712e 16332 if (current_function_calls_eh_return)
16333 asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, ARM_EH_STACKADJ_REGNUM);
cffb2a26 16334
16335 /* Return to caller. */
16336 asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
16337}
16338
cffb2a26 16339\f
16340void
25f905c2 16341thumb1_final_prescan_insn (rtx insn)
cffb2a26 16342{
cffb2a26 16343 if (flag_print_asm_name)
47fc0706 16344 asm_fprintf (asm_out_file, "%@ 0x%04x\n",
16345 INSN_ADDRESSES (INSN_UID (insn)));
cffb2a26 16346}
16347
16348int
ebd88a36 16349thumb_shiftable_const (unsigned HOST_WIDE_INT val)
cffb2a26 16350{
16351 unsigned HOST_WIDE_INT mask = 0xff;
16352 int i;
16353
16354 if (val == 0) /* XXX */
16355 return 0;
9e7454d0 16356
cffb2a26 16357 for (i = 0; i < 25; i++)
16358 if ((val & (mask << i)) == val)
16359 return 1;
16360
16361 return 0;
16362}
16363
e3e08e7f 16364/* Returns nonzero if the current function contains,
cffb2a26 16365 or might contain a far jump. */
f9273c43 16366static int
16367thumb_far_jump_used_p (void)
cffb2a26 16368{
16369 rtx insn;
16370
16371 /* This test is only important for leaf functions. */
215b30b3 16372 /* assert (!leaf_function_p ()); */
9e7454d0 16373
cffb2a26 16374 /* If we have already decided that far jumps may be used,
16375 do not bother checking again, and always return true even if
16376 it turns out that they are not being used. Once we have made
16377 the decision that far jumps are present (and that hence the link
16378 register will be pushed onto the stack) we cannot go back on it. */
16379 if (cfun->machine->far_jump_used)
16380 return 1;
16381
16382 /* If this function is not being called from the prologue/epilogue
16383 generation code then it must be being called from the
16384 INITIAL_ELIMINATION_OFFSET macro. */
f9273c43 16385 if (!(ARM_DOUBLEWORD_ALIGN || reload_completed))
cffb2a26 16386 {
16387 /* In this case we know that we are being asked about the elimination
16388 of the arg pointer register. If that register is not being used,
16389 then there are no arguments on the stack, and we do not have to
16390 worry that a far jump might force the prologue to push the link
16391 register, changing the stack offsets. In this case we can just
16392 return false, since the presence of far jumps in the function will
16393 not affect stack offsets.
16394
16395 If the arg pointer is live (or if it was live, but has now been
16396 eliminated and so set to dead) then we do have to test to see if
16397 the function might contain a far jump. This test can lead to some
16398 false negatives, since before reload is completed, then length of
16399 branch instructions is not known, so gcc defaults to returning their
16400 longest length, which in turn sets the far jump attribute to true.
16401
16402 A false negative will not result in bad code being generated, but it
16403 will result in a needless push and pop of the link register. We
f9273c43 16404 hope that this does not occur too often.
16405
16406 If we need doubleword stack alignment this could affect the other
16407 elimination offsets so we can't risk getting it wrong. */
3072d30e 16408 if (df_regs_ever_live_p (ARG_POINTER_REGNUM))
cffb2a26 16409 cfun->machine->arg_pointer_live = 1;
215b30b3 16410 else if (!cfun->machine->arg_pointer_live)
cffb2a26 16411 return 0;
16412 }
16413
16414 /* Check to see if the function contains a branch
16415 insn with the far jump attribute set. */
16416 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
16417 {
16418 if (GET_CODE (insn) == JUMP_INSN
16419 /* Ignore tablejump patterns. */
16420 && GET_CODE (PATTERN (insn)) != ADDR_VEC
16421 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
16422 && get_attr_far_jump (insn) == FAR_JUMP_YES
16423 )
16424 {
8d232dc7 16425 /* Record the fact that we have decided that
cffb2a26 16426 the function does use far jumps. */
16427 cfun->machine->far_jump_used = 1;
16428 return 1;
16429 }
16430 }
9e7454d0 16431
cffb2a26 16432 return 0;
16433}
16434
e3e08e7f 16435/* Return nonzero if FUNC must be entered in ARM mode. */
cffb2a26 16436int
ebd88a36 16437is_called_in_ARM_mode (tree func)
cffb2a26 16438{
ed29c566 16439 gcc_assert (TREE_CODE (func) == FUNCTION_DECL);
cffb2a26 16440
fccee353 16441 /* Ignore the problem about functions whose address is taken. */
cffb2a26 16442 if (TARGET_CALLEE_INTERWORKING && TREE_PUBLIC (func))
16443 return TRUE;
16444
9e7454d0 16445#ifdef ARM_PE
e3c541f0 16446 return lookup_attribute ("interfacearm", DECL_ATTRIBUTES (func)) != NULL_TREE;
cffb2a26 16447#else
16448 return FALSE;
16449#endif
16450}
16451
674a8f0b 16452/* The bits which aren't usefully expanded as rtl. */
0bd59681 16453const char *
ebd88a36 16454thumb_unexpanded_epilogue (void)
cffb2a26 16455{
16456 int regno;
53f179c0 16457 unsigned long live_regs_mask = 0;
cffb2a26 16458 int high_regs_pushed = 0;
cffb2a26 16459 int had_to_push_lr;
237533cc 16460 int size;
cffb2a26 16461
16462 if (return_used_this_function)
16463 return "";
16464
4d0f24bc 16465 if (IS_NAKED (arm_current_func_type ()))
16466 return "";
16467
25f905c2 16468 live_regs_mask = thumb1_compute_save_reg_mask ();
237533cc 16469 high_regs_pushed = bit_count (live_regs_mask & 0x0f00);
16470
16471 /* If we can deduce the registers used from the function's return value.
3072d30e 16472 This is more reliable that examining df_regs_ever_live_p () because that
237533cc 16473 will be set if the register is ever used in the function, not just if
16474 the register is used to hold a return value. */
0858d94e 16475 size = arm_size_return_regs ();
cffb2a26 16476
16477 /* The prolog may have pushed some high registers to use as
a361b456 16478 work registers. e.g. the testsuite file:
cffb2a26 16479 gcc/testsuite/gcc/gcc.c-torture/execute/complex-2.c
16480 compiles to produce:
16481 push {r4, r5, r6, r7, lr}
16482 mov r7, r9
16483 mov r6, r8
16484 push {r6, r7}
16485 as part of the prolog. We have to undo that pushing here. */
9e7454d0 16486
cffb2a26 16487 if (high_regs_pushed)
16488 {
53f179c0 16489 unsigned long mask = live_regs_mask & 0xff;
cffb2a26 16490 int next_hi_reg;
cffb2a26 16491
237533cc 16492 /* The available low registers depend on the size of the value we are
16493 returning. */
16494 if (size <= 12)
cffb2a26 16495 mask |= 1 << 3;
237533cc 16496 if (size <= 8)
16497 mask |= 1 << 2;
cffb2a26 16498
16499 if (mask == 0)
16500 /* Oh dear! We have no low registers into which we can pop
16501 high registers! */
f060a027 16502 internal_error
16503 ("no low registers available for popping high registers");
9e7454d0 16504
cffb2a26 16505 for (next_hi_reg = 8; next_hi_reg < 13; next_hi_reg++)
237533cc 16506 if (live_regs_mask & (1 << next_hi_reg))
cffb2a26 16507 break;
16508
16509 while (high_regs_pushed)
16510 {
16511 /* Find lo register(s) into which the high register(s) can
16512 be popped. */
16513 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
16514 {
16515 if (mask & (1 << regno))
16516 high_regs_pushed--;
16517 if (high_regs_pushed == 0)
16518 break;
16519 }
16520
16521 mask &= (2 << regno) - 1; /* A noop if regno == 8 */
16522
674a8f0b 16523 /* Pop the values into the low register(s). */
37826745 16524 thumb_pushpop (asm_out_file, mask, 0, NULL, mask);
cffb2a26 16525
16526 /* Move the value(s) into the high registers. */
16527 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
16528 {
16529 if (mask & (1 << regno))
16530 {
16531 asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", next_hi_reg,
16532 regno);
9e7454d0 16533
cffb2a26 16534 for (next_hi_reg++; next_hi_reg < 13; next_hi_reg++)
237533cc 16535 if (live_regs_mask & (1 << next_hi_reg))
cffb2a26 16536 break;
16537 }
16538 }
16539 }
237533cc 16540 live_regs_mask &= ~0x0f00;
cffb2a26 16541 }
16542
237533cc 16543 had_to_push_lr = (live_regs_mask & (1 << LR_REGNUM)) != 0;
16544 live_regs_mask &= 0xff;
16545
cffb2a26 16546 if (current_function_pretend_args_size == 0 || TARGET_BACKTRACE)
16547 {
9e7454d0 16548 /* Pop the return address into the PC. */
237533cc 16549 if (had_to_push_lr)
cffb2a26 16550 live_regs_mask |= 1 << PC_REGNUM;
16551
16552 /* Either no argument registers were pushed or a backtrace
16553 structure was created which includes an adjusted stack
16554 pointer, so just pop everything. */
16555 if (live_regs_mask)
37826745 16556 thumb_pushpop (asm_out_file, live_regs_mask, FALSE, NULL,
16557 live_regs_mask);
237533cc 16558
cffb2a26 16559 /* We have either just popped the return address into the
237533cc 16560 PC or it is was kept in LR for the entire function. */
16561 if (!had_to_push_lr)
16562 thumb_exit (asm_out_file, LR_REGNUM);
cffb2a26 16563 }
16564 else
16565 {
16566 /* Pop everything but the return address. */
cffb2a26 16567 if (live_regs_mask)
37826745 16568 thumb_pushpop (asm_out_file, live_regs_mask, FALSE, NULL,
16569 live_regs_mask);
cffb2a26 16570
16571 if (had_to_push_lr)
237533cc 16572 {
16573 if (size > 12)
16574 {
16575 /* We have no free low regs, so save one. */
16576 asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", IP_REGNUM,
16577 LAST_ARG_REGNUM);
16578 }
16579
16580 /* Get the return address into a temporary register. */
16581 thumb_pushpop (asm_out_file, 1 << LAST_ARG_REGNUM, 0, NULL,
16582 1 << LAST_ARG_REGNUM);
16583
16584 if (size > 12)
16585 {
16586 /* Move the return address to lr. */
16587 asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", LR_REGNUM,
16588 LAST_ARG_REGNUM);
16589 /* Restore the low register. */
16590 asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", LAST_ARG_REGNUM,
16591 IP_REGNUM);
16592 regno = LR_REGNUM;
16593 }
16594 else
16595 regno = LAST_ARG_REGNUM;
16596 }
16597 else
16598 regno = LR_REGNUM;
9e7454d0 16599
cffb2a26 16600 /* Remove the argument registers that were pushed onto the stack. */
16601 asm_fprintf (asm_out_file, "\tadd\t%r, %r, #%d\n",
16602 SP_REGNUM, SP_REGNUM,
16603 current_function_pretend_args_size);
9e7454d0 16604
237533cc 16605 thumb_exit (asm_out_file, regno);
cffb2a26 16606 }
16607
16608 return "";
16609}
16610
16611/* Functions to save and restore machine-specific function data. */
1f3233d1 16612static struct machine_function *
ebd88a36 16613arm_init_machine_status (void)
cffb2a26 16614{
1f3233d1 16615 struct machine_function *machine;
16616 machine = (machine_function *) ggc_alloc_cleared (sizeof (machine_function));
e27ad2d5 16617
9e7454d0 16618#if ARM_FT_UNKNOWN != 0
1f3233d1 16619 machine->func_type = ARM_FT_UNKNOWN;
e27ad2d5 16620#endif
1f3233d1 16621 return machine;
2997ed4d 16622}
16623
cffb2a26 16624/* Return an RTX indicating where the return address to the
16625 calling function can be found. */
16626rtx
ebd88a36 16627arm_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
cffb2a26 16628{
cffb2a26 16629 if (count != 0)
16630 return NULL_RTX;
16631
c1a66faf 16632 return get_hard_reg_initial_val (Pmode, LR_REGNUM);
cffb2a26 16633}
16634
16635/* Do anything needed before RTL is emitted for each function. */
16636void
ebd88a36 16637arm_init_expanders (void)
cffb2a26 16638{
16639 /* Arrange to initialize and mark the machine per-function status. */
16640 init_machine_status = arm_init_machine_status;
0e2db0a2 16641
16642 /* This is to stop the combine pass optimizing away the alignment
16643 adjustment of va_arg. */
16644 /* ??? It is claimed that this should not be necessary. */
16645 if (cfun)
16646 mark_reg_pointer (arg_pointer_rtx, PARM_BOUNDARY);
cffb2a26 16647}
16648
a7712927 16649
f90b51f1 16650/* Like arm_compute_initial_elimination offset. Simpler because there
16651 isn't an ABI specified frame pointer for Thumb. Instead, we set it
16652 to point at the base of the local variables after static stack
16653 space for a function has been allocated. */
a7712927 16654
f9273c43 16655HOST_WIDE_INT
16656thumb_compute_initial_elimination_offset (unsigned int from, unsigned int to)
16657{
16658 arm_stack_offsets *offsets;
a7712927 16659
f9273c43 16660 offsets = arm_get_frame_offsets ();
a7712927 16661
f9273c43 16662 switch (from)
a7712927 16663 {
f9273c43 16664 case ARG_POINTER_REGNUM:
16665 switch (to)
16666 {
16667 case STACK_POINTER_REGNUM:
16668 return offsets->outgoing_args - offsets->saved_args;
a7712927 16669
f9273c43 16670 case FRAME_POINTER_REGNUM:
16671 return offsets->soft_frame - offsets->saved_args;
a7712927 16672
f9273c43 16673 case ARM_HARD_FRAME_POINTER_REGNUM:
16674 return offsets->saved_regs - offsets->saved_args;
a7712927 16675
f90b51f1 16676 case THUMB_HARD_FRAME_POINTER_REGNUM:
16677 return offsets->locals_base - offsets->saved_args;
16678
f9273c43 16679 default:
ed29c566 16680 gcc_unreachable ();
f9273c43 16681 }
16682 break;
a7712927 16683
f9273c43 16684 case FRAME_POINTER_REGNUM:
16685 switch (to)
16686 {
16687 case STACK_POINTER_REGNUM:
16688 return offsets->outgoing_args - offsets->soft_frame;
a7712927 16689
f9273c43 16690 case ARM_HARD_FRAME_POINTER_REGNUM:
16691 return offsets->saved_regs - offsets->soft_frame;
a7712927 16692
f90b51f1 16693 case THUMB_HARD_FRAME_POINTER_REGNUM:
16694 return offsets->locals_base - offsets->soft_frame;
16695
f9273c43 16696 default:
ed29c566 16697 gcc_unreachable ();
f9273c43 16698 }
16699 break;
a7712927 16700
f9273c43 16701 default:
ed29c566 16702 gcc_unreachable ();
f9273c43 16703 }
a7712927 16704}
16705
cffb2a26 16706/* Generate the rest of a function's prologue. */
16707void
25f905c2 16708thumb1_expand_prologue (void)
cffb2a26 16709{
37826745 16710 rtx insn, dwarf;
16711
f9273c43 16712 HOST_WIDE_INT amount;
16713 arm_stack_offsets *offsets;
e27ad2d5 16714 unsigned long func_type;
ef5bbe67 16715 int regno;
237533cc 16716 unsigned long live_regs_mask;
e27ad2d5 16717
16718 func_type = arm_current_func_type ();
9e7454d0 16719
cffb2a26 16720 /* Naked functions don't have prologues. */
e27ad2d5 16721 if (IS_NAKED (func_type))
cffb2a26 16722 return;
16723
e27ad2d5 16724 if (IS_INTERRUPT (func_type))
16725 {
68435912 16726 error ("interrupt Service Routines cannot be coded in Thumb mode");
e27ad2d5 16727 return;
16728 }
16729
25f905c2 16730 live_regs_mask = thumb1_compute_save_reg_mask ();
53f179c0 16731 /* Load the pic register before setting the frame pointer,
16732 so we can use r7 as a temporary work register. */
2cb7d577 16733 if (flag_pic && arm_pic_register != INVALID_REGNUM)
aa6af490 16734 arm_load_pic_register (live_regs_mask);
ea32a06e 16735
f90b51f1 16736 if (!frame_pointer_needed && CALLER_INTERWORKING_SLOT_SIZE > 0)
150502c9 16737 emit_move_insn (gen_rtx_REG (Pmode, ARM_HARD_FRAME_POINTER_REGNUM),
16738 stack_pointer_rtx);
cffb2a26 16739
f90b51f1 16740 offsets = arm_get_frame_offsets ();
f9273c43 16741 amount = offsets->outgoing_args - offsets->saved_regs;
cffb2a26 16742 if (amount)
16743 {
cffb2a26 16744 if (amount < 512)
37826745 16745 {
16746 insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
16747 GEN_INT (- amount)));
16748 RTX_FRAME_RELATED_P (insn) = 1;
16749 }
cffb2a26 16750 else
16751 {
cffb2a26 16752 rtx reg;
16753
16754 /* The stack decrement is too big for an immediate value in a single
16755 insn. In theory we could issue multiple subtracts, but after
16756 three of them it becomes more space efficient to place the full
16757 value in the constant pool and load into a register. (Also the
16758 ARM debugger really likes to see only one stack decrement per
16759 function). So instead we look for a scratch register into which
16760 we can load the decrement, and then we subtract this from the
16761 stack pointer. Unfortunately on the thumb the only available
16762 scratch registers are the argument registers, and we cannot use
16763 these as they may hold arguments to the function. Instead we
16764 attempt to locate a call preserved register which is used by this
16765 function. If we can find one, then we know that it will have
16766 been pushed at the start of the prologue and so we can corrupt
16767 it now. */
16768 for (regno = LAST_ARG_REGNUM + 1; regno <= LAST_LO_REGNUM; regno++)
237533cc 16769 if (live_regs_mask & (1 << regno)
215b30b3 16770 && !(frame_pointer_needed
16771 && (regno == THUMB_HARD_FRAME_POINTER_REGNUM)))
cffb2a26 16772 break;
16773
9ac46427 16774 if (regno > LAST_LO_REGNUM) /* Very unlikely. */
cffb2a26 16775 {
1a83b3ff 16776 rtx spare = gen_rtx_REG (SImode, IP_REGNUM);
cffb2a26 16777
b89db9a7 16778 /* Choose an arbitrary, non-argument low register. */
1a83b3ff 16779 reg = gen_rtx_REG (SImode, LAST_LO_REGNUM);
cffb2a26 16780
16781 /* Save it by copying it into a high, scratch register. */
bf82d677 16782 emit_insn (gen_movsi (spare, reg));
16783 /* Add a USE to stop propagate_one_insn() from barfing. */
063a05c7 16784 emit_insn (gen_prologue_use (spare));
cffb2a26 16785
16786 /* Decrement the stack. */
a12be13c 16787 emit_insn (gen_movsi (reg, GEN_INT (- amount)));
37826745 16788 insn = emit_insn (gen_addsi3 (stack_pointer_rtx,
16789 stack_pointer_rtx, reg));
16790 RTX_FRAME_RELATED_P (insn) = 1;
0083a3b9 16791 dwarf = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
37826745 16792 plus_constant (stack_pointer_rtx,
af204f9f 16793 -amount));
37826745 16794 RTX_FRAME_RELATED_P (dwarf) = 1;
16795 REG_NOTES (insn)
16796 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
16797 REG_NOTES (insn));
cffb2a26 16798
16799 /* Restore the low register's original value. */
16800 emit_insn (gen_movsi (reg, spare));
9e7454d0 16801
cffb2a26 16802 /* Emit a USE of the restored scratch register, so that flow
16803 analysis will not consider the restore redundant. The
16804 register won't be used again in this function and isn't
16805 restored by the epilogue. */
063a05c7 16806 emit_insn (gen_prologue_use (reg));
cffb2a26 16807 }
16808 else
16809 {
1a83b3ff 16810 reg = gen_rtx_REG (SImode, regno);
cffb2a26 16811
a12be13c 16812 emit_insn (gen_movsi (reg, GEN_INT (- amount)));
37826745 16813
16814 insn = emit_insn (gen_addsi3 (stack_pointer_rtx,
16815 stack_pointer_rtx, reg));
16816 RTX_FRAME_RELATED_P (insn) = 1;
0083a3b9 16817 dwarf = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
37826745 16818 plus_constant (stack_pointer_rtx,
af204f9f 16819 -amount));
37826745 16820 RTX_FRAME_RELATED_P (dwarf) = 1;
16821 REG_NOTES (insn)
16822 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
16823 REG_NOTES (insn));
cffb2a26 16824 }
16825 }
f90b51f1 16826 }
16827
16828 if (frame_pointer_needed)
25f905c2 16829 thumb_set_frame_pointer (offsets);
9e7454d0 16830
363d487e 16831 /* If we are profiling, make sure no instructions are scheduled before
16832 the call to mcount. Similarly if the user has requested no
16833 scheduling in the prolog. Similarly if we want non-call exceptions
16834 using the EABI unwinder, to prevent faulting instructions from being
16835 swapped with a stack adjustment. */
16836 if (current_function_profile || !TARGET_SCHED_PROLOG
16837 || (ARM_EABI_UNWIND_TABLES && flag_non_call_exceptions))
cffb2a26 16838 emit_insn (gen_blockage ());
ef5bbe67 16839
16840 cfun->machine->lr_save_eliminated = !thumb_force_lr_save ();
237533cc 16841 if (live_regs_mask & 0xff)
16842 cfun->machine->lr_save_eliminated = 0;
cffb2a26 16843}
16844
237533cc 16845
cffb2a26 16846void
25f905c2 16847thumb1_expand_epilogue (void)
cffb2a26 16848{
f9273c43 16849 HOST_WIDE_INT amount;
16850 arm_stack_offsets *offsets;
58d6528b 16851 int regno;
16852
e27ad2d5 16853 /* Naked functions don't have prologues. */
16854 if (IS_NAKED (arm_current_func_type ()))
cffb2a26 16855 return;
16856
f9273c43 16857 offsets = arm_get_frame_offsets ();
16858 amount = offsets->outgoing_args - offsets->saved_regs;
16859
cffb2a26 16860 if (frame_pointer_needed)
f90b51f1 16861 {
16862 emit_insn (gen_movsi (stack_pointer_rtx, hard_frame_pointer_rtx));
16863 amount = offsets->locals_base - offsets->saved_regs;
16864 }
a60f1840 16865
a650636a 16866 gcc_assert (amount >= 0);
f90b51f1 16867 if (amount)
cffb2a26 16868 {
cffb2a26 16869 if (amount < 512)
16870 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
16871 GEN_INT (amount)));
16872 else
16873 {
16874 /* r3 is always free in the epilogue. */
1a83b3ff 16875 rtx reg = gen_rtx_REG (SImode, LAST_ARG_REGNUM);
cffb2a26 16876
16877 emit_insn (gen_movsi (reg, GEN_INT (amount)));
16878 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, reg));
16879 }
16880 }
9e7454d0 16881
cffb2a26 16882 /* Emit a USE (stack_pointer_rtx), so that
16883 the stack adjustment will not be deleted. */
063a05c7 16884 emit_insn (gen_prologue_use (stack_pointer_rtx));
cffb2a26 16885
81f6de2f 16886 if (current_function_profile || !TARGET_SCHED_PROLOG)
cffb2a26 16887 emit_insn (gen_blockage ());
58d6528b 16888
16889 /* Emit a clobber for each insn that will be restored in the epilogue,
16890 so that flow2 will get register lifetimes correct. */
16891 for (regno = 0; regno < 13; regno++)
3072d30e 16892 if (df_regs_ever_live_p (regno) && !call_used_regs[regno])
58d6528b 16893 emit_insn (gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, regno)));
16894
3072d30e 16895 if (! df_regs_ever_live_p (LR_REGNUM))
58d6528b 16896 emit_insn (gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, LR_REGNUM)));
cffb2a26 16897}
16898
17d9b0c3 16899static void
25f905c2 16900thumb1_output_function_prologue (FILE *f, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
cffb2a26 16901{
53f179c0 16902 unsigned long live_regs_mask = 0;
16903 unsigned long l_mask;
16904 unsigned high_regs_pushed = 0;
37826745 16905 int cfa_offset = 0;
cffb2a26 16906 int regno;
16907
e27ad2d5 16908 if (IS_NAKED (arm_current_func_type ()))
cffb2a26 16909 return;
16910
16911 if (is_called_in_ARM_mode (current_function_decl))
16912 {
16913 const char * name;
16914
ed29c566 16915 gcc_assert (GET_CODE (DECL_RTL (current_function_decl)) == MEM);
16916 gcc_assert (GET_CODE (XEXP (DECL_RTL (current_function_decl), 0))
16917 == SYMBOL_REF);
cffb2a26 16918 name = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
9e7454d0 16919
cffb2a26 16920 /* Generate code sequence to switch us into Thumb mode. */
16921 /* The .code 32 directive has already been emitted by
f5443994 16922 ASM_DECLARE_FUNCTION_NAME. */
cffb2a26 16923 asm_fprintf (f, "\torr\t%r, %r, #1\n", IP_REGNUM, PC_REGNUM);
16924 asm_fprintf (f, "\tbx\t%r\n", IP_REGNUM);
16925
16926 /* Generate a label, so that the debugger will notice the
16927 change in instruction sets. This label is also used by
16928 the assembler to bypass the ARM code when this function
16929 is called from a Thumb encoded function elsewhere in the
16930 same file. Hence the definition of STUB_NAME here must
674a8f0b 16931 agree with the definition in gas/config/tc-arm.c. */
9e7454d0 16932
cffb2a26 16933#define STUB_NAME ".real_start_of"
9e7454d0 16934
7fe1d31c 16935 fprintf (f, "\t.code\t16\n");
cffb2a26 16936#ifdef ARM_PE
16937 if (arm_dllexport_name_p (name))
08a98e4f 16938 name = arm_strip_name_encoding (name);
9e7454d0 16939#endif
cffb2a26 16940 asm_fprintf (f, "\t.globl %s%U%s\n", STUB_NAME, name);
7fe1d31c 16941 fprintf (f, "\t.thumb_func\n");
cffb2a26 16942 asm_fprintf (f, "%s%U%s:\n", STUB_NAME, name);
16943 }
9e7454d0 16944
cffb2a26 16945 if (current_function_pretend_args_size)
16946 {
1774763d 16947 /* Output unwind directive for the stack adjustment. */
16948 if (ARM_EABI_UNWIND_TABLES)
16949 fprintf (f, "\t.pad #%d\n",
16950 current_function_pretend_args_size);
16951
71904594 16952 if (cfun->machine->uses_anonymous_args)
cffb2a26 16953 {
16954 int num_pushes;
9e7454d0 16955
7fe1d31c 16956 fprintf (f, "\tpush\t{");
cffb2a26 16957
36837fde 16958 num_pushes = ARM_NUM_INTS (current_function_pretend_args_size);
9e7454d0 16959
cffb2a26 16960 for (regno = LAST_ARG_REGNUM + 1 - num_pushes;
16961 regno <= LAST_ARG_REGNUM;
215b30b3 16962 regno++)
cffb2a26 16963 asm_fprintf (f, "%r%s", regno,
16964 regno == LAST_ARG_REGNUM ? "" : ", ");
16965
7fe1d31c 16966 fprintf (f, "}\n");
cffb2a26 16967 }
16968 else
9e7454d0 16969 asm_fprintf (f, "\tsub\t%r, %r, #%d\n",
cffb2a26 16970 SP_REGNUM, SP_REGNUM,
16971 current_function_pretend_args_size);
37826745 16972
16973 /* We don't need to record the stores for unwinding (would it
16974 help the debugger any if we did?), but record the change in
16975 the stack pointer. */
16976 if (dwarf2out_do_frame ())
16977 {
16978 char *l = dwarf2out_cfi_label ();
53f179c0 16979
37826745 16980 cfa_offset = cfa_offset + current_function_pretend_args_size;
16981 dwarf2out_def_cfa (l, SP_REGNUM, cfa_offset);
16982 }
cffb2a26 16983 }
16984
53f179c0 16985 /* Get the registers we are going to push. */
25f905c2 16986 live_regs_mask = thumb1_compute_save_reg_mask ();
53f179c0 16987 /* Extract a mask of the ones we can give to the Thumb's push instruction. */
237533cc 16988 l_mask = live_regs_mask & 0x40ff;
53f179c0 16989 /* Then count how many other high registers will need to be pushed. */
16990 high_regs_pushed = bit_count (live_regs_mask & 0x0f00);
cffb2a26 16991
16992 if (TARGET_BACKTRACE)
16993 {
53f179c0 16994 unsigned offset;
16995 unsigned work_register;
9e7454d0 16996
cffb2a26 16997 /* We have been asked to create a stack backtrace structure.
16998 The code looks like this:
9e7454d0 16999
cffb2a26 17000 0 .align 2
17001 0 func:
17002 0 sub SP, #16 Reserve space for 4 registers.
237533cc 17003 2 push {R7} Push low registers.
cffb2a26 17004 4 add R7, SP, #20 Get the stack pointer before the push.
17005 6 str R7, [SP, #8] Store the stack pointer (before reserving the space).
17006 8 mov R7, PC Get hold of the start of this code plus 12.
17007 10 str R7, [SP, #16] Store it.
17008 12 mov R7, FP Get hold of the current frame pointer.
17009 14 str R7, [SP, #4] Store it.
17010 16 mov R7, LR Get hold of the current return address.
17011 18 str R7, [SP, #12] Store it.
17012 20 add R7, SP, #16 Point at the start of the backtrace structure.
17013 22 mov FP, R7 Put this value into the frame pointer. */
17014
237533cc 17015 work_register = thumb_find_work_register (live_regs_mask);
9e7454d0 17016
1774763d 17017 if (ARM_EABI_UNWIND_TABLES)
17018 asm_fprintf (f, "\t.pad #16\n");
17019
cffb2a26 17020 asm_fprintf
17021 (f, "\tsub\t%r, %r, #16\t%@ Create stack backtrace structure\n",
17022 SP_REGNUM, SP_REGNUM);
37826745 17023
17024 if (dwarf2out_do_frame ())
17025 {
17026 char *l = dwarf2out_cfi_label ();
53f179c0 17027
37826745 17028 cfa_offset = cfa_offset + 16;
17029 dwarf2out_def_cfa (l, SP_REGNUM, cfa_offset);
17030 }
17031
237533cc 17032 if (l_mask)
17033 {
17034 thumb_pushpop (f, l_mask, 1, &cfa_offset, l_mask);
e54325a1 17035 offset = bit_count (l_mask) * UNITS_PER_WORD;
237533cc 17036 }
17037 else
17038 offset = 0;
9e7454d0 17039
cffb2a26 17040 asm_fprintf (f, "\tadd\t%r, %r, #%d\n", work_register, SP_REGNUM,
17041 offset + 16 + current_function_pretend_args_size);
9e7454d0 17042
cffb2a26 17043 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
17044 offset + 4);
17045
17046 /* Make sure that the instruction fetching the PC is in the right place
17047 to calculate "start of backtrace creation code + 12". */
237533cc 17048 if (l_mask)
cffb2a26 17049 {
17050 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, PC_REGNUM);
17051 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
17052 offset + 12);
17053 asm_fprintf (f, "\tmov\t%r, %r\n", work_register,
17054 ARM_HARD_FRAME_POINTER_REGNUM);
17055 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
17056 offset);
17057 }
17058 else
17059 {
17060 asm_fprintf (f, "\tmov\t%r, %r\n", work_register,
17061 ARM_HARD_FRAME_POINTER_REGNUM);
17062 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
17063 offset);
17064 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, PC_REGNUM);
17065 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
17066 offset + 12);
17067 }
9e7454d0 17068
cffb2a26 17069 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, LR_REGNUM);
17070 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
17071 offset + 8);
17072 asm_fprintf (f, "\tadd\t%r, %r, #%d\n", work_register, SP_REGNUM,
17073 offset + 12);
17074 asm_fprintf (f, "\tmov\t%r, %r\t\t%@ Backtrace structure created\n",
17075 ARM_HARD_FRAME_POINTER_REGNUM, work_register);
17076 }
442e3cb9 17077 /* Optimization: If we are not pushing any low registers but we are going
53f179c0 17078 to push some high registers then delay our first push. This will just
17079 be a push of LR and we can combine it with the push of the first high
17080 register. */
17081 else if ((l_mask & 0xff) != 0
17082 || (high_regs_pushed == 0 && l_mask))
237533cc 17083 thumb_pushpop (f, l_mask, 1, &cfa_offset, l_mask);
cffb2a26 17084
cffb2a26 17085 if (high_regs_pushed)
17086 {
53f179c0 17087 unsigned pushable_regs;
17088 unsigned next_hi_reg;
cffb2a26 17089
17090 for (next_hi_reg = 12; next_hi_reg > LAST_LO_REGNUM; next_hi_reg--)
237533cc 17091 if (live_regs_mask & (1 << next_hi_reg))
9f468b67 17092 break;
cffb2a26 17093
237533cc 17094 pushable_regs = l_mask & 0xff;
cffb2a26 17095
17096 if (pushable_regs == 0)
237533cc 17097 pushable_regs = 1 << thumb_find_work_register (live_regs_mask);
cffb2a26 17098
17099 while (high_regs_pushed > 0)
17100 {
53f179c0 17101 unsigned long real_regs_mask = 0;
37826745 17102
53f179c0 17103 for (regno = LAST_LO_REGNUM; regno >= 0; regno --)
cffb2a26 17104 {
237533cc 17105 if (pushable_regs & (1 << regno))
cffb2a26 17106 {
17107 asm_fprintf (f, "\tmov\t%r, %r\n", regno, next_hi_reg);
9e7454d0 17108
53f179c0 17109 high_regs_pushed --;
37826745 17110 real_regs_mask |= (1 << next_hi_reg);
9e7454d0 17111
cffb2a26 17112 if (high_regs_pushed)
9ac46427 17113 {
53f179c0 17114 for (next_hi_reg --; next_hi_reg > LAST_LO_REGNUM;
17115 next_hi_reg --)
237533cc 17116 if (live_regs_mask & (1 << next_hi_reg))
cffb2a26 17117 break;
9ac46427 17118 }
cffb2a26 17119 else
17120 {
237533cc 17121 pushable_regs &= ~((1 << regno) - 1);
cffb2a26 17122 break;
17123 }
17124 }
17125 }
37826745 17126
53f179c0 17127 /* If we had to find a work register and we have not yet
17128 saved the LR then add it to the list of regs to push. */
17129 if (l_mask == (1 << LR_REGNUM))
17130 {
17131 thumb_pushpop (f, pushable_regs | (1 << LR_REGNUM),
17132 1, &cfa_offset,
17133 real_regs_mask | (1 << LR_REGNUM));
17134 l_mask = 0;
17135 }
17136 else
17137 thumb_pushpop (f, pushable_regs, 1, &cfa_offset, real_regs_mask);
cffb2a26 17138 }
cffb2a26 17139 }
17140}
17141
17142/* Handle the case of a double word load into a low register from
17143 a computed memory address. The computed address may involve a
17144 register which is overwritten by the load. */
0bd59681 17145const char *
ebd88a36 17146thumb_load_double_from_address (rtx *operands)
cffb2a26 17147{
17148 rtx addr;
17149 rtx base;
17150 rtx offset;
17151 rtx arg1;
17152 rtx arg2;
9e7454d0 17153
ed29c566 17154 gcc_assert (GET_CODE (operands[0]) == REG);
17155 gcc_assert (GET_CODE (operands[1]) == MEM);
cffb2a26 17156
17157 /* Get the memory address. */
17158 addr = XEXP (operands[1], 0);
9e7454d0 17159
cffb2a26 17160 /* Work out how the memory address is computed. */
17161 switch (GET_CODE (addr))
17162 {
17163 case REG:
788fcce0 17164 operands[2] = adjust_address (operands[1], SImode, 4);
a60f1840 17165
cffb2a26 17166 if (REGNO (operands[0]) == REGNO (addr))
17167 {
17168 output_asm_insn ("ldr\t%H0, %2", operands);
17169 output_asm_insn ("ldr\t%0, %1", operands);
17170 }
17171 else
17172 {
17173 output_asm_insn ("ldr\t%0, %1", operands);
17174 output_asm_insn ("ldr\t%H0, %2", operands);
17175 }
17176 break;
9e7454d0 17177
cffb2a26 17178 case CONST:
17179 /* Compute <address> + 4 for the high order load. */
788fcce0 17180 operands[2] = adjust_address (operands[1], SImode, 4);
a60f1840 17181
cffb2a26 17182 output_asm_insn ("ldr\t%0, %1", operands);
17183 output_asm_insn ("ldr\t%H0, %2", operands);
17184 break;
9e7454d0 17185
cffb2a26 17186 case PLUS:
17187 arg1 = XEXP (addr, 0);
17188 arg2 = XEXP (addr, 1);
9e7454d0 17189
cffb2a26 17190 if (CONSTANT_P (arg1))
17191 base = arg2, offset = arg1;
17192 else
17193 base = arg1, offset = arg2;
9e7454d0 17194
ed29c566 17195 gcc_assert (GET_CODE (base) == REG);
cffb2a26 17196
17197 /* Catch the case of <address> = <reg> + <reg> */
17198 if (GET_CODE (offset) == REG)
17199 {
17200 int reg_offset = REGNO (offset);
17201 int reg_base = REGNO (base);
17202 int reg_dest = REGNO (operands[0]);
9e7454d0 17203
cffb2a26 17204 /* Add the base and offset registers together into the
17205 higher destination register. */
17206 asm_fprintf (asm_out_file, "\tadd\t%r, %r, %r",
17207 reg_dest + 1, reg_base, reg_offset);
9e7454d0 17208
cffb2a26 17209 /* Load the lower destination register from the address in
17210 the higher destination register. */
17211 asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #0]",
17212 reg_dest, reg_dest + 1);
9e7454d0 17213
cffb2a26 17214 /* Load the higher destination register from its own address
17215 plus 4. */
17216 asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #4]",
17217 reg_dest + 1, reg_dest + 1);
17218 }
17219 else
17220 {
17221 /* Compute <address> + 4 for the high order load. */
788fcce0 17222 operands[2] = adjust_address (operands[1], SImode, 4);
9e7454d0 17223
cffb2a26 17224 /* If the computed address is held in the low order register
17225 then load the high order register first, otherwise always
17226 load the low order register first. */
17227 if (REGNO (operands[0]) == REGNO (base))
17228 {
17229 output_asm_insn ("ldr\t%H0, %2", operands);
17230 output_asm_insn ("ldr\t%0, %1", operands);
17231 }
17232 else
17233 {
17234 output_asm_insn ("ldr\t%0, %1", operands);
17235 output_asm_insn ("ldr\t%H0, %2", operands);
17236 }
17237 }
17238 break;
17239
17240 case LABEL_REF:
17241 /* With no registers to worry about we can just load the value
17242 directly. */
788fcce0 17243 operands[2] = adjust_address (operands[1], SImode, 4);
9e7454d0 17244
cffb2a26 17245 output_asm_insn ("ldr\t%H0, %2", operands);
17246 output_asm_insn ("ldr\t%0, %1", operands);
17247 break;
9e7454d0 17248
cffb2a26 17249 default:
ed29c566 17250 gcc_unreachable ();
cffb2a26 17251 }
9e7454d0 17252
cffb2a26 17253 return "";
17254}
17255
0bd59681 17256const char *
ebd88a36 17257thumb_output_move_mem_multiple (int n, rtx *operands)
cffb2a26 17258{
17259 rtx tmp;
17260
17261 switch (n)
17262 {
17263 case 2:
960f3acf 17264 if (REGNO (operands[4]) > REGNO (operands[5]))
cffb2a26 17265 {
960f3acf 17266 tmp = operands[4];
17267 operands[4] = operands[5];
17268 operands[5] = tmp;
cffb2a26 17269 }
960f3acf 17270 output_asm_insn ("ldmia\t%1!, {%4, %5}", operands);
17271 output_asm_insn ("stmia\t%0!, {%4, %5}", operands);
cffb2a26 17272 break;
17273
17274 case 3:
960f3acf 17275 if (REGNO (operands[4]) > REGNO (operands[5]))
cffb2a26 17276 {
960f3acf 17277 tmp = operands[4];
17278 operands[4] = operands[5];
17279 operands[5] = tmp;
cffb2a26 17280 }
960f3acf 17281 if (REGNO (operands[5]) > REGNO (operands[6]))
cffb2a26 17282 {
960f3acf 17283 tmp = operands[5];
17284 operands[5] = operands[6];
17285 operands[6] = tmp;
cffb2a26 17286 }
960f3acf 17287 if (REGNO (operands[4]) > REGNO (operands[5]))
cffb2a26 17288 {
960f3acf 17289 tmp = operands[4];
17290 operands[4] = operands[5];
17291 operands[5] = tmp;
cffb2a26 17292 }
9e7454d0 17293
960f3acf 17294 output_asm_insn ("ldmia\t%1!, {%4, %5, %6}", operands);
17295 output_asm_insn ("stmia\t%0!, {%4, %5, %6}", operands);
cffb2a26 17296 break;
17297
17298 default:
ed29c566 17299 gcc_unreachable ();
cffb2a26 17300 }
17301
17302 return "";
17303}
17304
afe27f3b 17305/* Output a call-via instruction for thumb state. */
17306const char *
17307thumb_call_via_reg (rtx reg)
17308{
17309 int regno = REGNO (reg);
17310 rtx *labelp;
17311
a52972b8 17312 gcc_assert (regno < LR_REGNUM);
afe27f3b 17313
17314 /* If we are in the normal text section we can use a single instance
17315 per compilation unit. If we are doing function sections, then we need
17316 an entry per section, since we can't rely on reachability. */
2f14b1f9 17317 if (in_section == text_section)
afe27f3b 17318 {
17319 thumb_call_reg_needed = 1;
17320
17321 if (thumb_call_via_label[regno] == NULL)
17322 thumb_call_via_label[regno] = gen_label_rtx ();
17323 labelp = thumb_call_via_label + regno;
17324 }
17325 else
17326 {
17327 if (cfun->machine->call_via[regno] == NULL)
17328 cfun->machine->call_via[regno] = gen_label_rtx ();
17329 labelp = cfun->machine->call_via + regno;
17330 }
17331
17332 output_asm_insn ("bl\t%a0", labelp);
17333 return "";
17334}
17335
a12be13c 17336/* Routines for generating rtl. */
cffb2a26 17337void
008c057d 17338thumb_expand_movmemqi (rtx *operands)
cffb2a26 17339{
17340 rtx out = copy_to_mode_reg (SImode, XEXP (operands[0], 0));
17341 rtx in = copy_to_mode_reg (SImode, XEXP (operands[1], 0));
17342 HOST_WIDE_INT len = INTVAL (operands[2]);
17343 HOST_WIDE_INT offset = 0;
17344
17345 while (len >= 12)
17346 {
960f3acf 17347 emit_insn (gen_movmem12b (out, in, out, in));
cffb2a26 17348 len -= 12;
17349 }
9e7454d0 17350
cffb2a26 17351 if (len >= 8)
17352 {
960f3acf 17353 emit_insn (gen_movmem8b (out, in, out, in));
cffb2a26 17354 len -= 8;
17355 }
9e7454d0 17356
cffb2a26 17357 if (len >= 4)
17358 {
17359 rtx reg = gen_reg_rtx (SImode);
1a83b3ff 17360 emit_insn (gen_movsi (reg, gen_rtx_MEM (SImode, in)));
17361 emit_insn (gen_movsi (gen_rtx_MEM (SImode, out), reg));
cffb2a26 17362 len -= 4;
17363 offset += 4;
17364 }
9e7454d0 17365
cffb2a26 17366 if (len >= 2)
17367 {
17368 rtx reg = gen_reg_rtx (HImode);
9e7454d0 17369 emit_insn (gen_movhi (reg, gen_rtx_MEM (HImode,
1a83b3ff 17370 plus_constant (in, offset))));
17371 emit_insn (gen_movhi (gen_rtx_MEM (HImode, plus_constant (out, offset)),
cffb2a26 17372 reg));
17373 len -= 2;
17374 offset += 2;
17375 }
9e7454d0 17376
cffb2a26 17377 if (len)
17378 {
17379 rtx reg = gen_reg_rtx (QImode);
1a83b3ff 17380 emit_insn (gen_movqi (reg, gen_rtx_MEM (QImode,
17381 plus_constant (in, offset))));
17382 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (out, offset)),
cffb2a26 17383 reg));
17384 }
17385}
17386
cffb2a26 17387void
ebd88a36 17388thumb_reload_out_hi (rtx *operands)
cffb2a26 17389{
17390 emit_insn (gen_thumb_movhi_clobber (operands[0], operands[1], operands[2]));
17391}
17392
9e7454d0 17393/* Handle reading a half-word from memory during reload. */
cffb2a26 17394void
ebd88a36 17395thumb_reload_in_hi (rtx *operands ATTRIBUTE_UNUSED)
cffb2a26 17396{
ed29c566 17397 gcc_unreachable ();
cffb2a26 17398}
17399
78fe751b 17400/* Return the length of a function name prefix
17401 that starts with the character 'c'. */
17402static int
ebd88a36 17403arm_get_strip_length (int c)
78fe751b 17404{
17405 switch (c)
17406 {
17407 ARM_NAME_ENCODING_LENGTHS
9e7454d0 17408 default: return 0;
78fe751b 17409 }
17410}
17411
17412/* Return a pointer to a function's name with any
17413 and all prefix encodings stripped from it. */
17414const char *
ebd88a36 17415arm_strip_name_encoding (const char *name)
78fe751b 17416{
17417 int skip;
9e7454d0 17418
78fe751b 17419 while ((skip = arm_get_strip_length (* name)))
17420 name += skip;
17421
17422 return name;
17423}
17424
d2fcdd8d 17425/* If there is a '*' anywhere in the name's prefix, then
17426 emit the stripped name verbatim, otherwise prepend an
17427 underscore if leading underscores are being used. */
d2fcdd8d 17428void
ebd88a36 17429arm_asm_output_labelref (FILE *stream, const char *name)
d2fcdd8d 17430{
17431 int skip;
17432 int verbatim = 0;
17433
17434 while ((skip = arm_get_strip_length (* name)))
17435 {
17436 verbatim |= (*name == '*');
17437 name += skip;
17438 }
17439
17440 if (verbatim)
17441 fputs (name, stream);
17442 else
17443 asm_fprintf (stream, "%U%s", name);
17444}
17445
5fad5123 17446static void
17447arm_file_start (void)
17448{
17449 int val;
17450
25f905c2 17451 if (TARGET_UNIFIED_ASM)
17452 asm_fprintf (asm_out_file, "\t.syntax unified\n");
17453
5fad5123 17454 if (TARGET_BPABI)
17455 {
17456 const char *fpu_name;
17457 if (arm_select[0].string)
17458 asm_fprintf (asm_out_file, "\t.cpu %s\n", arm_select[0].string);
17459 else if (arm_select[1].string)
17460 asm_fprintf (asm_out_file, "\t.arch %s\n", arm_select[1].string);
17461 else
17462 asm_fprintf (asm_out_file, "\t.cpu %s\n",
17463 all_cores[arm_default_cpu].name);
17464
17465 if (TARGET_SOFT_FLOAT)
17466 {
17467 if (TARGET_VFP)
17468 fpu_name = "softvfp";
17469 else
17470 fpu_name = "softfpa";
17471 }
17472 else
17473 {
b5a0636d 17474 int set_float_abi_attributes = 0;
5fad5123 17475 switch (arm_fpu_arch)
17476 {
17477 case FPUTYPE_FPA:
17478 fpu_name = "fpa";
17479 break;
17480 case FPUTYPE_FPA_EMU2:
17481 fpu_name = "fpe2";
17482 break;
17483 case FPUTYPE_FPA_EMU3:
17484 fpu_name = "fpe3";
17485 break;
17486 case FPUTYPE_MAVERICK:
17487 fpu_name = "maverick";
17488 break;
17489 case FPUTYPE_VFP:
5fad5123 17490 fpu_name = "vfp";
b5a0636d 17491 set_float_abi_attributes = 1;
17492 break;
17493 case FPUTYPE_VFP3:
17494 fpu_name = "vfp3";
17495 set_float_abi_attributes = 1;
5fad5123 17496 break;
d98a3884 17497 case FPUTYPE_NEON:
17498 fpu_name = "neon";
17499 set_float_abi_attributes = 1;
17500 break;
5fad5123 17501 default:
17502 abort();
17503 }
b5a0636d 17504 if (set_float_abi_attributes)
17505 {
17506 if (TARGET_HARD_FLOAT)
17507 asm_fprintf (asm_out_file, "\t.eabi_attribute 27, 3\n");
17508 if (TARGET_HARD_FLOAT_ABI)
17509 asm_fprintf (asm_out_file, "\t.eabi_attribute 28, 1\n");
17510 }
5fad5123 17511 }
17512 asm_fprintf (asm_out_file, "\t.fpu %s\n", fpu_name);
17513
17514 /* Some of these attributes only apply when the corresponding features
17515 are used. However we don't have any easy way of figuring this out.
17516 Conservatively record the setting that would have been used. */
17517
17518 /* Tag_ABI_PCS_wchar_t. */
17519 asm_fprintf (asm_out_file, "\t.eabi_attribute 18, %d\n",
17520 (int)WCHAR_TYPE_SIZE / BITS_PER_UNIT);
17521
17522 /* Tag_ABI_FP_rounding. */
17523 if (flag_rounding_math)
17524 asm_fprintf (asm_out_file, "\t.eabi_attribute 19, 1\n");
17525 if (!flag_unsafe_math_optimizations)
17526 {
17527 /* Tag_ABI_FP_denomal. */
17528 asm_fprintf (asm_out_file, "\t.eabi_attribute 20, 1\n");
17529 /* Tag_ABI_FP_exceptions. */
17530 asm_fprintf (asm_out_file, "\t.eabi_attribute 21, 1\n");
17531 }
17532 /* Tag_ABI_FP_user_exceptions. */
17533 if (flag_signaling_nans)
17534 asm_fprintf (asm_out_file, "\t.eabi_attribute 22, 1\n");
17535 /* Tag_ABI_FP_number_model. */
17536 asm_fprintf (asm_out_file, "\t.eabi_attribute 23, %d\n",
17537 flag_finite_math_only ? 1 : 3);
17538
17539 /* Tag_ABI_align8_needed. */
17540 asm_fprintf (asm_out_file, "\t.eabi_attribute 24, 1\n");
17541 /* Tag_ABI_align8_preserved. */
17542 asm_fprintf (asm_out_file, "\t.eabi_attribute 25, 1\n");
17543 /* Tag_ABI_enum_size. */
17544 asm_fprintf (asm_out_file, "\t.eabi_attribute 26, %d\n",
17545 flag_short_enums ? 1 : 2);
17546
17547 /* Tag_ABI_optimization_goals. */
17548 if (optimize_size)
17549 val = 4;
17550 else if (optimize >= 2)
17551 val = 2;
17552 else if (optimize)
17553 val = 1;
17554 else
17555 val = 6;
17556 asm_fprintf (asm_out_file, "\t.eabi_attribute 30, %d\n", val);
17557 }
17558 default_file_start();
17559}
17560
afe27f3b 17561static void
17562arm_file_end (void)
17563{
17564 int regno;
17565
9ffe2f5a 17566 if (NEED_INDICATE_EXEC_STACK)
17567 /* Add .note.GNU-stack. */
17568 file_end_indicate_exec_stack ();
17569
afe27f3b 17570 if (! thumb_call_reg_needed)
17571 return;
17572
2f14b1f9 17573 switch_to_section (text_section);
afe27f3b 17574 asm_fprintf (asm_out_file, "\t.code 16\n");
17575 ASM_OUTPUT_ALIGN (asm_out_file, 1);
17576
a52972b8 17577 for (regno = 0; regno < LR_REGNUM; regno++)
afe27f3b 17578 {
17579 rtx label = thumb_call_via_label[regno];
17580
17581 if (label != 0)
17582 {
17583 targetm.asm_out.internal_label (asm_out_file, "L",
17584 CODE_LABEL_NUMBER (label));
17585 asm_fprintf (asm_out_file, "\tbx\t%r\n", regno);
17586 }
17587 }
17588}
17589
1f3233d1 17590rtx aof_pic_label;
17591
64266206 17592#ifdef AOF_ASSEMBLER
66aacf41 17593/* Special functions only needed when producing AOF syntax assembler. */
64266206 17594
69120d26 17595struct pic_chain
17596{
bba10fb8 17597 struct pic_chain * next;
29122112 17598 const char * symname;
69120d26 17599};
17600
bba10fb8 17601static struct pic_chain * aof_pic_chain = NULL;
69120d26 17602
17603rtx
ebd88a36 17604aof_pic_entry (rtx x)
69120d26 17605{
bba10fb8 17606 struct pic_chain ** chainp;
69120d26 17607 int offset;
17608
17609 if (aof_pic_label == NULL_RTX)
17610 {
76676c8e 17611 aof_pic_label = gen_rtx_SYMBOL_REF (Pmode, "x$adcons");
69120d26 17612 }
17613
17614 for (offset = 0, chainp = &aof_pic_chain; *chainp;
17615 offset += 4, chainp = &(*chainp)->next)
17616 if ((*chainp)->symname == XSTR (x, 0))
17617 return plus_constant (aof_pic_label, offset);
17618
17619 *chainp = (struct pic_chain *) xmalloc (sizeof (struct pic_chain));
17620 (*chainp)->next = NULL;
17621 (*chainp)->symname = XSTR (x, 0);
17622 return plus_constant (aof_pic_label, offset);
17623}
17624
17625void
ebd88a36 17626aof_dump_pic_table (FILE *f)
69120d26 17627{
bba10fb8 17628 struct pic_chain * chain;
69120d26 17629
17630 if (aof_pic_chain == NULL)
17631 return;
17632
caceeb43 17633 asm_fprintf (f, "\tAREA |%r$$adcons|, BASED %r\n",
17634 PIC_OFFSET_TABLE_REGNUM,
17635 PIC_OFFSET_TABLE_REGNUM);
69120d26 17636 fputs ("|x$adcons|\n", f);
9e7454d0 17637
69120d26 17638 for (chain = aof_pic_chain; chain; chain = chain->next)
17639 {
17640 fputs ("\tDCD\t", f);
17641 assemble_name (f, chain->symname);
17642 fputs ("\n", f);
17643 }
17644}
17645
64266206 17646int arm_text_section_count = 1;
17647
2f14b1f9 17648/* A get_unnamed_section callback for switching to the text section. */
17649
17650static void
17651aof_output_text_section_asm_op (const void *data ATTRIBUTE_UNUSED)
64266206 17652{
2f14b1f9 17653 fprintf (asm_out_file, "\tAREA |C$$code%d|, CODE, READONLY",
64266206 17654 arm_text_section_count++);
17655 if (flag_pic)
2f14b1f9 17656 fprintf (asm_out_file, ", PIC, REENTRANT");
17657 fprintf (asm_out_file, "\n");
64266206 17658}
17659
17660static int arm_data_section_count = 1;
17661
2f14b1f9 17662/* A get_unnamed_section callback for switching to the data section. */
17663
17664static void
17665aof_output_data_section_asm_op (const void *data ATTRIBUTE_UNUSED)
17666{
17667 fprintf (asm_out_file, "\tAREA |C$$data%d|, DATA\n",
17668 arm_data_section_count++);
17669}
17670
17671/* Implement TARGET_ASM_INIT_SECTIONS.
17672
17673 AOF Assembler syntax is a nightmare when it comes to areas, since once
17674 we change from one area to another, we can't go back again. Instead,
17675 we must create a new area with the same attributes and add the new output
17676 to that. Unfortunately, there is nothing we can do here to guarantee that
17677 two areas with the same attributes will be linked adjacently in the
17678 resulting executable, so we have to be careful not to do pc-relative
17679 addressing across such boundaries. */
17680
17681static void
17682aof_asm_init_sections (void)
17683{
17684 text_section = get_unnamed_section (SECTION_CODE,
17685 aof_output_text_section_asm_op, NULL);
17686 data_section = get_unnamed_section (SECTION_WRITE,
17687 aof_output_data_section_asm_op, NULL);
17688 readonly_data_section = text_section;
17689}
17690
17691void
17692zero_init_section (void)
64266206 17693{
2f14b1f9 17694 static int zero_init_count = 1;
17695
17696 fprintf (asm_out_file, "\tAREA |C$$zidata%d|,NOINIT\n", zero_init_count++);
17697 in_section = NULL;
64266206 17698}
17699
17700/* The AOF assembler is religiously strict about declarations of
17701 imported and exported symbols, so that it is impossible to declare
ad87de1e 17702 a function as imported near the beginning of the file, and then to
64266206 17703 export it later on. It is, however, possible to delay the decision
17704 until all the functions in the file have been compiled. To get
17705 around this, we maintain a list of the imports and exports, and
17706 delete from it any that are subsequently defined. At the end of
17707 compilation we spit the remainder of the list out before the END
17708 directive. */
17709
17710struct import
17711{
bba10fb8 17712 struct import * next;
29122112 17713 const char * name;
64266206 17714};
17715
bba10fb8 17716static struct import * imports_list = NULL;
64266206 17717
17718void
ebd88a36 17719aof_add_import (const char *name)
64266206 17720{
bba10fb8 17721 struct import * new;
64266206 17722
17723 for (new = imports_list; new; new = new->next)
17724 if (new->name == name)
17725 return;
17726
17727 new = (struct import *) xmalloc (sizeof (struct import));
17728 new->next = imports_list;
17729 imports_list = new;
17730 new->name = name;
17731}
17732
17733void
ebd88a36 17734aof_delete_import (const char *name)
64266206 17735{
bba10fb8 17736 struct import ** old;
64266206 17737
17738 for (old = &imports_list; *old; old = & (*old)->next)
17739 {
17740 if ((*old)->name == name)
17741 {
17742 *old = (*old)->next;
17743 return;
17744 }
17745 }
17746}
17747
17748int arm_main_function = 0;
17749
f6940372 17750static void
ebd88a36 17751aof_dump_imports (FILE *f)
64266206 17752{
17753 /* The AOF assembler needs this to cause the startup code to be extracted
17754 from the library. Brining in __main causes the whole thing to work
17755 automagically. */
17756 if (arm_main_function)
17757 {
2f14b1f9 17758 switch_to_section (text_section);
64266206 17759 fputs ("\tIMPORT __main\n", f);
17760 fputs ("\tDCD __main\n", f);
17761 }
17762
17763 /* Now dump the remaining imports. */
17764 while (imports_list)
17765 {
17766 fprintf (f, "\tIMPORT\t");
17767 assemble_name (f, imports_list->name);
17768 fputc ('\n', f);
17769 imports_list = imports_list->next;
17770 }
17771}
67c1e638 17772
17773static void
ebd88a36 17774aof_globalize_label (FILE *stream, const char *name)
67c1e638 17775{
17776 default_globalize_label (stream, name);
17777 if (! strcmp (name, "main"))
17778 arm_main_function = 1;
17779}
f6940372 17780
92c473b8 17781static void
3285410a 17782aof_file_start (void)
92c473b8 17783{
17784 fputs ("__r0\tRN\t0\n", asm_out_file);
17785 fputs ("__a1\tRN\t0\n", asm_out_file);
17786 fputs ("__a2\tRN\t1\n", asm_out_file);
17787 fputs ("__a3\tRN\t2\n", asm_out_file);
17788 fputs ("__a4\tRN\t3\n", asm_out_file);
17789 fputs ("__v1\tRN\t4\n", asm_out_file);
17790 fputs ("__v2\tRN\t5\n", asm_out_file);
17791 fputs ("__v3\tRN\t6\n", asm_out_file);
17792 fputs ("__v4\tRN\t7\n", asm_out_file);
17793 fputs ("__v5\tRN\t8\n", asm_out_file);
17794 fputs ("__v6\tRN\t9\n", asm_out_file);
17795 fputs ("__sl\tRN\t10\n", asm_out_file);
17796 fputs ("__fp\tRN\t11\n", asm_out_file);
17797 fputs ("__ip\tRN\t12\n", asm_out_file);
17798 fputs ("__sp\tRN\t13\n", asm_out_file);
17799 fputs ("__lr\tRN\t14\n", asm_out_file);
17800 fputs ("__pc\tRN\t15\n", asm_out_file);
17801 fputs ("__f0\tFN\t0\n", asm_out_file);
17802 fputs ("__f1\tFN\t1\n", asm_out_file);
17803 fputs ("__f2\tFN\t2\n", asm_out_file);
17804 fputs ("__f3\tFN\t3\n", asm_out_file);
17805 fputs ("__f4\tFN\t4\n", asm_out_file);
17806 fputs ("__f5\tFN\t5\n", asm_out_file);
17807 fputs ("__f6\tFN\t6\n", asm_out_file);
17808 fputs ("__f7\tFN\t7\n", asm_out_file);
2f14b1f9 17809 switch_to_section (text_section);
92c473b8 17810}
17811
f6940372 17812static void
ebd88a36 17813aof_file_end (void)
f6940372 17814{
17815 if (flag_pic)
17816 aof_dump_pic_table (asm_out_file);
afe27f3b 17817 arm_file_end ();
f6940372 17818 aof_dump_imports (asm_out_file);
17819 fputs ("\tEND\n", asm_out_file);
17820}
64266206 17821#endif /* AOF_ASSEMBLER */
2cb4ac60 17822
7811991d 17823#ifndef ARM_PE
17824/* Symbols in the text segment can be accessed without indirecting via the
17825 constant pool; it may take an extra binary operation, but this is still
17826 faster than indirecting via memory. Don't do this when not optimizing,
17827 since we won't be calculating al of the offsets necessary to do this
17828 simplification. */
17829
17830static void
ebd88a36 17831arm_encode_section_info (tree decl, rtx rtl, int first)
7811991d 17832{
17833 /* This doesn't work with AOF syntax, since the string table may be in
17834 a different AREA. */
17835#ifndef AOF_ASSEMBLER
a814bad5 17836 if (optimize > 0 && TREE_CONSTANT (decl))
2c129d70 17837 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1;
7811991d 17838#endif
17839
f655717d 17840 default_encode_section_info (decl, rtl, first);
7811991d 17841}
17842#endif /* !ARM_PE */
c6933ba6 17843
805e22b2 17844static void
ebd88a36 17845arm_internal_label (FILE *stream, const char *prefix, unsigned long labelno)
805e22b2 17846{
17847 if (arm_ccfsm_state == 3 && (unsigned) arm_target_label == labelno
17848 && !strcmp (prefix, "L"))
17849 {
17850 arm_ccfsm_state = 0;
17851 arm_target_insn = NULL;
17852 }
17853 default_internal_label (stream, prefix, labelno);
17854}
17855
6988553d 17856/* Output code to add DELTA to the first argument, and then jump
17857 to FUNCTION. Used for C++ multiple inheritance. */
6988553d 17858static void
ebd88a36 17859arm_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
17860 HOST_WIDE_INT delta,
17861 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
17862 tree function)
c6933ba6 17863{
a2cd141b 17864 static int thunk_label = 0;
17865 char label[256];
ca1ede88 17866 char labelpc[256];
c6933ba6 17867 int mi_delta = delta;
17868 const char *const mi_op = mi_delta < 0 ? "sub" : "add";
17869 int shift = 0;
45550790 17870 int this_regno = (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function)
c6933ba6 17871 ? 1 : 0);
17872 if (mi_delta < 0)
17873 mi_delta = - mi_delta;
25f905c2 17874 /* When generating 16-bit thumb code, thunks are entered in arm mode. */
17875 if (TARGET_THUMB1)
a2cd141b 17876 {
17877 int labelno = thunk_label++;
17878 ASM_GENERATE_INTERNAL_LABEL (label, "LTHUMBFUNC", labelno);
17879 fputs ("\tldr\tr12, ", file);
17880 assemble_name (file, label);
17881 fputc ('\n', file);
ca1ede88 17882 if (flag_pic)
17883 {
17884 /* If we are generating PIC, the ldr instruction below loads
17885 "(target - 7) - .LTHUNKPCn" into r12. The pc reads as
17886 the address of the add + 8, so we have:
17887
17888 r12 = (target - 7) - .LTHUNKPCn + (.LTHUNKPCn + 8)
17889 = target + 1.
17890
17891 Note that we have "+ 1" because some versions of GNU ld
17892 don't set the low bit of the result for R_ARM_REL32
17893 relocations against thumb function symbols. */
17894 ASM_GENERATE_INTERNAL_LABEL (labelpc, "LTHUNKPC", labelno);
17895 assemble_name (file, labelpc);
17896 fputs (":\n", file);
17897 fputs ("\tadd\tr12, pc, r12\n", file);
17898 }
a2cd141b 17899 }
25f905c2 17900 /* TODO: Use movw/movt for large constants when available. */
c6933ba6 17901 while (mi_delta != 0)
17902 {
17903 if ((mi_delta & (3 << shift)) == 0)
17904 shift += 2;
17905 else
17906 {
17907 asm_fprintf (file, "\t%s\t%r, %r, #%d\n",
17908 mi_op, this_regno, this_regno,
17909 mi_delta & (0xff << shift));
17910 mi_delta &= ~(0xff << shift);
17911 shift += 8;
17912 }
17913 }
25f905c2 17914 if (TARGET_THUMB1)
a2cd141b 17915 {
17916 fprintf (file, "\tbx\tr12\n");
17917 ASM_OUTPUT_ALIGN (file, 2);
17918 assemble_name (file, label);
17919 fputs (":\n", file);
ca1ede88 17920 if (flag_pic)
17921 {
17922 /* Output ".word .LTHUNKn-7-.LTHUNKPCn". */
17923 rtx tem = XEXP (DECL_RTL (function), 0);
17924 tem = gen_rtx_PLUS (GET_MODE (tem), tem, GEN_INT (-7));
17925 tem = gen_rtx_MINUS (GET_MODE (tem),
17926 tem,
17927 gen_rtx_SYMBOL_REF (Pmode,
17928 ggc_strdup (labelpc)));
17929 assemble_integer (tem, 4, BITS_PER_WORD, 1);
17930 }
17931 else
17932 /* Output ".word .LTHUNKn". */
17933 assemble_integer (XEXP (DECL_RTL (function), 0), 4, BITS_PER_WORD, 1);
a2cd141b 17934 }
17935 else
17936 {
17937 fputs ("\tb\t", file);
17938 assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0));
17939 if (NEED_PLT_RELOC)
17940 fputs ("(PLT)", file);
17941 fputc ('\n', file);
17942 }
c6933ba6 17943}
755eb2b4 17944
17945int
068c4bec 17946arm_emit_vector_const (FILE *file, rtx x)
755eb2b4 17947{
17948 int i;
17949 const char * pattern;
17950
ed29c566 17951 gcc_assert (GET_CODE (x) == CONST_VECTOR);
755eb2b4 17952
17953 switch (GET_MODE (x))
17954 {
17955 case V2SImode: pattern = "%08x"; break;
17956 case V4HImode: pattern = "%04x"; break;
17957 case V8QImode: pattern = "%02x"; break;
ed29c566 17958 default: gcc_unreachable ();
755eb2b4 17959 }
17960
17961 fprintf (file, "0x");
17962 for (i = CONST_VECTOR_NUNITS (x); i--;)
17963 {
17964 rtx element;
17965
17966 element = CONST_VECTOR_ELT (x, i);
17967 fprintf (file, pattern, INTVAL (element));
17968 }
17969
17970 return 1;
17971}
17972
17973const char *
068c4bec 17974arm_output_load_gr (rtx *operands)
755eb2b4 17975{
17976 rtx reg;
17977 rtx offset;
17978 rtx wcgr;
17979 rtx sum;
9e7454d0 17980
755eb2b4 17981 if (GET_CODE (operands [1]) != MEM
17982 || GET_CODE (sum = XEXP (operands [1], 0)) != PLUS
17983 || GET_CODE (reg = XEXP (sum, 0)) != REG
17984 || GET_CODE (offset = XEXP (sum, 1)) != CONST_INT
17985 || ((INTVAL (offset) < 1024) && (INTVAL (offset) > -1024)))
17986 return "wldrw%?\t%0, %1";
9e7454d0 17987
17988 /* Fix up an out-of-range load of a GR register. */
755eb2b4 17989 output_asm_insn ("str%?\t%0, [sp, #-4]!\t@ Start of GR load expansion", & reg);
17990 wcgr = operands[0];
17991 operands[0] = reg;
17992 output_asm_insn ("ldr%?\t%0, %1", operands);
17993
17994 operands[0] = wcgr;
17995 operands[1] = reg;
17996 output_asm_insn ("tmcr%?\t%0, %1", operands);
17997 output_asm_insn ("ldr%?\t%0, [sp], #4\t@ End of GR load expansion", & reg);
17998
17999 return "";
18000}
f2eb2b4d 18001
4c66acf1 18002/* Worker function for TARGET_SETUP_INCOMING_VARARGS.
18003
18004 On the ARM, PRETEND_SIZE is set in order to have the prologue push the last
18005 named arg and all anonymous args onto the stack.
18006 XXX I know the prologue shouldn't be pushing registers, but it is faster
18007 that way. */
18008
18009static void
18010arm_setup_incoming_varargs (CUMULATIVE_ARGS *cum,
18011 enum machine_mode mode ATTRIBUTE_UNUSED,
18012 tree type ATTRIBUTE_UNUSED,
18013 int *pretend_size,
18014 int second_time ATTRIBUTE_UNUSED)
18015{
18016 cfun->machine->uses_anonymous_args = 1;
18017 if (cum->nregs < NUM_ARG_REGS)
18018 *pretend_size = (NUM_ARG_REGS - cum->nregs) * UNITS_PER_WORD;
18019}
a2cd141b 18020
58552ed0 18021/* Return nonzero if the CONSUMER instruction (a store) does not need
a2cd141b 18022 PRODUCER's value to calculate the address. */
18023
18024int
18025arm_no_early_store_addr_dep (rtx producer, rtx consumer)
18026{
18027 rtx value = PATTERN (producer);
18028 rtx addr = PATTERN (consumer);
18029
18030 if (GET_CODE (value) == COND_EXEC)
18031 value = COND_EXEC_CODE (value);
18032 if (GET_CODE (value) == PARALLEL)
18033 value = XVECEXP (value, 0, 0);
18034 value = XEXP (value, 0);
18035 if (GET_CODE (addr) == COND_EXEC)
18036 addr = COND_EXEC_CODE (addr);
18037 if (GET_CODE (addr) == PARALLEL)
18038 addr = XVECEXP (addr, 0, 0);
18039 addr = XEXP (addr, 0);
9e7454d0 18040
a2cd141b 18041 return !reg_overlap_mentioned_p (value, addr);
18042}
18043
58552ed0 18044/* Return nonzero if the CONSUMER instruction (an ALU op) does not
a2cd141b 18045 have an early register shift value or amount dependency on the
18046 result of PRODUCER. */
18047
18048int
18049arm_no_early_alu_shift_dep (rtx producer, rtx consumer)
18050{
18051 rtx value = PATTERN (producer);
18052 rtx op = PATTERN (consumer);
18053 rtx early_op;
18054
18055 if (GET_CODE (value) == COND_EXEC)
18056 value = COND_EXEC_CODE (value);
18057 if (GET_CODE (value) == PARALLEL)
18058 value = XVECEXP (value, 0, 0);
18059 value = XEXP (value, 0);
18060 if (GET_CODE (op) == COND_EXEC)
18061 op = COND_EXEC_CODE (op);
18062 if (GET_CODE (op) == PARALLEL)
18063 op = XVECEXP (op, 0, 0);
18064 op = XEXP (op, 1);
9e7454d0 18065
a2cd141b 18066 early_op = XEXP (op, 0);
18067 /* This is either an actual independent shift, or a shift applied to
18068 the first operand of another operation. We want the whole shift
18069 operation. */
18070 if (GET_CODE (early_op) == REG)
18071 early_op = op;
18072
18073 return !reg_overlap_mentioned_p (value, early_op);
18074}
18075
58552ed0 18076/* Return nonzero if the CONSUMER instruction (an ALU op) does not
a2cd141b 18077 have an early register shift value dependency on the result of
18078 PRODUCER. */
18079
18080int
18081arm_no_early_alu_shift_value_dep (rtx producer, rtx consumer)
18082{
18083 rtx value = PATTERN (producer);
18084 rtx op = PATTERN (consumer);
18085 rtx early_op;
18086
18087 if (GET_CODE (value) == COND_EXEC)
18088 value = COND_EXEC_CODE (value);
18089 if (GET_CODE (value) == PARALLEL)
18090 value = XVECEXP (value, 0, 0);
18091 value = XEXP (value, 0);
18092 if (GET_CODE (op) == COND_EXEC)
18093 op = COND_EXEC_CODE (op);
18094 if (GET_CODE (op) == PARALLEL)
18095 op = XVECEXP (op, 0, 0);
18096 op = XEXP (op, 1);
9e7454d0 18097
a2cd141b 18098 early_op = XEXP (op, 0);
18099
18100 /* This is either an actual independent shift, or a shift applied to
18101 the first operand of another operation. We want the value being
18102 shifted, in either case. */
18103 if (GET_CODE (early_op) != REG)
18104 early_op = XEXP (early_op, 0);
9e7454d0 18105
a2cd141b 18106 return !reg_overlap_mentioned_p (value, early_op);
18107}
18108
58552ed0 18109/* Return nonzero if the CONSUMER (a mul or mac op) does not
a2cd141b 18110 have an early register mult dependency on the result of
18111 PRODUCER. */
18112
18113int
18114arm_no_early_mul_dep (rtx producer, rtx consumer)
18115{
18116 rtx value = PATTERN (producer);
18117 rtx op = PATTERN (consumer);
18118
18119 if (GET_CODE (value) == COND_EXEC)
18120 value = COND_EXEC_CODE (value);
18121 if (GET_CODE (value) == PARALLEL)
18122 value = XVECEXP (value, 0, 0);
18123 value = XEXP (value, 0);
18124 if (GET_CODE (op) == COND_EXEC)
18125 op = COND_EXEC_CODE (op);
18126 if (GET_CODE (op) == PARALLEL)
18127 op = XVECEXP (op, 0, 0);
18128 op = XEXP (op, 1);
9e7454d0 18129
a2cd141b 18130 return (GET_CODE (op) == PLUS
18131 && !reg_overlap_mentioned_p (value, XEXP (op, 0)));
18132}
18133
72f1246c 18134/* We can't rely on the caller doing the proper promotion when
18135 using APCS or ATPCS. */
18136
18137static bool
18138arm_promote_prototypes (tree t ATTRIBUTE_UNUSED)
18139{
50459f30 18140 return !TARGET_AAPCS_BASED;
72f1246c 18141}
18142
7faec15f 18143
18144/* AAPCS based ABIs use short enums by default. */
18145
18146static bool
18147arm_default_short_enums (void)
18148{
6783d878 18149 return TARGET_AAPCS_BASED && arm_abi != ARM_ABI_AAPCS_LINUX;
7faec15f 18150}
25ba5be6 18151
18152
18153/* AAPCS requires that anonymous bitfields affect structure alignment. */
18154
18155static bool
18156arm_align_anon_bitfield (void)
18157{
18158 return TARGET_AAPCS_BASED;
18159}
c1dc02de 18160
18161
18162/* The generic C++ ABI says 64-bit (long long). The EABI says 32-bit. */
18163
18164static tree
18165arm_cxx_guard_type (void)
18166{
18167 return TARGET_AAPCS_BASED ? integer_type_node : long_long_integer_type_node;
18168}
18169
bcaec148 18170/* Return non-zero if the consumer (a multiply-accumulate instruction)
18171 has an accumulator dependency on the result of the producer (a
18172 multiplication instruction) and no other dependency on that result. */
18173int
18174arm_mac_accumulator_is_mul_result (rtx producer, rtx consumer)
18175{
18176 rtx mul = PATTERN (producer);
18177 rtx mac = PATTERN (consumer);
18178 rtx mul_result;
18179 rtx mac_op0, mac_op1, mac_acc;
18180
18181 if (GET_CODE (mul) == COND_EXEC)
18182 mul = COND_EXEC_CODE (mul);
18183 if (GET_CODE (mac) == COND_EXEC)
18184 mac = COND_EXEC_CODE (mac);
18185
18186 /* Check that mul is of the form (set (...) (mult ...))
18187 and mla is of the form (set (...) (plus (mult ...) (...))). */
18188 if ((GET_CODE (mul) != SET || GET_CODE (XEXP (mul, 1)) != MULT)
18189 || (GET_CODE (mac) != SET || GET_CODE (XEXP (mac, 1)) != PLUS
18190 || GET_CODE (XEXP (XEXP (mac, 1), 0)) != MULT))
18191 return 0;
18192
18193 mul_result = XEXP (mul, 0);
18194 mac_op0 = XEXP (XEXP (XEXP (mac, 1), 0), 0);
18195 mac_op1 = XEXP (XEXP (XEXP (mac, 1), 0), 1);
18196 mac_acc = XEXP (XEXP (mac, 1), 1);
18197
18198 return (reg_overlap_mentioned_p (mul_result, mac_acc)
18199 && !reg_overlap_mentioned_p (mul_result, mac_op0)
18200 && !reg_overlap_mentioned_p (mul_result, mac_op1));
18201}
18202
c1dc02de 18203
442e3cb9 18204/* The EABI says test the least significant bit of a guard variable. */
c1dc02de 18205
18206static bool
18207arm_cxx_guard_mask_bit (void)
18208{
18209 return TARGET_AAPCS_BASED;
18210}
600f4be7 18211
18212
18213/* The EABI specifies that all array cookies are 8 bytes long. */
18214
18215static tree
18216arm_get_cookie_size (tree type)
18217{
18218 tree size;
18219
18220 if (!TARGET_AAPCS_BASED)
18221 return default_cxx_get_cookie_size (type);
18222
7016c612 18223 size = build_int_cst (sizetype, 8);
600f4be7 18224 return size;
18225}
18226
18227
18228/* The EABI says that array cookies should also contain the element size. */
18229
18230static bool
18231arm_cookie_has_size (void)
18232{
18233 return TARGET_AAPCS_BASED;
18234}
853b7640 18235
18236
18237/* The EABI says constructors and destructors should return a pointer to
18238 the object constructed/destroyed. */
18239
18240static bool
18241arm_cxx_cdtor_returns_this (void)
18242{
18243 return TARGET_AAPCS_BASED;
18244}
4c44712e 18245
4fc9a8ec 18246/* The EABI says that an inline function may never be the key
18247 method. */
18248
18249static bool
18250arm_cxx_key_method_may_be_inline (void)
18251{
18252 return !TARGET_AAPCS_BASED;
18253}
18254
7908506d 18255static void
18256arm_cxx_determine_class_data_visibility (tree decl)
18257{
18258 if (!TARGET_AAPCS_BASED)
18259 return;
4fc9a8ec 18260
7908506d 18261 /* In general, \S 3.2.5.5 of the ARM EABI requires that class data
18262 is exported. However, on systems without dynamic vague linkage,
18263 \S 3.2.5.6 says that COMDAT class data has hidden linkage. */
18264 if (!TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P && DECL_COMDAT (decl))
18265 DECL_VISIBILITY (decl) = VISIBILITY_HIDDEN;
18266 else
18267 DECL_VISIBILITY (decl) = VISIBILITY_DEFAULT;
18268 DECL_VISIBILITY_SPECIFIED (decl) = 1;
18269}
a60f1840 18270
4fc9a8ec 18271static bool
7908506d 18272arm_cxx_class_data_always_comdat (void)
4fc9a8ec 18273{
7908506d 18274 /* \S 3.2.5.4 of the ARM C++ ABI says that class data only have
18275 vague linkage if the class has no key function. */
18276 return !TARGET_AAPCS_BASED;
4fc9a8ec 18277}
4c44712e 18278
46b9ff5e 18279
18280/* The EABI says __aeabi_atexit should be used to register static
18281 destructors. */
18282
18283static bool
18284arm_cxx_use_aeabi_atexit (void)
18285{
18286 return TARGET_AAPCS_BASED;
18287}
18288
18289
4c44712e 18290void
18291arm_set_return_address (rtx source, rtx scratch)
18292{
18293 arm_stack_offsets *offsets;
18294 HOST_WIDE_INT delta;
18295 rtx addr;
18296 unsigned long saved_regs;
18297
18298 saved_regs = arm_compute_save_reg_mask ();
18299
18300 if ((saved_regs & (1 << LR_REGNUM)) == 0)
18301 emit_move_insn (gen_rtx_REG (Pmode, LR_REGNUM), source);
18302 else
18303 {
18304 if (frame_pointer_needed)
18305 addr = plus_constant(hard_frame_pointer_rtx, -4);
18306 else
18307 {
18308 /* LR will be the first saved register. */
18309 offsets = arm_get_frame_offsets ();
18310 delta = offsets->outgoing_args - (offsets->frame + 4);
18311
9e7454d0 18312
4c44712e 18313 if (delta >= 4096)
18314 {
18315 emit_insn (gen_addsi3 (scratch, stack_pointer_rtx,
18316 GEN_INT (delta & ~4095)));
18317 addr = scratch;
18318 delta &= 4095;
18319 }
18320 else
18321 addr = stack_pointer_rtx;
18322
18323 addr = plus_constant (addr, delta);
18324 }
788fcce0 18325 emit_move_insn (gen_frame_mem (Pmode, addr), source);
4c44712e 18326 }
18327}
18328
18329
18330void
18331thumb_set_return_address (rtx source, rtx scratch)
18332{
18333 arm_stack_offsets *offsets;
4c44712e 18334 HOST_WIDE_INT delta;
25f905c2 18335 HOST_WIDE_INT limit;
4c44712e 18336 int reg;
18337 rtx addr;
237533cc 18338 unsigned long mask;
4c44712e 18339
18340 emit_insn (gen_rtx_USE (VOIDmode, source));
4c44712e 18341
25f905c2 18342 mask = thumb1_compute_save_reg_mask ();
237533cc 18343 if (mask & (1 << LR_REGNUM))
4c44712e 18344 {
18345 offsets = arm_get_frame_offsets ();
18346
25f905c2 18347 limit = 1024;
4c44712e 18348 /* Find the saved regs. */
18349 if (frame_pointer_needed)
18350 {
18351 delta = offsets->soft_frame - offsets->saved_args;
18352 reg = THUMB_HARD_FRAME_POINTER_REGNUM;
25f905c2 18353 if (TARGET_THUMB1)
18354 limit = 128;
4c44712e 18355 }
18356 else
18357 {
18358 delta = offsets->outgoing_args - offsets->saved_args;
18359 reg = SP_REGNUM;
18360 }
18361 /* Allow for the stack frame. */
25f905c2 18362 if (TARGET_THUMB1 && TARGET_BACKTRACE)
4c44712e 18363 delta -= 16;
18364 /* The link register is always the first saved register. */
18365 delta -= 4;
9e7454d0 18366
4c44712e 18367 /* Construct the address. */
18368 addr = gen_rtx_REG (SImode, reg);
25f905c2 18369 if (delta > limit)
4c44712e 18370 {
18371 emit_insn (gen_movsi (scratch, GEN_INT (delta)));
18372 emit_insn (gen_addsi3 (scratch, scratch, stack_pointer_rtx));
18373 addr = scratch;
18374 }
18375 else
18376 addr = plus_constant (addr, delta);
18377
788fcce0 18378 emit_move_insn (gen_frame_mem (Pmode, addr), source);
4c44712e 18379 }
18380 else
18381 emit_move_insn (gen_rtx_REG (Pmode, LR_REGNUM), source);
18382}
18383
9e7454d0 18384/* Implements target hook vector_mode_supported_p. */
18385bool
18386arm_vector_mode_supported_p (enum machine_mode mode)
18387{
d98a3884 18388 /* Neon also supports V2SImode, etc. listed in the clause below. */
18389 if (TARGET_NEON && (mode == V2SFmode || mode == V4SImode || mode == V8HImode
18390 || mode == V16QImode || mode == V4SFmode || mode == V2DImode))
18391 return true;
18392
9e7454d0 18393 if ((mode == V2SImode)
18394 || (mode == V4HImode)
18395 || (mode == V8QImode))
18396 return true;
18397
18398 return false;
18399}
c49547c4 18400
18401/* Implement TARGET_SHIFT_TRUNCATION_MASK. SImode shifts use normal
18402 ARM insns and therefore guarantee that the shift count is modulo 256.
18403 DImode shifts (those implemented by lib1funcs.asm or by optabs.c)
18404 guarantee no particular behavior for out-of-range counts. */
18405
18406static unsigned HOST_WIDE_INT
18407arm_shift_truncation_mask (enum machine_mode mode)
18408{
18409 return mode == SImode ? 255 : 0;
18410}
5f9d1097 18411
18412
18413/* Map internal gcc register numbers to DWARF2 register numbers. */
18414
18415unsigned int
18416arm_dbx_register_number (unsigned int regno)
18417{
18418 if (regno < 16)
18419 return regno;
18420
18421 /* TODO: Legacy targets output FPA regs as registers 16-23 for backwards
18422 compatibility. The EABI defines them as registers 96-103. */
18423 if (IS_FPA_REGNUM (regno))
18424 return (TARGET_AAPCS_BASED ? 96 : 16) + regno - FIRST_FPA_REGNUM;
18425
b5a0636d 18426 /* FIXME: VFPv3 register numbering. */
5f9d1097 18427 if (IS_VFP_REGNUM (regno))
18428 return 64 + regno - FIRST_VFP_REGNUM;
18429
18430 if (IS_IWMMXT_GR_REGNUM (regno))
18431 return 104 + regno - FIRST_IWMMXT_GR_REGNUM;
18432
18433 if (IS_IWMMXT_REGNUM (regno))
18434 return 112 + regno - FIRST_IWMMXT_REGNUM;
18435
ed29c566 18436 gcc_unreachable ();
5f9d1097 18437}
18438
1774763d 18439
18440#ifdef TARGET_UNWIND_INFO
25f905c2 18441/* Emit unwind directives for a store-multiple instruction or stack pointer
18442 push during alignment.
18443 These should only ever be generated by the function prologue code, so
18444 expect them to have a particular form. */
1774763d 18445
18446static void
25f905c2 18447arm_unwind_emit_sequence (FILE * asm_out_file, rtx p)
1774763d 18448{
18449 int i;
18450 HOST_WIDE_INT offset;
18451 HOST_WIDE_INT nregs;
18452 int reg_size;
18453 unsigned reg;
18454 unsigned lastreg;
18455 rtx e;
18456
1774763d 18457 e = XVECEXP (p, 0, 0);
25f905c2 18458 if (GET_CODE (e) != SET)
18459 abort ();
18460
18461 /* First insn will adjust the stack pointer. */
1774763d 18462 if (GET_CODE (e) != SET
18463 || GET_CODE (XEXP (e, 0)) != REG
18464 || REGNO (XEXP (e, 0)) != SP_REGNUM
18465 || GET_CODE (XEXP (e, 1)) != PLUS)
18466 abort ();
18467
18468 offset = -INTVAL (XEXP (XEXP (e, 1), 1));
18469 nregs = XVECLEN (p, 0) - 1;
18470
18471 reg = REGNO (XEXP (XVECEXP (p, 0, 1), 1));
18472 if (reg < 16)
18473 {
18474 /* The function prologue may also push pc, but not annotate it as it is
77aa6362 18475 never restored. We turn this into a stack pointer adjustment. */
1774763d 18476 if (nregs * 4 == offset - 4)
18477 {
18478 fprintf (asm_out_file, "\t.pad #4\n");
18479 offset -= 4;
18480 }
18481 reg_size = 4;
382a2a57 18482 fprintf (asm_out_file, "\t.save {");
1774763d 18483 }
18484 else if (IS_VFP_REGNUM (reg))
18485 {
1774763d 18486 reg_size = 8;
382a2a57 18487 fprintf (asm_out_file, "\t.vsave {");
1774763d 18488 }
18489 else if (reg >= FIRST_FPA_REGNUM && reg <= LAST_FPA_REGNUM)
18490 {
18491 /* FPA registers are done differently. */
7781aa77 18492 asm_fprintf (asm_out_file, "\t.save %r, %wd\n", reg, nregs);
1774763d 18493 return;
18494 }
18495 else
18496 /* Unknown register type. */
18497 abort ();
18498
18499 /* If the stack increment doesn't match the size of the saved registers,
18500 something has gone horribly wrong. */
18501 if (offset != nregs * reg_size)
18502 abort ();
18503
1774763d 18504 offset = 0;
18505 lastreg = 0;
18506 /* The remaining insns will describe the stores. */
18507 for (i = 1; i <= nregs; i++)
18508 {
18509 /* Expect (set (mem <addr>) (reg)).
18510 Where <addr> is (reg:SP) or (plus (reg:SP) (const_int)). */
18511 e = XVECEXP (p, 0, i);
18512 if (GET_CODE (e) != SET
18513 || GET_CODE (XEXP (e, 0)) != MEM
18514 || GET_CODE (XEXP (e, 1)) != REG)
18515 abort ();
a60f1840 18516
1774763d 18517 reg = REGNO (XEXP (e, 1));
18518 if (reg < lastreg)
18519 abort ();
a60f1840 18520
1774763d 18521 if (i != 1)
18522 fprintf (asm_out_file, ", ");
18523 /* We can't use %r for vfp because we need to use the
18524 double precision register names. */
18525 if (IS_VFP_REGNUM (reg))
18526 asm_fprintf (asm_out_file, "d%d", (reg - FIRST_VFP_REGNUM) / 2);
18527 else
18528 asm_fprintf (asm_out_file, "%r", reg);
18529
18530#ifdef ENABLE_CHECKING
18531 /* Check that the addresses are consecutive. */
18532 e = XEXP (XEXP (e, 0), 0);
18533 if (GET_CODE (e) == PLUS)
18534 {
18535 offset += reg_size;
18536 if (GET_CODE (XEXP (e, 0)) != REG
18537 || REGNO (XEXP (e, 0)) != SP_REGNUM
18538 || GET_CODE (XEXP (e, 1)) != CONST_INT
18539 || offset != INTVAL (XEXP (e, 1)))
18540 abort ();
18541 }
18542 else if (i != 1
18543 || GET_CODE (e) != REG
18544 || REGNO (e) != SP_REGNUM)
18545 abort ();
18546#endif
18547 }
18548 fprintf (asm_out_file, "}\n");
18549}
18550
18551/* Emit unwind directives for a SET. */
18552
18553static void
18554arm_unwind_emit_set (FILE * asm_out_file, rtx p)
18555{
18556 rtx e0;
18557 rtx e1;
25f905c2 18558 unsigned reg;
1774763d 18559
18560 e0 = XEXP (p, 0);
18561 e1 = XEXP (p, 1);
18562 switch (GET_CODE (e0))
18563 {
18564 case MEM:
18565 /* Pushing a single register. */
18566 if (GET_CODE (XEXP (e0, 0)) != PRE_DEC
18567 || GET_CODE (XEXP (XEXP (e0, 0), 0)) != REG
18568 || REGNO (XEXP (XEXP (e0, 0), 0)) != SP_REGNUM)
18569 abort ();
18570
18571 asm_fprintf (asm_out_file, "\t.save ");
18572 if (IS_VFP_REGNUM (REGNO (e1)))
18573 asm_fprintf(asm_out_file, "{d%d}\n",
18574 (REGNO (e1) - FIRST_VFP_REGNUM) / 2);
18575 else
18576 asm_fprintf(asm_out_file, "{%r}\n", REGNO (e1));
18577 break;
18578
18579 case REG:
18580 if (REGNO (e0) == SP_REGNUM)
18581 {
18582 /* A stack increment. */
18583 if (GET_CODE (e1) != PLUS
18584 || GET_CODE (XEXP (e1, 0)) != REG
18585 || REGNO (XEXP (e1, 0)) != SP_REGNUM
18586 || GET_CODE (XEXP (e1, 1)) != CONST_INT)
18587 abort ();
18588
7781aa77 18589 asm_fprintf (asm_out_file, "\t.pad #%wd\n",
1774763d 18590 -INTVAL (XEXP (e1, 1)));
18591 }
18592 else if (REGNO (e0) == HARD_FRAME_POINTER_REGNUM)
18593 {
18594 HOST_WIDE_INT offset;
a60f1840 18595
1774763d 18596 if (GET_CODE (e1) == PLUS)
18597 {
18598 if (GET_CODE (XEXP (e1, 0)) != REG
18599 || GET_CODE (XEXP (e1, 1)) != CONST_INT)
18600 abort ();
18601 reg = REGNO (XEXP (e1, 0));
18602 offset = INTVAL (XEXP (e1, 1));
7781aa77 18603 asm_fprintf (asm_out_file, "\t.setfp %r, %r, #%wd\n",
1774763d 18604 HARD_FRAME_POINTER_REGNUM, reg,
18605 INTVAL (XEXP (e1, 1)));
18606 }
18607 else if (GET_CODE (e1) == REG)
18608 {
18609 reg = REGNO (e1);
18610 asm_fprintf (asm_out_file, "\t.setfp %r, %r\n",
18611 HARD_FRAME_POINTER_REGNUM, reg);
18612 }
18613 else
18614 abort ();
18615 }
18616 else if (GET_CODE (e1) == REG && REGNO (e1) == SP_REGNUM)
18617 {
18618 /* Move from sp to reg. */
18619 asm_fprintf (asm_out_file, "\t.movsp %r\n", REGNO (e0));
18620 }
d105e3e2 18621 else if (GET_CODE (e1) == PLUS
18622 && GET_CODE (XEXP (e1, 0)) == REG
18623 && REGNO (XEXP (e1, 0)) == SP_REGNUM
18624 && GET_CODE (XEXP (e1, 1)) == CONST_INT)
18625 {
18626 /* Set reg to offset from sp. */
18627 asm_fprintf (asm_out_file, "\t.movsp %r, #%d\n",
18628 REGNO (e0), (int)INTVAL(XEXP (e1, 1)));
18629 }
25f905c2 18630 else if (GET_CODE (e1) == UNSPEC && XINT (e1, 1) == UNSPEC_STACK_ALIGN)
18631 {
18632 /* Stack pointer save before alignment. */
18633 reg = REGNO (e0);
18634 asm_fprintf (asm_out_file, "\t.unwind_raw 0, 0x%x @ vsp = r%d\n",
18635 reg + 0x90, reg);
18636 }
1774763d 18637 else
18638 abort ();
18639 break;
18640
18641 default:
18642 abort ();
18643 }
18644}
18645
18646
18647/* Emit unwind directives for the given insn. */
18648
18649static void
18650arm_unwind_emit (FILE * asm_out_file, rtx insn)
18651{
18652 rtx pat;
18653
18654 if (!ARM_EABI_UNWIND_TABLES)
18655 return;
18656
18657 if (GET_CODE (insn) == NOTE || !RTX_FRAME_RELATED_P (insn))
18658 return;
18659
18660 pat = find_reg_note (insn, REG_FRAME_RELATED_EXPR, NULL_RTX);
18661 if (pat)
18662 pat = XEXP (pat, 0);
18663 else
18664 pat = PATTERN (insn);
18665
18666 switch (GET_CODE (pat))
18667 {
18668 case SET:
18669 arm_unwind_emit_set (asm_out_file, pat);
18670 break;
18671
18672 case SEQUENCE:
18673 /* Store multiple. */
25f905c2 18674 arm_unwind_emit_sequence (asm_out_file, pat);
1774763d 18675 break;
18676
18677 default:
18678 abort();
18679 }
18680}
18681
18682
18683/* Output a reference from a function exception table to the type_info
18684 object X. The EABI specifies that the symbol should be relocated by
18685 an R_ARM_TARGET2 relocation. */
18686
18687static bool
18688arm_output_ttype (rtx x)
18689{
18690 fputs ("\t.word\t", asm_out_file);
18691 output_addr_const (asm_out_file, x);
18692 /* Use special relocations for symbol references. */
18693 if (GET_CODE (x) != CONST_INT)
18694 fputs ("(TARGET2)", asm_out_file);
18695 fputc ('\n', asm_out_file);
18696
18697 return TRUE;
18698}
18699#endif /* TARGET_UNWIND_INFO */
18700
18701
25f905c2 18702/* Handle UNSPEC DWARF call frame instructions. These are needed for dynamic
18703 stack alignment. */
18704
18705static void
18706arm_dwarf_handle_frame_unspec (const char *label, rtx pattern, int index)
18707{
18708 rtx unspec = SET_SRC (pattern);
18709 gcc_assert (GET_CODE (unspec) == UNSPEC);
18710
18711 switch (index)
18712 {
18713 case UNSPEC_STACK_ALIGN:
18714 /* ??? We should set the CFA = (SP & ~7). At this point we haven't
18715 put anything on the stack, so hopefully it won't matter.
18716 CFA = SP will be correct after alignment. */
18717 dwarf2out_reg_save_reg (label, stack_pointer_rtx,
18718 SET_DEST (pattern));
18719 break;
18720 default:
18721 gcc_unreachable ();
18722 }
18723}
18724
18725
1774763d 18726/* Output unwind directives for the start/end of a function. */
18727
18728void
18729arm_output_fn_unwind (FILE * f, bool prologue)
18730{
18731 if (!ARM_EABI_UNWIND_TABLES)
18732 return;
18733
18734 if (prologue)
18735 fputs ("\t.fnstart\n", f);
18736 else
18737 fputs ("\t.fnend\n", f);
18738}
f655717d 18739
18740static bool
18741arm_emit_tls_decoration (FILE *fp, rtx x)
18742{
18743 enum tls_reloc reloc;
18744 rtx val;
18745
18746 val = XVECEXP (x, 0, 0);
18747 reloc = INTVAL (XVECEXP (x, 0, 1));
18748
18749 output_addr_const (fp, val);
18750
18751 switch (reloc)
18752 {
18753 case TLS_GD32:
18754 fputs ("(tlsgd)", fp);
18755 break;
18756 case TLS_LDM32:
18757 fputs ("(tlsldm)", fp);
18758 break;
18759 case TLS_LDO32:
18760 fputs ("(tlsldo)", fp);
18761 break;
18762 case TLS_IE32:
18763 fputs ("(gottpoff)", fp);
18764 break;
18765 case TLS_LE32:
18766 fputs ("(tpoff)", fp);
18767 break;
18768 default:
18769 gcc_unreachable ();
18770 }
18771
18772 switch (reloc)
18773 {
18774 case TLS_GD32:
18775 case TLS_LDM32:
18776 case TLS_IE32:
18777 fputs (" + (. - ", fp);
18778 output_addr_const (fp, XVECEXP (x, 0, 2));
18779 fputs (" - ", fp);
18780 output_addr_const (fp, XVECEXP (x, 0, 3));
18781 fputc (')', fp);
18782 break;
18783 default:
18784 break;
18785 }
18786
18787 return TRUE;
18788}
18789
4471a482 18790/* ARM implementation of TARGET_ASM_OUTPUT_DWARF_DTPREL. */
18791
18792static void
18793arm_output_dwarf_dtprel (FILE *file, int size, rtx x)
18794{
18795 gcc_assert (size == 4);
18796 fputs ("\t.word\t", file);
18797 output_addr_const (file, x);
18798 fputs ("(tlsldo)", file);
18799}
18800
f655717d 18801bool
18802arm_output_addr_const_extra (FILE *fp, rtx x)
18803{
18804 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLS)
18805 return arm_emit_tls_decoration (fp, x);
6cdcb15c 18806 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_PIC_LABEL)
18807 {
18808 char label[256];
18809 int labelno = INTVAL (XVECEXP (x, 0, 0));
18810
18811 ASM_GENERATE_INTERNAL_LABEL (label, "LPIC", labelno);
18812 assemble_name_raw (fp, label);
18813
18814 return TRUE;
18815 }
f655717d 18816 else if (GET_CODE (x) == CONST_VECTOR)
18817 return arm_emit_vector_const (fp, x);
18818
18819 return FALSE;
18820}
18821
25f905c2 18822/* Output assembly for a shift instruction.
18823 SET_FLAGS determines how the instruction modifies the condition codes.
542d5028 18824 0 - Do not set condition codes.
25f905c2 18825 1 - Set condition codes.
18826 2 - Use smallest instruction. */
18827const char *
18828arm_output_shift(rtx * operands, int set_flags)
18829{
18830 char pattern[100];
18831 static const char flag_chars[3] = {'?', '.', '!'};
18832 const char *shift;
18833 HOST_WIDE_INT val;
18834 char c;
18835
18836 c = flag_chars[set_flags];
18837 if (TARGET_UNIFIED_ASM)
18838 {
18839 shift = shift_op(operands[3], &val);
18840 if (shift)
18841 {
18842 if (val != -1)
18843 operands[2] = GEN_INT(val);
18844 sprintf (pattern, "%s%%%c\t%%0, %%1, %%2", shift, c);
18845 }
18846 else
18847 sprintf (pattern, "mov%%%c\t%%0, %%1", c);
18848 }
18849 else
18850 sprintf (pattern, "mov%%%c\t%%0, %%1%%S3", c);
18851 output_asm_insn (pattern, operands);
18852 return "";
18853}
18854
18855/* Output a Thumb-2 casesi instruction. */
18856const char *
18857thumb2_output_casesi (rtx *operands)
18858{
18859 rtx diff_vec = PATTERN (next_real_insn (operands[2]));
18860
18861 gcc_assert (GET_CODE (diff_vec) == ADDR_DIFF_VEC);
18862
18863 output_asm_insn ("cmp\t%0, %1", operands);
18864 output_asm_insn ("bhi\t%l3", operands);
18865 switch (GET_MODE(diff_vec))
18866 {
18867 case QImode:
18868 return "tbb\t[%|pc, %0]";
18869 case HImode:
18870 return "tbh\t[%|pc, %0, lsl #1]";
18871 case SImode:
18872 if (flag_pic)
18873 {
18874 output_asm_insn ("adr\t%4, %l2", operands);
18875 output_asm_insn ("ldr\t%5, [%4, %0, lsl #2]", operands);
18876 output_asm_insn ("add\t%4, %4, %5", operands);
18877 return "bx\t%4";
18878 }
18879 else
18880 {
18881 output_asm_insn ("adr\t%4, %l2", operands);
18882 return "ldr\t%|pc, [%4, %0, lsl #2]";
18883 }
18884 default:
18885 gcc_unreachable ();
18886 }
18887}
18888
eddcdde1 18889/* A table and a function to perform ARM-specific name mangling for
18890 NEON vector types in order to conform to the AAPCS (see "Procedure
18891 Call Standard for the ARM Architecture", Appendix A). To qualify
18892 for emission with the mangled names defined in that document, a
18893 vector type must not only be of the correct mode but also be
18894 composed of NEON vector element types (e.g. __builtin_neon_qi). */
18895typedef struct
18896{
18897 enum machine_mode mode;
18898 const char *element_type_name;
18899 const char *aapcs_name;
18900} arm_mangle_map_entry;
18901
18902static arm_mangle_map_entry arm_mangle_map[] = {
18903 /* 64-bit containerized types. */
18904 { V8QImode, "__builtin_neon_qi", "15__simd64_int8_t" },
18905 { V8QImode, "__builtin_neon_uqi", "16__simd64_uint8_t" },
18906 { V4HImode, "__builtin_neon_hi", "16__simd64_int16_t" },
18907 { V4HImode, "__builtin_neon_uhi", "17__simd64_uint16_t" },
18908 { V2SImode, "__builtin_neon_si", "16__simd64_int32_t" },
18909 { V2SImode, "__builtin_neon_usi", "17__simd64_uint32_t" },
18910 { V2SFmode, "__builtin_neon_sf", "18__simd64_float32_t" },
18911 { V8QImode, "__builtin_neon_poly8", "16__simd64_poly8_t" },
18912 { V4HImode, "__builtin_neon_poly16", "17__simd64_poly16_t" },
18913 /* 128-bit containerized types. */
18914 { V16QImode, "__builtin_neon_qi", "16__simd128_int8_t" },
18915 { V16QImode, "__builtin_neon_uqi", "17__simd128_uint8_t" },
18916 { V8HImode, "__builtin_neon_hi", "17__simd128_int16_t" },
18917 { V8HImode, "__builtin_neon_uhi", "18__simd128_uint16_t" },
18918 { V4SImode, "__builtin_neon_si", "17__simd128_int32_t" },
18919 { V4SImode, "__builtin_neon_usi", "18__simd128_uint32_t" },
18920 { V4SFmode, "__builtin_neon_sf", "19__simd128_float32_t" },
18921 { V16QImode, "__builtin_neon_poly8", "17__simd128_poly8_t" },
18922 { V8HImode, "__builtin_neon_poly16", "18__simd128_poly16_t" },
18923 { VOIDmode, NULL, NULL }
18924};
18925
18926const char *
18927arm_mangle_type (tree type)
18928{
18929 arm_mangle_map_entry *pos = arm_mangle_map;
18930
18931 if (TREE_CODE (type) != VECTOR_TYPE)
18932 return NULL;
18933
18934 /* Check the mode of the vector type, and the name of the vector
18935 element type, against the table. */
18936 while (pos->mode != VOIDmode)
18937 {
18938 tree elt_type = TREE_TYPE (type);
18939
18940 if (pos->mode == TYPE_MODE (type)
18941 && TREE_CODE (TYPE_NAME (elt_type)) == TYPE_DECL
18942 && !strcmp (IDENTIFIER_POINTER (DECL_NAME (TYPE_NAME (elt_type))),
18943 pos->element_type_name))
18944 return pos->aapcs_name;
18945
18946 pos++;
18947 }
18948
18949 /* Use the default mangling for unrecognized (possibly user-defined)
18950 vector types. */
18951 return NULL;
18952}
18953
f655717d 18954#include "gt-arm.h"
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