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[thirdparty/gcc.git] / gcc / config / arm / arm.h
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f5a1b0d2 1/* Definitions of target machine for GNU compiler, for ARM.
cf011243 2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
b12a00f1 3 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
35d965d5 4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
8b109b37 5 and Martin Simmons (@harleqn.co.uk).
949d79eb 6 More major hacks by Richard Earnshaw (rearnsha@arm.com)
6cfc7210
NC		 7 Minor hacks by Nick Clifton (nickc@cygnus.com)
8
4f448245 9 This file is part of GCC.
35d965d5 10
4f448245
NC		 11 GCC is free software; you can redistribute it and/or modify it
12 under the terms of the GNU General Public License as published
13 by the Free Software Foundation; either version 2, or (at your
14 option) any later version.
35d965d5 15
4f448245
NC		 16 GCC is distributed in the hope that it will be useful, but WITHOUT
17 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
18 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
19 License for more details.
35d965d5 20
4f448245
NC		 21 You should have received a copy of the GNU General Public License
22 along with GCC; see the file COPYING. If not, write to
23 the Free Software Foundation, 59 Temple Place - Suite 330, Boston,
24 MA 02111-1307, USA. */
35d965d5 25
88657302
RH		 26#ifndef GCC_ARM_H
27#define GCC_ARM_H
b355a481 28
35fd3193 29/* The architecture define. */
78011587
PB		 30extern char arm_arch_name[];
31
e6471be6
NB		 32/* Target CPU builtins. */
33#define TARGET_CPU_CPP_BUILTINS() \
34 do \
35 { \
9b66ebb1
PB		 36 /* Define __arm__ even when in thumb mode, for \
37 consistency with armcc. */ \
38 builtin_define ("__arm__"); \
61f0ccff 39 builtin_define ("__APCS_32__"); \
9b66ebb1 40 if (TARGET_THUMB) \
e6471be6
NB		 41 builtin_define ("__thumb__"); \
42 \
43 if (TARGET_BIG_END) \
44 { \
45 builtin_define ("__ARMEB__"); \
46 if (TARGET_THUMB) \
47 builtin_define ("__THUMBEB__"); \
48 if (TARGET_LITTLE_WORDS) \
49 builtin_define ("__ARMWEL__"); \
50 } \
51 else \
52 { \
53 builtin_define ("__ARMEL__"); \
54 if (TARGET_THUMB) \
55 builtin_define ("__THUMBEL__"); \
56 } \
57 \
e6471be6
NB		 58 if (TARGET_SOFT_FLOAT) \
59 builtin_define ("__SOFTFP__"); \
60 \
9b66ebb1 61 if (TARGET_VFP) \
b5b620a4
JT		 62 builtin_define ("__VFP_FP__"); \
63 \
e6471be6
NB		 64 /* Add a define for interworking. \
65 Needed when building libgcc.a. */ \
2ad4dcf9 66 if (arm_cpp_interwork) \
e6471be6
NB		 67 builtin_define ("__THUMB_INTERWORK__"); \
68 \
69 builtin_assert ("cpu=arm"); \
70 builtin_assert ("machine=arm"); \
78011587
PB		 71 \
72 builtin_define (arm_arch_name); \
73 if (arm_arch_cirrus) \
74 builtin_define ("__MAVERICK__"); \
75 if (arm_arch_xscale) \
76 builtin_define ("__XSCALE__"); \
77 if (arm_arch_iwmmxt) \
78 builtin_define ("__IWMMXT__"); \
4adf3e34
PB		 79 if (TARGET_AAPCS_BASED) \
80 builtin_define ("__ARM_EABI__"); \
e6471be6
NB		 81 } while (0)
82
9b66ebb1
PB		 83/* The various ARM cores. */
84enum processor_type
85{
d98a72fd
RE		 86#define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
87 IDENT,
9b66ebb1
PB		 88#include "arm-cores.def"
89#undef ARM_CORE
90 /* Used to indicate that no processor has been specified. */
91 arm_none
92};
93
78011587
PB		 94enum target_cpus
95{
d98a72fd
RE		 96#define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
97 TARGET_CPU_##IDENT,
78011587
PB		 98#include "arm-cores.def"
99#undef ARM_CORE
100 TARGET_CPU_generic
101};
102
9b66ebb1
PB		 103/* The processor for which instructions should be scheduled. */
104extern enum processor_type arm_tune;
105
d5b7b3ae 106typedef enum arm_cond_code
89c7ca52
RE		 107{
108 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC,
109 ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV
d5b7b3ae
RE		 110}
111arm_cc;
6cfc7210 112
d5b7b3ae 113extern arm_cc arm_current_cc;
ff9940b0 114
d5b7b3ae 115#define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1))
89c7ca52 116
6cfc7210
NC		 117extern int arm_target_label;
118extern int arm_ccfsm_state;
e2500fed 119extern GTY(()) rtx arm_target_insn;
d5b7b3ae 120/* Define the information needed to generate branch insns. This is
e2500fed
GK		 121 stored from the compare operation. */
122extern GTY(()) rtx arm_compare_op0;
123extern GTY(()) rtx arm_compare_op1;
d5b7b3ae 124/* The label of the current constant pool. */
e2500fed 125extern rtx pool_vector_label;
d5b7b3ae 126/* Set to 1 when a return insn is output, this means that the epilogue
d6b4baa4 127 is not needed. */
d5b7b3ae 128extern int return_used_this_function;
e2500fed
GK		 129/* Used to produce AOF syntax assembler. */
130extern GTY(()) rtx aof_pic_label;
35d965d5 131\f
d6b4baa4 132/* Just in case configure has failed to define anything. */
7a801826
RE		 133#ifndef TARGET_CPU_DEFAULT
134#define TARGET_CPU_DEFAULT TARGET_CPU_generic
135#endif
136
7a801826 137
5742588d 138#undef CPP_SPEC
78011587 139#define CPP_SPEC "%(subtarget_cpp_spec) \
e6471be6
NB		 140%{msoft-float:%{mhard-float: \
141 %e-msoft-float and -mhard_float may not be used together}} \
142%{mbig-endian:%{mlittle-endian: \
143 %e-mbig-endian and -mlittle-endian may not be used together}}"
7a801826 144
be393ecf 145#ifndef CC1_SPEC
dfa08768 146#define CC1_SPEC ""
be393ecf 147#endif
7a801826
RE		 148
149/* This macro defines names of additional specifications to put in the specs
150 that can be used in various specifications like CC1_SPEC. Its definition
151 is an initializer with a subgrouping for each command option.
152
153 Each subgrouping contains a string constant, that defines the
4f448245 154 specification name, and a string constant that used by the GCC driver
7a801826
RE		 155 program.
156
157 Do not define this macro if it does not need to do anything. */
158#define EXTRA_SPECS \
38fc909b 159 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
7a801826
RE		 160 SUBTARGET_EXTRA_SPECS
161
914a3b8c 162#ifndef SUBTARGET_EXTRA_SPECS
7a801826 163#define SUBTARGET_EXTRA_SPECS
914a3b8c
DM		 164#endif
165
6cfc7210 166#ifndef SUBTARGET_CPP_SPEC
38fc909b 167#define SUBTARGET_CPP_SPEC ""
6cfc7210 168#endif
35d965d5
RS		 169\f
170/* Run-time Target Specification. */
ff9940b0 171#ifndef TARGET_VERSION
6cfc7210 172#define TARGET_VERSION fputs (" (ARM/generic)", stderr);
ff9940b0 173#endif
35d965d5 174
9b66ebb1 175#define TARGET_SOFT_FLOAT (arm_float_abi == ARM_FLOAT_ABI_SOFT)
72cdc543
PB		 176/* Use hardware floating point instructions. */
177#define TARGET_HARD_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT)
178/* Use hardware floating point calling convention. */
179#define TARGET_HARD_FLOAT_ABI (arm_float_abi == ARM_FLOAT_ABI_HARD)
9b66ebb1
PB		 180#define TARGET_FPA (arm_fp_model == ARM_FP_MODEL_FPA)
181#define TARGET_MAVERICK (arm_fp_model == ARM_FP_MODEL_MAVERICK)
182#define TARGET_VFP (arm_fp_model == ARM_FP_MODEL_VFP)
5a9335ef
NC		 183#define TARGET_IWMMXT (arm_arch_iwmmxt)
184#define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_ARM)
5848830f 185#define TARGET_IWMMXT_ABI (TARGET_ARM && arm_abi == ARM_ABI_IWMMXT)
d5b7b3ae
RE		 186#define TARGET_ARM (! TARGET_THUMB)
187#define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */
c54c7322
RS		 188#define TARGET_BACKTRACE (leaf_function_p () \
189 ? TARGET_TPCS_LEAF_FRAME \
190 : TARGET_TPCS_FRAME)
fdd695fd 191#define TARGET_LDRD (arm_arch5e && ARM_DOUBLEWORD_ALIGN)
b6685939
PB		 192#define TARGET_AAPCS_BASED \
193 (arm_abi != ARM_ABI_APCS && arm_abi != ARM_ABI_ATPCS)
3ada8e17 194
b3f8d95d
MM		 195/* True iff the full BPABI is being used. If TARGET_BPABI is true,
196 then TARGET_AAPCS_BASED must be true -- but the converse does not
197 hold. TARGET_BPABI implies the use of the BPABI runtime library,
198 etc., in addition to just the AAPCS calling conventions. */
199#ifndef TARGET_BPABI
200#define TARGET_BPABI false
f676971a 201#endif
b3f8d95d 202
7816bea0
DJ		 203/* Support for a compile-time default CPU, et cetera. The rules are:
204 --with-arch is ignored if -march or -mcpu are specified.
205 --with-cpu is ignored if -march or -mcpu are specified, and is overridden
206 by --with-arch.
207 --with-tune is ignored if -mtune or -mcpu are specified (but not affected
208 by -march).
9b66ebb1
PB		 209 --with-float is ignored if -mhard-float, -msoft-float or -mfloat-abi are
210 specified.
5848830f
PB		 211 --with-fpu is ignored if -mfpu is specified.
212 --with-abi is ignored is -mabi is specified. */
7816bea0
DJ		 213#define OPTION_DEFAULT_SPECS \
214 {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \
215 {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \
216 {"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}" }, \
9b66ebb1
PB		 217 {"float", \
218 "%{!msoft-float:%{!mhard-float:%{!mfloat-abi=*:-mfloat-abi=%(VALUE)}}}" }, \
5848830f
PB		 219 {"fpu", "%{!mfpu=*:-mfpu=%(VALUE)}"}, \
220 {"abi", "%{!mabi=*:-mabi=%(VALUE)}"},
7816bea0 221
9b66ebb1
PB		 222/* Which floating point model to use. */
223enum arm_fp_model
224{
225 ARM_FP_MODEL_UNKNOWN,
226 /* FPA model (Hardware or software). */
227 ARM_FP_MODEL_FPA,
228 /* Cirrus Maverick floating point model. */
229 ARM_FP_MODEL_MAVERICK,
230 /* VFP floating point model. */
231 ARM_FP_MODEL_VFP
232};
233
234extern enum arm_fp_model arm_fp_model;
235
236/* Which floating point hardware is available. Also update
237 fp_model_for_fpu in arm.c when adding entries to this list. */
29ad9694 238enum fputype
24f0c1b4 239{
9b66ebb1
PB		 240 /* No FP hardware. */
241 FPUTYPE_NONE,
29ad9694
RE		 242 /* Full FPA support. */
243 FPUTYPE_FPA,
244 /* Emulated FPA hardware, Issue 2 emulator (no LFM/SFM). */
245 FPUTYPE_FPA_EMU2,
246 /* Emulated FPA hardware, Issue 3 emulator. */
247 FPUTYPE_FPA_EMU3,
248 /* Cirrus Maverick floating point co-processor. */
9b66ebb1
PB		 249 FPUTYPE_MAVERICK,
250 /* VFP. */
251 FPUTYPE_VFP
24f0c1b4
RE		 252};
253
254/* Recast the floating point class to be the floating point attribute. */
29ad9694 255#define arm_fpu_attr ((enum attr_fpu) arm_fpu_tune)
24f0c1b4 256
71791e16 257/* What type of floating point to tune for */
29ad9694 258extern enum fputype arm_fpu_tune;
24f0c1b4 259
71791e16 260/* What type of floating point instructions are available */
29ad9694 261extern enum fputype arm_fpu_arch;
71791e16 262
9b66ebb1
PB		 263enum float_abi_type
264{
265 ARM_FLOAT_ABI_SOFT,
266 ARM_FLOAT_ABI_SOFTFP,
267 ARM_FLOAT_ABI_HARD
268};
269
270extern enum float_abi_type arm_float_abi;
271
3d8532aa
PB		 272#ifndef TARGET_DEFAULT_FLOAT_ABI
273#define TARGET_DEFAULT_FLOAT_ABI ARM_FLOAT_ABI_SOFT
274#endif
275
5848830f
PB		 276/* Which ABI to use. */
277enum arm_abi_type
278{
279 ARM_ABI_APCS,
280 ARM_ABI_ATPCS,
281 ARM_ABI_AAPCS,
282 ARM_ABI_IWMMXT
283};
284
285extern enum arm_abi_type arm_abi;
286
287#ifndef ARM_DEFAULT_ABI
288#define ARM_DEFAULT_ABI ARM_ABI_APCS
289#endif
290
9b66ebb1
PB		 291/* Nonzero if this chip supports the ARM Architecture 3M extensions. */
292extern int arm_arch3m;
11c1a207 293
9b66ebb1 294/* Nonzero if this chip supports the ARM Architecture 4 extensions. */
11c1a207
RE		 295extern int arm_arch4;
296
68d560d4
RE		 297/* Nonzero if this chip supports the ARM Architecture 4T extensions. */
298extern int arm_arch4t;
299
9b66ebb1 300/* Nonzero if this chip supports the ARM Architecture 5 extensions. */
62b10bbc
NC		 301extern int arm_arch5;
302
9b66ebb1 303/* Nonzero if this chip supports the ARM Architecture 5E extensions. */
b15bca31
RE		 304extern int arm_arch5e;
305
9b66ebb1
PB		 306/* Nonzero if this chip supports the ARM Architecture 6 extensions. */
307extern int arm_arch6;
308
f5a1b0d2
NC		 309/* Nonzero if this chip can benefit from load scheduling. */
310extern int arm_ld_sched;
311
0616531f
RE		 312/* Nonzero if generating thumb code. */
313extern int thumb_code;
314
f5a1b0d2 315/* Nonzero if this chip is a StrongARM. */
abac3b49 316extern int arm_tune_strongarm;
f5a1b0d2 317
9b6b54e2 318/* Nonzero if this chip is a Cirrus variant. */
78011587 319extern int arm_arch_cirrus;
9b6b54e2 320
5a9335ef
NC		 321/* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */
322extern int arm_arch_iwmmxt;
323
d19fb8e3 324/* Nonzero if this chip is an XScale. */
4b3c2e48
PB		 325extern int arm_arch_xscale;
326
abac3b49 327/* Nonzero if tuning for XScale. */
4b3c2e48 328extern int arm_tune_xscale;
d19fb8e3 329
abac3b49
RE		 330/* Nonzero if tuning for stores via the write buffer. */
331extern int arm_tune_wbuf;
f5a1b0d2 332
2ad4dcf9 333/* Nonzero if we should define __THUMB_INTERWORK__ in the
f676971a 334 preprocessor.
2ad4dcf9
RE		 335 XXX This is a bit of a hack, it's intended to help work around
336 problems in GLD which doesn't understand that armv5t code is
337 interworking clean. */
338extern int arm_cpp_interwork;
339
2ce9c1b9 340#ifndef TARGET_DEFAULT
c54c7322 341#define TARGET_DEFAULT (MASK_APCS_FRAME)
2ce9c1b9 342#endif
35d965d5 343
11c1a207
RE		 344/* The frame pointer register used in gcc has nothing to do with debugging;
345 that is controlled by the APCS-FRAME option. */
d5b7b3ae 346#define CAN_DEBUG_WITHOUT_FP
35d965d5 347
11c1a207 348#define OVERRIDE_OPTIONS arm_override_options ()
86efdc8e
PB		 349
350/* Nonzero if PIC code requires explicit qualifiers to generate
351 PLT and GOT relocs rather than the assembler doing so implicitly.
ed0e6530
PB		 352 Subtargets can override these if required. */
353#ifndef NEED_GOT_RELOC
354#define NEED_GOT_RELOC 0
355#endif
356#ifndef NEED_PLT_RELOC
357#define NEED_PLT_RELOC 0
e2723c62 358#endif
84306176
PB		 359
360/* Nonzero if we need to refer to the GOT with a PC-relative
361 offset. In other words, generate
362
f676971a 363 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)]
84306176
PB		 364
365 rather than
366
367 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8)
368
f676971a 369 The default is true, which matches NetBSD. Subtargets can
84306176
PB		 370 override this if required. */
371#ifndef GOT_PCREL
372#define GOT_PCREL 1
373#endif
35d965d5
RS		 374\f
375/* Target machine storage Layout. */
376
ff9940b0
RE		 377
378/* Define this macro if it is advisable to hold scalars in registers
379 in a wider mode than that declared by the program. In such cases,
380 the value is constrained to be within the bounds of the declared
381 type, but kept valid in the wider mode. The signedness of the
382 extension may differ from that of the type. */
383
384/* It is far faster to zero extend chars than to sign extend them */
385
6cfc7210 386#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
2ce9c1b9
RE		 387 if (GET_MODE_CLASS (MODE) == MODE_INT \
388 && GET_MODE_SIZE (MODE) < 4) \
389 { \
390 if (MODE == QImode) \
391 UNSIGNEDP = 1; \
392 else if (MODE == HImode) \
61f0ccff 393 UNSIGNEDP = 1; \
2ce9c1b9 394 (MODE) = SImode; \
ff9940b0
RE		 395 }
396
d4453b7a 397#define PROMOTE_FUNCTION_MODE(MODE, UNSIGNEDP, TYPE) \
866af8a9
JB		 398 if ((GET_MODE_CLASS (MODE) == MODE_INT \
399 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_INT) \
400 && GET_MODE_SIZE (MODE) < 4) \
401 (MODE) = SImode; \
d4453b7a 402
35d965d5
RS		 403/* Define this if most significant bit is lowest numbered
404 in instructions that operate on numbered bit-fields. */
405#define BITS_BIG_ENDIAN 0
406
f676971a 407/* Define this if most significant byte of a word is the lowest numbered.
3ada8e17
DE		 408 Most ARM processors are run in little endian mode, so that is the default.
409 If you want to have it run-time selectable, change the definition in a
410 cover file to be TARGET_BIG_ENDIAN. */
11c1a207 411#define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
35d965d5
RS		 412
413/* Define this if most significant word of a multiword number is the lowest
11c1a207
RE		 414 numbered.
415 This is always false, even when in big-endian mode. */
ddee6aba
RE		 416#define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS)
417
418/* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based
419 on processor pre-defineds when compiling libgcc2.c. */
420#if defined(__ARMEB__) && !defined(__ARMWEL__)
421#define LIBGCC2_WORDS_BIG_ENDIAN 1
422#else
423#define LIBGCC2_WORDS_BIG_ENDIAN 0
424#endif
35d965d5 425
11c1a207 426/* Define this if most significant word of doubles is the lowest numbered.
f0375c66
NC		 427 The rules are different based on whether or not we use FPA-format,
428 VFP-format or some other floating point co-processor's format doubles. */
b5b620a4 429#define FLOAT_WORDS_BIG_ENDIAN (arm_float_words_big_endian ())
7fc6c9f0 430
35d965d5
RS		 431#define UNITS_PER_WORD 4
432
5848830f 433/* True if natural alignment is used for doubleword types. */
b6685939
PB		 434#define ARM_DOUBLEWORD_ALIGN TARGET_AAPCS_BASED
435
5848830f 436#define DOUBLEWORD_ALIGNMENT 64
35d965d5 437
5848830f 438#define PARM_BOUNDARY 32
5a9335ef 439
5848830f 440#define STACK_BOUNDARY (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
35d965d5 441
5848830f
PB		 442#define PREFERRED_STACK_BOUNDARY \
443 (arm_abi == ARM_ABI_ATPCS ? 64 : STACK_BOUNDARY)
0977774b 444
35d965d5
RS		 445#define FUNCTION_BOUNDARY 32
446
92928d71
AO		 447/* The lowest bit is used to indicate Thumb-mode functions, so the
448 vbit must go into the delta field of pointers to member
449 functions. */
450#define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
451
35d965d5
RS		 452#define EMPTY_FIELD_BOUNDARY 32
453
5848830f 454#define BIGGEST_ALIGNMENT (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
5a9335ef 455
27847754
NC		 456/* XXX Blah -- this macro is used directly by libobjc. Since it
457 supports no vector modes, cut out the complexity and fall back
458 on BIGGEST_FIELD_ALIGNMENT. */
459#ifdef IN_TARGET_LIBS
8fca31a2 460#define BIGGEST_FIELD_ALIGNMENT 64
27847754 461#endif
5a9335ef 462
ff9940b0 463/* Make strings word-aligned so strcpy from constants will be faster. */
591af218 464#define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_tune_xscale ? 1 : 2)
f676971a 465
d19fb8e3 466#define CONSTANT_ALIGNMENT(EXP, ALIGN) \
5848830f
PB		 467 ((TREE_CODE (EXP) == STRING_CST \
468 && (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \
469 ? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN))
ff9940b0 470
723ae7c1
NC		 471/* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the
472 value set in previous versions of this toolchain was 8, which produces more
473 compact structures. The command line option -mstructure_size_boundary=<n>
f710504c 474 can be used to change this value. For compatibility with the ARM SDK
723ae7c1 475 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI
5848830f
PB		 476 0020D) page 2-20 says "Structures are aligned on word boundaries".
477 The AAPCS specifies a value of 8. */
6ead9ba5
NC		 478#define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary
479extern int arm_structure_size_boundary;
723ae7c1 480
4912a07c 481/* This is the value used to initialize arm_structure_size_boundary. If a
723ae7c1 482 particular arm target wants to change the default value it should change
6bc82793 483 the definition of this macro, not STRUCTURE_SIZE_BOUNDARY. See netbsd.h
723ae7c1
NC		 484 for an example of this. */
485#ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY
486#define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32
b355a481 487#endif
2a5307b1 488
825dda42 489/* Nonzero if move instructions will actually fail to work
ff9940b0 490 when given unaligned data. */
35d965d5 491#define STRICT_ALIGNMENT 1
b6685939
PB		 492
493/* wchar_t is unsigned under the AAPCS. */
494#ifndef WCHAR_TYPE
495#define WCHAR_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "int")
496
497#define WCHAR_TYPE_SIZE BITS_PER_WORD
498#endif
499
500#ifndef SIZE_TYPE
501#define SIZE_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "long unsigned int")
502#endif
d81d0bdd
PB		 503
504/* AAPCS requires that structure alignment is affected by bitfields. */
505#ifndef PCC_BITFIELD_TYPE_MATTERS
506#define PCC_BITFIELD_TYPE_MATTERS TARGET_AAPCS_BASED
507#endif
508
35d965d5
RS		 509\f
510/* Standard register usage. */
511
512/* Register allocation in ARM Procedure Call Standard (as used on RISCiX):
513 (S - saved over call).
514
515 r0 * argument word/integer result
516 r1-r3 argument word
517
518 r4-r8 S register variable
519 r9 S (rfp) register variable (real frame pointer)
f676971a 520
f5a1b0d2 521 r10 F S (sl) stack limit (used by -mapcs-stack-check)
35d965d5
RS		 522 r11 F S (fp) argument pointer
523 r12 (ip) temp workspace
524 r13 F S (sp) lower end of current stack frame
525 r14 (lr) link address/workspace
526 r15 F (pc) program counter
527
528 f0 floating point result
529 f1-f3 floating point scratch
530
531 f4-f7 S floating point variable
532
ff9940b0
RE		 533 cc This is NOT a real register, but is used internally
534 to represent things that use or set the condition
535 codes.
536 sfp This isn't either. It is used during rtl generation
537 since the offset between the frame pointer and the
538 auto's isn't known until after register allocation.
539 afp Nor this, we only need this because of non-local
540 goto. Without it fp appears to be used and the
541 elimination code won't get rid of sfp. It tracks
542 fp exactly at all times.
543
35d965d5
RS		 544 *: See CONDITIONAL_REGISTER_USAGE */
545
9b6b54e2
NC		 546/*
547 mvf0 Cirrus floating point result
548 mvf1-mvf3 Cirrus floating point scratch
549 mvf4-mvf15 S Cirrus floating point variable. */
550
9b66ebb1
PB		 551/* s0-s15 VFP scratch (aka d0-d7).
552 s16-s31 S VFP variable (aka d8-d15).
553 vfpcc Not a real register. Represents the VFP condition
554 code flags. */
555
ff9940b0
RE		 556/* The stack backtrace structure is as follows:
557 fp points to here: | save code pointer | [fp]
558 | return link value | [fp, #-4]
559 | return sp value | [fp, #-8]
560 | return fp value | [fp, #-12]
561 [| saved r10 value |]
562 [| saved r9 value |]
563 [| saved r8 value |]
564 [| saved r7 value |]
565 [| saved r6 value |]
566 [| saved r5 value |]
567 [| saved r4 value |]
568 [| saved r3 value |]
569 [| saved r2 value |]
570 [| saved r1 value |]
571 [| saved r0 value |]
572 [| saved f7 value |] three words
573 [| saved f6 value |] three words
574 [| saved f5 value |] three words
575 [| saved f4 value |] three words
576 r0-r3 are not normally saved in a C function. */
577
35d965d5
RS		 578/* 1 for registers that have pervasive standard uses
579 and are not available for the register allocator. */
9b66ebb1
PB		 580#define FIXED_REGISTERS \
581{ \
582 0,0,0,0,0,0,0,0, \
583 0,0,0,0,0,1,0,1, \
584 0,0,0,0,0,0,0,0, \
9b6b54e2
NC		 585 1,1,1, \
586 1,1,1,1,1,1,1,1, \
9b66ebb1
PB		 587 1,1,1,1,1,1,1,1, \
588 1,1,1,1,1,1,1,1, \
589 1,1,1,1,1,1,1,1, \
590 1,1,1,1, \
591 1,1,1,1,1,1,1,1, \
592 1,1,1,1,1,1,1,1, \
593 1,1,1,1,1,1,1,1, \
594 1,1,1,1,1,1,1,1, \
595 1 \
35d965d5
RS		 596}
597
598/* 1 for registers not available across function calls.
599 These must include the FIXED_REGISTERS and also any
600 registers that can be used without being saved.
601 The latter must include the registers where values are returned
602 and the register where structure-value addresses are passed.
ff9940b0 603 Aside from that, you can include as many other registers as you like.
f676971a 604 The CC is not preserved over function calls on the ARM 6, so it is
d6b4baa4 605 easier to assume this for all. SFP is preserved, since FP is. */
35d965d5
RS		 606#define CALL_USED_REGISTERS \
607{ \
608 1,1,1,1,0,0,0,0, \
d5b7b3ae 609 0,0,0,0,1,1,1,1, \
ff9940b0 610 1,1,1,1,0,0,0,0, \
9b6b54e2
NC		 611 1,1,1, \
612 1,1,1,1,1,1,1,1, \
5a9335ef
NC		 613 1,1,1,1,1,1,1,1, \
614 1,1,1,1,1,1,1,1, \
615 1,1,1,1,1,1,1,1, \
9b66ebb1
PB		 616 1,1,1,1, \
617 1,1,1,1,1,1,1,1, \
618 1,1,1,1,1,1,1,1, \
619 1,1,1,1,1,1,1,1, \
620 1,1,1,1,1,1,1,1, \
621 1 \
35d965d5
RS		 622}
623
6cc8c0b3
NC		 624#ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE
625#define SUBTARGET_CONDITIONAL_REGISTER_USAGE
626#endif
627
d5b7b3ae
RE		 628#define CONDITIONAL_REGISTER_USAGE \
629{ \
4b02997f
NC		 630 int regno; \
631 \
9b66ebb1 632 if (TARGET_SOFT_FLOAT || TARGET_THUMB || !TARGET_FPA) \
d5b7b3ae 633 { \
9b66ebb1
PB		 634 for (regno = FIRST_FPA_REGNUM; \
635 regno <= LAST_FPA_REGNUM; ++regno) \
d5b7b3ae
RE		 636 fixed_regs[regno] = call_used_regs[regno] = 1; \
637 } \
9b6b54e2 638 \
c769a35d
RE		 639 if (TARGET_THUMB && optimize_size) \
640 { \
641 /* When optimizing for size, it's better not to use \
642 the HI regs, because of the overhead of stacking \
d6b4baa4 643 them. */ \
c769a35d
RE		 644 for (regno = FIRST_HI_REGNUM; \
645 regno <= LAST_HI_REGNUM; ++regno) \
646 fixed_regs[regno] = call_used_regs[regno] = 1; \
647 } \
648 \
fb14bc89
RE		 649 /* The link register can be clobbered by any branch insn, \
650 but we have no way to track that at present, so mark \
651 it as unavailable. */ \
652 if (TARGET_THUMB) \
653 fixed_regs[LR_REGNUM] = call_used_regs[LR_REGNUM] = 1; \
654 \
9b66ebb1 655 if (TARGET_ARM && TARGET_HARD_FLOAT) \
9b6b54e2 656 { \
9b66ebb1 657 if (TARGET_MAVERICK) \
9b6b54e2 658 { \
9b66ebb1
PB		 659 for (regno = FIRST_FPA_REGNUM; \
660 regno <= LAST_FPA_REGNUM; ++ regno) \
661 fixed_regs[regno] = call_used_regs[regno] = 1; \
662 for (regno = FIRST_CIRRUS_FP_REGNUM; \
663 regno <= LAST_CIRRUS_FP_REGNUM; ++ regno) \
664 { \
665 fixed_regs[regno] = 0; \
666 call_used_regs[regno] = regno < FIRST_CIRRUS_FP_REGNUM + 4; \
667 } \
668 } \
669 if (TARGET_VFP) \
670 { \
671 for (regno = FIRST_VFP_REGNUM; \
672 regno <= LAST_VFP_REGNUM; ++ regno) \
673 { \
674 fixed_regs[regno] = 0; \
675 call_used_regs[regno] = regno < FIRST_VFP_REGNUM + 16; \
676 } \
9b6b54e2
NC		 677 } \
678 } \
679 \
5a9335ef
NC		 680 if (TARGET_REALLY_IWMMXT) \
681 { \
682 regno = FIRST_IWMMXT_GR_REGNUM; \
683 /* The 2002/10/09 revision of the XScale ABI has wCG0 \
684 and wCG1 as call-preserved registers. The 2002/11/21 \
685 revision changed this so that all wCG registers are \
686 scratch registers. */ \
687 for (regno = FIRST_IWMMXT_GR_REGNUM; \
688 regno <= LAST_IWMMXT_GR_REGNUM; ++ regno) \
119bb233 689 fixed_regs[regno] = 0; \
5a9335ef
NC		 690 /* The XScale ABI has wR0 - wR9 as scratch registers, \
691 the rest as call-preserved registers. */ \
692 for (regno = FIRST_IWMMXT_REGNUM; \
693 regno <= LAST_IWMMXT_REGNUM; ++ regno) \
694 { \
695 fixed_regs[regno] = 0; \
696 call_used_regs[regno] = regno < FIRST_IWMMXT_REGNUM + 10; \
697 } \
698 } \
699 \
fc555370 700 if ((unsigned) PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
d5b7b3ae
RE		 701 { \
702 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
703 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
704 } \
705 else if (TARGET_APCS_STACK) \
706 { \
707 fixed_regs[10] = 1; \
708 call_used_regs[10] = 1; \
709 } \
a2503645
RS		 710 /* -mcaller-super-interworking reserves r11 for calls to \
711 _interwork_r11_call_via_rN(). Making the register global \
712 is an easy way of ensuring that it remains valid for all \
713 calls. */ \
685c9c11 714 if (TARGET_APCS_FRAME || TARGET_CALLER_INTERWORKING \
c54c7322 715 || TARGET_TPCS_FRAME || TARGET_TPCS_LEAF_FRAME) \
d5b7b3ae
RE		 716 { \
717 fixed_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
718 call_used_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
a2503645
RS		 719 if (TARGET_CALLER_INTERWORKING) \
720 global_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
d5b7b3ae
RE		 721 } \
722 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
35d965d5 723}
f676971a 724
6bc82793 725/* These are a couple of extensions to the formats accepted
dd18ae56
NC		 726 by asm_fprintf:
727 %@ prints out ASM_COMMENT_START
728 %r prints out REGISTER_PREFIX reg_names[arg] */
729#define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \
730 case '@': \
731 fputs (ASM_COMMENT_START, FILE); \
732 break; \
733 \
734 case 'r': \
735 fputs (REGISTER_PREFIX, FILE); \
736 fputs (reg_names [va_arg (ARGS, int)], FILE); \
737 break;
738
d5b7b3ae 739/* Round X up to the nearest word. */
0c2ca901 740#define ROUND_UP_WORD(X) (((X) + 3) & ~3)
d5b7b3ae 741
6cfc7210 742/* Convert fron bytes to ints. */
e9d7b180 743#define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
6cfc7210 744
9b66ebb1
PB		 745/* The number of (integer) registers required to hold a quantity of type MODE.
746 Also used for VFP registers. */
e9d7b180
JD		 747#define ARM_NUM_REGS(MODE) \
748 ARM_NUM_INTS (GET_MODE_SIZE (MODE))
6cfc7210
NC		 749
750/* The number of (integer) registers required to hold a quantity of TYPE MODE. */
e9d7b180
JD		 751#define ARM_NUM_REGS2(MODE, TYPE) \
752 ARM_NUM_INTS ((MODE) == BLKmode ? \
d5b7b3ae 753 int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE))
6cfc7210
NC		 754
755/* The number of (integer) argument register available. */
d5b7b3ae 756#define NUM_ARG_REGS 4
6cfc7210 757
093354e0 758/* Return the register number of the N'th (integer) argument. */
d5b7b3ae 759#define ARG_REGISTER(N) (N - 1)
6cfc7210 760
d5b7b3ae
RE		 761/* Specify the registers used for certain standard purposes.
762 The values of these macros are register numbers. */
35d965d5 763
d5b7b3ae
RE		 764/* The number of the last argument register. */
765#define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS)
35d965d5 766
c769a35d
RE		 767/* The numbers of the Thumb register ranges. */
768#define FIRST_LO_REGNUM 0
6d3d9133 769#define LAST_LO_REGNUM 7
c769a35d
RE		 770#define FIRST_HI_REGNUM 8
771#define LAST_HI_REGNUM 11
6d3d9133 772
c9ca9b88
PB		 773/* We use sjlj exceptions for backwards compatibility. */
774#define MUST_USE_SJLJ_EXCEPTIONS 1
775/* We can generate DWARF2 Unwind info, even though we don't use it. */
776#define DWARF2_UNWIND_INFO 1
f676971a 777
c9ca9b88
PB		 778/* Use r0 and r1 to pass exception handling information. */
779#define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? N : INVALID_REGNUM)
780
6d3d9133 781/* The register that holds the return address in exception handlers. */
c9ca9b88
PB		 782#define ARM_EH_STACKADJ_REGNUM 2
783#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (SImode, ARM_EH_STACKADJ_REGNUM)
35d965d5 784
d5b7b3ae
RE		 785/* The native (Norcroft) Pascal compiler for the ARM passes the static chain
786 as an invisible last argument (possible since varargs don't exist in
787 Pascal), so the following is not true. */
68dfd979 788#define STATIC_CHAIN_REGNUM (TARGET_ARM ? 12 : 9)
35d965d5 789
d5b7b3ae
RE		 790/* Define this to be where the real frame pointer is if it is not possible to
791 work out the offset between the frame pointer and the automatic variables
792 until after register allocation has taken place. FRAME_POINTER_REGNUM
793 should point to a special register that we will make sure is eliminated.
794
795 For the Thumb we have another problem. The TPCS defines the frame pointer
6bc82793 796 as r11, and GCC believes that it is always possible to use the frame pointer
d5b7b3ae
RE		 797 as base register for addressing purposes. (See comments in
798 find_reloads_address()). But - the Thumb does not allow high registers,
799 including r11, to be used as base address registers. Hence our problem.
800
801 The solution used here, and in the old thumb port is to use r7 instead of
802 r11 as the hard frame pointer and to have special code to generate
803 backtrace structures on the stack (if required to do so via a command line
6bc82793 804 option) using r11. This is the only 'user visible' use of r11 as a frame
d5b7b3ae
RE		 805 pointer. */
806#define ARM_HARD_FRAME_POINTER_REGNUM 11
807#define THUMB_HARD_FRAME_POINTER_REGNUM 7
35d965d5 808
b15bca31
RE		 809#define HARD_FRAME_POINTER_REGNUM \
810 (TARGET_ARM \
811 ? ARM_HARD_FRAME_POINTER_REGNUM \
812 : THUMB_HARD_FRAME_POINTER_REGNUM)
d5b7b3ae 813
b15bca31 814#define FP_REGNUM HARD_FRAME_POINTER_REGNUM
d5b7b3ae 815
b15bca31
RE		 816/* Register to use for pushing function arguments. */
817#define STACK_POINTER_REGNUM SP_REGNUM
d5b7b3ae
RE		 818
819/* ARM floating pointer registers. */
9b66ebb1
PB		 820#define FIRST_FPA_REGNUM 16
821#define LAST_FPA_REGNUM 23
2fa330b2
PB		 822#define IS_FPA_REGNUM(REGNUM) \
823 (((REGNUM) >= FIRST_FPA_REGNUM) && ((REGNUM) <= LAST_FPA_REGNUM))
d5b7b3ae 824
5a9335ef
NC		 825#define FIRST_IWMMXT_GR_REGNUM 43
826#define LAST_IWMMXT_GR_REGNUM 46
827#define FIRST_IWMMXT_REGNUM 47
828#define LAST_IWMMXT_REGNUM 62
829#define IS_IWMMXT_REGNUM(REGNUM) \
830 (((REGNUM) >= FIRST_IWMMXT_REGNUM) && ((REGNUM) <= LAST_IWMMXT_REGNUM))
831#define IS_IWMMXT_GR_REGNUM(REGNUM) \
832 (((REGNUM) >= FIRST_IWMMXT_GR_REGNUM) && ((REGNUM) <= LAST_IWMMXT_GR_REGNUM))
833
35d965d5 834/* Base register for access to local variables of the function. */
ff9940b0
RE		 835#define FRAME_POINTER_REGNUM 25
836
d5b7b3ae
RE		 837/* Base register for access to arguments of the function. */
838#define ARG_POINTER_REGNUM 26
62b10bbc 839
9b6b54e2
NC		 840#define FIRST_CIRRUS_FP_REGNUM 27
841#define LAST_CIRRUS_FP_REGNUM 42
842#define IS_CIRRUS_REGNUM(REGNUM) \
843 (((REGNUM) >= FIRST_CIRRUS_FP_REGNUM) && ((REGNUM) <= LAST_CIRRUS_FP_REGNUM))
844
9b66ebb1
PB		 845#define FIRST_VFP_REGNUM 63
846#define LAST_VFP_REGNUM 94
847#define IS_VFP_REGNUM(REGNUM) \
848 (((REGNUM) >= FIRST_VFP_REGNUM) && ((REGNUM) <= LAST_VFP_REGNUM))
849
6f8c9bd1
NC		 850/* The number of hard registers is 16 ARM + 8 FPA + 1 CC + 1 SFP + 1 AFP. */
851/* + 16 Cirrus registers take us up to 43. */
5a9335ef 852/* Intel Wireless MMX Technology registers add 16 + 4 more. */
9b66ebb1
PB		 853/* VFP adds 32 + 1 more. */
854#define FIRST_PSEUDO_REGISTER 96
62b10bbc 855
2fa330b2
PB		 856#define DBX_REGISTER_NUMBER(REGNO) arm_dbx_register_number (REGNO)
857
35d965d5
RS		 858/* Value should be nonzero if functions must have frame pointers.
859 Zero means the frame pointer need not be set up (and parms may be accessed
f676971a 860 via the stack pointer) in functions that seem suitable.
ff9940b0
RE		 861 If we have to have a frame pointer we might as well make use of it.
862 APCS says that the frame pointer does not need to be pushed in leaf
2a5307b1 863 functions, or simple tail call functions. */
7b8b8ade
NC		 864#define FRAME_POINTER_REQUIRED \
865 (current_function_has_nonlocal_label \
d5b7b3ae 866 || (TARGET_ARM && TARGET_APCS_FRAME && ! leaf_function_p ()))
35d965d5 867
d5b7b3ae
RE		 868/* Return number of consecutive hard regs needed starting at reg REGNO
869 to hold something of mode MODE.
870 This is ordinarily the length in words of a value of mode MODE
871 but can be less for certain modes in special long registers.
35d965d5 872
3b684012 873 On the ARM regs are UNITS_PER_WORD bits wide; FPA regs can hold any FP
d5b7b3ae
RE		 874 mode. */
875#define HARD_REGNO_NREGS(REGNO, MODE) \
876 ((TARGET_ARM \
9b66ebb1 877 && REGNO >= FIRST_FPA_REGNUM \
d5b7b3ae
RE		 878 && REGNO != FRAME_POINTER_REGNUM \
879 && REGNO != ARG_POINTER_REGNUM) \
9b66ebb1 880 && !IS_VFP_REGNUM (REGNO) \
e9d7b180 881 ? 1 : ARM_NUM_REGS (MODE))
35d965d5 882
4b02997f 883/* Return true if REGNO is suitable for holding a quantity of type MODE. */
d5b7b3ae 884#define HARD_REGNO_MODE_OK(REGNO, MODE) \
4b02997f 885 arm_hard_regno_mode_ok ((REGNO), (MODE))
35d965d5 886
d5b7b3ae
RE		 887/* Value is 1 if it is a good idea to tie two pseudo registers
888 when one has mode MODE1 and one has mode MODE2.
889 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
890 for any hard reg, then this must be 0 for correct output. */
891#define MODES_TIEABLE_P(MODE1, MODE2) \
892 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
ff9940b0 893
5a9335ef 894#define VALID_IWMMXT_REG_MODE(MODE) \
f676971a 895 (arm_vector_mode_supported_p (MODE) || (MODE) == DImode)
5a9335ef 896
35d965d5 897/* The order in which register should be allocated. It is good to use ip
ff9940b0
RE		 898 since no saving is required (though calls clobber it) and it never contains
899 function parameters. It is quite good to use lr since other calls may
f676971a 900 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is
ff9940b0 901 least likely to contain a function parameter; in addition results are
d5b7b3ae 902 returned in r0. */
9b66ebb1 903
ff73fb53 904#define REG_ALLOC_ORDER \
35d965d5 905{ \
ff73fb53
NC		 906 3, 2, 1, 0, 12, 14, 4, 5, \
907 6, 7, 8, 10, 9, 11, 13, 15, \
ff9940b0 908 16, 17, 18, 19, 20, 21, 22, 23, \
9b6b54e2
NC		 909 27, 28, 29, 30, 31, 32, 33, 34, \
910 35, 36, 37, 38, 39, 40, 41, 42, \
5a9335ef
NC		 911 43, 44, 45, 46, 47, 48, 49, 50, \
912 51, 52, 53, 54, 55, 56, 57, 58, \
913 59, 60, 61, 62, \
9b66ebb1
PB		 914 24, 25, 26, \
915 78, 77, 76, 75, 74, 73, 72, 71, \
916 70, 69, 68, 67, 66, 65, 64, 63, \
917 79, 80, 81, 82, 83, 84, 85, 86, \
918 87, 88, 89, 90, 91, 92, 93, 94, \
919 95 \
35d965d5 920}
9338ffe6
PB		 921
922/* Interrupt functions can only use registers that have already been
923 saved by the prologue, even if they would normally be
924 call-clobbered. */
925#define HARD_REGNO_RENAME_OK(SRC, DST) \
926 (! IS_INTERRUPT (cfun->machine->func_type) || \
927 regs_ever_live[DST])
35d965d5
RS		 928\f
929/* Register and constant classes. */
930
3b684012 931/* Register classes: used to be simple, just all ARM regs or all FPA regs
d6a7951f 932 Now that the Thumb is involved it has become more complicated. */
35d965d5
RS		 933enum reg_class
934{
935 NO_REGS,
3b684012 936 FPA_REGS,
9b6b54e2 937 CIRRUS_REGS,
9b66ebb1 938 VFP_REGS,
5a9335ef
NC		 939 IWMMXT_GR_REGS,
940 IWMMXT_REGS,
d5b7b3ae
RE		 941 LO_REGS,
942 STACK_REG,
943 BASE_REGS,
944 HI_REGS,
945 CC_REG,
9b66ebb1 946 VFPCC_REG,
35d965d5
RS		 947 GENERAL_REGS,
948 ALL_REGS,
949 LIM_REG_CLASSES
950};
951
952#define N_REG_CLASSES (int) LIM_REG_CLASSES
953
d6b4baa4 954/* Give names of register classes as strings for dump file. */
35d965d5
RS		 955#define REG_CLASS_NAMES \
956{ \
957 "NO_REGS", \
3b684012 958 "FPA_REGS", \
9b6b54e2 959 "CIRRUS_REGS", \
9b66ebb1 960 "VFP_REGS", \
5a9335ef
NC		 961 "IWMMXT_GR_REGS", \
962 "IWMMXT_REGS", \
d5b7b3ae
RE		 963 "LO_REGS", \
964 "STACK_REG", \
965 "BASE_REGS", \
966 "HI_REGS", \
967 "CC_REG", \
5384443a 968 "VFPCC_REG", \
35d965d5
RS		 969 "GENERAL_REGS", \
970 "ALL_REGS", \
971}
972
973/* Define which registers fit in which classes.
974 This is an initializer for a vector of HARD_REG_SET
975 of length N_REG_CLASSES. */
9b66ebb1
PB		 976#define REG_CLASS_CONTENTS \
977{ \
978 { 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
979 { 0x00FF0000, 0x00000000, 0x00000000 }, /* FPA_REGS */ \
980 { 0xF8000000, 0x000007FF, 0x00000000 }, /* CIRRUS_REGS */ \
981 { 0x00000000, 0x80000000, 0x7FFFFFFF }, /* VFP_REGS */ \
982 { 0x00000000, 0x00007800, 0x00000000 }, /* IWMMXT_GR_REGS */ \
983 { 0x00000000, 0x7FFF8000, 0x00000000 }, /* IWMMXT_REGS */ \
984 { 0x000000FF, 0x00000000, 0x00000000 }, /* LO_REGS */ \
985 { 0x00002000, 0x00000000, 0x00000000 }, /* STACK_REG */ \
986 { 0x000020FF, 0x00000000, 0x00000000 }, /* BASE_REGS */ \
987 { 0x0000FF00, 0x00000000, 0x00000000 }, /* HI_REGS */ \
988 { 0x01000000, 0x00000000, 0x00000000 }, /* CC_REG */ \
989 { 0x00000000, 0x00000000, 0x80000000 }, /* VFPCC_REG */ \
990 { 0x0200FFFF, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \
991 { 0xFAFFFFFF, 0xFFFFFFFF, 0x7FFFFFFF } /* ALL_REGS */ \
35d965d5 992}
4b02997f 993
35d965d5
RS		 994/* The same information, inverted:
995 Return the class number of the smallest class containing
996 reg number REGNO. This could be a conditional expression
997 or could index an array. */
d5b7b3ae 998#define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO)
35d965d5 999
9b66ebb1 1000/* FPA registers can't do subreg as all values are reformatted to internal
59b9a953 1001 precision. VFP registers may only be accessed in the mode they
9b66ebb1 1002 were set. */
75d2580c
RE		 1003#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1004 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
9b66ebb1
PB		 1005 ? reg_classes_intersect_p (FPA_REGS, (CLASS)) \
1006 || reg_classes_intersect_p (VFP_REGS, (CLASS)) \
1007 : 0)
75d2580c 1008
cc81dde8
PB		 1009/* We need to define this for LO_REGS on thumb. Otherwise we can end up
1010 using r0-r4 for function arguments, r7 for the stack frame and don't
1011 have enough left over to do doubleword arithmetic. */
1012#define CLASS_LIKELY_SPILLED_P(CLASS) \
1013 ((TARGET_THUMB && (CLASS) == LO_REGS) \
1014 || (CLASS) == CC_REG)
f676971a 1015
35d965d5 1016/* The class value for index registers, and the one for base regs. */
d5b7b3ae 1017#define INDEX_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS)
b93a0fe6 1018#define BASE_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS)
d5b7b3ae 1019
b93a0fe6 1020/* For the Thumb the high registers cannot be used as base registers
6bc82793 1021 when addressing quantities in QI or HI mode; if we don't know the
888d2cd6 1022 mode, then we must be conservative. */
3dcc68a4 1023#define MODE_BASE_REG_CLASS(MODE) \
b93a0fe6 1024 (TARGET_ARM ? GENERAL_REGS : \
888d2cd6
DJ		 1025 (((MODE) == SImode) ? BASE_REGS : LO_REGS))
1026
1027/* For Thumb we can not support SP+reg addressing, so we return LO_REGS
1028 instead of BASE_REGS. */
1029#define MODE_BASE_REG_REG_CLASS(MODE) BASE_REG_CLASS
3dcc68a4 1030
d5b7b3ae
RE		 1031/* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1032 registers explicitly used in the rtl to be used as spill registers
1033 but prevents the compiler from extending the lifetime of these
d6b4baa4 1034 registers. */
d5b7b3ae 1035#define SMALL_REGISTER_CLASSES TARGET_THUMB
35d965d5
RS		 1036
1037/* Get reg_class from a letter such as appears in the machine description.
3b684012 1038 We only need constraint `f' for FPA_REGS (`r' == GENERAL_REGS) for the
d5b7b3ae
RE		 1039 ARM, but several more letters for the Thumb. */
1040#define REG_CLASS_FROM_LETTER(C) \
3b684012 1041 ( (C) == 'f' ? FPA_REGS \
9b6b54e2 1042 : (C) == 'v' ? CIRRUS_REGS \
9b66ebb1 1043 : (C) == 'w' ? VFP_REGS \
5a9335ef
NC		 1044 : (C) == 'y' ? IWMMXT_REGS \
1045 : (C) == 'z' ? IWMMXT_GR_REGS \
d5b7b3ae
RE		 1046 : (C) == 'l' ? (TARGET_ARM ? GENERAL_REGS : LO_REGS) \
1047 : TARGET_ARM ? NO_REGS \
1048 : (C) == 'h' ? HI_REGS \
1049 : (C) == 'b' ? BASE_REGS \
1050 : (C) == 'k' ? STACK_REG \
1051 : (C) == 'c' ? CC_REG \
1052 : NO_REGS)
35d965d5
RS		 1053
1054/* The letters I, J, K, L and M in a register constraint string
1055 can be used to stand for particular ranges of immediate operands.
1056 This macro defines what the ranges are.
1057 C is the letter, and VALUE is a constant value.
1058 Return 1 if VALUE is in the range specified by C.
b4ac57ab 1059 I: immediate arithmetic operand (i.e. 8 bits shifted as required).
f676971a 1060 J: valid indexing constants.
aef1764c 1061 K: ~value ok in rhs argument of data operand.
f676971a 1062 L: -value ok in rhs argument of data operand.
3967692c 1063 M: 0..32, or a power of 2 (for shifts, or mult done by shift). */
d5b7b3ae 1064#define CONST_OK_FOR_ARM_LETTER(VALUE, C) \
aef1764c
RE		 1065 ((C) == 'I' ? const_ok_for_arm (VALUE) : \
1066 (C) == 'J' ? ((VALUE) < 4096 && (VALUE) > -4096) : \
1067 (C) == 'K' ? (const_ok_for_arm (~(VALUE))) : \
3967692c
RE		 1068 (C) == 'L' ? (const_ok_for_arm (-(VALUE))) : \
1069 (C) == 'M' ? (((VALUE >= 0 && VALUE <= 32)) \
1070 || (((VALUE) & ((VALUE) - 1)) == 0)) \
1071 : 0)
ff9940b0 1072
d5b7b3ae
RE		 1073#define CONST_OK_FOR_THUMB_LETTER(VAL, C) \
1074 ((C) == 'I' ? (unsigned HOST_WIDE_INT) (VAL) < 256 : \
1075 (C) == 'J' ? (VAL) > -256 && (VAL) < 0 : \
1076 (C) == 'K' ? thumb_shiftable_const (VAL) : \
1077 (C) == 'L' ? (VAL) > -8 && (VAL) < 8 : \
1078 (C) == 'M' ? ((unsigned HOST_WIDE_INT) (VAL) < 1024 \
1079 && ((VAL) & 3) == 0) : \
1080 (C) == 'N' ? ((unsigned HOST_WIDE_INT) (VAL) < 32) : \
1081 (C) == 'O' ? ((VAL) >= -508 && (VAL) <= 508) \
1082 : 0)
1083
1084#define CONST_OK_FOR_LETTER_P(VALUE, C) \
1085 (TARGET_ARM ? \
1086 CONST_OK_FOR_ARM_LETTER (VALUE, C) : CONST_OK_FOR_THUMB_LETTER (VALUE, C))
f676971a 1087
9b66ebb1 1088/* Constant letter 'G' for the FP immediate constants.
d5b7b3ae
RE		 1089 'H' means the same constant negated. */
1090#define CONST_DOUBLE_OK_FOR_ARM_LETTER(X, C) \
9b66ebb1 1091 ((C) == 'G' ? arm_const_double_rtx (X) : \
3b684012 1092 (C) == 'H' ? neg_const_double_rtx_ok_for_fpa (X) : 0)
d5b7b3ae
RE		 1093
1094#define CONST_DOUBLE_OK_FOR_LETTER_P(X, C) \
1095 (TARGET_ARM ? \
1096 CONST_DOUBLE_OK_FOR_ARM_LETTER (X, C) : 0)
1097
ff9940b0 1098/* For the ARM, `Q' means that this is a memory operand that is just
f676971a 1099 an offset from a register.
ff9940b0
RE		 1100 `S' means any symbol that has the SYMBOL_REF_FLAG set or a CONSTANT_POOL
1101 address. This means that the symbol is in the text segment and can be
9b66ebb1 1102 accessed without using a load.
2075b05d
RE		 1103 'D' Prefixes a number of const_double operands where:
1104 'Da' is a constant that takes two ARM insns to load.
1105 'Db' takes three ARM insns.
1106 'Dc' takes four ARM insns, if we allow that in this compilation.
edc62122 1107 'U' Prefixes an extended memory constraint where:
f676971a
EC		 1108 'Uv' is an address valid for VFP load/store insns.
1109 'Uy' is an address valid for iwmmxt load/store insns.
edc62122 1110 'Uq' is an address valid for ldrsb. */
ff9940b0 1111
2075b05d 1112#define EXTRA_CONSTRAINT_STR_ARM(OP, C, STR) \
9b901d50
RE		 1113 (((C) == 'D') ? ((GET_CODE (OP) == CONST_DOUBLE \
1114 || GET_CODE (OP) == CONST_INT \
1115 || GET_CODE (OP) == CONST_VECTOR) \
2075b05d
RE		 1116 && (((STR)[1] == 'a' \
1117 && arm_const_double_inline_cost (OP) == 2) \
1118 || ((STR)[1] == 'b' \
1119 && arm_const_double_inline_cost (OP) == 3) \
1120 || ((STR)[1] == 'c' \
1121 && arm_const_double_inline_cost (OP) == 4 \
1122 && !(optimize_size || arm_ld_sched)))) : \
1123 ((C) == 'Q') ? (GET_CODE (OP) == MEM \
1124 && GET_CODE (XEXP (OP, 0)) == REG) : \
1125 ((C) == 'R') ? (GET_CODE (OP) == MEM \
1126 && GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \
1127 && CONSTANT_POOL_ADDRESS_P (XEXP (OP, 0))) : \
1128 ((C) == 'S') ? (optimize > 0 && CONSTANT_ADDRESS_P (OP)) : \
1129 ((C) == 'T') ? cirrus_memory_offset (OP) : \
fdd695fd
PB		 1130 ((C) == 'U' && (STR)[1] == 'v') ? arm_coproc_mem_operand (OP, FALSE) : \
1131 ((C) == 'U' && (STR)[1] == 'y') ? arm_coproc_mem_operand (OP, TRUE) : \
2075b05d
RE		 1132 ((C) == 'U' && (STR)[1] == 'q') \
1133 ? arm_extendqisi_mem_op (OP, GET_MODE (OP)) \
1134 : 0)
1e1ab407
RE		 1135
1136#define CONSTRAINT_LEN(C,STR) \
2075b05d 1137 (((C) == 'U' || (C) == 'D') ? 2 : DEFAULT_CONSTRAINT_LEN (C, STR))
ff9940b0 1138
d5b7b3ae
RE		 1139#define EXTRA_CONSTRAINT_THUMB(X, C) \
1140 ((C) == 'Q' ? (GET_CODE (X) == MEM \
1141 && GET_CODE (XEXP (X, 0)) == LABEL_REF) : 0)
1142
1e1ab407
RE		 1143#define EXTRA_CONSTRAINT_STR(X, C, STR) \
1144 (TARGET_ARM \
1145 ? EXTRA_CONSTRAINT_STR_ARM (X, C, STR) \
1146 : EXTRA_CONSTRAINT_THUMB (X, C))
35d965d5 1147
9b66ebb1
PB		 1148#define EXTRA_MEMORY_CONSTRAINT(C, STR) ((C) == 'U')
1149
35d965d5
RS		 1150/* Given an rtx X being reloaded into a reg required to be
1151 in class CLASS, return the class of reg to actually use.
d5b7b3ae
RE		 1152 In general this is just CLASS, but for the Thumb we prefer
1153 a LO_REGS class or a subset. */
1154#define PREFERRED_RELOAD_CLASS(X, CLASS) \
1155 (TARGET_ARM ? (CLASS) : \
1156 ((CLASS) == BASE_REGS ? (CLASS) : LO_REGS))
1157
1158/* Must leave BASE_REGS reloads alone */
1159#define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1160 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1161 ? ((true_regnum (X) == -1 ? LO_REGS \
1162 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1163 : NO_REGS)) \
1164 : NO_REGS)
1165
1166#define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
97358092 1167 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
d5b7b3ae
RE		 1168 ? ((true_regnum (X) == -1 ? LO_REGS \
1169 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1170 : NO_REGS)) \
1171 : NO_REGS)
35d965d5 1172
ff9940b0
RE		 1173/* Return the register class of a scratch register needed to copy IN into
1174 or out of a register in CLASS in MODE. If it can be done directly,
1175 NO_REGS is returned. */
d5b7b3ae 1176#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
9b66ebb1
PB		 1177 /* Restrict which direct reloads are allowed for VFP regs. */ \
1178 ((TARGET_VFP && TARGET_HARD_FLOAT \
1179 && (CLASS) == VFP_REGS) \
1180 ? vfp_secondary_reload_class (MODE, X) \
1181 : TARGET_ARM \
1182 ? (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \
d5b7b3ae
RE		 1183 ? GENERAL_REGS : NO_REGS) \
1184 : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X))
f676971a 1185
d6b4baa4 1186/* If we need to load shorts byte-at-a-time, then we need a scratch. */
d5b7b3ae 1187#define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
9b66ebb1
PB		 1188 /* Restrict which direct reloads are allowed for VFP regs. */ \
1189 ((TARGET_VFP && TARGET_HARD_FLOAT \
1190 && (CLASS) == VFP_REGS) \
1191 ? vfp_secondary_reload_class (MODE, X) : \
9b6b54e2 1192 /* Cannot load constants into Cirrus registers. */ \
9b66ebb1 1193 (TARGET_MAVERICK && TARGET_HARD_FLOAT \
9b6b54e2
NC		 1194 && (CLASS) == CIRRUS_REGS \
1195 && (CONSTANT_P (X) || GET_CODE (X) == SYMBOL_REF)) \
1196 ? GENERAL_REGS : \
d5b7b3ae 1197 (TARGET_ARM ? \
5a9335ef
NC		 1198 (((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \
1199 && CONSTANT_P (X)) \
1200 ? GENERAL_REGS : \
61f0ccff 1201 (((MODE) == HImode && ! arm_arch4 \
d5b7b3ae
RE		 1202 && (GET_CODE (X) == MEM \
1203 || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \
1204 && true_regnum (X) == -1))) \
1205 ? GENERAL_REGS : NO_REGS) \
9b6b54e2 1206 : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X)))
2ce9c1b9 1207
6f734908
RE		 1208/* Try a machine-dependent way of reloading an illegitimate address
1209 operand. If we find one, push the reload and jump to WIN. This
1210 macro is used in only one place: `find_reloads_address' in reload.c.
1211
1212 For the ARM, we wish to handle large displacements off a base
1213 register by splitting the addend across a MOV and the mem insn.
d5b7b3ae
RE		 1214 This can cut the number of reloads needed. */
1215#define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN) \
1216 do \
1217 { \
1218 if (GET_CODE (X) == PLUS \
1219 && GET_CODE (XEXP (X, 0)) == REG \
1220 && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \
1221 && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \
1222 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1223 { \
1224 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1225 HOST_WIDE_INT low, high; \
1226 \
de6f27a8 1227 if (MODE == DImode || (MODE == DFmode && TARGET_SOFT_FLOAT)) \
d5b7b3ae 1228 low = ((val & 0xf) ^ 0x8) - 0x8; \
9b66ebb1 1229 else if (TARGET_MAVERICK && TARGET_HARD_FLOAT) \
9b6b54e2
NC		 1230 /* Need to be careful, -256 is not a valid offset. */ \
1231 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
d5b7b3ae 1232 else if (MODE == SImode \
de6f27a8 1233 || (MODE == SFmode && TARGET_SOFT_FLOAT) \
d5b7b3ae
RE		 1234 || ((MODE == HImode || MODE == QImode) && ! arm_arch4)) \
1235 /* Need to be careful, -4096 is not a valid offset. */ \
1236 low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff); \
1237 else if ((MODE == HImode || MODE == QImode) && arm_arch4) \
1238 /* Need to be careful, -256 is not a valid offset. */ \
1239 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1240 else if (GET_MODE_CLASS (MODE) == MODE_FLOAT \
9b66ebb1 1241 && TARGET_HARD_FLOAT && TARGET_FPA) \
d5b7b3ae
RE		 1242 /* Need to be careful, -1024 is not a valid offset. */ \
1243 low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \
1244 else \
1245 break; \
1246 \
30cf4896
KG		 1247 high = ((((val - low) & (unsigned HOST_WIDE_INT) 0xffffffff) \
1248 ^ (unsigned HOST_WIDE_INT) 0x80000000) \
1249 - (unsigned HOST_WIDE_INT) 0x80000000); \
d5b7b3ae
RE		 1250 /* Check for overflow or zero */ \
1251 if (low == 0 || high == 0 || (high + low != val)) \
1252 break; \
1253 \
1254 /* Reload the high part into a base reg; leave the low part \
1255 in the mem. */ \
1256 X = gen_rtx_PLUS (GET_MODE (X), \
1257 gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \
1258 GEN_INT (high)), \
1259 GEN_INT (low)); \
df4ae160 1260 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
4a692617
NC		 1261 MODE_BASE_REG_CLASS (MODE), GET_MODE (X), \
1262 VOIDmode, 0, 0, OPNUM, TYPE); \
d5b7b3ae
RE		 1263 goto WIN; \
1264 } \
1265 } \
62b10bbc 1266 while (0)
6f734908 1267
27847754 1268/* XXX If an HImode FP+large_offset address is converted to an HImode
d5b7b3ae
RE		 1269 SP+large_offset address, then reload won't know how to fix it. It sees
1270 only that SP isn't valid for HImode, and so reloads the SP into an index
1271 register, but the resulting address is still invalid because the offset
1272 is too big. We fix it here instead by reloading the entire address. */
1273/* We could probably achieve better results by defining PROMOTE_MODE to help
1274 cope with the variances between the Thumb's signed and unsigned byte and
1275 halfword load instructions. */
1276#define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1277{ \
1278 if (GET_CODE (X) == PLUS \
1279 && GET_MODE_SIZE (MODE) < 4 \
1280 && GET_CODE (XEXP (X, 0)) == REG \
1281 && XEXP (X, 0) == stack_pointer_rtx \
1282 && GET_CODE (XEXP (X, 1)) == CONST_INT \
76a318e9 1283 && ! thumb_legitimate_offset_p (MODE, INTVAL (XEXP (X, 1)))) \
d5b7b3ae
RE		 1284 { \
1285 rtx orig_X = X; \
1286 X = copy_rtx (X); \
df4ae160 1287 push_reload (orig_X, NULL_RTX, &X, NULL, \
4a692617 1288 MODE_BASE_REG_CLASS (MODE), \
d5b7b3ae
RE		 1289 Pmode, VOIDmode, 0, 0, OPNUM, TYPE); \
1290 goto WIN; \
1291 } \
1292}
1293
1294#define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1295 if (TARGET_ARM) \
1296 ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \
1297 else \
1298 THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN)
f676971a 1299
35d965d5
RS		 1300/* Return the maximum number of consecutive registers
1301 needed to represent mode MODE in a register of class CLASS.
3b684012 1302 ARM regs are UNITS_PER_WORD bits while FPA regs can hold any FP mode */
35d965d5 1303#define CLASS_MAX_NREGS(CLASS, MODE) \
3b684012 1304 (((CLASS) == FPA_REGS || (CLASS) == CIRRUS_REGS) ? 1 : ARM_NUM_REGS (MODE))
9b6b54e2
NC		 1305
1306/* If defined, gives a class of registers that cannot be used as the
1307 operand of a SUBREG that changes the mode of the object illegally. */
35d965d5 1308
3b684012 1309/* Moves between FPA_REGS and GENERAL_REGS are two memory insns. */
cf011243 1310#define REGISTER_MOVE_COST(MODE, FROM, TO) \
d5b7b3ae 1311 (TARGET_ARM ? \
3b684012
RE		 1312 ((FROM) == FPA_REGS && (TO) != FPA_REGS ? 20 : \
1313 (FROM) != FPA_REGS && (TO) == FPA_REGS ? 20 : \
9b66ebb1
PB		 1314 (FROM) == VFP_REGS && (TO) != VFP_REGS ? 10 : \
1315 (FROM) != VFP_REGS && (TO) == VFP_REGS ? 10 : \
5a9335ef
NC		 1316 (FROM) == IWMMXT_REGS && (TO) != IWMMXT_REGS ? 4 : \
1317 (FROM) != IWMMXT_REGS && (TO) == IWMMXT_REGS ? 4 : \
1318 (FROM) == IWMMXT_GR_REGS || (TO) == IWMMXT_GR_REGS ? 20 : \
9b6b54e2
NC		 1319 (FROM) == CIRRUS_REGS && (TO) != CIRRUS_REGS ? 20 : \
1320 (FROM) != CIRRUS_REGS && (TO) == CIRRUS_REGS ? 20 : \
1321 2) \
d5b7b3ae
RE		 1322 : \
1323 ((FROM) == HI_REGS || (TO) == HI_REGS) ? 4 : 2)
35d965d5
RS		 1324\f
1325/* Stack layout; function entry, exit and calling. */
1326
1327/* Define this if pushing a word on the stack
1328 makes the stack pointer a smaller address. */
1329#define STACK_GROWS_DOWNWARD 1
1330
1331/* Define this if the nominal address of the stack frame
1332 is at the high-address end of the local variables;
1333 that is, each additional local variable allocated
1334 goes at a more negative offset in the frame. */
1335#define FRAME_GROWS_DOWNWARD 1
1336
a2503645
RS		 1337/* The amount of scratch space needed by _interwork_{r7,r11}_call_via_rN().
1338 When present, it is one word in size, and sits at the top of the frame,
1339 between the soft frame pointer and either r7 or r11.
1340
1341 We only need _interwork_rM_call_via_rN() for -mcaller-super-interworking,
1342 and only then if some outgoing arguments are passed on the stack. It would
1343 be tempting to also check whether the stack arguments are passed by indirect
1344 calls, but there seems to be no reason in principle why a post-reload pass
1345 couldn't convert a direct call into an indirect one. */
1346#define CALLER_INTERWORKING_SLOT_SIZE \
1347 (TARGET_CALLER_INTERWORKING \
1348 && current_function_outgoing_args_size != 0 \
1349 ? UNITS_PER_WORD : 0)
1350
35d965d5
RS		 1351/* Offset within stack frame to start allocating local variables at.
1352 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1353 first local allocated. Otherwise, it is the offset to the BEGINNING
1354 of the first local allocated. */
1355#define STARTING_FRAME_OFFSET 0
1356
1357/* If we generate an insn to push BYTES bytes,
1358 this says how many the stack pointer really advances by. */
d5b7b3ae 1359/* The push insns do not do this rounding implicitly.
d6b4baa4 1360 So don't define this. */
0c2ca901 1361/* #define PUSH_ROUNDING(NPUSHED) ROUND_UP_WORD (NPUSHED) */
18543a22
ILT		 1362
1363/* Define this if the maximum size of all the outgoing args is to be
1364 accumulated and pushed during the prologue. The amount can be
1365 found in the variable current_function_outgoing_args_size. */
6cfc7210 1366#define ACCUMULATE_OUTGOING_ARGS 1
35d965d5
RS		 1367
1368/* Offset of first parameter from the argument pointer register value. */
d5b7b3ae 1369#define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0)
35d965d5
RS		 1370
1371/* Value is the number of byte of arguments automatically
1372 popped when returning from a subroutine call.
8b109b37 1373 FUNDECL is the declaration node of the function (as a tree),
35d965d5
RS		 1374 FUNTYPE is the data type of the function (as a tree),
1375 or for a library call it is an identifier node for the subroutine name.
1376 SIZE is the number of bytes of arguments passed on the stack.
1377
1378 On the ARM, the caller does not pop any of its arguments that were passed
1379 on the stack. */
6cfc7210 1380#define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0
35d965d5
RS		 1381
1382/* Define how to find the value returned by a library function
1383 assuming the value has mode MODE. */
1384#define LIBCALL_VALUE(MODE) \
72cdc543 1385 (TARGET_ARM && TARGET_HARD_FLOAT_ABI && TARGET_FPA \
9b66ebb1
PB		 1386 && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1387 ? gen_rtx_REG (MODE, FIRST_FPA_REGNUM) \
72cdc543 1388 : TARGET_ARM && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK \
9b66ebb1 1389 && GET_MODE_CLASS (MODE) == MODE_FLOAT \
9b6b54e2 1390 ? gen_rtx_REG (MODE, FIRST_CIRRUS_FP_REGNUM) \
f676971a 1391 : TARGET_IWMMXT_ABI && arm_vector_mode_supported_p (MODE) \
5a9335ef 1392 ? gen_rtx_REG (MODE, FIRST_IWMMXT_REGNUM) \
d5b7b3ae 1393 : gen_rtx_REG (MODE, ARG_REGISTER (1)))
35d965d5 1394
6cfc7210
NC		 1395/* Define how to find the value returned by a function.
1396 VALTYPE is the data type of the value (as a tree).
1397 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1398 otherwise, FUNC is 0. */
d5b7b3ae 1399#define FUNCTION_VALUE(VALTYPE, FUNC) \
d4453b7a 1400 arm_function_value (VALTYPE, FUNC);
6cfc7210 1401
35d965d5
RS		 1402/* 1 if N is a possible register number for a function value.
1403 On the ARM, only r0 and f0 can return results. */
9b6b54e2 1404/* On a Cirrus chip, mvf0 can return results. */
35d965d5 1405#define FUNCTION_VALUE_REGNO_P(REGNO) \
d5b7b3ae 1406 ((REGNO) == ARG_REGISTER (1) \
9b66ebb1 1407 || (TARGET_ARM && ((REGNO) == FIRST_CIRRUS_FP_REGNUM) \
72cdc543 1408 && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK) \
5848830f 1409 || ((REGNO) == FIRST_IWMMXT_REGNUM && TARGET_IWMMXT_ABI) \
9b66ebb1 1410 || (TARGET_ARM && ((REGNO) == FIRST_FPA_REGNUM) \
72cdc543 1411 && TARGET_HARD_FLOAT_ABI && TARGET_FPA))
35d965d5 1412
9f7bf991
RE		 1413/* Amount of memory needed for an untyped call to save all possible return
1414 registers. */
1415#define APPLY_RESULT_SIZE arm_apply_result_size()
1416
11c1a207
RE		 1417/* How large values are returned */
1418/* A C expression which can inhibit the returning of certain function values
d6b4baa4 1419 in registers, based on the type of value. */
f5a1b0d2 1420#define RETURN_IN_MEMORY(TYPE) arm_return_in_memory (TYPE)
11c1a207
RE		 1421
1422/* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return
1423 values must be in memory. On the ARM, they need only do so if larger
d6b4baa4 1424 than a word, or if they contain elements offset from zero in the struct. */
11c1a207
RE		 1425#define DEFAULT_PCC_STRUCT_RETURN 0
1426
d5b7b3ae
RE		 1427/* Flags for the call/call_value rtl operations set up by function_arg. */
1428#define CALL_NORMAL 0x00000000 /* No special processing. */
1429#define CALL_LONG 0x00000001 /* Always call indirect. */
1430#define CALL_SHORT 0x00000002 /* Never call indirect. */
1431
6d3d9133 1432/* These bits describe the different types of function supported
112cdef5 1433 by the ARM backend. They are exclusive. i.e. a function cannot be both a
6d3d9133
NC		 1434 normal function and an interworked function, for example. Knowing the
1435 type of a function is important for determining its prologue and
1436 epilogue sequences.
1437 Note value 7 is currently unassigned. Also note that the interrupt
1438 function types all have bit 2 set, so that they can be tested for easily.
1439 Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the
4912a07c 1440 machine_function structure is initialized (to zero) func_type will
6d3d9133
NC		 1441 default to unknown. This will force the first use of arm_current_func_type
1442 to call arm_compute_func_type. */
1443#define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */
1444#define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */
1445#define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */
6d3d9133
NC		 1446#define ARM_FT_ISR 4 /* An interrupt service routine. */
1447#define ARM_FT_FIQ 5 /* A fast interrupt service routine. */
1448#define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */
1449
1450#define ARM_FT_TYPE_MASK ((1 << 3) - 1)
1451
1452/* In addition functions can have several type modifiers,
1453 outlined by these bit masks: */
1454#define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */
1455#define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */
1456#define ARM_FT_VOLATILE (1 << 4) /* Does not return. */
d6b4baa4 1457#define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */
6d3d9133
NC		 1458
1459/* Some macros to test these flags. */
1460#define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK)
1461#define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT)
1462#define IS_VOLATILE(t) (t & ARM_FT_VOLATILE)
1463#define IS_NAKED(t) (t & ARM_FT_NAKED)
1464#define IS_NESTED(t) (t & ARM_FT_NESTED)
1465
5848830f
PB		 1466
1467/* Structure used to hold the function stack frame layout. Offsets are
1468 relative to the stack pointer on function entry. Positive offsets are
1469 in the direction of stack growth.
1470 Only soft_frame is used in thumb mode. */
1471
1472typedef struct arm_stack_offsets GTY(())
1473{
1474 int saved_args; /* ARG_POINTER_REGNUM. */
1475 int frame; /* ARM_HARD_FRAME_POINTER_REGNUM. */
1476 int saved_regs;
1477 int soft_frame; /* FRAME_POINTER_REGNUM. */
1478 int outgoing_args; /* STACK_POINTER_REGNUM. */
1479}
1480arm_stack_offsets;
1481
6d3d9133
NC		 1482/* A C structure for machine-specific, per-function data.
1483 This is added to the cfun structure. */
e2500fed 1484typedef struct machine_function GTY(())
d5b7b3ae 1485{
6bc82793 1486 /* Additional stack adjustment in __builtin_eh_throw. */
e2500fed 1487 rtx eh_epilogue_sp_ofs;
d5b7b3ae
RE		 1488 /* Records if LR has to be saved for far jumps. */
1489 int far_jump_used;
1490 /* Records if ARG_POINTER was ever live. */
1491 int arg_pointer_live;
6f7ebcbb
NC		 1492 /* Records if the save of LR has been eliminated. */
1493 int lr_save_eliminated;
0977774b 1494 /* The size of the stack frame. Only valid after reload. */
5848830f 1495 arm_stack_offsets stack_offsets;
6d3d9133
NC		 1496 /* Records the type of the current function. */
1497 unsigned long func_type;
3cb66fd7
NC		 1498 /* Record if the function has a variable argument list. */
1499 int uses_anonymous_args;
5a9335ef
NC		 1500 /* Records if sibcalls are blocked because an argument
1501 register is needed to preserve stack alignment. */
1502 int sibcall_blocked;
b12a00f1 1503 /* Labels for per-function Thumb call-via stubs. One per potential calling
57ecec57
PB		 1504 register. We can never call via LR or PC. We can call via SP if a
1505 trampoline happens to be on the top of the stack. */
1506 rtx call_via[14];
6d3d9133
NC		 1507}
1508machine_function;
d5b7b3ae 1509
b12a00f1
RE		 1510/* As in the machine_function, a global set of call-via labels, for code
1511 that is in text_section(). */
57ecec57 1512extern GTY(()) rtx thumb_call_via_label[14];
b12a00f1 1513
82e9d970
PB		 1514/* A C type for declaring a variable that is used as the first argument of
1515 `FUNCTION_ARG' and other related values. For some target machines, the
1516 type `int' suffices and can hold the number of bytes of argument so far. */
1517typedef struct
1518{
d5b7b3ae 1519 /* This is the number of registers of arguments scanned so far. */
82e9d970 1520 int nregs;
5a9335ef
NC		 1521 /* This is the number of iWMMXt register arguments scanned so far. */
1522 int iwmmxt_nregs;
1523 int named_count;
1524 int nargs;
d6b4baa4 1525 /* One of CALL_NORMAL, CALL_LONG or CALL_SHORT. */
82e9d970 1526 int call_cookie;
5848830f 1527 int can_split;
d5b7b3ae 1528} CUMULATIVE_ARGS;
82e9d970 1529
35d965d5
RS		 1530/* Define where to put the arguments to a function.
1531 Value is zero to push the argument on the stack,
1532 or a hard register in which to store the argument.
1533
1534 MODE is the argument's machine mode.
1535 TYPE is the data type of the argument (as a tree).
1536 This is null for libcalls where that information may
1537 not be available.
1538 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1539 the preceding args and about the function being called.
1540 NAMED is nonzero if this argument is a named parameter
1541 (otherwise it is an extra parameter matching an ellipsis).
1542
1543 On the ARM, normally the first 16 bytes are passed in registers r0-r3; all
1544 other arguments are passed on the stack. If (NAMED == 0) (which happens
1cc9f5f5
KH		 1545 only in assign_parms, since TARGET_SETUP_INCOMING_VARARGS is
1546 defined), say it is passed in the stack (function_prologue will
1547 indeed make it pass in the stack if necessary). */
82e9d970
PB		 1548#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1549 arm_function_arg (&(CUM), (MODE), (TYPE), (NAMED))
35d965d5 1550
866af8a9
JB		 1551#define FUNCTION_ARG_PADDING(MODE, TYPE) \
1552 (arm_pad_arg_upward (MODE, TYPE) ? upward : downward)
1553
1554#define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
1555 (arm_pad_reg_upward (MODE, TYPE, FIRST) ? upward : downward)
1556
1557/* For AAPCS, padding should never be below the argument. For other ABIs,
1558 * mimic the default. */
1559#define PAD_VARARGS_DOWN \
1560 ((TARGET_AAPCS_BASED) ? 0 : BYTES_BIG_ENDIAN)
1561
35d965d5
RS		 1562/* Initialize a variable CUM of type CUMULATIVE_ARGS
1563 for a call to a function whose data type is FNTYPE.
1564 For a library call, FNTYPE is 0.
1565 On the ARM, the offset starts at 0. */
0f6937fe 1566#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
563a317a 1567 arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL))
35d965d5
RS		 1568
1569/* Update the data in CUM to advance over an argument
1570 of mode MODE and data type TYPE.
1571 (TYPE is null for libcalls where that information may not be available.) */
6cfc7210 1572#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
5a9335ef 1573 (CUM).nargs += 1; \
f676971a 1574 if (arm_vector_mode_supported_p (MODE) \
5848830f
PB		 1575 && (CUM).named_count > (CUM).nargs) \
1576 (CUM).iwmmxt_nregs += 1; \
5a9335ef 1577 else \
5848830f 1578 (CUM).nregs += ARM_NUM_REGS2 (MODE, TYPE)
35d965d5 1579
5a9335ef
NC		 1580/* If defined, a C expression that gives the alignment boundary, in bits, of an
1581 argument with the specified mode and type. If it is not defined,
1582 `PARM_BOUNDARY' is used for all arguments. */
1583#define FUNCTION_ARG_BOUNDARY(MODE,TYPE) \
5848830f
PB		 1584 ((ARM_DOUBLEWORD_ALIGN && arm_needs_doubleword_align (MODE, TYPE)) \
1585 ? DOUBLEWORD_ALIGNMENT \
1586 : PARM_BOUNDARY )
5a9335ef 1587
35d965d5
RS		 1588/* 1 if N is a possible register number for function argument passing.
1589 On the ARM, r0-r3 are used to pass args. */
5a9335ef
NC		 1590#define FUNCTION_ARG_REGNO_P(REGNO) \
1591 (IN_RANGE ((REGNO), 0, 3) \
5848830f
PB		 1592 || (TARGET_IWMMXT_ABI \
1593 && IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9)))
35d965d5 1594
f99fce0c 1595\f
afef3d7a
NC		 1596/* If your target environment doesn't prefix user functions with an
1597 underscore, you may wish to re-define this to prevent any conflicts.
1598 e.g. AOF may prefix mcount with an underscore. */
1599#ifndef ARM_MCOUNT_NAME
1600#define ARM_MCOUNT_NAME "*mcount"
1601#endif
1602
1603/* Call the function profiler with a given profile label. The Acorn
1604 compiler puts this BEFORE the prolog but gcc puts it afterwards.
1605 On the ARM the full profile code will look like:
1606 .data
1607 LP1
1608 .word 0
1609 .text
1610 mov ip, lr
1611 bl mcount
1612 .word LP1
1613
1614 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER
1615 will output the .text section.
1616
1617 The ``mov ip,lr'' seems like a good idea to stick with cc convention.
59be6073
AN		 1618 ``prof'' doesn't seem to mind about this!
1619
1620 Note - this version of the code is designed to work in both ARM and
1621 Thumb modes. */
be393ecf 1622#ifndef ARM_FUNCTION_PROFILER
d5b7b3ae 1623#define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \
6cfc7210
NC		 1624{ \
1625 char temp[20]; \
1626 rtx sym; \
1627 \
dd18ae56 1628 asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \
d5b7b3ae 1629 IP_REGNUM, LR_REGNUM); \
6cfc7210
NC		 1630 assemble_name (STREAM, ARM_MCOUNT_NAME); \
1631 fputc ('\n', STREAM); \
1632 ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \
f1c25d3b 1633 sym = gen_rtx_SYMBOL_REF (Pmode, temp); \
301d03af 1634 assemble_aligned_integer (UNITS_PER_WORD, sym); \
35d965d5 1635}
be393ecf 1636#endif
35d965d5 1637
59be6073 1638#ifdef THUMB_FUNCTION_PROFILER
d5b7b3ae
RE		 1639#define FUNCTION_PROFILER(STREAM, LABELNO) \
1640 if (TARGET_ARM) \
1641 ARM_FUNCTION_PROFILER (STREAM, LABELNO) \
1642 else \
1643 THUMB_FUNCTION_PROFILER (STREAM, LABELNO)
59be6073
AN		 1644#else
1645#define FUNCTION_PROFILER(STREAM, LABELNO) \
1646 ARM_FUNCTION_PROFILER (STREAM, LABELNO)
1647#endif
d5b7b3ae 1648
35d965d5
RS		 1649/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1650 the stack pointer does not matter. The value is tested only in
1651 functions that have frame pointers.
1652 No definition is equivalent to always zero.
1653
1654 On the ARM, the function epilogue recovers the stack pointer from the
1655 frame. */
1656#define EXIT_IGNORE_STACK 1
1657
c7861455
RE		 1658#define EPILOGUE_USES(REGNO) (reload_completed && (REGNO) == LR_REGNUM)
1659
35d965d5
RS		 1660/* Determine if the epilogue should be output as RTL.
1661 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
d5b7b3ae 1662#define USE_RETURN_INSN(ISCOND) \
a72d4945 1663 (TARGET_ARM ? use_return_insn (ISCOND, NULL) : 0)
ff9940b0
RE		 1664
1665/* Definitions for register eliminations.
1666
1667 This is an array of structures. Each structure initializes one pair
1668 of eliminable registers. The "from" register number is given first,
1669 followed by "to". Eliminations of the same "from" register are listed
1670 in order of preference.
1671
1672 We have two registers that can be eliminated on the ARM. First, the
1673 arg pointer register can often be eliminated in favor of the stack
1674 pointer register. Secondly, the pseudo frame pointer register can always
1675 be eliminated; it is replaced with either the stack or the real frame
d5b7b3ae 1676 pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM
d6a7951f 1677 because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */
ff9940b0 1678
d5b7b3ae
RE		 1679#define ELIMINABLE_REGS \
1680{{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1681 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\
1682 { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1683 { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\
1684 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1685 { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1686 { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }}
ff9940b0 1687
d5b7b3ae
RE		 1688/* Given FROM and TO register numbers, say whether this elimination is
1689 allowed. Frame pointer elimination is automatically handled.
ff9940b0
RE		 1690
1691 All eliminations are permissible. Note that ARG_POINTER_REGNUM and
abc95ed3 1692 HARD_FRAME_POINTER_REGNUM are in fact the same thing. If we need a frame
ff9940b0 1693 pointer, we must eliminate FRAME_POINTER_REGNUM into
d5b7b3ae
RE		 1694 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM or
1695 ARG_POINTER_REGNUM. */
1696#define CAN_ELIMINATE(FROM, TO) \
1697 (((TO) == FRAME_POINTER_REGNUM && (FROM) == ARG_POINTER_REGNUM) ? 0 : \
1698 ((TO) == STACK_POINTER_REGNUM && frame_pointer_needed) ? 0 : \
1699 ((TO) == ARM_HARD_FRAME_POINTER_REGNUM && TARGET_THUMB) ? 0 : \
1700 ((TO) == THUMB_HARD_FRAME_POINTER_REGNUM && TARGET_ARM) ? 0 : \
1701 1)
aeaf4d25 1702
d5b7b3ae
RE		 1703/* Define the offset between two registers, one to be eliminated, and the
1704 other its replacement, at the start of a routine. */
d5b7b3ae
RE		 1705#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1706 if (TARGET_ARM) \
5848830f 1707 (OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \
d5b7b3ae 1708 else \
5848830f
PB		 1709 (OFFSET) = thumb_compute_initial_elimination_offset (FROM, TO)
1710
d5b7b3ae
RE		 1711/* Special case handling of the location of arguments passed on the stack. */
1712#define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr)
f676971a 1713
d5b7b3ae
RE		 1714/* Initialize data used by insn expanders. This is called from insn_emit,
1715 once for every function before code is generated. */
1716#define INIT_EXPANDERS arm_init_expanders ()
1717
35d965d5
RS		 1718/* Output assembler code for a block containing the constant parts
1719 of a trampoline, leaving space for the variable parts.
1720
1721 On the ARM, (if r8 is the static chain regnum, and remembering that
1722 referencing pc adds an offset of 8) the trampoline looks like:
1723 ldr r8, [pc, #0]
1724 ldr pc, [pc]
1725 .word static chain value
11c1a207 1726 .word function's address
27847754 1727 XXX FIXME: When the trampoline returns, r8 will be clobbered. */
301d03af
RS		 1728#define ARM_TRAMPOLINE_TEMPLATE(FILE) \
1729{ \
1730 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
1731 STATIC_CHAIN_REGNUM, PC_REGNUM); \
1732 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
1733 PC_REGNUM, PC_REGNUM); \
1734 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1735 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
d5b7b3ae
RE		 1736}
1737
1738/* On the Thumb we always switch into ARM mode to execute the trampoline.
1739 Why - because it is easier. This code will always be branched to via
1740 a BX instruction and since the compiler magically generates the address
1741 of the function the linker has no opportunity to ensure that the
1742 bottom bit is set. Thus the processor will be in ARM mode when it
1743 reaches this code. So we duplicate the ARM trampoline code and add
1744 a switch into Thumb mode as well. */
1745#define THUMB_TRAMPOLINE_TEMPLATE(FILE) \
1746{ \
1747 fprintf (FILE, "\t.code 32\n"); \
1748 fprintf (FILE, ".Ltrampoline_start:\n"); \
1749 asm_fprintf (FILE, "\tldr\t%r, [%r, #8]\n", \
1750 STATIC_CHAIN_REGNUM, PC_REGNUM); \
1751 asm_fprintf (FILE, "\tldr\t%r, [%r, #8]\n", \
1752 IP_REGNUM, PC_REGNUM); \
1753 asm_fprintf (FILE, "\torr\t%r, %r, #1\n", \
1754 IP_REGNUM, IP_REGNUM); \
1755 asm_fprintf (FILE, "\tbx\t%r\n", IP_REGNUM); \
1756 fprintf (FILE, "\t.word\t0\n"); \
1757 fprintf (FILE, "\t.word\t0\n"); \
1758 fprintf (FILE, "\t.code 16\n"); \
35d965d5
RS		 1759}
1760
d5b7b3ae
RE		 1761#define TRAMPOLINE_TEMPLATE(FILE) \
1762 if (TARGET_ARM) \
1763 ARM_TRAMPOLINE_TEMPLATE (FILE) \
1764 else \
1765 THUMB_TRAMPOLINE_TEMPLATE (FILE)
f676971a 1766
35d965d5 1767/* Length in units of the trampoline for entering a nested function. */
d5b7b3ae 1768#define TRAMPOLINE_SIZE (TARGET_ARM ? 16 : 24)
35d965d5 1769
006946e4
JM		 1770/* Alignment required for a trampoline in bits. */
1771#define TRAMPOLINE_ALIGNMENT 32
35d965d5 1772
2a86f515
PB		 1773/* Call __clear_cache after setting up the trampoline unless this is a nop. */
1774#ifdef CLEAR_INSN_CACHE
1775#define ARM_EMIT_TRAMPOLINE_CACHE_CLEAR(TRAMP) \
1776 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__clear_cache"), \
1777 0, VOIDmode, 2, TRAMP, Pmode, \
1778 plus_constant (TRAMP, TRAMPOLINE_SIZE), Pmode);
1779#else
1780#define ARM_EMIT_TRAMPOLINE_CACHE_CLEAR(TRAMP) do {} while (0)
1781#endif
1782
35d965d5
RS		 1783/* Emit RTL insns to initialize the variable parts of a trampoline.
1784 FNADDR is an RTX for the address of the function's pure code.
1785 CXT is an RTX for the static chain value for the function. */
192c8d78
RE		 1786#ifndef INITIALIZE_TRAMPOLINE
1787#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1788{ \
1789 emit_move_insn (gen_rtx_MEM (SImode, \
1790 plus_constant (TRAMP, \
1791 TARGET_ARM ? 8 : 16)), \
1792 CXT); \
1793 emit_move_insn (gen_rtx_MEM (SImode, \
1794 plus_constant (TRAMP, \
1795 TARGET_ARM ? 12 : 20)), \
1796 FNADDR); \
2a86f515 1797 ARM_EMIT_TRAMPOLINE_CACHE_CLEAR (TRAMP); \
35d965d5 1798}
192c8d78 1799#endif
35d965d5 1800
35d965d5
RS		 1801\f
1802/* Addressing modes, and classification of registers for them. */
3cd45774
RE		 1803#define HAVE_POST_INCREMENT 1
1804#define HAVE_PRE_INCREMENT TARGET_ARM
1805#define HAVE_POST_DECREMENT TARGET_ARM
1806#define HAVE_PRE_DECREMENT TARGET_ARM
1807#define HAVE_PRE_MODIFY_DISP TARGET_ARM
1808#define HAVE_POST_MODIFY_DISP TARGET_ARM
1809#define HAVE_PRE_MODIFY_REG TARGET_ARM
1810#define HAVE_POST_MODIFY_REG TARGET_ARM
35d965d5
RS		 1811
1812/* Macros to check register numbers against specific register classes. */
1813
1814/* These assume that REGNO is a hard or pseudo reg number.
1815 They give nonzero only if REGNO is a hard reg of the suitable class
1816 or a pseudo reg currently allocated to a suitable hard reg.
1817 Since they use reg_renumber, they are safe only once reg_renumber
d6b4baa4 1818 has been allocated, which happens in local-alloc.c. */
d5b7b3ae
RE		 1819#define TEST_REGNO(R, TEST, VALUE) \
1820 ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE))
1821
1822/* On the ARM, don't allow the pc to be used. */
f1008e52
RE		 1823#define ARM_REGNO_OK_FOR_BASE_P(REGNO) \
1824 (TEST_REGNO (REGNO, <, PC_REGNUM) \
1825 || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \
1826 || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM))
1827
1828#define THUMB_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1829 (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \
1830 || (GET_MODE_SIZE (MODE) >= 4 \
1831 && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)))
1832
1833#define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1834 (TARGET_THUMB \
1835 ? THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \
1836 : ARM_REGNO_OK_FOR_BASE_P (REGNO))
1837
888d2cd6
DJ		 1838/* Nonzero if X can be the base register in a reg+reg addressing mode.
1839 For Thumb, we can not use SP + reg, so reject SP. */
1840#define REGNO_MODE_OK_FOR_REG_BASE_P(X, MODE) \
1841 REGNO_OK_FOR_INDEX_P (X)
1842
f1008e52
RE		 1843/* For ARM code, we don't care about the mode, but for Thumb, the index
1844 must be suitable for use in a QImode load. */
d5b7b3ae
RE		 1845#define REGNO_OK_FOR_INDEX_P(REGNO) \
1846 REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode)
35d965d5
RS		 1847
1848/* Maximum number of registers that can appear in a valid memory address.
d6b4baa4 1849 Shifts in addresses can't be by a register. */
ff9940b0 1850#define MAX_REGS_PER_ADDRESS 2
35d965d5
RS		 1851
1852/* Recognize any constant value that is a valid address. */
1853/* XXX We can address any constant, eventually... */
11c1a207
RE		 1854
1855#ifdef AOF_ASSEMBLER
1856
1857#define CONSTANT_ADDRESS_P(X) \
d5b7b3ae 1858 (GET_CODE (X) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (X))
11c1a207
RE		 1859
1860#else
35d965d5 1861
008cf58a
RE		 1862#define CONSTANT_ADDRESS_P(X) \
1863 (GET_CODE (X) == SYMBOL_REF \
1864 && (CONSTANT_POOL_ADDRESS_P (X) \
d5b7b3ae 1865 || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X))))
35d965d5 1866
11c1a207
RE		 1867#endif /* AOF_ASSEMBLER */
1868
35d965d5
RS		 1869/* Nonzero if the constant value X is a legitimate general operand.
1870 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1871
1872 On the ARM, allow any integer (invalid ones are removed later by insn
1873 patterns), nice doubles and symbol_refs which refer to the function's
d5b7b3ae 1874 constant pool XXX.
f676971a 1875
82e9d970 1876 When generating pic allow anything. */
d5b7b3ae
RE		 1877#define ARM_LEGITIMATE_CONSTANT_P(X) (flag_pic || ! label_mentioned_p (X))
1878
1879#define THUMB_LEGITIMATE_CONSTANT_P(X) \
1880 ( GET_CODE (X) == CONST_INT \
1881 || GET_CODE (X) == CONST_DOUBLE \
7b8781c8
PB		 1882 || CONSTANT_ADDRESS_P (X) \
1883 || flag_pic)
d5b7b3ae
RE		 1884
1885#define LEGITIMATE_CONSTANT_P(X) \
1886 (TARGET_ARM ? ARM_LEGITIMATE_CONSTANT_P (X) : THUMB_LEGITIMATE_CONSTANT_P (X))
1887
c27ba912
DM		 1888/* Special characters prefixed to function names
1889 in order to encode attribute like information.
1890 Note, '@' and '*' have already been taken. */
1891#define SHORT_CALL_FLAG_CHAR '^'
1892#define LONG_CALL_FLAG_CHAR '#'
1893
1894#define ENCODED_SHORT_CALL_ATTR_P(SYMBOL_NAME) \
1895 (*(SYMBOL_NAME) == SHORT_CALL_FLAG_CHAR)
1896
1897#define ENCODED_LONG_CALL_ATTR_P(SYMBOL_NAME) \
1898 (*(SYMBOL_NAME) == LONG_CALL_FLAG_CHAR)
1899
1900#ifndef SUBTARGET_NAME_ENCODING_LENGTHS
1901#define SUBTARGET_NAME_ENCODING_LENGTHS
1902#endif
1903
6bc82793 1904/* This is a C fragment for the inside of a switch statement.
c27ba912
DM		 1905 Each case label should return the number of characters to
1906 be stripped from the start of a function's name, if that
1907 name starts with the indicated character. */
1908#define ARM_NAME_ENCODING_LENGTHS \
1909 case SHORT_CALL_FLAG_CHAR: return 1; \
1910 case LONG_CALL_FLAG_CHAR: return 1; \
00fdafef 1911 case '*': return 1; \
f676971a 1912 SUBTARGET_NAME_ENCODING_LENGTHS
c27ba912 1913
c27ba912
DM		 1914/* This is how to output a reference to a user-level label named NAME.
1915 `assemble_name' uses this. */
e5951263 1916#undef ASM_OUTPUT_LABELREF
c27ba912 1917#define ASM_OUTPUT_LABELREF(FILE, NAME) \
e1944073 1918 arm_asm_output_labelref (FILE, NAME)
c27ba912 1919
7abc66b1
JB		 1920/* The EABI specifies that constructors should go in .init_array.
1921 Other targets use .ctors for compatibility. */
88c6057f 1922#ifndef ARM_EABI_CTORS_SECTION_OP
7abc66b1
JB		 1923#define ARM_EABI_CTORS_SECTION_OP \
1924 "\t.section\t.init_array,\"aw\",%init_array"
88c6057f
MM		 1925#endif
1926#ifndef ARM_EABI_DTORS_SECTION_OP
7abc66b1
JB		 1927#define ARM_EABI_DTORS_SECTION_OP \
1928 "\t.section\t.fini_array,\"aw\",%fini_array"
88c6057f 1929#endif
7abc66b1
JB		 1930#define ARM_CTORS_SECTION_OP \
1931 "\t.section\t.ctors,\"aw\",%progbits"
1932#define ARM_DTORS_SECTION_OP \
1933 "\t.section\t.dtors,\"aw\",%progbits"
1934
1935/* Define CTORS_SECTION_ASM_OP. */
1936#undef CTORS_SECTION_ASM_OP
1937#undef DTORS_SECTION_ASM_OP
1938#ifndef IN_LIBGCC2
1939# define CTORS_SECTION_ASM_OP \
1940 (TARGET_AAPCS_BASED ? ARM_EABI_CTORS_SECTION_OP : ARM_CTORS_SECTION_OP)
1941# define DTORS_SECTION_ASM_OP \
1942 (TARGET_AAPCS_BASED ? ARM_EABI_DTORS_SECTION_OP : ARM_DTORS_SECTION_OP)
1943#else /* !defined (IN_LIBGCC2) */
1944/* In libgcc, CTORS_SECTION_ASM_OP must be a compile-time constant,
1945 so we cannot use the definition above. */
1946# ifdef __ARM_EABI__
1947/* The .ctors section is not part of the EABI, so we do not define
1948 CTORS_SECTION_ASM_OP when in libgcc; that prevents crtstuff
1949 from trying to use it. We do define it when doing normal
1950 compilation, as .init_array can be used instead of .ctors. */
1951/* There is no need to emit begin or end markers when using
1952 init_array; the dynamic linker will compute the size of the
1953 array itself based on special symbols created by the static
1954 linker. However, we do need to arrange to set up
1955 exception-handling here. */
1956# define CTOR_LIST_BEGIN asm (ARM_EABI_CTORS_SECTION_OP)
1957# define CTOR_LIST_END /* empty */
1958# define DTOR_LIST_BEGIN asm (ARM_EABI_DTORS_SECTION_OP)
1959# define DTOR_LIST_END /* empty */
1960# else /* !defined (__ARM_EABI__) */
1961# define CTORS_SECTION_ASM_OP ARM_CTORS_SECTION_OP
1962# define DTORS_SECTION_ASM_OP ARM_DTORS_SECTION_OP
1963# endif /* !defined (__ARM_EABI__) */
1964#endif /* !defined (IN_LIBCC2) */
1965
1e731102
MM		 1966/* True if the operating system can merge entities with vague linkage
1967 (e.g., symbols in COMDAT group) during dynamic linking. */
1968#ifndef TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P
1969#define TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P true
1970#endif
1971
a77655b1
NC		 1972/* Set the short-call flag for any function compiled in the current
1973 compilation unit. We skip this for functions with the section
c112cf2b 1974 attribute when long-calls are in effect as this tells the compiler
a77655b1
NC		 1975 that the section might be placed a long way from the caller.
1976 See arm_is_longcall_p() for more information. */
c27ba912 1977#define ARM_DECLARE_FUNCTION_SIZE(STREAM, NAME, DECL) \
a77655b1
NC		 1978 if (!TARGET_LONG_CALLS || ! DECL_SECTION_NAME (DECL)) \
1979 arm_encode_call_attribute (DECL, SHORT_CALL_FLAG_CHAR)
c27ba912 1980
35d965d5
RS		 1981/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1982 and check its validity for a certain class.
1983 We have two alternate definitions for each of them.
1984 The usual definition accepts all pseudo regs; the other rejects
1985 them unless they have been allocated suitable hard regs.
1986 The symbol REG_OK_STRICT causes the latter definition to be used. */
1987#ifndef REG_OK_STRICT
ff9940b0 1988
f1008e52
RE		 1989#define ARM_REG_OK_FOR_BASE_P(X) \
1990 (REGNO (X) <= LAST_ARM_REGNUM \
1991 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
1992 || REGNO (X) == FRAME_POINTER_REGNUM \
1993 || REGNO (X) == ARG_POINTER_REGNUM)
ff9940b0 1994
f1008e52
RE		 1995#define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \
1996 (REGNO (X) <= LAST_LO_REGNUM \
1997 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
1998 || (GET_MODE_SIZE (MODE) >= 4 \
1999 && (REGNO (X) == STACK_POINTER_REGNUM \
2000 || (X) == hard_frame_pointer_rtx \
2001 || (X) == arg_pointer_rtx)))
ff9940b0 2002
76a318e9
RE		 2003#define REG_STRICT_P 0
2004
d5b7b3ae 2005#else /* REG_OK_STRICT */
ff9940b0 2006
f1008e52
RE		 2007#define ARM_REG_OK_FOR_BASE_P(X) \
2008 ARM_REGNO_OK_FOR_BASE_P (REGNO (X))
ff9940b0 2009
f1008e52
RE		 2010#define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \
2011 THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE)
ff9940b0 2012
76a318e9
RE		 2013#define REG_STRICT_P 1
2014
d5b7b3ae 2015#endif /* REG_OK_STRICT */
f1008e52
RE		 2016
2017/* Now define some helpers in terms of the above. */
2018
2019#define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2020 (TARGET_THUMB \
2021 ? THUMB_REG_MODE_OK_FOR_BASE_P (X, MODE) \
2022 : ARM_REG_OK_FOR_BASE_P (X))
2023
2024#define ARM_REG_OK_FOR_INDEX_P(X) ARM_REG_OK_FOR_BASE_P (X)
2025
2026/* For Thumb, a valid index register is anything that can be used in
2027 a byte load instruction. */
2028#define THUMB_REG_OK_FOR_INDEX_P(X) THUMB_REG_MODE_OK_FOR_BASE_P (X, QImode)
2029
2030/* Nonzero if X is a hard reg that can be used as an index
2031 or if it is a pseudo reg. On the Thumb, the stack pointer
2032 is not suitable. */
2033#define REG_OK_FOR_INDEX_P(X) \
2034 (TARGET_THUMB \
2035 ? THUMB_REG_OK_FOR_INDEX_P (X) \
2036 : ARM_REG_OK_FOR_INDEX_P (X))
2037
888d2cd6
DJ		 2038/* Nonzero if X can be the base register in a reg+reg addressing mode.
2039 For Thumb, we can not use SP + reg, so reject SP. */
2040#define REG_MODE_OK_FOR_REG_BASE_P(X, MODE) \
2041 REG_OK_FOR_INDEX_P (X)
35d965d5
RS		 2042\f
2043/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2044 that is a valid memory address for an instruction.
2045 The MODE argument is the machine mode for the MEM expression
76a318e9 2046 that wants to use this address. */
f676971a 2047
f1008e52
RE		 2048#define ARM_BASE_REGISTER_RTX_P(X) \
2049 (GET_CODE (X) == REG && ARM_REG_OK_FOR_BASE_P (X))
35d965d5 2050
f1008e52
RE		 2051#define ARM_INDEX_REGISTER_RTX_P(X) \
2052 (GET_CODE (X) == REG && ARM_REG_OK_FOR_INDEX_P (X))
35d965d5 2053
76a318e9
RE		 2054#define ARM_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
2055 { \
1e1ab407 2056 if (arm_legitimate_address_p (MODE, X, SET, REG_STRICT_P)) \
76a318e9 2057 goto WIN; \
6b990f6b 2058 }
d5b7b3ae 2059
76a318e9
RE		 2060#define THUMB_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
2061 { \
2062 if (thumb_legitimate_address_p (MODE, X, REG_STRICT_P)) \
2063 goto WIN; \
2064 }
d5b7b3ae 2065
d5b7b3ae
RE		 2066#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \
2067 if (TARGET_ARM) \
2068 ARM_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN) \
2069 else /* if (TARGET_THUMB) */ \
f676971a 2070 THUMB_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN)
76a318e9 2071
35d965d5
RS		 2072\f
2073/* Try machine-dependent ways of modifying an illegitimate address
ccf4d512
RE		 2074 to be legitimate. If we find one, return the new, valid address. */
2075#define ARM_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2076do { \
2077 X = arm_legitimize_address (X, OLDX, MODE); \
ccf4d512
RE		 2078} while (0)
2079
6f5b4f3e
RE		 2080#define THUMB_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2081do { \
2082 X = thumb_legitimize_address (X, OLDX, MODE); \
ccf4d512
RE		 2083} while (0)
2084
2085#define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2086do { \
2087 if (TARGET_ARM) \
2088 ARM_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
2089 else \
2090 THUMB_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
6f5b4f3e
RE		 2091 \
2092 if (memory_address_p (MODE, X)) \
2093 goto WIN; \
ccf4d512 2094} while (0)
f676971a 2095
35d965d5
RS		 2096/* Go to LABEL if ADDR (a legitimate address expression)
2097 has an effect that depends on the machine mode it is used for. */
d5b7b3ae 2098#define ARM_GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
35d965d5 2099{ \
d5b7b3ae
RE		 2100 if ( GET_CODE (ADDR) == PRE_DEC || GET_CODE (ADDR) == POST_DEC \
2101 || GET_CODE (ADDR) == PRE_INC || GET_CODE (ADDR) == POST_INC) \
35d965d5
RS		 2102 goto LABEL; \
2103}
d5b7b3ae
RE		 2104
2105/* Nothing helpful to do for the Thumb */
2106#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2107 if (TARGET_ARM) \
f676971a 2108 ARM_GO_IF_MODE_DEPENDENT_ADDRESS (ADDR, LABEL)
35d965d5 2109\f
d5b7b3ae 2110
35d965d5
RS		 2111/* Specify the machine mode that this machine uses
2112 for the index in the tablejump instruction. */
d5b7b3ae 2113#define CASE_VECTOR_MODE Pmode
35d965d5 2114
ff9940b0
RE		 2115/* signed 'char' is most compatible, but RISC OS wants it unsigned.
2116 unsigned is probably best, but may break some code. */
2117#ifndef DEFAULT_SIGNED_CHAR
3967692c 2118#define DEFAULT_SIGNED_CHAR 0
35d965d5
RS		 2119#endif
2120
35d965d5 2121/* Max number of bytes we can move from memory to memory
d17ce9af
TG		 2122 in one reasonably fast instruction. */
2123#define MOVE_MAX 4
35d965d5 2124
d19fb8e3 2125#undef MOVE_RATIO
591af218 2126#define MOVE_RATIO (arm_tune_xscale ? 4 : 2)
d19fb8e3 2127
ff9940b0
RE		 2128/* Define if operations between registers always perform the operation
2129 on the full register even if a narrower mode is specified. */
2130#define WORD_REGISTER_OPERATIONS
2131
2132/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2133 will either zero-extend or sign-extend. The value of this macro should
2134 be the code that says which one of the two operations is implicitly
f822d252 2135 done, UNKNOWN if none. */
9c872872 2136#define LOAD_EXTEND_OP(MODE) \
d5b7b3ae
RE		 2137 (TARGET_THUMB ? ZERO_EXTEND : \
2138 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \
f822d252 2139 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : UNKNOWN)))
ff9940b0 2140
35d965d5
RS		 2141/* Nonzero if access to memory by bytes is slow and undesirable. */
2142#define SLOW_BYTE_ACCESS 0
2143
d5b7b3ae 2144#define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1
f676971a 2145
35d965d5
RS		 2146/* Immediate shift counts are truncated by the output routines (or was it
2147 the assembler?). Shift counts in a register are truncated by ARM. Note
2148 that the native compiler puts too large (> 32) immediate shift counts
2149 into a register and shifts by the register, letting the ARM decide what
2150 to do instead of doing that itself. */
ff9940b0
RE		 2151/* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that
2152 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
2153 On the arm, Y in a register is used modulo 256 for the shift. Only for
d6b4baa4 2154 rotates is modulo 32 used. */
ff9940b0 2155/* #define SHIFT_COUNT_TRUNCATED 1 */
35d965d5 2156
35d965d5 2157/* All integers have the same format so truncation is easy. */
d5b7b3ae 2158#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
35d965d5
RS		 2159
2160/* Calling from registers is a massive pain. */
2161#define NO_FUNCTION_CSE 1
2162
35d965d5
RS		 2163/* The machine modes of pointers and functions */
2164#define Pmode SImode
2165#define FUNCTION_MODE Pmode
2166
d5b7b3ae
RE		 2167#define ARM_FRAME_RTX(X) \
2168 ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
3967692c
RE		 2169 || (X) == arg_pointer_rtx)
2170
ff9940b0 2171/* Moves to and from memory are quite expensive */
d5b7b3ae
RE		 2172#define MEMORY_MOVE_COST(M, CLASS, IN) \
2173 (TARGET_ARM ? 10 : \
2174 ((GET_MODE_SIZE (M) < 4 ? 8 : 2 * GET_MODE_SIZE (M)) \
2175 * (CLASS == LO_REGS ? 1 : 2)))
f676971a 2176
ff9940b0
RE		 2177/* Try to generate sequences that don't involve branches, we can then use
2178 conditional instructions */
d5b7b3ae
RE		 2179#define BRANCH_COST \
2180 (TARGET_ARM ? 4 : (optimize > 1 ? 1 : 0))
7a801826
RE		 2181\f
2182/* Position Independent Code. */
2183/* We decide which register to use based on the compilation options and
2184 the assembler in use; this is more general than the APCS restriction of
2185 using sb (r9) all the time. */
2186extern int arm_pic_register;
2187
2188/* The register number of the register used to address a table of static
2189 data addresses in memory. */
2190#define PIC_OFFSET_TABLE_REGNUM arm_pic_register
2191
f5a1b0d2
NC		 2192/* We can't directly access anything that contains a symbol,
2193 nor can we indirect via the constant pool. */
82e9d970 2194#define LEGITIMATE_PIC_OPERAND_P(X) \
1575c31e
JD		 2195 (!(symbol_mentioned_p (X) \
2196 || label_mentioned_p (X) \
2197 || (GET_CODE (X) == SYMBOL_REF \
2198 && CONSTANT_POOL_ADDRESS_P (X) \
2199 && (symbol_mentioned_p (get_pool_constant (X)) \
2200 || label_mentioned_p (get_pool_constant (X))))))
2201
13bd191d
PB		 2202/* We need to know when we are making a constant pool; this determines
2203 whether data needs to be in the GOT or can be referenced via a GOT
2204 offset. */
2205extern int making_const_table;
82e9d970 2206\f
c27ba912 2207/* Handle pragmas for compatibility with Intel's compilers. */
c58b209a
NB		 2208#define REGISTER_TARGET_PRAGMAS() do { \
2209 c_register_pragma (0, "long_calls", arm_pr_long_calls); \
2210 c_register_pragma (0, "no_long_calls", arm_pr_no_long_calls); \
2211 c_register_pragma (0, "long_calls_off", arm_pr_long_calls_off); \
8b97c5f8
ZW		 2212} while (0)
2213
d6b4baa4 2214/* Condition code information. */
ff9940b0 2215/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
a5381466 2216 return the mode to be used for the comparison. */
d5b7b3ae
RE		 2217
2218#define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y)
ff9940b0 2219
880873be
RE		 2220#define REVERSIBLE_CC_MODE(MODE) 1
2221
2222#define REVERSE_CONDITION(CODE,MODE) \
2223 (((MODE) == CCFPmode || (MODE) == CCFPEmode) \
2224 ? reverse_condition_maybe_unordered (code) \
2225 : reverse_condition (code))
008cf58a 2226
62b10bbc
NC		 2227#define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \
2228 do \
2229 { \
2230 if (GET_CODE (OP1) == CONST_INT \
2231 && ! (const_ok_for_arm (INTVAL (OP1)) \
2232 || (const_ok_for_arm (- INTVAL (OP1))))) \
2233 { \
2234 rtx const_op = OP1; \
2235 CODE = arm_canonicalize_comparison ((CODE), &const_op); \
2236 OP1 = const_op; \
2237 } \
2238 } \
2239 while (0)
62dd06ea 2240
7dba8395
RH		 2241/* The arm5 clz instruction returns 32. */
2242#define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
35d965d5 2243\f
d5b7b3ae
RE		 2244#undef ASM_APP_OFF
2245#define ASM_APP_OFF (TARGET_THUMB ? "\t.code\t16\n" : "")
35d965d5 2246
35d965d5 2247/* Output a push or a pop instruction (only used when profiling). */
d5b7b3ae 2248#define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \
8a81cc45
RE		 2249 do \
2250 { \
2251 if (TARGET_ARM) \
2252 asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", \
2253 STACK_POINTER_REGNUM, REGNO); \
2254 else \
2255 asm_fprintf (STREAM, "\tpush {%r}\n", REGNO); \
2256 } while (0)
d5b7b3ae
RE		 2257
2258
2259#define ASM_OUTPUT_REG_POP(STREAM, REGNO) \
8a81cc45
RE		 2260 do \
2261 { \
2262 if (TARGET_ARM) \
2263 asm_fprintf (STREAM, "\tldmfd\t%r!,{%r}\n", \
2264 STACK_POINTER_REGNUM, REGNO); \
2265 else \
2266 asm_fprintf (STREAM, "\tpop {%r}\n", REGNO); \
2267 } while (0)
d5b7b3ae
RE		 2268
2269/* This is how to output a label which precedes a jumptable. Since
2270 Thumb instructions are 2 bytes, we may need explicit alignment here. */
be393ecf 2271#undef ASM_OUTPUT_CASE_LABEL
d5b7b3ae
RE		 2272#define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, JUMPTABLE) \
2273 do \
2274 { \
2275 if (TARGET_THUMB) \
2276 ASM_OUTPUT_ALIGN (FILE, 2); \
8a81cc45 2277 (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \
d5b7b3ae
RE		 2278 } \
2279 while (0)
35d965d5 2280
6cfc7210
NC		 2281#define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \
2282 do \
2283 { \
d5b7b3ae
RE		 2284 if (TARGET_THUMB) \
2285 { \
9b66ebb1
PB		 2286 if (is_called_in_ARM_mode (DECL) \
2287 || current_function_is_thunk) \
d5b7b3ae
RE		 2288 fprintf (STREAM, "\t.code 32\n") ; \
2289 else \
9b66ebb1 2290 fprintf (STREAM, "\t.code 16\n\t.thumb_func\n") ; \
d5b7b3ae 2291 } \
6cfc7210 2292 if (TARGET_POKE_FUNCTION_NAME) \
6354dc9b 2293 arm_poke_function_name (STREAM, (char *) NAME); \
6cfc7210
NC		 2294 } \
2295 while (0)
35d965d5 2296
d5b7b3ae
RE		 2297/* For aliases of functions we use .thumb_set instead. */
2298#define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \
2299 do \
2300 { \
91ea4f8d
KG		 2301 const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \
2302 const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \
d5b7b3ae
RE		 2303 \
2304 if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \
2305 { \
2306 fprintf (FILE, "\t.thumb_set "); \
2307 assemble_name (FILE, LABEL1); \
2308 fprintf (FILE, ","); \
2309 assemble_name (FILE, LABEL2); \
2310 fprintf (FILE, "\n"); \
2311 } \
2312 else \
2313 ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \
2314 } \
2315 while (0)
2316
fdc2d3b0
NC		 2317#ifdef HAVE_GAS_MAX_SKIP_P2ALIGN
2318/* To support -falign-* switches we need to use .p2align so
2319 that alignment directives in code sections will be padded
2320 with no-op instructions, rather than zeroes. */
5a9335ef 2321#define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE, LOG, MAX_SKIP) \
fdc2d3b0
NC		 2322 if ((LOG) != 0) \
2323 { \
2324 if ((MAX_SKIP) == 0) \
5a9335ef 2325 fprintf ((FILE), "\t.p2align %d\n", (int) (LOG)); \
fdc2d3b0
NC		 2326 else \
2327 fprintf ((FILE), "\t.p2align %d,,%d\n", \
5a9335ef 2328 (int) (LOG), (int) (MAX_SKIP)); \
fdc2d3b0
NC		 2329 }
2330#endif
35d965d5 2331\f
35d965d5 2332/* Only perform branch elimination (by making instructions conditional) if
72ac76be 2333 we're optimizing. Otherwise it's of no use anyway. */
d5b7b3ae
RE		 2334#define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2335 if (TARGET_ARM && optimize) \
2336 arm_final_prescan_insn (INSN); \
2337 else if (TARGET_THUMB) \
2338 thumb_final_prescan_insn (INSN)
35d965d5 2339
7bc7696c 2340#define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
d5b7b3ae
RE		 2341 (CODE == '@' || CODE == '|' \
2342 || (TARGET_ARM && (CODE == '?')) \
2343 || (TARGET_THUMB && (CODE == '_')))
6cfc7210 2344
7bc7696c 2345/* Output an operand of an instruction. */
35d965d5 2346#define PRINT_OPERAND(STREAM, X, CODE) \
7bc7696c
RE		 2347 arm_print_operand (STREAM, X, CODE)
2348
7b8b8ade
NC		 2349#define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \
2350 (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \
30cf4896
KG		 2351 : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\
2352 ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \
2353 ? ((~ (unsigned HOST_WIDE_INT) 0) \
2354 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \
7bc7696c 2355 : 0))))
35d965d5
RS		 2356
2357/* Output the address of an operand. */
3cd45774
RE		 2358#define ARM_PRINT_OPERAND_ADDRESS(STREAM, X) \
2359{ \
2360 int is_minus = GET_CODE (X) == MINUS; \
2361 \
2362 if (GET_CODE (X) == REG) \
2363 asm_fprintf (STREAM, "[%r, #0]", REGNO (X)); \
2364 else if (GET_CODE (X) == PLUS || is_minus) \
2365 { \
2366 rtx base = XEXP (X, 0); \
2367 rtx index = XEXP (X, 1); \
2368 HOST_WIDE_INT offset = 0; \
2369 if (GET_CODE (base) != REG) \
2370 { \
d6b4baa4
KH		 2371 /* Ensure that BASE is a register. */ \
2372 /* (one of them must be). */ \
3cd45774
RE		 2373 rtx temp = base; \
2374 base = index; \
2375 index = temp; \
2376 } \
2377 switch (GET_CODE (index)) \
2378 { \
2379 case CONST_INT: \
2380 offset = INTVAL (index); \
2381 if (is_minus) \
2382 offset = -offset; \
c53dddc2 2383 asm_fprintf (STREAM, "[%r, #%wd]", \
3cd45774
RE		 2384 REGNO (base), offset); \
2385 break; \
2386 \
2387 case REG: \
2388 asm_fprintf (STREAM, "[%r, %s%r]", \
2389 REGNO (base), is_minus ? "-" : "", \
2390 REGNO (index)); \
2391 break; \
2392 \
2393 case MULT: \
2394 case ASHIFTRT: \
2395 case LSHIFTRT: \
2396 case ASHIFT: \
2397 case ROTATERT: \
2398 { \
2399 asm_fprintf (STREAM, "[%r, %s%r", \
2400 REGNO (base), is_minus ? "-" : "", \
2401 REGNO (XEXP (index, 0))); \
2402 arm_print_operand (STREAM, index, 'S'); \
2403 fputs ("]", STREAM); \
2404 break; \
2405 } \
2406 \
2407 default: \
e6d29d15 2408 gcc_unreachable (); \
3cd45774
RE		 2409 } \
2410 } \
2411 else if (GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC \
2412 || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC) \
2413 { \
2414 extern enum machine_mode output_memory_reference_mode; \
2415 \
e6d29d15 2416 gcc_assert (GET_CODE (XEXP (X, 0)) == REG); \
3cd45774
RE		 2417 \
2418 if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \
2419 asm_fprintf (STREAM, "[%r, #%s%d]!", \
2420 REGNO (XEXP (X, 0)), \
2421 GET_CODE (X) == PRE_DEC ? "-" : "", \
2422 GET_MODE_SIZE (output_memory_reference_mode)); \
2423 else \
2424 asm_fprintf (STREAM, "[%r], #%s%d", \
2425 REGNO (XEXP (X, 0)), \
2426 GET_CODE (X) == POST_DEC ? "-" : "", \
2427 GET_MODE_SIZE (output_memory_reference_mode)); \
2428 } \
2429 else if (GET_CODE (X) == PRE_MODIFY) \
2430 { \
2431 asm_fprintf (STREAM, "[%r, ", REGNO (XEXP (X, 0))); \
2432 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \
c53dddc2 2433 asm_fprintf (STREAM, "#%wd]!", \
3cd45774
RE		 2434 INTVAL (XEXP (XEXP (X, 1), 1))); \
2435 else \
2436 asm_fprintf (STREAM, "%r]!", \
2437 REGNO (XEXP (XEXP (X, 1), 1))); \
2438 } \
2439 else if (GET_CODE (X) == POST_MODIFY) \
2440 { \
2441 asm_fprintf (STREAM, "[%r], ", REGNO (XEXP (X, 0))); \
2442 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \
c53dddc2 2443 asm_fprintf (STREAM, "#%wd", \
3cd45774
RE		 2444 INTVAL (XEXP (XEXP (X, 1), 1))); \
2445 else \
2446 asm_fprintf (STREAM, "%r", \
2447 REGNO (XEXP (XEXP (X, 1), 1))); \
2448 } \
2449 else output_addr_const (STREAM, X); \
35d965d5 2450}
62dd06ea 2451
d5b7b3ae
RE		 2452#define THUMB_PRINT_OPERAND_ADDRESS(STREAM, X) \
2453{ \
2454 if (GET_CODE (X) == REG) \
2455 asm_fprintf (STREAM, "[%r]", REGNO (X)); \
2456 else if (GET_CODE (X) == POST_INC) \
2457 asm_fprintf (STREAM, "%r!", REGNO (XEXP (X, 0))); \
2458 else if (GET_CODE (X) == PLUS) \
2459 { \
e6d29d15 2460 gcc_assert (GET_CODE (XEXP (X, 0)) == REG); \
d5b7b3ae 2461 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
659bdc68 2462 asm_fprintf (STREAM, "[%r, #%wd]", \
d5b7b3ae 2463 REGNO (XEXP (X, 0)), \
659bdc68 2464 INTVAL (XEXP (X, 1))); \
d5b7b3ae
RE		 2465 else \
2466 asm_fprintf (STREAM, "[%r, %r]", \
2467 REGNO (XEXP (X, 0)), \
2468 REGNO (XEXP (X, 1))); \
2469 } \
2470 else \
2471 output_addr_const (STREAM, X); \
2472}
2473
2474#define PRINT_OPERAND_ADDRESS(STREAM, X) \
2475 if (TARGET_ARM) \
2476 ARM_PRINT_OPERAND_ADDRESS (STREAM, X) \
2477 else \
2478 THUMB_PRINT_OPERAND_ADDRESS (STREAM, X)
5a9335ef
NC		 2479
2480#define OUTPUT_ADDR_CONST_EXTRA(FILE, X, FAIL) \
2481 if (GET_CODE (X) != CONST_VECTOR \
2482 || ! arm_emit_vector_const (FILE, X)) \
2483 goto FAIL;
2484
6a5d7526
MS		 2485/* A C expression whose value is RTL representing the value of the return
2486 address for the frame COUNT steps up from the current frame. */
2487
d5b7b3ae
RE		 2488#define RETURN_ADDR_RTX(COUNT, FRAME) \
2489 arm_return_addr (COUNT, FRAME)
2490
f676971a 2491/* Mask of the bits in the PC that contain the real return address
d5b7b3ae
RE		 2492 when running in 26-bit mode. */
2493#define RETURN_ADDR_MASK26 (0x03fffffc)
6a5d7526 2494
2c849145
JM		 2495/* Pick up the return address upon entry to a procedure. Used for
2496 dwarf2 unwind information. This also enables the table driven
2497 mechanism. */
2c849145
JM		 2498#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM)
2499#define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM)
2500
39950dff
MS		 2501/* Used to mask out junk bits from the return address, such as
2502 processor state, interrupt status, condition codes and the like. */
2503#define MASK_RETURN_ADDR \
2504 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \
2505 in 26 bit mode, the condition codes must be masked out of the \
2506 return address. This does not apply to ARM6 and later processors \
2507 when running in 32 bit mode. */ \
61f0ccff
RE		 2508 ((arm_arch4 || TARGET_THUMB) \
2509 ? (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \
fcd53748 2510 : arm_gen_return_addr_mask ())
d5b7b3ae
RE		 2511
2512\f
5a9335ef
NC		 2513enum arm_builtins
2514{
2515 ARM_BUILTIN_GETWCX,
2516 ARM_BUILTIN_SETWCX,
2517
2518 ARM_BUILTIN_WZERO,
2519
2520 ARM_BUILTIN_WAVG2BR,
2521 ARM_BUILTIN_WAVG2HR,
2522 ARM_BUILTIN_WAVG2B,
2523 ARM_BUILTIN_WAVG2H,
2524
2525 ARM_BUILTIN_WACCB,
2526 ARM_BUILTIN_WACCH,
2527 ARM_BUILTIN_WACCW,
2528
2529 ARM_BUILTIN_WMACS,
2530 ARM_BUILTIN_WMACSZ,
2531 ARM_BUILTIN_WMACU,
2532 ARM_BUILTIN_WMACUZ,
2533
2534 ARM_BUILTIN_WSADB,
2535 ARM_BUILTIN_WSADBZ,
2536 ARM_BUILTIN_WSADH,
2537 ARM_BUILTIN_WSADHZ,
2538
2539 ARM_BUILTIN_WALIGN,
2540
2541 ARM_BUILTIN_TMIA,
2542 ARM_BUILTIN_TMIAPH,
2543 ARM_BUILTIN_TMIABB,
2544 ARM_BUILTIN_TMIABT,
2545 ARM_BUILTIN_TMIATB,
2546 ARM_BUILTIN_TMIATT,
2547
2548 ARM_BUILTIN_TMOVMSKB,
2549 ARM_BUILTIN_TMOVMSKH,
2550 ARM_BUILTIN_TMOVMSKW,
2551
2552 ARM_BUILTIN_TBCSTB,
2553 ARM_BUILTIN_TBCSTH,
2554 ARM_BUILTIN_TBCSTW,
2555
2556 ARM_BUILTIN_WMADDS,
2557 ARM_BUILTIN_WMADDU,
2558
2559 ARM_BUILTIN_WPACKHSS,
2560 ARM_BUILTIN_WPACKWSS,
2561 ARM_BUILTIN_WPACKDSS,
2562 ARM_BUILTIN_WPACKHUS,
2563 ARM_BUILTIN_WPACKWUS,
2564 ARM_BUILTIN_WPACKDUS,
2565
2566 ARM_BUILTIN_WADDB,
2567 ARM_BUILTIN_WADDH,
2568 ARM_BUILTIN_WADDW,
2569 ARM_BUILTIN_WADDSSB,
2570 ARM_BUILTIN_WADDSSH,
2571 ARM_BUILTIN_WADDSSW,
2572 ARM_BUILTIN_WADDUSB,
2573 ARM_BUILTIN_WADDUSH,
2574 ARM_BUILTIN_WADDUSW,
2575 ARM_BUILTIN_WSUBB,
2576 ARM_BUILTIN_WSUBH,
2577 ARM_BUILTIN_WSUBW,
2578 ARM_BUILTIN_WSUBSSB,
2579 ARM_BUILTIN_WSUBSSH,
2580 ARM_BUILTIN_WSUBSSW,
2581 ARM_BUILTIN_WSUBUSB,
2582 ARM_BUILTIN_WSUBUSH,
2583 ARM_BUILTIN_WSUBUSW,
2584
2585 ARM_BUILTIN_WAND,
2586 ARM_BUILTIN_WANDN,
2587 ARM_BUILTIN_WOR,
2588 ARM_BUILTIN_WXOR,
2589
2590 ARM_BUILTIN_WCMPEQB,
2591 ARM_BUILTIN_WCMPEQH,
2592 ARM_BUILTIN_WCMPEQW,
2593 ARM_BUILTIN_WCMPGTUB,
2594 ARM_BUILTIN_WCMPGTUH,
2595 ARM_BUILTIN_WCMPGTUW,
2596 ARM_BUILTIN_WCMPGTSB,
2597 ARM_BUILTIN_WCMPGTSH,
2598 ARM_BUILTIN_WCMPGTSW,
2599
2600 ARM_BUILTIN_TEXTRMSB,
2601 ARM_BUILTIN_TEXTRMSH,
2602 ARM_BUILTIN_TEXTRMSW,
2603 ARM_BUILTIN_TEXTRMUB,
2604 ARM_BUILTIN_TEXTRMUH,
2605 ARM_BUILTIN_TEXTRMUW,
2606 ARM_BUILTIN_TINSRB,
2607 ARM_BUILTIN_TINSRH,
2608 ARM_BUILTIN_TINSRW,
2609
2610 ARM_BUILTIN_WMAXSW,
2611 ARM_BUILTIN_WMAXSH,
2612 ARM_BUILTIN_WMAXSB,
2613 ARM_BUILTIN_WMAXUW,
2614 ARM_BUILTIN_WMAXUH,
2615 ARM_BUILTIN_WMAXUB,
2616 ARM_BUILTIN_WMINSW,
2617 ARM_BUILTIN_WMINSH,
2618 ARM_BUILTIN_WMINSB,
2619 ARM_BUILTIN_WMINUW,
2620 ARM_BUILTIN_WMINUH,
2621 ARM_BUILTIN_WMINUB,
2622
f07a6b21
BE		 2623 ARM_BUILTIN_WMULUM,
2624 ARM_BUILTIN_WMULSM,
5a9335ef
NC		 2625 ARM_BUILTIN_WMULUL,
2626
2627 ARM_BUILTIN_PSADBH,
2628 ARM_BUILTIN_WSHUFH,
2629
2630 ARM_BUILTIN_WSLLH,
2631 ARM_BUILTIN_WSLLW,
2632 ARM_BUILTIN_WSLLD,
2633 ARM_BUILTIN_WSRAH,
2634 ARM_BUILTIN_WSRAW,
2635 ARM_BUILTIN_WSRAD,
2636 ARM_BUILTIN_WSRLH,
2637 ARM_BUILTIN_WSRLW,
2638 ARM_BUILTIN_WSRLD,
2639 ARM_BUILTIN_WRORH,
2640 ARM_BUILTIN_WRORW,
2641 ARM_BUILTIN_WRORD,
2642 ARM_BUILTIN_WSLLHI,
2643 ARM_BUILTIN_WSLLWI,
2644 ARM_BUILTIN_WSLLDI,
2645 ARM_BUILTIN_WSRAHI,
2646 ARM_BUILTIN_WSRAWI,
2647 ARM_BUILTIN_WSRADI,
2648 ARM_BUILTIN_WSRLHI,
2649 ARM_BUILTIN_WSRLWI,
2650 ARM_BUILTIN_WSRLDI,
2651 ARM_BUILTIN_WRORHI,
2652 ARM_BUILTIN_WRORWI,
2653 ARM_BUILTIN_WRORDI,
2654
2655 ARM_BUILTIN_WUNPCKIHB,
2656 ARM_BUILTIN_WUNPCKIHH,
2657 ARM_BUILTIN_WUNPCKIHW,
2658 ARM_BUILTIN_WUNPCKILB,
2659 ARM_BUILTIN_WUNPCKILH,
2660 ARM_BUILTIN_WUNPCKILW,
2661
2662 ARM_BUILTIN_WUNPCKEHSB,
2663 ARM_BUILTIN_WUNPCKEHSH,
2664 ARM_BUILTIN_WUNPCKEHSW,
2665 ARM_BUILTIN_WUNPCKEHUB,
2666 ARM_BUILTIN_WUNPCKEHUH,
2667 ARM_BUILTIN_WUNPCKEHUW,
2668 ARM_BUILTIN_WUNPCKELSB,
2669 ARM_BUILTIN_WUNPCKELSH,
2670 ARM_BUILTIN_WUNPCKELSW,
2671 ARM_BUILTIN_WUNPCKELUB,
2672 ARM_BUILTIN_WUNPCKELUH,
2673 ARM_BUILTIN_WUNPCKELUW,
2674
2675 ARM_BUILTIN_MAX
2676};
88657302 2677#endif /* ! GCC_ARM_H */
Mirror of https://gcc.gnu.org/git/gcc.git