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[thirdparty/gcc.git] / gcc / config / arm / arm.h
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f5a1b0d2 1/* Definitions of target machine for GNU compiler, for ARM.
cf011243 2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
5b3e6663 3 2001, 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
35d965d5 4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
8b109b37 5 and Martin Simmons (@harleqn.co.uk).
949d79eb 6 More major hacks by Richard Earnshaw (rearnsha@arm.com)
6cfc7210
NC		 7 Minor hacks by Nick Clifton (nickc@cygnus.com)
8
4f448245 9 This file is part of GCC.
35d965d5 10
4f448245
NC		 11 GCC is free software; you can redistribute it and/or modify it
12 under the terms of the GNU General Public License as published
2f83c7d6 13 by the Free Software Foundation; either version 3, or (at your
4f448245 14 option) any later version.
35d965d5 15
4f448245
NC		 16 GCC is distributed in the hope that it will be useful, but WITHOUT
17 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
18 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
19 License for more details.
35d965d5 20
4f448245 21 You should have received a copy of the GNU General Public License
2f83c7d6
NC		 22 along with GCC; see the file COPYING3. If not see
23 <http://www.gnu.org/licenses/>. */
35d965d5 24
88657302
RH		 25#ifndef GCC_ARM_H
26#define GCC_ARM_H
b355a481 27
9403b7f7
RS		 28#include "config/vxworks-dummy.h"
29
35fd3193 30/* The architecture define. */
78011587
PB		 31extern char arm_arch_name[];
32
e6471be6
NB		 33/* Target CPU builtins. */
34#define TARGET_CPU_CPP_BUILTINS() \
35 do \
36 { \
9b66ebb1
PB		 37 /* Define __arm__ even when in thumb mode, for \
38 consistency with armcc. */ \
39 builtin_define ("__arm__"); \
61f0ccff 40 builtin_define ("__APCS_32__"); \
9b66ebb1 41 if (TARGET_THUMB) \
e6471be6 42 builtin_define ("__thumb__"); \
5b3e6663
PB		 43 if (TARGET_THUMB2) \
44 builtin_define ("__thumb2__"); \
e6471be6
NB		 45 \
46 if (TARGET_BIG_END) \
47 { \
48 builtin_define ("__ARMEB__"); \
49 if (TARGET_THUMB) \
50 builtin_define ("__THUMBEB__"); \
51 if (TARGET_LITTLE_WORDS) \
52 builtin_define ("__ARMWEL__"); \
53 } \
54 else \
55 { \
56 builtin_define ("__ARMEL__"); \
57 if (TARGET_THUMB) \
58 builtin_define ("__THUMBEL__"); \
59 } \
60 \
e6471be6
NB		 61 if (TARGET_SOFT_FLOAT) \
62 builtin_define ("__SOFTFP__"); \
63 \
9b66ebb1 64 if (TARGET_VFP) \
b5b620a4
JT		 65 builtin_define ("__VFP_FP__"); \
66 \
88f77cba
JB		 67 if (TARGET_NEON) \
68 builtin_define ("__ARM_NEON__"); \
69 \
e6471be6
NB		 70 /* Add a define for interworking. \
71 Needed when building libgcc.a. */ \
2ad4dcf9 72 if (arm_cpp_interwork) \
e6471be6
NB		 73 builtin_define ("__THUMB_INTERWORK__"); \
74 \
75 builtin_assert ("cpu=arm"); \
76 builtin_assert ("machine=arm"); \
78011587
PB		 77 \
78 builtin_define (arm_arch_name); \
79 if (arm_arch_cirrus) \
80 builtin_define ("__MAVERICK__"); \
81 if (arm_arch_xscale) \
82 builtin_define ("__XSCALE__"); \
83 if (arm_arch_iwmmxt) \
84 builtin_define ("__IWMMXT__"); \
4adf3e34
PB		 85 if (TARGET_AAPCS_BASED) \
86 builtin_define ("__ARM_EABI__"); \
e6471be6
NB		 87 } while (0)
88
9b66ebb1
PB		 89/* The various ARM cores. */
90enum processor_type
91{
d98a72fd
RE		 92#define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
93 IDENT,
9b66ebb1
PB		 94#include "arm-cores.def"
95#undef ARM_CORE
96 /* Used to indicate that no processor has been specified. */
97 arm_none
98};
99
78011587
PB		 100enum target_cpus
101{
d98a72fd
RE		 102#define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
103 TARGET_CPU_##IDENT,
78011587
PB		 104#include "arm-cores.def"
105#undef ARM_CORE
106 TARGET_CPU_generic
107};
108
9b66ebb1
PB		 109/* The processor for which instructions should be scheduled. */
110extern enum processor_type arm_tune;
111
d5b7b3ae 112typedef enum arm_cond_code
89c7ca52
RE		 113{
114 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC,
115 ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV
d5b7b3ae
RE		 116}
117arm_cc;
6cfc7210 118
d5b7b3ae 119extern arm_cc arm_current_cc;
ff9940b0 120
d5b7b3ae 121#define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1))
89c7ca52 122
6cfc7210
NC		 123extern int arm_target_label;
124extern int arm_ccfsm_state;
e2500fed 125extern GTY(()) rtx arm_target_insn;
d5b7b3ae 126/* Define the information needed to generate branch insns. This is
e2500fed
GK		 127 stored from the compare operation. */
128extern GTY(()) rtx arm_compare_op0;
129extern GTY(()) rtx arm_compare_op1;
d5b7b3ae 130/* The label of the current constant pool. */
e2500fed 131extern rtx pool_vector_label;
d5b7b3ae 132/* Set to 1 when a return insn is output, this means that the epilogue
d6b4baa4 133 is not needed. */
d5b7b3ae 134extern int return_used_this_function;
e2500fed
GK		 135/* Used to produce AOF syntax assembler. */
136extern GTY(()) rtx aof_pic_label;
35d965d5 137\f
d6b4baa4 138/* Just in case configure has failed to define anything. */
7a801826
RE		 139#ifndef TARGET_CPU_DEFAULT
140#define TARGET_CPU_DEFAULT TARGET_CPU_generic
141#endif
142
7a801826 143
5742588d 144#undef CPP_SPEC
78011587 145#define CPP_SPEC "%(subtarget_cpp_spec) \
e6471be6
NB		 146%{msoft-float:%{mhard-float: \
147 %e-msoft-float and -mhard_float may not be used together}} \
148%{mbig-endian:%{mlittle-endian: \
149 %e-mbig-endian and -mlittle-endian may not be used together}}"
7a801826 150
be393ecf 151#ifndef CC1_SPEC
dfa08768 152#define CC1_SPEC ""
be393ecf 153#endif
7a801826
RE		 154
155/* This macro defines names of additional specifications to put in the specs
156 that can be used in various specifications like CC1_SPEC. Its definition
157 is an initializer with a subgrouping for each command option.
158
159 Each subgrouping contains a string constant, that defines the
4f448245 160 specification name, and a string constant that used by the GCC driver
7a801826
RE		 161 program.
162
163 Do not define this macro if it does not need to do anything. */
164#define EXTRA_SPECS \
38fc909b 165 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
7a801826
RE		 166 SUBTARGET_EXTRA_SPECS
167
914a3b8c 168#ifndef SUBTARGET_EXTRA_SPECS
7a801826 169#define SUBTARGET_EXTRA_SPECS
914a3b8c
DM		 170#endif
171
6cfc7210 172#ifndef SUBTARGET_CPP_SPEC
38fc909b 173#define SUBTARGET_CPP_SPEC ""
6cfc7210 174#endif
35d965d5
RS		 175\f
176/* Run-time Target Specification. */
ff9940b0 177#ifndef TARGET_VERSION
6cfc7210 178#define TARGET_VERSION fputs (" (ARM/generic)", stderr);
ff9940b0 179#endif
35d965d5 180
9b66ebb1 181#define TARGET_SOFT_FLOAT (arm_float_abi == ARM_FLOAT_ABI_SOFT)
72cdc543
PB		 182/* Use hardware floating point instructions. */
183#define TARGET_HARD_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT)
184/* Use hardware floating point calling convention. */
185#define TARGET_HARD_FLOAT_ABI (arm_float_abi == ARM_FLOAT_ABI_HARD)
9b66ebb1
PB		 186#define TARGET_FPA (arm_fp_model == ARM_FP_MODEL_FPA)
187#define TARGET_MAVERICK (arm_fp_model == ARM_FP_MODEL_MAVERICK)
188#define TARGET_VFP (arm_fp_model == ARM_FP_MODEL_VFP)
5a9335ef 189#define TARGET_IWMMXT (arm_arch_iwmmxt)
5b3e6663
PB		 190#define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_32BIT)
191#define TARGET_IWMMXT_ABI (TARGET_32BIT && arm_abi == ARM_ABI_IWMMXT)
d5b7b3ae
RE		 192#define TARGET_ARM (! TARGET_THUMB)
193#define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */
c54c7322
RS		 194#define TARGET_BACKTRACE (leaf_function_p () \
195 ? TARGET_TPCS_LEAF_FRAME \
196 : TARGET_TPCS_FRAME)
fdd695fd 197#define TARGET_LDRD (arm_arch5e && ARM_DOUBLEWORD_ALIGN)
b6685939
PB		 198#define TARGET_AAPCS_BASED \
199 (arm_abi != ARM_ABI_APCS && arm_abi != ARM_ABI_ATPCS)
3ada8e17 200
d3585b76
DJ		 201#define TARGET_HARD_TP (target_thread_pointer == TP_CP15)
202#define TARGET_SOFT_TP (target_thread_pointer == TP_SOFT)
203
5b3e6663
PB		 204/* Only 16-bit thumb code. */
205#define TARGET_THUMB1 (TARGET_THUMB && !arm_arch_thumb2)
206/* Arm or Thumb-2 32-bit code. */
207#define TARGET_32BIT (TARGET_ARM || arm_arch_thumb2)
208/* 32-bit Thumb-2 code. */
209#define TARGET_THUMB2 (TARGET_THUMB && arm_arch_thumb2)
210
88f77cba
JB		 211/* The following two macros concern the ability to execute coprocessor
212 instructions for VFPv3 or NEON. TARGET_VFP3 is currently only ever
213 tested when we know we are generating for VFP hardware; we need to
214 be more careful with TARGET_NEON as noted below. */
215
f1adb0a9
JB		 216/* FPU is VFPv3 (with twice the number of D registers). Setting the FPU to
217 Neon automatically enables VFPv3 too. */
218#define TARGET_VFP3 (arm_fp_model == ARM_FP_MODEL_VFP \
88f77cba
JB		 219 && (arm_fpu_arch == FPUTYPE_VFP3 \
220 || arm_fpu_arch == FPUTYPE_NEON))
221/* FPU supports Neon instructions. The setting of this macro gets
222 revealed via __ARM_NEON__ so we add extra guards upon TARGET_32BIT
223 and TARGET_HARD_FLOAT to ensure that NEON instructions are
224 available. */
225#define TARGET_NEON (TARGET_32BIT && TARGET_HARD_FLOAT \
226 && arm_fp_model == ARM_FP_MODEL_VFP \
227 && arm_fpu_arch == FPUTYPE_NEON)
f1adb0a9 228
5b3e6663
PB		 229/* "DSP" multiply instructions, eg. SMULxy. */
230#define TARGET_DSP_MULTIPLY \
231 (TARGET_32BIT && arm_arch5e && arm_arch_notm)
232/* Integer SIMD instructions, and extend-accumulate instructions. */
233#define TARGET_INT_SIMD \
234 (TARGET_32BIT && arm_arch6 && arm_arch_notm)
235
236/* We could use unified syntax for arm mode, but for now we just use it
237 for Thumb-2. */
238#define TARGET_UNIFIED_ASM TARGET_THUMB2
239
240
b3f8d95d
MM		 241/* True iff the full BPABI is being used. If TARGET_BPABI is true,
242 then TARGET_AAPCS_BASED must be true -- but the converse does not
243 hold. TARGET_BPABI implies the use of the BPABI runtime library,
244 etc., in addition to just the AAPCS calling conventions. */
245#ifndef TARGET_BPABI
246#define TARGET_BPABI false
f676971a 247#endif
b3f8d95d 248
7816bea0
DJ		 249/* Support for a compile-time default CPU, et cetera. The rules are:
250 --with-arch is ignored if -march or -mcpu are specified.
251 --with-cpu is ignored if -march or -mcpu are specified, and is overridden
252 by --with-arch.
253 --with-tune is ignored if -mtune or -mcpu are specified (but not affected
254 by -march).
9b66ebb1
PB		 255 --with-float is ignored if -mhard-float, -msoft-float or -mfloat-abi are
256 specified.
5848830f
PB		 257 --with-fpu is ignored if -mfpu is specified.
258 --with-abi is ignored is -mabi is specified. */
7816bea0
DJ		 259#define OPTION_DEFAULT_SPECS \
260 {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \
261 {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \
262 {"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}" }, \
9b66ebb1
PB		 263 {"float", \
264 "%{!msoft-float:%{!mhard-float:%{!mfloat-abi=*:-mfloat-abi=%(VALUE)}}}" }, \
5848830f 265 {"fpu", "%{!mfpu=*:-mfpu=%(VALUE)}"}, \
3cf94279
PB		 266 {"abi", "%{!mabi=*:-mabi=%(VALUE)}"}, \
267 {"mode", "%{!marm:%{!mthumb:-m%(VALUE)}}"},
7816bea0 268
9b66ebb1
PB		 269/* Which floating point model to use. */
270enum arm_fp_model
271{
272 ARM_FP_MODEL_UNKNOWN,
273 /* FPA model (Hardware or software). */
274 ARM_FP_MODEL_FPA,
275 /* Cirrus Maverick floating point model. */
276 ARM_FP_MODEL_MAVERICK,
277 /* VFP floating point model. */
278 ARM_FP_MODEL_VFP
279};
280
281extern enum arm_fp_model arm_fp_model;
282
283/* Which floating point hardware is available. Also update
284 fp_model_for_fpu in arm.c when adding entries to this list. */
29ad9694 285enum fputype
24f0c1b4 286{
9b66ebb1
PB		 287 /* No FP hardware. */
288 FPUTYPE_NONE,
29ad9694
RE		 289 /* Full FPA support. */
290 FPUTYPE_FPA,
291 /* Emulated FPA hardware, Issue 2 emulator (no LFM/SFM). */
292 FPUTYPE_FPA_EMU2,
293 /* Emulated FPA hardware, Issue 3 emulator. */
294 FPUTYPE_FPA_EMU3,
295 /* Cirrus Maverick floating point co-processor. */
9b66ebb1
PB		 296 FPUTYPE_MAVERICK,
297 /* VFP. */
f1adb0a9
JB		 298 FPUTYPE_VFP,
299 /* VFPv3. */
88f77cba
JB		 300 FPUTYPE_VFP3,
301 /* Neon. */
302 FPUTYPE_NEON
24f0c1b4
RE		 303};
304
305/* Recast the floating point class to be the floating point attribute. */
29ad9694 306#define arm_fpu_attr ((enum attr_fpu) arm_fpu_tune)
24f0c1b4 307
71791e16 308/* What type of floating point to tune for */
29ad9694 309extern enum fputype arm_fpu_tune;
24f0c1b4 310
71791e16 311/* What type of floating point instructions are available */
29ad9694 312extern enum fputype arm_fpu_arch;
71791e16 313
9b66ebb1
PB		 314enum float_abi_type
315{
316 ARM_FLOAT_ABI_SOFT,
317 ARM_FLOAT_ABI_SOFTFP,
318 ARM_FLOAT_ABI_HARD
319};
320
321extern enum float_abi_type arm_float_abi;
322
3d8532aa
PB		 323#ifndef TARGET_DEFAULT_FLOAT_ABI
324#define TARGET_DEFAULT_FLOAT_ABI ARM_FLOAT_ABI_SOFT
325#endif
326
5848830f
PB		 327/* Which ABI to use. */
328enum arm_abi_type
329{
330 ARM_ABI_APCS,
331 ARM_ABI_ATPCS,
332 ARM_ABI_AAPCS,
077fc835
KH		 333 ARM_ABI_IWMMXT,
334 ARM_ABI_AAPCS_LINUX
5848830f
PB		 335};
336
337extern enum arm_abi_type arm_abi;
338
339#ifndef ARM_DEFAULT_ABI
340#define ARM_DEFAULT_ABI ARM_ABI_APCS
341#endif
342
d3585b76
DJ		 343/* Which thread pointer access sequence to use. */
344enum arm_tp_type {
345 TP_AUTO,
346 TP_SOFT,
347 TP_CP15
348};
349
350extern enum arm_tp_type target_thread_pointer;
351
9b66ebb1
PB		 352/* Nonzero if this chip supports the ARM Architecture 3M extensions. */
353extern int arm_arch3m;
11c1a207 354
9b66ebb1 355/* Nonzero if this chip supports the ARM Architecture 4 extensions. */
11c1a207
RE		 356extern int arm_arch4;
357
68d560d4
RE		 358/* Nonzero if this chip supports the ARM Architecture 4T extensions. */
359extern int arm_arch4t;
360
9b66ebb1 361/* Nonzero if this chip supports the ARM Architecture 5 extensions. */
62b10bbc
NC		 362extern int arm_arch5;
363
9b66ebb1 364/* Nonzero if this chip supports the ARM Architecture 5E extensions. */
b15bca31
RE		 365extern int arm_arch5e;
366
9b66ebb1
PB		 367/* Nonzero if this chip supports the ARM Architecture 6 extensions. */
368extern int arm_arch6;
369
5b3e6663
PB		 370/* Nonzero if instructions not present in the 'M' profile can be used. */
371extern int arm_arch_notm;
372
f5a1b0d2
NC		 373/* Nonzero if this chip can benefit from load scheduling. */
374extern int arm_ld_sched;
375
0616531f
RE		 376/* Nonzero if generating thumb code. */
377extern int thumb_code;
378
f5a1b0d2 379/* Nonzero if this chip is a StrongARM. */
abac3b49 380extern int arm_tune_strongarm;
f5a1b0d2 381
9b6b54e2 382/* Nonzero if this chip is a Cirrus variant. */
78011587 383extern int arm_arch_cirrus;
9b6b54e2 384
5a9335ef
NC		 385/* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */
386extern int arm_arch_iwmmxt;
387
d19fb8e3 388/* Nonzero if this chip is an XScale. */
4b3c2e48
PB		 389extern int arm_arch_xscale;
390
abac3b49 391/* Nonzero if tuning for XScale. */
4b3c2e48 392extern int arm_tune_xscale;
d19fb8e3 393
abac3b49
RE		 394/* Nonzero if tuning for stores via the write buffer. */
395extern int arm_tune_wbuf;
f5a1b0d2 396
2ad4dcf9 397/* Nonzero if we should define __THUMB_INTERWORK__ in the
f676971a 398 preprocessor.
2ad4dcf9
RE		 399 XXX This is a bit of a hack, it's intended to help work around
400 problems in GLD which doesn't understand that armv5t code is
401 interworking clean. */
402extern int arm_cpp_interwork;
403
5b3e6663
PB		 404/* Nonzero if chip supports Thumb 2. */
405extern int arm_arch_thumb2;
406
407/* Nonzero if chip supports integer division instruction. */
408extern int arm_arch_hwdiv;
409
2ce9c1b9 410#ifndef TARGET_DEFAULT
c54c7322 411#define TARGET_DEFAULT (MASK_APCS_FRAME)
2ce9c1b9 412#endif
35d965d5 413
11c1a207
RE		 414/* The frame pointer register used in gcc has nothing to do with debugging;
415 that is controlled by the APCS-FRAME option. */
d5b7b3ae 416#define CAN_DEBUG_WITHOUT_FP
35d965d5 417
11c1a207 418#define OVERRIDE_OPTIONS arm_override_options ()
86efdc8e
PB		 419
420/* Nonzero if PIC code requires explicit qualifiers to generate
421 PLT and GOT relocs rather than the assembler doing so implicitly.
ed0e6530
PB		 422 Subtargets can override these if required. */
423#ifndef NEED_GOT_RELOC
424#define NEED_GOT_RELOC 0
425#endif
426#ifndef NEED_PLT_RELOC
427#define NEED_PLT_RELOC 0
e2723c62 428#endif
84306176
PB		 429
430/* Nonzero if we need to refer to the GOT with a PC-relative
431 offset. In other words, generate
432
f676971a 433 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)]
84306176
PB		 434
435 rather than
436
437 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8)
438
f676971a 439 The default is true, which matches NetBSD. Subtargets can
84306176
PB		 440 override this if required. */
441#ifndef GOT_PCREL
442#define GOT_PCREL 1
443#endif
35d965d5
RS		 444\f
445/* Target machine storage Layout. */
446
ff9940b0
RE		 447
448/* Define this macro if it is advisable to hold scalars in registers
449 in a wider mode than that declared by the program. In such cases,
450 the value is constrained to be within the bounds of the declared
451 type, but kept valid in the wider mode. The signedness of the
452 extension may differ from that of the type. */
453
454/* It is far faster to zero extend chars than to sign extend them */
455
6cfc7210 456#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
2ce9c1b9
RE		 457 if (GET_MODE_CLASS (MODE) == MODE_INT \
458 && GET_MODE_SIZE (MODE) < 4) \
459 { \
460 if (MODE == QImode) \
461 UNSIGNEDP = 1; \
462 else if (MODE == HImode) \
61f0ccff 463 UNSIGNEDP = 1; \
2ce9c1b9 464 (MODE) = SImode; \
ff9940b0
RE		 465 }
466
d4453b7a 467#define PROMOTE_FUNCTION_MODE(MODE, UNSIGNEDP, TYPE) \
866af8a9
JB		 468 if ((GET_MODE_CLASS (MODE) == MODE_INT \
469 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_INT) \
470 && GET_MODE_SIZE (MODE) < 4) \
471 (MODE) = SImode; \
d4453b7a 472
35d965d5
RS		 473/* Define this if most significant bit is lowest numbered
474 in instructions that operate on numbered bit-fields. */
475#define BITS_BIG_ENDIAN 0
476
f676971a 477/* Define this if most significant byte of a word is the lowest numbered.
3ada8e17
DE		 478 Most ARM processors are run in little endian mode, so that is the default.
479 If you want to have it run-time selectable, change the definition in a
480 cover file to be TARGET_BIG_ENDIAN. */
11c1a207 481#define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
35d965d5
RS		 482
483/* Define this if most significant word of a multiword number is the lowest
11c1a207
RE		 484 numbered.
485 This is always false, even when in big-endian mode. */
ddee6aba
RE		 486#define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS)
487
488/* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based
489 on processor pre-defineds when compiling libgcc2.c. */
490#if defined(__ARMEB__) && !defined(__ARMWEL__)
491#define LIBGCC2_WORDS_BIG_ENDIAN 1
492#else
493#define LIBGCC2_WORDS_BIG_ENDIAN 0
494#endif
35d965d5 495
11c1a207 496/* Define this if most significant word of doubles is the lowest numbered.
f0375c66
NC		 497 The rules are different based on whether or not we use FPA-format,
498 VFP-format or some other floating point co-processor's format doubles. */
b5b620a4 499#define FLOAT_WORDS_BIG_ENDIAN (arm_float_words_big_endian ())
7fc6c9f0 500
35d965d5
RS		 501#define UNITS_PER_WORD 4
502
88f77cba
JB		 503/* Use the option -mvectorize-with-neon-quad to override the use of doubleword
504 registers when autovectorizing for Neon, at least until multiple vector
505 widths are supported properly by the middle-end. */
506#define UNITS_PER_SIMD_WORD \
507 (TARGET_NEON ? (TARGET_NEON_VECTORIZE_QUAD ? 16 : 8) : UNITS_PER_WORD)
508
5848830f 509/* True if natural alignment is used for doubleword types. */
b6685939
PB		 510#define ARM_DOUBLEWORD_ALIGN TARGET_AAPCS_BASED
511
5848830f 512#define DOUBLEWORD_ALIGNMENT 64
35d965d5 513
5848830f 514#define PARM_BOUNDARY 32
5a9335ef 515
5848830f 516#define STACK_BOUNDARY (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
35d965d5 517
5848830f
PB		 518#define PREFERRED_STACK_BOUNDARY \
519 (arm_abi == ARM_ABI_ATPCS ? 64 : STACK_BOUNDARY)
0977774b 520
35d965d5
RS		 521#define FUNCTION_BOUNDARY 32
522
92928d71
AO		 523/* The lowest bit is used to indicate Thumb-mode functions, so the
524 vbit must go into the delta field of pointers to member
525 functions. */
526#define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
527
35d965d5
RS		 528#define EMPTY_FIELD_BOUNDARY 32
529
5848830f 530#define BIGGEST_ALIGNMENT (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
5a9335ef 531
27847754
NC		 532/* XXX Blah -- this macro is used directly by libobjc. Since it
533 supports no vector modes, cut out the complexity and fall back
534 on BIGGEST_FIELD_ALIGNMENT. */
535#ifdef IN_TARGET_LIBS
8fca31a2 536#define BIGGEST_FIELD_ALIGNMENT 64
27847754 537#endif
5a9335ef 538
ff9940b0 539/* Make strings word-aligned so strcpy from constants will be faster. */
591af218 540#define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_tune_xscale ? 1 : 2)
f676971a 541
d19fb8e3 542#define CONSTANT_ALIGNMENT(EXP, ALIGN) \
5848830f 543 ((TREE_CODE (EXP) == STRING_CST \
36b15ad0 544 && !optimize_size \
5848830f
PB		 545 && (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \
546 ? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN))
ff9940b0 547
723ae7c1
NC		 548/* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the
549 value set in previous versions of this toolchain was 8, which produces more
550 compact structures. The command line option -mstructure_size_boundary=<n>
f710504c 551 can be used to change this value. For compatibility with the ARM SDK
723ae7c1 552 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI
5848830f
PB		 553 0020D) page 2-20 says "Structures are aligned on word boundaries".
554 The AAPCS specifies a value of 8. */
6ead9ba5
NC		 555#define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary
556extern int arm_structure_size_boundary;
723ae7c1 557
4912a07c 558/* This is the value used to initialize arm_structure_size_boundary. If a
723ae7c1 559 particular arm target wants to change the default value it should change
6bc82793 560 the definition of this macro, not STRUCTURE_SIZE_BOUNDARY. See netbsd.h
723ae7c1
NC		 561 for an example of this. */
562#ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY
563#define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32
b355a481 564#endif
2a5307b1 565
825dda42 566/* Nonzero if move instructions will actually fail to work
ff9940b0 567 when given unaligned data. */
35d965d5 568#define STRICT_ALIGNMENT 1
b6685939
PB		 569
570/* wchar_t is unsigned under the AAPCS. */
571#ifndef WCHAR_TYPE
572#define WCHAR_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "int")
573
574#define WCHAR_TYPE_SIZE BITS_PER_WORD
575#endif
576
577#ifndef SIZE_TYPE
578#define SIZE_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "long unsigned int")
579#endif
d81d0bdd 580
077fc835
KH		 581#ifndef PTRDIFF_TYPE
582#define PTRDIFF_TYPE (TARGET_AAPCS_BASED ? "int" : "long int")
583#endif
584
d81d0bdd
PB		 585/* AAPCS requires that structure alignment is affected by bitfields. */
586#ifndef PCC_BITFIELD_TYPE_MATTERS
587#define PCC_BITFIELD_TYPE_MATTERS TARGET_AAPCS_BASED
588#endif
589
35d965d5
RS		 590\f
591/* Standard register usage. */
592
593/* Register allocation in ARM Procedure Call Standard (as used on RISCiX):
594 (S - saved over call).
595
596 r0 * argument word/integer result
597 r1-r3 argument word
598
599 r4-r8 S register variable
600 r9 S (rfp) register variable (real frame pointer)
f676971a 601
f5a1b0d2 602 r10 F S (sl) stack limit (used by -mapcs-stack-check)
35d965d5
RS		 603 r11 F S (fp) argument pointer
604 r12 (ip) temp workspace
605 r13 F S (sp) lower end of current stack frame
606 r14 (lr) link address/workspace
607 r15 F (pc) program counter
608
609 f0 floating point result
610 f1-f3 floating point scratch
611
612 f4-f7 S floating point variable
613
ff9940b0
RE		 614 cc This is NOT a real register, but is used internally
615 to represent things that use or set the condition
616 codes.
617 sfp This isn't either. It is used during rtl generation
618 since the offset between the frame pointer and the
619 auto's isn't known until after register allocation.
620 afp Nor this, we only need this because of non-local
621 goto. Without it fp appears to be used and the
622 elimination code won't get rid of sfp. It tracks
623 fp exactly at all times.
624
35d965d5
RS		 625 *: See CONDITIONAL_REGISTER_USAGE */
626
9b6b54e2
NC		 627/*
628 mvf0 Cirrus floating point result
629 mvf1-mvf3 Cirrus floating point scratch
630 mvf4-mvf15 S Cirrus floating point variable. */
631
9b66ebb1
PB		 632/* s0-s15 VFP scratch (aka d0-d7).
633 s16-s31 S VFP variable (aka d8-d15).
634 vfpcc Not a real register. Represents the VFP condition
635 code flags. */
636
ff9940b0
RE		 637/* The stack backtrace structure is as follows:
638 fp points to here: | save code pointer | [fp]
639 | return link value | [fp, #-4]
640 | return sp value | [fp, #-8]
641 | return fp value | [fp, #-12]
642 [| saved r10 value |]
643 [| saved r9 value |]
644 [| saved r8 value |]
645 [| saved r7 value |]
646 [| saved r6 value |]
647 [| saved r5 value |]
648 [| saved r4 value |]
649 [| saved r3 value |]
650 [| saved r2 value |]
651 [| saved r1 value |]
652 [| saved r0 value |]
653 [| saved f7 value |] three words
654 [| saved f6 value |] three words
655 [| saved f5 value |] three words
656 [| saved f4 value |] three words
657 r0-r3 are not normally saved in a C function. */
658
35d965d5
RS		 659/* 1 for registers that have pervasive standard uses
660 and are not available for the register allocator. */
9b66ebb1
PB		 661#define FIXED_REGISTERS \
662{ \
663 0,0,0,0,0,0,0,0, \
664 0,0,0,0,0,1,0,1, \
665 0,0,0,0,0,0,0,0, \
9b6b54e2
NC		 666 1,1,1, \
667 1,1,1,1,1,1,1,1, \
9b66ebb1
PB		 668 1,1,1,1,1,1,1,1, \
669 1,1,1,1,1,1,1,1, \
670 1,1,1,1,1,1,1,1, \
671 1,1,1,1, \
672 1,1,1,1,1,1,1,1, \
673 1,1,1,1,1,1,1,1, \
674 1,1,1,1,1,1,1,1, \
675 1,1,1,1,1,1,1,1, \
f1adb0a9
JB		 676 1,1,1,1,1,1,1,1, \
677 1,1,1,1,1,1,1,1, \
678 1,1,1,1,1,1,1,1, \
679 1,1,1,1,1,1,1,1, \
9b66ebb1 680 1 \
35d965d5
RS		 681}
682
683/* 1 for registers not available across function calls.
684 These must include the FIXED_REGISTERS and also any
685 registers that can be used without being saved.
686 The latter must include the registers where values are returned
687 and the register where structure-value addresses are passed.
ff9940b0 688 Aside from that, you can include as many other registers as you like.
f676971a 689 The CC is not preserved over function calls on the ARM 6, so it is
d6b4baa4 690 easier to assume this for all. SFP is preserved, since FP is. */
35d965d5
RS		 691#define CALL_USED_REGISTERS \
692{ \
693 1,1,1,1,0,0,0,0, \
d5b7b3ae 694 0,0,0,0,1,1,1,1, \
ff9940b0 695 1,1,1,1,0,0,0,0, \
9b6b54e2
NC		 696 1,1,1, \
697 1,1,1,1,1,1,1,1, \
5a9335ef
NC		 698 1,1,1,1,1,1,1,1, \
699 1,1,1,1,1,1,1,1, \
700 1,1,1,1,1,1,1,1, \
9b66ebb1
PB		 701 1,1,1,1, \
702 1,1,1,1,1,1,1,1, \
703 1,1,1,1,1,1,1,1, \
704 1,1,1,1,1,1,1,1, \
705 1,1,1,1,1,1,1,1, \
f1adb0a9
JB		 706 1,1,1,1,1,1,1,1, \
707 1,1,1,1,1,1,1,1, \
708 1,1,1,1,1,1,1,1, \
709 1,1,1,1,1,1,1,1, \
9b66ebb1 710 1 \
35d965d5
RS		 711}
712
6cc8c0b3
NC		 713#ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE
714#define SUBTARGET_CONDITIONAL_REGISTER_USAGE
715#endif
716
d5b7b3ae
RE		 717#define CONDITIONAL_REGISTER_USAGE \
718{ \
4b02997f
NC		 719 int regno; \
720 \
5b3e6663 721 if (TARGET_SOFT_FLOAT || TARGET_THUMB1 || !TARGET_FPA) \
d5b7b3ae 722 { \
9b66ebb1
PB		 723 for (regno = FIRST_FPA_REGNUM; \
724 regno <= LAST_FPA_REGNUM; ++regno) \
d5b7b3ae
RE		 725 fixed_regs[regno] = call_used_regs[regno] = 1; \
726 } \
9b6b54e2 727 \
c769a35d
RE		 728 if (TARGET_THUMB && optimize_size) \
729 { \
730 /* When optimizing for size, it's better not to use \
731 the HI regs, because of the overhead of stacking \
d6b4baa4 732 them. */ \
5b3e6663 733 /* ??? Is this still true for thumb2? */ \
c769a35d
RE		 734 for (regno = FIRST_HI_REGNUM; \
735 regno <= LAST_HI_REGNUM; ++regno) \
736 fixed_regs[regno] = call_used_regs[regno] = 1; \
737 } \
738 \
fb14bc89
RE		 739 /* The link register can be clobbered by any branch insn, \
740 but we have no way to track that at present, so mark \
741 it as unavailable. */ \
5b3e6663 742 if (TARGET_THUMB1) \
fb14bc89
RE		 743 fixed_regs[LR_REGNUM] = call_used_regs[LR_REGNUM] = 1; \
744 \
5b3e6663 745 if (TARGET_32BIT && TARGET_HARD_FLOAT) \
9b6b54e2 746 { \
9b66ebb1 747 if (TARGET_MAVERICK) \
9b6b54e2 748 { \
9b66ebb1
PB		 749 for (regno = FIRST_FPA_REGNUM; \
750 regno <= LAST_FPA_REGNUM; ++ regno) \
751 fixed_regs[regno] = call_used_regs[regno] = 1; \
752 for (regno = FIRST_CIRRUS_FP_REGNUM; \
753 regno <= LAST_CIRRUS_FP_REGNUM; ++ regno) \
754 { \
755 fixed_regs[regno] = 0; \
756 call_used_regs[regno] = regno < FIRST_CIRRUS_FP_REGNUM + 4; \
757 } \
758 } \
759 if (TARGET_VFP) \
760 { \
f1adb0a9
JB		 761 /* VFPv3 registers are disabled when earlier VFP \
762 versions are selected due to the definition of \
763 LAST_VFP_REGNUM. */ \
9b66ebb1
PB		 764 for (regno = FIRST_VFP_REGNUM; \
765 regno <= LAST_VFP_REGNUM; ++ regno) \
766 { \
767 fixed_regs[regno] = 0; \
f1adb0a9
JB		 768 call_used_regs[regno] = regno < FIRST_VFP_REGNUM + 16 \
769 || regno >= FIRST_VFP_REGNUM + 32; \
9b66ebb1 770 } \
9b6b54e2
NC		 771 } \
772 } \
773 \
5a9335ef
NC		 774 if (TARGET_REALLY_IWMMXT) \
775 { \
776 regno = FIRST_IWMMXT_GR_REGNUM; \
777 /* The 2002/10/09 revision of the XScale ABI has wCG0 \
778 and wCG1 as call-preserved registers. The 2002/11/21 \
779 revision changed this so that all wCG registers are \
780 scratch registers. */ \
781 for (regno = FIRST_IWMMXT_GR_REGNUM; \
782 regno <= LAST_IWMMXT_GR_REGNUM; ++ regno) \
119bb233 783 fixed_regs[regno] = 0; \
5a9335ef
NC		 784 /* The XScale ABI has wR0 - wR9 as scratch registers, \
785 the rest as call-preserved registers. */ \
786 for (regno = FIRST_IWMMXT_REGNUM; \
787 regno <= LAST_IWMMXT_REGNUM; ++ regno) \
788 { \
789 fixed_regs[regno] = 0; \
790 call_used_regs[regno] = regno < FIRST_IWMMXT_REGNUM + 10; \
791 } \
792 } \
793 \
fc555370 794 if ((unsigned) PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
d5b7b3ae
RE		 795 { \
796 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
797 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
798 } \
799 else if (TARGET_APCS_STACK) \
800 { \
801 fixed_regs[10] = 1; \
802 call_used_regs[10] = 1; \
803 } \
a2503645
RS		 804 /* -mcaller-super-interworking reserves r11 for calls to \
805 _interwork_r11_call_via_rN(). Making the register global \
806 is an easy way of ensuring that it remains valid for all \
807 calls. */ \
685c9c11 808 if (TARGET_APCS_FRAME || TARGET_CALLER_INTERWORKING \
c54c7322 809 || TARGET_TPCS_FRAME || TARGET_TPCS_LEAF_FRAME) \
d5b7b3ae
RE		 810 { \
811 fixed_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
812 call_used_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
a2503645
RS		 813 if (TARGET_CALLER_INTERWORKING) \
814 global_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
d5b7b3ae
RE		 815 } \
816 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
35d965d5 817}
f676971a 818
6bc82793 819/* These are a couple of extensions to the formats accepted
dd18ae56
NC		 820 by asm_fprintf:
821 %@ prints out ASM_COMMENT_START
822 %r prints out REGISTER_PREFIX reg_names[arg] */
823#define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \
824 case '@': \
825 fputs (ASM_COMMENT_START, FILE); \
826 break; \
827 \
828 case 'r': \
829 fputs (REGISTER_PREFIX, FILE); \
830 fputs (reg_names [va_arg (ARGS, int)], FILE); \
831 break;
832
d5b7b3ae 833/* Round X up to the nearest word. */
0c2ca901 834#define ROUND_UP_WORD(X) (((X) + 3) & ~3)
d5b7b3ae 835
6cfc7210 836/* Convert fron bytes to ints. */
e9d7b180 837#define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
6cfc7210 838
9b66ebb1
PB		 839/* The number of (integer) registers required to hold a quantity of type MODE.
840 Also used for VFP registers. */
e9d7b180
JD		 841#define ARM_NUM_REGS(MODE) \
842 ARM_NUM_INTS (GET_MODE_SIZE (MODE))
6cfc7210
NC		 843
844/* The number of (integer) registers required to hold a quantity of TYPE MODE. */
e9d7b180
JD		 845#define ARM_NUM_REGS2(MODE, TYPE) \
846 ARM_NUM_INTS ((MODE) == BLKmode ? \
d5b7b3ae 847 int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE))
6cfc7210
NC		 848
849/* The number of (integer) argument register available. */
d5b7b3ae 850#define NUM_ARG_REGS 4
6cfc7210 851
093354e0 852/* Return the register number of the N'th (integer) argument. */
d5b7b3ae 853#define ARG_REGISTER(N) (N - 1)
6cfc7210 854
d5b7b3ae
RE		 855/* Specify the registers used for certain standard purposes.
856 The values of these macros are register numbers. */
35d965d5 857
d5b7b3ae
RE		 858/* The number of the last argument register. */
859#define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS)
35d965d5 860
c769a35d
RE		 861/* The numbers of the Thumb register ranges. */
862#define FIRST_LO_REGNUM 0
6d3d9133 863#define LAST_LO_REGNUM 7
c769a35d
RE		 864#define FIRST_HI_REGNUM 8
865#define LAST_HI_REGNUM 11
6d3d9133 866
617a1b71 867#ifndef TARGET_UNWIND_INFO
c9ca9b88
PB		 868/* We use sjlj exceptions for backwards compatibility. */
869#define MUST_USE_SJLJ_EXCEPTIONS 1
617a1b71
PB		 870#endif
871
c9ca9b88
PB		 872/* We can generate DWARF2 Unwind info, even though we don't use it. */
873#define DWARF2_UNWIND_INFO 1
f676971a 874
c9ca9b88
PB		 875/* Use r0 and r1 to pass exception handling information. */
876#define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? N : INVALID_REGNUM)
877
6d3d9133 878/* The register that holds the return address in exception handlers. */
c9ca9b88
PB		 879#define ARM_EH_STACKADJ_REGNUM 2
880#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (SImode, ARM_EH_STACKADJ_REGNUM)
35d965d5 881
d5b7b3ae
RE		 882/* The native (Norcroft) Pascal compiler for the ARM passes the static chain
883 as an invisible last argument (possible since varargs don't exist in
884 Pascal), so the following is not true. */
5b3e6663 885#define STATIC_CHAIN_REGNUM 12
35d965d5 886
d5b7b3ae
RE		 887/* Define this to be where the real frame pointer is if it is not possible to
888 work out the offset between the frame pointer and the automatic variables
889 until after register allocation has taken place. FRAME_POINTER_REGNUM
890 should point to a special register that we will make sure is eliminated.
891
892 For the Thumb we have another problem. The TPCS defines the frame pointer
6bc82793 893 as r11, and GCC believes that it is always possible to use the frame pointer
d5b7b3ae
RE		 894 as base register for addressing purposes. (See comments in
895 find_reloads_address()). But - the Thumb does not allow high registers,
896 including r11, to be used as base address registers. Hence our problem.
897
898 The solution used here, and in the old thumb port is to use r7 instead of
899 r11 as the hard frame pointer and to have special code to generate
900 backtrace structures on the stack (if required to do so via a command line
6bc82793 901 option) using r11. This is the only 'user visible' use of r11 as a frame
d5b7b3ae
RE		 902 pointer. */
903#define ARM_HARD_FRAME_POINTER_REGNUM 11
904#define THUMB_HARD_FRAME_POINTER_REGNUM 7
35d965d5 905
b15bca31
RE		 906#define HARD_FRAME_POINTER_REGNUM \
907 (TARGET_ARM \
908 ? ARM_HARD_FRAME_POINTER_REGNUM \
909 : THUMB_HARD_FRAME_POINTER_REGNUM)
d5b7b3ae 910
b15bca31 911#define FP_REGNUM HARD_FRAME_POINTER_REGNUM
d5b7b3ae 912
b15bca31
RE		 913/* Register to use for pushing function arguments. */
914#define STACK_POINTER_REGNUM SP_REGNUM
d5b7b3ae
RE		 915
916/* ARM floating pointer registers. */
9b66ebb1
PB		 917#define FIRST_FPA_REGNUM 16
918#define LAST_FPA_REGNUM 23
2fa330b2
PB		 919#define IS_FPA_REGNUM(REGNUM) \
920 (((REGNUM) >= FIRST_FPA_REGNUM) && ((REGNUM) <= LAST_FPA_REGNUM))
d5b7b3ae 921
5a9335ef
NC		 922#define FIRST_IWMMXT_GR_REGNUM 43
923#define LAST_IWMMXT_GR_REGNUM 46
924#define FIRST_IWMMXT_REGNUM 47
925#define LAST_IWMMXT_REGNUM 62
926#define IS_IWMMXT_REGNUM(REGNUM) \
927 (((REGNUM) >= FIRST_IWMMXT_REGNUM) && ((REGNUM) <= LAST_IWMMXT_REGNUM))
928#define IS_IWMMXT_GR_REGNUM(REGNUM) \
929 (((REGNUM) >= FIRST_IWMMXT_GR_REGNUM) && ((REGNUM) <= LAST_IWMMXT_GR_REGNUM))
930
35d965d5 931/* Base register for access to local variables of the function. */
ff9940b0
RE		 932#define FRAME_POINTER_REGNUM 25
933
d5b7b3ae
RE		 934/* Base register for access to arguments of the function. */
935#define ARG_POINTER_REGNUM 26
62b10bbc 936
9b6b54e2
NC		 937#define FIRST_CIRRUS_FP_REGNUM 27
938#define LAST_CIRRUS_FP_REGNUM 42
939#define IS_CIRRUS_REGNUM(REGNUM) \
940 (((REGNUM) >= FIRST_CIRRUS_FP_REGNUM) && ((REGNUM) <= LAST_CIRRUS_FP_REGNUM))
941
9b66ebb1 942#define FIRST_VFP_REGNUM 63
f1adb0a9
JB		 943#define D7_VFP_REGNUM 78 /* Registers 77 and 78 == VFP reg D7. */
944#define LAST_VFP_REGNUM \
945 (TARGET_VFP3 ? LAST_HI_VFP_REGNUM : LAST_LO_VFP_REGNUM)
946
9b66ebb1
PB		 947#define IS_VFP_REGNUM(REGNUM) \
948 (((REGNUM) >= FIRST_VFP_REGNUM) && ((REGNUM) <= LAST_VFP_REGNUM))
949
f1adb0a9
JB		 950/* VFP registers are split into two types: those defined by VFP versions < 3
951 have D registers overlaid on consecutive pairs of S registers. VFP version 3
952 defines 16 new D registers (d16-d31) which, for simplicity and correctness
953 in various parts of the backend, we implement as "fake" single-precision
954 registers (which would be S32-S63, but cannot be used in that way). The
955 following macros define these ranges of registers. */
956#define LAST_LO_VFP_REGNUM 94
957#define FIRST_HI_VFP_REGNUM 95
958#define LAST_HI_VFP_REGNUM 126
959
960#define VFP_REGNO_OK_FOR_SINGLE(REGNUM) \
961 ((REGNUM) <= LAST_LO_VFP_REGNUM)
962
963/* DFmode values are only valid in even register pairs. */
964#define VFP_REGNO_OK_FOR_DOUBLE(REGNUM) \
965 ((((REGNUM) - FIRST_VFP_REGNUM) & 1) == 0)
966
88f77cba
JB		 967/* Neon Quad values must start at a multiple of four registers. */
968#define NEON_REGNO_OK_FOR_QUAD(REGNUM) \
969 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0)
970
971/* Neon structures of vectors must be in even register pairs and there
972 must be enough registers available. Because of various patterns
973 requiring quad registers, we require them to start at a multiple of
974 four. */
975#define NEON_REGNO_OK_FOR_NREGS(REGNUM, N) \
976 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0 \
977 && (LAST_VFP_REGNUM - (REGNUM) >= 2 * (N) - 1))
978
6f8c9bd1
NC		 979/* The number of hard registers is 16 ARM + 8 FPA + 1 CC + 1 SFP + 1 AFP. */
980/* + 16 Cirrus registers take us up to 43. */
5a9335ef 981/* Intel Wireless MMX Technology registers add 16 + 4 more. */
f1adb0a9
JB		 982/* VFP (VFP3) adds 32 (64) + 1 more. */
983#define FIRST_PSEUDO_REGISTER 128
62b10bbc 984
2fa330b2
PB		 985#define DBX_REGISTER_NUMBER(REGNO) arm_dbx_register_number (REGNO)
986
35d965d5
RS		 987/* Value should be nonzero if functions must have frame pointers.
988 Zero means the frame pointer need not be set up (and parms may be accessed
f676971a 989 via the stack pointer) in functions that seem suitable.
ff9940b0
RE		 990 If we have to have a frame pointer we might as well make use of it.
991 APCS says that the frame pointer does not need to be pushed in leaf
2a5307b1 992 functions, or simple tail call functions. */
a15900b5
DJ		 993
994#ifndef SUBTARGET_FRAME_POINTER_REQUIRED
995#define SUBTARGET_FRAME_POINTER_REQUIRED 0
996#endif
997
7b8b8ade
NC		 998#define FRAME_POINTER_REQUIRED \
999 (current_function_has_nonlocal_label \
a15900b5 1000 || SUBTARGET_FRAME_POINTER_REQUIRED \
d5b7b3ae 1001 || (TARGET_ARM && TARGET_APCS_FRAME && ! leaf_function_p ()))
35d965d5 1002
d5b7b3ae
RE		 1003/* Return number of consecutive hard regs needed starting at reg REGNO
1004 to hold something of mode MODE.
1005 This is ordinarily the length in words of a value of mode MODE
1006 but can be less for certain modes in special long registers.
35d965d5 1007
3b684012 1008 On the ARM regs are UNITS_PER_WORD bits wide; FPA regs can hold any FP
d5b7b3ae
RE		 1009 mode. */
1010#define HARD_REGNO_NREGS(REGNO, MODE) \
5b3e6663 1011 ((TARGET_32BIT \
9b66ebb1 1012 && REGNO >= FIRST_FPA_REGNUM \
d5b7b3ae
RE		 1013 && REGNO != FRAME_POINTER_REGNUM \
1014 && REGNO != ARG_POINTER_REGNUM) \
9b66ebb1 1015 && !IS_VFP_REGNUM (REGNO) \
e9d7b180 1016 ? 1 : ARM_NUM_REGS (MODE))
35d965d5 1017
4b02997f 1018/* Return true if REGNO is suitable for holding a quantity of type MODE. */
d5b7b3ae 1019#define HARD_REGNO_MODE_OK(REGNO, MODE) \
4b02997f 1020 arm_hard_regno_mode_ok ((REGNO), (MODE))
35d965d5 1021
d5b7b3ae
RE		 1022/* Value is 1 if it is a good idea to tie two pseudo registers
1023 when one has mode MODE1 and one has mode MODE2.
1024 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1025 for any hard reg, then this must be 0 for correct output. */
1026#define MODES_TIEABLE_P(MODE1, MODE2) \
1027 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
ff9940b0 1028
5a9335ef 1029#define VALID_IWMMXT_REG_MODE(MODE) \
f676971a 1030 (arm_vector_mode_supported_p (MODE) || (MODE) == DImode)
5a9335ef 1031
88f77cba
JB		 1032/* Modes valid for Neon D registers. */
1033#define VALID_NEON_DREG_MODE(MODE) \
1034 ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode \
1035 || (MODE) == V2SFmode || (MODE) == DImode)
1036
1037/* Modes valid for Neon Q registers. */
1038#define VALID_NEON_QREG_MODE(MODE) \
1039 ((MODE) == V4SImode || (MODE) == V8HImode || (MODE) == V16QImode \
1040 || (MODE) == V4SFmode || (MODE) == V2DImode)
1041
1042/* Structure modes valid for Neon registers. */
1043#define VALID_NEON_STRUCT_MODE(MODE) \
1044 ((MODE) == TImode || (MODE) == EImode || (MODE) == OImode \
1045 || (MODE) == CImode || (MODE) == XImode)
1046
35d965d5 1047/* The order in which register should be allocated. It is good to use ip
ff9940b0
RE		 1048 since no saving is required (though calls clobber it) and it never contains
1049 function parameters. It is quite good to use lr since other calls may
f676971a 1050 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is
ff9940b0 1051 least likely to contain a function parameter; in addition results are
f1adb0a9
JB		 1052 returned in r0.
1053 For VFP/VFPv3, allocate D16-D31 first, then caller-saved registers (D0-D7),
1054 then D8-D15. The reason for doing this is to attempt to reduce register
1055 pressure when both single- and double-precision registers are used in a
1056 function. */
1057
1058#define REG_ALLOC_ORDER \
1059{ \
1060 3, 2, 1, 0, 12, 14, 4, 5, \
1061 6, 7, 8, 10, 9, 11, 13, 15, \
1062 16, 17, 18, 19, 20, 21, 22, 23, \
1063 27, 28, 29, 30, 31, 32, 33, 34, \
1064 35, 36, 37, 38, 39, 40, 41, 42, \
1065 43, 44, 45, 46, 47, 48, 49, 50, \
1066 51, 52, 53, 54, 55, 56, 57, 58, \
1067 59, 60, 61, 62, \
1068 24, 25, 26, \
1069 95, 96, 97, 98, 99, 100, 101, 102, \
1070 103, 104, 105, 106, 107, 108, 109, 110, \
1071 111, 112, 113, 114, 115, 116, 117, 118, \
1072 119, 120, 121, 122, 123, 124, 125, 126, \
1073 78, 77, 76, 75, 74, 73, 72, 71, \
1074 70, 69, 68, 67, 66, 65, 64, 63, \
1075 79, 80, 81, 82, 83, 84, 85, 86, \
1076 87, 88, 89, 90, 91, 92, 93, 94, \
1077 127 \
35d965d5 1078}
9338ffe6
PB		 1079
1080/* Interrupt functions can only use registers that have already been
1081 saved by the prologue, even if they would normally be
1082 call-clobbered. */
1083#define HARD_REGNO_RENAME_OK(SRC, DST) \
1084 (! IS_INTERRUPT (cfun->machine->func_type) || \
6fb5fa3c 1085 df_regs_ever_live_p (DST))
35d965d5
RS		 1086\f
1087/* Register and constant classes. */
1088
3b684012 1089/* Register classes: used to be simple, just all ARM regs or all FPA regs
d6a7951f 1090 Now that the Thumb is involved it has become more complicated. */
35d965d5
RS		 1091enum reg_class
1092{
1093 NO_REGS,
3b684012 1094 FPA_REGS,
9b6b54e2 1095 CIRRUS_REGS,
f1adb0a9
JB		 1096 VFP_D0_D7_REGS,
1097 VFP_LO_REGS,
1098 VFP_HI_REGS,
9b66ebb1 1099 VFP_REGS,
5a9335ef
NC		 1100 IWMMXT_GR_REGS,
1101 IWMMXT_REGS,
d5b7b3ae
RE		 1102 LO_REGS,
1103 STACK_REG,
1104 BASE_REGS,
1105 HI_REGS,
1106 CC_REG,
9b66ebb1 1107 VFPCC_REG,
35d965d5
RS		 1108 GENERAL_REGS,
1109 ALL_REGS,
1110 LIM_REG_CLASSES
1111};
1112
1113#define N_REG_CLASSES (int) LIM_REG_CLASSES
1114
d6b4baa4 1115/* Give names of register classes as strings for dump file. */
35d965d5
RS		 1116#define REG_CLASS_NAMES \
1117{ \
1118 "NO_REGS", \
3b684012 1119 "FPA_REGS", \
9b6b54e2 1120 "CIRRUS_REGS", \
f1adb0a9
JB		 1121 "VFP_D0_D7_REGS", \
1122 "VFP_LO_REGS", \
1123 "VFP_HI_REGS", \
9b66ebb1 1124 "VFP_REGS", \
5a9335ef
NC		 1125 "IWMMXT_GR_REGS", \
1126 "IWMMXT_REGS", \
d5b7b3ae
RE		 1127 "LO_REGS", \
1128 "STACK_REG", \
1129 "BASE_REGS", \
1130 "HI_REGS", \
1131 "CC_REG", \
5384443a 1132 "VFPCC_REG", \
35d965d5
RS		 1133 "GENERAL_REGS", \
1134 "ALL_REGS", \
1135}
1136
1137/* Define which registers fit in which classes.
1138 This is an initializer for a vector of HARD_REG_SET
1139 of length N_REG_CLASSES. */
f1adb0a9
JB		 1140#define REG_CLASS_CONTENTS \
1141{ \
1142 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1143 { 0x00FF0000, 0x00000000, 0x00000000, 0x00000000 }, /* FPA_REGS */ \
1144 { 0xF8000000, 0x000007FF, 0x00000000, 0x00000000 }, /* CIRRUS_REGS */ \
1145 { 0x00000000, 0x80000000, 0x00007FFF, 0x00000000 }, /* VFP_D0_D7_REGS */ \
1146 { 0x00000000, 0x80000000, 0x7FFFFFFF, 0x00000000 }, /* VFP_LO_REGS */ \
1147 { 0x00000000, 0x00000000, 0x80000000, 0x7FFFFFFF }, /* VFP_HI_REGS */ \
1148 { 0x00000000, 0x80000000, 0xFFFFFFFF, 0x7FFFFFFF }, /* VFP_REGS */ \
1149 { 0x00000000, 0x00007800, 0x00000000, 0x00000000 }, /* IWMMXT_GR_REGS */ \
1150 { 0x00000000, 0x7FFF8000, 0x00000000, 0x00000000 }, /* IWMMXT_REGS */ \
1151 { 0x000000FF, 0x00000000, 0x00000000, 0x00000000 }, /* LO_REGS */ \
1152 { 0x00002000, 0x00000000, 0x00000000, 0x00000000 }, /* STACK_REG */ \
1153 { 0x000020FF, 0x00000000, 0x00000000, 0x00000000 }, /* BASE_REGS */ \
1154 { 0x0000FF00, 0x00000000, 0x00000000, 0x00000000 }, /* HI_REGS */ \
1155 { 0x01000000, 0x00000000, 0x00000000, 0x00000000 }, /* CC_REG */ \
1156 { 0x00000000, 0x00000000, 0x00000000, 0x80000000 }, /* VFPCC_REG */ \
1157 { 0x0200FFFF, 0x00000000, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \
1158 { 0xFAFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x7FFFFFFF } /* ALL_REGS */ \
35d965d5 1159}
4b02997f 1160
f1adb0a9
JB		 1161/* Any of the VFP register classes. */
1162#define IS_VFP_CLASS(X) \
1163 ((X) == VFP_D0_D7_REGS || (X) == VFP_LO_REGS \
1164 || (X) == VFP_HI_REGS || (X) == VFP_REGS)
1165
35d965d5
RS		 1166/* The same information, inverted:
1167 Return the class number of the smallest class containing
1168 reg number REGNO. This could be a conditional expression
1169 or could index an array. */
d5b7b3ae 1170#define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO)
35d965d5 1171
9b66ebb1 1172/* FPA registers can't do subreg as all values are reformatted to internal
59b9a953 1173 precision. VFP registers may only be accessed in the mode they
9b66ebb1 1174 were set. */
75d2580c
RE		 1175#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1176 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
9b66ebb1
PB		 1177 ? reg_classes_intersect_p (FPA_REGS, (CLASS)) \
1178 || reg_classes_intersect_p (VFP_REGS, (CLASS)) \
1179 : 0)
75d2580c 1180
cc81dde8
PB		 1181/* We need to define this for LO_REGS on thumb. Otherwise we can end up
1182 using r0-r4 for function arguments, r7 for the stack frame and don't
1183 have enough left over to do doubleword arithmetic. */
1184#define CLASS_LIKELY_SPILLED_P(CLASS) \
1185 ((TARGET_THUMB && (CLASS) == LO_REGS) \
1186 || (CLASS) == CC_REG)
f676971a 1187
35d965d5 1188/* The class value for index registers, and the one for base regs. */
5b3e6663
PB		 1189#define INDEX_REG_CLASS (TARGET_THUMB1 ? LO_REGS : GENERAL_REGS)
1190#define BASE_REG_CLASS (TARGET_THUMB1 ? LO_REGS : GENERAL_REGS)
d5b7b3ae 1191
b93a0fe6 1192/* For the Thumb the high registers cannot be used as base registers
6bc82793 1193 when addressing quantities in QI or HI mode; if we don't know the
888d2cd6 1194 mode, then we must be conservative. */
3dcc68a4 1195#define MODE_BASE_REG_CLASS(MODE) \
5b3e6663 1196 (TARGET_32BIT ? GENERAL_REGS : \
888d2cd6
DJ		 1197 (((MODE) == SImode) ? BASE_REGS : LO_REGS))
1198
1199/* For Thumb we can not support SP+reg addressing, so we return LO_REGS
1200 instead of BASE_REGS. */
1201#define MODE_BASE_REG_REG_CLASS(MODE) BASE_REG_CLASS
3dcc68a4 1202
d5b7b3ae
RE		 1203/* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1204 registers explicitly used in the rtl to be used as spill registers
1205 but prevents the compiler from extending the lifetime of these
d6b4baa4 1206 registers. */
5b3e6663 1207#define SMALL_REGISTER_CLASSES TARGET_THUMB1
35d965d5 1208
35d965d5
RS		 1209/* Given an rtx X being reloaded into a reg required to be
1210 in class CLASS, return the class of reg to actually use.
5b3e6663
PB		 1211 In general this is just CLASS, but for the Thumb core registers and
1212 immediate constants we prefer a LO_REGS class or a subset. */
1213#define PREFERRED_RELOAD_CLASS(X, CLASS) \
1214 (TARGET_ARM ? (CLASS) : \
1215 ((CLASS) == GENERAL_REGS || (CLASS) == HI_REGS \
1216 || (CLASS) == NO_REGS ? LO_REGS : (CLASS)))
d5b7b3ae
RE		 1217
1218/* Must leave BASE_REGS reloads alone */
1219#define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1220 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1221 ? ((true_regnum (X) == -1 ? LO_REGS \
1222 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1223 : NO_REGS)) \
1224 : NO_REGS)
1225
1226#define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
97358092 1227 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
d5b7b3ae
RE		 1228 ? ((true_regnum (X) == -1 ? LO_REGS \
1229 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1230 : NO_REGS)) \
1231 : NO_REGS)
35d965d5 1232
ff9940b0
RE		 1233/* Return the register class of a scratch register needed to copy IN into
1234 or out of a register in CLASS in MODE. If it can be done directly,
1235 NO_REGS is returned. */
d5b7b3ae 1236#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
fe2d934b 1237 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \
9b66ebb1 1238 ((TARGET_VFP && TARGET_HARD_FLOAT \
f1adb0a9 1239 && IS_VFP_CLASS (CLASS)) \
fe2d934b
PB		 1240 ? coproc_secondary_reload_class (MODE, X, FALSE) \
1241 : (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) \
1242 ? coproc_secondary_reload_class (MODE, X, TRUE) \
5b3e6663 1243 : TARGET_32BIT \
9b66ebb1 1244 ? (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \
d5b7b3ae
RE		 1245 ? GENERAL_REGS : NO_REGS) \
1246 : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X))
f676971a 1247
d6b4baa4 1248/* If we need to load shorts byte-at-a-time, then we need a scratch. */
d5b7b3ae 1249#define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
fe2d934b 1250 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \
9b66ebb1 1251 ((TARGET_VFP && TARGET_HARD_FLOAT \
f1adb0a9 1252 && IS_VFP_CLASS (CLASS)) \
fe2d934b
PB		 1253 ? coproc_secondary_reload_class (MODE, X, FALSE) : \
1254 (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) ? \
1255 coproc_secondary_reload_class (MODE, X, TRUE) : \
9b6b54e2 1256 /* Cannot load constants into Cirrus registers. */ \
9b66ebb1 1257 (TARGET_MAVERICK && TARGET_HARD_FLOAT \
9b6b54e2
NC		 1258 && (CLASS) == CIRRUS_REGS \
1259 && (CONSTANT_P (X) || GET_CODE (X) == SYMBOL_REF)) \
1260 ? GENERAL_REGS : \
5b3e6663 1261 (TARGET_32BIT ? \
5a9335ef
NC		 1262 (((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \
1263 && CONSTANT_P (X)) \
1264 ? GENERAL_REGS : \
61f0ccff 1265 (((MODE) == HImode && ! arm_arch4 \
d5b7b3ae
RE		 1266 && (GET_CODE (X) == MEM \
1267 || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \
1268 && true_regnum (X) == -1))) \
1269 ? GENERAL_REGS : NO_REGS) \
9b6b54e2 1270 : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X)))
2ce9c1b9 1271
6f734908
RE		 1272/* Try a machine-dependent way of reloading an illegitimate address
1273 operand. If we find one, push the reload and jump to WIN. This
1274 macro is used in only one place: `find_reloads_address' in reload.c.
1275
1276 For the ARM, we wish to handle large displacements off a base
1277 register by splitting the addend across a MOV and the mem insn.
d5b7b3ae
RE		 1278 This can cut the number of reloads needed. */
1279#define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN) \
1280 do \
1281 { \
1282 if (GET_CODE (X) == PLUS \
1283 && GET_CODE (XEXP (X, 0)) == REG \
1284 && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \
1285 && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \
1286 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1287 { \
1288 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1289 HOST_WIDE_INT low, high; \
1290 \
de6f27a8 1291 if (MODE == DImode || (MODE == DFmode && TARGET_SOFT_FLOAT)) \
d5b7b3ae 1292 low = ((val & 0xf) ^ 0x8) - 0x8; \
9b66ebb1 1293 else if (TARGET_MAVERICK && TARGET_HARD_FLOAT) \
9b6b54e2
NC		 1294 /* Need to be careful, -256 is not a valid offset. */ \
1295 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
d5b7b3ae 1296 else if (MODE == SImode \
de6f27a8 1297 || (MODE == SFmode && TARGET_SOFT_FLOAT) \
d5b7b3ae
RE		 1298 || ((MODE == HImode || MODE == QImode) && ! arm_arch4)) \
1299 /* Need to be careful, -4096 is not a valid offset. */ \
1300 low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff); \
1301 else if ((MODE == HImode || MODE == QImode) && arm_arch4) \
1302 /* Need to be careful, -256 is not a valid offset. */ \
1303 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1304 else if (GET_MODE_CLASS (MODE) == MODE_FLOAT \
9b66ebb1 1305 && TARGET_HARD_FLOAT && TARGET_FPA) \
d5b7b3ae
RE		 1306 /* Need to be careful, -1024 is not a valid offset. */ \
1307 low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \
1308 else \
1309 break; \
1310 \
30cf4896
KG		 1311 high = ((((val - low) & (unsigned HOST_WIDE_INT) 0xffffffff) \
1312 ^ (unsigned HOST_WIDE_INT) 0x80000000) \
1313 - (unsigned HOST_WIDE_INT) 0x80000000); \
d5b7b3ae
RE		 1314 /* Check for overflow or zero */ \
1315 if (low == 0 || high == 0 || (high + low != val)) \
1316 break; \
1317 \
1318 /* Reload the high part into a base reg; leave the low part \
1319 in the mem. */ \
1320 X = gen_rtx_PLUS (GET_MODE (X), \
1321 gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \
1322 GEN_INT (high)), \
1323 GEN_INT (low)); \
df4ae160 1324 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
4a692617
NC		 1325 MODE_BASE_REG_CLASS (MODE), GET_MODE (X), \
1326 VOIDmode, 0, 0, OPNUM, TYPE); \
d5b7b3ae
RE		 1327 goto WIN; \
1328 } \
1329 } \
62b10bbc 1330 while (0)
6f734908 1331
27847754 1332/* XXX If an HImode FP+large_offset address is converted to an HImode
d5b7b3ae
RE		 1333 SP+large_offset address, then reload won't know how to fix it. It sees
1334 only that SP isn't valid for HImode, and so reloads the SP into an index
1335 register, but the resulting address is still invalid because the offset
1336 is too big. We fix it here instead by reloading the entire address. */
1337/* We could probably achieve better results by defining PROMOTE_MODE to help
1338 cope with the variances between the Thumb's signed and unsigned byte and
1339 halfword load instructions. */
5b3e6663 1340/* ??? This should be safe for thumb2, but we may be able to do better. */
a132dad6
RE		 1341#define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_L, WIN) \
1342do { \
1343 rtx new_x = thumb_legitimize_reload_address (&X, MODE, OPNUM, TYPE, IND_L); \
1344 if (new_x) \
1345 { \
1346 X = new_x; \
1347 goto WIN; \
1348 } \
1349} while (0)
d5b7b3ae
RE		 1350
1351#define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1352 if (TARGET_ARM) \
1353 ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \
1354 else \
1355 THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN)
f676971a 1356
35d965d5
RS		 1357/* Return the maximum number of consecutive registers
1358 needed to represent mode MODE in a register of class CLASS.
3b684012 1359 ARM regs are UNITS_PER_WORD bits while FPA regs can hold any FP mode */
35d965d5 1360#define CLASS_MAX_NREGS(CLASS, MODE) \
3b684012 1361 (((CLASS) == FPA_REGS || (CLASS) == CIRRUS_REGS) ? 1 : ARM_NUM_REGS (MODE))
9b6b54e2
NC		 1362
1363/* If defined, gives a class of registers that cannot be used as the
1364 operand of a SUBREG that changes the mode of the object illegally. */
35d965d5 1365
3b684012 1366/* Moves between FPA_REGS and GENERAL_REGS are two memory insns. */
cf011243 1367#define REGISTER_MOVE_COST(MODE, FROM, TO) \
5b3e6663 1368 (TARGET_32BIT ? \
3b684012
RE		 1369 ((FROM) == FPA_REGS && (TO) != FPA_REGS ? 20 : \
1370 (FROM) != FPA_REGS && (TO) == FPA_REGS ? 20 : \
f1adb0a9
JB		 1371 IS_VFP_CLASS (FROM) && !IS_VFP_CLASS (TO) ? 10 : \
1372 !IS_VFP_CLASS (FROM) && IS_VFP_CLASS (TO) ? 10 : \
5a9335ef
NC		 1373 (FROM) == IWMMXT_REGS && (TO) != IWMMXT_REGS ? 4 : \
1374 (FROM) != IWMMXT_REGS && (TO) == IWMMXT_REGS ? 4 : \
1375 (FROM) == IWMMXT_GR_REGS || (TO) == IWMMXT_GR_REGS ? 20 : \
9b6b54e2
NC		 1376 (FROM) == CIRRUS_REGS && (TO) != CIRRUS_REGS ? 20 : \
1377 (FROM) != CIRRUS_REGS && (TO) == CIRRUS_REGS ? 20 : \
1378 2) \
d5b7b3ae
RE		 1379 : \
1380 ((FROM) == HI_REGS || (TO) == HI_REGS) ? 4 : 2)
35d965d5
RS		 1381\f
1382/* Stack layout; function entry, exit and calling. */
1383
1384/* Define this if pushing a word on the stack
1385 makes the stack pointer a smaller address. */
1386#define STACK_GROWS_DOWNWARD 1
1387
a4d05547 1388/* Define this to nonzero if the nominal address of the stack frame
35d965d5
RS		 1389 is at the high-address end of the local variables;
1390 that is, each additional local variable allocated
1391 goes at a more negative offset in the frame. */
1392#define FRAME_GROWS_DOWNWARD 1
1393
a2503645
RS		 1394/* The amount of scratch space needed by _interwork_{r7,r11}_call_via_rN().
1395 When present, it is one word in size, and sits at the top of the frame,
1396 between the soft frame pointer and either r7 or r11.
1397
1398 We only need _interwork_rM_call_via_rN() for -mcaller-super-interworking,
1399 and only then if some outgoing arguments are passed on the stack. It would
1400 be tempting to also check whether the stack arguments are passed by indirect
1401 calls, but there seems to be no reason in principle why a post-reload pass
1402 couldn't convert a direct call into an indirect one. */
1403#define CALLER_INTERWORKING_SLOT_SIZE \
1404 (TARGET_CALLER_INTERWORKING \
1405 && current_function_outgoing_args_size != 0 \
1406 ? UNITS_PER_WORD : 0)
1407
35d965d5
RS		 1408/* Offset within stack frame to start allocating local variables at.
1409 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1410 first local allocated. Otherwise, it is the offset to the BEGINNING
1411 of the first local allocated. */
1412#define STARTING_FRAME_OFFSET 0
1413
1414/* If we generate an insn to push BYTES bytes,
1415 this says how many the stack pointer really advances by. */
d5b7b3ae 1416/* The push insns do not do this rounding implicitly.
d6b4baa4 1417 So don't define this. */
0c2ca901 1418/* #define PUSH_ROUNDING(NPUSHED) ROUND_UP_WORD (NPUSHED) */
18543a22
ILT		 1419
1420/* Define this if the maximum size of all the outgoing args is to be
1421 accumulated and pushed during the prologue. The amount can be
1422 found in the variable current_function_outgoing_args_size. */
6cfc7210 1423#define ACCUMULATE_OUTGOING_ARGS 1
35d965d5
RS		 1424
1425/* Offset of first parameter from the argument pointer register value. */
d5b7b3ae 1426#define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0)
35d965d5
RS		 1427
1428/* Value is the number of byte of arguments automatically
1429 popped when returning from a subroutine call.
8b109b37 1430 FUNDECL is the declaration node of the function (as a tree),
35d965d5
RS		 1431 FUNTYPE is the data type of the function (as a tree),
1432 or for a library call it is an identifier node for the subroutine name.
1433 SIZE is the number of bytes of arguments passed on the stack.
1434
1435 On the ARM, the caller does not pop any of its arguments that were passed
1436 on the stack. */
6cfc7210 1437#define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0
35d965d5
RS		 1438
1439/* Define how to find the value returned by a library function
1440 assuming the value has mode MODE. */
1441#define LIBCALL_VALUE(MODE) \
5b3e6663 1442 (TARGET_32BIT && TARGET_HARD_FLOAT_ABI && TARGET_FPA \
9b66ebb1
PB		 1443 && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1444 ? gen_rtx_REG (MODE, FIRST_FPA_REGNUM) \
5b3e6663 1445 : TARGET_32BIT && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK \
9b66ebb1 1446 && GET_MODE_CLASS (MODE) == MODE_FLOAT \
9b6b54e2 1447 ? gen_rtx_REG (MODE, FIRST_CIRRUS_FP_REGNUM) \
f676971a 1448 : TARGET_IWMMXT_ABI && arm_vector_mode_supported_p (MODE) \
5a9335ef 1449 ? gen_rtx_REG (MODE, FIRST_IWMMXT_REGNUM) \
d5b7b3ae 1450 : gen_rtx_REG (MODE, ARG_REGISTER (1)))
35d965d5 1451
6cfc7210
NC		 1452/* Define how to find the value returned by a function.
1453 VALTYPE is the data type of the value (as a tree).
1454 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1455 otherwise, FUNC is 0. */
d5b7b3ae 1456#define FUNCTION_VALUE(VALTYPE, FUNC) \
d4453b7a 1457 arm_function_value (VALTYPE, FUNC);
6cfc7210 1458
35d965d5
RS		 1459/* 1 if N is a possible register number for a function value.
1460 On the ARM, only r0 and f0 can return results. */
9b6b54e2 1461/* On a Cirrus chip, mvf0 can return results. */
35d965d5 1462#define FUNCTION_VALUE_REGNO_P(REGNO) \
d5b7b3ae 1463 ((REGNO) == ARG_REGISTER (1) \
5b3e6663 1464 || (TARGET_32BIT && ((REGNO) == FIRST_CIRRUS_FP_REGNUM) \
72cdc543 1465 && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK) \
5848830f 1466 || ((REGNO) == FIRST_IWMMXT_REGNUM && TARGET_IWMMXT_ABI) \
5b3e6663 1467 || (TARGET_32BIT && ((REGNO) == FIRST_FPA_REGNUM) \
72cdc543 1468 && TARGET_HARD_FLOAT_ABI && TARGET_FPA))
35d965d5 1469
9f7bf991
RE		 1470/* Amount of memory needed for an untyped call to save all possible return
1471 registers. */
1472#define APPLY_RESULT_SIZE arm_apply_result_size()
1473
11c1a207
RE		 1474/* How large values are returned */
1475/* A C expression which can inhibit the returning of certain function values
d6b4baa4 1476 in registers, based on the type of value. */
f5a1b0d2 1477#define RETURN_IN_MEMORY(TYPE) arm_return_in_memory (TYPE)
11c1a207
RE		 1478
1479/* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return
1480 values must be in memory. On the ARM, they need only do so if larger
d6b4baa4 1481 than a word, or if they contain elements offset from zero in the struct. */
11c1a207
RE		 1482#define DEFAULT_PCC_STRUCT_RETURN 0
1483
6d3d9133 1484/* These bits describe the different types of function supported
112cdef5 1485 by the ARM backend. They are exclusive. i.e. a function cannot be both a
6d3d9133
NC		 1486 normal function and an interworked function, for example. Knowing the
1487 type of a function is important for determining its prologue and
1488 epilogue sequences.
1489 Note value 7 is currently unassigned. Also note that the interrupt
1490 function types all have bit 2 set, so that they can be tested for easily.
1491 Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the
4912a07c 1492 machine_function structure is initialized (to zero) func_type will
6d3d9133
NC		 1493 default to unknown. This will force the first use of arm_current_func_type
1494 to call arm_compute_func_type. */
1495#define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */
1496#define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */
1497#define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */
6d3d9133
NC		 1498#define ARM_FT_ISR 4 /* An interrupt service routine. */
1499#define ARM_FT_FIQ 5 /* A fast interrupt service routine. */
1500#define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */
1501
1502#define ARM_FT_TYPE_MASK ((1 << 3) - 1)
1503
1504/* In addition functions can have several type modifiers,
1505 outlined by these bit masks: */
1506#define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */
1507#define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */
1508#define ARM_FT_VOLATILE (1 << 4) /* Does not return. */
d6b4baa4 1509#define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */
5b3e6663 1510#define ARM_FT_STACKALIGN (1 << 6) /* Called with misaligned stack. */
6d3d9133
NC		 1511
1512/* Some macros to test these flags. */
1513#define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK)
1514#define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT)
1515#define IS_VOLATILE(t) (t & ARM_FT_VOLATILE)
1516#define IS_NAKED(t) (t & ARM_FT_NAKED)
1517#define IS_NESTED(t) (t & ARM_FT_NESTED)
5b3e6663 1518#define IS_STACKALIGN(t) (t & ARM_FT_STACKALIGN)
6d3d9133 1519
5848830f
PB		 1520
1521/* Structure used to hold the function stack frame layout. Offsets are
1522 relative to the stack pointer on function entry. Positive offsets are
1523 in the direction of stack growth.
1524 Only soft_frame is used in thumb mode. */
1525
1526typedef struct arm_stack_offsets GTY(())
1527{
1528 int saved_args; /* ARG_POINTER_REGNUM. */
1529 int frame; /* ARM_HARD_FRAME_POINTER_REGNUM. */
1530 int saved_regs;
1531 int soft_frame; /* FRAME_POINTER_REGNUM. */
2591db65 1532 int locals_base; /* THUMB_HARD_FRAME_POINTER_REGNUM. */
5848830f
PB		 1533 int outgoing_args; /* STACK_POINTER_REGNUM. */
1534}
1535arm_stack_offsets;
1536
6d3d9133
NC		 1537/* A C structure for machine-specific, per-function data.
1538 This is added to the cfun structure. */
e2500fed 1539typedef struct machine_function GTY(())
d5b7b3ae 1540{
6bc82793 1541 /* Additional stack adjustment in __builtin_eh_throw. */
e2500fed 1542 rtx eh_epilogue_sp_ofs;
d5b7b3ae
RE		 1543 /* Records if LR has to be saved for far jumps. */
1544 int far_jump_used;
1545 /* Records if ARG_POINTER was ever live. */
1546 int arg_pointer_live;
6f7ebcbb
NC		 1547 /* Records if the save of LR has been eliminated. */
1548 int lr_save_eliminated;
0977774b 1549 /* The size of the stack frame. Only valid after reload. */
5848830f 1550 arm_stack_offsets stack_offsets;
6d3d9133
NC		 1551 /* Records the type of the current function. */
1552 unsigned long func_type;
3cb66fd7
NC		 1553 /* Record if the function has a variable argument list. */
1554 int uses_anonymous_args;
5a9335ef
NC		 1555 /* Records if sibcalls are blocked because an argument
1556 register is needed to preserve stack alignment. */
1557 int sibcall_blocked;
020a4035
RE		 1558 /* The PIC register for this function. This might be a pseudo. */
1559 rtx pic_reg;
b12a00f1 1560 /* Labels for per-function Thumb call-via stubs. One per potential calling
57ecec57
PB		 1561 register. We can never call via LR or PC. We can call via SP if a
1562 trampoline happens to be on the top of the stack. */
1563 rtx call_via[14];
6d3d9133
NC		 1564}
1565machine_function;
d5b7b3ae 1566
b12a00f1 1567/* As in the machine_function, a global set of call-via labels, for code
d6b5193b 1568 that is in text_section. */
57ecec57 1569extern GTY(()) rtx thumb_call_via_label[14];
b12a00f1 1570
82e9d970
PB		 1571/* A C type for declaring a variable that is used as the first argument of
1572 `FUNCTION_ARG' and other related values. For some target machines, the
1573 type `int' suffices and can hold the number of bytes of argument so far. */
1574typedef struct
1575{
d5b7b3ae 1576 /* This is the number of registers of arguments scanned so far. */
82e9d970 1577 int nregs;
5a9335ef
NC		 1578 /* This is the number of iWMMXt register arguments scanned so far. */
1579 int iwmmxt_nregs;
1580 int named_count;
1581 int nargs;
5848830f 1582 int can_split;
d5b7b3ae 1583} CUMULATIVE_ARGS;
82e9d970 1584
35d965d5
RS		 1585/* Define where to put the arguments to a function.
1586 Value is zero to push the argument on the stack,
1587 or a hard register in which to store the argument.
1588
1589 MODE is the argument's machine mode.
1590 TYPE is the data type of the argument (as a tree).
1591 This is null for libcalls where that information may
1592 not be available.
1593 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1594 the preceding args and about the function being called.
1595 NAMED is nonzero if this argument is a named parameter
1596 (otherwise it is an extra parameter matching an ellipsis).
1597
1598 On the ARM, normally the first 16 bytes are passed in registers r0-r3; all
1599 other arguments are passed on the stack. If (NAMED == 0) (which happens
1cc9f5f5
KH		 1600 only in assign_parms, since TARGET_SETUP_INCOMING_VARARGS is
1601 defined), say it is passed in the stack (function_prologue will
1602 indeed make it pass in the stack if necessary). */
82e9d970
PB		 1603#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1604 arm_function_arg (&(CUM), (MODE), (TYPE), (NAMED))
35d965d5 1605
866af8a9
JB		 1606#define FUNCTION_ARG_PADDING(MODE, TYPE) \
1607 (arm_pad_arg_upward (MODE, TYPE) ? upward : downward)
1608
1609#define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
1610 (arm_pad_reg_upward (MODE, TYPE, FIRST) ? upward : downward)
1611
1612/* For AAPCS, padding should never be below the argument. For other ABIs,
1613 * mimic the default. */
1614#define PAD_VARARGS_DOWN \
1615 ((TARGET_AAPCS_BASED) ? 0 : BYTES_BIG_ENDIAN)
1616
35d965d5
RS		 1617/* Initialize a variable CUM of type CUMULATIVE_ARGS
1618 for a call to a function whose data type is FNTYPE.
1619 For a library call, FNTYPE is 0.
1620 On the ARM, the offset starts at 0. */
0f6937fe 1621#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
563a317a 1622 arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL))
35d965d5
RS		 1623
1624/* Update the data in CUM to advance over an argument
1625 of mode MODE and data type TYPE.
1626 (TYPE is null for libcalls where that information may not be available.) */
6cfc7210 1627#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
5a9335ef 1628 (CUM).nargs += 1; \
f0c1ebb7
JM		 1629 if (arm_vector_mode_supported_p (MODE) \
1630 && (CUM).named_count > (CUM).nargs \
1631 && TARGET_IWMMXT_ABI) \
5848830f 1632 (CUM).iwmmxt_nregs += 1; \
5a9335ef 1633 else \
5848830f 1634 (CUM).nregs += ARM_NUM_REGS2 (MODE, TYPE)
35d965d5 1635
5a9335ef
NC		 1636/* If defined, a C expression that gives the alignment boundary, in bits, of an
1637 argument with the specified mode and type. If it is not defined,
1638 `PARM_BOUNDARY' is used for all arguments. */
1639#define FUNCTION_ARG_BOUNDARY(MODE,TYPE) \
5848830f
PB		 1640 ((ARM_DOUBLEWORD_ALIGN && arm_needs_doubleword_align (MODE, TYPE)) \
1641 ? DOUBLEWORD_ALIGNMENT \
1642 : PARM_BOUNDARY )
5a9335ef 1643
35d965d5
RS		 1644/* 1 if N is a possible register number for function argument passing.
1645 On the ARM, r0-r3 are used to pass args. */
5a9335ef
NC		 1646#define FUNCTION_ARG_REGNO_P(REGNO) \
1647 (IN_RANGE ((REGNO), 0, 3) \
5848830f
PB		 1648 || (TARGET_IWMMXT_ABI \
1649 && IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9)))
35d965d5 1650
f99fce0c 1651\f
afef3d7a
NC		 1652/* If your target environment doesn't prefix user functions with an
1653 underscore, you may wish to re-define this to prevent any conflicts.
1654 e.g. AOF may prefix mcount with an underscore. */
1655#ifndef ARM_MCOUNT_NAME
1656#define ARM_MCOUNT_NAME "*mcount"
1657#endif
1658
1659/* Call the function profiler with a given profile label. The Acorn
1660 compiler puts this BEFORE the prolog but gcc puts it afterwards.
1661 On the ARM the full profile code will look like:
1662 .data
1663 LP1
1664 .word 0
1665 .text
1666 mov ip, lr
1667 bl mcount
1668 .word LP1
1669
1670 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER
1671 will output the .text section.
1672
1673 The ``mov ip,lr'' seems like a good idea to stick with cc convention.
59be6073
AN		 1674 ``prof'' doesn't seem to mind about this!
1675
1676 Note - this version of the code is designed to work in both ARM and
1677 Thumb modes. */
be393ecf 1678#ifndef ARM_FUNCTION_PROFILER
d5b7b3ae 1679#define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \
6cfc7210
NC		 1680{ \
1681 char temp[20]; \
1682 rtx sym; \
1683 \
dd18ae56 1684 asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \
d5b7b3ae 1685 IP_REGNUM, LR_REGNUM); \
6cfc7210
NC		 1686 assemble_name (STREAM, ARM_MCOUNT_NAME); \
1687 fputc ('\n', STREAM); \
1688 ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \
f1c25d3b 1689 sym = gen_rtx_SYMBOL_REF (Pmode, temp); \
301d03af 1690 assemble_aligned_integer (UNITS_PER_WORD, sym); \
35d965d5 1691}
be393ecf 1692#endif
35d965d5 1693
59be6073 1694#ifdef THUMB_FUNCTION_PROFILER
d5b7b3ae
RE		 1695#define FUNCTION_PROFILER(STREAM, LABELNO) \
1696 if (TARGET_ARM) \
1697 ARM_FUNCTION_PROFILER (STREAM, LABELNO) \
1698 else \
1699 THUMB_FUNCTION_PROFILER (STREAM, LABELNO)
59be6073
AN		 1700#else
1701#define FUNCTION_PROFILER(STREAM, LABELNO) \
1702 ARM_FUNCTION_PROFILER (STREAM, LABELNO)
1703#endif
d5b7b3ae 1704
35d965d5
RS		 1705/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1706 the stack pointer does not matter. The value is tested only in
1707 functions that have frame pointers.
1708 No definition is equivalent to always zero.
1709
1710 On the ARM, the function epilogue recovers the stack pointer from the
1711 frame. */
1712#define EXIT_IGNORE_STACK 1
1713
6fb5fa3c 1714#define EPILOGUE_USES(REGNO) ((REGNO) == LR_REGNUM)
c7861455 1715
35d965d5
RS		 1716/* Determine if the epilogue should be output as RTL.
1717 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
5b3e6663
PB		 1718/* This is disabled for Thumb-2 because it will confuse the
1719 conditional insn counter. */
d5b7b3ae 1720#define USE_RETURN_INSN(ISCOND) \
a72d4945 1721 (TARGET_ARM ? use_return_insn (ISCOND, NULL) : 0)
ff9940b0
RE		 1722
1723/* Definitions for register eliminations.
1724
1725 This is an array of structures. Each structure initializes one pair
1726 of eliminable registers. The "from" register number is given first,
1727 followed by "to". Eliminations of the same "from" register are listed
1728 in order of preference.
1729
1730 We have two registers that can be eliminated on the ARM. First, the
1731 arg pointer register can often be eliminated in favor of the stack
1732 pointer register. Secondly, the pseudo frame pointer register can always
1733 be eliminated; it is replaced with either the stack or the real frame
d5b7b3ae 1734 pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM
d6a7951f 1735 because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */
ff9940b0 1736
d5b7b3ae
RE		 1737#define ELIMINABLE_REGS \
1738{{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1739 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\
1740 { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1741 { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\
1742 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1743 { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1744 { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }}
ff9940b0 1745
d5b7b3ae
RE		 1746/* Given FROM and TO register numbers, say whether this elimination is
1747 allowed. Frame pointer elimination is automatically handled.
ff9940b0
RE		 1748
1749 All eliminations are permissible. Note that ARG_POINTER_REGNUM and
abc95ed3 1750 HARD_FRAME_POINTER_REGNUM are in fact the same thing. If we need a frame
ff9940b0 1751 pointer, we must eliminate FRAME_POINTER_REGNUM into
d5b7b3ae
RE		 1752 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM or
1753 ARG_POINTER_REGNUM. */
1754#define CAN_ELIMINATE(FROM, TO) \
1755 (((TO) == FRAME_POINTER_REGNUM && (FROM) == ARG_POINTER_REGNUM) ? 0 : \
1756 ((TO) == STACK_POINTER_REGNUM && frame_pointer_needed) ? 0 : \
1757 ((TO) == ARM_HARD_FRAME_POINTER_REGNUM && TARGET_THUMB) ? 0 : \
1758 ((TO) == THUMB_HARD_FRAME_POINTER_REGNUM && TARGET_ARM) ? 0 : \
1759 1)
aeaf4d25 1760
d5b7b3ae
RE		 1761/* Define the offset between two registers, one to be eliminated, and the
1762 other its replacement, at the start of a routine. */
d5b7b3ae
RE		 1763#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1764 if (TARGET_ARM) \
5848830f 1765 (OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \
d5b7b3ae 1766 else \
5848830f
PB		 1767 (OFFSET) = thumb_compute_initial_elimination_offset (FROM, TO)
1768
d5b7b3ae
RE		 1769/* Special case handling of the location of arguments passed on the stack. */
1770#define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr)
f676971a 1771
d5b7b3ae
RE		 1772/* Initialize data used by insn expanders. This is called from insn_emit,
1773 once for every function before code is generated. */
1774#define INIT_EXPANDERS arm_init_expanders ()
1775
35d965d5
RS		 1776/* Output assembler code for a block containing the constant parts
1777 of a trampoline, leaving space for the variable parts.
1778
1779 On the ARM, (if r8 is the static chain regnum, and remembering that
1780 referencing pc adds an offset of 8) the trampoline looks like:
1781 ldr r8, [pc, #0]
1782 ldr pc, [pc]
1783 .word static chain value
11c1a207 1784 .word function's address
27847754 1785 XXX FIXME: When the trampoline returns, r8 will be clobbered. */
301d03af
RS		 1786#define ARM_TRAMPOLINE_TEMPLATE(FILE) \
1787{ \
1788 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
1789 STATIC_CHAIN_REGNUM, PC_REGNUM); \
1790 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
1791 PC_REGNUM, PC_REGNUM); \
1792 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1793 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
d5b7b3ae
RE		 1794}
1795
5b3e6663
PB		 1796/* The Thumb-2 trampoline is similar to the arm implementation.
1797 Unlike 16-bit Thumb, we enter the stub in thumb mode. */
1798#define THUMB2_TRAMPOLINE_TEMPLATE(FILE) \
1799{ \
1800 asm_fprintf (FILE, "\tldr.w\t%r, [%r, #4]\n", \
1801 STATIC_CHAIN_REGNUM, PC_REGNUM); \
1802 asm_fprintf (FILE, "\tldr.w\t%r, [%r, #4]\n", \
1803 PC_REGNUM, PC_REGNUM); \
1804 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1805 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1806}
1807
1808#define THUMB1_TRAMPOLINE_TEMPLATE(FILE) \
d5b7b3ae 1809{ \
5b3e6663
PB		 1810 ASM_OUTPUT_ALIGN(FILE, 2); \
1811 fprintf (FILE, "\t.code\t16\n"); \
d5b7b3ae 1812 fprintf (FILE, ".Ltrampoline_start:\n"); \
5b3e6663
PB		 1813 asm_fprintf (FILE, "\tpush\t{r0, r1}\n"); \
1814 asm_fprintf (FILE, "\tldr\tr0, [%r, #8]\n", \
1815 PC_REGNUM); \
1816 asm_fprintf (FILE, "\tmov\t%r, r0\n", \
1817 STATIC_CHAIN_REGNUM); \
1818 asm_fprintf (FILE, "\tldr\tr0, [%r, #8]\n", \
1819 PC_REGNUM); \
1820 asm_fprintf (FILE, "\tstr\tr0, [%r, #4]\n", \
1821 SP_REGNUM); \
1822 asm_fprintf (FILE, "\tpop\t{r0, %r}\n", \
1823 PC_REGNUM); \
1824 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1825 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
35d965d5
RS		 1826}
1827
d5b7b3ae
RE		 1828#define TRAMPOLINE_TEMPLATE(FILE) \
1829 if (TARGET_ARM) \
1830 ARM_TRAMPOLINE_TEMPLATE (FILE) \
5b3e6663
PB		 1831 else if (TARGET_THUMB2) \
1832 THUMB2_TRAMPOLINE_TEMPLATE (FILE) \
d5b7b3ae 1833 else \
5b3e6663
PB		 1834 THUMB1_TRAMPOLINE_TEMPLATE (FILE)
1835
1836/* Thumb trampolines should be entered in thumb mode, so set the bottom bit
1837 of the address. */
1838#define TRAMPOLINE_ADJUST_ADDRESS(ADDR) do \
1839{ \
1840 if (TARGET_THUMB) \
1841 (ADDR) = expand_simple_binop (Pmode, IOR, (ADDR), GEN_INT(1), \
1842 gen_reg_rtx (Pmode), 0, OPTAB_LIB_WIDEN); \
1843} while(0)
f676971a 1844
35d965d5 1845/* Length in units of the trampoline for entering a nested function. */
5b3e6663 1846#define TRAMPOLINE_SIZE (TARGET_32BIT ? 16 : 20)
35d965d5 1847
006946e4
JM		 1848/* Alignment required for a trampoline in bits. */
1849#define TRAMPOLINE_ALIGNMENT 32
35d965d5 1850
2a86f515 1851
35d965d5
RS		 1852/* Emit RTL insns to initialize the variable parts of a trampoline.
1853 FNADDR is an RTX for the address of the function's pure code.
1854 CXT is an RTX for the static chain value for the function. */
192c8d78
RE		 1855#ifndef INITIALIZE_TRAMPOLINE
1856#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1857{ \
1858 emit_move_insn (gen_rtx_MEM (SImode, \
1859 plus_constant (TRAMP, \
5b3e6663 1860 TARGET_32BIT ? 8 : 12)), \
192c8d78
RE		 1861 CXT); \
1862 emit_move_insn (gen_rtx_MEM (SImode, \
1863 plus_constant (TRAMP, \
5b3e6663 1864 TARGET_32BIT ? 12 : 16)), \
192c8d78 1865 FNADDR); \
49755603
RE		 1866 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__clear_cache"), \
1867 0, VOIDmode, 2, TRAMP, Pmode, \
1868 plus_constant (TRAMP, TRAMPOLINE_SIZE), Pmode); \
35d965d5 1869}
192c8d78 1870#endif
35d965d5 1871
35d965d5
RS		 1872\f
1873/* Addressing modes, and classification of registers for them. */
3cd45774 1874#define HAVE_POST_INCREMENT 1
5b3e6663
PB		 1875#define HAVE_PRE_INCREMENT TARGET_32BIT
1876#define HAVE_POST_DECREMENT TARGET_32BIT
1877#define HAVE_PRE_DECREMENT TARGET_32BIT
1878#define HAVE_PRE_MODIFY_DISP TARGET_32BIT
1879#define HAVE_POST_MODIFY_DISP TARGET_32BIT
1880#define HAVE_PRE_MODIFY_REG TARGET_32BIT
1881#define HAVE_POST_MODIFY_REG TARGET_32BIT
35d965d5
RS		 1882
1883/* Macros to check register numbers against specific register classes. */
1884
1885/* These assume that REGNO is a hard or pseudo reg number.
1886 They give nonzero only if REGNO is a hard reg of the suitable class
1887 or a pseudo reg currently allocated to a suitable hard reg.
1888 Since they use reg_renumber, they are safe only once reg_renumber
d6b4baa4 1889 has been allocated, which happens in local-alloc.c. */
d5b7b3ae
RE		 1890#define TEST_REGNO(R, TEST, VALUE) \
1891 ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE))
1892
5b3e6663 1893/* Don't allow the pc to be used. */
f1008e52
RE		 1894#define ARM_REGNO_OK_FOR_BASE_P(REGNO) \
1895 (TEST_REGNO (REGNO, <, PC_REGNUM) \
1896 || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \
1897 || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM))
1898
5b3e6663 1899#define THUMB1_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
f1008e52
RE		 1900 (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \
1901 || (GET_MODE_SIZE (MODE) >= 4 \
1902 && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)))
1903
1904#define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
5b3e6663
PB		 1905 (TARGET_THUMB1 \
1906 ? THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \
f1008e52
RE		 1907 : ARM_REGNO_OK_FOR_BASE_P (REGNO))
1908
888d2cd6
DJ		 1909/* Nonzero if X can be the base register in a reg+reg addressing mode.
1910 For Thumb, we can not use SP + reg, so reject SP. */
1911#define REGNO_MODE_OK_FOR_REG_BASE_P(X, MODE) \
1912 REGNO_OK_FOR_INDEX_P (X)
1913
f1008e52
RE		 1914/* For ARM code, we don't care about the mode, but for Thumb, the index
1915 must be suitable for use in a QImode load. */
d5b7b3ae
RE		 1916#define REGNO_OK_FOR_INDEX_P(REGNO) \
1917 REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode)
35d965d5
RS		 1918
1919/* Maximum number of registers that can appear in a valid memory address.
d6b4baa4 1920 Shifts in addresses can't be by a register. */
ff9940b0 1921#define MAX_REGS_PER_ADDRESS 2
35d965d5
RS		 1922
1923/* Recognize any constant value that is a valid address. */
1924/* XXX We can address any constant, eventually... */
11c1a207
RE		 1925
1926#ifdef AOF_ASSEMBLER
1927
1928#define CONSTANT_ADDRESS_P(X) \
d5b7b3ae 1929 (GET_CODE (X) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (X))
11c1a207
RE		 1930
1931#else
35d965d5 1932
5b3e6663 1933/* ??? Should the TARGET_ARM here also apply to thumb2? */
008cf58a
RE		 1934#define CONSTANT_ADDRESS_P(X) \
1935 (GET_CODE (X) == SYMBOL_REF \
1936 && (CONSTANT_POOL_ADDRESS_P (X) \
d5b7b3ae 1937 || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X))))
35d965d5 1938
11c1a207
RE		 1939#endif /* AOF_ASSEMBLER */
1940
8426b956
RS		 1941/* True if SYMBOL + OFFSET constants must refer to something within
1942 SYMBOL's section. */
1943#define ARM_OFFSETS_MUST_BE_WITHIN_SECTIONS_P 0
1944
35d965d5
RS		 1945/* Nonzero if the constant value X is a legitimate general operand.
1946 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1947
1948 On the ARM, allow any integer (invalid ones are removed later by insn
1949 patterns), nice doubles and symbol_refs which refer to the function's
d5b7b3ae 1950 constant pool XXX.
f676971a 1951
82e9d970 1952 When generating pic allow anything. */
d5b7b3ae
RE		 1953#define ARM_LEGITIMATE_CONSTANT_P(X) (flag_pic || ! label_mentioned_p (X))
1954
1955#define THUMB_LEGITIMATE_CONSTANT_P(X) \
1956 ( GET_CODE (X) == CONST_INT \
1957 || GET_CODE (X) == CONST_DOUBLE \
7b8781c8
PB		 1958 || CONSTANT_ADDRESS_P (X) \
1959 || flag_pic)
d5b7b3ae 1960
d3585b76 1961#define LEGITIMATE_CONSTANT_P(X) \
8426b956 1962 (!arm_cannot_force_const_mem (X) \
5b3e6663
PB		 1963 && (TARGET_32BIT ? ARM_LEGITIMATE_CONSTANT_P (X) \
1964 : THUMB_LEGITIMATE_CONSTANT_P (X)))
d5b7b3ae 1965
c27ba912
DM		 1966#ifndef SUBTARGET_NAME_ENCODING_LENGTHS
1967#define SUBTARGET_NAME_ENCODING_LENGTHS
1968#endif
1969
6bc82793 1970/* This is a C fragment for the inside of a switch statement.
c27ba912
DM		 1971 Each case label should return the number of characters to
1972 be stripped from the start of a function's name, if that
1973 name starts with the indicated character. */
1974#define ARM_NAME_ENCODING_LENGTHS \
00fdafef 1975 case '*': return 1; \
f676971a 1976 SUBTARGET_NAME_ENCODING_LENGTHS
c27ba912 1977
c27ba912
DM		 1978/* This is how to output a reference to a user-level label named NAME.
1979 `assemble_name' uses this. */
e5951263 1980#undef ASM_OUTPUT_LABELREF
c27ba912 1981#define ASM_OUTPUT_LABELREF(FILE, NAME) \
e1944073 1982 arm_asm_output_labelref (FILE, NAME)
c27ba912 1983
7a085dce 1984/* Output IT instructions for conditionally executed Thumb-2 instructions. */
5b3e6663
PB		 1985#define ASM_OUTPUT_OPCODE(STREAM, PTR) \
1986 if (TARGET_THUMB2) \
1987 thumb2_asm_output_opcode (STREAM);
1988
7abc66b1
JB		 1989/* The EABI specifies that constructors should go in .init_array.
1990 Other targets use .ctors for compatibility. */
88c6057f 1991#ifndef ARM_EABI_CTORS_SECTION_OP
7abc66b1
JB		 1992#define ARM_EABI_CTORS_SECTION_OP \
1993 "\t.section\t.init_array,\"aw\",%init_array"
88c6057f
MM		 1994#endif
1995#ifndef ARM_EABI_DTORS_SECTION_OP
7abc66b1
JB		 1996#define ARM_EABI_DTORS_SECTION_OP \
1997 "\t.section\t.fini_array,\"aw\",%fini_array"
88c6057f 1998#endif
7abc66b1
JB		 1999#define ARM_CTORS_SECTION_OP \
2000 "\t.section\t.ctors,\"aw\",%progbits"
2001#define ARM_DTORS_SECTION_OP \
2002 "\t.section\t.dtors,\"aw\",%progbits"
2003
2004/* Define CTORS_SECTION_ASM_OP. */
2005#undef CTORS_SECTION_ASM_OP
2006#undef DTORS_SECTION_ASM_OP
2007#ifndef IN_LIBGCC2
2008# define CTORS_SECTION_ASM_OP \
2009 (TARGET_AAPCS_BASED ? ARM_EABI_CTORS_SECTION_OP : ARM_CTORS_SECTION_OP)
2010# define DTORS_SECTION_ASM_OP \
2011 (TARGET_AAPCS_BASED ? ARM_EABI_DTORS_SECTION_OP : ARM_DTORS_SECTION_OP)
2012#else /* !defined (IN_LIBGCC2) */
2013/* In libgcc, CTORS_SECTION_ASM_OP must be a compile-time constant,
2014 so we cannot use the definition above. */
2015# ifdef __ARM_EABI__
2016/* The .ctors section is not part of the EABI, so we do not define
2017 CTORS_SECTION_ASM_OP when in libgcc; that prevents crtstuff
2018 from trying to use it. We do define it when doing normal
2019 compilation, as .init_array can be used instead of .ctors. */
2020/* There is no need to emit begin or end markers when using
2021 init_array; the dynamic linker will compute the size of the
2022 array itself based on special symbols created by the static
2023 linker. However, we do need to arrange to set up
2024 exception-handling here. */
2025# define CTOR_LIST_BEGIN asm (ARM_EABI_CTORS_SECTION_OP)
2026# define CTOR_LIST_END /* empty */
2027# define DTOR_LIST_BEGIN asm (ARM_EABI_DTORS_SECTION_OP)
2028# define DTOR_LIST_END /* empty */
2029# else /* !defined (__ARM_EABI__) */
2030# define CTORS_SECTION_ASM_OP ARM_CTORS_SECTION_OP
2031# define DTORS_SECTION_ASM_OP ARM_DTORS_SECTION_OP
2032# endif /* !defined (__ARM_EABI__) */
2033#endif /* !defined (IN_LIBCC2) */
2034
1e731102
MM		 2035/* True if the operating system can merge entities with vague linkage
2036 (e.g., symbols in COMDAT group) during dynamic linking. */
2037#ifndef TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P
2038#define TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P true
2039#endif
2040
617a1b71
PB		 2041#define ARM_OUTPUT_FN_UNWIND(F, PROLOGUE) arm_output_fn_unwind (F, PROLOGUE)
2042
2043#ifdef TARGET_UNWIND_INFO
2044#define ARM_EABI_UNWIND_TABLES \
2045 ((!USING_SJLJ_EXCEPTIONS && flag_exceptions) || flag_unwind_tables)
2046#else
2047#define ARM_EABI_UNWIND_TABLES 0
2048#endif
2049
35d965d5
RS		 2050/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2051 and check its validity for a certain class.
2052 We have two alternate definitions for each of them.
2053 The usual definition accepts all pseudo regs; the other rejects
2054 them unless they have been allocated suitable hard regs.
5b3e6663 2055 The symbol REG_OK_STRICT causes the latter definition to be used.
7a085dce 2056 Thumb-2 has the same restrictions as arm. */
35d965d5 2057#ifndef REG_OK_STRICT
ff9940b0 2058
f1008e52
RE		 2059#define ARM_REG_OK_FOR_BASE_P(X) \
2060 (REGNO (X) <= LAST_ARM_REGNUM \
2061 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
2062 || REGNO (X) == FRAME_POINTER_REGNUM \
2063 || REGNO (X) == ARG_POINTER_REGNUM)
ff9940b0 2064
5b3e6663 2065#define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \
f1008e52
RE		 2066 (REGNO (X) <= LAST_LO_REGNUM \
2067 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
2068 || (GET_MODE_SIZE (MODE) >= 4 \
2069 && (REGNO (X) == STACK_POINTER_REGNUM \
2070 || (X) == hard_frame_pointer_rtx \
2071 || (X) == arg_pointer_rtx)))
ff9940b0 2072
76a318e9
RE		 2073#define REG_STRICT_P 0
2074
d5b7b3ae 2075#else /* REG_OK_STRICT */
ff9940b0 2076
f1008e52
RE		 2077#define ARM_REG_OK_FOR_BASE_P(X) \
2078 ARM_REGNO_OK_FOR_BASE_P (REGNO (X))
ff9940b0 2079
5b3e6663
PB		 2080#define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \
2081 THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE)
ff9940b0 2082
76a318e9
RE		 2083#define REG_STRICT_P 1
2084
d5b7b3ae 2085#endif /* REG_OK_STRICT */
f1008e52
RE		 2086
2087/* Now define some helpers in terms of the above. */
2088
2089#define REG_MODE_OK_FOR_BASE_P(X, MODE) \
5b3e6663
PB		 2090 (TARGET_THUMB1 \
2091 ? THUMB1_REG_MODE_OK_FOR_BASE_P (X, MODE) \
f1008e52
RE		 2092 : ARM_REG_OK_FOR_BASE_P (X))
2093
2094#define ARM_REG_OK_FOR_INDEX_P(X) ARM_REG_OK_FOR_BASE_P (X)
2095
5b3e6663 2096/* For 16-bit Thumb, a valid index register is anything that can be used in
f1008e52 2097 a byte load instruction. */
5b3e6663
PB		 2098#define THUMB1_REG_OK_FOR_INDEX_P(X) \
2099 THUMB1_REG_MODE_OK_FOR_BASE_P (X, QImode)
f1008e52
RE		 2100
2101/* Nonzero if X is a hard reg that can be used as an index
2102 or if it is a pseudo reg. On the Thumb, the stack pointer
2103 is not suitable. */
2104#define REG_OK_FOR_INDEX_P(X) \
5b3e6663
PB		 2105 (TARGET_THUMB1 \
2106 ? THUMB1_REG_OK_FOR_INDEX_P (X) \
f1008e52
RE		 2107 : ARM_REG_OK_FOR_INDEX_P (X))
2108
888d2cd6
DJ		 2109/* Nonzero if X can be the base register in a reg+reg addressing mode.
2110 For Thumb, we can not use SP + reg, so reject SP. */
2111#define REG_MODE_OK_FOR_REG_BASE_P(X, MODE) \
2112 REG_OK_FOR_INDEX_P (X)
35d965d5
RS		 2113\f
2114/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2115 that is a valid memory address for an instruction.
2116 The MODE argument is the machine mode for the MEM expression
76a318e9 2117 that wants to use this address. */
f676971a 2118
f1008e52
RE		 2119#define ARM_BASE_REGISTER_RTX_P(X) \
2120 (GET_CODE (X) == REG && ARM_REG_OK_FOR_BASE_P (X))
35d965d5 2121
f1008e52
RE		 2122#define ARM_INDEX_REGISTER_RTX_P(X) \
2123 (GET_CODE (X) == REG && ARM_REG_OK_FOR_INDEX_P (X))
35d965d5 2124
76a318e9
RE		 2125#define ARM_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
2126 { \
1e1ab407 2127 if (arm_legitimate_address_p (MODE, X, SET, REG_STRICT_P)) \
76a318e9 2128 goto WIN; \
6b990f6b 2129 }
d5b7b3ae 2130
5b3e6663 2131#define THUMB2_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
76a318e9 2132 { \
5b3e6663
PB		 2133 if (thumb2_legitimate_address_p (MODE, X, REG_STRICT_P)) \
2134 goto WIN; \
2135 }
2136
2137#define THUMB1_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
2138 { \
2139 if (thumb1_legitimate_address_p (MODE, X, REG_STRICT_P)) \
76a318e9
RE		 2140 goto WIN; \
2141 }
d5b7b3ae 2142
d5b7b3ae
RE		 2143#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \
2144 if (TARGET_ARM) \
2145 ARM_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN) \
5b3e6663
PB		 2146 else if (TARGET_THUMB2) \
2147 THUMB2_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN) \
2148 else /* if (TARGET_THUMB1) */ \
2149 THUMB1_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN)
76a318e9 2150
35d965d5
RS		 2151\f
2152/* Try machine-dependent ways of modifying an illegitimate address
ccf4d512
RE		 2153 to be legitimate. If we find one, return the new, valid address. */
2154#define ARM_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2155do { \
2156 X = arm_legitimize_address (X, OLDX, MODE); \
ccf4d512
RE		 2157} while (0)
2158
5b3e6663
PB		 2159/* ??? Implement LEGITIMIZE_ADDRESS for thumb2. */
2160#define THUMB2_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2161do { \
2162} while (0)
2163
2164#define THUMB1_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
6f5b4f3e
RE		 2165do { \
2166 X = thumb_legitimize_address (X, OLDX, MODE); \
ccf4d512
RE		 2167} while (0)
2168
2169#define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2170do { \
2171 if (TARGET_ARM) \
2172 ARM_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
5b3e6663
PB		 2173 else if (TARGET_THUMB2) \
2174 THUMB2_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
ccf4d512 2175 else \
5b3e6663 2176 THUMB1_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
6f5b4f3e
RE		 2177 \
2178 if (memory_address_p (MODE, X)) \
2179 goto WIN; \
ccf4d512 2180} while (0)
f676971a 2181
35d965d5
RS		 2182/* Go to LABEL if ADDR (a legitimate address expression)
2183 has an effect that depends on the machine mode it is used for. */
d5b7b3ae 2184#define ARM_GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
35d965d5 2185{ \
d5b7b3ae
RE		 2186 if ( GET_CODE (ADDR) == PRE_DEC || GET_CODE (ADDR) == POST_DEC \
2187 || GET_CODE (ADDR) == PRE_INC || GET_CODE (ADDR) == POST_INC) \
35d965d5
RS		 2188 goto LABEL; \
2189}
d5b7b3ae
RE		 2190
2191/* Nothing helpful to do for the Thumb */
2192#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
5b3e6663 2193 if (TARGET_32BIT) \
f676971a 2194 ARM_GO_IF_MODE_DEPENDENT_ADDRESS (ADDR, LABEL)
35d965d5 2195\f
d5b7b3ae 2196
35d965d5
RS		 2197/* Specify the machine mode that this machine uses
2198 for the index in the tablejump instruction. */
d5b7b3ae 2199#define CASE_VECTOR_MODE Pmode
35d965d5 2200
5b3e6663
PB		 2201#define CASE_VECTOR_PC_RELATIVE TARGET_THUMB2
2202
2203#define CASE_VECTOR_SHORTEN_MODE(min, max, body) \
2204 ((min < 0 || max >= 0x2000 || !TARGET_THUMB2) ? SImode \
2205 : (max >= 0x200) ? HImode \
2206 : QImode)
2207
ff9940b0
RE		 2208/* signed 'char' is most compatible, but RISC OS wants it unsigned.
2209 unsigned is probably best, but may break some code. */
2210#ifndef DEFAULT_SIGNED_CHAR
3967692c 2211#define DEFAULT_SIGNED_CHAR 0
35d965d5
RS		 2212#endif
2213
35d965d5 2214/* Max number of bytes we can move from memory to memory
d17ce9af
TG		 2215 in one reasonably fast instruction. */
2216#define MOVE_MAX 4
35d965d5 2217
d19fb8e3 2218#undef MOVE_RATIO
591af218 2219#define MOVE_RATIO (arm_tune_xscale ? 4 : 2)
d19fb8e3 2220
ff9940b0
RE		 2221/* Define if operations between registers always perform the operation
2222 on the full register even if a narrower mode is specified. */
2223#define WORD_REGISTER_OPERATIONS
2224
2225/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2226 will either zero-extend or sign-extend. The value of this macro should
2227 be the code that says which one of the two operations is implicitly
f822d252 2228 done, UNKNOWN if none. */
9c872872 2229#define LOAD_EXTEND_OP(MODE) \
d5b7b3ae
RE		 2230 (TARGET_THUMB ? ZERO_EXTEND : \
2231 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \
f822d252 2232 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : UNKNOWN)))
ff9940b0 2233
35d965d5
RS		 2234/* Nonzero if access to memory by bytes is slow and undesirable. */
2235#define SLOW_BYTE_ACCESS 0
2236
d5b7b3ae 2237#define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1
f676971a 2238
35d965d5
RS		 2239/* Immediate shift counts are truncated by the output routines (or was it
2240 the assembler?). Shift counts in a register are truncated by ARM. Note
2241 that the native compiler puts too large (> 32) immediate shift counts
2242 into a register and shifts by the register, letting the ARM decide what
2243 to do instead of doing that itself. */
ff9940b0
RE		 2244/* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that
2245 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
2246 On the arm, Y in a register is used modulo 256 for the shift. Only for
d6b4baa4 2247 rotates is modulo 32 used. */
ff9940b0 2248/* #define SHIFT_COUNT_TRUNCATED 1 */
35d965d5 2249
35d965d5 2250/* All integers have the same format so truncation is easy. */
d5b7b3ae 2251#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
35d965d5
RS		 2252
2253/* Calling from registers is a massive pain. */
2254#define NO_FUNCTION_CSE 1
2255
35d965d5
RS		 2256/* The machine modes of pointers and functions */
2257#define Pmode SImode
2258#define FUNCTION_MODE Pmode
2259
d5b7b3ae
RE		 2260#define ARM_FRAME_RTX(X) \
2261 ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
3967692c
RE		 2262 || (X) == arg_pointer_rtx)
2263
ff9940b0 2264/* Moves to and from memory are quite expensive */
d5b7b3ae 2265#define MEMORY_MOVE_COST(M, CLASS, IN) \
5b3e6663 2266 (TARGET_32BIT ? 10 : \
d5b7b3ae
RE		 2267 ((GET_MODE_SIZE (M) < 4 ? 8 : 2 * GET_MODE_SIZE (M)) \
2268 * (CLASS == LO_REGS ? 1 : 2)))
f676971a 2269
ff9940b0
RE		 2270/* Try to generate sequences that don't involve branches, we can then use
2271 conditional instructions */
d5b7b3ae 2272#define BRANCH_COST \
5b3e6663 2273 (TARGET_32BIT ? 4 : (optimize > 0 ? 2 : 0))
7a801826
RE		 2274\f
2275/* Position Independent Code. */
2276/* We decide which register to use based on the compilation options and
2277 the assembler in use; this is more general than the APCS restriction of
2278 using sb (r9) all the time. */
020a4035 2279extern unsigned arm_pic_register;
7a801826
RE		 2280
2281/* The register number of the register used to address a table of static
2282 data addresses in memory. */
2283#define PIC_OFFSET_TABLE_REGNUM arm_pic_register
2284
f5a1b0d2 2285/* We can't directly access anything that contains a symbol,
d3585b76
DJ		 2286 nor can we indirect via the constant pool. One exception is
2287 UNSPEC_TLS, which is always PIC. */
82e9d970 2288#define LEGITIMATE_PIC_OPERAND_P(X) \
1575c31e
JD		 2289 (!(symbol_mentioned_p (X) \
2290 || label_mentioned_p (X) \
2291 || (GET_CODE (X) == SYMBOL_REF \
2292 && CONSTANT_POOL_ADDRESS_P (X) \
2293 && (symbol_mentioned_p (get_pool_constant (X)) \
d3585b76
DJ		 2294 || label_mentioned_p (get_pool_constant (X))))) \
2295 || tls_mentioned_p (X))
1575c31e 2296
13bd191d
PB		 2297/* We need to know when we are making a constant pool; this determines
2298 whether data needs to be in the GOT or can be referenced via a GOT
2299 offset. */
2300extern int making_const_table;
82e9d970 2301\f
c27ba912 2302/* Handle pragmas for compatibility with Intel's compilers. */
c58b209a
NB		 2303#define REGISTER_TARGET_PRAGMAS() do { \
2304 c_register_pragma (0, "long_calls", arm_pr_long_calls); \
2305 c_register_pragma (0, "no_long_calls", arm_pr_no_long_calls); \
2306 c_register_pragma (0, "long_calls_off", arm_pr_long_calls_off); \
8b97c5f8
ZW		 2307} while (0)
2308
d6b4baa4 2309/* Condition code information. */
ff9940b0 2310/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
a5381466 2311 return the mode to be used for the comparison. */
d5b7b3ae
RE		 2312
2313#define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y)
ff9940b0 2314
880873be
RE		 2315#define REVERSIBLE_CC_MODE(MODE) 1
2316
2317#define REVERSE_CONDITION(CODE,MODE) \
2318 (((MODE) == CCFPmode || (MODE) == CCFPEmode) \
2319 ? reverse_condition_maybe_unordered (code) \
2320 : reverse_condition (code))
008cf58a 2321
62b10bbc
NC		 2322#define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \
2323 do \
2324 { \
2325 if (GET_CODE (OP1) == CONST_INT \
2326 && ! (const_ok_for_arm (INTVAL (OP1)) \
2327 || (const_ok_for_arm (- INTVAL (OP1))))) \
2328 { \
2329 rtx const_op = OP1; \
a14b88bb
PB		 2330 CODE = arm_canonicalize_comparison ((CODE), GET_MODE (OP0), \
2331 &const_op); \
62b10bbc
NC		 2332 OP1 = const_op; \
2333 } \
2334 } \
2335 while (0)
62dd06ea 2336
7dba8395
RH		 2337/* The arm5 clz instruction returns 32. */
2338#define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
35d965d5 2339\f
d5b7b3ae 2340#undef ASM_APP_OFF
5b3e6663
PB		 2341#define ASM_APP_OFF (TARGET_THUMB1 ? "\t.code\t16\n" : \
2342 TARGET_THUMB2 ? "\t.thumb\n" : "")
35d965d5 2343
35d965d5 2344/* Output a push or a pop instruction (only used when profiling). */
d5b7b3ae 2345#define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \
8a81cc45
RE		 2346 do \
2347 { \
2348 if (TARGET_ARM) \
2349 asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", \
2350 STACK_POINTER_REGNUM, REGNO); \
2351 else \
2352 asm_fprintf (STREAM, "\tpush {%r}\n", REGNO); \
2353 } while (0)
d5b7b3ae
RE		 2354
2355
2356#define ASM_OUTPUT_REG_POP(STREAM, REGNO) \
8a81cc45
RE		 2357 do \
2358 { \
2359 if (TARGET_ARM) \
2360 asm_fprintf (STREAM, "\tldmfd\t%r!,{%r}\n", \
2361 STACK_POINTER_REGNUM, REGNO); \
2362 else \
2363 asm_fprintf (STREAM, "\tpop {%r}\n", REGNO); \
2364 } while (0)
d5b7b3ae 2365
5b3e6663
PB		 2366/* Jump table alignment is explicit in ASM_OUTPUT_CASE_LABEL. */
2367#define ADDR_VEC_ALIGN(JUMPTABLE) 0
2368
d5b7b3ae
RE		 2369/* This is how to output a label which precedes a jumptable. Since
2370 Thumb instructions are 2 bytes, we may need explicit alignment here. */
be393ecf 2371#undef ASM_OUTPUT_CASE_LABEL
5b3e6663
PB		 2372#define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, JUMPTABLE) \
2373 do \
2374 { \
2375 if (TARGET_THUMB && GET_MODE (PATTERN (JUMPTABLE)) == SImode) \
2376 ASM_OUTPUT_ALIGN (FILE, 2); \
2377 (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \
2378 } \
2379 while (0)
2380
2381/* Make sure subsequent insns are aligned after a TBB. */
2382#define ASM_OUTPUT_CASE_END(FILE, NUM, JUMPTABLE) \
2383 do \
2384 { \
2385 if (GET_MODE (PATTERN (JUMPTABLE)) == QImode) \
2386 ASM_OUTPUT_ALIGN (FILE, 1); \
2387 } \
d5b7b3ae 2388 while (0)
35d965d5 2389
6cfc7210
NC		 2390#define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \
2391 do \
2392 { \
d5b7b3ae
RE		 2393 if (TARGET_THUMB) \
2394 { \
5b3e6663
PB		 2395 if (is_called_in_ARM_mode (DECL) \
2396 || (TARGET_THUMB1 && current_function_is_thunk)) \
d5b7b3ae 2397 fprintf (STREAM, "\t.code 32\n") ; \
5b3e6663
PB		 2398 else if (TARGET_THUMB1) \
2399 fprintf (STREAM, "\t.code\t16\n\t.thumb_func\n") ; \
d5b7b3ae 2400 else \
5b3e6663 2401 fprintf (STREAM, "\t.thumb\n\t.thumb_func\n") ; \
d5b7b3ae 2402 } \
6cfc7210 2403 if (TARGET_POKE_FUNCTION_NAME) \
6354dc9b 2404 arm_poke_function_name (STREAM, (char *) NAME); \
6cfc7210
NC		 2405 } \
2406 while (0)
35d965d5 2407
d5b7b3ae
RE		 2408/* For aliases of functions we use .thumb_set instead. */
2409#define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \
2410 do \
2411 { \
91ea4f8d
KG		 2412 const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \
2413 const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \
d5b7b3ae
RE		 2414 \
2415 if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \
2416 { \
2417 fprintf (FILE, "\t.thumb_set "); \
2418 assemble_name (FILE, LABEL1); \
2419 fprintf (FILE, ","); \
2420 assemble_name (FILE, LABEL2); \
2421 fprintf (FILE, "\n"); \
2422 } \
2423 else \
2424 ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \
2425 } \
2426 while (0)
2427
fdc2d3b0
NC		 2428#ifdef HAVE_GAS_MAX_SKIP_P2ALIGN
2429/* To support -falign-* switches we need to use .p2align so
2430 that alignment directives in code sections will be padded
2431 with no-op instructions, rather than zeroes. */
5a9335ef 2432#define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE, LOG, MAX_SKIP) \
fdc2d3b0
NC		 2433 if ((LOG) != 0) \
2434 { \
2435 if ((MAX_SKIP) == 0) \
5a9335ef 2436 fprintf ((FILE), "\t.p2align %d\n", (int) (LOG)); \
fdc2d3b0
NC		 2437 else \
2438 fprintf ((FILE), "\t.p2align %d,,%d\n", \
5a9335ef 2439 (int) (LOG), (int) (MAX_SKIP)); \
fdc2d3b0
NC		 2440 }
2441#endif
35d965d5 2442\f
5b3e6663
PB		 2443/* Add two bytes to the length of conditionally executed Thumb-2
2444 instructions for the IT instruction. */
2445#define ADJUST_INSN_LENGTH(insn, length) \
2446 if (TARGET_THUMB2 && GET_CODE (PATTERN (insn)) == COND_EXEC) \
2447 length += 2;
2448
35d965d5 2449/* Only perform branch elimination (by making instructions conditional) if
5b3e6663
PB		 2450 we're optimizing. For Thumb-2 check if any IT instructions need
2451 outputting. */
d5b7b3ae
RE		 2452#define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2453 if (TARGET_ARM && optimize) \
2454 arm_final_prescan_insn (INSN); \
5b3e6663
PB		 2455 else if (TARGET_THUMB2) \
2456 thumb2_final_prescan_insn (INSN); \
2457 else if (TARGET_THUMB1) \
2458 thumb1_final_prescan_insn (INSN)
35d965d5 2459
7bc7696c 2460#define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
5b3e6663 2461 (CODE == '@' || CODE == '|' || CODE == '.' \
88f77cba 2462 || CODE == '(' || CODE == ')' || CODE == '#' \
5b3e6663
PB		 2463 || (TARGET_32BIT && (CODE == '?')) \
2464 || (TARGET_THUMB2 && (CODE == '!')) \
d5b7b3ae 2465 || (TARGET_THUMB && (CODE == '_')))
6cfc7210 2466
7bc7696c 2467/* Output an operand of an instruction. */
35d965d5 2468#define PRINT_OPERAND(STREAM, X, CODE) \
7bc7696c
RE		 2469 arm_print_operand (STREAM, X, CODE)
2470
7b8b8ade
NC		 2471#define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \
2472 (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \
30cf4896
KG		 2473 : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\
2474 ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \
2475 ? ((~ (unsigned HOST_WIDE_INT) 0) \
2476 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \
7bc7696c 2477 : 0))))
35d965d5
RS		 2478
2479/* Output the address of an operand. */
3cd45774
RE		 2480#define ARM_PRINT_OPERAND_ADDRESS(STREAM, X) \
2481{ \
2482 int is_minus = GET_CODE (X) == MINUS; \
2483 \
2484 if (GET_CODE (X) == REG) \
2485 asm_fprintf (STREAM, "[%r, #0]", REGNO (X)); \
2486 else if (GET_CODE (X) == PLUS || is_minus) \
2487 { \
2488 rtx base = XEXP (X, 0); \
2489 rtx index = XEXP (X, 1); \
2490 HOST_WIDE_INT offset = 0; \
2491 if (GET_CODE (base) != REG) \
2492 { \
d6b4baa4
KH		 2493 /* Ensure that BASE is a register. */ \
2494 /* (one of them must be). */ \
3cd45774
RE		 2495 rtx temp = base; \
2496 base = index; \
2497 index = temp; \
2498 } \
2499 switch (GET_CODE (index)) \
2500 { \
2501 case CONST_INT: \
2502 offset = INTVAL (index); \
2503 if (is_minus) \
2504 offset = -offset; \
c53dddc2 2505 asm_fprintf (STREAM, "[%r, #%wd]", \
3cd45774
RE		 2506 REGNO (base), offset); \
2507 break; \
2508 \
2509 case REG: \
2510 asm_fprintf (STREAM, "[%r, %s%r]", \
2511 REGNO (base), is_minus ? "-" : "", \
2512 REGNO (index)); \
2513 break; \
2514 \
2515 case MULT: \
2516 case ASHIFTRT: \
2517 case LSHIFTRT: \
2518 case ASHIFT: \
2519 case ROTATERT: \
2520 { \
2521 asm_fprintf (STREAM, "[%r, %s%r", \
2522 REGNO (base), is_minus ? "-" : "", \
2523 REGNO (XEXP (index, 0))); \
2524 arm_print_operand (STREAM, index, 'S'); \
2525 fputs ("]", STREAM); \
2526 break; \
2527 } \
2528 \
2529 default: \
e6d29d15 2530 gcc_unreachable (); \
3cd45774
RE		 2531 } \
2532 } \
2533 else if (GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC \
2534 || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC) \
2535 { \
2536 extern enum machine_mode output_memory_reference_mode; \
2537 \
e6d29d15 2538 gcc_assert (GET_CODE (XEXP (X, 0)) == REG); \
3cd45774
RE		 2539 \
2540 if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \
2541 asm_fprintf (STREAM, "[%r, #%s%d]!", \
2542 REGNO (XEXP (X, 0)), \
2543 GET_CODE (X) == PRE_DEC ? "-" : "", \
2544 GET_MODE_SIZE (output_memory_reference_mode)); \
2545 else \
2546 asm_fprintf (STREAM, "[%r], #%s%d", \
2547 REGNO (XEXP (X, 0)), \
2548 GET_CODE (X) == POST_DEC ? "-" : "", \
2549 GET_MODE_SIZE (output_memory_reference_mode)); \
2550 } \
2551 else if (GET_CODE (X) == PRE_MODIFY) \
2552 { \
2553 asm_fprintf (STREAM, "[%r, ", REGNO (XEXP (X, 0))); \
2554 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \
c53dddc2 2555 asm_fprintf (STREAM, "#%wd]!", \
3cd45774
RE		 2556 INTVAL (XEXP (XEXP (X, 1), 1))); \
2557 else \
2558 asm_fprintf (STREAM, "%r]!", \
2559 REGNO (XEXP (XEXP (X, 1), 1))); \
2560 } \
2561 else if (GET_CODE (X) == POST_MODIFY) \
2562 { \
2563 asm_fprintf (STREAM, "[%r], ", REGNO (XEXP (X, 0))); \
2564 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \
c53dddc2 2565 asm_fprintf (STREAM, "#%wd", \
3cd45774
RE		 2566 INTVAL (XEXP (XEXP (X, 1), 1))); \
2567 else \
2568 asm_fprintf (STREAM, "%r", \
2569 REGNO (XEXP (XEXP (X, 1), 1))); \
2570 } \
2571 else output_addr_const (STREAM, X); \
35d965d5 2572}
62dd06ea 2573
d5b7b3ae
RE		 2574#define THUMB_PRINT_OPERAND_ADDRESS(STREAM, X) \
2575{ \
2576 if (GET_CODE (X) == REG) \
2577 asm_fprintf (STREAM, "[%r]", REGNO (X)); \
2578 else if (GET_CODE (X) == POST_INC) \
2579 asm_fprintf (STREAM, "%r!", REGNO (XEXP (X, 0))); \
2580 else if (GET_CODE (X) == PLUS) \
2581 { \
e6d29d15 2582 gcc_assert (GET_CODE (XEXP (X, 0)) == REG); \
d5b7b3ae 2583 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
659bdc68 2584 asm_fprintf (STREAM, "[%r, #%wd]", \
d5b7b3ae 2585 REGNO (XEXP (X, 0)), \
659bdc68 2586 INTVAL (XEXP (X, 1))); \
d5b7b3ae
RE		 2587 else \
2588 asm_fprintf (STREAM, "[%r, %r]", \
2589 REGNO (XEXP (X, 0)), \
2590 REGNO (XEXP (X, 1))); \
2591 } \
2592 else \
2593 output_addr_const (STREAM, X); \
2594}
2595
2596#define PRINT_OPERAND_ADDRESS(STREAM, X) \
5b3e6663 2597 if (TARGET_32BIT) \
d5b7b3ae
RE		 2598 ARM_PRINT_OPERAND_ADDRESS (STREAM, X) \
2599 else \
2600 THUMB_PRINT_OPERAND_ADDRESS (STREAM, X)
5a9335ef 2601
d3585b76
DJ		 2602#define OUTPUT_ADDR_CONST_EXTRA(file, x, fail) \
2603 if (arm_output_addr_const_extra (file, x) == FALSE) \
2604 goto fail
5a9335ef 2605
6a5d7526
MS		 2606/* A C expression whose value is RTL representing the value of the return
2607 address for the frame COUNT steps up from the current frame. */
2608
d5b7b3ae
RE		 2609#define RETURN_ADDR_RTX(COUNT, FRAME) \
2610 arm_return_addr (COUNT, FRAME)
2611
f676971a 2612/* Mask of the bits in the PC that contain the real return address
d5b7b3ae
RE		 2613 when running in 26-bit mode. */
2614#define RETURN_ADDR_MASK26 (0x03fffffc)
6a5d7526 2615
2c849145
JM		 2616/* Pick up the return address upon entry to a procedure. Used for
2617 dwarf2 unwind information. This also enables the table driven
2618 mechanism. */
2c849145
JM		 2619#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM)
2620#define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM)
2621
39950dff
MS		 2622/* Used to mask out junk bits from the return address, such as
2623 processor state, interrupt status, condition codes and the like. */
2624#define MASK_RETURN_ADDR \
2625 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \
2626 in 26 bit mode, the condition codes must be masked out of the \
2627 return address. This does not apply to ARM6 and later processors \
2628 when running in 32 bit mode. */ \
61f0ccff
RE		 2629 ((arm_arch4 || TARGET_THUMB) \
2630 ? (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \
fcd53748 2631 : arm_gen_return_addr_mask ())
d5b7b3ae
RE		 2632
2633\f
88f77cba
JB		 2634/* Neon defines builtins from ARM_BUILTIN_MAX upwards, though they don't have
2635 symbolic names defined here (which would require too much duplication).
2636 FIXME? */
5a9335ef
NC		 2637enum arm_builtins
2638{
2639 ARM_BUILTIN_GETWCX,
2640 ARM_BUILTIN_SETWCX,
2641
2642 ARM_BUILTIN_WZERO,
2643
2644 ARM_BUILTIN_WAVG2BR,
2645 ARM_BUILTIN_WAVG2HR,
2646 ARM_BUILTIN_WAVG2B,
2647 ARM_BUILTIN_WAVG2H,
2648
2649 ARM_BUILTIN_WACCB,
2650 ARM_BUILTIN_WACCH,
2651 ARM_BUILTIN_WACCW,
2652
2653 ARM_BUILTIN_WMACS,
2654 ARM_BUILTIN_WMACSZ,
2655 ARM_BUILTIN_WMACU,
2656 ARM_BUILTIN_WMACUZ,
2657
2658 ARM_BUILTIN_WSADB,
2659 ARM_BUILTIN_WSADBZ,
2660 ARM_BUILTIN_WSADH,
2661 ARM_BUILTIN_WSADHZ,
2662
2663 ARM_BUILTIN_WALIGN,
2664
2665 ARM_BUILTIN_TMIA,
2666 ARM_BUILTIN_TMIAPH,
2667 ARM_BUILTIN_TMIABB,
2668 ARM_BUILTIN_TMIABT,
2669 ARM_BUILTIN_TMIATB,
2670 ARM_BUILTIN_TMIATT,
2671
2672 ARM_BUILTIN_TMOVMSKB,
2673 ARM_BUILTIN_TMOVMSKH,
2674 ARM_BUILTIN_TMOVMSKW,
2675
2676 ARM_BUILTIN_TBCSTB,
2677 ARM_BUILTIN_TBCSTH,
2678 ARM_BUILTIN_TBCSTW,
2679
2680 ARM_BUILTIN_WMADDS,
2681 ARM_BUILTIN_WMADDU,
2682
2683 ARM_BUILTIN_WPACKHSS,
2684 ARM_BUILTIN_WPACKWSS,
2685 ARM_BUILTIN_WPACKDSS,
2686 ARM_BUILTIN_WPACKHUS,
2687 ARM_BUILTIN_WPACKWUS,
2688 ARM_BUILTIN_WPACKDUS,
2689
2690 ARM_BUILTIN_WADDB,
2691 ARM_BUILTIN_WADDH,
2692 ARM_BUILTIN_WADDW,
2693 ARM_BUILTIN_WADDSSB,
2694 ARM_BUILTIN_WADDSSH,
2695 ARM_BUILTIN_WADDSSW,
2696 ARM_BUILTIN_WADDUSB,
2697 ARM_BUILTIN_WADDUSH,
2698 ARM_BUILTIN_WADDUSW,
2699 ARM_BUILTIN_WSUBB,
2700 ARM_BUILTIN_WSUBH,
2701 ARM_BUILTIN_WSUBW,
2702 ARM_BUILTIN_WSUBSSB,
2703 ARM_BUILTIN_WSUBSSH,
2704 ARM_BUILTIN_WSUBSSW,
2705 ARM_BUILTIN_WSUBUSB,
2706 ARM_BUILTIN_WSUBUSH,
2707 ARM_BUILTIN_WSUBUSW,
2708
2709 ARM_BUILTIN_WAND,
2710 ARM_BUILTIN_WANDN,
2711 ARM_BUILTIN_WOR,
2712 ARM_BUILTIN_WXOR,
2713
2714 ARM_BUILTIN_WCMPEQB,
2715 ARM_BUILTIN_WCMPEQH,
2716 ARM_BUILTIN_WCMPEQW,
2717 ARM_BUILTIN_WCMPGTUB,
2718 ARM_BUILTIN_WCMPGTUH,
2719 ARM_BUILTIN_WCMPGTUW,
2720 ARM_BUILTIN_WCMPGTSB,
2721 ARM_BUILTIN_WCMPGTSH,
2722 ARM_BUILTIN_WCMPGTSW,
2723
2724 ARM_BUILTIN_TEXTRMSB,
2725 ARM_BUILTIN_TEXTRMSH,
2726 ARM_BUILTIN_TEXTRMSW,
2727 ARM_BUILTIN_TEXTRMUB,
2728 ARM_BUILTIN_TEXTRMUH,
2729 ARM_BUILTIN_TEXTRMUW,
2730 ARM_BUILTIN_TINSRB,
2731 ARM_BUILTIN_TINSRH,
2732 ARM_BUILTIN_TINSRW,
2733
2734 ARM_BUILTIN_WMAXSW,
2735 ARM_BUILTIN_WMAXSH,
2736 ARM_BUILTIN_WMAXSB,
2737 ARM_BUILTIN_WMAXUW,
2738 ARM_BUILTIN_WMAXUH,
2739 ARM_BUILTIN_WMAXUB,
2740 ARM_BUILTIN_WMINSW,
2741 ARM_BUILTIN_WMINSH,
2742 ARM_BUILTIN_WMINSB,
2743 ARM_BUILTIN_WMINUW,
2744 ARM_BUILTIN_WMINUH,
2745 ARM_BUILTIN_WMINUB,
2746
f07a6b21
BE		 2747 ARM_BUILTIN_WMULUM,
2748 ARM_BUILTIN_WMULSM,
5a9335ef
NC		 2749 ARM_BUILTIN_WMULUL,
2750
2751 ARM_BUILTIN_PSADBH,
2752 ARM_BUILTIN_WSHUFH,
2753
2754 ARM_BUILTIN_WSLLH,
2755 ARM_BUILTIN_WSLLW,
2756 ARM_BUILTIN_WSLLD,
2757 ARM_BUILTIN_WSRAH,
2758 ARM_BUILTIN_WSRAW,
2759 ARM_BUILTIN_WSRAD,
2760 ARM_BUILTIN_WSRLH,
2761 ARM_BUILTIN_WSRLW,
2762 ARM_BUILTIN_WSRLD,
2763 ARM_BUILTIN_WRORH,
2764 ARM_BUILTIN_WRORW,
2765 ARM_BUILTIN_WRORD,
2766 ARM_BUILTIN_WSLLHI,
2767 ARM_BUILTIN_WSLLWI,
2768 ARM_BUILTIN_WSLLDI,
2769 ARM_BUILTIN_WSRAHI,
2770 ARM_BUILTIN_WSRAWI,
2771 ARM_BUILTIN_WSRADI,
2772 ARM_BUILTIN_WSRLHI,
2773 ARM_BUILTIN_WSRLWI,
2774 ARM_BUILTIN_WSRLDI,
2775 ARM_BUILTIN_WRORHI,
2776 ARM_BUILTIN_WRORWI,
2777 ARM_BUILTIN_WRORDI,
2778
2779 ARM_BUILTIN_WUNPCKIHB,
2780 ARM_BUILTIN_WUNPCKIHH,
2781 ARM_BUILTIN_WUNPCKIHW,
2782 ARM_BUILTIN_WUNPCKILB,
2783 ARM_BUILTIN_WUNPCKILH,
2784 ARM_BUILTIN_WUNPCKILW,
2785
2786 ARM_BUILTIN_WUNPCKEHSB,
2787 ARM_BUILTIN_WUNPCKEHSH,
2788 ARM_BUILTIN_WUNPCKEHSW,
2789 ARM_BUILTIN_WUNPCKEHUB,
2790 ARM_BUILTIN_WUNPCKEHUH,
2791 ARM_BUILTIN_WUNPCKEHUW,
2792 ARM_BUILTIN_WUNPCKELSB,
2793 ARM_BUILTIN_WUNPCKELSH,
2794 ARM_BUILTIN_WUNPCKELSW,
2795 ARM_BUILTIN_WUNPCKELUB,
2796 ARM_BUILTIN_WUNPCKELUH,
2797 ARM_BUILTIN_WUNPCKELUW,
2798
d3585b76
DJ		 2799 ARM_BUILTIN_THREAD_POINTER,
2800
88f77cba
JB		 2801 ARM_BUILTIN_NEON_BASE,
2802
2803 ARM_BUILTIN_MAX = ARM_BUILTIN_NEON_BASE /* FIXME: Wrong! */
5a9335ef 2804};
978e411f
CD		 2805
2806/* Do not emit .note.GNU-stack by default. */
2807#ifndef NEED_INDICATE_EXEC_STACK
2808#define NEED_INDICATE_EXEC_STACK 0
2809#endif
2810
88657302 2811#endif /* ! GCC_ARM_H */
Mirror of https://gcc.gnu.org/git/gcc.git