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f5a1b0d2 | 1 | /* Definitions of target machine for GNU compiler, for ARM. |
cf011243 | 2 | Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, |
16c484c7 | 3 | 2001, 2002 Free Software Foundation, Inc. |
35d965d5 | 4 | Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl) |
8b109b37 | 5 | and Martin Simmons (@harleqn.co.uk). |
949d79eb | 6 | More major hacks by Richard Earnshaw (rearnsha@arm.com) |
6cfc7210 NC |
7 | Minor hacks by Nick Clifton (nickc@cygnus.com) |
8 | ||
35d965d5 RS |
9 | This file is part of GNU CC. |
10 | ||
11 | GNU CC is free software; you can redistribute it and/or modify | |
12 | it under the terms of the GNU General Public License as published by | |
13 | the Free Software Foundation; either version 2, or (at your option) | |
14 | any later version. | |
15 | ||
16 | GNU CC is distributed in the hope that it will be useful, | |
17 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | GNU General Public License for more details. | |
20 | ||
21 | You should have received a copy of the GNU General Public License | |
22 | along with GNU CC; see the file COPYING. If not, write to | |
8fb289e7 RK |
23 | the Free Software Foundation, 59 Temple Place - Suite 330, |
24 | Boston, MA 02111-1307, USA. */ | |
35d965d5 | 25 | |
88657302 RH |
26 | #ifndef GCC_ARM_H |
27 | #define GCC_ARM_H | |
b355a481 | 28 | |
e6471be6 NB |
29 | /* Target CPU builtins. */ |
30 | #define TARGET_CPU_CPP_BUILTINS() \ | |
31 | do \ | |
32 | { \ | |
48f6efae | 33 | if (TARGET_ARM) \ |
e6471be6 NB |
34 | builtin_define ("__arm__"); \ |
35 | else \ | |
36 | builtin_define ("__thumb__"); \ | |
37 | \ | |
38 | if (TARGET_BIG_END) \ | |
39 | { \ | |
40 | builtin_define ("__ARMEB__"); \ | |
41 | if (TARGET_THUMB) \ | |
42 | builtin_define ("__THUMBEB__"); \ | |
43 | if (TARGET_LITTLE_WORDS) \ | |
44 | builtin_define ("__ARMWEL__"); \ | |
45 | } \ | |
46 | else \ | |
47 | { \ | |
48 | builtin_define ("__ARMEL__"); \ | |
49 | if (TARGET_THUMB) \ | |
50 | builtin_define ("__THUMBEL__"); \ | |
51 | } \ | |
52 | \ | |
53 | if (TARGET_APCS_32) \ | |
54 | builtin_define ("__APCS_32__"); \ | |
55 | else \ | |
56 | builtin_define ("__APCS_26__"); \ | |
57 | \ | |
58 | if (TARGET_SOFT_FLOAT) \ | |
59 | builtin_define ("__SOFTFP__"); \ | |
60 | \ | |
61 | /* Add a define for interworking. \ | |
62 | Needed when building libgcc.a. */ \ | |
63 | if (TARGET_INTERWORK) \ | |
64 | builtin_define ("__THUMB_INTERWORK__"); \ | |
65 | \ | |
66 | builtin_assert ("cpu=arm"); \ | |
67 | builtin_assert ("machine=arm"); \ | |
68 | } while (0) | |
69 | ||
7a801826 RE |
70 | #define TARGET_CPU_arm2 0x0000 |
71 | #define TARGET_CPU_arm250 0x0000 | |
72 | #define TARGET_CPU_arm3 0x0000 | |
73 | #define TARGET_CPU_arm6 0x0001 | |
74 | #define TARGET_CPU_arm600 0x0001 | |
75 | #define TARGET_CPU_arm610 0x0002 | |
76 | #define TARGET_CPU_arm7 0x0001 | |
77 | #define TARGET_CPU_arm7m 0x0004 | |
78 | #define TARGET_CPU_arm7dm 0x0004 | |
79 | #define TARGET_CPU_arm7dmi 0x0004 | |
80 | #define TARGET_CPU_arm700 0x0001 | |
81 | #define TARGET_CPU_arm710 0x0002 | |
82 | #define TARGET_CPU_arm7100 0x0002 | |
83 | #define TARGET_CPU_arm7500 0x0002 | |
84 | #define TARGET_CPU_arm7500fe 0x1001 | |
85 | #define TARGET_CPU_arm7tdmi 0x0008 | |
86 | #define TARGET_CPU_arm8 0x0010 | |
87 | #define TARGET_CPU_arm810 0x0020 | |
88 | #define TARGET_CPU_strongarm 0x0040 | |
89 | #define TARGET_CPU_strongarm110 0x0040 | |
f5a1b0d2 | 90 | #define TARGET_CPU_strongarm1100 0x0040 |
b36ba79f RE |
91 | #define TARGET_CPU_arm9 0x0080 |
92 | #define TARGET_CPU_arm9tdmi 0x0080 | |
d19fb8e3 | 93 | #define TARGET_CPU_xscale 0x0100 |
82e9d970 | 94 | /* Configure didn't specify. */ |
7a801826 | 95 | #define TARGET_CPU_generic 0x8000 |
ff9940b0 | 96 | |
d5b7b3ae | 97 | typedef enum arm_cond_code |
89c7ca52 RE |
98 | { |
99 | ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC, | |
100 | ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV | |
d5b7b3ae RE |
101 | } |
102 | arm_cc; | |
6cfc7210 | 103 | |
d5b7b3ae | 104 | extern arm_cc arm_current_cc; |
ff9940b0 | 105 | |
d5b7b3ae | 106 | #define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1)) |
89c7ca52 | 107 | |
6cfc7210 NC |
108 | extern int arm_target_label; |
109 | extern int arm_ccfsm_state; | |
e2500fed | 110 | extern GTY(()) rtx arm_target_insn; |
6cfc7210 NC |
111 | /* Run-time compilation parameters selecting different hardware subsets. */ |
112 | extern int target_flags; | |
113 | /* The floating point instruction architecture, can be 2 or 3 */ | |
114 | extern const char * target_fp_name; | |
d5b7b3ae | 115 | /* Define the information needed to generate branch insns. This is |
e2500fed GK |
116 | stored from the compare operation. */ |
117 | extern GTY(()) rtx arm_compare_op0; | |
118 | extern GTY(()) rtx arm_compare_op1; | |
d5b7b3ae | 119 | /* The label of the current constant pool. */ |
e2500fed | 120 | extern rtx pool_vector_label; |
d5b7b3ae RE |
121 | /* Set to 1 when a return insn is output, this means that the epilogue |
122 | is not needed. */ | |
123 | extern int return_used_this_function; | |
e2500fed GK |
124 | /* Used to produce AOF syntax assembler. */ |
125 | extern GTY(()) rtx aof_pic_label; | |
35d965d5 | 126 | \f |
7a801826 RE |
127 | /* Just in case configure has failed to define anything. */ |
128 | #ifndef TARGET_CPU_DEFAULT | |
129 | #define TARGET_CPU_DEFAULT TARGET_CPU_generic | |
130 | #endif | |
131 | ||
132 | /* If the configuration file doesn't specify the cpu, the subtarget may | |
70f24e49 | 133 | override it. If it doesn't, then default to an ARM6. */ |
7a801826 RE |
134 | #if TARGET_CPU_DEFAULT == TARGET_CPU_generic |
135 | #undef TARGET_CPU_DEFAULT | |
70f24e49 | 136 | |
7a801826 RE |
137 | #ifdef SUBTARGET_CPU_DEFAULT |
138 | #define TARGET_CPU_DEFAULT SUBTARGET_CPU_DEFAULT | |
139 | #else | |
140 | #define TARGET_CPU_DEFAULT TARGET_CPU_arm6 | |
141 | #endif | |
142 | #endif | |
143 | ||
144 | #if TARGET_CPU_DEFAULT == TARGET_CPU_arm2 | |
145 | #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_2__" | |
146 | #else | |
18543a22 | 147 | #if TARGET_CPU_DEFAULT == TARGET_CPU_arm6 || TARGET_CPU_DEFAULT == TARGET_CPU_arm610 || TARGET_CPU_DEFAULT == TARGET_CPU_arm7500fe |
7a801826 RE |
148 | #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_3__" |
149 | #else | |
150 | #if TARGET_CPU_DEFAULT == TARGET_CPU_arm7m | |
151 | #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_3M__" | |
152 | #else | |
70f24e49 | 153 | #if TARGET_CPU_DEFAULT == TARGET_CPU_arm7tdmi || TARGET_CPU_DEFAULT == TARGET_CPU_arm9 || TARGET_CPU_DEFAULT == TARGET_CPU_arm9tdmi |
7a801826 RE |
154 | #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4T__" |
155 | #else | |
dc60a41b | 156 | #if TARGET_CPU_DEFAULT == TARGET_CPU_arm8 || TARGET_CPU_DEFAULT == TARGET_CPU_arm810 || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm110 || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm1100 |
7a801826 RE |
157 | #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4__" |
158 | #else | |
d19fb8e3 NC |
159 | #if TARGET_CPU_DEFAULT == TARGET_CPU_xscale |
160 | #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_5TE__ -D__XSCALE__" | |
161 | #else | |
7a801826 RE |
162 | Unrecognized value in TARGET_CPU_DEFAULT. |
163 | #endif | |
164 | #endif | |
165 | #endif | |
166 | #endif | |
167 | #endif | |
d19fb8e3 | 168 | #endif |
7a801826 | 169 | |
5742588d | 170 | #undef CPP_SPEC |
e6471be6 NB |
171 | #define CPP_SPEC "%(cpp_cpu_arch) %(subtarget_cpp_spec) \ |
172 | %{mapcs-32:%{mapcs-26: \ | |
173 | %e-mapcs-26 and -mapcs-32 may not be used together}} \ | |
174 | %{msoft-float:%{mhard-float: \ | |
175 | %e-msoft-float and -mhard_float may not be used together}} \ | |
176 | %{mbig-endian:%{mlittle-endian: \ | |
177 | %e-mbig-endian and -mlittle-endian may not be used together}}" | |
7a801826 | 178 | |
71791e16 RE |
179 | /* Set the architecture define -- if -march= is set, then it overrides |
180 | the -mcpu= setting. */ | |
7a801826 | 181 | #define CPP_CPU_ARCH_SPEC "\ |
71791e16 RE |
182 | %{march=arm2:-D__ARM_ARCH_2__} \ |
183 | %{march=arm250:-D__ARM_ARCH_2__} \ | |
184 | %{march=arm3:-D__ARM_ARCH_2__} \ | |
185 | %{march=arm6:-D__ARM_ARCH_3__} \ | |
186 | %{march=arm600:-D__ARM_ARCH_3__} \ | |
187 | %{march=arm610:-D__ARM_ARCH_3__} \ | |
188 | %{march=arm7:-D__ARM_ARCH_3__} \ | |
189 | %{march=arm700:-D__ARM_ARCH_3__} \ | |
190 | %{march=arm710:-D__ARM_ARCH_3__} \ | |
a120a3bd | 191 | %{march=arm720:-D__ARM_ARCH_3__} \ |
71791e16 RE |
192 | %{march=arm7100:-D__ARM_ARCH_3__} \ |
193 | %{march=arm7500:-D__ARM_ARCH_3__} \ | |
194 | %{march=arm7500fe:-D__ARM_ARCH_3__} \ | |
195 | %{march=arm7m:-D__ARM_ARCH_3M__} \ | |
196 | %{march=arm7dm:-D__ARM_ARCH_3M__} \ | |
197 | %{march=arm7dmi:-D__ARM_ARCH_3M__} \ | |
198 | %{march=arm7tdmi:-D__ARM_ARCH_4T__} \ | |
199 | %{march=arm8:-D__ARM_ARCH_4__} \ | |
200 | %{march=arm810:-D__ARM_ARCH_4__} \ | |
b36ba79f | 201 | %{march=arm9:-D__ARM_ARCH_4T__} \ |
60d0536b NC |
202 | %{march=arm920:-D__ARM_ARCH_4__} \ |
203 | %{march=arm920t:-D__ARM_ARCH_4T__} \ | |
b36ba79f | 204 | %{march=arm9tdmi:-D__ARM_ARCH_4T__} \ |
71791e16 RE |
205 | %{march=strongarm:-D__ARM_ARCH_4__} \ |
206 | %{march=strongarm110:-D__ARM_ARCH_4__} \ | |
f5a1b0d2 | 207 | %{march=strongarm1100:-D__ARM_ARCH_4__} \ |
d19fb8e3 NC |
208 | %{march=xscale:-D__ARM_ARCH_5TE__} \ |
209 | %{march=xscale:-D__XSCALE__} \ | |
71791e16 RE |
210 | %{march=armv2:-D__ARM_ARCH_2__} \ |
211 | %{march=armv2a:-D__ARM_ARCH_2__} \ | |
212 | %{march=armv3:-D__ARM_ARCH_3__} \ | |
213 | %{march=armv3m:-D__ARM_ARCH_3M__} \ | |
214 | %{march=armv4:-D__ARM_ARCH_4__} \ | |
215 | %{march=armv4t:-D__ARM_ARCH_4T__} \ | |
62b10bbc | 216 | %{march=armv5:-D__ARM_ARCH_5__} \ |
d5b7b3ae RE |
217 | %{march=armv5t:-D__ARM_ARCH_5T__} \ |
218 | %{march=armv5e:-D__ARM_ARCH_5E__} \ | |
219 | %{march=armv5te:-D__ARM_ARCH_5TE__} \ | |
71791e16 RE |
220 | %{!march=*: \ |
221 | %{mcpu=arm2:-D__ARM_ARCH_2__} \ | |
222 | %{mcpu=arm250:-D__ARM_ARCH_2__} \ | |
223 | %{mcpu=arm3:-D__ARM_ARCH_2__} \ | |
224 | %{mcpu=arm6:-D__ARM_ARCH_3__} \ | |
225 | %{mcpu=arm600:-D__ARM_ARCH_3__} \ | |
226 | %{mcpu=arm610:-D__ARM_ARCH_3__} \ | |
227 | %{mcpu=arm7:-D__ARM_ARCH_3__} \ | |
228 | %{mcpu=arm700:-D__ARM_ARCH_3__} \ | |
229 | %{mcpu=arm710:-D__ARM_ARCH_3__} \ | |
a120a3bd | 230 | %{mcpu=arm720:-D__ARM_ARCH_3__} \ |
71791e16 RE |
231 | %{mcpu=arm7100:-D__ARM_ARCH_3__} \ |
232 | %{mcpu=arm7500:-D__ARM_ARCH_3__} \ | |
233 | %{mcpu=arm7500fe:-D__ARM_ARCH_3__} \ | |
234 | %{mcpu=arm7m:-D__ARM_ARCH_3M__} \ | |
235 | %{mcpu=arm7dm:-D__ARM_ARCH_3M__} \ | |
236 | %{mcpu=arm7dmi:-D__ARM_ARCH_3M__} \ | |
237 | %{mcpu=arm7tdmi:-D__ARM_ARCH_4T__} \ | |
238 | %{mcpu=arm8:-D__ARM_ARCH_4__} \ | |
239 | %{mcpu=arm810:-D__ARM_ARCH_4__} \ | |
b36ba79f | 240 | %{mcpu=arm9:-D__ARM_ARCH_4T__} \ |
60d0536b NC |
241 | %{mcpu=arm920:-D__ARM_ARCH_4__} \ |
242 | %{mcpu=arm920t:-D__ARM_ARCH_4T__} \ | |
b36ba79f | 243 | %{mcpu=arm9tdmi:-D__ARM_ARCH_4T__} \ |
71791e16 RE |
244 | %{mcpu=strongarm:-D__ARM_ARCH_4__} \ |
245 | %{mcpu=strongarm110:-D__ARM_ARCH_4__} \ | |
f5a1b0d2 | 246 | %{mcpu=strongarm1100:-D__ARM_ARCH_4__} \ |
d19fb8e3 NC |
247 | %{mcpu=xscale:-D__ARM_ARCH_5TE__} \ |
248 | %{mcpu=xscale:-D__XSCALE__} \ | |
dfa08768 | 249 | %{!mcpu*:%(cpp_cpu_arch_default)}} \ |
11c1a207 | 250 | " |
7a801826 | 251 | |
be393ecf | 252 | #ifndef CC1_SPEC |
dfa08768 | 253 | #define CC1_SPEC "" |
be393ecf | 254 | #endif |
7a801826 RE |
255 | |
256 | /* This macro defines names of additional specifications to put in the specs | |
257 | that can be used in various specifications like CC1_SPEC. Its definition | |
258 | is an initializer with a subgrouping for each command option. | |
259 | ||
260 | Each subgrouping contains a string constant, that defines the | |
261 | specification name, and a string constant that used by the GNU CC driver | |
262 | program. | |
263 | ||
264 | Do not define this macro if it does not need to do anything. */ | |
265 | #define EXTRA_SPECS \ | |
266 | { "cpp_cpu_arch", CPP_CPU_ARCH_SPEC }, \ | |
267 | { "cpp_cpu_arch_default", CPP_ARCH_DEFAULT_SPEC }, \ | |
38fc909b | 268 | { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \ |
7a801826 RE |
269 | SUBTARGET_EXTRA_SPECS |
270 | ||
914a3b8c | 271 | #ifndef SUBTARGET_EXTRA_SPECS |
7a801826 | 272 | #define SUBTARGET_EXTRA_SPECS |
914a3b8c DM |
273 | #endif |
274 | ||
6cfc7210 | 275 | #ifndef SUBTARGET_CPP_SPEC |
38fc909b | 276 | #define SUBTARGET_CPP_SPEC "" |
6cfc7210 | 277 | #endif |
35d965d5 RS |
278 | \f |
279 | /* Run-time Target Specification. */ | |
ff9940b0 | 280 | #ifndef TARGET_VERSION |
6cfc7210 | 281 | #define TARGET_VERSION fputs (" (ARM/generic)", stderr); |
ff9940b0 | 282 | #endif |
35d965d5 | 283 | |
35d965d5 RS |
284 | /* Nonzero if the function prologue (and epilogue) should obey |
285 | the ARM Procedure Call Standard. */ | |
6cfc7210 | 286 | #define ARM_FLAG_APCS_FRAME (1 << 0) |
35d965d5 RS |
287 | |
288 | /* Nonzero if the function prologue should output the function name to enable | |
289 | the post mortem debugger to print a backtrace (very useful on RISCOS, | |
11c1a207 RE |
290 | unused on RISCiX). Specifying this flag also enables |
291 | -fno-omit-frame-pointer. | |
35d965d5 | 292 | XXX Must still be implemented in the prologue. */ |
6cfc7210 | 293 | #define ARM_FLAG_POKE (1 << 1) |
35d965d5 RS |
294 | |
295 | /* Nonzero if floating point instructions are emulated by the FPE, in which | |
296 | case instruction scheduling becomes very uninteresting. */ | |
6cfc7210 | 297 | #define ARM_FLAG_FPE (1 << 2) |
35d965d5 | 298 | |
11c1a207 RE |
299 | /* Nonzero if destined for a processor in 32-bit program mode. Takes out bit |
300 | that assume restoration of the condition flags when returning from a | |
301 | branch and link (ie a function). */ | |
6cfc7210 | 302 | #define ARM_FLAG_APCS_32 (1 << 3) |
11c1a207 | 303 | |
dfa08768 RE |
304 | /* FLAGS 0x0008 and 0x0010 are now spare (used to be arm3/6 selection). */ |
305 | ||
11c1a207 RE |
306 | /* Nonzero if stack checking should be performed on entry to each function |
307 | which allocates temporary variables on the stack. */ | |
6cfc7210 | 308 | #define ARM_FLAG_APCS_STACK (1 << 4) |
11c1a207 RE |
309 | |
310 | /* Nonzero if floating point parameters should be passed to functions in | |
311 | floating point registers. */ | |
6cfc7210 | 312 | #define ARM_FLAG_APCS_FLOAT (1 << 5) |
11c1a207 RE |
313 | |
314 | /* Nonzero if re-entrant, position independent code should be generated. | |
315 | This is equivalent to -fpic. */ | |
6cfc7210 | 316 | #define ARM_FLAG_APCS_REENT (1 << 6) |
11c1a207 | 317 | |
5f1e6755 NC |
318 | /* Nonzero if the MMU will trap unaligned word accesses, so shorts must |
319 | be loaded using either LDRH or LDRB instructions. */ | |
320 | #define ARM_FLAG_MMU_TRAPS (1 << 7) | |
11c1a207 RE |
321 | |
322 | /* Nonzero if all floating point instructions are missing (and there is no | |
323 | emulator either). Generate function calls for all ops in this case. */ | |
6cfc7210 | 324 | #define ARM_FLAG_SOFT_FLOAT (1 << 8) |
11c1a207 RE |
325 | |
326 | /* Nonzero if we should compile with BYTES_BIG_ENDIAN set to 1. */ | |
6cfc7210 | 327 | #define ARM_FLAG_BIG_END (1 << 9) |
11c1a207 RE |
328 | |
329 | /* Nonzero if we should compile for Thumb interworking. */ | |
6cfc7210 | 330 | #define ARM_FLAG_INTERWORK (1 << 10) |
11c1a207 | 331 | |
ddee6aba RE |
332 | /* Nonzero if we should have little-endian words even when compiling for |
333 | big-endian (for backwards compatibility with older versions of GCC). */ | |
6cfc7210 | 334 | #define ARM_FLAG_LITTLE_WORDS (1 << 11) |
ddee6aba | 335 | |
f5a1b0d2 | 336 | /* Nonzero if we need to protect the prolog from scheduling */ |
6cfc7210 | 337 | #define ARM_FLAG_NO_SCHED_PRO (1 << 12) |
f5a1b0d2 | 338 | |
c11145f6 | 339 | /* Nonzero if a call to abort should be generated if a noreturn |
dd18ae56 | 340 | function tries to return. */ |
6cfc7210 | 341 | #define ARM_FLAG_ABORT_NORETURN (1 << 13) |
c11145f6 | 342 | |
ed0e6530 | 343 | /* Nonzero if function prologues should not load the PIC register. */ |
dd18ae56 | 344 | #define ARM_FLAG_SINGLE_PIC_BASE (1 << 14) |
ed0e6530 | 345 | |
b020fd92 NC |
346 | /* Nonzero if all call instructions should be indirect. */ |
347 | #define ARM_FLAG_LONG_CALLS (1 << 15) | |
d5b7b3ae RE |
348 | |
349 | /* Nonzero means that the target ISA is the THUMB, not the ARM. */ | |
350 | #define ARM_FLAG_THUMB (1 << 16) | |
351 | ||
352 | /* Set if a TPCS style stack frame should be generated, for non-leaf | |
353 | functions, even if they do not need one. */ | |
354 | #define THUMB_FLAG_BACKTRACE (1 << 17) | |
b020fd92 | 355 | |
d5b7b3ae RE |
356 | /* Set if a TPCS style stack frame should be generated, for leaf |
357 | functions, even if they do not need one. */ | |
358 | #define THUMB_FLAG_LEAF_BACKTRACE (1 << 18) | |
359 | ||
360 | /* Set if externally visible functions should assume that they | |
361 | might be called in ARM mode, from a non-thumb aware code. */ | |
362 | #define THUMB_FLAG_CALLEE_SUPER_INTERWORKING (1 << 19) | |
363 | ||
364 | /* Set if calls via function pointers should assume that their | |
365 | destination is non-Thumb aware. */ | |
366 | #define THUMB_FLAG_CALLER_SUPER_INTERWORKING (1 << 20) | |
367 | ||
368 | #define TARGET_APCS_FRAME (target_flags & ARM_FLAG_APCS_FRAME) | |
11c1a207 RE |
369 | #define TARGET_POKE_FUNCTION_NAME (target_flags & ARM_FLAG_POKE) |
370 | #define TARGET_FPE (target_flags & ARM_FLAG_FPE) | |
11c1a207 RE |
371 | #define TARGET_APCS_32 (target_flags & ARM_FLAG_APCS_32) |
372 | #define TARGET_APCS_STACK (target_flags & ARM_FLAG_APCS_STACK) | |
373 | #define TARGET_APCS_FLOAT (target_flags & ARM_FLAG_APCS_FLOAT) | |
374 | #define TARGET_APCS_REENT (target_flags & ARM_FLAG_APCS_REENT) | |
5f1e6755 | 375 | #define TARGET_MMU_TRAPS (target_flags & ARM_FLAG_MMU_TRAPS) |
11c1a207 RE |
376 | #define TARGET_SOFT_FLOAT (target_flags & ARM_FLAG_SOFT_FLOAT) |
377 | #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT) | |
378 | #define TARGET_BIG_END (target_flags & ARM_FLAG_BIG_END) | |
6cfc7210 | 379 | #define TARGET_INTERWORK (target_flags & ARM_FLAG_INTERWORK) |
ddee6aba | 380 | #define TARGET_LITTLE_WORDS (target_flags & ARM_FLAG_LITTLE_WORDS) |
f5a1b0d2 | 381 | #define TARGET_NO_SCHED_PRO (target_flags & ARM_FLAG_NO_SCHED_PRO) |
dd18ae56 | 382 | #define TARGET_ABORT_NORETURN (target_flags & ARM_FLAG_ABORT_NORETURN) |
ed0e6530 | 383 | #define TARGET_SINGLE_PIC_BASE (target_flags & ARM_FLAG_SINGLE_PIC_BASE) |
b020fd92 | 384 | #define TARGET_LONG_CALLS (target_flags & ARM_FLAG_LONG_CALLS) |
d5b7b3ae RE |
385 | #define TARGET_THUMB (target_flags & ARM_FLAG_THUMB) |
386 | #define TARGET_ARM (! TARGET_THUMB) | |
387 | #define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */ | |
388 | #define TARGET_CALLEE_INTERWORKING (target_flags & THUMB_FLAG_CALLEE_SUPER_INTERWORKING) | |
389 | #define TARGET_CALLER_INTERWORKING (target_flags & THUMB_FLAG_CALLER_SUPER_INTERWORKING) | |
390 | #define TARGET_BACKTRACE (leaf_function_p () \ | |
391 | ? (target_flags & THUMB_FLAG_LEAF_BACKTRACE) \ | |
392 | : (target_flags & THUMB_FLAG_BACKTRACE)) | |
3ada8e17 | 393 | |
c7bdf0a6 | 394 | /* SUBTARGET_SWITCHES is used to add flags on a per-config basis. */ |
3ada8e17 DE |
395 | #ifndef SUBTARGET_SWITCHES |
396 | #define SUBTARGET_SWITCHES | |
ff9940b0 RE |
397 | #endif |
398 | ||
047142d3 PT |
399 | #define TARGET_SWITCHES \ |
400 | { \ | |
401 | {"apcs", ARM_FLAG_APCS_FRAME, "" }, \ | |
402 | {"apcs-frame", ARM_FLAG_APCS_FRAME, \ | |
403 | N_("Generate APCS conformant stack frames") }, \ | |
404 | {"no-apcs-frame", -ARM_FLAG_APCS_FRAME, "" }, \ | |
405 | {"poke-function-name", ARM_FLAG_POKE, \ | |
406 | N_("Store function names in object code") }, \ | |
407 | {"no-poke-function-name", -ARM_FLAG_POKE, "" }, \ | |
408 | {"fpe", ARM_FLAG_FPE, "" }, \ | |
409 | {"apcs-32", ARM_FLAG_APCS_32, \ | |
b605cfa8 | 410 | N_("Use the 32-bit version of the APCS") }, \ |
047142d3 | 411 | {"apcs-26", -ARM_FLAG_APCS_32, \ |
b605cfa8 | 412 | N_("Use the 26-bit version of the APCS") }, \ |
047142d3 PT |
413 | {"apcs-stack-check", ARM_FLAG_APCS_STACK, "" }, \ |
414 | {"no-apcs-stack-check", -ARM_FLAG_APCS_STACK, "" }, \ | |
415 | {"apcs-float", ARM_FLAG_APCS_FLOAT, \ | |
416 | N_("Pass FP arguments in FP registers") }, \ | |
417 | {"no-apcs-float", -ARM_FLAG_APCS_FLOAT, "" }, \ | |
418 | {"apcs-reentrant", ARM_FLAG_APCS_REENT, \ | |
419 | N_("Generate re-entrant, PIC code") }, \ | |
420 | {"no-apcs-reentrant", -ARM_FLAG_APCS_REENT, "" }, \ | |
421 | {"alignment-traps", ARM_FLAG_MMU_TRAPS, \ | |
422 | N_("The MMU will trap on unaligned accesses") }, \ | |
423 | {"no-alignment-traps", -ARM_FLAG_MMU_TRAPS, "" }, \ | |
424 | {"short-load-bytes", ARM_FLAG_MMU_TRAPS, "" }, \ | |
425 | {"no-short-load-bytes", -ARM_FLAG_MMU_TRAPS, "" }, \ | |
426 | {"short-load-words", -ARM_FLAG_MMU_TRAPS, "" }, \ | |
427 | {"no-short-load-words", ARM_FLAG_MMU_TRAPS, "" }, \ | |
428 | {"soft-float", ARM_FLAG_SOFT_FLOAT, \ | |
429 | N_("Use library calls to perform FP operations") }, \ | |
430 | {"hard-float", -ARM_FLAG_SOFT_FLOAT, \ | |
431 | N_("Use hardware floating point instructions") }, \ | |
432 | {"big-endian", ARM_FLAG_BIG_END, \ | |
433 | N_("Assume target CPU is configured as big endian") }, \ | |
434 | {"little-endian", -ARM_FLAG_BIG_END, \ | |
435 | N_("Assume target CPU is configured as little endian") }, \ | |
436 | {"words-little-endian", ARM_FLAG_LITTLE_WORDS, \ | |
437 | N_("Assume big endian bytes, little endian words") }, \ | |
438 | {"thumb-interwork", ARM_FLAG_INTERWORK, \ | |
b605cfa8 | 439 | N_("Support calls between Thumb and ARM instruction sets") }, \ |
047142d3 PT |
440 | {"no-thumb-interwork", -ARM_FLAG_INTERWORK, "" }, \ |
441 | {"abort-on-noreturn", ARM_FLAG_ABORT_NORETURN, \ | |
442 | N_("Generate a call to abort if a noreturn function returns")}, \ | |
443 | {"no-abort-on-noreturn", -ARM_FLAG_ABORT_NORETURN, "" }, \ | |
b605cfa8 | 444 | {"no-sched-prolog", ARM_FLAG_NO_SCHED_PRO, \ |
047142d3 | 445 | N_("Do not move instructions into a function's prologue") }, \ |
b605cfa8 | 446 | {"sched-prolog", -ARM_FLAG_NO_SCHED_PRO, "" }, \ |
047142d3 PT |
447 | {"single-pic-base", ARM_FLAG_SINGLE_PIC_BASE, \ |
448 | N_("Do not load the PIC register in function prologues") }, \ | |
449 | {"no-single-pic-base", -ARM_FLAG_SINGLE_PIC_BASE, "" }, \ | |
450 | {"long-calls", ARM_FLAG_LONG_CALLS, \ | |
451 | N_("Generate call insns as indirect calls, if necessary") }, \ | |
452 | {"no-long-calls", -ARM_FLAG_LONG_CALLS, "" }, \ | |
453 | {"thumb", ARM_FLAG_THUMB, \ | |
454 | N_("Compile for the Thumb not the ARM") }, \ | |
455 | {"no-thumb", -ARM_FLAG_THUMB, "" }, \ | |
456 | {"arm", -ARM_FLAG_THUMB, "" }, \ | |
457 | {"tpcs-frame", THUMB_FLAG_BACKTRACE, \ | |
458 | N_("Thumb: Generate (non-leaf) stack frames even if not needed") }, \ | |
459 | {"no-tpcs-frame", -THUMB_FLAG_BACKTRACE, "" }, \ | |
460 | {"tpcs-leaf-frame", THUMB_FLAG_LEAF_BACKTRACE, \ | |
461 | N_("Thumb: Generate (leaf) stack frames even if not needed") }, \ | |
462 | {"no-tpcs-leaf-frame", -THUMB_FLAG_LEAF_BACKTRACE, "" }, \ | |
463 | {"callee-super-interworking", THUMB_FLAG_CALLEE_SUPER_INTERWORKING, \ | |
464 | N_("Thumb: Assume non-static functions may be called from ARM code") }, \ | |
465 | {"no-callee-super-interworking", -THUMB_FLAG_CALLEE_SUPER_INTERWORKING, \ | |
466 | "" }, \ | |
467 | {"caller-super-interworking", THUMB_FLAG_CALLER_SUPER_INTERWORKING, \ | |
468 | N_("Thumb: Assume function pointers may go to non-Thumb aware code") }, \ | |
469 | {"no-caller-super-interworking", -THUMB_FLAG_CALLER_SUPER_INTERWORKING, \ | |
470 | "" }, \ | |
471 | SUBTARGET_SWITCHES \ | |
472 | {"", TARGET_DEFAULT, "" } \ | |
35d965d5 RS |
473 | } |
474 | ||
43cffd11 RE |
475 | #define TARGET_OPTIONS \ |
476 | { \ | |
f5a1b0d2 | 477 | {"cpu=", & arm_select[0].string, \ |
047142d3 | 478 | N_("Specify the name of the target CPU") }, \ |
f5a1b0d2 | 479 | {"arch=", & arm_select[1].string, \ |
047142d3 | 480 | N_("Specify the name of the target architecture") }, \ |
f5a1b0d2 NC |
481 | {"tune=", & arm_select[2].string, "" }, \ |
482 | {"fpe=", & target_fp_name, "" }, \ | |
483 | {"fp=", & target_fp_name, \ | |
047142d3 PT |
484 | N_("Specify the version of the floating point emulator") }, \ |
485 | {"structure-size-boundary=", & structure_size_string, \ | |
486 | N_("Specify the minimum bit alignment of structures") }, \ | |
487 | {"pic-register=", & arm_pic_register_string, \ | |
488 | N_("Specify the register to be used for PIC addressing") } \ | |
11c1a207 | 489 | } |
ff9940b0 | 490 | |
62dd06ea RE |
491 | struct arm_cpu_select |
492 | { | |
f9cc092a RE |
493 | const char * string; |
494 | const char * name; | |
495 | const struct processors * processors; | |
62dd06ea RE |
496 | }; |
497 | ||
f5a1b0d2 NC |
498 | /* This is a magic array. If the user specifies a command line switch |
499 | which matches one of the entries in TARGET_OPTIONS then the corresponding | |
500 | string pointer will be set to the value specified by the user. */ | |
62dd06ea RE |
501 | extern struct arm_cpu_select arm_select[]; |
502 | ||
11c1a207 RE |
503 | enum prog_mode_type |
504 | { | |
505 | prog_mode26, | |
506 | prog_mode32 | |
507 | }; | |
508 | ||
509 | /* Recast the program mode class to be the prog_mode attribute */ | |
510 | #define arm_prog_mode ((enum attr_prog_mode) arm_prgmode) | |
511 | ||
512 | extern enum prog_mode_type arm_prgmode; | |
513 | ||
514 | /* What sort of floating point unit do we have? Hardware or software. | |
515 | If software, is it issue 2 or issue 3? */ | |
24f0c1b4 RE |
516 | enum floating_point_type |
517 | { | |
518 | FP_HARD, | |
11c1a207 RE |
519 | FP_SOFT2, |
520 | FP_SOFT3 | |
24f0c1b4 RE |
521 | }; |
522 | ||
523 | /* Recast the floating point class to be the floating point attribute. */ | |
524 | #define arm_fpu_attr ((enum attr_fpu) arm_fpu) | |
525 | ||
71791e16 | 526 | /* What type of floating point to tune for */ |
24f0c1b4 RE |
527 | extern enum floating_point_type arm_fpu; |
528 | ||
71791e16 RE |
529 | /* What type of floating point instructions are available */ |
530 | extern enum floating_point_type arm_fpu_arch; | |
531 | ||
18543a22 | 532 | /* Default floating point architecture. Override in sub-target if |
71791e16 | 533 | necessary. */ |
be393ecf | 534 | #ifndef FP_DEFAULT |
71791e16 | 535 | #define FP_DEFAULT FP_SOFT2 |
be393ecf | 536 | #endif |
71791e16 | 537 | |
11c1a207 RE |
538 | /* Nonzero if the processor has a fast multiply insn, and one that does |
539 | a 64-bit multiply of two 32-bit values. */ | |
540 | extern int arm_fast_multiply; | |
541 | ||
71791e16 | 542 | /* Nonzero if this chip supports the ARM Architecture 4 extensions */ |
11c1a207 RE |
543 | extern int arm_arch4; |
544 | ||
62b10bbc NC |
545 | /* Nonzero if this chip supports the ARM Architecture 5 extensions */ |
546 | extern int arm_arch5; | |
547 | ||
b15bca31 RE |
548 | /* Nonzero if this chip supports the ARM Architecture 5E extensions */ |
549 | extern int arm_arch5e; | |
550 | ||
f5a1b0d2 NC |
551 | /* Nonzero if this chip can benefit from load scheduling. */ |
552 | extern int arm_ld_sched; | |
553 | ||
0616531f RE |
554 | /* Nonzero if generating thumb code. */ |
555 | extern int thumb_code; | |
556 | ||
f5a1b0d2 NC |
557 | /* Nonzero if this chip is a StrongARM. */ |
558 | extern int arm_is_strong; | |
559 | ||
d19fb8e3 NC |
560 | /* Nonzero if this chip is an XScale. */ |
561 | extern int arm_is_xscale; | |
562 | ||
3569057d | 563 | /* Nonzero if this chip is an ARM6 or an ARM7. */ |
f5a1b0d2 NC |
564 | extern int arm_is_6_or_7; |
565 | ||
2ce9c1b9 | 566 | #ifndef TARGET_DEFAULT |
d5b7b3ae | 567 | #define TARGET_DEFAULT (ARM_FLAG_APCS_FRAME) |
2ce9c1b9 | 568 | #endif |
35d965d5 | 569 | |
11c1a207 RE |
570 | /* The frame pointer register used in gcc has nothing to do with debugging; |
571 | that is controlled by the APCS-FRAME option. */ | |
d5b7b3ae | 572 | #define CAN_DEBUG_WITHOUT_FP |
35d965d5 | 573 | |
be393ecf | 574 | #undef TARGET_MEM_FUNCTIONS |
11c1a207 RE |
575 | #define TARGET_MEM_FUNCTIONS 1 |
576 | ||
577 | #define OVERRIDE_OPTIONS arm_override_options () | |
86efdc8e PB |
578 | |
579 | /* Nonzero if PIC code requires explicit qualifiers to generate | |
580 | PLT and GOT relocs rather than the assembler doing so implicitly. | |
ed0e6530 PB |
581 | Subtargets can override these if required. */ |
582 | #ifndef NEED_GOT_RELOC | |
583 | #define NEED_GOT_RELOC 0 | |
584 | #endif | |
585 | #ifndef NEED_PLT_RELOC | |
586 | #define NEED_PLT_RELOC 0 | |
e2723c62 | 587 | #endif |
84306176 PB |
588 | |
589 | /* Nonzero if we need to refer to the GOT with a PC-relative | |
590 | offset. In other words, generate | |
591 | ||
592 | .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)] | |
593 | ||
594 | rather than | |
595 | ||
596 | .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8) | |
597 | ||
598 | The default is true, which matches NetBSD. Subtargets can | |
599 | override this if required. */ | |
600 | #ifndef GOT_PCREL | |
601 | #define GOT_PCREL 1 | |
602 | #endif | |
35d965d5 RS |
603 | \f |
604 | /* Target machine storage Layout. */ | |
605 | ||
ff9940b0 RE |
606 | |
607 | /* Define this macro if it is advisable to hold scalars in registers | |
608 | in a wider mode than that declared by the program. In such cases, | |
609 | the value is constrained to be within the bounds of the declared | |
610 | type, but kept valid in the wider mode. The signedness of the | |
611 | extension may differ from that of the type. */ | |
612 | ||
613 | /* It is far faster to zero extend chars than to sign extend them */ | |
614 | ||
6cfc7210 | 615 | #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ |
2ce9c1b9 RE |
616 | if (GET_MODE_CLASS (MODE) == MODE_INT \ |
617 | && GET_MODE_SIZE (MODE) < 4) \ | |
618 | { \ | |
619 | if (MODE == QImode) \ | |
620 | UNSIGNEDP = 1; \ | |
621 | else if (MODE == HImode) \ | |
5f1e6755 | 622 | UNSIGNEDP = TARGET_MMU_TRAPS != 0; \ |
2ce9c1b9 | 623 | (MODE) = SImode; \ |
ff9940b0 RE |
624 | } |
625 | ||
18543a22 ILT |
626 | /* Define this macro if the promotion described by `PROMOTE_MODE' |
627 | should also be done for outgoing function arguments. */ | |
628 | /* This is required to ensure that push insns always push a word. */ | |
629 | #define PROMOTE_FUNCTION_ARGS | |
630 | ||
ff9940b0 RE |
631 | /* For the ARM: |
632 | I think I have added all the code to make this work. Unfortunately, | |
633 | early releases of the floating point emulation code on RISCiX used a | |
634 | different format for extended precision numbers. On my RISCiX box there | |
635 | is a bug somewhere which causes the machine to lock up when running enquire | |
636 | with long doubles. There is the additional aspect that Norcroft C | |
637 | treats long doubles as doubles and we ought to remain compatible. | |
638 | Perhaps someone with an FPA coprocessor and not running RISCiX would like | |
639 | to try this someday. */ | |
640 | /* #define LONG_DOUBLE_TYPE_SIZE 96 */ | |
641 | ||
642 | /* Disable XFmode patterns in md file */ | |
643 | #define ENABLE_XF_PATTERNS 0 | |
644 | ||
35d965d5 RS |
645 | /* Define this if most significant bit is lowest numbered |
646 | in instructions that operate on numbered bit-fields. */ | |
647 | #define BITS_BIG_ENDIAN 0 | |
648 | ||
9c872872 | 649 | /* Define this if most significant byte of a word is the lowest numbered. |
3ada8e17 DE |
650 | Most ARM processors are run in little endian mode, so that is the default. |
651 | If you want to have it run-time selectable, change the definition in a | |
652 | cover file to be TARGET_BIG_ENDIAN. */ | |
11c1a207 | 653 | #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0) |
35d965d5 RS |
654 | |
655 | /* Define this if most significant word of a multiword number is the lowest | |
11c1a207 RE |
656 | numbered. |
657 | This is always false, even when in big-endian mode. */ | |
ddee6aba RE |
658 | #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS) |
659 | ||
660 | /* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based | |
661 | on processor pre-defineds when compiling libgcc2.c. */ | |
662 | #if defined(__ARMEB__) && !defined(__ARMWEL__) | |
663 | #define LIBGCC2_WORDS_BIG_ENDIAN 1 | |
664 | #else | |
665 | #define LIBGCC2_WORDS_BIG_ENDIAN 0 | |
666 | #endif | |
35d965d5 | 667 | |
11c1a207 RE |
668 | /* Define this if most significant word of doubles is the lowest numbered. |
669 | This is always true, even when in little-endian mode. */ | |
7fc6c9f0 RK |
670 | #define FLOAT_WORDS_BIG_ENDIAN 1 |
671 | ||
35d965d5 RS |
672 | #define UNITS_PER_WORD 4 |
673 | ||
35d965d5 RS |
674 | #define PARM_BOUNDARY 32 |
675 | ||
676 | #define STACK_BOUNDARY 32 | |
677 | ||
678 | #define FUNCTION_BOUNDARY 32 | |
679 | ||
92928d71 AO |
680 | /* The lowest bit is used to indicate Thumb-mode functions, so the |
681 | vbit must go into the delta field of pointers to member | |
682 | functions. */ | |
683 | #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta | |
684 | ||
35d965d5 RS |
685 | #define EMPTY_FIELD_BOUNDARY 32 |
686 | ||
687 | #define BIGGEST_ALIGNMENT 32 | |
688 | ||
ff9940b0 | 689 | /* Make strings word-aligned so strcpy from constants will be faster. */ |
d19fb8e3 NC |
690 | #define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_is_xscale ? 1 : 2) |
691 | ||
692 | #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ | |
693 | ((TREE_CODE (EXP) == STRING_CST \ | |
694 | && (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \ | |
695 | ? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN)) | |
ff9940b0 | 696 | |
723ae7c1 NC |
697 | /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the |
698 | value set in previous versions of this toolchain was 8, which produces more | |
699 | compact structures. The command line option -mstructure_size_boundary=<n> | |
f710504c | 700 | can be used to change this value. For compatibility with the ARM SDK |
723ae7c1 NC |
701 | however the value should be left at 32. ARM SDT Reference Manual (ARM DUI |
702 | 0020D) page 2-20 says "Structures are aligned on word boundaries". */ | |
6ead9ba5 NC |
703 | #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary |
704 | extern int arm_structure_size_boundary; | |
723ae7c1 NC |
705 | |
706 | /* This is the value used to initialise arm_structure_size_boundary. If a | |
707 | particular arm target wants to change the default value it should change | |
708 | the definition of this macro, not STRUCTRUE_SIZE_BOUNDARY. See netbsd.h | |
709 | for an example of this. */ | |
710 | #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY | |
711 | #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32 | |
b355a481 | 712 | #endif |
2a5307b1 | 713 | |
b355a481 | 714 | /* Used when parsing command line option -mstructure_size_boundary. */ |
f9cc092a | 715 | extern const char * structure_size_string; |
b4ac57ab | 716 | |
ff9940b0 RE |
717 | /* Non-zero if move instructions will actually fail to work |
718 | when given unaligned data. */ | |
35d965d5 RS |
719 | #define STRICT_ALIGNMENT 1 |
720 | ||
ff9940b0 RE |
721 | #define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT |
722 | ||
35d965d5 RS |
723 | \f |
724 | /* Standard register usage. */ | |
725 | ||
726 | /* Register allocation in ARM Procedure Call Standard (as used on RISCiX): | |
727 | (S - saved over call). | |
728 | ||
729 | r0 * argument word/integer result | |
730 | r1-r3 argument word | |
731 | ||
732 | r4-r8 S register variable | |
733 | r9 S (rfp) register variable (real frame pointer) | |
f5a1b0d2 NC |
734 | |
735 | r10 F S (sl) stack limit (used by -mapcs-stack-check) | |
35d965d5 RS |
736 | r11 F S (fp) argument pointer |
737 | r12 (ip) temp workspace | |
738 | r13 F S (sp) lower end of current stack frame | |
739 | r14 (lr) link address/workspace | |
740 | r15 F (pc) program counter | |
741 | ||
742 | f0 floating point result | |
743 | f1-f3 floating point scratch | |
744 | ||
745 | f4-f7 S floating point variable | |
746 | ||
ff9940b0 RE |
747 | cc This is NOT a real register, but is used internally |
748 | to represent things that use or set the condition | |
749 | codes. | |
750 | sfp This isn't either. It is used during rtl generation | |
751 | since the offset between the frame pointer and the | |
752 | auto's isn't known until after register allocation. | |
753 | afp Nor this, we only need this because of non-local | |
754 | goto. Without it fp appears to be used and the | |
755 | elimination code won't get rid of sfp. It tracks | |
756 | fp exactly at all times. | |
757 | ||
35d965d5 RS |
758 | *: See CONDITIONAL_REGISTER_USAGE */ |
759 | ||
ff9940b0 RE |
760 | /* The stack backtrace structure is as follows: |
761 | fp points to here: | save code pointer | [fp] | |
762 | | return link value | [fp, #-4] | |
763 | | return sp value | [fp, #-8] | |
764 | | return fp value | [fp, #-12] | |
765 | [| saved r10 value |] | |
766 | [| saved r9 value |] | |
767 | [| saved r8 value |] | |
768 | [| saved r7 value |] | |
769 | [| saved r6 value |] | |
770 | [| saved r5 value |] | |
771 | [| saved r4 value |] | |
772 | [| saved r3 value |] | |
773 | [| saved r2 value |] | |
774 | [| saved r1 value |] | |
775 | [| saved r0 value |] | |
776 | [| saved f7 value |] three words | |
777 | [| saved f6 value |] three words | |
778 | [| saved f5 value |] three words | |
779 | [| saved f4 value |] three words | |
780 | r0-r3 are not normally saved in a C function. */ | |
781 | ||
35d965d5 RS |
782 | /* 1 for registers that have pervasive standard uses |
783 | and are not available for the register allocator. */ | |
784 | #define FIXED_REGISTERS \ | |
785 | { \ | |
786 | 0,0,0,0,0,0,0,0, \ | |
d5b7b3ae | 787 | 0,0,0,0,0,1,0,1, \ |
ff9940b0 RE |
788 | 0,0,0,0,0,0,0,0, \ |
789 | 1,1,1 \ | |
35d965d5 RS |
790 | } |
791 | ||
792 | /* 1 for registers not available across function calls. | |
793 | These must include the FIXED_REGISTERS and also any | |
794 | registers that can be used without being saved. | |
795 | The latter must include the registers where values are returned | |
796 | and the register where structure-value addresses are passed. | |
ff9940b0 RE |
797 | Aside from that, you can include as many other registers as you like. |
798 | The CC is not preserved over function calls on the ARM 6, so it is | |
799 | easier to assume this for all. SFP is preserved, since FP is. */ | |
35d965d5 RS |
800 | #define CALL_USED_REGISTERS \ |
801 | { \ | |
802 | 1,1,1,1,0,0,0,0, \ | |
d5b7b3ae | 803 | 0,0,0,0,1,1,1,1, \ |
ff9940b0 RE |
804 | 1,1,1,1,0,0,0,0, \ |
805 | 1,1,1 \ | |
35d965d5 RS |
806 | } |
807 | ||
6cc8c0b3 NC |
808 | #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE |
809 | #define SUBTARGET_CONDITIONAL_REGISTER_USAGE | |
810 | #endif | |
811 | ||
d5b7b3ae RE |
812 | #define CONDITIONAL_REGISTER_USAGE \ |
813 | { \ | |
4b02997f NC |
814 | int regno; \ |
815 | \ | |
d5b7b3ae RE |
816 | if (TARGET_SOFT_FLOAT || TARGET_THUMB) \ |
817 | { \ | |
d5b7b3ae RE |
818 | for (regno = FIRST_ARM_FP_REGNUM; \ |
819 | regno <= LAST_ARM_FP_REGNUM; ++regno) \ | |
820 | fixed_regs[regno] = call_used_regs[regno] = 1; \ | |
821 | } \ | |
5b43fed1 | 822 | if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \ |
d5b7b3ae RE |
823 | { \ |
824 | fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ | |
825 | call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ | |
826 | } \ | |
827 | else if (TARGET_APCS_STACK) \ | |
828 | { \ | |
829 | fixed_regs[10] = 1; \ | |
830 | call_used_regs[10] = 1; \ | |
831 | } \ | |
832 | if (TARGET_APCS_FRAME) \ | |
833 | { \ | |
834 | fixed_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \ | |
835 | call_used_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \ | |
836 | } \ | |
837 | SUBTARGET_CONDITIONAL_REGISTER_USAGE \ | |
35d965d5 | 838 | } |
d5b7b3ae | 839 | |
dd18ae56 NC |
840 | /* These are a couple of extensions to the formats accecpted |
841 | by asm_fprintf: | |
842 | %@ prints out ASM_COMMENT_START | |
843 | %r prints out REGISTER_PREFIX reg_names[arg] */ | |
844 | #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \ | |
845 | case '@': \ | |
846 | fputs (ASM_COMMENT_START, FILE); \ | |
847 | break; \ | |
848 | \ | |
849 | case 'r': \ | |
850 | fputs (REGISTER_PREFIX, FILE); \ | |
851 | fputs (reg_names [va_arg (ARGS, int)], FILE); \ | |
852 | break; | |
853 | ||
d5b7b3ae RE |
854 | /* Round X up to the nearest word. */ |
855 | #define ROUND_UP(X) (((X) + 3) & ~3) | |
856 | ||
6cfc7210 NC |
857 | /* Convert fron bytes to ints. */ |
858 | #define NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) | |
859 | ||
860 | /* The number of (integer) registers required to hold a quantity of type MODE. */ | |
861 | #define NUM_REGS(MODE) \ | |
862 | NUM_INTS (GET_MODE_SIZE (MODE)) | |
863 | ||
864 | /* The number of (integer) registers required to hold a quantity of TYPE MODE. */ | |
865 | #define NUM_REGS2(MODE, TYPE) \ | |
d5b7b3ae RE |
866 | NUM_INTS ((MODE) == BLKmode ? \ |
867 | int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE)) | |
6cfc7210 NC |
868 | |
869 | /* The number of (integer) argument register available. */ | |
d5b7b3ae | 870 | #define NUM_ARG_REGS 4 |
6cfc7210 NC |
871 | |
872 | /* Return the regiser number of the N'th (integer) argument. */ | |
d5b7b3ae | 873 | #define ARG_REGISTER(N) (N - 1) |
6cfc7210 | 874 | |
e04546dc NC |
875 | #if 0 /* FIXME: The ARM backend has special code to handle structure |
876 | returns, and will reserve its own hidden first argument. So | |
877 | if this macro is enabled a *second* hidden argument will be | |
d6a7951f | 878 | reserved, which will break binary compatibility with old |
e04546dc NC |
879 | toolchains and also thunk handling. One day this should be |
880 | fixed. */ | |
64a7723d | 881 | /* RTX for structure returns. NULL means use a hidden first argument. */ |
31448271 | 882 | #define STRUCT_VALUE 0 |
e04546dc NC |
883 | #else |
884 | /* Register in which address to store a structure value | |
885 | is passed to a function. */ | |
886 | #define STRUCT_VALUE_REGNUM ARG_REGISTER (1) | |
887 | #endif | |
6cfc7210 | 888 | |
d5b7b3ae RE |
889 | /* Specify the registers used for certain standard purposes. |
890 | The values of these macros are register numbers. */ | |
35d965d5 | 891 | |
d5b7b3ae RE |
892 | /* The number of the last argument register. */ |
893 | #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS) | |
35d965d5 | 894 | |
d5b7b3ae | 895 | /* The number of the last "lo" register (thumb). */ |
6d3d9133 NC |
896 | #define LAST_LO_REGNUM 7 |
897 | ||
898 | /* The register that holds the return address in exception handlers. */ | |
899 | #define EXCEPTION_LR_REGNUM 2 | |
35d965d5 | 900 | |
d5b7b3ae RE |
901 | /* The native (Norcroft) Pascal compiler for the ARM passes the static chain |
902 | as an invisible last argument (possible since varargs don't exist in | |
903 | Pascal), so the following is not true. */ | |
68dfd979 | 904 | #define STATIC_CHAIN_REGNUM (TARGET_ARM ? 12 : 9) |
35d965d5 | 905 | |
d5b7b3ae RE |
906 | /* Define this to be where the real frame pointer is if it is not possible to |
907 | work out the offset between the frame pointer and the automatic variables | |
908 | until after register allocation has taken place. FRAME_POINTER_REGNUM | |
909 | should point to a special register that we will make sure is eliminated. | |
910 | ||
911 | For the Thumb we have another problem. The TPCS defines the frame pointer | |
912 | as r11, and GCC belives that it is always possible to use the frame pointer | |
913 | as base register for addressing purposes. (See comments in | |
914 | find_reloads_address()). But - the Thumb does not allow high registers, | |
915 | including r11, to be used as base address registers. Hence our problem. | |
916 | ||
917 | The solution used here, and in the old thumb port is to use r7 instead of | |
918 | r11 as the hard frame pointer and to have special code to generate | |
919 | backtrace structures on the stack (if required to do so via a command line | |
920 | option) using r11. This is the only 'user visable' use of r11 as a frame | |
921 | pointer. */ | |
922 | #define ARM_HARD_FRAME_POINTER_REGNUM 11 | |
923 | #define THUMB_HARD_FRAME_POINTER_REGNUM 7 | |
35d965d5 | 924 | |
b15bca31 RE |
925 | #define HARD_FRAME_POINTER_REGNUM \ |
926 | (TARGET_ARM \ | |
927 | ? ARM_HARD_FRAME_POINTER_REGNUM \ | |
928 | : THUMB_HARD_FRAME_POINTER_REGNUM) | |
d5b7b3ae | 929 | |
b15bca31 | 930 | #define FP_REGNUM HARD_FRAME_POINTER_REGNUM |
d5b7b3ae | 931 | |
b15bca31 RE |
932 | /* Register to use for pushing function arguments. */ |
933 | #define STACK_POINTER_REGNUM SP_REGNUM | |
d5b7b3ae RE |
934 | |
935 | /* ARM floating pointer registers. */ | |
936 | #define FIRST_ARM_FP_REGNUM 16 | |
937 | #define LAST_ARM_FP_REGNUM 23 | |
938 | ||
35d965d5 | 939 | /* Base register for access to local variables of the function. */ |
ff9940b0 RE |
940 | #define FRAME_POINTER_REGNUM 25 |
941 | ||
d5b7b3ae RE |
942 | /* Base register for access to arguments of the function. */ |
943 | #define ARG_POINTER_REGNUM 26 | |
62b10bbc | 944 | |
d5b7b3ae RE |
945 | /* The number of hard registers is 16 ARM + 8 FPU + 1 CC + 1 SFP. */ |
946 | #define FIRST_PSEUDO_REGISTER 27 | |
62b10bbc | 947 | |
35d965d5 RS |
948 | /* Value should be nonzero if functions must have frame pointers. |
949 | Zero means the frame pointer need not be set up (and parms may be accessed | |
ff9940b0 RE |
950 | via the stack pointer) in functions that seem suitable. |
951 | If we have to have a frame pointer we might as well make use of it. | |
952 | APCS says that the frame pointer does not need to be pushed in leaf | |
2a5307b1 | 953 | functions, or simple tail call functions. */ |
7b8b8ade NC |
954 | #define FRAME_POINTER_REQUIRED \ |
955 | (current_function_has_nonlocal_label \ | |
d5b7b3ae | 956 | || (TARGET_ARM && TARGET_APCS_FRAME && ! leaf_function_p ())) |
35d965d5 | 957 | |
d5b7b3ae RE |
958 | /* Return number of consecutive hard regs needed starting at reg REGNO |
959 | to hold something of mode MODE. | |
960 | This is ordinarily the length in words of a value of mode MODE | |
961 | but can be less for certain modes in special long registers. | |
35d965d5 | 962 | |
d5b7b3ae RE |
963 | On the ARM regs are UNITS_PER_WORD bits wide; FPU regs can hold any FP |
964 | mode. */ | |
965 | #define HARD_REGNO_NREGS(REGNO, MODE) \ | |
966 | ((TARGET_ARM \ | |
967 | && REGNO >= FIRST_ARM_FP_REGNUM \ | |
968 | && REGNO != FRAME_POINTER_REGNUM \ | |
969 | && REGNO != ARG_POINTER_REGNUM) \ | |
970 | ? 1 : NUM_REGS (MODE)) | |
35d965d5 | 971 | |
4b02997f | 972 | /* Return true if REGNO is suitable for holding a quantity of type MODE. */ |
d5b7b3ae | 973 | #define HARD_REGNO_MODE_OK(REGNO, MODE) \ |
4b02997f | 974 | arm_hard_regno_mode_ok ((REGNO), (MODE)) |
35d965d5 | 975 | |
d5b7b3ae RE |
976 | /* Value is 1 if it is a good idea to tie two pseudo registers |
977 | when one has mode MODE1 and one has mode MODE2. | |
978 | If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, | |
979 | for any hard reg, then this must be 0 for correct output. */ | |
980 | #define MODES_TIEABLE_P(MODE1, MODE2) \ | |
981 | (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2)) | |
ff9940b0 | 982 | |
35d965d5 | 983 | /* The order in which register should be allocated. It is good to use ip |
ff9940b0 RE |
984 | since no saving is required (though calls clobber it) and it never contains |
985 | function parameters. It is quite good to use lr since other calls may | |
986 | clobber it anyway. Allocate r0 through r3 in reverse order since r3 is | |
987 | least likely to contain a function parameter; in addition results are | |
d5b7b3ae | 988 | returned in r0. */ |
ff73fb53 | 989 | #define REG_ALLOC_ORDER \ |
35d965d5 | 990 | { \ |
ff73fb53 NC |
991 | 3, 2, 1, 0, 12, 14, 4, 5, \ |
992 | 6, 7, 8, 10, 9, 11, 13, 15, \ | |
ff9940b0 | 993 | 16, 17, 18, 19, 20, 21, 22, 23, \ |
ff73fb53 | 994 | 24, 25, 26 \ |
35d965d5 | 995 | } |
9338ffe6 PB |
996 | |
997 | /* Interrupt functions can only use registers that have already been | |
998 | saved by the prologue, even if they would normally be | |
999 | call-clobbered. */ | |
1000 | #define HARD_REGNO_RENAME_OK(SRC, DST) \ | |
1001 | (! IS_INTERRUPT (cfun->machine->func_type) || \ | |
1002 | regs_ever_live[DST]) | |
35d965d5 RS |
1003 | \f |
1004 | /* Register and constant classes. */ | |
1005 | ||
d5b7b3ae | 1006 | /* Register classes: used to be simple, just all ARM regs or all FPU regs |
d6a7951f | 1007 | Now that the Thumb is involved it has become more complicated. */ |
35d965d5 RS |
1008 | enum reg_class |
1009 | { | |
1010 | NO_REGS, | |
1011 | FPU_REGS, | |
d5b7b3ae RE |
1012 | LO_REGS, |
1013 | STACK_REG, | |
1014 | BASE_REGS, | |
1015 | HI_REGS, | |
1016 | CC_REG, | |
35d965d5 RS |
1017 | GENERAL_REGS, |
1018 | ALL_REGS, | |
1019 | LIM_REG_CLASSES | |
1020 | }; | |
1021 | ||
1022 | #define N_REG_CLASSES (int) LIM_REG_CLASSES | |
1023 | ||
1024 | /* Give names of register classes as strings for dump file. */ | |
1025 | #define REG_CLASS_NAMES \ | |
1026 | { \ | |
1027 | "NO_REGS", \ | |
1028 | "FPU_REGS", \ | |
d5b7b3ae RE |
1029 | "LO_REGS", \ |
1030 | "STACK_REG", \ | |
1031 | "BASE_REGS", \ | |
1032 | "HI_REGS", \ | |
1033 | "CC_REG", \ | |
35d965d5 RS |
1034 | "GENERAL_REGS", \ |
1035 | "ALL_REGS", \ | |
1036 | } | |
1037 | ||
1038 | /* Define which registers fit in which classes. | |
1039 | This is an initializer for a vector of HARD_REG_SET | |
1040 | of length N_REG_CLASSES. */ | |
aec3cfba NC |
1041 | #define REG_CLASS_CONTENTS \ |
1042 | { \ | |
1043 | { 0x0000000 }, /* NO_REGS */ \ | |
1044 | { 0x0FF0000 }, /* FPU_REGS */ \ | |
d5b7b3ae RE |
1045 | { 0x00000FF }, /* LO_REGS */ \ |
1046 | { 0x0002000 }, /* STACK_REG */ \ | |
1047 | { 0x00020FF }, /* BASE_REGS */ \ | |
1048 | { 0x000FF00 }, /* HI_REGS */ \ | |
1049 | { 0x1000000 }, /* CC_REG */ \ | |
aec3cfba NC |
1050 | { 0x200FFFF }, /* GENERAL_REGS */ \ |
1051 | { 0x2FFFFFF } /* ALL_REGS */ \ | |
35d965d5 | 1052 | } |
4b02997f | 1053 | |
35d965d5 RS |
1054 | /* The same information, inverted: |
1055 | Return the class number of the smallest class containing | |
1056 | reg number REGNO. This could be a conditional expression | |
1057 | or could index an array. */ | |
d5b7b3ae | 1058 | #define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO) |
35d965d5 RS |
1059 | |
1060 | /* The class value for index registers, and the one for base regs. */ | |
d5b7b3ae RE |
1061 | #define INDEX_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS) |
1062 | #define BASE_REG_CLASS (TARGET_THUMB ? BASE_REGS : GENERAL_REGS) | |
1063 | ||
3dcc68a4 NC |
1064 | /* For the Thumb the high registers cannot be used as base |
1065 | registers when addressing quanitities in QI or HI mode. */ | |
1066 | #define MODE_BASE_REG_CLASS(MODE) \ | |
1067 | (TARGET_ARM ? BASE_REGS : \ | |
1068 | (((MODE) == QImode || (MODE) == HImode || (MODE) == VOIDmode) \ | |
1069 | ? LO_REGS : BASE_REGS)) | |
1070 | ||
d5b7b3ae RE |
1071 | /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows |
1072 | registers explicitly used in the rtl to be used as spill registers | |
1073 | but prevents the compiler from extending the lifetime of these | |
1074 | registers. */ | |
1075 | #define SMALL_REGISTER_CLASSES TARGET_THUMB | |
35d965d5 RS |
1076 | |
1077 | /* Get reg_class from a letter such as appears in the machine description. | |
d5b7b3ae RE |
1078 | We only need constraint `f' for FPU_REGS (`r' == GENERAL_REGS) for the |
1079 | ARM, but several more letters for the Thumb. */ | |
1080 | #define REG_CLASS_FROM_LETTER(C) \ | |
1081 | ( (C) == 'f' ? FPU_REGS \ | |
1082 | : (C) == 'l' ? (TARGET_ARM ? GENERAL_REGS : LO_REGS) \ | |
1083 | : TARGET_ARM ? NO_REGS \ | |
1084 | : (C) == 'h' ? HI_REGS \ | |
1085 | : (C) == 'b' ? BASE_REGS \ | |
1086 | : (C) == 'k' ? STACK_REG \ | |
1087 | : (C) == 'c' ? CC_REG \ | |
1088 | : NO_REGS) | |
35d965d5 RS |
1089 | |
1090 | /* The letters I, J, K, L and M in a register constraint string | |
1091 | can be used to stand for particular ranges of immediate operands. | |
1092 | This macro defines what the ranges are. | |
1093 | C is the letter, and VALUE is a constant value. | |
1094 | Return 1 if VALUE is in the range specified by C. | |
b4ac57ab | 1095 | I: immediate arithmetic operand (i.e. 8 bits shifted as required). |
ff9940b0 | 1096 | J: valid indexing constants. |
aef1764c | 1097 | K: ~value ok in rhs argument of data operand. |
3967692c RE |
1098 | L: -value ok in rhs argument of data operand. |
1099 | M: 0..32, or a power of 2 (for shifts, or mult done by shift). */ | |
d5b7b3ae | 1100 | #define CONST_OK_FOR_ARM_LETTER(VALUE, C) \ |
aef1764c RE |
1101 | ((C) == 'I' ? const_ok_for_arm (VALUE) : \ |
1102 | (C) == 'J' ? ((VALUE) < 4096 && (VALUE) > -4096) : \ | |
1103 | (C) == 'K' ? (const_ok_for_arm (~(VALUE))) : \ | |
3967692c RE |
1104 | (C) == 'L' ? (const_ok_for_arm (-(VALUE))) : \ |
1105 | (C) == 'M' ? (((VALUE >= 0 && VALUE <= 32)) \ | |
1106 | || (((VALUE) & ((VALUE) - 1)) == 0)) \ | |
1107 | : 0) | |
ff9940b0 | 1108 | |
d5b7b3ae RE |
1109 | #define CONST_OK_FOR_THUMB_LETTER(VAL, C) \ |
1110 | ((C) == 'I' ? (unsigned HOST_WIDE_INT) (VAL) < 256 : \ | |
1111 | (C) == 'J' ? (VAL) > -256 && (VAL) < 0 : \ | |
1112 | (C) == 'K' ? thumb_shiftable_const (VAL) : \ | |
1113 | (C) == 'L' ? (VAL) > -8 && (VAL) < 8 : \ | |
1114 | (C) == 'M' ? ((unsigned HOST_WIDE_INT) (VAL) < 1024 \ | |
1115 | && ((VAL) & 3) == 0) : \ | |
1116 | (C) == 'N' ? ((unsigned HOST_WIDE_INT) (VAL) < 32) : \ | |
1117 | (C) == 'O' ? ((VAL) >= -508 && (VAL) <= 508) \ | |
1118 | : 0) | |
1119 | ||
1120 | #define CONST_OK_FOR_LETTER_P(VALUE, C) \ | |
1121 | (TARGET_ARM ? \ | |
1122 | CONST_OK_FOR_ARM_LETTER (VALUE, C) : CONST_OK_FOR_THUMB_LETTER (VALUE, C)) | |
1123 | ||
1124 | /* Constant letter 'G' for the FPU immediate constants. | |
1125 | 'H' means the same constant negated. */ | |
1126 | #define CONST_DOUBLE_OK_FOR_ARM_LETTER(X, C) \ | |
1127 | ((C) == 'G' ? const_double_rtx_ok_for_fpu (X) : \ | |
1128 | (C) == 'H' ? neg_const_double_rtx_ok_for_fpu (X) : 0) | |
1129 | ||
1130 | #define CONST_DOUBLE_OK_FOR_LETTER_P(X, C) \ | |
1131 | (TARGET_ARM ? \ | |
1132 | CONST_DOUBLE_OK_FOR_ARM_LETTER (X, C) : 0) | |
1133 | ||
ff9940b0 RE |
1134 | /* For the ARM, `Q' means that this is a memory operand that is just |
1135 | an offset from a register. | |
1136 | `S' means any symbol that has the SYMBOL_REF_FLAG set or a CONSTANT_POOL | |
1137 | address. This means that the symbol is in the text segment and can be | |
1138 | accessed without using a load. */ | |
1139 | ||
d5b7b3ae RE |
1140 | #define EXTRA_CONSTRAINT_ARM(OP, C) \ |
1141 | ((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG : \ | |
1142 | (C) == 'R' ? (GET_CODE (OP) == MEM \ | |
1143 | && GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \ | |
1144 | && CONSTANT_POOL_ADDRESS_P (XEXP (OP, 0))) : \ | |
1145 | (C) == 'S' ? (optimize > 0 && CONSTANT_ADDRESS_P (OP)) \ | |
7a801826 | 1146 | : 0) |
ff9940b0 | 1147 | |
d5b7b3ae RE |
1148 | #define EXTRA_CONSTRAINT_THUMB(X, C) \ |
1149 | ((C) == 'Q' ? (GET_CODE (X) == MEM \ | |
1150 | && GET_CODE (XEXP (X, 0)) == LABEL_REF) : 0) | |
1151 | ||
1152 | #define EXTRA_CONSTRAINT(X, C) \ | |
1153 | (TARGET_ARM ? \ | |
1154 | EXTRA_CONSTRAINT_ARM (X, C) : EXTRA_CONSTRAINT_THUMB (X, C)) | |
35d965d5 RS |
1155 | |
1156 | /* Given an rtx X being reloaded into a reg required to be | |
1157 | in class CLASS, return the class of reg to actually use. | |
d5b7b3ae RE |
1158 | In general this is just CLASS, but for the Thumb we prefer |
1159 | a LO_REGS class or a subset. */ | |
1160 | #define PREFERRED_RELOAD_CLASS(X, CLASS) \ | |
1161 | (TARGET_ARM ? (CLASS) : \ | |
1162 | ((CLASS) == BASE_REGS ? (CLASS) : LO_REGS)) | |
1163 | ||
1164 | /* Must leave BASE_REGS reloads alone */ | |
1165 | #define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \ | |
1166 | ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \ | |
1167 | ? ((true_regnum (X) == -1 ? LO_REGS \ | |
1168 | : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \ | |
1169 | : NO_REGS)) \ | |
1170 | : NO_REGS) | |
1171 | ||
1172 | #define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \ | |
1173 | ((CLASS) != LO_REGS \ | |
1174 | ? ((true_regnum (X) == -1 ? LO_REGS \ | |
1175 | : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \ | |
1176 | : NO_REGS)) \ | |
1177 | : NO_REGS) | |
35d965d5 | 1178 | |
ff9940b0 RE |
1179 | /* Return the register class of a scratch register needed to copy IN into |
1180 | or out of a register in CLASS in MODE. If it can be done directly, | |
1181 | NO_REGS is returned. */ | |
d5b7b3ae RE |
1182 | #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \ |
1183 | (TARGET_ARM ? \ | |
1184 | (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \ | |
1185 | ? GENERAL_REGS : NO_REGS) \ | |
1186 | : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X)) | |
1187 | ||
2ce9c1b9 | 1188 | /* If we need to load shorts byte-at-a-time, then we need a scratch. */ |
d5b7b3ae RE |
1189 | #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \ |
1190 | (TARGET_ARM ? \ | |
1191 | (((MODE) == HImode && ! arm_arch4 && TARGET_MMU_TRAPS \ | |
1192 | && (GET_CODE (X) == MEM \ | |
1193 | || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \ | |
1194 | && true_regnum (X) == -1))) \ | |
1195 | ? GENERAL_REGS : NO_REGS) \ | |
1196 | : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X)) | |
2ce9c1b9 | 1197 | |
6f734908 RE |
1198 | /* Try a machine-dependent way of reloading an illegitimate address |
1199 | operand. If we find one, push the reload and jump to WIN. This | |
1200 | macro is used in only one place: `find_reloads_address' in reload.c. | |
1201 | ||
1202 | For the ARM, we wish to handle large displacements off a base | |
1203 | register by splitting the addend across a MOV and the mem insn. | |
d5b7b3ae RE |
1204 | This can cut the number of reloads needed. */ |
1205 | #define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN) \ | |
1206 | do \ | |
1207 | { \ | |
1208 | if (GET_CODE (X) == PLUS \ | |
1209 | && GET_CODE (XEXP (X, 0)) == REG \ | |
1210 | && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \ | |
1211 | && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \ | |
1212 | && GET_CODE (XEXP (X, 1)) == CONST_INT) \ | |
1213 | { \ | |
1214 | HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \ | |
1215 | HOST_WIDE_INT low, high; \ | |
1216 | \ | |
1217 | if (MODE == DImode || (TARGET_SOFT_FLOAT && MODE == DFmode)) \ | |
1218 | low = ((val & 0xf) ^ 0x8) - 0x8; \ | |
1219 | else if (MODE == SImode \ | |
1220 | || (MODE == SFmode && TARGET_SOFT_FLOAT) \ | |
1221 | || ((MODE == HImode || MODE == QImode) && ! arm_arch4)) \ | |
1222 | /* Need to be careful, -4096 is not a valid offset. */ \ | |
1223 | low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff); \ | |
1224 | else if ((MODE == HImode || MODE == QImode) && arm_arch4) \ | |
1225 | /* Need to be careful, -256 is not a valid offset. */ \ | |
1226 | low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \ | |
1227 | else if (GET_MODE_CLASS (MODE) == MODE_FLOAT \ | |
1228 | && TARGET_HARD_FLOAT) \ | |
1229 | /* Need to be careful, -1024 is not a valid offset. */ \ | |
1230 | low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \ | |
1231 | else \ | |
1232 | break; \ | |
1233 | \ | |
30cf4896 KG |
1234 | high = ((((val - low) & (unsigned HOST_WIDE_INT) 0xffffffff) \ |
1235 | ^ (unsigned HOST_WIDE_INT) 0x80000000) \ | |
1236 | - (unsigned HOST_WIDE_INT) 0x80000000); \ | |
d5b7b3ae RE |
1237 | /* Check for overflow or zero */ \ |
1238 | if (low == 0 || high == 0 || (high + low != val)) \ | |
1239 | break; \ | |
1240 | \ | |
1241 | /* Reload the high part into a base reg; leave the low part \ | |
1242 | in the mem. */ \ | |
1243 | X = gen_rtx_PLUS (GET_MODE (X), \ | |
1244 | gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \ | |
1245 | GEN_INT (high)), \ | |
1246 | GEN_INT (low)); \ | |
df4ae160 | 1247 | push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \ |
4a692617 NC |
1248 | MODE_BASE_REG_CLASS (MODE), GET_MODE (X), \ |
1249 | VOIDmode, 0, 0, OPNUM, TYPE); \ | |
d5b7b3ae RE |
1250 | goto WIN; \ |
1251 | } \ | |
1252 | } \ | |
62b10bbc | 1253 | while (0) |
6f734908 | 1254 | |
d5b7b3ae RE |
1255 | /* ??? If an HImode FP+large_offset address is converted to an HImode |
1256 | SP+large_offset address, then reload won't know how to fix it. It sees | |
1257 | only that SP isn't valid for HImode, and so reloads the SP into an index | |
1258 | register, but the resulting address is still invalid because the offset | |
1259 | is too big. We fix it here instead by reloading the entire address. */ | |
1260 | /* We could probably achieve better results by defining PROMOTE_MODE to help | |
1261 | cope with the variances between the Thumb's signed and unsigned byte and | |
1262 | halfword load instructions. */ | |
1263 | #define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \ | |
1264 | { \ | |
1265 | if (GET_CODE (X) == PLUS \ | |
1266 | && GET_MODE_SIZE (MODE) < 4 \ | |
1267 | && GET_CODE (XEXP (X, 0)) == REG \ | |
1268 | && XEXP (X, 0) == stack_pointer_rtx \ | |
1269 | && GET_CODE (XEXP (X, 1)) == CONST_INT \ | |
f1008e52 | 1270 | && ! THUMB_LEGITIMATE_OFFSET (MODE, INTVAL (XEXP (X, 1)))) \ |
d5b7b3ae RE |
1271 | { \ |
1272 | rtx orig_X = X; \ | |
1273 | X = copy_rtx (X); \ | |
df4ae160 | 1274 | push_reload (orig_X, NULL_RTX, &X, NULL, \ |
4a692617 | 1275 | MODE_BASE_REG_CLASS (MODE), \ |
d5b7b3ae RE |
1276 | Pmode, VOIDmode, 0, 0, OPNUM, TYPE); \ |
1277 | goto WIN; \ | |
1278 | } \ | |
1279 | } | |
1280 | ||
1281 | #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \ | |
1282 | if (TARGET_ARM) \ | |
1283 | ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \ | |
1284 | else \ | |
1285 | THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) | |
1286 | ||
35d965d5 RS |
1287 | /* Return the maximum number of consecutive registers |
1288 | needed to represent mode MODE in a register of class CLASS. | |
1289 | ARM regs are UNITS_PER_WORD bits while FPU regs can hold any FP mode */ | |
1290 | #define CLASS_MAX_NREGS(CLASS, MODE) \ | |
6cfc7210 | 1291 | ((CLASS) == FPU_REGS ? 1 : NUM_REGS (MODE)) |
35d965d5 | 1292 | |
ff9940b0 | 1293 | /* Moves between FPU_REGS and GENERAL_REGS are two memory insns. */ |
cf011243 | 1294 | #define REGISTER_MOVE_COST(MODE, FROM, TO) \ |
d5b7b3ae RE |
1295 | (TARGET_ARM ? \ |
1296 | ((FROM) == FPU_REGS && (TO) != FPU_REGS ? 20 : \ | |
1297 | (FROM) != FPU_REGS && (TO) == FPU_REGS ? 20 : 2) \ | |
1298 | : \ | |
1299 | ((FROM) == HI_REGS || (TO) == HI_REGS) ? 4 : 2) | |
35d965d5 RS |
1300 | \f |
1301 | /* Stack layout; function entry, exit and calling. */ | |
1302 | ||
1303 | /* Define this if pushing a word on the stack | |
1304 | makes the stack pointer a smaller address. */ | |
1305 | #define STACK_GROWS_DOWNWARD 1 | |
1306 | ||
1307 | /* Define this if the nominal address of the stack frame | |
1308 | is at the high-address end of the local variables; | |
1309 | that is, each additional local variable allocated | |
1310 | goes at a more negative offset in the frame. */ | |
1311 | #define FRAME_GROWS_DOWNWARD 1 | |
1312 | ||
1313 | /* Offset within stack frame to start allocating local variables at. | |
1314 | If FRAME_GROWS_DOWNWARD, this is the offset to the END of the | |
1315 | first local allocated. Otherwise, it is the offset to the BEGINNING | |
1316 | of the first local allocated. */ | |
1317 | #define STARTING_FRAME_OFFSET 0 | |
1318 | ||
1319 | /* If we generate an insn to push BYTES bytes, | |
1320 | this says how many the stack pointer really advances by. */ | |
d5b7b3ae RE |
1321 | /* The push insns do not do this rounding implicitly. |
1322 | So don't define this. */ | |
1323 | /* #define PUSH_ROUNDING(NPUSHED) ROUND_UP (NPUSHED) */ | |
18543a22 ILT |
1324 | |
1325 | /* Define this if the maximum size of all the outgoing args is to be | |
1326 | accumulated and pushed during the prologue. The amount can be | |
1327 | found in the variable current_function_outgoing_args_size. */ | |
6cfc7210 | 1328 | #define ACCUMULATE_OUTGOING_ARGS 1 |
35d965d5 RS |
1329 | |
1330 | /* Offset of first parameter from the argument pointer register value. */ | |
d5b7b3ae | 1331 | #define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0) |
35d965d5 RS |
1332 | |
1333 | /* Value is the number of byte of arguments automatically | |
1334 | popped when returning from a subroutine call. | |
8b109b37 | 1335 | FUNDECL is the declaration node of the function (as a tree), |
35d965d5 RS |
1336 | FUNTYPE is the data type of the function (as a tree), |
1337 | or for a library call it is an identifier node for the subroutine name. | |
1338 | SIZE is the number of bytes of arguments passed on the stack. | |
1339 | ||
1340 | On the ARM, the caller does not pop any of its arguments that were passed | |
1341 | on the stack. */ | |
6cfc7210 | 1342 | #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0 |
35d965d5 RS |
1343 | |
1344 | /* Define how to find the value returned by a library function | |
1345 | assuming the value has mode MODE. */ | |
1346 | #define LIBCALL_VALUE(MODE) \ | |
d5b7b3ae RE |
1347 | (TARGET_ARM && TARGET_HARD_FLOAT && GET_MODE_CLASS (MODE) == MODE_FLOAT \ |
1348 | ? gen_rtx_REG (MODE, FIRST_ARM_FP_REGNUM) \ | |
1349 | : gen_rtx_REG (MODE, ARG_REGISTER (1))) | |
35d965d5 | 1350 | |
6cfc7210 NC |
1351 | /* Define how to find the value returned by a function. |
1352 | VALTYPE is the data type of the value (as a tree). | |
1353 | If the precise function being called is known, FUNC is its FUNCTION_DECL; | |
1354 | otherwise, FUNC is 0. */ | |
d5b7b3ae | 1355 | #define FUNCTION_VALUE(VALTYPE, FUNC) \ |
6cfc7210 NC |
1356 | LIBCALL_VALUE (TYPE_MODE (VALTYPE)) |
1357 | ||
35d965d5 RS |
1358 | /* 1 if N is a possible register number for a function value. |
1359 | On the ARM, only r0 and f0 can return results. */ | |
1360 | #define FUNCTION_VALUE_REGNO_P(REGNO) \ | |
d5b7b3ae RE |
1361 | ((REGNO) == ARG_REGISTER (1) \ |
1362 | || (TARGET_ARM && ((REGNO) == FIRST_ARM_FP_REGNUM) && TARGET_HARD_FLOAT)) | |
35d965d5 | 1363 | |
11c1a207 RE |
1364 | /* How large values are returned */ |
1365 | /* A C expression which can inhibit the returning of certain function values | |
1366 | in registers, based on the type of value. */ | |
f5a1b0d2 | 1367 | #define RETURN_IN_MEMORY(TYPE) arm_return_in_memory (TYPE) |
11c1a207 RE |
1368 | |
1369 | /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return | |
1370 | values must be in memory. On the ARM, they need only do so if larger | |
1371 | than a word, or if they contain elements offset from zero in the struct. */ | |
1372 | #define DEFAULT_PCC_STRUCT_RETURN 0 | |
1373 | ||
d5b7b3ae RE |
1374 | /* Flags for the call/call_value rtl operations set up by function_arg. */ |
1375 | #define CALL_NORMAL 0x00000000 /* No special processing. */ | |
1376 | #define CALL_LONG 0x00000001 /* Always call indirect. */ | |
1377 | #define CALL_SHORT 0x00000002 /* Never call indirect. */ | |
1378 | ||
6d3d9133 NC |
1379 | /* These bits describe the different types of function supported |
1380 | by the ARM backend. They are exclusive. ie a function cannot be both a | |
1381 | normal function and an interworked function, for example. Knowing the | |
1382 | type of a function is important for determining its prologue and | |
1383 | epilogue sequences. | |
1384 | Note value 7 is currently unassigned. Also note that the interrupt | |
1385 | function types all have bit 2 set, so that they can be tested for easily. | |
1386 | Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the | |
1387 | machine_function structure is initialised (to zero) func_type will | |
1388 | default to unknown. This will force the first use of arm_current_func_type | |
1389 | to call arm_compute_func_type. */ | |
1390 | #define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */ | |
1391 | #define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */ | |
1392 | #define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */ | |
1393 | #define ARM_FT_EXCEPTION_HANDLER 3 /* A C++ exception handler. */ | |
1394 | #define ARM_FT_ISR 4 /* An interrupt service routine. */ | |
1395 | #define ARM_FT_FIQ 5 /* A fast interrupt service routine. */ | |
1396 | #define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */ | |
1397 | ||
1398 | #define ARM_FT_TYPE_MASK ((1 << 3) - 1) | |
1399 | ||
1400 | /* In addition functions can have several type modifiers, | |
1401 | outlined by these bit masks: */ | |
1402 | #define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */ | |
1403 | #define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */ | |
1404 | #define ARM_FT_VOLATILE (1 << 4) /* Does not return. */ | |
1405 | #define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */ | |
1406 | ||
1407 | /* Some macros to test these flags. */ | |
1408 | #define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK) | |
1409 | #define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT) | |
1410 | #define IS_VOLATILE(t) (t & ARM_FT_VOLATILE) | |
1411 | #define IS_NAKED(t) (t & ARM_FT_NAKED) | |
1412 | #define IS_NESTED(t) (t & ARM_FT_NESTED) | |
1413 | ||
1414 | /* A C structure for machine-specific, per-function data. | |
1415 | This is added to the cfun structure. */ | |
e2500fed | 1416 | typedef struct machine_function GTY(()) |
d5b7b3ae | 1417 | { |
d5b7b3ae | 1418 | /* Additionsl stack adjustment in __builtin_eh_throw. */ |
e2500fed | 1419 | rtx eh_epilogue_sp_ofs; |
d5b7b3ae RE |
1420 | /* Records if LR has to be saved for far jumps. */ |
1421 | int far_jump_used; | |
1422 | /* Records if ARG_POINTER was ever live. */ | |
1423 | int arg_pointer_live; | |
6f7ebcbb NC |
1424 | /* Records if the save of LR has been eliminated. */ |
1425 | int lr_save_eliminated; | |
6d3d9133 NC |
1426 | /* Records the type of the current function. */ |
1427 | unsigned long func_type; | |
3cb66fd7 NC |
1428 | /* Record if the function has a variable argument list. */ |
1429 | int uses_anonymous_args; | |
6d3d9133 NC |
1430 | } |
1431 | machine_function; | |
d5b7b3ae | 1432 | |
82e9d970 PB |
1433 | /* A C type for declaring a variable that is used as the first argument of |
1434 | `FUNCTION_ARG' and other related values. For some target machines, the | |
1435 | type `int' suffices and can hold the number of bytes of argument so far. */ | |
1436 | typedef struct | |
1437 | { | |
d5b7b3ae | 1438 | /* This is the number of registers of arguments scanned so far. */ |
82e9d970 | 1439 | int nregs; |
d5b7b3ae | 1440 | /* One of CALL_NORMAL, CALL_LONG or CALL_SHORT . */ |
82e9d970 | 1441 | int call_cookie; |
d5b7b3ae | 1442 | } CUMULATIVE_ARGS; |
82e9d970 | 1443 | |
35d965d5 RS |
1444 | /* Define where to put the arguments to a function. |
1445 | Value is zero to push the argument on the stack, | |
1446 | or a hard register in which to store the argument. | |
1447 | ||
1448 | MODE is the argument's machine mode. | |
1449 | TYPE is the data type of the argument (as a tree). | |
1450 | This is null for libcalls where that information may | |
1451 | not be available. | |
1452 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
1453 | the preceding args and about the function being called. | |
1454 | NAMED is nonzero if this argument is a named parameter | |
1455 | (otherwise it is an extra parameter matching an ellipsis). | |
1456 | ||
1457 | On the ARM, normally the first 16 bytes are passed in registers r0-r3; all | |
1458 | other arguments are passed on the stack. If (NAMED == 0) (which happens | |
1459 | only in assign_parms, since SETUP_INCOMING_VARARGS is defined), say it is | |
1460 | passed in the stack (function_prologue will indeed make it pass in the | |
1461 | stack if necessary). */ | |
82e9d970 PB |
1462 | #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ |
1463 | arm_function_arg (&(CUM), (MODE), (TYPE), (NAMED)) | |
35d965d5 RS |
1464 | |
1465 | /* For an arg passed partly in registers and partly in memory, | |
1466 | this is the number of registers used. | |
1467 | For args passed entirely in registers or entirely in memory, zero. */ | |
6cfc7210 | 1468 | #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \ |
82e9d970 PB |
1469 | ( NUM_ARG_REGS > (CUM).nregs \ |
1470 | && (NUM_ARG_REGS < ((CUM).nregs + NUM_REGS2 (MODE, TYPE))) \ | |
1471 | ? NUM_ARG_REGS - (CUM).nregs : 0) | |
35d965d5 RS |
1472 | |
1473 | /* Initialize a variable CUM of type CUMULATIVE_ARGS | |
1474 | for a call to a function whose data type is FNTYPE. | |
1475 | For a library call, FNTYPE is 0. | |
1476 | On the ARM, the offset starts at 0. */ | |
82e9d970 PB |
1477 | #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \ |
1478 | arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (INDIRECT)) | |
35d965d5 RS |
1479 | |
1480 | /* Update the data in CUM to advance over an argument | |
1481 | of mode MODE and data type TYPE. | |
1482 | (TYPE is null for libcalls where that information may not be available.) */ | |
6cfc7210 | 1483 | #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ |
82e9d970 | 1484 | (CUM).nregs += NUM_REGS2 (MODE, TYPE) |
35d965d5 RS |
1485 | |
1486 | /* 1 if N is a possible register number for function argument passing. | |
1487 | On the ARM, r0-r3 are used to pass args. */ | |
5297e085 | 1488 | #define FUNCTION_ARG_REGNO_P(REGNO) (IN_RANGE ((REGNO), 0, 3)) |
35d965d5 | 1489 | |
f99fce0c RE |
1490 | \f |
1491 | /* Tail calling. */ | |
1492 | ||
1493 | /* A C expression that evaluates to true if it is ok to perform a sibling | |
1494 | call to DECL. */ | |
1495 | #define FUNCTION_OK_FOR_SIBCALL(DECL) arm_function_ok_for_sibcall ((DECL)) | |
1496 | ||
35d965d5 RS |
1497 | /* Perform any actions needed for a function that is receiving a variable |
1498 | number of arguments. CUM is as above. MODE and TYPE are the mode and type | |
1499 | of the current parameter. PRETEND_SIZE is a variable that should be set to | |
1500 | the amount of stack that must be pushed by the prolog to pretend that our | |
1501 | caller pushed it. | |
1502 | ||
1503 | Normally, this macro will push all remaining incoming registers on the | |
1504 | stack and set PRETEND_SIZE to the length of the registers pushed. | |
1505 | ||
1506 | On the ARM, PRETEND_SIZE is set in order to have the prologue push the last | |
1507 | named arg and all anonymous args onto the stack. | |
1508 | XXX I know the prologue shouldn't be pushing registers, but it is faster | |
1509 | that way. */ | |
6cfc7210 | 1510 | #define SETUP_INCOMING_VARARGS(CUM, MODE, TYPE, PRETEND_SIZE, NO_RTL) \ |
35d965d5 | 1511 | { \ |
3cb66fd7 | 1512 | cfun->machine->uses_anonymous_args = 1; \ |
82e9d970 PB |
1513 | if ((CUM).nregs < NUM_ARG_REGS) \ |
1514 | (PRETEND_SIZE) = (NUM_ARG_REGS - (CUM).nregs) * UNITS_PER_WORD; \ | |
35d965d5 RS |
1515 | } |
1516 | ||
afef3d7a NC |
1517 | /* If your target environment doesn't prefix user functions with an |
1518 | underscore, you may wish to re-define this to prevent any conflicts. | |
1519 | e.g. AOF may prefix mcount with an underscore. */ | |
1520 | #ifndef ARM_MCOUNT_NAME | |
1521 | #define ARM_MCOUNT_NAME "*mcount" | |
1522 | #endif | |
1523 | ||
1524 | /* Call the function profiler with a given profile label. The Acorn | |
1525 | compiler puts this BEFORE the prolog but gcc puts it afterwards. | |
1526 | On the ARM the full profile code will look like: | |
1527 | .data | |
1528 | LP1 | |
1529 | .word 0 | |
1530 | .text | |
1531 | mov ip, lr | |
1532 | bl mcount | |
1533 | .word LP1 | |
1534 | ||
1535 | profile_function() in final.c outputs the .data section, FUNCTION_PROFILER | |
1536 | will output the .text section. | |
1537 | ||
1538 | The ``mov ip,lr'' seems like a good idea to stick with cc convention. | |
1539 | ``prof'' doesn't seem to mind about this! */ | |
be393ecf | 1540 | #ifndef ARM_FUNCTION_PROFILER |
d5b7b3ae | 1541 | #define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \ |
6cfc7210 NC |
1542 | { \ |
1543 | char temp[20]; \ | |
1544 | rtx sym; \ | |
1545 | \ | |
dd18ae56 | 1546 | asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \ |
d5b7b3ae | 1547 | IP_REGNUM, LR_REGNUM); \ |
6cfc7210 NC |
1548 | assemble_name (STREAM, ARM_MCOUNT_NAME); \ |
1549 | fputc ('\n', STREAM); \ | |
1550 | ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \ | |
1551 | sym = gen_rtx (SYMBOL_REF, Pmode, temp); \ | |
301d03af | 1552 | assemble_aligned_integer (UNITS_PER_WORD, sym); \ |
35d965d5 | 1553 | } |
be393ecf | 1554 | #endif |
35d965d5 | 1555 | |
cf8002d0 | 1556 | #ifndef THUMB_FUNCTION_PROFILER |
d5b7b3ae RE |
1557 | #define THUMB_FUNCTION_PROFILER(STREAM, LABELNO) \ |
1558 | { \ | |
89632846 | 1559 | fprintf (STREAM, "\tmov\tip, lr\n"); \ |
d5b7b3ae RE |
1560 | fprintf (STREAM, "\tbl\tmcount\n"); \ |
1561 | fprintf (STREAM, "\t.word\tLP%d\n", LABELNO); \ | |
1562 | } | |
cf8002d0 | 1563 | #endif |
d5b7b3ae RE |
1564 | |
1565 | #define FUNCTION_PROFILER(STREAM, LABELNO) \ | |
1566 | if (TARGET_ARM) \ | |
1567 | ARM_FUNCTION_PROFILER (STREAM, LABELNO) \ | |
1568 | else \ | |
1569 | THUMB_FUNCTION_PROFILER (STREAM, LABELNO) | |
1570 | ||
35d965d5 RS |
1571 | /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, |
1572 | the stack pointer does not matter. The value is tested only in | |
1573 | functions that have frame pointers. | |
1574 | No definition is equivalent to always zero. | |
1575 | ||
1576 | On the ARM, the function epilogue recovers the stack pointer from the | |
1577 | frame. */ | |
1578 | #define EXIT_IGNORE_STACK 1 | |
1579 | ||
c7861455 RE |
1580 | #define EPILOGUE_USES(REGNO) (reload_completed && (REGNO) == LR_REGNUM) |
1581 | ||
35d965d5 RS |
1582 | /* Determine if the epilogue should be output as RTL. |
1583 | You should override this if you define FUNCTION_EXTRA_EPILOGUE. */ | |
d5b7b3ae RE |
1584 | #define USE_RETURN_INSN(ISCOND) \ |
1585 | (TARGET_ARM ? use_return_insn (ISCOND) : 0) | |
ff9940b0 RE |
1586 | |
1587 | /* Definitions for register eliminations. | |
1588 | ||
1589 | This is an array of structures. Each structure initializes one pair | |
1590 | of eliminable registers. The "from" register number is given first, | |
1591 | followed by "to". Eliminations of the same "from" register are listed | |
1592 | in order of preference. | |
1593 | ||
1594 | We have two registers that can be eliminated on the ARM. First, the | |
1595 | arg pointer register can often be eliminated in favor of the stack | |
1596 | pointer register. Secondly, the pseudo frame pointer register can always | |
1597 | be eliminated; it is replaced with either the stack or the real frame | |
d5b7b3ae | 1598 | pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM |
d6a7951f | 1599 | because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */ |
ff9940b0 | 1600 | |
d5b7b3ae RE |
1601 | #define ELIMINABLE_REGS \ |
1602 | {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\ | |
1603 | { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\ | |
1604 | { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\ | |
1605 | { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\ | |
1606 | { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\ | |
1607 | { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\ | |
1608 | { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }} | |
ff9940b0 | 1609 | |
d5b7b3ae RE |
1610 | /* Given FROM and TO register numbers, say whether this elimination is |
1611 | allowed. Frame pointer elimination is automatically handled. | |
ff9940b0 RE |
1612 | |
1613 | All eliminations are permissible. Note that ARG_POINTER_REGNUM and | |
abc95ed3 | 1614 | HARD_FRAME_POINTER_REGNUM are in fact the same thing. If we need a frame |
ff9940b0 | 1615 | pointer, we must eliminate FRAME_POINTER_REGNUM into |
d5b7b3ae RE |
1616 | HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM or |
1617 | ARG_POINTER_REGNUM. */ | |
1618 | #define CAN_ELIMINATE(FROM, TO) \ | |
1619 | (((TO) == FRAME_POINTER_REGNUM && (FROM) == ARG_POINTER_REGNUM) ? 0 : \ | |
1620 | ((TO) == STACK_POINTER_REGNUM && frame_pointer_needed) ? 0 : \ | |
1621 | ((TO) == ARM_HARD_FRAME_POINTER_REGNUM && TARGET_THUMB) ? 0 : \ | |
1622 | ((TO) == THUMB_HARD_FRAME_POINTER_REGNUM && TARGET_ARM) ? 0 : \ | |
1623 | 1) | |
1624 | ||
1625 | /* Define the offset between two registers, one to be eliminated, and the | |
1626 | other its replacement, at the start of a routine. */ | |
1627 | #define ARM_INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ | |
095bb276 | 1628 | do \ |
ff9940b0 | 1629 | { \ |
095bb276 | 1630 | (OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \ |
ff9940b0 | 1631 | } \ |
095bb276 | 1632 | while (0) |
35d965d5 | 1633 | |
d5b7b3ae RE |
1634 | /* Note: This macro must match the code in thumb_function_prologue(). */ |
1635 | #define THUMB_INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ | |
1636 | { \ | |
1637 | (OFFSET) = 0; \ | |
1638 | if ((FROM) == ARG_POINTER_REGNUM) \ | |
1639 | { \ | |
1640 | int count_regs = 0; \ | |
1641 | int regno; \ | |
1642 | for (regno = 8; regno < 13; regno ++) \ | |
1643 | if (regs_ever_live[regno] && ! call_used_regs[regno]) \ | |
1644 | count_regs ++; \ | |
1645 | if (count_regs) \ | |
1646 | (OFFSET) += 4 * count_regs; \ | |
1647 | count_regs = 0; \ | |
1648 | for (regno = 0; regno <= LAST_LO_REGNUM; regno ++) \ | |
1649 | if (regs_ever_live[regno] && ! call_used_regs[regno]) \ | |
1650 | count_regs ++; \ | |
1651 | if (count_regs || ! leaf_function_p () || thumb_far_jump_used_p (0))\ | |
1652 | (OFFSET) += 4 * (count_regs + 1); \ | |
1653 | if (TARGET_BACKTRACE) \ | |
1654 | { \ | |
1655 | if ((count_regs & 0xFF) == 0 && (regs_ever_live[3] != 0)) \ | |
1656 | (OFFSET) += 20; \ | |
1657 | else \ | |
1658 | (OFFSET) += 16; \ | |
1659 | } \ | |
1660 | } \ | |
1661 | if ((TO) == STACK_POINTER_REGNUM) \ | |
1662 | { \ | |
1663 | (OFFSET) += current_function_outgoing_args_size; \ | |
1664 | (OFFSET) += ROUND_UP (get_frame_size ()); \ | |
1665 | } \ | |
1666 | } | |
1667 | ||
1668 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ | |
1669 | if (TARGET_ARM) \ | |
095bb276 | 1670 | ARM_INITIAL_ELIMINATION_OFFSET (FROM, TO, OFFSET); \ |
d5b7b3ae RE |
1671 | else \ |
1672 | THUMB_INITIAL_ELIMINATION_OFFSET (FROM, TO, OFFSET) | |
1673 | ||
1674 | /* Special case handling of the location of arguments passed on the stack. */ | |
1675 | #define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr) | |
1676 | ||
1677 | /* Initialize data used by insn expanders. This is called from insn_emit, | |
1678 | once for every function before code is generated. */ | |
1679 | #define INIT_EXPANDERS arm_init_expanders () | |
1680 | ||
35d965d5 RS |
1681 | /* Output assembler code for a block containing the constant parts |
1682 | of a trampoline, leaving space for the variable parts. | |
1683 | ||
1684 | On the ARM, (if r8 is the static chain regnum, and remembering that | |
1685 | referencing pc adds an offset of 8) the trampoline looks like: | |
1686 | ldr r8, [pc, #0] | |
1687 | ldr pc, [pc] | |
1688 | .word static chain value | |
11c1a207 RE |
1689 | .word function's address |
1690 | ??? FIXME: When the trampoline returns, r8 will be clobbered. */ | |
301d03af RS |
1691 | #define ARM_TRAMPOLINE_TEMPLATE(FILE) \ |
1692 | { \ | |
1693 | asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \ | |
1694 | STATIC_CHAIN_REGNUM, PC_REGNUM); \ | |
1695 | asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \ | |
1696 | PC_REGNUM, PC_REGNUM); \ | |
1697 | assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \ | |
1698 | assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \ | |
d5b7b3ae RE |
1699 | } |
1700 | ||
1701 | /* On the Thumb we always switch into ARM mode to execute the trampoline. | |
1702 | Why - because it is easier. This code will always be branched to via | |
1703 | a BX instruction and since the compiler magically generates the address | |
1704 | of the function the linker has no opportunity to ensure that the | |
1705 | bottom bit is set. Thus the processor will be in ARM mode when it | |
1706 | reaches this code. So we duplicate the ARM trampoline code and add | |
1707 | a switch into Thumb mode as well. */ | |
1708 | #define THUMB_TRAMPOLINE_TEMPLATE(FILE) \ | |
1709 | { \ | |
1710 | fprintf (FILE, "\t.code 32\n"); \ | |
1711 | fprintf (FILE, ".Ltrampoline_start:\n"); \ | |
1712 | asm_fprintf (FILE, "\tldr\t%r, [%r, #8]\n", \ | |
1713 | STATIC_CHAIN_REGNUM, PC_REGNUM); \ | |
1714 | asm_fprintf (FILE, "\tldr\t%r, [%r, #8]\n", \ | |
1715 | IP_REGNUM, PC_REGNUM); \ | |
1716 | asm_fprintf (FILE, "\torr\t%r, %r, #1\n", \ | |
1717 | IP_REGNUM, IP_REGNUM); \ | |
1718 | asm_fprintf (FILE, "\tbx\t%r\n", IP_REGNUM); \ | |
1719 | fprintf (FILE, "\t.word\t0\n"); \ | |
1720 | fprintf (FILE, "\t.word\t0\n"); \ | |
1721 | fprintf (FILE, "\t.code 16\n"); \ | |
35d965d5 RS |
1722 | } |
1723 | ||
d5b7b3ae RE |
1724 | #define TRAMPOLINE_TEMPLATE(FILE) \ |
1725 | if (TARGET_ARM) \ | |
1726 | ARM_TRAMPOLINE_TEMPLATE (FILE) \ | |
1727 | else \ | |
1728 | THUMB_TRAMPOLINE_TEMPLATE (FILE) | |
1729 | ||
35d965d5 | 1730 | /* Length in units of the trampoline for entering a nested function. */ |
d5b7b3ae | 1731 | #define TRAMPOLINE_SIZE (TARGET_ARM ? 16 : 24) |
35d965d5 | 1732 | |
006946e4 JM |
1733 | /* Alignment required for a trampoline in bits. */ |
1734 | #define TRAMPOLINE_ALIGNMENT 32 | |
35d965d5 RS |
1735 | |
1736 | /* Emit RTL insns to initialize the variable parts of a trampoline. | |
1737 | FNADDR is an RTX for the address of the function's pure code. | |
1738 | CXT is an RTX for the static chain value for the function. */ | |
d5b7b3ae RE |
1739 | #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ |
1740 | { \ | |
1741 | emit_move_insn \ | |
1742 | (gen_rtx_MEM (SImode, plus_constant (TRAMP, TARGET_ARM ? 8 : 16)), CXT); \ | |
1743 | emit_move_insn \ | |
1744 | (gen_rtx_MEM (SImode, plus_constant (TRAMP, TARGET_ARM ? 12 : 20)), FNADDR); \ | |
35d965d5 RS |
1745 | } |
1746 | ||
35d965d5 RS |
1747 | \f |
1748 | /* Addressing modes, and classification of registers for them. */ | |
35d965d5 | 1749 | #define HAVE_POST_INCREMENT 1 |
d5b7b3ae RE |
1750 | #define HAVE_PRE_INCREMENT TARGET_ARM |
1751 | #define HAVE_POST_DECREMENT TARGET_ARM | |
1752 | #define HAVE_PRE_DECREMENT TARGET_ARM | |
35d965d5 RS |
1753 | |
1754 | /* Macros to check register numbers against specific register classes. */ | |
1755 | ||
1756 | /* These assume that REGNO is a hard or pseudo reg number. | |
1757 | They give nonzero only if REGNO is a hard reg of the suitable class | |
1758 | or a pseudo reg currently allocated to a suitable hard reg. | |
1759 | Since they use reg_renumber, they are safe only once reg_renumber | |
d5b7b3ae RE |
1760 | has been allocated, which happens in local-alloc.c. */ |
1761 | #define TEST_REGNO(R, TEST, VALUE) \ | |
1762 | ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE)) | |
1763 | ||
1764 | /* On the ARM, don't allow the pc to be used. */ | |
f1008e52 RE |
1765 | #define ARM_REGNO_OK_FOR_BASE_P(REGNO) \ |
1766 | (TEST_REGNO (REGNO, <, PC_REGNUM) \ | |
1767 | || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \ | |
1768 | || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM)) | |
1769 | ||
1770 | #define THUMB_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \ | |
1771 | (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \ | |
1772 | || (GET_MODE_SIZE (MODE) >= 4 \ | |
1773 | && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM))) | |
1774 | ||
1775 | #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \ | |
1776 | (TARGET_THUMB \ | |
1777 | ? THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \ | |
1778 | : ARM_REGNO_OK_FOR_BASE_P (REGNO)) | |
1779 | ||
1780 | /* For ARM code, we don't care about the mode, but for Thumb, the index | |
1781 | must be suitable for use in a QImode load. */ | |
d5b7b3ae RE |
1782 | #define REGNO_OK_FOR_INDEX_P(REGNO) \ |
1783 | REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode) | |
35d965d5 RS |
1784 | |
1785 | /* Maximum number of registers that can appear in a valid memory address. | |
ff9940b0 | 1786 | Shifts in addresses can't be by a register. */ |
ff9940b0 | 1787 | #define MAX_REGS_PER_ADDRESS 2 |
35d965d5 RS |
1788 | |
1789 | /* Recognize any constant value that is a valid address. */ | |
1790 | /* XXX We can address any constant, eventually... */ | |
11c1a207 RE |
1791 | |
1792 | #ifdef AOF_ASSEMBLER | |
1793 | ||
1794 | #define CONSTANT_ADDRESS_P(X) \ | |
d5b7b3ae | 1795 | (GET_CODE (X) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (X)) |
11c1a207 RE |
1796 | |
1797 | #else | |
35d965d5 | 1798 | |
008cf58a RE |
1799 | #define CONSTANT_ADDRESS_P(X) \ |
1800 | (GET_CODE (X) == SYMBOL_REF \ | |
1801 | && (CONSTANT_POOL_ADDRESS_P (X) \ | |
d5b7b3ae | 1802 | || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X)))) |
35d965d5 | 1803 | |
11c1a207 RE |
1804 | #endif /* AOF_ASSEMBLER */ |
1805 | ||
35d965d5 RS |
1806 | /* Nonzero if the constant value X is a legitimate general operand. |
1807 | It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. | |
1808 | ||
1809 | On the ARM, allow any integer (invalid ones are removed later by insn | |
1810 | patterns), nice doubles and symbol_refs which refer to the function's | |
d5b7b3ae | 1811 | constant pool XXX. |
82e9d970 PB |
1812 | |
1813 | When generating pic allow anything. */ | |
d5b7b3ae RE |
1814 | #define ARM_LEGITIMATE_CONSTANT_P(X) (flag_pic || ! label_mentioned_p (X)) |
1815 | ||
1816 | #define THUMB_LEGITIMATE_CONSTANT_P(X) \ | |
1817 | ( GET_CODE (X) == CONST_INT \ | |
1818 | || GET_CODE (X) == CONST_DOUBLE \ | |
7b8781c8 PB |
1819 | || CONSTANT_ADDRESS_P (X) \ |
1820 | || flag_pic) | |
d5b7b3ae RE |
1821 | |
1822 | #define LEGITIMATE_CONSTANT_P(X) \ | |
1823 | (TARGET_ARM ? ARM_LEGITIMATE_CONSTANT_P (X) : THUMB_LEGITIMATE_CONSTANT_P (X)) | |
1824 | ||
c27ba912 DM |
1825 | /* Special characters prefixed to function names |
1826 | in order to encode attribute like information. | |
1827 | Note, '@' and '*' have already been taken. */ | |
1828 | #define SHORT_CALL_FLAG_CHAR '^' | |
1829 | #define LONG_CALL_FLAG_CHAR '#' | |
1830 | ||
1831 | #define ENCODED_SHORT_CALL_ATTR_P(SYMBOL_NAME) \ | |
1832 | (*(SYMBOL_NAME) == SHORT_CALL_FLAG_CHAR) | |
1833 | ||
1834 | #define ENCODED_LONG_CALL_ATTR_P(SYMBOL_NAME) \ | |
1835 | (*(SYMBOL_NAME) == LONG_CALL_FLAG_CHAR) | |
1836 | ||
1837 | #ifndef SUBTARGET_NAME_ENCODING_LENGTHS | |
1838 | #define SUBTARGET_NAME_ENCODING_LENGTHS | |
1839 | #endif | |
1840 | ||
1841 | /* This is a C fragement for the inside of a switch statement. | |
1842 | Each case label should return the number of characters to | |
1843 | be stripped from the start of a function's name, if that | |
1844 | name starts with the indicated character. */ | |
1845 | #define ARM_NAME_ENCODING_LENGTHS \ | |
1846 | case SHORT_CALL_FLAG_CHAR: return 1; \ | |
1847 | case LONG_CALL_FLAG_CHAR: return 1; \ | |
00fdafef | 1848 | case '*': return 1; \ |
c27ba912 DM |
1849 | SUBTARGET_NAME_ENCODING_LENGTHS |
1850 | ||
c27ba912 DM |
1851 | /* This is how to output a reference to a user-level label named NAME. |
1852 | `assemble_name' uses this. */ | |
e5951263 | 1853 | #undef ASM_OUTPUT_LABELREF |
c27ba912 | 1854 | #define ASM_OUTPUT_LABELREF(FILE, NAME) \ |
d4206a10 | 1855 | asm_fprintf (FILE, "%U%s", arm_strip_name_encoding (NAME)) |
c27ba912 | 1856 | |
c27ba912 DM |
1857 | #define ARM_DECLARE_FUNCTION_SIZE(STREAM, NAME, DECL) \ |
1858 | arm_encode_call_attribute (DECL, SHORT_CALL_FLAG_CHAR) | |
1859 | ||
35d965d5 RS |
1860 | /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx |
1861 | and check its validity for a certain class. | |
1862 | We have two alternate definitions for each of them. | |
1863 | The usual definition accepts all pseudo regs; the other rejects | |
1864 | them unless they have been allocated suitable hard regs. | |
1865 | The symbol REG_OK_STRICT causes the latter definition to be used. */ | |
1866 | #ifndef REG_OK_STRICT | |
ff9940b0 | 1867 | |
f1008e52 RE |
1868 | #define ARM_REG_OK_FOR_BASE_P(X) \ |
1869 | (REGNO (X) <= LAST_ARM_REGNUM \ | |
1870 | || REGNO (X) >= FIRST_PSEUDO_REGISTER \ | |
1871 | || REGNO (X) == FRAME_POINTER_REGNUM \ | |
1872 | || REGNO (X) == ARG_POINTER_REGNUM) | |
ff9940b0 | 1873 | |
f1008e52 RE |
1874 | #define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \ |
1875 | (REGNO (X) <= LAST_LO_REGNUM \ | |
1876 | || REGNO (X) >= FIRST_PSEUDO_REGISTER \ | |
1877 | || (GET_MODE_SIZE (MODE) >= 4 \ | |
1878 | && (REGNO (X) == STACK_POINTER_REGNUM \ | |
1879 | || (X) == hard_frame_pointer_rtx \ | |
1880 | || (X) == arg_pointer_rtx))) | |
ff9940b0 | 1881 | |
d5b7b3ae | 1882 | #else /* REG_OK_STRICT */ |
ff9940b0 | 1883 | |
f1008e52 RE |
1884 | #define ARM_REG_OK_FOR_BASE_P(X) \ |
1885 | ARM_REGNO_OK_FOR_BASE_P (REGNO (X)) | |
ff9940b0 | 1886 | |
f1008e52 RE |
1887 | #define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \ |
1888 | THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE) | |
ff9940b0 | 1889 | |
d5b7b3ae | 1890 | #endif /* REG_OK_STRICT */ |
f1008e52 RE |
1891 | |
1892 | /* Now define some helpers in terms of the above. */ | |
1893 | ||
1894 | #define REG_MODE_OK_FOR_BASE_P(X, MODE) \ | |
1895 | (TARGET_THUMB \ | |
1896 | ? THUMB_REG_MODE_OK_FOR_BASE_P (X, MODE) \ | |
1897 | : ARM_REG_OK_FOR_BASE_P (X)) | |
1898 | ||
1899 | #define ARM_REG_OK_FOR_INDEX_P(X) ARM_REG_OK_FOR_BASE_P (X) | |
1900 | ||
1901 | /* For Thumb, a valid index register is anything that can be used in | |
1902 | a byte load instruction. */ | |
1903 | #define THUMB_REG_OK_FOR_INDEX_P(X) THUMB_REG_MODE_OK_FOR_BASE_P (X, QImode) | |
1904 | ||
1905 | /* Nonzero if X is a hard reg that can be used as an index | |
1906 | or if it is a pseudo reg. On the Thumb, the stack pointer | |
1907 | is not suitable. */ | |
1908 | #define REG_OK_FOR_INDEX_P(X) \ | |
1909 | (TARGET_THUMB \ | |
1910 | ? THUMB_REG_OK_FOR_INDEX_P (X) \ | |
1911 | : ARM_REG_OK_FOR_INDEX_P (X)) | |
1912 | ||
35d965d5 RS |
1913 | \f |
1914 | /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression | |
1915 | that is a valid memory address for an instruction. | |
1916 | The MODE argument is the machine mode for the MEM expression | |
1917 | that wants to use this address. | |
1918 | ||
d5b7b3ae RE |
1919 | The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */ |
1920 | ||
1921 | /* --------------------------------arm version----------------------------- */ | |
f1008e52 RE |
1922 | #define ARM_BASE_REGISTER_RTX_P(X) \ |
1923 | (GET_CODE (X) == REG && ARM_REG_OK_FOR_BASE_P (X)) | |
35d965d5 | 1924 | |
f1008e52 RE |
1925 | #define ARM_INDEX_REGISTER_RTX_P(X) \ |
1926 | (GET_CODE (X) == REG && ARM_REG_OK_FOR_INDEX_P (X)) | |
35d965d5 RS |
1927 | |
1928 | /* A C statement (sans semicolon) to jump to LABEL for legitimate index RTXs | |
1929 | used by the macro GO_IF_LEGITIMATE_ADDRESS. Floating point indices can | |
1930 | only be small constants. */ | |
f1008e52 RE |
1931 | #define ARM_GO_IF_LEGITIMATE_INDEX(MODE, BASE_REGNO, INDEX, LABEL) \ |
1932 | do \ | |
35d965d5 | 1933 | { \ |
f1008e52 RE |
1934 | HOST_WIDE_INT range; \ |
1935 | enum rtx_code code = GET_CODE (INDEX); \ | |
35d965d5 | 1936 | \ |
f1008e52 RE |
1937 | if (TARGET_HARD_FLOAT && GET_MODE_CLASS (MODE) == MODE_FLOAT) \ |
1938 | { \ | |
1939 | if (code == CONST_INT && INTVAL (INDEX) < 1024 \ | |
1940 | && INTVAL (INDEX) > -1024 \ | |
1941 | && (INTVAL (INDEX) & 3) == 0) \ | |
1942 | goto LABEL; \ | |
1943 | } \ | |
1944 | else \ | |
1945 | { \ | |
1946 | if (ARM_INDEX_REGISTER_RTX_P (INDEX) \ | |
1947 | && GET_MODE_SIZE (MODE) <= 4) \ | |
1948 | goto LABEL; \ | |
1949 | if (GET_MODE_SIZE (MODE) <= 4 && code == MULT \ | |
1950 | && (! arm_arch4 || (MODE) != HImode)) \ | |
1951 | { \ | |
1952 | rtx xiop0 = XEXP (INDEX, 0); \ | |
1953 | rtx xiop1 = XEXP (INDEX, 1); \ | |
1954 | if (ARM_INDEX_REGISTER_RTX_P (xiop0) \ | |
1955 | && power_of_two_operand (xiop1, SImode)) \ | |
1956 | goto LABEL; \ | |
1957 | if (ARM_INDEX_REGISTER_RTX_P (xiop1) \ | |
1958 | && power_of_two_operand (xiop0, SImode)) \ | |
1959 | goto LABEL; \ | |
1960 | } \ | |
1961 | if (GET_MODE_SIZE (MODE) <= 4 \ | |
1962 | && (code == LSHIFTRT || code == ASHIFTRT \ | |
1963 | || code == ASHIFT || code == ROTATERT) \ | |
1964 | && (! arm_arch4 || (MODE) != HImode)) \ | |
1965 | { \ | |
1966 | rtx op = XEXP (INDEX, 1); \ | |
1967 | if (ARM_INDEX_REGISTER_RTX_P (XEXP (INDEX, 0)) \ | |
1968 | && GET_CODE (op) == CONST_INT && INTVAL (op) > 0 \ | |
1969 | && INTVAL (op) <= 31) \ | |
1970 | goto LABEL; \ | |
1971 | } \ | |
1972 | /* NASTY: Since this limits the addressing of unsigned \ | |
1973 | byte loads. */ \ | |
1974 | range = ((MODE) == HImode || (MODE) == QImode) \ | |
1975 | ? (arm_arch4 ? 256 : 4095) : 4096; \ | |
1976 | if (code == CONST_INT && INTVAL (INDEX) < range \ | |
1977 | && INTVAL (INDEX) > -range) \ | |
1978 | goto LABEL; \ | |
1979 | } \ | |
35d965d5 | 1980 | } \ |
f1008e52 RE |
1981 | while (0) |
1982 | ||
1983 | /* Jump to LABEL if X is a valid address RTX. This must take | |
1984 | REG_OK_STRICT into account when deciding about valid registers. | |
1985 | ||
1986 | Allow REG, REG+REG, REG+INDEX, INDEX+REG, REG-INDEX, and non | |
1987 | floating SYMBOL_REF to the constant pool. Allow REG-only and | |
1988 | AUTINC-REG if handling TImode or HImode. Other symbol refs must be | |
1989 | forced though a static cell to ensure addressability. */ | |
d19fb8e3 NC |
1990 | #define ARM_GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \ |
1991 | { \ | |
1992 | if (ARM_BASE_REGISTER_RTX_P (X)) \ | |
1993 | goto LABEL; \ | |
1994 | else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \ | |
1995 | && GET_CODE (XEXP (X, 0)) == REG \ | |
1996 | && ARM_REG_OK_FOR_BASE_P (XEXP (X, 0))) \ | |
1997 | goto LABEL; \ | |
1998 | else if (GET_MODE_SIZE (MODE) >= 4 && reload_completed \ | |
1999 | && (GET_CODE (X) == LABEL_REF \ | |
2000 | || (GET_CODE (X) == CONST \ | |
2001 | && GET_CODE (XEXP ((X), 0)) == PLUS \ | |
2002 | && GET_CODE (XEXP (XEXP ((X), 0), 0)) == LABEL_REF \ | |
2003 | && GET_CODE (XEXP (XEXP ((X), 0), 1)) == CONST_INT)))\ | |
2004 | goto LABEL; \ | |
2005 | else if ((MODE) == TImode) \ | |
2006 | ; \ | |
2007 | else if ((MODE) == DImode || (TARGET_SOFT_FLOAT && (MODE) == DFmode)) \ | |
2008 | { \ | |
2009 | if (GET_CODE (X) == PLUS && ARM_BASE_REGISTER_RTX_P (XEXP (X, 0)) \ | |
2010 | && GET_CODE (XEXP (X, 1)) == CONST_INT) \ | |
2011 | { \ | |
2012 | HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \ | |
2013 | if (val == 4 || val == -4 || val == -8) \ | |
2014 | goto LABEL; \ | |
2015 | } \ | |
2016 | } \ | |
2017 | else if (GET_CODE (X) == PLUS) \ | |
2018 | { \ | |
2019 | rtx xop0 = XEXP (X, 0); \ | |
2020 | rtx xop1 = XEXP (X, 1); \ | |
2021 | \ | |
2022 | if (ARM_BASE_REGISTER_RTX_P (xop0)) \ | |
2023 | ARM_GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop0), xop1, LABEL); \ | |
2024 | else if (ARM_BASE_REGISTER_RTX_P (xop1)) \ | |
2025 | ARM_GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop1), xop0, LABEL); \ | |
2026 | } \ | |
2027 | /* Reload currently can't handle MINUS, so disable this for now */ \ | |
2028 | /* else if (GET_CODE (X) == MINUS) \ | |
2029 | { \ | |
2030 | rtx xop0 = XEXP (X,0); \ | |
2031 | rtx xop1 = XEXP (X,1); \ | |
2032 | \ | |
2033 | if (ARM_BASE_REGISTER_RTX_P (xop0)) \ | |
2034 | ARM_GO_IF_LEGITIMATE_INDEX (MODE, -1, xop1, LABEL); \ | |
2035 | } */ \ | |
2036 | else if (GET_MODE_CLASS (MODE) != MODE_FLOAT \ | |
2037 | && GET_CODE (X) == SYMBOL_REF \ | |
2038 | && CONSTANT_POOL_ADDRESS_P (X) \ | |
2039 | && ! (flag_pic \ | |
2040 | && symbol_mentioned_p (get_pool_constant (X)))) \ | |
2041 | goto LABEL; \ | |
2042 | else if ((GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_DEC) \ | |
2043 | && (GET_MODE_SIZE (MODE) <= 4) \ | |
2044 | && GET_CODE (XEXP (X, 0)) == REG \ | |
2045 | && ARM_REG_OK_FOR_BASE_P (XEXP (X, 0))) \ | |
2046 | goto LABEL; \ | |
35d965d5 | 2047 | } |
d5b7b3ae RE |
2048 | |
2049 | /* ---------------------thumb version----------------------------------*/ | |
f1008e52 | 2050 | #define THUMB_LEGITIMATE_OFFSET(MODE, VAL) \ |
d5b7b3ae RE |
2051 | (GET_MODE_SIZE (MODE) == 1 ? ((unsigned HOST_WIDE_INT) (VAL) < 32) \ |
2052 | : GET_MODE_SIZE (MODE) == 2 ? ((unsigned HOST_WIDE_INT) (VAL) < 64 \ | |
2053 | && ((VAL) & 1) == 0) \ | |
2054 | : ((VAL) >= 0 && ((VAL) + GET_MODE_SIZE (MODE)) <= 128 \ | |
2055 | && ((VAL) & 3) == 0)) | |
2056 | ||
2057 | /* The AP may be eliminated to either the SP or the FP, so we use the | |
2058 | least common denominator, e.g. SImode, and offsets from 0 to 64. */ | |
2059 | ||
2060 | /* ??? Verify whether the above is the right approach. */ | |
2061 | ||
2062 | /* ??? Also, the FP may be eliminated to the SP, so perhaps that | |
2063 | needs special handling also. */ | |
2064 | ||
2065 | /* ??? Look at how the mips16 port solves this problem. It probably uses | |
2066 | better ways to solve some of these problems. */ | |
2067 | ||
2068 | /* Although it is not incorrect, we don't accept QImode and HImode | |
f1008e52 RE |
2069 | addresses based on the frame pointer or arg pointer until the |
2070 | reload pass starts. This is so that eliminating such addresses | |
2071 | into stack based ones won't produce impossible code. */ | |
d5b7b3ae RE |
2072 | #define THUMB_GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \ |
2073 | { \ | |
2074 | /* ??? Not clear if this is right. Experiment. */ \ | |
2075 | if (GET_MODE_SIZE (MODE) < 4 \ | |
2076 | && ! (reload_in_progress || reload_completed) \ | |
2077 | && ( reg_mentioned_p (frame_pointer_rtx, X) \ | |
2078 | || reg_mentioned_p (arg_pointer_rtx, X) \ | |
2079 | || reg_mentioned_p (virtual_incoming_args_rtx, X) \ | |
2080 | || reg_mentioned_p (virtual_outgoing_args_rtx, X) \ | |
2081 | || reg_mentioned_p (virtual_stack_dynamic_rtx, X) \ | |
2082 | || reg_mentioned_p (virtual_stack_vars_rtx, X))) \ | |
2083 | ; \ | |
2084 | /* Accept any base register. SP only in SImode or larger. */ \ | |
f1008e52 RE |
2085 | else if (GET_CODE (X) == REG \ |
2086 | && THUMB_REG_MODE_OK_FOR_BASE_P (X, MODE)) \ | |
d5b7b3ae RE |
2087 | goto WIN; \ |
2088 | /* This is PC relative data before MACHINE_DEPENDENT_REORG runs. */ \ | |
2089 | else if (GET_MODE_SIZE (MODE) >= 4 && CONSTANT_P (X) \ | |
48f6efae NC |
2090 | && GET_CODE (X) == SYMBOL_REF \ |
2091 | && CONSTANT_POOL_ADDRESS_P (X) && ! flag_pic) \ | |
d5b7b3ae RE |
2092 | goto WIN; \ |
2093 | /* This is PC relative data after MACHINE_DEPENDENT_REORG runs. */ \ | |
2094 | else if (GET_MODE_SIZE (MODE) >= 4 && reload_completed \ | |
2095 | && (GET_CODE (X) == LABEL_REF \ | |
2096 | || (GET_CODE (X) == CONST \ | |
2097 | && GET_CODE (XEXP (X, 0)) == PLUS \ | |
2098 | && GET_CODE (XEXP (XEXP (X, 0), 0)) == LABEL_REF \ | |
2099 | && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT))) \ | |
2100 | goto WIN; \ | |
2101 | /* Post-inc indexing only supported for SImode and larger. */ \ | |
2102 | else if (GET_CODE (X) == POST_INC && GET_MODE_SIZE (MODE) >= 4 \ | |
2103 | && GET_CODE (XEXP (X, 0)) == REG \ | |
f1008e52 | 2104 | && THUMB_REG_OK_FOR_INDEX_P (XEXP (X, 0))) \ |
d5b7b3ae RE |
2105 | goto WIN; \ |
2106 | else if (GET_CODE (X) == PLUS) \ | |
2107 | { \ | |
2108 | /* REG+REG address can be any two index registers. */ \ | |
2109 | /* We disallow FRAME+REG addressing since we know that FRAME \ | |
2110 | will be replaced with STACK, and SP relative addressing only \ | |
2111 | permits SP+OFFSET. */ \ | |
2112 | if (GET_MODE_SIZE (MODE) <= 4 \ | |
2113 | && GET_CODE (XEXP (X, 0)) == REG \ | |
2114 | && GET_CODE (XEXP (X, 1)) == REG \ | |
2115 | && XEXP (X, 0) != frame_pointer_rtx \ | |
2116 | && XEXP (X, 1) != frame_pointer_rtx \ | |
2117 | && XEXP (X, 0) != virtual_stack_vars_rtx \ | |
2118 | && XEXP (X, 1) != virtual_stack_vars_rtx \ | |
f1008e52 RE |
2119 | && THUMB_REG_OK_FOR_INDEX_P (XEXP (X, 0)) \ |
2120 | && THUMB_REG_OK_FOR_INDEX_P (XEXP (X, 1))) \ | |
d5b7b3ae RE |
2121 | goto WIN; \ |
2122 | /* REG+const has 5-7 bit offset for non-SP registers. */ \ | |
2123 | else if (GET_CODE (XEXP (X, 0)) == REG \ | |
f1008e52 | 2124 | && (THUMB_REG_OK_FOR_INDEX_P (XEXP (X, 0)) \ |
d5b7b3ae RE |
2125 | || XEXP (X, 0) == arg_pointer_rtx) \ |
2126 | && GET_CODE (XEXP (X, 1)) == CONST_INT \ | |
f1008e52 | 2127 | && THUMB_LEGITIMATE_OFFSET (MODE, INTVAL (XEXP (X, 1)))) \ |
d5b7b3ae RE |
2128 | goto WIN; \ |
2129 | /* REG+const has 10 bit offset for SP, but only SImode and \ | |
2130 | larger is supported. */ \ | |
2131 | /* ??? Should probably check for DI/DFmode overflow here \ | |
2132 | just like GO_IF_LEGITIMATE_OFFSET does. */ \ | |
2133 | else if (GET_CODE (XEXP (X, 0)) == REG \ | |
2134 | && REGNO (XEXP (X, 0)) == STACK_POINTER_REGNUM \ | |
2135 | && GET_MODE_SIZE (MODE) >= 4 \ | |
2136 | && GET_CODE (XEXP (X, 1)) == CONST_INT \ | |
2137 | && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (X, 1)) \ | |
2138 | + GET_MODE_SIZE (MODE)) <= 1024 \ | |
2139 | && (INTVAL (XEXP (X, 1)) & 3) == 0) \ | |
2140 | goto WIN; \ | |
2141 | else if (GET_CODE (XEXP (X, 0)) == REG \ | |
2142 | && REGNO (XEXP (X, 0)) == FRAME_POINTER_REGNUM \ | |
2143 | && GET_MODE_SIZE (MODE) >= 4 \ | |
2144 | && GET_CODE (XEXP (X, 1)) == CONST_INT \ | |
2145 | && (INTVAL (XEXP (X, 1)) & 3) == 0) \ | |
2146 | goto WIN; \ | |
2147 | } \ | |
2148 | else if (GET_MODE_CLASS (MODE) != MODE_FLOAT \ | |
2149 | && GET_CODE (X) == SYMBOL_REF \ | |
2150 | && CONSTANT_POOL_ADDRESS_P (X) \ | |
2151 | && ! (flag_pic \ | |
2152 | && symbol_mentioned_p (get_pool_constant (X)))) \ | |
2153 | goto WIN; \ | |
2154 | } | |
2155 | ||
2156 | /* ------------------------------------------------------------------- */ | |
2157 | #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \ | |
2158 | if (TARGET_ARM) \ | |
2159 | ARM_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN) \ | |
2160 | else /* if (TARGET_THUMB) */ \ | |
2161 | THUMB_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN) | |
2162 | /* ------------------------------------------------------------------- */ | |
35d965d5 RS |
2163 | \f |
2164 | /* Try machine-dependent ways of modifying an illegitimate address | |
2165 | to be legitimate. If we find one, return the new, valid address. | |
2166 | This macro is used in only one place: `memory_address' in explow.c. | |
2167 | ||
2168 | OLDX is the address as it was before break_out_memory_refs was called. | |
2169 | In some cases it is useful to look at this to decide what needs to be done. | |
2170 | ||
2171 | MODE and WIN are passed so that this macro can use | |
2172 | GO_IF_LEGITIMATE_ADDRESS. | |
2173 | ||
2174 | It is always safe for this macro to do nothing. It exists to recognize | |
2175 | opportunities to optimize the output. | |
2176 | ||
2177 | On the ARM, try to convert [REG, #BIGCONST] | |
2178 | into ADD BASE, REG, #UPPERCONST and [BASE, #VALIDCONST], | |
2179 | where VALIDCONST == 0 in case of TImode. */ | |
d5b7b3ae | 2180 | #define ARM_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \ |
3967692c RE |
2181 | { \ |
2182 | if (GET_CODE (X) == PLUS) \ | |
2183 | { \ | |
2184 | rtx xop0 = XEXP (X, 0); \ | |
2185 | rtx xop1 = XEXP (X, 1); \ | |
2186 | \ | |
11c1a207 | 2187 | if (CONSTANT_P (xop0) && ! symbol_mentioned_p (xop0)) \ |
3967692c | 2188 | xop0 = force_reg (SImode, xop0); \ |
11c1a207 | 2189 | if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1)) \ |
3967692c | 2190 | xop1 = force_reg (SImode, xop1); \ |
f1008e52 RE |
2191 | if (ARM_BASE_REGISTER_RTX_P (xop0) \ |
2192 | && GET_CODE (xop1) == CONST_INT) \ | |
3967692c RE |
2193 | { \ |
2194 | HOST_WIDE_INT n, low_n; \ | |
2195 | rtx base_reg, val; \ | |
2196 | n = INTVAL (xop1); \ | |
2197 | \ | |
11c1a207 | 2198 | if (MODE == DImode || (TARGET_SOFT_FLOAT && MODE == DFmode)) \ |
3967692c RE |
2199 | { \ |
2200 | low_n = n & 0x0f; \ | |
2201 | n &= ~0x0f; \ | |
2202 | if (low_n > 4) \ | |
2203 | { \ | |
2204 | n += 16; \ | |
2205 | low_n -= 16; \ | |
2206 | } \ | |
2207 | } \ | |
2208 | else \ | |
2209 | { \ | |
2210 | low_n = ((MODE) == TImode ? 0 \ | |
2211 | : n >= 0 ? (n & 0xfff) : -((-n) & 0xfff)); \ | |
2212 | n -= low_n; \ | |
2213 | } \ | |
2214 | base_reg = gen_reg_rtx (SImode); \ | |
43cffd11 RE |
2215 | val = force_operand (gen_rtx_PLUS (SImode, xop0, \ |
2216 | GEN_INT (n)), NULL_RTX); \ | |
3967692c RE |
2217 | emit_move_insn (base_reg, val); \ |
2218 | (X) = (low_n == 0 ? base_reg \ | |
43cffd11 | 2219 | : gen_rtx_PLUS (SImode, base_reg, GEN_INT (low_n))); \ |
3967692c RE |
2220 | } \ |
2221 | else if (xop0 != XEXP (X, 0) || xop1 != XEXP (x, 1)) \ | |
43cffd11 | 2222 | (X) = gen_rtx_PLUS (SImode, xop0, xop1); \ |
3967692c RE |
2223 | } \ |
2224 | else if (GET_CODE (X) == MINUS) \ | |
2225 | { \ | |
2226 | rtx xop0 = XEXP (X, 0); \ | |
2227 | rtx xop1 = XEXP (X, 1); \ | |
2228 | \ | |
2229 | if (CONSTANT_P (xop0)) \ | |
2230 | xop0 = force_reg (SImode, xop0); \ | |
11c1a207 | 2231 | if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1)) \ |
3967692c RE |
2232 | xop1 = force_reg (SImode, xop1); \ |
2233 | if (xop0 != XEXP (X, 0) || xop1 != XEXP (X, 1)) \ | |
43cffd11 | 2234 | (X) = gen_rtx_MINUS (SImode, xop0, xop1); \ |
3967692c | 2235 | } \ |
7a801826 RE |
2236 | if (flag_pic) \ |
2237 | (X) = legitimize_pic_address (OLDX, MODE, NULL_RTX); \ | |
3967692c RE |
2238 | if (memory_address_p (MODE, X)) \ |
2239 | goto WIN; \ | |
35d965d5 RS |
2240 | } |
2241 | ||
d5b7b3ae RE |
2242 | #define THUMB_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \ |
2243 | if (flag_pic) \ | |
2244 | (X) = legitimize_pic_address (OLDX, MODE, NULL_RTX); | |
2245 | ||
2246 | #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \ | |
2247 | if (TARGET_ARM) \ | |
2248 | ARM_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN) \ | |
2249 | else \ | |
2250 | THUMB_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN) | |
2251 | ||
35d965d5 RS |
2252 | /* Go to LABEL if ADDR (a legitimate address expression) |
2253 | has an effect that depends on the machine mode it is used for. */ | |
d5b7b3ae | 2254 | #define ARM_GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \ |
35d965d5 | 2255 | { \ |
d5b7b3ae RE |
2256 | if ( GET_CODE (ADDR) == PRE_DEC || GET_CODE (ADDR) == POST_DEC \ |
2257 | || GET_CODE (ADDR) == PRE_INC || GET_CODE (ADDR) == POST_INC) \ | |
35d965d5 RS |
2258 | goto LABEL; \ |
2259 | } | |
d5b7b3ae RE |
2260 | |
2261 | /* Nothing helpful to do for the Thumb */ | |
2262 | #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \ | |
2263 | if (TARGET_ARM) \ | |
2264 | ARM_GO_IF_MODE_DEPENDENT_ADDRESS (ADDR, LABEL) | |
35d965d5 | 2265 | \f |
d5b7b3ae | 2266 | |
35d965d5 RS |
2267 | /* Specify the machine mode that this machine uses |
2268 | for the index in the tablejump instruction. */ | |
d5b7b3ae | 2269 | #define CASE_VECTOR_MODE Pmode |
35d965d5 | 2270 | |
18543a22 ILT |
2271 | /* Define as C expression which evaluates to nonzero if the tablejump |
2272 | instruction expects the table to contain offsets from the address of the | |
2273 | table. | |
2274 | Do not define this if the table should contain absolute addresses. */ | |
2275 | /* #define CASE_VECTOR_PC_RELATIVE 1 */ | |
35d965d5 | 2276 | |
ff9940b0 RE |
2277 | /* signed 'char' is most compatible, but RISC OS wants it unsigned. |
2278 | unsigned is probably best, but may break some code. */ | |
2279 | #ifndef DEFAULT_SIGNED_CHAR | |
3967692c | 2280 | #define DEFAULT_SIGNED_CHAR 0 |
35d965d5 RS |
2281 | #endif |
2282 | ||
2283 | /* Don't cse the address of the function being compiled. */ | |
2284 | #define NO_RECURSIVE_FUNCTION_CSE 1 | |
2285 | ||
2286 | /* Max number of bytes we can move from memory to memory | |
d17ce9af TG |
2287 | in one reasonably fast instruction. */ |
2288 | #define MOVE_MAX 4 | |
35d965d5 | 2289 | |
d19fb8e3 NC |
2290 | #undef MOVE_RATIO |
2291 | #define MOVE_RATIO (arm_is_xscale ? 4 : 2) | |
2292 | ||
ff9940b0 RE |
2293 | /* Define if operations between registers always perform the operation |
2294 | on the full register even if a narrower mode is specified. */ | |
2295 | #define WORD_REGISTER_OPERATIONS | |
2296 | ||
2297 | /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD | |
2298 | will either zero-extend or sign-extend. The value of this macro should | |
2299 | be the code that says which one of the two operations is implicitly | |
2300 | done, NIL if none. */ | |
9c872872 | 2301 | #define LOAD_EXTEND_OP(MODE) \ |
d5b7b3ae RE |
2302 | (TARGET_THUMB ? ZERO_EXTEND : \ |
2303 | ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \ | |
2304 | : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : NIL))) | |
ff9940b0 | 2305 | |
35d965d5 RS |
2306 | /* Nonzero if access to memory by bytes is slow and undesirable. */ |
2307 | #define SLOW_BYTE_ACCESS 0 | |
2308 | ||
d5b7b3ae RE |
2309 | #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1 |
2310 | ||
35d965d5 RS |
2311 | /* Immediate shift counts are truncated by the output routines (or was it |
2312 | the assembler?). Shift counts in a register are truncated by ARM. Note | |
2313 | that the native compiler puts too large (> 32) immediate shift counts | |
2314 | into a register and shifts by the register, letting the ARM decide what | |
2315 | to do instead of doing that itself. */ | |
ff9940b0 RE |
2316 | /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that |
2317 | code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y). | |
2318 | On the arm, Y in a register is used modulo 256 for the shift. Only for | |
2319 | rotates is modulo 32 used. */ | |
2320 | /* #define SHIFT_COUNT_TRUNCATED 1 */ | |
35d965d5 | 2321 | |
35d965d5 | 2322 | /* All integers have the same format so truncation is easy. */ |
d5b7b3ae | 2323 | #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 |
35d965d5 RS |
2324 | |
2325 | /* Calling from registers is a massive pain. */ | |
2326 | #define NO_FUNCTION_CSE 1 | |
2327 | ||
2328 | /* Chars and shorts should be passed as ints. */ | |
2329 | #define PROMOTE_PROTOTYPES 1 | |
2330 | ||
35d965d5 RS |
2331 | /* The machine modes of pointers and functions */ |
2332 | #define Pmode SImode | |
2333 | #define FUNCTION_MODE Pmode | |
2334 | ||
d5b7b3ae RE |
2335 | #define ARM_FRAME_RTX(X) \ |
2336 | ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \ | |
3967692c RE |
2337 | || (X) == arg_pointer_rtx) |
2338 | ||
62b10bbc | 2339 | #define DEFAULT_RTX_COSTS(X, CODE, OUTER_CODE) \ |
d5b7b3ae | 2340 | return arm_rtx_costs (X, CODE, OUTER_CODE); |
ff9940b0 RE |
2341 | |
2342 | /* Moves to and from memory are quite expensive */ | |
d5b7b3ae RE |
2343 | #define MEMORY_MOVE_COST(M, CLASS, IN) \ |
2344 | (TARGET_ARM ? 10 : \ | |
2345 | ((GET_MODE_SIZE (M) < 4 ? 8 : 2 * GET_MODE_SIZE (M)) \ | |
2346 | * (CLASS == LO_REGS ? 1 : 2))) | |
2347 | ||
3967692c | 2348 | /* All address computations that can be done are free, but rtx cost returns |
ddd5a7c1 | 2349 | the same for practically all of them. So we weight the different types |
3967692c RE |
2350 | of address here in the order (most pref first): |
2351 | PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */ | |
d5b7b3ae | 2352 | #define ARM_ADDRESS_COST(X) \ |
3967692c RE |
2353 | (10 - ((GET_CODE (X) == MEM || GET_CODE (X) == LABEL_REF \ |
2354 | || GET_CODE (X) == SYMBOL_REF) \ | |
2355 | ? 0 \ | |
2356 | : ((GET_CODE (X) == PRE_INC || GET_CODE (X) == PRE_DEC \ | |
2357 | || GET_CODE (X) == POST_INC || GET_CODE (X) == POST_DEC) \ | |
2358 | ? 10 \ | |
2359 | : (((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS) \ | |
2360 | ? 6 + (GET_CODE (XEXP (X, 1)) == CONST_INT ? 2 \ | |
2361 | : ((GET_RTX_CLASS (GET_CODE (XEXP (X, 0))) == '2' \ | |
2362 | || GET_RTX_CLASS (GET_CODE (XEXP (X, 0))) == 'c' \ | |
2363 | || GET_RTX_CLASS (GET_CODE (XEXP (X, 1))) == '2' \ | |
2364 | || GET_RTX_CLASS (GET_CODE (XEXP (X, 1))) == 'c') \ | |
2365 | ? 1 : 0)) \ | |
2366 | : 4))))) | |
d5b7b3ae RE |
2367 | |
2368 | #define THUMB_ADDRESS_COST(X) \ | |
2369 | ((GET_CODE (X) == REG \ | |
2370 | || (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == REG \ | |
2371 | && GET_CODE (XEXP (X, 1)) == CONST_INT)) \ | |
2372 | ? 1 : 2) | |
2373 | ||
2374 | #define ADDRESS_COST(X) \ | |
2375 | (TARGET_ARM ? ARM_ADDRESS_COST (X) : THUMB_ADDRESS_COST (X)) | |
2376 | ||
ff9940b0 RE |
2377 | /* Try to generate sequences that don't involve branches, we can then use |
2378 | conditional instructions */ | |
d5b7b3ae RE |
2379 | #define BRANCH_COST \ |
2380 | (TARGET_ARM ? 4 : (optimize > 1 ? 1 : 0)) | |
7a801826 RE |
2381 | \f |
2382 | /* Position Independent Code. */ | |
2383 | /* We decide which register to use based on the compilation options and | |
2384 | the assembler in use; this is more general than the APCS restriction of | |
2385 | using sb (r9) all the time. */ | |
2386 | extern int arm_pic_register; | |
2387 | ||
ed0e6530 PB |
2388 | /* Used when parsing command line option -mpic-register=. */ |
2389 | extern const char * arm_pic_register_string; | |
2390 | ||
7a801826 RE |
2391 | /* The register number of the register used to address a table of static |
2392 | data addresses in memory. */ | |
2393 | #define PIC_OFFSET_TABLE_REGNUM arm_pic_register | |
2394 | ||
c1163e75 | 2395 | #define FINALIZE_PIC arm_finalize_pic (1) |
7a801826 | 2396 | |
f5a1b0d2 NC |
2397 | /* We can't directly access anything that contains a symbol, |
2398 | nor can we indirect via the constant pool. */ | |
82e9d970 PB |
2399 | #define LEGITIMATE_PIC_OPERAND_P(X) \ |
2400 | ( ! symbol_mentioned_p (X) \ | |
2401 | && ! label_mentioned_p (X) \ | |
2402 | && (! CONSTANT_POOL_ADDRESS_P (X) \ | |
c27ba912 DM |
2403 | || ( ! symbol_mentioned_p (get_pool_constant (X)) \ |
2404 | && ! label_mentioned_p (get_pool_constant (X))))) | |
13bd191d PB |
2405 | |
2406 | /* We need to know when we are making a constant pool; this determines | |
2407 | whether data needs to be in the GOT or can be referenced via a GOT | |
2408 | offset. */ | |
2409 | extern int making_const_table; | |
82e9d970 | 2410 | \f |
c27ba912 | 2411 | /* Handle pragmas for compatibility with Intel's compilers. */ |
8b97c5f8 ZW |
2412 | #define REGISTER_TARGET_PRAGMAS(PFILE) do { \ |
2413 | cpp_register_pragma (PFILE, 0, "long_calls", arm_pr_long_calls); \ | |
2414 | cpp_register_pragma (PFILE, 0, "no_long_calls", arm_pr_no_long_calls); \ | |
2415 | cpp_register_pragma (PFILE, 0, "long_calls_off", arm_pr_long_calls_off); \ | |
2416 | } while (0) | |
2417 | ||
ff9940b0 RE |
2418 | /* Condition code information. */ |
2419 | /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, | |
a5381466 | 2420 | return the mode to be used for the comparison. */ |
d5b7b3ae RE |
2421 | |
2422 | #define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y) | |
ff9940b0 | 2423 | |
008cf58a RE |
2424 | #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode) |
2425 | ||
62b10bbc NC |
2426 | #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \ |
2427 | do \ | |
2428 | { \ | |
2429 | if (GET_CODE (OP1) == CONST_INT \ | |
2430 | && ! (const_ok_for_arm (INTVAL (OP1)) \ | |
2431 | || (const_ok_for_arm (- INTVAL (OP1))))) \ | |
2432 | { \ | |
2433 | rtx const_op = OP1; \ | |
2434 | CODE = arm_canonicalize_comparison ((CODE), &const_op); \ | |
2435 | OP1 = const_op; \ | |
2436 | } \ | |
2437 | } \ | |
2438 | while (0) | |
62dd06ea | 2439 | |
ff9940b0 RE |
2440 | #define STORE_FLAG_VALUE 1 |
2441 | ||
35d965d5 | 2442 | \f |
35d965d5 | 2443 | |
11c1a207 RE |
2444 | /* Gcc puts the pool in the wrong place for ARM, since we can only |
2445 | load addresses a limited distance around the pc. We do some | |
2446 | special munging to move the constant pool values to the correct | |
2447 | point in the code. */ | |
d5b7b3ae RE |
2448 | #define MACHINE_DEPENDENT_REORG(INSN) \ |
2449 | arm_reorg (INSN); \ | |
2450 | ||
2451 | #undef ASM_APP_OFF | |
2452 | #define ASM_APP_OFF (TARGET_THUMB ? "\t.code\t16\n" : "") | |
35d965d5 | 2453 | |
35d965d5 | 2454 | /* Output an internal label definition. */ |
b355a481 | 2455 | #ifndef ASM_OUTPUT_INTERNAL_LABEL |
62b10bbc NC |
2456 | #define ASM_OUTPUT_INTERNAL_LABEL(STREAM, PREFIX, NUM) \ |
2457 | do \ | |
2458 | { \ | |
2a5307b1 | 2459 | char * s = (char *) alloca (40 + strlen (PREFIX)); \ |
62b10bbc NC |
2460 | \ |
2461 | if (arm_ccfsm_state == 3 && arm_target_label == (NUM) \ | |
2462 | && !strcmp (PREFIX, "L")) \ | |
18543a22 | 2463 | { \ |
62b10bbc | 2464 | arm_ccfsm_state = 0; \ |
18543a22 ILT |
2465 | arm_target_insn = NULL; \ |
2466 | } \ | |
62b10bbc NC |
2467 | ASM_GENERATE_INTERNAL_LABEL (s, (PREFIX), (NUM)); \ |
2468 | ASM_OUTPUT_LABEL (STREAM, s); \ | |
2469 | } \ | |
2470 | while (0) | |
b355a481 | 2471 | #endif |
2a5307b1 | 2472 | |
35d965d5 | 2473 | /* Output a push or a pop instruction (only used when profiling). */ |
d5b7b3ae RE |
2474 | #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \ |
2475 | if (TARGET_ARM) \ | |
2476 | asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", \ | |
2477 | STACK_POINTER_REGNUM, REGNO); \ | |
2478 | else \ | |
2479 | asm_fprintf (STREAM, "\tpush {%r}\n", REGNO) | |
2480 | ||
2481 | ||
2482 | #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \ | |
2483 | if (TARGET_ARM) \ | |
2484 | asm_fprintf (STREAM, "\tldmfd\t%r!,{%r}\n", \ | |
2485 | STACK_POINTER_REGNUM, REGNO); \ | |
2486 | else \ | |
2487 | asm_fprintf (STREAM, "\tpop {%r}\n", REGNO) | |
2488 | ||
2489 | /* This is how to output a label which precedes a jumptable. Since | |
2490 | Thumb instructions are 2 bytes, we may need explicit alignment here. */ | |
be393ecf | 2491 | #undef ASM_OUTPUT_CASE_LABEL |
d5b7b3ae RE |
2492 | #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, JUMPTABLE) \ |
2493 | do \ | |
2494 | { \ | |
2495 | if (TARGET_THUMB) \ | |
2496 | ASM_OUTPUT_ALIGN (FILE, 2); \ | |
2497 | ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM); \ | |
2498 | } \ | |
2499 | while (0) | |
35d965d5 | 2500 | |
6cfc7210 NC |
2501 | #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \ |
2502 | do \ | |
2503 | { \ | |
d5b7b3ae RE |
2504 | if (TARGET_THUMB) \ |
2505 | { \ | |
2506 | if (is_called_in_ARM_mode (DECL)) \ | |
2507 | fprintf (STREAM, "\t.code 32\n") ; \ | |
2508 | else \ | |
2509 | fprintf (STREAM, "\t.thumb_func\n") ; \ | |
2510 | } \ | |
6cfc7210 | 2511 | if (TARGET_POKE_FUNCTION_NAME) \ |
6354dc9b | 2512 | arm_poke_function_name (STREAM, (char *) NAME); \ |
6cfc7210 NC |
2513 | } \ |
2514 | while (0) | |
35d965d5 | 2515 | |
d5b7b3ae RE |
2516 | /* For aliases of functions we use .thumb_set instead. */ |
2517 | #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \ | |
2518 | do \ | |
2519 | { \ | |
91ea4f8d KG |
2520 | const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \ |
2521 | const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \ | |
d5b7b3ae RE |
2522 | \ |
2523 | if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \ | |
2524 | { \ | |
2525 | fprintf (FILE, "\t.thumb_set "); \ | |
2526 | assemble_name (FILE, LABEL1); \ | |
2527 | fprintf (FILE, ","); \ | |
2528 | assemble_name (FILE, LABEL2); \ | |
2529 | fprintf (FILE, "\n"); \ | |
2530 | } \ | |
2531 | else \ | |
2532 | ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \ | |
2533 | } \ | |
2534 | while (0) | |
2535 | ||
fdc2d3b0 NC |
2536 | #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN |
2537 | /* To support -falign-* switches we need to use .p2align so | |
2538 | that alignment directives in code sections will be padded | |
2539 | with no-op instructions, rather than zeroes. */ | |
2540 | #define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE,LOG,MAX_SKIP) \ | |
2541 | if ((LOG) != 0) \ | |
2542 | { \ | |
2543 | if ((MAX_SKIP) == 0) \ | |
2544 | fprintf ((FILE), "\t.p2align %d\n", (LOG)); \ | |
2545 | else \ | |
2546 | fprintf ((FILE), "\t.p2align %d,,%d\n", \ | |
2547 | (LOG), (MAX_SKIP)); \ | |
2548 | } | |
2549 | #endif | |
35d965d5 | 2550 | \f |
35d965d5 RS |
2551 | /* Only perform branch elimination (by making instructions conditional) if |
2552 | we're optimising. Otherwise it's of no use anyway. */ | |
d5b7b3ae RE |
2553 | #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \ |
2554 | if (TARGET_ARM && optimize) \ | |
2555 | arm_final_prescan_insn (INSN); \ | |
2556 | else if (TARGET_THUMB) \ | |
2557 | thumb_final_prescan_insn (INSN) | |
35d965d5 | 2558 | |
7bc7696c | 2559 | #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ |
d5b7b3ae RE |
2560 | (CODE == '@' || CODE == '|' \ |
2561 | || (TARGET_ARM && (CODE == '?')) \ | |
2562 | || (TARGET_THUMB && (CODE == '_'))) | |
6cfc7210 | 2563 | |
7bc7696c | 2564 | /* Output an operand of an instruction. */ |
35d965d5 | 2565 | #define PRINT_OPERAND(STREAM, X, CODE) \ |
7bc7696c RE |
2566 | arm_print_operand (STREAM, X, CODE) |
2567 | ||
7b8b8ade NC |
2568 | #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \ |
2569 | (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \ | |
30cf4896 KG |
2570 | : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\ |
2571 | ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \ | |
2572 | ? ((~ (unsigned HOST_WIDE_INT) 0) \ | |
2573 | & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \ | |
7bc7696c | 2574 | : 0)))) |
35d965d5 RS |
2575 | |
2576 | /* Output the address of an operand. */ | |
d5b7b3ae RE |
2577 | #define ARM_PRINT_OPERAND_ADDRESS(STREAM, X) \ |
2578 | { \ | |
2579 | int is_minus = GET_CODE (X) == MINUS; \ | |
2580 | \ | |
2581 | if (GET_CODE (X) == REG) \ | |
2582 | asm_fprintf (STREAM, "[%r, #0]", REGNO (X)); \ | |
2583 | else if (GET_CODE (X) == PLUS || is_minus) \ | |
2584 | { \ | |
2585 | rtx base = XEXP (X, 0); \ | |
2586 | rtx index = XEXP (X, 1); \ | |
2587 | HOST_WIDE_INT offset = 0; \ | |
2588 | if (GET_CODE (base) != REG) \ | |
2589 | { \ | |
2590 | /* Ensure that BASE is a register */ \ | |
2591 | /* (one of them must be). */ \ | |
2592 | rtx temp = base; \ | |
2593 | base = index; \ | |
2594 | index = temp; \ | |
2595 | } \ | |
2596 | switch (GET_CODE (index)) \ | |
2597 | { \ | |
2598 | case CONST_INT: \ | |
2599 | offset = INTVAL (index); \ | |
2600 | if (is_minus) \ | |
2601 | offset = -offset; \ | |
2602 | asm_fprintf (STREAM, "[%r, #%d]", \ | |
2603 | REGNO (base), offset); \ | |
2604 | break; \ | |
2605 | \ | |
2606 | case REG: \ | |
2607 | asm_fprintf (STREAM, "[%r, %s%r]", \ | |
2608 | REGNO (base), is_minus ? "-" : "", \ | |
2609 | REGNO (index)); \ | |
2610 | break; \ | |
2611 | \ | |
2612 | case MULT: \ | |
2613 | case ASHIFTRT: \ | |
2614 | case LSHIFTRT: \ | |
2615 | case ASHIFT: \ | |
2616 | case ROTATERT: \ | |
2617 | { \ | |
2618 | asm_fprintf (STREAM, "[%r, %s%r", \ | |
2619 | REGNO (base), is_minus ? "-" : "", \ | |
2620 | REGNO (XEXP (index, 0))); \ | |
2621 | arm_print_operand (STREAM, index, 'S'); \ | |
2622 | fputs ("]", STREAM); \ | |
2623 | break; \ | |
2624 | } \ | |
2625 | \ | |
2626 | default: \ | |
2627 | abort(); \ | |
2628 | } \ | |
2629 | } \ | |
2630 | else if ( GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC\ | |
2631 | || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC)\ | |
2632 | { \ | |
2633 | extern int output_memory_reference_mode; \ | |
2634 | \ | |
2635 | if (GET_CODE (XEXP (X, 0)) != REG) \ | |
2636 | abort (); \ | |
2637 | \ | |
2638 | if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \ | |
2639 | asm_fprintf (STREAM, "[%r, #%s%d]!", \ | |
2640 | REGNO (XEXP (X, 0)), \ | |
2641 | GET_CODE (X) == PRE_DEC ? "-" : "", \ | |
2642 | GET_MODE_SIZE (output_memory_reference_mode));\ | |
2643 | else \ | |
2644 | asm_fprintf (STREAM, "[%r], #%s%d", \ | |
2645 | REGNO (XEXP (X, 0)), \ | |
2646 | GET_CODE (X) == POST_DEC ? "-" : "", \ | |
2647 | GET_MODE_SIZE (output_memory_reference_mode));\ | |
2648 | } \ | |
2649 | else output_addr_const (STREAM, X); \ | |
35d965d5 | 2650 | } |
62dd06ea | 2651 | |
d5b7b3ae RE |
2652 | #define THUMB_PRINT_OPERAND_ADDRESS(STREAM, X) \ |
2653 | { \ | |
2654 | if (GET_CODE (X) == REG) \ | |
2655 | asm_fprintf (STREAM, "[%r]", REGNO (X)); \ | |
2656 | else if (GET_CODE (X) == POST_INC) \ | |
2657 | asm_fprintf (STREAM, "%r!", REGNO (XEXP (X, 0))); \ | |
2658 | else if (GET_CODE (X) == PLUS) \ | |
2659 | { \ | |
2660 | if (GET_CODE (XEXP (X, 1)) == CONST_INT) \ | |
2661 | asm_fprintf (STREAM, "[%r, #%d]", \ | |
2662 | REGNO (XEXP (X, 0)), \ | |
2663 | (int) INTVAL (XEXP (X, 1))); \ | |
2664 | else \ | |
2665 | asm_fprintf (STREAM, "[%r, %r]", \ | |
2666 | REGNO (XEXP (X, 0)), \ | |
2667 | REGNO (XEXP (X, 1))); \ | |
2668 | } \ | |
2669 | else \ | |
2670 | output_addr_const (STREAM, X); \ | |
2671 | } | |
2672 | ||
2673 | #define PRINT_OPERAND_ADDRESS(STREAM, X) \ | |
2674 | if (TARGET_ARM) \ | |
2675 | ARM_PRINT_OPERAND_ADDRESS (STREAM, X) \ | |
2676 | else \ | |
2677 | THUMB_PRINT_OPERAND_ADDRESS (STREAM, X) | |
2678 | ||
62dd06ea RE |
2679 | /* Output code to add DELTA to the first argument, and then jump to FUNCTION. |
2680 | Used for C++ multiple inheritance. */ | |
62b10bbc NC |
2681 | #define ASM_OUTPUT_MI_THUNK(FILE, THUNK_FNDECL, DELTA, FUNCTION) \ |
2682 | do \ | |
2683 | { \ | |
2684 | int mi_delta = (DELTA); \ | |
27c38fbe | 2685 | const char *const mi_op = mi_delta < 0 ? "sub" : "add"; \ |
62b10bbc NC |
2686 | int shift = 0; \ |
2687 | int this_regno = (aggregate_value_p (TREE_TYPE (TREE_TYPE (FUNCTION))) \ | |
2688 | ? 1 : 0); \ | |
b1801c02 NC |
2689 | if (mi_delta < 0) \ |
2690 | mi_delta = - mi_delta; \ | |
62b10bbc NC |
2691 | while (mi_delta != 0) \ |
2692 | { \ | |
b1801c02 | 2693 | if ((mi_delta & (3 << shift)) == 0) \ |
62b10bbc NC |
2694 | shift += 2; \ |
2695 | else \ | |
2696 | { \ | |
dd18ae56 NC |
2697 | asm_fprintf (FILE, "\t%s\t%r, %r, #%d\n", \ |
2698 | mi_op, this_regno, this_regno, \ | |
6cfc7210 | 2699 | mi_delta & (0xff << shift)); \ |
62b10bbc NC |
2700 | mi_delta &= ~(0xff << shift); \ |
2701 | shift += 8; \ | |
2702 | } \ | |
2703 | } \ | |
2704 | fputs ("\tb\t", FILE); \ | |
2705 | assemble_name (FILE, XSTR (XEXP (DECL_RTL (FUNCTION), 0), 0)); \ | |
dd18ae56 | 2706 | if (NEED_PLT_RELOC) \ |
62b10bbc NC |
2707 | fputs ("(PLT)", FILE); \ |
2708 | fputc ('\n', FILE); \ | |
2709 | } \ | |
2710 | while (0) | |
39950dff | 2711 | |
6a5d7526 MS |
2712 | /* A C expression whose value is RTL representing the value of the return |
2713 | address for the frame COUNT steps up from the current frame. */ | |
2714 | ||
d5b7b3ae RE |
2715 | #define RETURN_ADDR_RTX(COUNT, FRAME) \ |
2716 | arm_return_addr (COUNT, FRAME) | |
2717 | ||
2718 | /* Mask of the bits in the PC that contain the real return address | |
2719 | when running in 26-bit mode. */ | |
2720 | #define RETURN_ADDR_MASK26 (0x03fffffc) | |
6a5d7526 | 2721 | |
2c849145 JM |
2722 | /* Pick up the return address upon entry to a procedure. Used for |
2723 | dwarf2 unwind information. This also enables the table driven | |
2724 | mechanism. */ | |
2c849145 JM |
2725 | #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM) |
2726 | #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM) | |
2727 | ||
39950dff MS |
2728 | /* Used to mask out junk bits from the return address, such as |
2729 | processor state, interrupt status, condition codes and the like. */ | |
2730 | #define MASK_RETURN_ADDR \ | |
2731 | /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \ | |
2732 | in 26 bit mode, the condition codes must be masked out of the \ | |
2733 | return address. This does not apply to ARM6 and later processors \ | |
2734 | when running in 32 bit mode. */ \ | |
d5b7b3ae RE |
2735 | ((!TARGET_APCS_32) ? (GEN_INT (RETURN_ADDR_MASK26)) \ |
2736 | : (GEN_INT ((unsigned long)0xffffffff))) | |
2737 | ||
2738 | \f | |
2739 | /* Define the codes that are matched by predicates in arm.c */ | |
2740 | #define PREDICATE_CODES \ | |
2741 | {"s_register_operand", {SUBREG, REG}}, \ | |
b15bca31 | 2742 | {"arm_hard_register_operand", {REG}}, \ |
d5b7b3ae RE |
2743 | {"f_register_operand", {SUBREG, REG}}, \ |
2744 | {"arm_add_operand", {SUBREG, REG, CONST_INT}}, \ | |
2745 | {"fpu_add_operand", {SUBREG, REG, CONST_DOUBLE}}, \ | |
2746 | {"fpu_rhs_operand", {SUBREG, REG, CONST_DOUBLE}}, \ | |
2747 | {"arm_rhs_operand", {SUBREG, REG, CONST_INT}}, \ | |
2748 | {"arm_not_operand", {SUBREG, REG, CONST_INT}}, \ | |
2749 | {"reg_or_int_operand", {SUBREG, REG, CONST_INT}}, \ | |
2750 | {"index_operand", {SUBREG, REG, CONST_INT}}, \ | |
2751 | {"thumb_cmp_operand", {SUBREG, REG, CONST_INT}}, \ | |
2752 | {"offsettable_memory_operand", {MEM}}, \ | |
2753 | {"bad_signed_byte_operand", {MEM}}, \ | |
2754 | {"alignable_memory_operand", {MEM}}, \ | |
2755 | {"shiftable_operator", {PLUS, MINUS, AND, IOR, XOR}}, \ | |
2756 | {"minmax_operator", {SMIN, SMAX, UMIN, UMAX}}, \ | |
2757 | {"shift_operator", {ASHIFT, ASHIFTRT, LSHIFTRT, ROTATERT, MULT}}, \ | |
2758 | {"di_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE, MEM}}, \ | |
2759 | {"nonimmediate_di_operand", {SUBREG, REG, MEM}}, \ | |
2760 | {"soft_df_operand", {SUBREG, REG, CONST_DOUBLE, MEM}}, \ | |
2761 | {"nonimmediate_soft_df_operand", {SUBREG, REG, MEM}}, \ | |
2762 | {"load_multiple_operation", {PARALLEL}}, \ | |
2763 | {"store_multiple_operation", {PARALLEL}}, \ | |
2764 | {"equality_operator", {EQ, NE}}, \ | |
e45b72c4 RE |
2765 | {"arm_comparison_operator", {EQ, NE, LE, LT, GE, GT, GEU, GTU, LEU, \ |
2766 | LTU, UNORDERED, ORDERED, UNLT, UNLE, \ | |
2767 | UNGE, UNGT}}, \ | |
d5b7b3ae RE |
2768 | {"arm_rhsm_operand", {SUBREG, REG, CONST_INT, MEM}}, \ |
2769 | {"const_shift_operand", {CONST_INT}}, \ | |
2770 | {"multi_register_push", {PARALLEL}}, \ | |
2771 | {"cc_register", {REG}}, \ | |
2772 | {"logical_binary_operator", {AND, IOR, XOR}}, \ | |
2773 | {"dominant_cc_register", {REG}}, | |
71791e16 | 2774 | |
ad027eae RE |
2775 | /* Define this if you have special predicates that know special things |
2776 | about modes. Genrecog will warn about certain forms of | |
2777 | match_operand without a mode; if the operand predicate is listed in | |
2778 | SPECIAL_MODE_PREDICATES, the warning will be suppressed. */ | |
2779 | #define SPECIAL_MODE_PREDICATES \ | |
2780 | "cc_register", "dominant_cc_register", | |
2781 | ||
d19fb8e3 NC |
2782 | enum arm_builtins |
2783 | { | |
2784 | ARM_BUILTIN_CLZ, | |
d19fb8e3 NC |
2785 | ARM_BUILTIN_MAX |
2786 | }; | |
88657302 | 2787 | #endif /* ! GCC_ARM_H */ |