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f5a1b0d2 1/* Definitions of target machine for GNU compiler, for ARM.
d1e082c2 2 Copyright (C) 1991-2013 Free Software Foundation, Inc.
35d965d5 3 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
8b109b37 4 and Martin Simmons (@harleqn.co.uk).
949d79eb 5 More major hacks by Richard Earnshaw (rearnsha@arm.com)
6cfc7210
NC		 6 Minor hacks by Nick Clifton (nickc@cygnus.com)
7
4f448245 8 This file is part of GCC.
35d965d5 9
4f448245
NC		 10 GCC is free software; you can redistribute it and/or modify it
11 under the terms of the GNU General Public License as published
2f83c7d6 12 by the Free Software Foundation; either version 3, or (at your
4f448245 13 option) any later version.
35d965d5 14
4f448245
NC		 15 GCC is distributed in the hope that it will be useful, but WITHOUT
16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
18 License for more details.
35d965d5 19
4f448245 20 You should have received a copy of the GNU General Public License
2f83c7d6
NC		 21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
35d965d5 23
88657302
RH		 24#ifndef GCC_ARM_H
25#define GCC_ARM_H
b355a481 26
46107b99
RE		 27/* We can't use enum machine_mode inside a generator file because it
28 hasn't been created yet; we shouldn't be using any code that
29 needs the real definition though, so this ought to be safe. */
30#ifdef GENERATOR_FILE
31#define MACHMODE int
32#else
33#include "insn-modes.h"
34#define MACHMODE enum machine_mode
35#endif
36
9403b7f7
RS		 37#include "config/vxworks-dummy.h"
38
35fd3193 39/* The architecture define. */
78011587
PB		 40extern char arm_arch_name[];
41
e6471be6
NB		 42/* Target CPU builtins. */
43#define TARGET_CPU_CPP_BUILTINS() \
44 do \
45 { \
c884924f
JG		 46 if (TARGET_DSP_MULTIPLY) \
47 builtin_define ("__ARM_FEATURE_DSP"); \
9e94a7fc
MGD		 48 if (TARGET_ARM_QBIT) \
49 builtin_define ("__ARM_FEATURE_QBIT"); \
50 if (TARGET_ARM_SAT) \
51 builtin_define ("__ARM_FEATURE_SAT"); \
5d248b41
JG		 52 if (unaligned_access) \
53 builtin_define ("__ARM_FEATURE_UNALIGNED"); \
9e94a7fc
MGD		 54 if (TARGET_ARM_FEATURE_LDREX) \
55 builtin_define_with_int_value ( \
56 "__ARM_FEATURE_LDREX", TARGET_ARM_FEATURE_LDREX); \
57 if ((TARGET_ARM_ARCH >= 5 && !TARGET_THUMB) \
58 || TARGET_ARM_ARCH_ISA_THUMB >=2) \
59 builtin_define ("__ARM_FEATURE_CLZ"); \
60 if (TARGET_INT_SIMD) \
61 builtin_define ("__ARM_FEATURE_SIMD32"); \
62 \
63 builtin_define_with_int_value ( \
64 "__ARM_SIZEOF_MINIMAL_ENUM", \
65 flag_short_enums ? 1 : 4); \
66 builtin_define_with_int_value ( \
67 "__ARM_SIZEOF_WCHAR_T", WCHAR_TYPE_SIZE); \
68 if (TARGET_ARM_ARCH_PROFILE) \
69 builtin_define_with_int_value ( \
70 "__ARM_ARCH_PROFILE", TARGET_ARM_ARCH_PROFILE); \
71 \
9b66ebb1
PB		 72 /* Define __arm__ even when in thumb mode, for \
73 consistency with armcc. */ \
74 builtin_define ("__arm__"); \
9e94a7fc
MGD		 75 if (TARGET_ARM_ARCH) \
76 builtin_define_with_int_value ( \
77 "__ARM_ARCH", TARGET_ARM_ARCH); \
78 if (arm_arch_notm) \
79 builtin_define ("__ARM_ARCH_ISA_ARM"); \
61f0ccff 80 builtin_define ("__APCS_32__"); \
9b66ebb1 81 if (TARGET_THUMB) \
e6471be6 82 builtin_define ("__thumb__"); \
5b3e6663
PB		 83 if (TARGET_THUMB2) \
84 builtin_define ("__thumb2__"); \
9e94a7fc
MGD		 85 if (TARGET_ARM_ARCH_ISA_THUMB) \
86 builtin_define_with_int_value ( \
87 "__ARM_ARCH_ISA_THUMB", \
88 TARGET_ARM_ARCH_ISA_THUMB); \
e6471be6
NB		 89 \
90 if (TARGET_BIG_END) \
91 { \
92 builtin_define ("__ARMEB__"); \
9e94a7fc 93 builtin_define ("__ARM_BIG_ENDIAN"); \
e6471be6
NB		 94 if (TARGET_THUMB) \
95 builtin_define ("__THUMBEB__"); \
96 if (TARGET_LITTLE_WORDS) \
97 builtin_define ("__ARMWEL__"); \
98 } \
99 else \
100 { \
101 builtin_define ("__ARMEL__"); \
102 if (TARGET_THUMB) \
103 builtin_define ("__THUMBEL__"); \
104 } \
105 \
e6471be6
NB		 106 if (TARGET_SOFT_FLOAT) \
107 builtin_define ("__SOFTFP__"); \
108 \
9b66ebb1 109 if (TARGET_VFP) \
b5b620a4
JT		 110 builtin_define ("__VFP_FP__"); \
111 \
9e94a7fc
MGD		 112 if (TARGET_ARM_FP) \
113 builtin_define_with_int_value ( \
114 "__ARM_FP", TARGET_ARM_FP); \
115 if (arm_fp16_format == ARM_FP16_FORMAT_IEEE) \
116 builtin_define ("__ARM_FP16_FORMAT_IEEE"); \
117 if (arm_fp16_format == ARM_FP16_FORMAT_ALTERNATIVE) \
118 builtin_define ("__ARM_FP16_FORMAT_ALTERNATIVE"); \
119 if (TARGET_FMA) \
120 builtin_define ("__ARM_FEATURE_FMA"); \
121 \
88f77cba 122 if (TARGET_NEON) \
9e94a7fc
MGD		 123 { \
124 builtin_define ("__ARM_NEON__"); \
125 builtin_define ("__ARM_NEON"); \
126 } \
127 if (TARGET_NEON_FP) \
128 builtin_define_with_int_value ( \
129 "__ARM_NEON_FP", TARGET_NEON_FP); \
88f77cba 130 \
e6471be6
NB		 131 /* Add a define for interworking. \
132 Needed when building libgcc.a. */ \
2ad4dcf9 133 if (arm_cpp_interwork) \
e6471be6
NB		 134 builtin_define ("__THUMB_INTERWORK__"); \
135 \
136 builtin_assert ("cpu=arm"); \
137 builtin_assert ("machine=arm"); \
78011587
PB		 138 \
139 builtin_define (arm_arch_name); \
78011587
PB		 140 if (arm_arch_xscale) \
141 builtin_define ("__XSCALE__"); \
142 if (arm_arch_iwmmxt) \
9e94a7fc
MGD		 143 { \
144 builtin_define ("__IWMMXT__"); \
145 builtin_define ("__ARM_WMMX"); \
146 } \
8fd03515
XQ		 147 if (arm_arch_iwmmxt2) \
148 builtin_define ("__IWMMXT2__"); \
4adf3e34 149 if (TARGET_AAPCS_BASED) \
12ffc7d5
CLT		 150 { \
151 if (arm_pcs_default == ARM_PCS_AAPCS_VFP) \
152 builtin_define ("__ARM_PCS_VFP"); \
153 else if (arm_pcs_default == ARM_PCS_AAPCS) \
154 builtin_define ("__ARM_PCS"); \
155 builtin_define ("__ARM_EABI__"); \
156 } \
572070ef
PB		 157 if (TARGET_IDIV) \
158 builtin_define ("__ARM_ARCH_EXT_IDIV__"); \
e6471be6
NB		 159 } while (0)
160
ad7be009 161#include "config/arm/arm-opts.h"
9b66ebb1 162
78011587
PB		 163enum target_cpus
164{
d98a72fd
RE		 165#define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
166 TARGET_CPU_##IDENT,
78011587
PB		 167#include "arm-cores.def"
168#undef ARM_CORE
169 TARGET_CPU_generic
170};
171
9b66ebb1
PB		 172/* The processor for which instructions should be scheduled. */
173extern enum processor_type arm_tune;
174
d5b7b3ae 175typedef enum arm_cond_code
89c7ca52
RE		 176{
177 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC,
178 ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV
d5b7b3ae
RE		 179}
180arm_cc;
6cfc7210 181
d5b7b3ae 182extern arm_cc arm_current_cc;
ff9940b0 183
d5b7b3ae 184#define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1))
89c7ca52 185
b24a2ce5
GY		 186/* The maximaum number of instructions that is beneficial to
187 conditionally execute. */
188#undef MAX_CONDITIONAL_EXECUTE
189#define MAX_CONDITIONAL_EXECUTE arm_max_conditional_execute ()
190
6cfc7210
NC		 191extern int arm_target_label;
192extern int arm_ccfsm_state;
e2500fed 193extern GTY(()) rtx arm_target_insn;
d5b7b3ae 194/* The label of the current constant pool. */
e2500fed 195extern rtx pool_vector_label;
d5b7b3ae 196/* Set to 1 when a return insn is output, this means that the epilogue
d6b4baa4 197 is not needed. */
d5b7b3ae 198extern int return_used_this_function;
b76c3c4b
PB		 199/* Callback to output language specific object attributes. */
200extern void (*arm_lang_output_object_attributes_hook)(void);
35d965d5 201\f
d6b4baa4 202/* Just in case configure has failed to define anything. */
7a801826
RE		 203#ifndef TARGET_CPU_DEFAULT
204#define TARGET_CPU_DEFAULT TARGET_CPU_generic
205#endif
206
7a801826 207
5742588d 208#undef CPP_SPEC
78011587 209#define CPP_SPEC "%(subtarget_cpp_spec) \
5e1b4d5a
JM		 210%{mfloat-abi=soft:%{mfloat-abi=hard: \
211 %e-mfloat-abi=soft and -mfloat-abi=hard may not be used together}} \
e6471be6
NB		 212%{mbig-endian:%{mlittle-endian: \
213 %e-mbig-endian and -mlittle-endian may not be used together}}"
7a801826 214
be393ecf 215#ifndef CC1_SPEC
dfa08768 216#define CC1_SPEC ""
be393ecf 217#endif
7a801826
RE		 218
219/* This macro defines names of additional specifications to put in the specs
220 that can be used in various specifications like CC1_SPEC. Its definition
221 is an initializer with a subgrouping for each command option.
222
223 Each subgrouping contains a string constant, that defines the
4f448245 224 specification name, and a string constant that used by the GCC driver
7a801826
RE		 225 program.
226
227 Do not define this macro if it does not need to do anything. */
228#define EXTRA_SPECS \
38fc909b 229 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
54e73f88 230 { "asm_cpu_spec", ASM_CPU_SPEC }, \
7a801826
RE		 231 SUBTARGET_EXTRA_SPECS
232
914a3b8c 233#ifndef SUBTARGET_EXTRA_SPECS
7a801826 234#define SUBTARGET_EXTRA_SPECS
914a3b8c
DM		 235#endif
236
6cfc7210 237#ifndef SUBTARGET_CPP_SPEC
38fc909b 238#define SUBTARGET_CPP_SPEC ""
6cfc7210 239#endif
35d965d5
RS		 240\f
241/* Run-time Target Specification. */
9b66ebb1 242#define TARGET_SOFT_FLOAT (arm_float_abi == ARM_FLOAT_ABI_SOFT)
72cdc543
PB		 243/* Use hardware floating point instructions. */
244#define TARGET_HARD_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT)
245/* Use hardware floating point calling convention. */
246#define TARGET_HARD_FLOAT_ABI (arm_float_abi == ARM_FLOAT_ABI_HARD)
d79f3032 247#define TARGET_VFP (arm_fpu_desc->model == ARM_FP_MODEL_VFP)
5a9335ef 248#define TARGET_IWMMXT (arm_arch_iwmmxt)
8fd03515 249#define TARGET_IWMMXT2 (arm_arch_iwmmxt2)
5b3e6663 250#define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_32BIT)
8fd03515 251#define TARGET_REALLY_IWMMXT2 (TARGET_IWMMXT2 && TARGET_32BIT)
5b3e6663 252#define TARGET_IWMMXT_ABI (TARGET_32BIT && arm_abi == ARM_ABI_IWMMXT)
d5b7b3ae
RE		 253#define TARGET_ARM (! TARGET_THUMB)
254#define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */
c54c7322
RS		 255#define TARGET_BACKTRACE (leaf_function_p () \
256 ? TARGET_TPCS_LEAF_FRAME \
257 : TARGET_TPCS_FRAME)
b6685939
PB		 258#define TARGET_AAPCS_BASED \
259 (arm_abi != ARM_ABI_APCS && arm_abi != ARM_ABI_ATPCS)
3ada8e17 260
d3585b76
DJ		 261#define TARGET_HARD_TP (target_thread_pointer == TP_CP15)
262#define TARGET_SOFT_TP (target_thread_pointer == TP_SOFT)
ccdc2164 263#define TARGET_GNU2_TLS (target_tls_dialect == TLS_GNU2)
d3585b76 264
5b3e6663
PB		 265/* Only 16-bit thumb code. */
266#define TARGET_THUMB1 (TARGET_THUMB && !arm_arch_thumb2)
267/* Arm or Thumb-2 32-bit code. */
268#define TARGET_32BIT (TARGET_ARM || arm_arch_thumb2)
269/* 32-bit Thumb-2 code. */
270#define TARGET_THUMB2 (TARGET_THUMB && arm_arch_thumb2)
bf98ec6c
PB		 271/* Thumb-1 only. */
272#define TARGET_THUMB1_ONLY (TARGET_THUMB1 && !arm_arch_notm)
5b3e6663 273
3383b7fa
GY		 274#define TARGET_LDRD (arm_arch5e && ARM_DOUBLEWORD_ALIGN \
275 && !TARGET_THUMB1)
276
88f77cba 277/* The following two macros concern the ability to execute coprocessor
302c3d8e
PB		 278 instructions for VFPv3 or NEON. TARGET_VFP3/TARGET_VFPD32 are currently
279 only ever tested when we know we are generating for VFP hardware; we need
280 to be more careful with TARGET_NEON as noted below. */
88f77cba 281
302c3d8e 282/* FPU is has the full VFPv3/NEON register file of 32 D registers. */
d79f3032 283#define TARGET_VFPD32 (TARGET_VFP && arm_fpu_desc->regs == VFP_REG_D32)
302c3d8e
PB		 284
285/* FPU supports VFPv3 instructions. */
d79f3032 286#define TARGET_VFP3 (TARGET_VFP && arm_fpu_desc->rev >= 3)
302c3d8e 287
e0dc3601
PB		 288/* FPU only supports VFP single-precision instructions. */
289#define TARGET_VFP_SINGLE (TARGET_VFP && arm_fpu_desc->regs == VFP_REG_SINGLE)
290
291/* FPU supports VFP double-precision instructions. */
292#define TARGET_VFP_DOUBLE (TARGET_VFP && arm_fpu_desc->regs != VFP_REG_SINGLE)
293
294/* FPU supports half-precision floating-point with NEON element load/store. */
d79f3032
PB		 295#define TARGET_NEON_FP16 \
296 (TARGET_VFP && arm_fpu_desc->neon && arm_fpu_desc->fp16)
0fd8c3ad 297
e0dc3601
PB		 298/* FPU supports VFP half-precision floating-point. */
299#define TARGET_FP16 (TARGET_VFP && arm_fpu_desc->fp16)
300
9e94a7fc
MGD		 301/* FPU supports fused-multiply-add operations. */
302#define TARGET_FMA (TARGET_VFP && arm_fpu_desc->rev >= 4)
303
1dd4fe1f
KT		 304/* FPU is ARMv8 compatible. */
305#define TARGET_FPU_ARMV8 (TARGET_VFP && arm_fpu_desc->rev >= 8)
306
595fefee
MGD		 307/* FPU supports Crypto extensions. */
308#define TARGET_CRYPTO (TARGET_VFP && arm_fpu_desc->crypto)
309
88f77cba
JB		 310/* FPU supports Neon instructions. The setting of this macro gets
311 revealed via __ARM_NEON__ so we add extra guards upon TARGET_32BIT
312 and TARGET_HARD_FLOAT to ensure that NEON instructions are
313 available. */
314#define TARGET_NEON (TARGET_32BIT && TARGET_HARD_FLOAT \
d79f3032 315 && TARGET_VFP && arm_fpu_desc->neon)
f1adb0a9 316
9e94a7fc
MGD		 317/* Q-bit is present. */
318#define TARGET_ARM_QBIT \
319 (TARGET_32BIT && arm_arch5e && (arm_arch_notm || arm_arch7))
320/* Saturation operation, e.g. SSAT. */
321#define TARGET_ARM_SAT \
322 (TARGET_32BIT && arm_arch6 && (arm_arch_notm || arm_arch7))
5b3e6663
PB		 323/* "DSP" multiply instructions, eg. SMULxy. */
324#define TARGET_DSP_MULTIPLY \
60bd3528 325 (TARGET_32BIT && arm_arch5e && (arm_arch_notm || arm_arch7em))
5b3e6663
PB		 326/* Integer SIMD instructions, and extend-accumulate instructions. */
327#define TARGET_INT_SIMD \
60bd3528 328 (TARGET_32BIT && arm_arch6 && (arm_arch_notm || arm_arch7em))
5b3e6663 329
571191af 330/* Should MOVW/MOVT be used in preference to a constant pool. */
7ec70105
JB		 331#define TARGET_USE_MOVT \
332 (arm_arch_thumb2 && !optimize_size && !current_tune->prefer_constant_pool)
571191af 333
5b3e6663
PB		 334/* We could use unified syntax for arm mode, but for now we just use it
335 for Thumb-2. */
336#define TARGET_UNIFIED_ASM TARGET_THUMB2
337
029e79eb 338/* Nonzero if this chip provides the DMB instruction. */
9e2a6301 339#define TARGET_HAVE_DMB (arm_arch6m || arm_arch7)
029e79eb
MS		 340
341/* Nonzero if this chip implements a memory barrier via CP15. */
80651d8e
DAG		 342#define TARGET_HAVE_DMB_MCR (arm_arch6 && ! TARGET_HAVE_DMB \
343 && ! TARGET_THUMB1)
029e79eb
MS		 344
345/* Nonzero if this chip implements a memory barrier instruction. */
346#define TARGET_HAVE_MEMORY_BARRIER (TARGET_HAVE_DMB || TARGET_HAVE_DMB_MCR)
347
348/* Nonzero if this chip supports ldrex and strex */
349#define TARGET_HAVE_LDREX ((arm_arch6 && TARGET_ARM) || arm_arch7)
350
cfe52743
DAG		 351/* Nonzero if this chip supports ldrex{bh} and strex{bh}. */
352#define TARGET_HAVE_LDREXBH ((arm_arch6k && TARGET_ARM) || arm_arch7)
353
354/* Nonzero if this chip supports ldrexd and strexd. */
355#define TARGET_HAVE_LDREXD (((arm_arch6k && TARGET_ARM) || arm_arch7) \
356 && arm_arch_notm)
5b3e6663 357
5ad29f12
KT		 358/* Nonzero if this chip supports load-acquire and store-release. */
359#define TARGET_HAVE_LDACQ (TARGET_ARM_ARCH >= 8)
360
572070ef
PB		 361/* Nonzero if integer division instructions supported. */
362#define TARGET_IDIV ((TARGET_ARM && arm_arch_arm_hwdiv) \
363 || (TARGET_THUMB2 && arm_arch_thumb_hwdiv))
364
65074f54
CL		 365/* Should NEON be used for 64-bits bitops. */
366#define TARGET_PREFER_NEON_64BITS (prefer_neon_for_64bits)
367
b3f8d95d
MM		 368/* True iff the full BPABI is being used. If TARGET_BPABI is true,
369 then TARGET_AAPCS_BASED must be true -- but the converse does not
370 hold. TARGET_BPABI implies the use of the BPABI runtime library,
371 etc., in addition to just the AAPCS calling conventions. */
372#ifndef TARGET_BPABI
373#define TARGET_BPABI false
f676971a 374#endif
b3f8d95d 375
7816bea0
DJ		 376/* Support for a compile-time default CPU, et cetera. The rules are:
377 --with-arch is ignored if -march or -mcpu are specified.
378 --with-cpu is ignored if -march or -mcpu are specified, and is overridden
379 by --with-arch.
380 --with-tune is ignored if -mtune or -mcpu are specified (but not affected
381 by -march).
5e1b4d5a 382 --with-float is ignored if -mfloat-abi is specified.
5848830f 383 --with-fpu is ignored if -mfpu is specified.
ccdc2164
NS		 384 --with-abi is ignored if -mabi is specified.
385 --with-tls is ignored if -mtls-dialect is specified. */
7816bea0
DJ		 386#define OPTION_DEFAULT_SPECS \
387 {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \
388 {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \
389 {"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}" }, \
5e1b4d5a 390 {"float", "%{!mfloat-abi=*:-mfloat-abi=%(VALUE)}" }, \
5848830f 391 {"fpu", "%{!mfpu=*:-mfpu=%(VALUE)}"}, \
3cf94279 392 {"abi", "%{!mabi=*:-mabi=%(VALUE)}"}, \
ccdc2164 393 {"mode", "%{!marm:%{!mthumb:-m%(VALUE)}}"}, \
7cf13d1f 394 {"tls", "%{!mtls-dialect=*:-mtls-dialect=%(VALUE)}"},
7816bea0 395
9b66ebb1
PB		 396/* Which floating point model to use. */
397enum arm_fp_model
398{
399 ARM_FP_MODEL_UNKNOWN,
9b66ebb1
PB		 400 /* VFP floating point model. */
401 ARM_FP_MODEL_VFP
402};
403
d79f3032 404enum vfp_reg_type
24f0c1b4 405{
70dd156a 406 VFP_NONE = 0,
d79f3032
PB		 407 VFP_REG_D16,
408 VFP_REG_D32,
409 VFP_REG_SINGLE
24f0c1b4
RE		 410};
411
d79f3032
PB		 412extern const struct arm_fpu_desc
413{
414 const char *name;
415 enum arm_fp_model model;
416 int rev;
417 enum vfp_reg_type regs;
418 int neon;
419 int fp16;
595fefee 420 int crypto;
d79f3032
PB		 421} *arm_fpu_desc;
422
423/* Which floating point hardware to schedule for. */
424extern int arm_fpu_attr;
71791e16 425
3d8532aa
PB		 426#ifndef TARGET_DEFAULT_FLOAT_ABI
427#define TARGET_DEFAULT_FLOAT_ABI ARM_FLOAT_ABI_SOFT
428#endif
429
0fd8c3ad
SL		 430#define LARGEST_EXPONENT_IS_NORMAL(bits) \
431 ((bits) == 16 && arm_fp16_format == ARM_FP16_FORMAT_ALTERNATIVE)
432
5848830f
PB		 433#ifndef ARM_DEFAULT_ABI
434#define ARM_DEFAULT_ABI ARM_ABI_APCS
435#endif
436
9e94a7fc
MGD		 437/* Map each of the micro-architecture variants to their corresponding
438 major architecture revision. */
439
440enum base_architecture
441{
442 BASE_ARCH_0 = 0,
443 BASE_ARCH_2 = 2,
444 BASE_ARCH_3 = 3,
445 BASE_ARCH_3M = 3,
446 BASE_ARCH_4 = 4,
447 BASE_ARCH_4T = 4,
448 BASE_ARCH_5 = 5,
449 BASE_ARCH_5E = 5,
450 BASE_ARCH_5T = 5,
451 BASE_ARCH_5TE = 5,
452 BASE_ARCH_5TEJ = 5,
453 BASE_ARCH_6 = 6,
454 BASE_ARCH_6J = 6,
455 BASE_ARCH_6ZK = 6,
456 BASE_ARCH_6K = 6,
457 BASE_ARCH_6T2 = 6,
458 BASE_ARCH_6M = 6,
459 BASE_ARCH_6Z = 6,
460 BASE_ARCH_7 = 7,
461 BASE_ARCH_7A = 7,
462 BASE_ARCH_7R = 7,
463 BASE_ARCH_7M = 7,
595fefee
MGD		 464 BASE_ARCH_7EM = 7,
465 BASE_ARCH_8A = 8
9e94a7fc
MGD		 466};
467
468/* The major revision number of the ARM Architecture implemented by the target. */
469extern enum base_architecture arm_base_arch;
470
9b66ebb1
PB		 471/* Nonzero if this chip supports the ARM Architecture 3M extensions. */
472extern int arm_arch3m;
11c1a207 473
9b66ebb1 474/* Nonzero if this chip supports the ARM Architecture 4 extensions. */
11c1a207
RE		 475extern int arm_arch4;
476
68d560d4
RE		 477/* Nonzero if this chip supports the ARM Architecture 4T extensions. */
478extern int arm_arch4t;
479
9b66ebb1 480/* Nonzero if this chip supports the ARM Architecture 5 extensions. */
62b10bbc
NC		 481extern int arm_arch5;
482
9b66ebb1 483/* Nonzero if this chip supports the ARM Architecture 5E extensions. */
b15bca31
RE		 484extern int arm_arch5e;
485
9b66ebb1
PB		 486/* Nonzero if this chip supports the ARM Architecture 6 extensions. */
487extern int arm_arch6;
488
029e79eb
MS		 489/* Nonzero if this chip supports the ARM Architecture 6k extensions. */
490extern int arm_arch6k;
491
9e2a6301
TG		 492/* Nonzero if instructions present in ARMv6-M can be used. */
493extern int arm_arch6m;
494
029e79eb
MS		 495/* Nonzero if this chip supports the ARM Architecture 7 extensions. */
496extern int arm_arch7;
497
5b3e6663
PB		 498/* Nonzero if instructions not present in the 'M' profile can be used. */
499extern int arm_arch_notm;
500
60bd3528
PB		 501/* Nonzero if instructions present in ARMv7E-M can be used. */
502extern int arm_arch7em;
503
595fefee
MGD		 504/* Nonzero if this chip supports the ARM Architecture 8 extensions. */
505extern int arm_arch8;
506
f5a1b0d2
NC		 507/* Nonzero if this chip can benefit from load scheduling. */
508extern int arm_ld_sched;
509
906668bb 510/* Nonzero if generating Thumb code, either Thumb-1 or Thumb-2. */
0616531f
RE		 511extern int thumb_code;
512
906668bb
BS		 513/* Nonzero if generating Thumb-1 code. */
514extern int thumb1_code;
515
f5a1b0d2 516/* Nonzero if this chip is a StrongARM. */
abac3b49 517extern int arm_tune_strongarm;
f5a1b0d2 518
5a9335ef
NC		 519/* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */
520extern int arm_arch_iwmmxt;
521
8fd03515
XQ		 522/* Nonzero if this chip supports Intel Wireless MMX2 technology. */
523extern int arm_arch_iwmmxt2;
524
d19fb8e3 525/* Nonzero if this chip is an XScale. */
4b3c2e48
PB		 526extern int arm_arch_xscale;
527
abac3b49 528/* Nonzero if tuning for XScale. */
4b3c2e48 529extern int arm_tune_xscale;
d19fb8e3 530
abac3b49
RE		 531/* Nonzero if tuning for stores via the write buffer. */
532extern int arm_tune_wbuf;
f5a1b0d2 533
7612f14d
PB		 534/* Nonzero if tuning for Cortex-A9. */
535extern int arm_tune_cortex_a9;
536
2ad4dcf9 537/* Nonzero if we should define __THUMB_INTERWORK__ in the
f676971a 538 preprocessor.
2ad4dcf9
RE		 539 XXX This is a bit of a hack, it's intended to help work around
540 problems in GLD which doesn't understand that armv5t code is
541 interworking clean. */
542extern int arm_cpp_interwork;
543
5b3e6663
PB		 544/* Nonzero if chip supports Thumb 2. */
545extern int arm_arch_thumb2;
546
572070ef
PB		 547/* Nonzero if chip supports integer division instruction in ARM mode. */
548extern int arm_arch_arm_hwdiv;
549
550/* Nonzero if chip supports integer division instruction in Thumb mode. */
551extern int arm_arch_thumb_hwdiv;
5b3e6663 552
65074f54
CL		 553/* Nonzero if we should use Neon to handle 64-bits operations rather
554 than core registers. */
555extern int prefer_neon_for_64bits;
556
2ce9c1b9 557#ifndef TARGET_DEFAULT
c54c7322 558#define TARGET_DEFAULT (MASK_APCS_FRAME)
2ce9c1b9 559#endif
35d965d5 560
86efdc8e
PB		 561/* Nonzero if PIC code requires explicit qualifiers to generate
562 PLT and GOT relocs rather than the assembler doing so implicitly.
ed0e6530
PB		 563 Subtargets can override these if required. */
564#ifndef NEED_GOT_RELOC
565#define NEED_GOT_RELOC 0
566#endif
567#ifndef NEED_PLT_RELOC
568#define NEED_PLT_RELOC 0
e2723c62 569#endif
84306176
PB		 570
571/* Nonzero if we need to refer to the GOT with a PC-relative
572 offset. In other words, generate
573
f676971a 574 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)]
84306176
PB		 575
576 rather than
577
578 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8)
579
f676971a 580 The default is true, which matches NetBSD. Subtargets can
84306176
PB		 581 override this if required. */
582#ifndef GOT_PCREL
583#define GOT_PCREL 1
584#endif
35d965d5
RS		 585\f
586/* Target machine storage Layout. */
587
ff9940b0
RE		 588
589/* Define this macro if it is advisable to hold scalars in registers
590 in a wider mode than that declared by the program. In such cases,
591 the value is constrained to be within the bounds of the declared
592 type, but kept valid in the wider mode. The signedness of the
593 extension may differ from that of the type. */
594
595/* It is far faster to zero extend chars than to sign extend them */
596
6cfc7210 597#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
2ce9c1b9
RE		 598 if (GET_MODE_CLASS (MODE) == MODE_INT \
599 && GET_MODE_SIZE (MODE) < 4) \
600 { \
601 if (MODE == QImode) \
602 UNSIGNEDP = 1; \
603 else if (MODE == HImode) \
61f0ccff 604 UNSIGNEDP = 1; \
2ce9c1b9 605 (MODE) = SImode; \
ff9940b0
RE		 606 }
607
35d965d5
RS		 608/* Define this if most significant bit is lowest numbered
609 in instructions that operate on numbered bit-fields. */
610#define BITS_BIG_ENDIAN 0
611
f676971a 612/* Define this if most significant byte of a word is the lowest numbered.
3ada8e17
DE		 613 Most ARM processors are run in little endian mode, so that is the default.
614 If you want to have it run-time selectable, change the definition in a
615 cover file to be TARGET_BIG_ENDIAN. */
11c1a207 616#define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
35d965d5
RS		 617
618/* Define this if most significant word of a multiword number is the lowest
11c1a207
RE		 619 numbered.
620 This is always false, even when in big-endian mode. */
ddee6aba
RE		 621#define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS)
622
35d965d5
RS		 623#define UNITS_PER_WORD 4
624
5848830f 625/* True if natural alignment is used for doubleword types. */
b6685939
PB		 626#define ARM_DOUBLEWORD_ALIGN TARGET_AAPCS_BASED
627
5848830f 628#define DOUBLEWORD_ALIGNMENT 64
35d965d5 629
5848830f 630#define PARM_BOUNDARY 32
5a9335ef 631
5848830f 632#define STACK_BOUNDARY (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
35d965d5 633
5848830f
PB		 634#define PREFERRED_STACK_BOUNDARY \
635 (arm_abi == ARM_ABI_ATPCS ? 64 : STACK_BOUNDARY)
0977774b 636
f711a87a 637#define FUNCTION_BOUNDARY ((TARGET_THUMB && optimize_size) ? 16 : 32)
35d965d5 638
92928d71
AO		 639/* The lowest bit is used to indicate Thumb-mode functions, so the
640 vbit must go into the delta field of pointers to member
641 functions. */
642#define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
643
35d965d5
RS		 644#define EMPTY_FIELD_BOUNDARY 32
645
5848830f 646#define BIGGEST_ALIGNMENT (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
5a9335ef 647
27847754
NC		 648/* XXX Blah -- this macro is used directly by libobjc. Since it
649 supports no vector modes, cut out the complexity and fall back
650 on BIGGEST_FIELD_ALIGNMENT. */
651#ifdef IN_TARGET_LIBS
8fca31a2 652#define BIGGEST_FIELD_ALIGNMENT 64
27847754 653#endif
5a9335ef 654
ff9940b0 655/* Make strings word-aligned so strcpy from constants will be faster. */
591af218 656#define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_tune_xscale ? 1 : 2)
f676971a 657
d19fb8e3 658#define CONSTANT_ALIGNMENT(EXP, ALIGN) \
5848830f 659 ((TREE_CODE (EXP) == STRING_CST \
36b15ad0 660 && !optimize_size \
5848830f
PB		 661 && (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \
662 ? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN))
ff9940b0 663
96339268
RE		 664/* Align definitions of arrays, unions and structures so that
665 initializations and copies can be made more efficient. This is not
666 ABI-changing, so it only affects places where we can see the
0c86e0dd
CLT		 667 definition. Increasing the alignment tends to introduce padding,
668 so don't do this when optimizing for size/conserving stack space. */
669#define ARM_EXPAND_ALIGNMENT(COND, EXP, ALIGN) \
670 (((COND) && ((ALIGN) < BITS_PER_WORD) \
96339268
RE		 671 && (TREE_CODE (EXP) == ARRAY_TYPE \
672 || TREE_CODE (EXP) == UNION_TYPE \
673 || TREE_CODE (EXP) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
674
0c86e0dd
CLT		 675/* Align global data. */
676#define DATA_ALIGNMENT(EXP, ALIGN) \
677 ARM_EXPAND_ALIGNMENT(!optimize_size, EXP, ALIGN)
678
96339268 679/* Similarly, make sure that objects on the stack are sensibly aligned. */
0c86e0dd
CLT		 680#define LOCAL_ALIGNMENT(EXP, ALIGN) \
681 ARM_EXPAND_ALIGNMENT(!flag_conserve_stack, EXP, ALIGN)
96339268 682
723ae7c1
NC		 683/* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the
684 value set in previous versions of this toolchain was 8, which produces more
685 compact structures. The command line option -mstructure_size_boundary=<n>
f710504c 686 can be used to change this value. For compatibility with the ARM SDK
723ae7c1 687 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI
5848830f
PB		 688 0020D) page 2-20 says "Structures are aligned on word boundaries".
689 The AAPCS specifies a value of 8. */
6ead9ba5 690#define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary
723ae7c1 691
4912a07c 692/* This is the value used to initialize arm_structure_size_boundary. If a
723ae7c1 693 particular arm target wants to change the default value it should change
6bc82793 694 the definition of this macro, not STRUCTURE_SIZE_BOUNDARY. See netbsd.h
723ae7c1
NC		 695 for an example of this. */
696#ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY
697#define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32
b355a481 698#endif
2a5307b1 699
825dda42 700/* Nonzero if move instructions will actually fail to work
ff9940b0 701 when given unaligned data. */
35d965d5 702#define STRICT_ALIGNMENT 1
b6685939
PB		 703
704/* wchar_t is unsigned under the AAPCS. */
705#ifndef WCHAR_TYPE
706#define WCHAR_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "int")
707
708#define WCHAR_TYPE_SIZE BITS_PER_WORD
709#endif
710
655b30bf
JB		 711/* Sized for fixed-point types. */
712
713#define SHORT_FRACT_TYPE_SIZE 8
714#define FRACT_TYPE_SIZE 16
715#define LONG_FRACT_TYPE_SIZE 32
716#define LONG_LONG_FRACT_TYPE_SIZE 64
717
718#define SHORT_ACCUM_TYPE_SIZE 16
719#define ACCUM_TYPE_SIZE 32
720#define LONG_ACCUM_TYPE_SIZE 64
721#define LONG_LONG_ACCUM_TYPE_SIZE 64
722
723#define MAX_FIXED_MODE_SIZE 64
724
b6685939
PB		 725#ifndef SIZE_TYPE
726#define SIZE_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "long unsigned int")
727#endif
d81d0bdd 728
077fc835
KH		 729#ifndef PTRDIFF_TYPE
730#define PTRDIFF_TYPE (TARGET_AAPCS_BASED ? "int" : "long int")
731#endif
732
d81d0bdd
PB		 733/* AAPCS requires that structure alignment is affected by bitfields. */
734#ifndef PCC_BITFIELD_TYPE_MATTERS
735#define PCC_BITFIELD_TYPE_MATTERS TARGET_AAPCS_BASED
736#endif
737
35d965d5
RS		 738\f
739/* Standard register usage. */
740
0be8bd1a 741/* Register allocation in ARM Procedure Call Standard
35d965d5
RS		 742 (S - saved over call).
743
744 r0 * argument word/integer result
745 r1-r3 argument word
746
747 r4-r8 S register variable
748 r9 S (rfp) register variable (real frame pointer)
f676971a 749
f5a1b0d2 750 r10 F S (sl) stack limit (used by -mapcs-stack-check)
35d965d5
RS		 751 r11 F S (fp) argument pointer
752 r12 (ip) temp workspace
753 r13 F S (sp) lower end of current stack frame
754 r14 (lr) link address/workspace
755 r15 F (pc) program counter
756
ff9940b0
RE		 757 cc This is NOT a real register, but is used internally
758 to represent things that use or set the condition
759 codes.
760 sfp This isn't either. It is used during rtl generation
761 since the offset between the frame pointer and the
762 auto's isn't known until after register allocation.
763 afp Nor this, we only need this because of non-local
764 goto. Without it fp appears to be used and the
765 elimination code won't get rid of sfp. It tracks
766 fp exactly at all times.
767
5efd84c5 768 *: See TARGET_CONDITIONAL_REGISTER_USAGE */
35d965d5 769
9b66ebb1
PB		 770/* s0-s15 VFP scratch (aka d0-d7).
771 s16-s31 S VFP variable (aka d8-d15).
772 vfpcc Not a real register. Represents the VFP condition
773 code flags. */
774
ff9940b0
RE		 775/* The stack backtrace structure is as follows:
776 fp points to here: | save code pointer | [fp]
777 | return link value | [fp, #-4]
778 | return sp value | [fp, #-8]
779 | return fp value | [fp, #-12]
780 [| saved r10 value |]
781 [| saved r9 value |]
782 [| saved r8 value |]
783 [| saved r7 value |]
784 [| saved r6 value |]
785 [| saved r5 value |]
786 [| saved r4 value |]
787 [| saved r3 value |]
788 [| saved r2 value |]
789 [| saved r1 value |]
790 [| saved r0 value |]
ff9940b0
RE		 791 r0-r3 are not normally saved in a C function. */
792
35d965d5
RS		 793/* 1 for registers that have pervasive standard uses
794 and are not available for the register allocator. */
0be8bd1a
RE		 795#define FIXED_REGISTERS \
796{ \
797 /* Core regs. */ \
798 0,0,0,0,0,0,0,0, \
799 0,0,0,0,0,1,0,1, \
800 /* VFP regs. */ \
801 1,1,1,1,1,1,1,1, \
802 1,1,1,1,1,1,1,1, \
803 1,1,1,1,1,1,1,1, \
804 1,1,1,1,1,1,1,1, \
805 1,1,1,1,1,1,1,1, \
806 1,1,1,1,1,1,1,1, \
807 1,1,1,1,1,1,1,1, \
808 1,1,1,1,1,1,1,1, \
809 /* IWMMXT regs. */ \
810 1,1,1,1,1,1,1,1, \
811 1,1,1,1,1,1,1,1, \
812 1,1,1,1, \
813 /* Specials. */ \
814 1,1,1,1 \
35d965d5
RS		 815}
816
817/* 1 for registers not available across function calls.
818 These must include the FIXED_REGISTERS and also any
819 registers that can be used without being saved.
820 The latter must include the registers where values are returned
821 and the register where structure-value addresses are passed.
ff9940b0 822 Aside from that, you can include as many other registers as you like.
f676971a 823 The CC is not preserved over function calls on the ARM 6, so it is
d6b4baa4 824 easier to assume this for all. SFP is preserved, since FP is. */
0be8bd1a
RE		 825#define CALL_USED_REGISTERS \
826{ \
827 /* Core regs. */ \
828 1,1,1,1,0,0,0,0, \
829 0,0,0,0,1,1,1,1, \
830 /* VFP Regs. */ \
831 1,1,1,1,1,1,1,1, \
832 1,1,1,1,1,1,1,1, \
833 1,1,1,1,1,1,1,1, \
834 1,1,1,1,1,1,1,1, \
835 1,1,1,1,1,1,1,1, \
836 1,1,1,1,1,1,1,1, \
837 1,1,1,1,1,1,1,1, \
838 1,1,1,1,1,1,1,1, \
839 /* IWMMXT regs. */ \
840 1,1,1,1,1,1,1,1, \
841 1,1,1,1,1,1,1,1, \
842 1,1,1,1, \
843 /* Specials. */ \
844 1,1,1,1 \
35d965d5
RS		 845}
846
6cc8c0b3
NC		 847#ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE
848#define SUBTARGET_CONDITIONAL_REGISTER_USAGE
849#endif
850
6bc82793 851/* These are a couple of extensions to the formats accepted
dd18ae56
NC		 852 by asm_fprintf:
853 %@ prints out ASM_COMMENT_START
854 %r prints out REGISTER_PREFIX reg_names[arg] */
855#define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \
856 case '@': \
857 fputs (ASM_COMMENT_START, FILE); \
858 break; \
859 \
860 case 'r': \
861 fputs (REGISTER_PREFIX, FILE); \
862 fputs (reg_names [va_arg (ARGS, int)], FILE); \
863 break;
864
d5b7b3ae 865/* Round X up to the nearest word. */
0c2ca901 866#define ROUND_UP_WORD(X) (((X) + 3) & ~3)
d5b7b3ae 867
6cfc7210 868/* Convert fron bytes to ints. */
e9d7b180 869#define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
6cfc7210 870
9b66ebb1
PB		 871/* The number of (integer) registers required to hold a quantity of type MODE.
872 Also used for VFP registers. */
e9d7b180
JD		 873#define ARM_NUM_REGS(MODE) \
874 ARM_NUM_INTS (GET_MODE_SIZE (MODE))
6cfc7210
NC		 875
876/* The number of (integer) registers required to hold a quantity of TYPE MODE. */
e9d7b180
JD		 877#define ARM_NUM_REGS2(MODE, TYPE) \
878 ARM_NUM_INTS ((MODE) == BLKmode ? \
d5b7b3ae 879 int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE))
6cfc7210
NC		 880
881/* The number of (integer) argument register available. */
d5b7b3ae 882#define NUM_ARG_REGS 4
6cfc7210 883
390b17c2
RE		 884/* And similarly for the VFP. */
885#define NUM_VFP_ARG_REGS 16
886
093354e0 887/* Return the register number of the N'th (integer) argument. */
d5b7b3ae 888#define ARG_REGISTER(N) (N - 1)
6cfc7210 889
d5b7b3ae
RE		 890/* Specify the registers used for certain standard purposes.
891 The values of these macros are register numbers. */
35d965d5 892
d5b7b3ae
RE		 893/* The number of the last argument register. */
894#define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS)
35d965d5 895
c769a35d
RE		 896/* The numbers of the Thumb register ranges. */
897#define FIRST_LO_REGNUM 0
6d3d9133 898#define LAST_LO_REGNUM 7
c769a35d
RE		 899#define FIRST_HI_REGNUM 8
900#define LAST_HI_REGNUM 11
6d3d9133 901
f0a0390e
RH		 902/* Overridden by config/arm/bpabi.h. */
903#ifndef ARM_UNWIND_INFO
904#define ARM_UNWIND_INFO 0
617a1b71
PB		 905#endif
906
c9ca9b88
PB		 907/* Use r0 and r1 to pass exception handling information. */
908#define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? N : INVALID_REGNUM)
909
6d3d9133 910/* The register that holds the return address in exception handlers. */
c9ca9b88
PB		 911#define ARM_EH_STACKADJ_REGNUM 2
912#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (SImode, ARM_EH_STACKADJ_REGNUM)
35d965d5 913
1e874273
PB		 914#ifndef ARM_TARGET2_DWARF_FORMAT
915#define ARM_TARGET2_DWARF_FORMAT DW_EH_PE_pcrel
916
917/* ttype entries (the only interesting data references used)
918 use TARGET2 relocations. */
919#define ASM_PREFERRED_EH_DATA_FORMAT(code, data) \
920 (((code) == 0 && (data) == 1 && ARM_UNWIND_INFO) ? ARM_TARGET2_DWARF_FORMAT \
921 : DW_EH_PE_absptr)
922#endif
923
d5b7b3ae
RE		 924/* The native (Norcroft) Pascal compiler for the ARM passes the static chain
925 as an invisible last argument (possible since varargs don't exist in
926 Pascal), so the following is not true. */
5b3e6663 927#define STATIC_CHAIN_REGNUM 12
35d965d5 928
d5b7b3ae
RE		 929/* Define this to be where the real frame pointer is if it is not possible to
930 work out the offset between the frame pointer and the automatic variables
931 until after register allocation has taken place. FRAME_POINTER_REGNUM
932 should point to a special register that we will make sure is eliminated.
933
934 For the Thumb we have another problem. The TPCS defines the frame pointer
6bc82793 935 as r11, and GCC believes that it is always possible to use the frame pointer
d5b7b3ae
RE		 936 as base register for addressing purposes. (See comments in
937 find_reloads_address()). But - the Thumb does not allow high registers,
938 including r11, to be used as base address registers. Hence our problem.
939
940 The solution used here, and in the old thumb port is to use r7 instead of
941 r11 as the hard frame pointer and to have special code to generate
942 backtrace structures on the stack (if required to do so via a command line
6bc82793 943 option) using r11. This is the only 'user visible' use of r11 as a frame
d5b7b3ae
RE		 944 pointer. */
945#define ARM_HARD_FRAME_POINTER_REGNUM 11
946#define THUMB_HARD_FRAME_POINTER_REGNUM 7
35d965d5 947
b15bca31
RE		 948#define HARD_FRAME_POINTER_REGNUM \
949 (TARGET_ARM \
950 ? ARM_HARD_FRAME_POINTER_REGNUM \
951 : THUMB_HARD_FRAME_POINTER_REGNUM)
d5b7b3ae 952
e3339d0f
JM		 953#define HARD_FRAME_POINTER_IS_FRAME_POINTER 0
954#define HARD_FRAME_POINTER_IS_ARG_POINTER 0
955
b15bca31 956#define FP_REGNUM HARD_FRAME_POINTER_REGNUM
d5b7b3ae 957
b15bca31
RE		 958/* Register to use for pushing function arguments. */
959#define STACK_POINTER_REGNUM SP_REGNUM
d5b7b3ae 960
0be8bd1a
RE		 961#define FIRST_IWMMXT_REGNUM (LAST_HI_VFP_REGNUM + 1)
962#define LAST_IWMMXT_REGNUM (FIRST_IWMMXT_REGNUM + 15)
a76213b9
XQ		 963
964/* Need to sync with WCGR in iwmmxt.md. */
0be8bd1a
RE		 965#define FIRST_IWMMXT_GR_REGNUM (LAST_IWMMXT_REGNUM + 1)
966#define LAST_IWMMXT_GR_REGNUM (FIRST_IWMMXT_GR_REGNUM + 3)
d5b7b3ae 967
5a9335ef
NC		 968#define IS_IWMMXT_REGNUM(REGNUM) \
969 (((REGNUM) >= FIRST_IWMMXT_REGNUM) && ((REGNUM) <= LAST_IWMMXT_REGNUM))
970#define IS_IWMMXT_GR_REGNUM(REGNUM) \
971 (((REGNUM) >= FIRST_IWMMXT_GR_REGNUM) && ((REGNUM) <= LAST_IWMMXT_GR_REGNUM))
972
35d965d5 973/* Base register for access to local variables of the function. */
0be8bd1a 974#define FRAME_POINTER_REGNUM 102
ff9940b0 975
d5b7b3ae 976/* Base register for access to arguments of the function. */
0be8bd1a 977#define ARG_POINTER_REGNUM 103
62b10bbc 978
0be8bd1a
RE		 979#define FIRST_VFP_REGNUM 16
980#define D7_VFP_REGNUM (FIRST_VFP_REGNUM + 15)
f1adb0a9 981#define LAST_VFP_REGNUM \
302c3d8e 982 (TARGET_VFPD32 ? LAST_HI_VFP_REGNUM : LAST_LO_VFP_REGNUM)
f1adb0a9 983
9b66ebb1
PB		 984#define IS_VFP_REGNUM(REGNUM) \
985 (((REGNUM) >= FIRST_VFP_REGNUM) && ((REGNUM) <= LAST_VFP_REGNUM))
986
f1adb0a9
JB		 987/* VFP registers are split into two types: those defined by VFP versions < 3
988 have D registers overlaid on consecutive pairs of S registers. VFP version 3
989 defines 16 new D registers (d16-d31) which, for simplicity and correctness
990 in various parts of the backend, we implement as "fake" single-precision
991 registers (which would be S32-S63, but cannot be used in that way). The
992 following macros define these ranges of registers. */
0be8bd1a
RE		 993#define LAST_LO_VFP_REGNUM (FIRST_VFP_REGNUM + 31)
994#define FIRST_HI_VFP_REGNUM (LAST_LO_VFP_REGNUM + 1)
995#define LAST_HI_VFP_REGNUM (FIRST_HI_VFP_REGNUM + 31)
f1adb0a9
JB		 996
997#define VFP_REGNO_OK_FOR_SINGLE(REGNUM) \
998 ((REGNUM) <= LAST_LO_VFP_REGNUM)
999
1000/* DFmode values are only valid in even register pairs. */
1001#define VFP_REGNO_OK_FOR_DOUBLE(REGNUM) \
1002 ((((REGNUM) - FIRST_VFP_REGNUM) & 1) == 0)
1003
88f77cba
JB		 1004/* Neon Quad values must start at a multiple of four registers. */
1005#define NEON_REGNO_OK_FOR_QUAD(REGNUM) \
1006 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0)
1007
1008/* Neon structures of vectors must be in even register pairs and there
1009 must be enough registers available. Because of various patterns
1010 requiring quad registers, we require them to start at a multiple of
1011 four. */
1012#define NEON_REGNO_OK_FOR_NREGS(REGNUM, N) \
1013 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0 \
1014 && (LAST_VFP_REGNUM - (REGNUM) >= 2 * (N) - 1))
1015
0be8bd1a 1016/* The number of hard registers is 16 ARM + 1 CC + 1 SFP + 1 AFP. */
5a9335ef 1017/* Intel Wireless MMX Technology registers add 16 + 4 more. */
0be8bd1a
RE		 1018/* VFP (VFP3) adds 32 (64) + 1 VFPCC. */
1019#define FIRST_PSEUDO_REGISTER 104
62b10bbc 1020
2fa330b2
PB		 1021#define DBX_REGISTER_NUMBER(REGNO) arm_dbx_register_number (REGNO)
1022
35d965d5
RS		 1023/* Value should be nonzero if functions must have frame pointers.
1024 Zero means the frame pointer need not be set up (and parms may be accessed
f676971a 1025 via the stack pointer) in functions that seem suitable.
ff9940b0
RE		 1026 If we have to have a frame pointer we might as well make use of it.
1027 APCS says that the frame pointer does not need to be pushed in leaf
2a5307b1 1028 functions, or simple tail call functions. */
a15900b5
DJ		 1029
1030#ifndef SUBTARGET_FRAME_POINTER_REQUIRED
1031#define SUBTARGET_FRAME_POINTER_REQUIRED 0
1032#endif
1033
d5b7b3ae
RE		 1034/* Return number of consecutive hard regs needed starting at reg REGNO
1035 to hold something of mode MODE.
1036 This is ordinarily the length in words of a value of mode MODE
1037 but can be less for certain modes in special long registers.
35d965d5 1038
0be8bd1a 1039 On the ARM core regs are UNITS_PER_WORD bits wide. */
d5b7b3ae 1040#define HARD_REGNO_NREGS(REGNO, MODE) \
5b3e6663 1041 ((TARGET_32BIT \
0be8bd1a 1042 && REGNO > PC_REGNUM \
d5b7b3ae
RE		 1043 && REGNO != FRAME_POINTER_REGNUM \
1044 && REGNO != ARG_POINTER_REGNUM) \
9b66ebb1 1045 && !IS_VFP_REGNUM (REGNO) \
e9d7b180 1046 ? 1 : ARM_NUM_REGS (MODE))
35d965d5 1047
4b02997f 1048/* Return true if REGNO is suitable for holding a quantity of type MODE. */
d5b7b3ae 1049#define HARD_REGNO_MODE_OK(REGNO, MODE) \
4b02997f 1050 arm_hard_regno_mode_ok ((REGNO), (MODE))
35d965d5 1051
2af8e257 1052#define MODES_TIEABLE_P(MODE1, MODE2) arm_modes_tieable_p (MODE1, MODE2)
ff9940b0 1053
5a9335ef 1054#define VALID_IWMMXT_REG_MODE(MODE) \
f676971a 1055 (arm_vector_mode_supported_p (MODE) || (MODE) == DImode)
5a9335ef 1056
88f77cba
JB		 1057/* Modes valid for Neon D registers. */
1058#define VALID_NEON_DREG_MODE(MODE) \
1059 ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode \
5819f96f 1060 || (MODE) == V4HFmode || (MODE) == V2SFmode || (MODE) == DImode)
88f77cba
JB		 1061
1062/* Modes valid for Neon Q registers. */
1063#define VALID_NEON_QREG_MODE(MODE) \
1064 ((MODE) == V4SImode || (MODE) == V8HImode || (MODE) == V16QImode \
1065 || (MODE) == V4SFmode || (MODE) == V2DImode)
1066
1067/* Structure modes valid for Neon registers. */
1068#define VALID_NEON_STRUCT_MODE(MODE) \
1069 ((MODE) == TImode || (MODE) == EImode || (MODE) == OImode \
1070 || (MODE) == CImode || (MODE) == XImode)
1071
37119410
BS		 1072/* The register numbers in sequence, for passing to arm_gen_load_multiple. */
1073extern int arm_regs_in_sequence[];
1074
35d965d5 1075/* The order in which register should be allocated. It is good to use ip
ff9940b0
RE		 1076 since no saving is required (though calls clobber it) and it never contains
1077 function parameters. It is quite good to use lr since other calls may
f676971a 1078 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is
ff9940b0 1079 least likely to contain a function parameter; in addition results are
f1adb0a9
JB		 1080 returned in r0.
1081 For VFP/VFPv3, allocate D16-D31 first, then caller-saved registers (D0-D7),
1082 then D8-D15. The reason for doing this is to attempt to reduce register
1083 pressure when both single- and double-precision registers are used in a
1084 function. */
1085
0be8bd1a
RE		 1086#define VREG(X) (FIRST_VFP_REGNUM + (X))
1087#define WREG(X) (FIRST_IWMMXT_REGNUM + (X))
1088#define WGREG(X) (FIRST_IWMMXT_GR_REGNUM + (X))
1089
f1adb0a9
JB		 1090#define REG_ALLOC_ORDER \
1091{ \
0be8bd1a
RE		 1092 /* General registers. */ \
1093 3, 2, 1, 0, 12, 14, 4, 5, \
1094 6, 7, 8, 9, 10, 11, \
1095 /* High VFP registers. */ \
1096 VREG(32), VREG(33), VREG(34), VREG(35), \
1097 VREG(36), VREG(37), VREG(38), VREG(39), \
1098 VREG(40), VREG(41), VREG(42), VREG(43), \
1099 VREG(44), VREG(45), VREG(46), VREG(47), \
1100 VREG(48), VREG(49), VREG(50), VREG(51), \
1101 VREG(52), VREG(53), VREG(54), VREG(55), \
1102 VREG(56), VREG(57), VREG(58), VREG(59), \
1103 VREG(60), VREG(61), VREG(62), VREG(63), \
1104 /* VFP argument registers. */ \
1105 VREG(15), VREG(14), VREG(13), VREG(12), \
1106 VREG(11), VREG(10), VREG(9), VREG(8), \
1107 VREG(7), VREG(6), VREG(5), VREG(4), \
1108 VREG(3), VREG(2), VREG(1), VREG(0), \
1109 /* VFP call-saved registers. */ \
1110 VREG(16), VREG(17), VREG(18), VREG(19), \
1111 VREG(20), VREG(21), VREG(22), VREG(23), \
1112 VREG(24), VREG(25), VREG(26), VREG(27), \
1113 VREG(28), VREG(29), VREG(30), VREG(31), \
1114 /* IWMMX registers. */ \
1115 WREG(0), WREG(1), WREG(2), WREG(3), \
1116 WREG(4), WREG(5), WREG(6), WREG(7), \
1117 WREG(8), WREG(9), WREG(10), WREG(11), \
1118 WREG(12), WREG(13), WREG(14), WREG(15), \
1119 WGREG(0), WGREG(1), WGREG(2), WGREG(3), \
1120 /* Registers not for general use. */ \
1121 CC_REGNUM, VFPCC_REGNUM, \
1122 FRAME_POINTER_REGNUM, ARG_POINTER_REGNUM, \
1123 SP_REGNUM, PC_REGNUM \
35d965d5 1124}
9338ffe6 1125
795dc4fc 1126/* Use different register alloc ordering for Thumb. */
5a733826
BS		 1127#define ADJUST_REG_ALLOC_ORDER arm_order_regs_for_local_alloc ()
1128
1129/* Tell IRA to use the order we define rather than messing it up with its
1130 own cost calculations. */
1131#define HONOR_REG_ALLOC_ORDER
795dc4fc 1132
9338ffe6
PB		 1133/* Interrupt functions can only use registers that have already been
1134 saved by the prologue, even if they would normally be
1135 call-clobbered. */
1136#define HARD_REGNO_RENAME_OK(SRC, DST) \
1137 (! IS_INTERRUPT (cfun->machine->func_type) || \
6fb5fa3c 1138 df_regs_ever_live_p (DST))
35d965d5
RS		 1139\f
1140/* Register and constant classes. */
1141
0be8bd1a 1142/* Register classes. */
35d965d5
RS		 1143enum reg_class
1144{
1145 NO_REGS,
0be8bd1a
RE		 1146 LO_REGS,
1147 STACK_REG,
1148 BASE_REGS,
1149 HI_REGS,
9adcfa3c 1150 CALLER_SAVE_REGS,
0be8bd1a
RE		 1151 GENERAL_REGS,
1152 CORE_REGS,
f1adb0a9
JB		 1153 VFP_D0_D7_REGS,
1154 VFP_LO_REGS,
1155 VFP_HI_REGS,
9b66ebb1 1156 VFP_REGS,
5a9335ef 1157 IWMMXT_REGS,
0be8bd1a 1158 IWMMXT_GR_REGS,
d5b7b3ae 1159 CC_REG,
9b66ebb1 1160 VFPCC_REG,
0be8bd1a
RE		 1161 SFP_REG,
1162 AFP_REG,
35d965d5
RS		 1163 ALL_REGS,
1164 LIM_REG_CLASSES
1165};
1166
1167#define N_REG_CLASSES (int) LIM_REG_CLASSES
1168
d6b4baa4 1169/* Give names of register classes as strings for dump file. */
35d965d5
RS		 1170#define REG_CLASS_NAMES \
1171{ \
1172 "NO_REGS", \
0be8bd1a
RE		 1173 "LO_REGS", \
1174 "STACK_REG", \
1175 "BASE_REGS", \
1176 "HI_REGS", \
9adcfa3c 1177 "CALLER_SAVE_REGS", \
0be8bd1a
RE		 1178 "GENERAL_REGS", \
1179 "CORE_REGS", \
f1adb0a9
JB		 1180 "VFP_D0_D7_REGS", \
1181 "VFP_LO_REGS", \
1182 "VFP_HI_REGS", \
9b66ebb1 1183 "VFP_REGS", \
5a9335ef 1184 "IWMMXT_REGS", \
0be8bd1a 1185 "IWMMXT_GR_REGS", \
d5b7b3ae 1186 "CC_REG", \
5384443a 1187 "VFPCC_REG", \
9f4f1735
JJ		 1188 "SFP_REG", \
1189 "AFP_REG", \
1190 "ALL_REGS" \
35d965d5
RS		 1191}
1192
1193/* Define which registers fit in which classes.
1194 This is an initializer for a vector of HARD_REG_SET
1195 of length N_REG_CLASSES. */
f1adb0a9
JB		 1196#define REG_CLASS_CONTENTS \
1197{ \
1198 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
f1adb0a9
JB		 1199 { 0x000000FF, 0x00000000, 0x00000000, 0x00000000 }, /* LO_REGS */ \
1200 { 0x00002000, 0x00000000, 0x00000000, 0x00000000 }, /* STACK_REG */ \
1201 { 0x000020FF, 0x00000000, 0x00000000, 0x00000000 }, /* BASE_REGS */ \
0be8bd1a 1202 { 0x00005F00, 0x00000000, 0x00000000, 0x00000000 }, /* HI_REGS */ \
9adcfa3c 1203 { 0x0000100F, 0x00000000, 0x00000000, 0x00000000 }, /* CALLER_SAVE_REGS */ \
0be8bd1a
RE		 1204 { 0x00005FFF, 0x00000000, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \
1205 { 0x00007FFF, 0x00000000, 0x00000000, 0x00000000 }, /* CORE_REGS */ \
1206 { 0xFFFF0000, 0x00000000, 0x00000000, 0x00000000 }, /* VFP_D0_D7_REGS */ \
1207 { 0xFFFF0000, 0x0000FFFF, 0x00000000, 0x00000000 }, /* VFP_LO_REGS */ \
1208 { 0x00000000, 0xFFFF0000, 0x0000FFFF, 0x00000000 }, /* VFP_HI_REGS */ \
1209 { 0xFFFF0000, 0xFFFFFFFF, 0x0000FFFF, 0x00000000 }, /* VFP_REGS */ \
1210 { 0x00000000, 0x00000000, 0xFFFF0000, 0x00000000 }, /* IWMMXT_REGS */ \
1211 { 0x00000000, 0x00000000, 0x00000000, 0x0000000F }, /* IWMMXT_GR_REGS */ \
1212 { 0x00000000, 0x00000000, 0x00000000, 0x00000010 }, /* CC_REG */ \
1213 { 0x00000000, 0x00000000, 0x00000000, 0x00000020 }, /* VFPCC_REG */ \
1214 { 0x00000000, 0x00000000, 0x00000000, 0x00000040 }, /* SFP_REG */ \
1215 { 0x00000000, 0x00000000, 0x00000000, 0x00000080 }, /* AFP_REG */ \
d8484d41 1216 { 0xFFFF7FFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x0000000F } /* ALL_REGS */ \
35d965d5 1217}
4b02997f 1218
f1adb0a9
JB		 1219/* Any of the VFP register classes. */
1220#define IS_VFP_CLASS(X) \
1221 ((X) == VFP_D0_D7_REGS || (X) == VFP_LO_REGS \
1222 || (X) == VFP_HI_REGS || (X) == VFP_REGS)
1223
35d965d5
RS		 1224/* The same information, inverted:
1225 Return the class number of the smallest class containing
1226 reg number REGNO. This could be a conditional expression
1227 or could index an array. */
d5b7b3ae 1228#define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO)
35d965d5 1229
0be8bd1a
RE		 1230/* In VFPv1, VFP registers could only be accessed in the mode they
1231 were set, so subregs would be invalid there. However, we don't
1232 support VFPv1 at the moment, and the restriction was lifted in
e81bf2ce
JB		 1233 VFPv2.
1234 In big-endian mode, modes greater than word size (i.e. DFmode) are stored in
1235 VFP registers in little-endian order. We can't describe that accurately to
1236 GCC, so avoid taking subregs of such values. */
1237#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1238 (TARGET_VFP && TARGET_BIG_END \
1239 && (GET_MODE_SIZE (FROM) > UNITS_PER_WORD \
1240 || GET_MODE_SIZE (TO) > UNITS_PER_WORD) \
1241 && reg_classes_intersect_p (VFP_REGS, (CLASS)))
75d2580c 1242
35d965d5 1243/* The class value for index registers, and the one for base regs. */
5b3e6663 1244#define INDEX_REG_CLASS (TARGET_THUMB1 ? LO_REGS : GENERAL_REGS)
f5c630c3 1245#define BASE_REG_CLASS (TARGET_THUMB1 ? LO_REGS : CORE_REGS)
d5b7b3ae 1246
b93a0fe6 1247/* For the Thumb the high registers cannot be used as base registers
6bc82793 1248 when addressing quantities in QI or HI mode; if we don't know the
888d2cd6 1249 mode, then we must be conservative. */
3dcc68a4 1250#define MODE_BASE_REG_CLASS(MODE) \
9adc580c 1251 (TARGET_ARM || (TARGET_THUMB2 && !optimize_size) ? CORE_REGS : \
888d2cd6
DJ		 1252 (((MODE) == SImode) ? BASE_REGS : LO_REGS))
1253
1254/* For Thumb we can not support SP+reg addressing, so we return LO_REGS
1255 instead of BASE_REGS. */
1256#define MODE_BASE_REG_REG_CLASS(MODE) BASE_REG_CLASS
3dcc68a4 1257
42db504c 1258/* When this hook returns true for MODE, the compiler allows
d5b7b3ae
RE		 1259 registers explicitly used in the rtl to be used as spill registers
1260 but prevents the compiler from extending the lifetime of these
d6b4baa4 1261 registers. */
42db504c
SB		 1262#define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \
1263 arm_small_register_classes_for_mode_p
35d965d5 1264
d5b7b3ae
RE		 1265/* Must leave BASE_REGS reloads alone */
1266#define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1267 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1268 ? ((true_regnum (X) == -1 ? LO_REGS \
1269 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1270 : NO_REGS)) \
1271 : NO_REGS)
1272
1273#define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
97358092 1274 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
d5b7b3ae
RE		 1275 ? ((true_regnum (X) == -1 ? LO_REGS \
1276 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1277 : NO_REGS)) \
1278 : NO_REGS)
35d965d5 1279
ff9940b0
RE		 1280/* Return the register class of a scratch register needed to copy IN into
1281 or out of a register in CLASS in MODE. If it can be done directly,
1282 NO_REGS is returned. */
d5b7b3ae 1283#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
fe2d934b 1284 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \
9b66ebb1 1285 ((TARGET_VFP && TARGET_HARD_FLOAT \
f1adb0a9 1286 && IS_VFP_CLASS (CLASS)) \
fe2d934b
PB		 1287 ? coproc_secondary_reload_class (MODE, X, FALSE) \
1288 : (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) \
1289 ? coproc_secondary_reload_class (MODE, X, TRUE) \
5b3e6663 1290 : TARGET_32BIT \
9b66ebb1 1291 ? (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \
d5b7b3ae
RE		 1292 ? GENERAL_REGS : NO_REGS) \
1293 : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X))
f676971a 1294
d6b4baa4 1295/* If we need to load shorts byte-at-a-time, then we need a scratch. */
d5b7b3ae 1296#define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
fe2d934b 1297 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \
9b66ebb1 1298 ((TARGET_VFP && TARGET_HARD_FLOAT \
f1adb0a9 1299 && IS_VFP_CLASS (CLASS)) \
fe2d934b
PB		 1300 ? coproc_secondary_reload_class (MODE, X, FALSE) : \
1301 (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) ? \
1302 coproc_secondary_reload_class (MODE, X, TRUE) : \
0be8bd1a
RE		 1303 (TARGET_32BIT ? \
1304 (((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \
1305 && CONSTANT_P (X)) \
9b6b54e2 1306 ? GENERAL_REGS : \
0be8bd1a 1307 (((MODE) == HImode && ! arm_arch4 \
d435a4be
KT		 1308 && (MEM_P (X) \
1309 || ((REG_P (X) || GET_CODE (X) == SUBREG) \
0be8bd1a
RE		 1310 && true_regnum (X) == -1))) \
1311 ? GENERAL_REGS : NO_REGS) \
1312 : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X)))
2ce9c1b9 1313
6f734908
RE		 1314/* Try a machine-dependent way of reloading an illegitimate address
1315 operand. If we find one, push the reload and jump to WIN. This
1316 macro is used in only one place: `find_reloads_address' in reload.c.
1317
1318 For the ARM, we wish to handle large displacements off a base
1319 register by splitting the addend across a MOV and the mem insn.
d5b7b3ae
RE		 1320 This can cut the number of reloads needed. */
1321#define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN) \
1322 do \
1323 { \
0cd98787
JZ		 1324 if (arm_legitimize_reload_address (&X, MODE, OPNUM, TYPE, IND)) \
1325 goto WIN; \
d5b7b3ae 1326 } \
62b10bbc 1327 while (0)
6f734908 1328
27847754 1329/* XXX If an HImode FP+large_offset address is converted to an HImode
d5b7b3ae
RE		 1330 SP+large_offset address, then reload won't know how to fix it. It sees
1331 only that SP isn't valid for HImode, and so reloads the SP into an index
1332 register, but the resulting address is still invalid because the offset
1333 is too big. We fix it here instead by reloading the entire address. */
1334/* We could probably achieve better results by defining PROMOTE_MODE to help
1335 cope with the variances between the Thumb's signed and unsigned byte and
1336 halfword load instructions. */
5b3e6663 1337/* ??? This should be safe for thumb2, but we may be able to do better. */
a132dad6
RE		 1338#define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_L, WIN) \
1339do { \
1340 rtx new_x = thumb_legitimize_reload_address (&X, MODE, OPNUM, TYPE, IND_L); \
1341 if (new_x) \
1342 { \
1343 X = new_x; \
1344 goto WIN; \
1345 } \
1346} while (0)
d5b7b3ae
RE		 1347
1348#define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1349 if (TARGET_ARM) \
1350 ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \
1351 else \
1352 THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN)
f676971a 1353
35d965d5
RS		 1354/* Return the maximum number of consecutive registers
1355 needed to represent mode MODE in a register of class CLASS.
0be8bd1a
RE		 1356 ARM regs are UNITS_PER_WORD bits.
1357 FIXME: Is this true for iWMMX? */
35d965d5 1358#define CLASS_MAX_NREGS(CLASS, MODE) \
0be8bd1a 1359 (ARM_NUM_REGS (MODE))
9b6b54e2
NC		 1360
1361/* If defined, gives a class of registers that cannot be used as the
1362 operand of a SUBREG that changes the mode of the object illegally. */
35d965d5
RS		 1363\f
1364/* Stack layout; function entry, exit and calling. */
1365
1366/* Define this if pushing a word on the stack
1367 makes the stack pointer a smaller address. */
1368#define STACK_GROWS_DOWNWARD 1
1369
a4d05547 1370/* Define this to nonzero if the nominal address of the stack frame
35d965d5
RS		 1371 is at the high-address end of the local variables;
1372 that is, each additional local variable allocated
1373 goes at a more negative offset in the frame. */
1374#define FRAME_GROWS_DOWNWARD 1
1375
a2503645
RS		 1376/* The amount of scratch space needed by _interwork_{r7,r11}_call_via_rN().
1377 When present, it is one word in size, and sits at the top of the frame,
1378 between the soft frame pointer and either r7 or r11.
1379
1380 We only need _interwork_rM_call_via_rN() for -mcaller-super-interworking,
1381 and only then if some outgoing arguments are passed on the stack. It would
1382 be tempting to also check whether the stack arguments are passed by indirect
1383 calls, but there seems to be no reason in principle why a post-reload pass
1384 couldn't convert a direct call into an indirect one. */
1385#define CALLER_INTERWORKING_SLOT_SIZE \
1386 (TARGET_CALLER_INTERWORKING \
38173d38 1387 && crtl->outgoing_args_size != 0 \
a2503645
RS		 1388 ? UNITS_PER_WORD : 0)
1389
35d965d5
RS		 1390/* Offset within stack frame to start allocating local variables at.
1391 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1392 first local allocated. Otherwise, it is the offset to the BEGINNING
1393 of the first local allocated. */
1394#define STARTING_FRAME_OFFSET 0
1395
1396/* If we generate an insn to push BYTES bytes,
1397 this says how many the stack pointer really advances by. */
d5b7b3ae 1398/* The push insns do not do this rounding implicitly.
d6b4baa4 1399 So don't define this. */
0c2ca901 1400/* #define PUSH_ROUNDING(NPUSHED) ROUND_UP_WORD (NPUSHED) */
18543a22
ILT		 1401
1402/* Define this if the maximum size of all the outgoing args is to be
1403 accumulated and pushed during the prologue. The amount can be
38173d38 1404 found in the variable crtl->outgoing_args_size. */
6cfc7210 1405#define ACCUMULATE_OUTGOING_ARGS 1
35d965d5
RS		 1406
1407/* Offset of first parameter from the argument pointer register value. */
d5b7b3ae 1408#define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0)
35d965d5 1409
9f7bf991
RE		 1410/* Amount of memory needed for an untyped call to save all possible return
1411 registers. */
1412#define APPLY_RESULT_SIZE arm_apply_result_size()
1413
11c1a207
RE		 1414/* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return
1415 values must be in memory. On the ARM, they need only do so if larger
d6b4baa4 1416 than a word, or if they contain elements offset from zero in the struct. */
11c1a207
RE		 1417#define DEFAULT_PCC_STRUCT_RETURN 0
1418
6d3d9133 1419/* These bits describe the different types of function supported
112cdef5 1420 by the ARM backend. They are exclusive. i.e. a function cannot be both a
6d3d9133
NC		 1421 normal function and an interworked function, for example. Knowing the
1422 type of a function is important for determining its prologue and
1423 epilogue sequences.
1424 Note value 7 is currently unassigned. Also note that the interrupt
1425 function types all have bit 2 set, so that they can be tested for easily.
1426 Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the
4912a07c 1427 machine_function structure is initialized (to zero) func_type will
6d3d9133
NC		 1428 default to unknown. This will force the first use of arm_current_func_type
1429 to call arm_compute_func_type. */
1430#define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */
1431#define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */
1432#define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */
6d3d9133
NC		 1433#define ARM_FT_ISR 4 /* An interrupt service routine. */
1434#define ARM_FT_FIQ 5 /* A fast interrupt service routine. */
1435#define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */
1436
1437#define ARM_FT_TYPE_MASK ((1 << 3) - 1)
1438
1439/* In addition functions can have several type modifiers,
1440 outlined by these bit masks: */
1441#define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */
1442#define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */
1443#define ARM_FT_VOLATILE (1 << 4) /* Does not return. */
d6b4baa4 1444#define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */
5b3e6663 1445#define ARM_FT_STACKALIGN (1 << 6) /* Called with misaligned stack. */
6d3d9133
NC		 1446
1447/* Some macros to test these flags. */
1448#define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK)
1449#define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT)
1450#define IS_VOLATILE(t) (t & ARM_FT_VOLATILE)
1451#define IS_NAKED(t) (t & ARM_FT_NAKED)
1452#define IS_NESTED(t) (t & ARM_FT_NESTED)
5b3e6663 1453#define IS_STACKALIGN(t) (t & ARM_FT_STACKALIGN)
6d3d9133 1454
5848830f
PB		 1455
1456/* Structure used to hold the function stack frame layout. Offsets are
1457 relative to the stack pointer on function entry. Positive offsets are
1458 in the direction of stack growth.
1459 Only soft_frame is used in thumb mode. */
1460
d1b38208 1461typedef struct GTY(()) arm_stack_offsets
5848830f
PB		 1462{
1463 int saved_args; /* ARG_POINTER_REGNUM. */
1464 int frame; /* ARM_HARD_FRAME_POINTER_REGNUM. */
1465 int saved_regs;
1466 int soft_frame; /* FRAME_POINTER_REGNUM. */
2591db65 1467 int locals_base; /* THUMB_HARD_FRAME_POINTER_REGNUM. */
5848830f 1468 int outgoing_args; /* STACK_POINTER_REGNUM. */
954954d1 1469 unsigned int saved_regs_mask;
5848830f
PB		 1470}
1471arm_stack_offsets;
1472
906668bb 1473#ifndef GENERATOR_FILE
6d3d9133
NC		 1474/* A C structure for machine-specific, per-function data.
1475 This is added to the cfun structure. */
d1b38208 1476typedef struct GTY(()) machine_function
d5b7b3ae 1477{
6bc82793 1478 /* Additional stack adjustment in __builtin_eh_throw. */
e2500fed 1479 rtx eh_epilogue_sp_ofs;
d5b7b3ae
RE		 1480 /* Records if LR has to be saved for far jumps. */
1481 int far_jump_used;
1482 /* Records if ARG_POINTER was ever live. */
1483 int arg_pointer_live;
6f7ebcbb
NC		 1484 /* Records if the save of LR has been eliminated. */
1485 int lr_save_eliminated;
0977774b 1486 /* The size of the stack frame. Only valid after reload. */
5848830f 1487 arm_stack_offsets stack_offsets;
6d3d9133
NC		 1488 /* Records the type of the current function. */
1489 unsigned long func_type;
3cb66fd7
NC		 1490 /* Record if the function has a variable argument list. */
1491 int uses_anonymous_args;
5a9335ef
NC		 1492 /* Records if sibcalls are blocked because an argument
1493 register is needed to preserve stack alignment. */
1494 int sibcall_blocked;
020a4035
RE		 1495 /* The PIC register for this function. This might be a pseudo. */
1496 rtx pic_reg;
b12a00f1 1497 /* Labels for per-function Thumb call-via stubs. One per potential calling
57ecec57
PB		 1498 register. We can never call via LR or PC. We can call via SP if a
1499 trampoline happens to be on the top of the stack. */
1500 rtx call_via[14];
934c2060
RR		 1501 /* Set to 1 when a return insn is output, this means that the epilogue
1502 is not needed. */
1503 int return_used_this_function;
906668bb
BS		 1504 /* When outputting Thumb-1 code, record the last insn that provides
1505 information about condition codes, and the comparison operands. */
1506 rtx thumb1_cc_insn;
1507 rtx thumb1_cc_op0;
1508 rtx thumb1_cc_op1;
1509 /* Also record the CC mode that is supported. */
1510 enum machine_mode thumb1_cc_mode;
6d3d9133
NC		 1511}
1512machine_function;
906668bb 1513#endif
d5b7b3ae 1514
b12a00f1 1515/* As in the machine_function, a global set of call-via labels, for code
d6b5193b 1516 that is in text_section. */
57ecec57 1517extern GTY(()) rtx thumb_call_via_label[14];
b12a00f1 1518
390b17c2
RE		 1519/* The number of potential ways of assigning to a co-processor. */
1520#define ARM_NUM_COPROC_SLOTS 1
1521
1522/* Enumeration of procedure calling standard variants. We don't really
1523 support all of these yet. */
1524enum arm_pcs
1525{
1526 ARM_PCS_AAPCS, /* Base standard AAPCS. */
1527 ARM_PCS_AAPCS_VFP, /* Use VFP registers for floating point values. */
1528 ARM_PCS_AAPCS_IWMMXT, /* Use iWMMXT registers for vectors. */
1529 /* This must be the last AAPCS variant. */
1530 ARM_PCS_AAPCS_LOCAL, /* Private call within this compilation unit. */
1531 ARM_PCS_ATPCS, /* ATPCS. */
1532 ARM_PCS_APCS, /* APCS (legacy Linux etc). */
1533 ARM_PCS_UNKNOWN
1534};
1535
12ffc7d5
CLT		 1536/* Default procedure calling standard of current compilation unit. */
1537extern enum arm_pcs arm_pcs_default;
1538
82e9d970 1539/* A C type for declaring a variable that is used as the first argument of
390b17c2 1540 `FUNCTION_ARG' and other related values. */
82e9d970
PB		 1541typedef struct
1542{
d5b7b3ae 1543 /* This is the number of registers of arguments scanned so far. */
82e9d970 1544 int nregs;
5a9335ef
NC		 1545 /* This is the number of iWMMXt register arguments scanned so far. */
1546 int iwmmxt_nregs;
1547 int named_count;
1548 int nargs;
390b17c2
RE		 1549 /* Which procedure call variant to use for this call. */
1550 enum arm_pcs pcs_variant;
1551
1552 /* AAPCS related state tracking. */
1553 int aapcs_arg_processed; /* No need to lay out this argument again. */
1554 int aapcs_cprc_slot; /* Index of co-processor rules to handle
1555 this argument, or -1 if using core
1556 registers. */
1557 int aapcs_ncrn;
1558 int aapcs_next_ncrn;
1559 rtx aapcs_reg; /* Register assigned to this argument. */
1560 int aapcs_partial; /* How many bytes are passed in regs (if
1561 split between core regs and stack.
1562 Zero otherwise. */
1563 int aapcs_cprc_failed[ARM_NUM_COPROC_SLOTS];
1564 int can_split; /* Argument can be split between core regs
1565 and the stack. */
1566 /* Private data for tracking VFP register allocation */
1567 unsigned aapcs_vfp_regs_free;
1568 unsigned aapcs_vfp_reg_alloc;
1569 int aapcs_vfp_rcount;
46107b99 1570 MACHMODE aapcs_vfp_rmode;
d5b7b3ae 1571} CUMULATIVE_ARGS;
82e9d970 1572
866af8a9
JB		 1573#define FUNCTION_ARG_PADDING(MODE, TYPE) \
1574 (arm_pad_arg_upward (MODE, TYPE) ? upward : downward)
1575
1576#define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
1577 (arm_pad_reg_upward (MODE, TYPE, FIRST) ? upward : downward)
1578
1579/* For AAPCS, padding should never be below the argument. For other ABIs,
1580 * mimic the default. */
1581#define PAD_VARARGS_DOWN \
1582 ((TARGET_AAPCS_BASED) ? 0 : BYTES_BIG_ENDIAN)
1583
35d965d5
RS		 1584/* Initialize a variable CUM of type CUMULATIVE_ARGS
1585 for a call to a function whose data type is FNTYPE.
1586 For a library call, FNTYPE is 0.
1587 On the ARM, the offset starts at 0. */
0f6937fe 1588#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
563a317a 1589 arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL))
35d965d5 1590
35d965d5
RS		 1591/* 1 if N is a possible register number for function argument passing.
1592 On the ARM, r0-r3 are used to pass args. */
390b17c2
RE		 1593#define FUNCTION_ARG_REGNO_P(REGNO) \
1594 (IN_RANGE ((REGNO), 0, 3) \
1595 || (TARGET_AAPCS_BASED && TARGET_VFP && TARGET_HARD_FLOAT \
1596 && IN_RANGE ((REGNO), FIRST_VFP_REGNUM, FIRST_VFP_REGNUM + 15)) \
1597 || (TARGET_IWMMXT_ABI \
5848830f 1598 && IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9)))
35d965d5 1599
f99fce0c 1600\f
afef3d7a 1601/* If your target environment doesn't prefix user functions with an
96a3900d 1602 underscore, you may wish to re-define this to prevent any conflicts. */
afef3d7a
NC		 1603#ifndef ARM_MCOUNT_NAME
1604#define ARM_MCOUNT_NAME "*mcount"
1605#endif
1606
1607/* Call the function profiler with a given profile label. The Acorn
1608 compiler puts this BEFORE the prolog but gcc puts it afterwards.
1609 On the ARM the full profile code will look like:
1610 .data
1611 LP1
1612 .word 0
1613 .text
1614 mov ip, lr
1615 bl mcount
1616 .word LP1
1617
1618 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER
1619 will output the .text section.
1620
1621 The ``mov ip,lr'' seems like a good idea to stick with cc convention.
59be6073
AN		 1622 ``prof'' doesn't seem to mind about this!
1623
1624 Note - this version of the code is designed to work in both ARM and
1625 Thumb modes. */
be393ecf 1626#ifndef ARM_FUNCTION_PROFILER
d5b7b3ae 1627#define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \
6cfc7210
NC		 1628{ \
1629 char temp[20]; \
1630 rtx sym; \
1631 \
dd18ae56 1632 asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \
d5b7b3ae 1633 IP_REGNUM, LR_REGNUM); \
6cfc7210
NC		 1634 assemble_name (STREAM, ARM_MCOUNT_NAME); \
1635 fputc ('\n', STREAM); \
1636 ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \
f1c25d3b 1637 sym = gen_rtx_SYMBOL_REF (Pmode, temp); \
301d03af 1638 assemble_aligned_integer (UNITS_PER_WORD, sym); \
35d965d5 1639}
be393ecf 1640#endif
35d965d5 1641
59be6073 1642#ifdef THUMB_FUNCTION_PROFILER
d5b7b3ae
RE		 1643#define FUNCTION_PROFILER(STREAM, LABELNO) \
1644 if (TARGET_ARM) \
1645 ARM_FUNCTION_PROFILER (STREAM, LABELNO) \
1646 else \
1647 THUMB_FUNCTION_PROFILER (STREAM, LABELNO)
59be6073
AN		 1648#else
1649#define FUNCTION_PROFILER(STREAM, LABELNO) \
1650 ARM_FUNCTION_PROFILER (STREAM, LABELNO)
1651#endif
d5b7b3ae 1652
35d965d5
RS		 1653/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1654 the stack pointer does not matter. The value is tested only in
1655 functions that have frame pointers.
1656 No definition is equivalent to always zero.
1657
1658 On the ARM, the function epilogue recovers the stack pointer from the
1659 frame. */
1660#define EXIT_IGNORE_STACK 1
1661
2b261262 1662#define EPILOGUE_USES(REGNO) (epilogue_completed && (REGNO) == LR_REGNUM)
c7861455 1663
35d965d5
RS		 1664/* Determine if the epilogue should be output as RTL.
1665 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
d5b7b3ae 1666#define USE_RETURN_INSN(ISCOND) \
7c19c715 1667 (TARGET_32BIT ? use_return_insn (ISCOND, NULL) : 0)
ff9940b0
RE		 1668
1669/* Definitions for register eliminations.
1670
1671 This is an array of structures. Each structure initializes one pair
1672 of eliminable registers. The "from" register number is given first,
1673 followed by "to". Eliminations of the same "from" register are listed
1674 in order of preference.
1675
1676 We have two registers that can be eliminated on the ARM. First, the
1677 arg pointer register can often be eliminated in favor of the stack
1678 pointer register. Secondly, the pseudo frame pointer register can always
1679 be eliminated; it is replaced with either the stack or the real frame
d5b7b3ae 1680 pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM
d6a7951f 1681 because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */
ff9940b0 1682
d5b7b3ae
RE		 1683#define ELIMINABLE_REGS \
1684{{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1685 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\
1686 { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1687 { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\
1688 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1689 { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1690 { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }}
ff9940b0 1691
d5b7b3ae
RE		 1692/* Define the offset between two registers, one to be eliminated, and the
1693 other its replacement, at the start of a routine. */
d5b7b3ae
RE		 1694#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1695 if (TARGET_ARM) \
5848830f 1696 (OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \
d5b7b3ae 1697 else \
5848830f
PB		 1698 (OFFSET) = thumb_compute_initial_elimination_offset (FROM, TO)
1699
d5b7b3ae
RE		 1700/* Special case handling of the location of arguments passed on the stack. */
1701#define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr)
f676971a 1702
d5b7b3ae
RE		 1703/* Initialize data used by insn expanders. This is called from insn_emit,
1704 once for every function before code is generated. */
1705#define INIT_EXPANDERS arm_init_expanders ()
1706
35d965d5 1707/* Length in units of the trampoline for entering a nested function. */
5b3e6663 1708#define TRAMPOLINE_SIZE (TARGET_32BIT ? 16 : 20)
35d965d5 1709
006946e4
JM		 1710/* Alignment required for a trampoline in bits. */
1711#define TRAMPOLINE_ALIGNMENT 32
35d965d5
RS		 1712\f
1713/* Addressing modes, and classification of registers for them. */
3cd45774 1714#define HAVE_POST_INCREMENT 1
5b3e6663
PB		 1715#define HAVE_PRE_INCREMENT TARGET_32BIT
1716#define HAVE_POST_DECREMENT TARGET_32BIT
1717#define HAVE_PRE_DECREMENT TARGET_32BIT
1718#define HAVE_PRE_MODIFY_DISP TARGET_32BIT
1719#define HAVE_POST_MODIFY_DISP TARGET_32BIT
1720#define HAVE_PRE_MODIFY_REG TARGET_32BIT
1721#define HAVE_POST_MODIFY_REG TARGET_32BIT
35d965d5 1722
8875e939
RR		 1723enum arm_auto_incmodes
1724 {
1725 ARM_POST_INC,
1726 ARM_PRE_INC,
1727 ARM_POST_DEC,
1728 ARM_PRE_DEC
1729 };
1730
1731#define ARM_AUTOINC_VALID_FOR_MODE_P(mode, code) \
1732 (TARGET_32BIT && arm_autoinc_modes_ok_p (mode, code))
1733#define USE_LOAD_POST_INCREMENT(mode) \
1734 ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_POST_INC)
1735#define USE_LOAD_PRE_INCREMENT(mode) \
1736 ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_PRE_INC)
1737#define USE_LOAD_POST_DECREMENT(mode) \
1738 ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_POST_DEC)
1739#define USE_LOAD_PRE_DECREMENT(mode) \
1740 ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_PRE_DEC)
1741
1742#define USE_STORE_PRE_DECREMENT(mode) USE_LOAD_PRE_DECREMENT(mode)
1743#define USE_STORE_PRE_INCREMENT(mode) USE_LOAD_PRE_INCREMENT(mode)
1744#define USE_STORE_POST_DECREMENT(mode) USE_LOAD_POST_DECREMENT(mode)
1745#define USE_STORE_POST_INCREMENT(mode) USE_LOAD_POST_INCREMENT(mode)
1746
35d965d5
RS		 1747/* Macros to check register numbers against specific register classes. */
1748
1749/* These assume that REGNO is a hard or pseudo reg number.
1750 They give nonzero only if REGNO is a hard reg of the suitable class
1751 or a pseudo reg currently allocated to a suitable hard reg.
1752 Since they use reg_renumber, they are safe only once reg_renumber
aeb9f7cf
SB		 1753 has been allocated, which happens in reginfo.c during register
1754 allocation. */
d5b7b3ae
RE		 1755#define TEST_REGNO(R, TEST, VALUE) \
1756 ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE))
1757
5b3e6663 1758/* Don't allow the pc to be used. */
f1008e52
RE		 1759#define ARM_REGNO_OK_FOR_BASE_P(REGNO) \
1760 (TEST_REGNO (REGNO, <, PC_REGNUM) \
1761 || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \
1762 || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM))
1763
5b3e6663 1764#define THUMB1_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
f1008e52
RE		 1765 (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \
1766 || (GET_MODE_SIZE (MODE) >= 4 \
1767 && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)))
1768
1769#define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
5b3e6663
PB		 1770 (TARGET_THUMB1 \
1771 ? THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \
f1008e52
RE		 1772 : ARM_REGNO_OK_FOR_BASE_P (REGNO))
1773
888d2cd6
DJ		 1774/* Nonzero if X can be the base register in a reg+reg addressing mode.
1775 For Thumb, we can not use SP + reg, so reject SP. */
1776#define REGNO_MODE_OK_FOR_REG_BASE_P(X, MODE) \
f5c630c3 1777 REGNO_MODE_OK_FOR_BASE_P (X, QImode)
888d2cd6 1778
f1008e52
RE		 1779/* For ARM code, we don't care about the mode, but for Thumb, the index
1780 must be suitable for use in a QImode load. */
d5b7b3ae 1781#define REGNO_OK_FOR_INDEX_P(REGNO) \
f5c630c3
PB		 1782 (REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode) \
1783 && !TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM))
35d965d5
RS		 1784
1785/* Maximum number of registers that can appear in a valid memory address.
d6b4baa4 1786 Shifts in addresses can't be by a register. */
ff9940b0 1787#define MAX_REGS_PER_ADDRESS 2
35d965d5
RS		 1788
1789/* Recognize any constant value that is a valid address. */
1790/* XXX We can address any constant, eventually... */
5b3e6663 1791/* ??? Should the TARGET_ARM here also apply to thumb2? */
008cf58a
RE		 1792#define CONSTANT_ADDRESS_P(X) \
1793 (GET_CODE (X) == SYMBOL_REF \
1794 && (CONSTANT_POOL_ADDRESS_P (X) \
d5b7b3ae 1795 || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X))))
35d965d5 1796
8426b956
RS		 1797/* True if SYMBOL + OFFSET constants must refer to something within
1798 SYMBOL's section. */
1799#define ARM_OFFSETS_MUST_BE_WITHIN_SECTIONS_P 0
1800
571191af
PB		 1801/* Nonzero if all target requires all absolute relocations be R_ARM_ABS32. */
1802#ifndef TARGET_DEFAULT_WORD_RELOCATIONS
1803#define TARGET_DEFAULT_WORD_RELOCATIONS 0
1804#endif
1805
c27ba912
DM		 1806#ifndef SUBTARGET_NAME_ENCODING_LENGTHS
1807#define SUBTARGET_NAME_ENCODING_LENGTHS
1808#endif
1809
6bc82793 1810/* This is a C fragment for the inside of a switch statement.
c27ba912
DM		 1811 Each case label should return the number of characters to
1812 be stripped from the start of a function's name, if that
1813 name starts with the indicated character. */
1814#define ARM_NAME_ENCODING_LENGTHS \
00fdafef 1815 case '*': return 1; \
f676971a 1816 SUBTARGET_NAME_ENCODING_LENGTHS
c27ba912 1817
c27ba912
DM		 1818/* This is how to output a reference to a user-level label named NAME.
1819 `assemble_name' uses this. */
e5951263 1820#undef ASM_OUTPUT_LABELREF
c27ba912 1821#define ASM_OUTPUT_LABELREF(FILE, NAME) \
e1944073 1822 arm_asm_output_labelref (FILE, NAME)
c27ba912 1823
7a085dce 1824/* Output IT instructions for conditionally executed Thumb-2 instructions. */
5b3e6663
PB		 1825#define ASM_OUTPUT_OPCODE(STREAM, PTR) \
1826 if (TARGET_THUMB2) \
1827 thumb2_asm_output_opcode (STREAM);
1828
7abc66b1
JB		 1829/* The EABI specifies that constructors should go in .init_array.
1830 Other targets use .ctors for compatibility. */
88c6057f 1831#ifndef ARM_EABI_CTORS_SECTION_OP
7abc66b1
JB		 1832#define ARM_EABI_CTORS_SECTION_OP \
1833 "\t.section\t.init_array,\"aw\",%init_array"
88c6057f
MM		 1834#endif
1835#ifndef ARM_EABI_DTORS_SECTION_OP
7abc66b1
JB		 1836#define ARM_EABI_DTORS_SECTION_OP \
1837 "\t.section\t.fini_array,\"aw\",%fini_array"
88c6057f 1838#endif
7abc66b1
JB		 1839#define ARM_CTORS_SECTION_OP \
1840 "\t.section\t.ctors,\"aw\",%progbits"
1841#define ARM_DTORS_SECTION_OP \
1842 "\t.section\t.dtors,\"aw\",%progbits"
1843
1844/* Define CTORS_SECTION_ASM_OP. */
1845#undef CTORS_SECTION_ASM_OP
1846#undef DTORS_SECTION_ASM_OP
1847#ifndef IN_LIBGCC2
1848# define CTORS_SECTION_ASM_OP \
1849 (TARGET_AAPCS_BASED ? ARM_EABI_CTORS_SECTION_OP : ARM_CTORS_SECTION_OP)
1850# define DTORS_SECTION_ASM_OP \
1851 (TARGET_AAPCS_BASED ? ARM_EABI_DTORS_SECTION_OP : ARM_DTORS_SECTION_OP)
1852#else /* !defined (IN_LIBGCC2) */
1853/* In libgcc, CTORS_SECTION_ASM_OP must be a compile-time constant,
1854 so we cannot use the definition above. */
1855# ifdef __ARM_EABI__
1856/* The .ctors section is not part of the EABI, so we do not define
1857 CTORS_SECTION_ASM_OP when in libgcc; that prevents crtstuff
1858 from trying to use it. We do define it when doing normal
1859 compilation, as .init_array can be used instead of .ctors. */
1860/* There is no need to emit begin or end markers when using
1861 init_array; the dynamic linker will compute the size of the
1862 array itself based on special symbols created by the static
1863 linker. However, we do need to arrange to set up
1864 exception-handling here. */
1865# define CTOR_LIST_BEGIN asm (ARM_EABI_CTORS_SECTION_OP)
1866# define CTOR_LIST_END /* empty */
1867# define DTOR_LIST_BEGIN asm (ARM_EABI_DTORS_SECTION_OP)
1868# define DTOR_LIST_END /* empty */
1869# else /* !defined (__ARM_EABI__) */
1870# define CTORS_SECTION_ASM_OP ARM_CTORS_SECTION_OP
1871# define DTORS_SECTION_ASM_OP ARM_DTORS_SECTION_OP
1872# endif /* !defined (__ARM_EABI__) */
1873#endif /* !defined (IN_LIBCC2) */
1874
1e731102
MM		 1875/* True if the operating system can merge entities with vague linkage
1876 (e.g., symbols in COMDAT group) during dynamic linking. */
1877#ifndef TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P
1878#define TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P true
1879#endif
1880
617a1b71
PB		 1881#define ARM_OUTPUT_FN_UNWIND(F, PROLOGUE) arm_output_fn_unwind (F, PROLOGUE)
1882
35d965d5
RS		 1883/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1884 and check its validity for a certain class.
1885 We have two alternate definitions for each of them.
1886 The usual definition accepts all pseudo regs; the other rejects
1887 them unless they have been allocated suitable hard regs.
5b3e6663 1888 The symbol REG_OK_STRICT causes the latter definition to be used.
7a085dce 1889 Thumb-2 has the same restrictions as arm. */
35d965d5 1890#ifndef REG_OK_STRICT
ff9940b0 1891
f1008e52
RE		 1892#define ARM_REG_OK_FOR_BASE_P(X) \
1893 (REGNO (X) <= LAST_ARM_REGNUM \
1894 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
1895 || REGNO (X) == FRAME_POINTER_REGNUM \
1896 || REGNO (X) == ARG_POINTER_REGNUM)
ff9940b0 1897
f5c630c3
PB		 1898#define ARM_REG_OK_FOR_INDEX_P(X) \
1899 ((REGNO (X) <= LAST_ARM_REGNUM \
1900 && REGNO (X) != STACK_POINTER_REGNUM) \
1901 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
1902 || REGNO (X) == FRAME_POINTER_REGNUM \
1903 || REGNO (X) == ARG_POINTER_REGNUM)
1904
5b3e6663 1905#define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \
f1008e52
RE		 1906 (REGNO (X) <= LAST_LO_REGNUM \
1907 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
1908 || (GET_MODE_SIZE (MODE) >= 4 \
1909 && (REGNO (X) == STACK_POINTER_REGNUM \
1910 || (X) == hard_frame_pointer_rtx \
1911 || (X) == arg_pointer_rtx)))
ff9940b0 1912
76a318e9
RE		 1913#define REG_STRICT_P 0
1914
d5b7b3ae 1915#else /* REG_OK_STRICT */
ff9940b0 1916
f1008e52
RE		 1917#define ARM_REG_OK_FOR_BASE_P(X) \
1918 ARM_REGNO_OK_FOR_BASE_P (REGNO (X))
ff9940b0 1919
f5c630c3
PB		 1920#define ARM_REG_OK_FOR_INDEX_P(X) \
1921 ARM_REGNO_OK_FOR_INDEX_P (REGNO (X))
1922
5b3e6663
PB		 1923#define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \
1924 THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE)
ff9940b0 1925
76a318e9
RE		 1926#define REG_STRICT_P 1
1927
d5b7b3ae 1928#endif /* REG_OK_STRICT */
f1008e52
RE		 1929
1930/* Now define some helpers in terms of the above. */
1931
1932#define REG_MODE_OK_FOR_BASE_P(X, MODE) \
5b3e6663
PB		 1933 (TARGET_THUMB1 \
1934 ? THUMB1_REG_MODE_OK_FOR_BASE_P (X, MODE) \
f1008e52
RE		 1935 : ARM_REG_OK_FOR_BASE_P (X))
1936
5b3e6663 1937/* For 16-bit Thumb, a valid index register is anything that can be used in
f1008e52 1938 a byte load instruction. */
5b3e6663
PB		 1939#define THUMB1_REG_OK_FOR_INDEX_P(X) \
1940 THUMB1_REG_MODE_OK_FOR_BASE_P (X, QImode)
f1008e52
RE		 1941
1942/* Nonzero if X is a hard reg that can be used as an index
1943 or if it is a pseudo reg. On the Thumb, the stack pointer
1944 is not suitable. */
1945#define REG_OK_FOR_INDEX_P(X) \
5b3e6663
PB		 1946 (TARGET_THUMB1 \
1947 ? THUMB1_REG_OK_FOR_INDEX_P (X) \
f1008e52
RE		 1948 : ARM_REG_OK_FOR_INDEX_P (X))
1949
888d2cd6
DJ		 1950/* Nonzero if X can be the base register in a reg+reg addressing mode.
1951 For Thumb, we can not use SP + reg, so reject SP. */
1952#define REG_MODE_OK_FOR_REG_BASE_P(X, MODE) \
1953 REG_OK_FOR_INDEX_P (X)
35d965d5 1954\f
f1008e52 1955#define ARM_BASE_REGISTER_RTX_P(X) \
d435a4be 1956 (REG_P (X) && ARM_REG_OK_FOR_BASE_P (X))
35d965d5 1957
f1008e52 1958#define ARM_INDEX_REGISTER_RTX_P(X) \
d435a4be 1959 (REG_P (X) && ARM_REG_OK_FOR_INDEX_P (X))
35d965d5 1960\f
35d965d5
RS		 1961/* Specify the machine mode that this machine uses
1962 for the index in the tablejump instruction. */
d5b7b3ae 1963#define CASE_VECTOR_MODE Pmode
35d965d5 1964
907dd0c7 1965#define CASE_VECTOR_PC_RELATIVE (TARGET_THUMB2 \
83c3a2d8 1966 || (TARGET_THUMB1 \
907dd0c7
RE		 1967 && (optimize_size || flag_pic)))
1968
1969#define CASE_VECTOR_SHORTEN_MODE(min, max, body) \
83c3a2d8 1970 (TARGET_THUMB1 \
907dd0c7
RE		 1971 ? (min >= 0 && max < 512 \
1972 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 1, QImode) \
1973 : min >= -256 && max < 256 \
1974 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, QImode) \
1975 : min >= 0 && max < 8192 \
1976 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 1, HImode) \
1977 : min >= -4096 && max < 4096 \
1978 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, HImode) \
1979 : SImode) \
10c241af 1980 : ((min < 0 || max >= 0x20000 || !TARGET_THUMB2) ? SImode \
907dd0c7
RE		 1981 : (max >= 0x200) ? HImode \
1982 : QImode))
5b3e6663 1983
ff9940b0
RE		 1984/* signed 'char' is most compatible, but RISC OS wants it unsigned.
1985 unsigned is probably best, but may break some code. */
1986#ifndef DEFAULT_SIGNED_CHAR
3967692c 1987#define DEFAULT_SIGNED_CHAR 0
35d965d5
RS		 1988#endif
1989
35d965d5 1990/* Max number of bytes we can move from memory to memory
d17ce9af
TG		 1991 in one reasonably fast instruction. */
1992#define MOVE_MAX 4
35d965d5 1993
d19fb8e3 1994#undef MOVE_RATIO
e04ad03d 1995#define MOVE_RATIO(speed) (arm_tune_xscale ? 4 : 2)
d19fb8e3 1996
ff9940b0
RE		 1997/* Define if operations between registers always perform the operation
1998 on the full register even if a narrower mode is specified. */
1999#define WORD_REGISTER_OPERATIONS
2000
2001/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2002 will either zero-extend or sign-extend. The value of this macro should
2003 be the code that says which one of the two operations is implicitly
f822d252 2004 done, UNKNOWN if none. */
9c872872 2005#define LOAD_EXTEND_OP(MODE) \
d5b7b3ae
RE		 2006 (TARGET_THUMB ? ZERO_EXTEND : \
2007 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \
f822d252 2008 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : UNKNOWN)))
ff9940b0 2009
35d965d5
RS		 2010/* Nonzero if access to memory by bytes is slow and undesirable. */
2011#define SLOW_BYTE_ACCESS 0
2012
d5b7b3ae 2013#define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1
f676971a 2014
35d965d5
RS		 2015/* Immediate shift counts are truncated by the output routines (or was it
2016 the assembler?). Shift counts in a register are truncated by ARM. Note
2017 that the native compiler puts too large (> 32) immediate shift counts
2018 into a register and shifts by the register, letting the ARM decide what
2019 to do instead of doing that itself. */
ff9940b0
RE		 2020/* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that
2021 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
2022 On the arm, Y in a register is used modulo 256 for the shift. Only for
d6b4baa4 2023 rotates is modulo 32 used. */
ff9940b0 2024/* #define SHIFT_COUNT_TRUNCATED 1 */
35d965d5 2025
35d965d5 2026/* All integers have the same format so truncation is easy. */
d5b7b3ae 2027#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
35d965d5
RS		 2028
2029/* Calling from registers is a massive pain. */
2030#define NO_FUNCTION_CSE 1
2031
35d965d5
RS		 2032/* The machine modes of pointers and functions */
2033#define Pmode SImode
2034#define FUNCTION_MODE Pmode
2035
d5b7b3ae
RE		 2036#define ARM_FRAME_RTX(X) \
2037 ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
3967692c
RE		 2038 || (X) == arg_pointer_rtx)
2039
ff9940b0 2040/* Try to generate sequences that don't involve branches, we can then use
a51fb17f 2041 conditional instructions. */
3a4fd356 2042#define BRANCH_COST(speed_p, predictable_p) \
153668ec
JB		 2043 (current_tune->branch_cost (speed_p, predictable_p))
2044
a51fb17f
BC		 2045/* False if short circuit operation is preferred. */
2046#define LOGICAL_OP_NON_SHORT_CIRCUIT \
2047 ((optimize_size) \
2048 ? (TARGET_THUMB ? false : true) \
2049 : (current_tune->logical_op_non_short_circuit[TARGET_ARM]))
2050
7a801826
RE		 2051\f
2052/* Position Independent Code. */
2053/* We decide which register to use based on the compilation options and
2054 the assembler in use; this is more general than the APCS restriction of
2055 using sb (r9) all the time. */
020a4035 2056extern unsigned arm_pic_register;
7a801826
RE		 2057
2058/* The register number of the register used to address a table of static
2059 data addresses in memory. */
2060#define PIC_OFFSET_TABLE_REGNUM arm_pic_register
2061
f5a1b0d2 2062/* We can't directly access anything that contains a symbol,
d3585b76
DJ		 2063 nor can we indirect via the constant pool. One exception is
2064 UNSPEC_TLS, which is always PIC. */
82e9d970 2065#define LEGITIMATE_PIC_OPERAND_P(X) \
1575c31e
JD		 2066 (!(symbol_mentioned_p (X) \
2067 || label_mentioned_p (X) \
2068 || (GET_CODE (X) == SYMBOL_REF \
2069 && CONSTANT_POOL_ADDRESS_P (X) \
2070 && (symbol_mentioned_p (get_pool_constant (X)) \
d3585b76
DJ		 2071 || label_mentioned_p (get_pool_constant (X))))) \
2072 || tls_mentioned_p (X))
1575c31e 2073
13bd191d
PB		 2074/* We need to know when we are making a constant pool; this determines
2075 whether data needs to be in the GOT or can be referenced via a GOT
2076 offset. */
2077extern int making_const_table;
82e9d970 2078\f
c27ba912 2079/* Handle pragmas for compatibility with Intel's compilers. */
b76c3c4b 2080/* Also abuse this to register additional C specific EABI attributes. */
c58b209a
NB		 2081#define REGISTER_TARGET_PRAGMAS() do { \
2082 c_register_pragma (0, "long_calls", arm_pr_long_calls); \
2083 c_register_pragma (0, "no_long_calls", arm_pr_no_long_calls); \
2084 c_register_pragma (0, "long_calls_off", arm_pr_long_calls_off); \
b76c3c4b 2085 arm_lang_object_attributes_init(); \
8b97c5f8
ZW		 2086} while (0)
2087
d6b4baa4 2088/* Condition code information. */
ff9940b0 2089/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
a5381466 2090 return the mode to be used for the comparison. */
d5b7b3ae
RE		 2091
2092#define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y)
ff9940b0 2093
880873be
RE		 2094#define REVERSIBLE_CC_MODE(MODE) 1
2095
2096#define REVERSE_CONDITION(CODE,MODE) \
2097 (((MODE) == CCFPmode || (MODE) == CCFPEmode) \
2098 ? reverse_condition_maybe_unordered (code) \
2099 : reverse_condition (code))
008cf58a 2100
7dba8395
RH		 2101/* The arm5 clz instruction returns 32. */
2102#define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
ca96ed43 2103#define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
35d965d5 2104\f
906668bb
BS		 2105#define CC_STATUS_INIT \
2106 do { cfun->machine->thumb1_cc_insn = NULL_RTX; } while (0)
2107
d5b7b3ae 2108#undef ASM_APP_OFF
5b3e6663
PB		 2109#define ASM_APP_OFF (TARGET_THUMB1 ? "\t.code\t16\n" : \
2110 TARGET_THUMB2 ? "\t.thumb\n" : "")
35d965d5 2111
2ee67fbb
JB		 2112/* Output a push or a pop instruction (only used when profiling).
2113 We can't push STATIC_CHAIN_REGNUM (r12) directly with Thumb-1. We know
2114 that ASM_OUTPUT_REG_PUSH will be matched with ASM_OUTPUT_REG_POP, and
2115 that r7 isn't used by the function profiler, so we can use it as a
2116 scratch reg. WARNING: This isn't safe in the general case! It may be
2117 sensitive to future changes in final.c:profile_function. */
d5b7b3ae 2118#define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \
8a81cc45
RE		 2119 do \
2120 { \
2121 if (TARGET_ARM) \
2122 asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", \
2123 STACK_POINTER_REGNUM, REGNO); \
2ee67fbb
JB		 2124 else if (TARGET_THUMB1 \
2125 && (REGNO) == STATIC_CHAIN_REGNUM) \
2126 { \
2127 asm_fprintf (STREAM, "\tpush\t{r7}\n"); \
2128 asm_fprintf (STREAM, "\tmov\tr7, %r\n", REGNO);\
2129 asm_fprintf (STREAM, "\tpush\t{r7}\n"); \
2130 } \
8a81cc45
RE		 2131 else \
2132 asm_fprintf (STREAM, "\tpush {%r}\n", REGNO); \
2133 } while (0)
d5b7b3ae
RE		 2134
2135
2ee67fbb 2136/* See comment for ASM_OUTPUT_REG_PUSH concerning Thumb-1 issue. */
d5b7b3ae 2137#define ASM_OUTPUT_REG_POP(STREAM, REGNO) \
8a81cc45
RE		 2138 do \
2139 { \
2140 if (TARGET_ARM) \
2141 asm_fprintf (STREAM, "\tldmfd\t%r!,{%r}\n", \
2142 STACK_POINTER_REGNUM, REGNO); \
2ee67fbb
JB		 2143 else if (TARGET_THUMB1 \
2144 && (REGNO) == STATIC_CHAIN_REGNUM) \
2145 { \
2146 asm_fprintf (STREAM, "\tpop\t{r7}\n"); \
2147 asm_fprintf (STREAM, "\tmov\t%r, r7\n", REGNO);\
2148 asm_fprintf (STREAM, "\tpop\t{r7}\n"); \
2149 } \
8a81cc45
RE		 2150 else \
2151 asm_fprintf (STREAM, "\tpop {%r}\n", REGNO); \
2152 } while (0)
d5b7b3ae 2153
b0fe107e
JM		 2154#define ADDR_VEC_ALIGN(JUMPTABLE) \
2155 ((TARGET_THUMB && GET_MODE (PATTERN (JUMPTABLE)) == SImode) ? 2 : 0)
2156
2157/* Alignment for case labels comes from ADDR_VEC_ALIGN; avoid the
2158 default alignment from elfos.h. */
2159#undef ASM_OUTPUT_BEFORE_CASE_LABEL
2160#define ASM_OUTPUT_BEFORE_CASE_LABEL(FILE, PREFIX, NUM, TABLE) /* Empty. */
5b3e6663
PB		 2161
2162/* Make sure subsequent insns are aligned after a TBB. */
2163#define ASM_OUTPUT_CASE_END(FILE, NUM, JUMPTABLE) \
2164 do \
2165 { \
2166 if (GET_MODE (PATTERN (JUMPTABLE)) == QImode) \
2167 ASM_OUTPUT_ALIGN (FILE, 1); \
2168 } \
d5b7b3ae 2169 while (0)
35d965d5 2170
6cfc7210
NC		 2171#define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \
2172 do \
2173 { \
d5b7b3ae
RE		 2174 if (TARGET_THUMB) \
2175 { \
5b3e6663 2176 if (is_called_in_ARM_mode (DECL) \
bf98ec6c 2177 || (TARGET_THUMB1 && !TARGET_THUMB1_ONLY \
3c072c6b 2178 && cfun->is_thunk)) \
d5b7b3ae 2179 fprintf (STREAM, "\t.code 32\n") ; \
5b3e6663
PB		 2180 else if (TARGET_THUMB1) \
2181 fprintf (STREAM, "\t.code\t16\n\t.thumb_func\n") ; \
d5b7b3ae 2182 else \
5b3e6663 2183 fprintf (STREAM, "\t.thumb\n\t.thumb_func\n") ; \
d5b7b3ae 2184 } \
6cfc7210 2185 if (TARGET_POKE_FUNCTION_NAME) \
586de218 2186 arm_poke_function_name (STREAM, (const char *) NAME); \
6cfc7210
NC		 2187 } \
2188 while (0)
35d965d5 2189
d5b7b3ae
RE		 2190/* For aliases of functions we use .thumb_set instead. */
2191#define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \
2192 do \
2193 { \
91ea4f8d
KG		 2194 const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \
2195 const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \
d5b7b3ae
RE		 2196 \
2197 if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \
2198 { \
2199 fprintf (FILE, "\t.thumb_set "); \
2200 assemble_name (FILE, LABEL1); \
2201 fprintf (FILE, ","); \
2202 assemble_name (FILE, LABEL2); \
2203 fprintf (FILE, "\n"); \
2204 } \
2205 else \
2206 ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \
2207 } \
2208 while (0)
2209
fdc2d3b0
NC		 2210#ifdef HAVE_GAS_MAX_SKIP_P2ALIGN
2211/* To support -falign-* switches we need to use .p2align so
2212 that alignment directives in code sections will be padded
2213 with no-op instructions, rather than zeroes. */
5a9335ef 2214#define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE, LOG, MAX_SKIP) \
fdc2d3b0
NC		 2215 if ((LOG) != 0) \
2216 { \
2217 if ((MAX_SKIP) == 0) \
5a9335ef 2218 fprintf ((FILE), "\t.p2align %d\n", (int) (LOG)); \
fdc2d3b0
NC		 2219 else \
2220 fprintf ((FILE), "\t.p2align %d,,%d\n", \
5a9335ef 2221 (int) (LOG), (int) (MAX_SKIP)); \
fdc2d3b0
NC		 2222 }
2223#endif
35d965d5 2224\f
5b3e6663
PB		 2225/* Add two bytes to the length of conditionally executed Thumb-2
2226 instructions for the IT instruction. */
2227#define ADJUST_INSN_LENGTH(insn, length) \
2228 if (TARGET_THUMB2 && GET_CODE (PATTERN (insn)) == COND_EXEC) \
2229 length += 2;
2230
35d965d5 2231/* Only perform branch elimination (by making instructions conditional) if
5b3e6663
PB		 2232 we're optimizing. For Thumb-2 check if any IT instructions need
2233 outputting. */
d5b7b3ae
RE		 2234#define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2235 if (TARGET_ARM && optimize) \
2236 arm_final_prescan_insn (INSN); \
5b3e6663
PB		 2237 else if (TARGET_THUMB2) \
2238 thumb2_final_prescan_insn (INSN); \
2239 else if (TARGET_THUMB1) \
2240 thumb1_final_prescan_insn (INSN)
35d965d5 2241
7b8b8ade
NC		 2242#define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \
2243 (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \
30cf4896
KG		 2244 : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\
2245 ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \
2246 ? ((~ (unsigned HOST_WIDE_INT) 0) \
2247 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \
7bc7696c 2248 : 0))))
35d965d5 2249
6a5d7526
MS		 2250/* A C expression whose value is RTL representing the value of the return
2251 address for the frame COUNT steps up from the current frame. */
2252
d5b7b3ae
RE		 2253#define RETURN_ADDR_RTX(COUNT, FRAME) \
2254 arm_return_addr (COUNT, FRAME)
2255
f676971a 2256/* Mask of the bits in the PC that contain the real return address
d5b7b3ae
RE		 2257 when running in 26-bit mode. */
2258#define RETURN_ADDR_MASK26 (0x03fffffc)
6a5d7526 2259
2c849145
JM		 2260/* Pick up the return address upon entry to a procedure. Used for
2261 dwarf2 unwind information. This also enables the table driven
2262 mechanism. */
2c849145
JM		 2263#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM)
2264#define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM)
2265
39950dff
MS		 2266/* Used to mask out junk bits from the return address, such as
2267 processor state, interrupt status, condition codes and the like. */
2268#define MASK_RETURN_ADDR \
2269 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \
2270 in 26 bit mode, the condition codes must be masked out of the \
2271 return address. This does not apply to ARM6 and later processors \
2272 when running in 32 bit mode. */ \
61f0ccff
RE		 2273 ((arm_arch4 || TARGET_THUMB) \
2274 ? (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \
fcd53748 2275 : arm_gen_return_addr_mask ())
d5b7b3ae
RE		 2276
2277\f
978e411f
CD		 2278/* Do not emit .note.GNU-stack by default. */
2279#ifndef NEED_INDICATE_EXEC_STACK
2280#define NEED_INDICATE_EXEC_STACK 0
2281#endif
2282
9e94a7fc
MGD		 2283#define TARGET_ARM_ARCH \
2284 (arm_base_arch) \
2285
2286#define TARGET_ARM_V6M (!arm_arch_notm && !arm_arch_thumb2)
2287#define TARGET_ARM_V7M (!arm_arch_notm && arm_arch_thumb2)
2288
2289/* The highest Thumb instruction set version supported by the chip. */
2290#define TARGET_ARM_ARCH_ISA_THUMB \
2291 (arm_arch_thumb2 ? 2 \
2292 : ((TARGET_ARM_ARCH >= 5 || arm_arch4t) ? 1 : 0))
2293
2294/* Expands to an upper-case char of the target's architectural
2295 profile. */
2296#define TARGET_ARM_ARCH_PROFILE \
2297 (!arm_arch_notm \
2298 ? 'M' \
2299 : (arm_arch7 \
2300 ? (strlen (arm_arch_name) >=3 \
2301 ? (arm_arch_name[strlen (arm_arch_name) - 3]) \
2302 : 0) \
2303 : 0))
2304
2305/* Bit-field indicating what size LDREX/STREX loads/stores are available.
2306 Bit 0 for bytes, up to bit 3 for double-words. */
2307#define TARGET_ARM_FEATURE_LDREX \
2308 ((TARGET_HAVE_LDREX ? 4 : 0) \
2309 | (TARGET_HAVE_LDREXBH ? 3 : 0) \
2310 | (TARGET_HAVE_LDREXD ? 8 : 0))
2311
2312/* Set as a bit mask indicating the available widths of hardware floating
2313 point types. Where bit 1 indicates 16-bit support, bit 2 indicates
2314 32-bit support, bit 3 indicates 64-bit support. */
2315#define TARGET_ARM_FP \
2316 (TARGET_VFP_SINGLE ? 4 \
2317 : (TARGET_VFP_DOUBLE ? (TARGET_FP16 ? 14 : 12) : 0))
2318
2319
2320/* Set as a bit mask indicating the available widths of floating point
2321 types for hardware NEON floating point. This is the same as
2322 TARGET_ARM_FP without the 64-bit bit set. */
2323#ifdef TARGET_NEON
2324#define TARGET_NEON_FP \
2325 (TARGET_ARM_FP & (0xff ^ 0x08))
2326#endif
2327
93b338c3
BS		 2328/* The maximum number of parallel loads or stores we support in an ldm/stm
2329 instruction. */
2330#define MAX_LDM_STM_OPS 4
2331
54e73f88
AS		 2332#define ASM_CPU_SPEC \
2333 " %{mcpu=generic-*:-march=%*;" \
2334 " :%{mcpu=*:-mcpu=%*} %{march=*:-march=%*}}"
2335
33aa08b3
AS		 2336/* -mcpu=native handling only makes sense with compiler running on
2337 an ARM chip. */
2338#if defined(__arm__)
2339extern const char *host_detect_local_cpu (int argc, const char **argv);
2340# define EXTRA_SPEC_FUNCTIONS \
2341 { "local_cpu_detect", host_detect_local_cpu },
2342
2343# define MCPU_MTUNE_NATIVE_SPECS \
2344 " %{march=native:%<march=native %:local_cpu_detect(arch)}" \
2345 " %{mcpu=native:%<mcpu=native %:local_cpu_detect(cpu)}" \
2346 " %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}"
2347#else
2348# define MCPU_MTUNE_NATIVE_SPECS ""
2349#endif
2350
2351#define DRIVER_SELF_SPECS MCPU_MTUNE_NATIVE_SPECS
2352
88657302 2353#endif /* ! GCC_ARM_H */
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