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Support '-plugin' as the second option to the linker.
[thirdparty/gcc.git] / gcc / config / arm / arm.h
CommitLineData
f5a1b0d2 1/* Definitions of target machine for GNU compiler, for ARM.
cf011243 2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
c5387660 3 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
bf98ec6c 4 Free Software Foundation, Inc.
35d965d5 5 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
8b109b37 6 and Martin Simmons (@harleqn.co.uk).
949d79eb 7 More major hacks by Richard Earnshaw (rearnsha@arm.com)
6cfc7210
NC		 8 Minor hacks by Nick Clifton (nickc@cygnus.com)
9
4f448245 10 This file is part of GCC.
35d965d5 11
4f448245
NC		 12 GCC is free software; you can redistribute it and/or modify it
13 under the terms of the GNU General Public License as published
2f83c7d6 14 by the Free Software Foundation; either version 3, or (at your
4f448245 15 option) any later version.
35d965d5 16
4f448245
NC		 17 GCC is distributed in the hope that it will be useful, but WITHOUT
18 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
19 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
20 License for more details.
35d965d5 21
4f448245 22 You should have received a copy of the GNU General Public License
2f83c7d6
NC		 23 along with GCC; see the file COPYING3. If not see
24 <http://www.gnu.org/licenses/>. */
35d965d5 25
88657302
RH		 26#ifndef GCC_ARM_H
27#define GCC_ARM_H
b355a481 28
46107b99
RE		 29/* We can't use enum machine_mode inside a generator file because it
30 hasn't been created yet; we shouldn't be using any code that
31 needs the real definition though, so this ought to be safe. */
32#ifdef GENERATOR_FILE
33#define MACHMODE int
34#else
35#include "insn-modes.h"
36#define MACHMODE enum machine_mode
37#endif
38
9403b7f7
RS		 39#include "config/vxworks-dummy.h"
40
35fd3193 41/* The architecture define. */
78011587
PB		 42extern char arm_arch_name[];
43
e6471be6
NB		 44/* Target CPU builtins. */
45#define TARGET_CPU_CPP_BUILTINS() \
46 do \
47 { \
9b66ebb1
PB		 48 /* Define __arm__ even when in thumb mode, for \
49 consistency with armcc. */ \
50 builtin_define ("__arm__"); \
61f0ccff 51 builtin_define ("__APCS_32__"); \
9b66ebb1 52 if (TARGET_THUMB) \
e6471be6 53 builtin_define ("__thumb__"); \
5b3e6663
PB		 54 if (TARGET_THUMB2) \
55 builtin_define ("__thumb2__"); \
e6471be6
NB		 56 \
57 if (TARGET_BIG_END) \
58 { \
59 builtin_define ("__ARMEB__"); \
60 if (TARGET_THUMB) \
61 builtin_define ("__THUMBEB__"); \
62 if (TARGET_LITTLE_WORDS) \
63 builtin_define ("__ARMWEL__"); \
64 } \
65 else \
66 { \
67 builtin_define ("__ARMEL__"); \
68 if (TARGET_THUMB) \
69 builtin_define ("__THUMBEL__"); \
70 } \
71 \
e6471be6
NB		 72 if (TARGET_SOFT_FLOAT) \
73 builtin_define ("__SOFTFP__"); \
74 \
9b66ebb1 75 if (TARGET_VFP) \
b5b620a4
JT		 76 builtin_define ("__VFP_FP__"); \
77 \
88f77cba
JB		 78 if (TARGET_NEON) \
79 builtin_define ("__ARM_NEON__"); \
80 \
e6471be6
NB		 81 /* Add a define for interworking. \
82 Needed when building libgcc.a. */ \
2ad4dcf9 83 if (arm_cpp_interwork) \
e6471be6
NB		 84 builtin_define ("__THUMB_INTERWORK__"); \
85 \
86 builtin_assert ("cpu=arm"); \
87 builtin_assert ("machine=arm"); \
78011587
PB		 88 \
89 builtin_define (arm_arch_name); \
90 if (arm_arch_cirrus) \
91 builtin_define ("__MAVERICK__"); \
92 if (arm_arch_xscale) \
93 builtin_define ("__XSCALE__"); \
94 if (arm_arch_iwmmxt) \
95 builtin_define ("__IWMMXT__"); \
4adf3e34 96 if (TARGET_AAPCS_BASED) \
12ffc7d5
CLT		 97 { \
98 if (arm_pcs_default == ARM_PCS_AAPCS_VFP) \
99 builtin_define ("__ARM_PCS_VFP"); \
100 else if (arm_pcs_default == ARM_PCS_AAPCS) \
101 builtin_define ("__ARM_PCS"); \
102 builtin_define ("__ARM_EABI__"); \
103 } \
e6471be6
NB		 104 } while (0)
105
9b66ebb1
PB		 106/* The various ARM cores. */
107enum processor_type
108{
d98a72fd
RE		 109#define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
110 IDENT,
9b66ebb1
PB		 111#include "arm-cores.def"
112#undef ARM_CORE
113 /* Used to indicate that no processor has been specified. */
114 arm_none
115};
116
78011587
PB		 117enum target_cpus
118{
d98a72fd
RE		 119#define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
120 TARGET_CPU_##IDENT,
78011587
PB		 121#include "arm-cores.def"
122#undef ARM_CORE
123 TARGET_CPU_generic
124};
125
9b66ebb1
PB		 126/* The processor for which instructions should be scheduled. */
127extern enum processor_type arm_tune;
128
029e79eb
MS		 129enum arm_sync_generator_tag
130 {
131 arm_sync_generator_omn,
132 arm_sync_generator_omrn
133 };
134
135/* Wrapper to pass around a polymorphic pointer to a sync instruction
136 generator and. */
137struct arm_sync_generator
138{
139 enum arm_sync_generator_tag op;
140 union
141 {
142 rtx (* omn) (rtx, rtx, rtx);
143 rtx (* omrn) (rtx, rtx, rtx, rtx);
144 } u;
145};
146
d5b7b3ae 147typedef enum arm_cond_code
89c7ca52
RE		 148{
149 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC,
150 ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV
d5b7b3ae
RE		 151}
152arm_cc;
6cfc7210 153
d5b7b3ae 154extern arm_cc arm_current_cc;
ff9940b0 155
d5b7b3ae 156#define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1))
89c7ca52 157
6cfc7210
NC		 158extern int arm_target_label;
159extern int arm_ccfsm_state;
e2500fed 160extern GTY(()) rtx arm_target_insn;
d5b7b3ae 161/* The label of the current constant pool. */
e2500fed 162extern rtx pool_vector_label;
d5b7b3ae 163/* Set to 1 when a return insn is output, this means that the epilogue
d6b4baa4 164 is not needed. */
d5b7b3ae 165extern int return_used_this_function;
b76c3c4b
PB		 166/* Callback to output language specific object attributes. */
167extern void (*arm_lang_output_object_attributes_hook)(void);
35d965d5 168\f
d6b4baa4 169/* Just in case configure has failed to define anything. */
7a801826
RE		 170#ifndef TARGET_CPU_DEFAULT
171#define TARGET_CPU_DEFAULT TARGET_CPU_generic
172#endif
173
7a801826 174
5742588d 175#undef CPP_SPEC
78011587 176#define CPP_SPEC "%(subtarget_cpp_spec) \
e6471be6
NB		 177%{msoft-float:%{mhard-float: \
178 %e-msoft-float and -mhard_float may not be used together}} \
179%{mbig-endian:%{mlittle-endian: \
180 %e-mbig-endian and -mlittle-endian may not be used together}}"
7a801826 181
be393ecf 182#ifndef CC1_SPEC
dfa08768 183#define CC1_SPEC ""
be393ecf 184#endif
7a801826
RE		 185
186/* This macro defines names of additional specifications to put in the specs
187 that can be used in various specifications like CC1_SPEC. Its definition
188 is an initializer with a subgrouping for each command option.
189
190 Each subgrouping contains a string constant, that defines the
4f448245 191 specification name, and a string constant that used by the GCC driver
7a801826
RE		 192 program.
193
194 Do not define this macro if it does not need to do anything. */
195#define EXTRA_SPECS \
38fc909b 196 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
7a801826
RE		 197 SUBTARGET_EXTRA_SPECS
198
914a3b8c 199#ifndef SUBTARGET_EXTRA_SPECS
7a801826 200#define SUBTARGET_EXTRA_SPECS
914a3b8c
DM		 201#endif
202
6cfc7210 203#ifndef SUBTARGET_CPP_SPEC
38fc909b 204#define SUBTARGET_CPP_SPEC ""
6cfc7210 205#endif
35d965d5
RS		 206\f
207/* Run-time Target Specification. */
ff9940b0 208#ifndef TARGET_VERSION
6cfc7210 209#define TARGET_VERSION fputs (" (ARM/generic)", stderr);
ff9940b0 210#endif
35d965d5 211
9b66ebb1 212#define TARGET_SOFT_FLOAT (arm_float_abi == ARM_FLOAT_ABI_SOFT)
72cdc543
PB		 213/* Use hardware floating point instructions. */
214#define TARGET_HARD_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT)
215/* Use hardware floating point calling convention. */
216#define TARGET_HARD_FLOAT_ABI (arm_float_abi == ARM_FLOAT_ABI_HARD)
d79f3032
PB		 217#define TARGET_FPA (arm_fpu_desc->model == ARM_FP_MODEL_FPA)
218#define TARGET_MAVERICK (arm_fpu_desc->model == ARM_FP_MODEL_MAVERICK)
219#define TARGET_VFP (arm_fpu_desc->model == ARM_FP_MODEL_VFP)
5a9335ef 220#define TARGET_IWMMXT (arm_arch_iwmmxt)
5b3e6663
PB		 221#define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_32BIT)
222#define TARGET_IWMMXT_ABI (TARGET_32BIT && arm_abi == ARM_ABI_IWMMXT)
d5b7b3ae
RE		 223#define TARGET_ARM (! TARGET_THUMB)
224#define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */
c54c7322
RS		 225#define TARGET_BACKTRACE (leaf_function_p () \
226 ? TARGET_TPCS_LEAF_FRAME \
227 : TARGET_TPCS_FRAME)
fdd695fd 228#define TARGET_LDRD (arm_arch5e && ARM_DOUBLEWORD_ALIGN)
b6685939
PB		 229#define TARGET_AAPCS_BASED \
230 (arm_abi != ARM_ABI_APCS && arm_abi != ARM_ABI_ATPCS)
3ada8e17 231
d3585b76
DJ		 232#define TARGET_HARD_TP (target_thread_pointer == TP_CP15)
233#define TARGET_SOFT_TP (target_thread_pointer == TP_SOFT)
234
5b3e6663
PB		 235/* Only 16-bit thumb code. */
236#define TARGET_THUMB1 (TARGET_THUMB && !arm_arch_thumb2)
237/* Arm or Thumb-2 32-bit code. */
238#define TARGET_32BIT (TARGET_ARM || arm_arch_thumb2)
239/* 32-bit Thumb-2 code. */
240#define TARGET_THUMB2 (TARGET_THUMB && arm_arch_thumb2)
bf98ec6c
PB		 241/* Thumb-1 only. */
242#define TARGET_THUMB1_ONLY (TARGET_THUMB1 && !arm_arch_notm)
d79f3032
PB		 243/* FPA emulator without LFM. */
244#define TARGET_FPA_EMU2 (TARGET_FPA && arm_fpu_desc->rev == 2)
5b3e6663 245
88f77cba 246/* The following two macros concern the ability to execute coprocessor
302c3d8e
PB		 247 instructions for VFPv3 or NEON. TARGET_VFP3/TARGET_VFPD32 are currently
248 only ever tested when we know we are generating for VFP hardware; we need
249 to be more careful with TARGET_NEON as noted below. */
88f77cba 250
302c3d8e 251/* FPU is has the full VFPv3/NEON register file of 32 D registers. */
d79f3032 252#define TARGET_VFPD32 (TARGET_VFP && arm_fpu_desc->regs == VFP_REG_D32)
302c3d8e
PB		 253
254/* FPU supports VFPv3 instructions. */
d79f3032 255#define TARGET_VFP3 (TARGET_VFP && arm_fpu_desc->rev >= 3)
302c3d8e 256
e0dc3601
PB		 257/* FPU only supports VFP single-precision instructions. */
258#define TARGET_VFP_SINGLE (TARGET_VFP && arm_fpu_desc->regs == VFP_REG_SINGLE)
259
260/* FPU supports VFP double-precision instructions. */
261#define TARGET_VFP_DOUBLE (TARGET_VFP && arm_fpu_desc->regs != VFP_REG_SINGLE)
262
263/* FPU supports half-precision floating-point with NEON element load/store. */
d79f3032
PB		 264#define TARGET_NEON_FP16 \
265 (TARGET_VFP && arm_fpu_desc->neon && arm_fpu_desc->fp16)
0fd8c3ad 266
e0dc3601
PB		 267/* FPU supports VFP half-precision floating-point. */
268#define TARGET_FP16 (TARGET_VFP && arm_fpu_desc->fp16)
269
88f77cba
JB		 270/* FPU supports Neon instructions. The setting of this macro gets
271 revealed via __ARM_NEON__ so we add extra guards upon TARGET_32BIT
272 and TARGET_HARD_FLOAT to ensure that NEON instructions are
273 available. */
274#define TARGET_NEON (TARGET_32BIT && TARGET_HARD_FLOAT \
d79f3032 275 && TARGET_VFP && arm_fpu_desc->neon)
f1adb0a9 276
5b3e6663
PB		 277/* "DSP" multiply instructions, eg. SMULxy. */
278#define TARGET_DSP_MULTIPLY \
60bd3528 279 (TARGET_32BIT && arm_arch5e && (arm_arch_notm || arm_arch7em))
5b3e6663
PB		 280/* Integer SIMD instructions, and extend-accumulate instructions. */
281#define TARGET_INT_SIMD \
60bd3528 282 (TARGET_32BIT && arm_arch6 && (arm_arch_notm || arm_arch7em))
5b3e6663 283
571191af
PB		 284/* Should MOVW/MOVT be used in preference to a constant pool. */
285#define TARGET_USE_MOVT (arm_arch_thumb2 && !optimize_size)
286
5b3e6663
PB		 287/* We could use unified syntax for arm mode, but for now we just use it
288 for Thumb-2. */
289#define TARGET_UNIFIED_ASM TARGET_THUMB2
290
029e79eb
MS		 291/* Nonzero if this chip provides the DMB instruction. */
292#define TARGET_HAVE_DMB (arm_arch7)
293
294/* Nonzero if this chip implements a memory barrier via CP15. */
295#define TARGET_HAVE_DMB_MCR (arm_arch6k && ! TARGET_HAVE_DMB)
296
297/* Nonzero if this chip implements a memory barrier instruction. */
298#define TARGET_HAVE_MEMORY_BARRIER (TARGET_HAVE_DMB || TARGET_HAVE_DMB_MCR)
299
300/* Nonzero if this chip supports ldrex and strex */
301#define TARGET_HAVE_LDREX ((arm_arch6 && TARGET_ARM) || arm_arch7)
302
303/* Nonzero if this chip supports ldrex{bhd} and strex{bhd}. */
304#define TARGET_HAVE_LDREXBHD ((arm_arch6k && TARGET_ARM) || arm_arch7)
5b3e6663 305
b3f8d95d
MM		 306/* True iff the full BPABI is being used. If TARGET_BPABI is true,
307 then TARGET_AAPCS_BASED must be true -- but the converse does not
308 hold. TARGET_BPABI implies the use of the BPABI runtime library,
309 etc., in addition to just the AAPCS calling conventions. */
310#ifndef TARGET_BPABI
311#define TARGET_BPABI false
f676971a 312#endif
b3f8d95d 313
7816bea0
DJ		 314/* Support for a compile-time default CPU, et cetera. The rules are:
315 --with-arch is ignored if -march or -mcpu are specified.
316 --with-cpu is ignored if -march or -mcpu are specified, and is overridden
317 by --with-arch.
318 --with-tune is ignored if -mtune or -mcpu are specified (but not affected
319 by -march).
9b66ebb1
PB		 320 --with-float is ignored if -mhard-float, -msoft-float or -mfloat-abi are
321 specified.
5848830f
PB		 322 --with-fpu is ignored if -mfpu is specified.
323 --with-abi is ignored is -mabi is specified. */
7816bea0
DJ		 324#define OPTION_DEFAULT_SPECS \
325 {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \
326 {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \
327 {"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}" }, \
9b66ebb1
PB		 328 {"float", \
329 "%{!msoft-float:%{!mhard-float:%{!mfloat-abi=*:-mfloat-abi=%(VALUE)}}}" }, \
5848830f 330 {"fpu", "%{!mfpu=*:-mfpu=%(VALUE)}"}, \
3cf94279
PB		 331 {"abi", "%{!mabi=*:-mabi=%(VALUE)}"}, \
332 {"mode", "%{!marm:%{!mthumb:-m%(VALUE)}}"},
7816bea0 333
9b66ebb1
PB		 334/* Which floating point model to use. */
335enum arm_fp_model
336{
337 ARM_FP_MODEL_UNKNOWN,
338 /* FPA model (Hardware or software). */
339 ARM_FP_MODEL_FPA,
340 /* Cirrus Maverick floating point model. */
341 ARM_FP_MODEL_MAVERICK,
342 /* VFP floating point model. */
343 ARM_FP_MODEL_VFP
344};
345
d79f3032 346enum vfp_reg_type
24f0c1b4 347{
70dd156a 348 VFP_NONE = 0,
d79f3032
PB		 349 VFP_REG_D16,
350 VFP_REG_D32,
351 VFP_REG_SINGLE
24f0c1b4
RE		 352};
353
d79f3032
PB		 354extern const struct arm_fpu_desc
355{
356 const char *name;
357 enum arm_fp_model model;
358 int rev;
359 enum vfp_reg_type regs;
360 int neon;
361 int fp16;
362} *arm_fpu_desc;
363
364/* Which floating point hardware to schedule for. */
365extern int arm_fpu_attr;
71791e16 366
9b66ebb1
PB		 367enum float_abi_type
368{
369 ARM_FLOAT_ABI_SOFT,
370 ARM_FLOAT_ABI_SOFTFP,
371 ARM_FLOAT_ABI_HARD
372};
373
374extern enum float_abi_type arm_float_abi;
375
3d8532aa
PB		 376#ifndef TARGET_DEFAULT_FLOAT_ABI
377#define TARGET_DEFAULT_FLOAT_ABI ARM_FLOAT_ABI_SOFT
378#endif
379
0fd8c3ad
SL		 380/* Which __fp16 format to use.
381 The enumeration values correspond to the numbering for the
382 Tag_ABI_FP_16bit_format attribute.
383 */
384enum arm_fp16_format_type
385{
386 ARM_FP16_FORMAT_NONE = 0,
387 ARM_FP16_FORMAT_IEEE = 1,
388 ARM_FP16_FORMAT_ALTERNATIVE = 2
389};
390
391extern enum arm_fp16_format_type arm_fp16_format;
392#define LARGEST_EXPONENT_IS_NORMAL(bits) \
393 ((bits) == 16 && arm_fp16_format == ARM_FP16_FORMAT_ALTERNATIVE)
394
5848830f
PB		 395/* Which ABI to use. */
396enum arm_abi_type
397{
398 ARM_ABI_APCS,
399 ARM_ABI_ATPCS,
400 ARM_ABI_AAPCS,
077fc835
KH		 401 ARM_ABI_IWMMXT,
402 ARM_ABI_AAPCS_LINUX
5848830f
PB		 403};
404
405extern enum arm_abi_type arm_abi;
406
407#ifndef ARM_DEFAULT_ABI
408#define ARM_DEFAULT_ABI ARM_ABI_APCS
409#endif
410
d3585b76
DJ		 411/* Which thread pointer access sequence to use. */
412enum arm_tp_type {
413 TP_AUTO,
414 TP_SOFT,
415 TP_CP15
416};
417
418extern enum arm_tp_type target_thread_pointer;
419
9b66ebb1
PB		 420/* Nonzero if this chip supports the ARM Architecture 3M extensions. */
421extern int arm_arch3m;
11c1a207 422
9b66ebb1 423/* Nonzero if this chip supports the ARM Architecture 4 extensions. */
11c1a207
RE		 424extern int arm_arch4;
425
68d560d4
RE		 426/* Nonzero if this chip supports the ARM Architecture 4T extensions. */
427extern int arm_arch4t;
428
9b66ebb1 429/* Nonzero if this chip supports the ARM Architecture 5 extensions. */
62b10bbc
NC		 430extern int arm_arch5;
431
9b66ebb1 432/* Nonzero if this chip supports the ARM Architecture 5E extensions. */
b15bca31
RE		 433extern int arm_arch5e;
434
9b66ebb1
PB		 435/* Nonzero if this chip supports the ARM Architecture 6 extensions. */
436extern int arm_arch6;
437
029e79eb
MS		 438/* Nonzero if this chip supports the ARM Architecture 6k extensions. */
439extern int arm_arch6k;
440
441/* Nonzero if this chip supports the ARM Architecture 7 extensions. */
442extern int arm_arch7;
443
5b3e6663
PB		 444/* Nonzero if instructions not present in the 'M' profile can be used. */
445extern int arm_arch_notm;
446
60bd3528
PB		 447/* Nonzero if instructions present in ARMv7E-M can be used. */
448extern int arm_arch7em;
449
f5a1b0d2
NC		 450/* Nonzero if this chip can benefit from load scheduling. */
451extern int arm_ld_sched;
452
906668bb 453/* Nonzero if generating Thumb code, either Thumb-1 or Thumb-2. */
0616531f
RE		 454extern int thumb_code;
455
906668bb
BS		 456/* Nonzero if generating Thumb-1 code. */
457extern int thumb1_code;
458
f5a1b0d2 459/* Nonzero if this chip is a StrongARM. */
abac3b49 460extern int arm_tune_strongarm;
f5a1b0d2 461
9b6b54e2 462/* Nonzero if this chip is a Cirrus variant. */
78011587 463extern int arm_arch_cirrus;
9b6b54e2 464
5a9335ef
NC		 465/* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */
466extern int arm_arch_iwmmxt;
467
d19fb8e3 468/* Nonzero if this chip is an XScale. */
4b3c2e48
PB		 469extern int arm_arch_xscale;
470
abac3b49 471/* Nonzero if tuning for XScale. */
4b3c2e48 472extern int arm_tune_xscale;
d19fb8e3 473
abac3b49
RE		 474/* Nonzero if tuning for stores via the write buffer. */
475extern int arm_tune_wbuf;
f5a1b0d2 476
7612f14d
PB		 477/* Nonzero if tuning for Cortex-A9. */
478extern int arm_tune_cortex_a9;
479
2ad4dcf9 480/* Nonzero if we should define __THUMB_INTERWORK__ in the
f676971a 481 preprocessor.
2ad4dcf9
RE		 482 XXX This is a bit of a hack, it's intended to help work around
483 problems in GLD which doesn't understand that armv5t code is
484 interworking clean. */
485extern int arm_cpp_interwork;
486
5b3e6663
PB		 487/* Nonzero if chip supports Thumb 2. */
488extern int arm_arch_thumb2;
489
490/* Nonzero if chip supports integer division instruction. */
491extern int arm_arch_hwdiv;
492
2ce9c1b9 493#ifndef TARGET_DEFAULT
c54c7322 494#define TARGET_DEFAULT (MASK_APCS_FRAME)
2ce9c1b9 495#endif
35d965d5 496
11c1a207
RE		 497/* The frame pointer register used in gcc has nothing to do with debugging;
498 that is controlled by the APCS-FRAME option. */
d5b7b3ae 499#define CAN_DEBUG_WITHOUT_FP
35d965d5 500
86efdc8e
PB		 501/* Nonzero if PIC code requires explicit qualifiers to generate
502 PLT and GOT relocs rather than the assembler doing so implicitly.
ed0e6530
PB		 503 Subtargets can override these if required. */
504#ifndef NEED_GOT_RELOC
505#define NEED_GOT_RELOC 0
506#endif
507#ifndef NEED_PLT_RELOC
508#define NEED_PLT_RELOC 0
e2723c62 509#endif
84306176
PB		 510
511/* Nonzero if we need to refer to the GOT with a PC-relative
512 offset. In other words, generate
513
f676971a 514 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)]
84306176
PB		 515
516 rather than
517
518 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8)
519
f676971a 520 The default is true, which matches NetBSD. Subtargets can
84306176
PB		 521 override this if required. */
522#ifndef GOT_PCREL
523#define GOT_PCREL 1
524#endif
35d965d5
RS		 525\f
526/* Target machine storage Layout. */
527
ff9940b0
RE		 528
529/* Define this macro if it is advisable to hold scalars in registers
530 in a wider mode than that declared by the program. In such cases,
531 the value is constrained to be within the bounds of the declared
532 type, but kept valid in the wider mode. The signedness of the
533 extension may differ from that of the type. */
534
535/* It is far faster to zero extend chars than to sign extend them */
536
6cfc7210 537#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
2ce9c1b9
RE		 538 if (GET_MODE_CLASS (MODE) == MODE_INT \
539 && GET_MODE_SIZE (MODE) < 4) \
540 { \
541 if (MODE == QImode) \
542 UNSIGNEDP = 1; \
543 else if (MODE == HImode) \
61f0ccff 544 UNSIGNEDP = 1; \
2ce9c1b9 545 (MODE) = SImode; \
ff9940b0
RE		 546 }
547
35d965d5
RS		 548/* Define this if most significant bit is lowest numbered
549 in instructions that operate on numbered bit-fields. */
550#define BITS_BIG_ENDIAN 0
551
f676971a 552/* Define this if most significant byte of a word is the lowest numbered.
3ada8e17
DE		 553 Most ARM processors are run in little endian mode, so that is the default.
554 If you want to have it run-time selectable, change the definition in a
555 cover file to be TARGET_BIG_ENDIAN. */
11c1a207 556#define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
35d965d5
RS		 557
558/* Define this if most significant word of a multiword number is the lowest
11c1a207
RE		 559 numbered.
560 This is always false, even when in big-endian mode. */
ddee6aba
RE		 561#define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS)
562
563/* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based
564 on processor pre-defineds when compiling libgcc2.c. */
565#if defined(__ARMEB__) && !defined(__ARMWEL__)
566#define LIBGCC2_WORDS_BIG_ENDIAN 1
567#else
568#define LIBGCC2_WORDS_BIG_ENDIAN 0
569#endif
35d965d5 570
11c1a207 571/* Define this if most significant word of doubles is the lowest numbered.
f0375c66
NC		 572 The rules are different based on whether or not we use FPA-format,
573 VFP-format or some other floating point co-processor's format doubles. */
b5b620a4 574#define FLOAT_WORDS_BIG_ENDIAN (arm_float_words_big_endian ())
7fc6c9f0 575
35d965d5
RS		 576#define UNITS_PER_WORD 4
577
5848830f 578/* True if natural alignment is used for doubleword types. */
b6685939
PB		 579#define ARM_DOUBLEWORD_ALIGN TARGET_AAPCS_BASED
580
5848830f 581#define DOUBLEWORD_ALIGNMENT 64
35d965d5 582
5848830f 583#define PARM_BOUNDARY 32
5a9335ef 584
5848830f 585#define STACK_BOUNDARY (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
35d965d5 586
5848830f
PB		 587#define PREFERRED_STACK_BOUNDARY \
588 (arm_abi == ARM_ABI_ATPCS ? 64 : STACK_BOUNDARY)
0977774b 589
f711a87a 590#define FUNCTION_BOUNDARY ((TARGET_THUMB && optimize_size) ? 16 : 32)
35d965d5 591
92928d71
AO		 592/* The lowest bit is used to indicate Thumb-mode functions, so the
593 vbit must go into the delta field of pointers to member
594 functions. */
595#define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
596
35d965d5
RS		 597#define EMPTY_FIELD_BOUNDARY 32
598
5848830f 599#define BIGGEST_ALIGNMENT (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
5a9335ef 600
27847754
NC		 601/* XXX Blah -- this macro is used directly by libobjc. Since it
602 supports no vector modes, cut out the complexity and fall back
603 on BIGGEST_FIELD_ALIGNMENT. */
604#ifdef IN_TARGET_LIBS
8fca31a2 605#define BIGGEST_FIELD_ALIGNMENT 64
27847754 606#endif
5a9335ef 607
ff9940b0 608/* Make strings word-aligned so strcpy from constants will be faster. */
591af218 609#define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_tune_xscale ? 1 : 2)
f676971a 610
d19fb8e3 611#define CONSTANT_ALIGNMENT(EXP, ALIGN) \
5848830f 612 ((TREE_CODE (EXP) == STRING_CST \
36b15ad0 613 && !optimize_size \
5848830f
PB		 614 && (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \
615 ? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN))
ff9940b0 616
96339268
RE		 617/* Align definitions of arrays, unions and structures so that
618 initializations and copies can be made more efficient. This is not
619 ABI-changing, so it only affects places where we can see the
620 definition. */
621#define DATA_ALIGNMENT(EXP, ALIGN) \
622 ((((ALIGN) < BITS_PER_WORD) \
623 && (TREE_CODE (EXP) == ARRAY_TYPE \
624 || TREE_CODE (EXP) == UNION_TYPE \
625 || TREE_CODE (EXP) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
626
627/* Similarly, make sure that objects on the stack are sensibly aligned. */
628#define LOCAL_ALIGNMENT(EXP, ALIGN) DATA_ALIGNMENT(EXP, ALIGN)
629
723ae7c1
NC		 630/* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the
631 value set in previous versions of this toolchain was 8, which produces more
632 compact structures. The command line option -mstructure_size_boundary=<n>
f710504c 633 can be used to change this value. For compatibility with the ARM SDK
723ae7c1 634 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI
5848830f
PB		 635 0020D) page 2-20 says "Structures are aligned on word boundaries".
636 The AAPCS specifies a value of 8. */
6ead9ba5
NC		 637#define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary
638extern int arm_structure_size_boundary;
723ae7c1 639
4912a07c 640/* This is the value used to initialize arm_structure_size_boundary. If a
723ae7c1 641 particular arm target wants to change the default value it should change
6bc82793 642 the definition of this macro, not STRUCTURE_SIZE_BOUNDARY. See netbsd.h
723ae7c1
NC		 643 for an example of this. */
644#ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY
645#define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32
b355a481 646#endif
2a5307b1 647
825dda42 648/* Nonzero if move instructions will actually fail to work
ff9940b0 649 when given unaligned data. */
35d965d5 650#define STRICT_ALIGNMENT 1
b6685939
PB		 651
652/* wchar_t is unsigned under the AAPCS. */
653#ifndef WCHAR_TYPE
654#define WCHAR_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "int")
655
656#define WCHAR_TYPE_SIZE BITS_PER_WORD
657#endif
658
659#ifndef SIZE_TYPE
660#define SIZE_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "long unsigned int")
661#endif
d81d0bdd 662
077fc835
KH		 663#ifndef PTRDIFF_TYPE
664#define PTRDIFF_TYPE (TARGET_AAPCS_BASED ? "int" : "long int")
665#endif
666
d81d0bdd
PB		 667/* AAPCS requires that structure alignment is affected by bitfields. */
668#ifndef PCC_BITFIELD_TYPE_MATTERS
669#define PCC_BITFIELD_TYPE_MATTERS TARGET_AAPCS_BASED
670#endif
671
35d965d5
RS		 672\f
673/* Standard register usage. */
674
675/* Register allocation in ARM Procedure Call Standard (as used on RISCiX):
676 (S - saved over call).
677
678 r0 * argument word/integer result
679 r1-r3 argument word
680
681 r4-r8 S register variable
682 r9 S (rfp) register variable (real frame pointer)
f676971a 683
f5a1b0d2 684 r10 F S (sl) stack limit (used by -mapcs-stack-check)
35d965d5
RS		 685 r11 F S (fp) argument pointer
686 r12 (ip) temp workspace
687 r13 F S (sp) lower end of current stack frame
688 r14 (lr) link address/workspace
689 r15 F (pc) program counter
690
691 f0 floating point result
692 f1-f3 floating point scratch
693
694 f4-f7 S floating point variable
695
ff9940b0
RE		 696 cc This is NOT a real register, but is used internally
697 to represent things that use or set the condition
698 codes.
699 sfp This isn't either. It is used during rtl generation
700 since the offset between the frame pointer and the
701 auto's isn't known until after register allocation.
702 afp Nor this, we only need this because of non-local
703 goto. Without it fp appears to be used and the
704 elimination code won't get rid of sfp. It tracks
705 fp exactly at all times.
706
35d965d5
RS		 707 *: See CONDITIONAL_REGISTER_USAGE */
708
9b6b54e2
NC		 709/*
710 mvf0 Cirrus floating point result
711 mvf1-mvf3 Cirrus floating point scratch
712 mvf4-mvf15 S Cirrus floating point variable. */
713
9b66ebb1
PB		 714/* s0-s15 VFP scratch (aka d0-d7).
715 s16-s31 S VFP variable (aka d8-d15).
716 vfpcc Not a real register. Represents the VFP condition
717 code flags. */
718
ff9940b0
RE		 719/* The stack backtrace structure is as follows:
720 fp points to here: | save code pointer | [fp]
721 | return link value | [fp, #-4]
722 | return sp value | [fp, #-8]
723 | return fp value | [fp, #-12]
724 [| saved r10 value |]
725 [| saved r9 value |]
726 [| saved r8 value |]
727 [| saved r7 value |]
728 [| saved r6 value |]
729 [| saved r5 value |]
730 [| saved r4 value |]
731 [| saved r3 value |]
732 [| saved r2 value |]
733 [| saved r1 value |]
734 [| saved r0 value |]
735 [| saved f7 value |] three words
736 [| saved f6 value |] three words
737 [| saved f5 value |] three words
738 [| saved f4 value |] three words
739 r0-r3 are not normally saved in a C function. */
740
35d965d5
RS		 741/* 1 for registers that have pervasive standard uses
742 and are not available for the register allocator. */
9b66ebb1
PB		 743#define FIXED_REGISTERS \
744{ \
745 0,0,0,0,0,0,0,0, \
746 0,0,0,0,0,1,0,1, \
747 0,0,0,0,0,0,0,0, \
9b6b54e2
NC		 748 1,1,1, \
749 1,1,1,1,1,1,1,1, \
9b66ebb1
PB		 750 1,1,1,1,1,1,1,1, \
751 1,1,1,1,1,1,1,1, \
752 1,1,1,1,1,1,1,1, \
753 1,1,1,1, \
754 1,1,1,1,1,1,1,1, \
755 1,1,1,1,1,1,1,1, \
756 1,1,1,1,1,1,1,1, \
757 1,1,1,1,1,1,1,1, \
f1adb0a9
JB		 758 1,1,1,1,1,1,1,1, \
759 1,1,1,1,1,1,1,1, \
760 1,1,1,1,1,1,1,1, \
761 1,1,1,1,1,1,1,1, \
9b66ebb1 762 1 \
35d965d5
RS		 763}
764
765/* 1 for registers not available across function calls.
766 These must include the FIXED_REGISTERS and also any
767 registers that can be used without being saved.
768 The latter must include the registers where values are returned
769 and the register where structure-value addresses are passed.
ff9940b0 770 Aside from that, you can include as many other registers as you like.
f676971a 771 The CC is not preserved over function calls on the ARM 6, so it is
d6b4baa4 772 easier to assume this for all. SFP is preserved, since FP is. */
35d965d5
RS		 773#define CALL_USED_REGISTERS \
774{ \
775 1,1,1,1,0,0,0,0, \
d5b7b3ae 776 0,0,0,0,1,1,1,1, \
ff9940b0 777 1,1,1,1,0,0,0,0, \
9b6b54e2
NC		 778 1,1,1, \
779 1,1,1,1,1,1,1,1, \
5a9335ef
NC		 780 1,1,1,1,1,1,1,1, \
781 1,1,1,1,1,1,1,1, \
782 1,1,1,1,1,1,1,1, \
9b66ebb1
PB		 783 1,1,1,1, \
784 1,1,1,1,1,1,1,1, \
785 1,1,1,1,1,1,1,1, \
786 1,1,1,1,1,1,1,1, \
787 1,1,1,1,1,1,1,1, \
f1adb0a9
JB		 788 1,1,1,1,1,1,1,1, \
789 1,1,1,1,1,1,1,1, \
790 1,1,1,1,1,1,1,1, \
791 1,1,1,1,1,1,1,1, \
9b66ebb1 792 1 \
35d965d5
RS		 793}
794
6cc8c0b3
NC		 795#ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE
796#define SUBTARGET_CONDITIONAL_REGISTER_USAGE
797#endif
798
d5b7b3ae
RE		 799#define CONDITIONAL_REGISTER_USAGE \
800{ \
4b02997f
NC		 801 int regno; \
802 \
5b3e6663 803 if (TARGET_SOFT_FLOAT || TARGET_THUMB1 || !TARGET_FPA) \
d5b7b3ae 804 { \
9b66ebb1
PB		 805 for (regno = FIRST_FPA_REGNUM; \
806 regno <= LAST_FPA_REGNUM; ++regno) \
d5b7b3ae
RE		 807 fixed_regs[regno] = call_used_regs[regno] = 1; \
808 } \
9b6b54e2 809 \
28907f9a
MS		 810 if (TARGET_THUMB1 && optimize_size) \
811 { \
812 /* When optimizing for size on Thumb-1, it's better not \
813 to use the HI regs, because of the overhead of \
814 stacking them. */ \
c769a35d
RE		 815 for (regno = FIRST_HI_REGNUM; \
816 regno <= LAST_HI_REGNUM; ++regno) \
817 fixed_regs[regno] = call_used_regs[regno] = 1; \
818 } \
819 \
fb14bc89
RE		 820 /* The link register can be clobbered by any branch insn, \
821 but we have no way to track that at present, so mark \
822 it as unavailable. */ \
5b3e6663 823 if (TARGET_THUMB1) \
fb14bc89
RE		 824 fixed_regs[LR_REGNUM] = call_used_regs[LR_REGNUM] = 1; \
825 \
5b3e6663 826 if (TARGET_32BIT && TARGET_HARD_FLOAT) \
9b6b54e2 827 { \
9b66ebb1 828 if (TARGET_MAVERICK) \
9b6b54e2 829 { \
9b66ebb1
PB		 830 for (regno = FIRST_FPA_REGNUM; \
831 regno <= LAST_FPA_REGNUM; ++ regno) \
832 fixed_regs[regno] = call_used_regs[regno] = 1; \
833 for (regno = FIRST_CIRRUS_FP_REGNUM; \
834 regno <= LAST_CIRRUS_FP_REGNUM; ++ regno) \
835 { \
836 fixed_regs[regno] = 0; \
837 call_used_regs[regno] = regno < FIRST_CIRRUS_FP_REGNUM + 4; \
838 } \
839 } \
840 if (TARGET_VFP) \
841 { \
f1adb0a9
JB		 842 /* VFPv3 registers are disabled when earlier VFP \
843 versions are selected due to the definition of \
844 LAST_VFP_REGNUM. */ \
9b66ebb1
PB		 845 for (regno = FIRST_VFP_REGNUM; \
846 regno <= LAST_VFP_REGNUM; ++ regno) \
847 { \
848 fixed_regs[regno] = 0; \
f1adb0a9
JB		 849 call_used_regs[regno] = regno < FIRST_VFP_REGNUM + 16 \
850 || regno >= FIRST_VFP_REGNUM + 32; \
9b66ebb1 851 } \
9b6b54e2
NC		 852 } \
853 } \
854 \
5a9335ef
NC		 855 if (TARGET_REALLY_IWMMXT) \
856 { \
857 regno = FIRST_IWMMXT_GR_REGNUM; \
858 /* The 2002/10/09 revision of the XScale ABI has wCG0 \
859 and wCG1 as call-preserved registers. The 2002/11/21 \
860 revision changed this so that all wCG registers are \
861 scratch registers. */ \
862 for (regno = FIRST_IWMMXT_GR_REGNUM; \
863 regno <= LAST_IWMMXT_GR_REGNUM; ++ regno) \
119bb233 864 fixed_regs[regno] = 0; \
5a9335ef
NC		 865 /* The XScale ABI has wR0 - wR9 as scratch registers, \
866 the rest as call-preserved registers. */ \
867 for (regno = FIRST_IWMMXT_REGNUM; \
868 regno <= LAST_IWMMXT_REGNUM; ++ regno) \
869 { \
870 fixed_regs[regno] = 0; \
871 call_used_regs[regno] = regno < FIRST_IWMMXT_REGNUM + 10; \
872 } \
873 } \
874 \
fc555370 875 if ((unsigned) PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
d5b7b3ae
RE		 876 { \
877 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
878 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
879 } \
880 else if (TARGET_APCS_STACK) \
881 { \
882 fixed_regs[10] = 1; \
883 call_used_regs[10] = 1; \
884 } \
a2503645
RS		 885 /* -mcaller-super-interworking reserves r11 for calls to \
886 _interwork_r11_call_via_rN(). Making the register global \
887 is an easy way of ensuring that it remains valid for all \
888 calls. */ \
685c9c11 889 if (TARGET_APCS_FRAME || TARGET_CALLER_INTERWORKING \
c54c7322 890 || TARGET_TPCS_FRAME || TARGET_TPCS_LEAF_FRAME) \
d5b7b3ae
RE		 891 { \
892 fixed_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
893 call_used_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
a2503645
RS		 894 if (TARGET_CALLER_INTERWORKING) \
895 global_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
d5b7b3ae
RE		 896 } \
897 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
35d965d5 898}
f676971a 899
6bc82793 900/* These are a couple of extensions to the formats accepted
dd18ae56
NC		 901 by asm_fprintf:
902 %@ prints out ASM_COMMENT_START
903 %r prints out REGISTER_PREFIX reg_names[arg] */
904#define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \
905 case '@': \
906 fputs (ASM_COMMENT_START, FILE); \
907 break; \
908 \
909 case 'r': \
910 fputs (REGISTER_PREFIX, FILE); \
911 fputs (reg_names [va_arg (ARGS, int)], FILE); \
912 break;
913
d5b7b3ae 914/* Round X up to the nearest word. */
0c2ca901 915#define ROUND_UP_WORD(X) (((X) + 3) & ~3)
d5b7b3ae 916
6cfc7210 917/* Convert fron bytes to ints. */
e9d7b180 918#define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
6cfc7210 919
9b66ebb1
PB		 920/* The number of (integer) registers required to hold a quantity of type MODE.
921 Also used for VFP registers. */
e9d7b180
JD		 922#define ARM_NUM_REGS(MODE) \
923 ARM_NUM_INTS (GET_MODE_SIZE (MODE))
6cfc7210
NC		 924
925/* The number of (integer) registers required to hold a quantity of TYPE MODE. */
e9d7b180
JD		 926#define ARM_NUM_REGS2(MODE, TYPE) \
927 ARM_NUM_INTS ((MODE) == BLKmode ? \
d5b7b3ae 928 int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE))
6cfc7210
NC		 929
930/* The number of (integer) argument register available. */
d5b7b3ae 931#define NUM_ARG_REGS 4
6cfc7210 932
390b17c2
RE		 933/* And similarly for the VFP. */
934#define NUM_VFP_ARG_REGS 16
935
093354e0 936/* Return the register number of the N'th (integer) argument. */
d5b7b3ae 937#define ARG_REGISTER(N) (N - 1)
6cfc7210 938
d5b7b3ae
RE		 939/* Specify the registers used for certain standard purposes.
940 The values of these macros are register numbers. */
35d965d5 941
d5b7b3ae
RE		 942/* The number of the last argument register. */
943#define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS)
35d965d5 944
c769a35d
RE		 945/* The numbers of the Thumb register ranges. */
946#define FIRST_LO_REGNUM 0
6d3d9133 947#define LAST_LO_REGNUM 7
c769a35d
RE		 948#define FIRST_HI_REGNUM 8
949#define LAST_HI_REGNUM 11
6d3d9133 950
f0a0390e
RH		 951/* Overridden by config/arm/bpabi.h. */
952#ifndef ARM_UNWIND_INFO
953#define ARM_UNWIND_INFO 0
617a1b71
PB		 954#endif
955
c9ca9b88
PB		 956/* Use r0 and r1 to pass exception handling information. */
957#define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? N : INVALID_REGNUM)
958
6d3d9133 959/* The register that holds the return address in exception handlers. */
c9ca9b88
PB		 960#define ARM_EH_STACKADJ_REGNUM 2
961#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (SImode, ARM_EH_STACKADJ_REGNUM)
35d965d5 962
d5b7b3ae
RE		 963/* The native (Norcroft) Pascal compiler for the ARM passes the static chain
964 as an invisible last argument (possible since varargs don't exist in
965 Pascal), so the following is not true. */
5b3e6663 966#define STATIC_CHAIN_REGNUM 12
35d965d5 967
d5b7b3ae
RE		 968/* Define this to be where the real frame pointer is if it is not possible to
969 work out the offset between the frame pointer and the automatic variables
970 until after register allocation has taken place. FRAME_POINTER_REGNUM
971 should point to a special register that we will make sure is eliminated.
972
973 For the Thumb we have another problem. The TPCS defines the frame pointer
6bc82793 974 as r11, and GCC believes that it is always possible to use the frame pointer
d5b7b3ae
RE		 975 as base register for addressing purposes. (See comments in
976 find_reloads_address()). But - the Thumb does not allow high registers,
977 including r11, to be used as base address registers. Hence our problem.
978
979 The solution used here, and in the old thumb port is to use r7 instead of
980 r11 as the hard frame pointer and to have special code to generate
981 backtrace structures on the stack (if required to do so via a command line
6bc82793 982 option) using r11. This is the only 'user visible' use of r11 as a frame
d5b7b3ae
RE		 983 pointer. */
984#define ARM_HARD_FRAME_POINTER_REGNUM 11
985#define THUMB_HARD_FRAME_POINTER_REGNUM 7
35d965d5 986
b15bca31
RE		 987#define HARD_FRAME_POINTER_REGNUM \
988 (TARGET_ARM \
989 ? ARM_HARD_FRAME_POINTER_REGNUM \
990 : THUMB_HARD_FRAME_POINTER_REGNUM)
d5b7b3ae 991
e3339d0f
JM		 992#define HARD_FRAME_POINTER_IS_FRAME_POINTER 0
993#define HARD_FRAME_POINTER_IS_ARG_POINTER 0
994
b15bca31 995#define FP_REGNUM HARD_FRAME_POINTER_REGNUM
d5b7b3ae 996
b15bca31
RE		 997/* Register to use for pushing function arguments. */
998#define STACK_POINTER_REGNUM SP_REGNUM
d5b7b3ae
RE		 999
1000/* ARM floating pointer registers. */
9b66ebb1
PB		 1001#define FIRST_FPA_REGNUM 16
1002#define LAST_FPA_REGNUM 23
2fa330b2
PB		 1003#define IS_FPA_REGNUM(REGNUM) \
1004 (((REGNUM) >= FIRST_FPA_REGNUM) && ((REGNUM) <= LAST_FPA_REGNUM))
d5b7b3ae 1005
5a9335ef
NC		 1006#define FIRST_IWMMXT_GR_REGNUM 43
1007#define LAST_IWMMXT_GR_REGNUM 46
1008#define FIRST_IWMMXT_REGNUM 47
1009#define LAST_IWMMXT_REGNUM 62
1010#define IS_IWMMXT_REGNUM(REGNUM) \
1011 (((REGNUM) >= FIRST_IWMMXT_REGNUM) && ((REGNUM) <= LAST_IWMMXT_REGNUM))
1012#define IS_IWMMXT_GR_REGNUM(REGNUM) \
1013 (((REGNUM) >= FIRST_IWMMXT_GR_REGNUM) && ((REGNUM) <= LAST_IWMMXT_GR_REGNUM))
1014
35d965d5 1015/* Base register for access to local variables of the function. */
ff9940b0
RE		 1016#define FRAME_POINTER_REGNUM 25
1017
d5b7b3ae
RE		 1018/* Base register for access to arguments of the function. */
1019#define ARG_POINTER_REGNUM 26
62b10bbc 1020
9b6b54e2
NC		 1021#define FIRST_CIRRUS_FP_REGNUM 27
1022#define LAST_CIRRUS_FP_REGNUM 42
1023#define IS_CIRRUS_REGNUM(REGNUM) \
1024 (((REGNUM) >= FIRST_CIRRUS_FP_REGNUM) && ((REGNUM) <= LAST_CIRRUS_FP_REGNUM))
1025
9b66ebb1 1026#define FIRST_VFP_REGNUM 63
f1adb0a9
JB		 1027#define D7_VFP_REGNUM 78 /* Registers 77 and 78 == VFP reg D7. */
1028#define LAST_VFP_REGNUM \
302c3d8e 1029 (TARGET_VFPD32 ? LAST_HI_VFP_REGNUM : LAST_LO_VFP_REGNUM)
f1adb0a9 1030
9b66ebb1
PB		 1031#define IS_VFP_REGNUM(REGNUM) \
1032 (((REGNUM) >= FIRST_VFP_REGNUM) && ((REGNUM) <= LAST_VFP_REGNUM))
1033
f1adb0a9
JB		 1034/* VFP registers are split into two types: those defined by VFP versions < 3
1035 have D registers overlaid on consecutive pairs of S registers. VFP version 3
1036 defines 16 new D registers (d16-d31) which, for simplicity and correctness
1037 in various parts of the backend, we implement as "fake" single-precision
1038 registers (which would be S32-S63, but cannot be used in that way). The
1039 following macros define these ranges of registers. */
1040#define LAST_LO_VFP_REGNUM 94
1041#define FIRST_HI_VFP_REGNUM 95
1042#define LAST_HI_VFP_REGNUM 126
1043
1044#define VFP_REGNO_OK_FOR_SINGLE(REGNUM) \
1045 ((REGNUM) <= LAST_LO_VFP_REGNUM)
1046
1047/* DFmode values are only valid in even register pairs. */
1048#define VFP_REGNO_OK_FOR_DOUBLE(REGNUM) \
1049 ((((REGNUM) - FIRST_VFP_REGNUM) & 1) == 0)
1050
88f77cba
JB		 1051/* Neon Quad values must start at a multiple of four registers. */
1052#define NEON_REGNO_OK_FOR_QUAD(REGNUM) \
1053 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0)
1054
1055/* Neon structures of vectors must be in even register pairs and there
1056 must be enough registers available. Because of various patterns
1057 requiring quad registers, we require them to start at a multiple of
1058 four. */
1059#define NEON_REGNO_OK_FOR_NREGS(REGNUM, N) \
1060 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0 \
1061 && (LAST_VFP_REGNUM - (REGNUM) >= 2 * (N) - 1))
1062
6f8c9bd1
NC		 1063/* The number of hard registers is 16 ARM + 8 FPA + 1 CC + 1 SFP + 1 AFP. */
1064/* + 16 Cirrus registers take us up to 43. */
5a9335ef 1065/* Intel Wireless MMX Technology registers add 16 + 4 more. */
f1adb0a9
JB		 1066/* VFP (VFP3) adds 32 (64) + 1 more. */
1067#define FIRST_PSEUDO_REGISTER 128
62b10bbc 1068
2fa330b2
PB		 1069#define DBX_REGISTER_NUMBER(REGNO) arm_dbx_register_number (REGNO)
1070
35d965d5
RS		 1071/* Value should be nonzero if functions must have frame pointers.
1072 Zero means the frame pointer need not be set up (and parms may be accessed
f676971a 1073 via the stack pointer) in functions that seem suitable.
ff9940b0
RE		 1074 If we have to have a frame pointer we might as well make use of it.
1075 APCS says that the frame pointer does not need to be pushed in leaf
2a5307b1 1076 functions, or simple tail call functions. */
a15900b5
DJ		 1077
1078#ifndef SUBTARGET_FRAME_POINTER_REQUIRED
1079#define SUBTARGET_FRAME_POINTER_REQUIRED 0
1080#endif
1081
d5b7b3ae
RE		 1082/* Return number of consecutive hard regs needed starting at reg REGNO
1083 to hold something of mode MODE.
1084 This is ordinarily the length in words of a value of mode MODE
1085 but can be less for certain modes in special long registers.
35d965d5 1086
3b684012 1087 On the ARM regs are UNITS_PER_WORD bits wide; FPA regs can hold any FP
d5b7b3ae
RE		 1088 mode. */
1089#define HARD_REGNO_NREGS(REGNO, MODE) \
5b3e6663 1090 ((TARGET_32BIT \
9b66ebb1 1091 && REGNO >= FIRST_FPA_REGNUM \
d5b7b3ae
RE		 1092 && REGNO != FRAME_POINTER_REGNUM \
1093 && REGNO != ARG_POINTER_REGNUM) \
9b66ebb1 1094 && !IS_VFP_REGNUM (REGNO) \
e9d7b180 1095 ? 1 : ARM_NUM_REGS (MODE))
35d965d5 1096
4b02997f 1097/* Return true if REGNO is suitable for holding a quantity of type MODE. */
d5b7b3ae 1098#define HARD_REGNO_MODE_OK(REGNO, MODE) \
4b02997f 1099 arm_hard_regno_mode_ok ((REGNO), (MODE))
35d965d5 1100
d5b7b3ae
RE		 1101/* Value is 1 if it is a good idea to tie two pseudo registers
1102 when one has mode MODE1 and one has mode MODE2.
1103 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1104 for any hard reg, then this must be 0 for correct output. */
1105#define MODES_TIEABLE_P(MODE1, MODE2) \
1106 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
ff9940b0 1107
5a9335ef 1108#define VALID_IWMMXT_REG_MODE(MODE) \
f676971a 1109 (arm_vector_mode_supported_p (MODE) || (MODE) == DImode)
5a9335ef 1110
88f77cba
JB		 1111/* Modes valid for Neon D registers. */
1112#define VALID_NEON_DREG_MODE(MODE) \
1113 ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode \
1114 || (MODE) == V2SFmode || (MODE) == DImode)
1115
1116/* Modes valid for Neon Q registers. */
1117#define VALID_NEON_QREG_MODE(MODE) \
1118 ((MODE) == V4SImode || (MODE) == V8HImode || (MODE) == V16QImode \
1119 || (MODE) == V4SFmode || (MODE) == V2DImode)
1120
1121/* Structure modes valid for Neon registers. */
1122#define VALID_NEON_STRUCT_MODE(MODE) \
1123 ((MODE) == TImode || (MODE) == EImode || (MODE) == OImode \
1124 || (MODE) == CImode || (MODE) == XImode)
1125
37119410
BS		 1126/* The register numbers in sequence, for passing to arm_gen_load_multiple. */
1127extern int arm_regs_in_sequence[];
1128
35d965d5 1129/* The order in which register should be allocated. It is good to use ip
ff9940b0
RE		 1130 since no saving is required (though calls clobber it) and it never contains
1131 function parameters. It is quite good to use lr since other calls may
f676971a 1132 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is
ff9940b0 1133 least likely to contain a function parameter; in addition results are
f1adb0a9
JB		 1134 returned in r0.
1135 For VFP/VFPv3, allocate D16-D31 first, then caller-saved registers (D0-D7),
1136 then D8-D15. The reason for doing this is to attempt to reduce register
1137 pressure when both single- and double-precision registers are used in a
1138 function. */
1139
1140#define REG_ALLOC_ORDER \
1141{ \
1142 3, 2, 1, 0, 12, 14, 4, 5, \
1143 6, 7, 8, 10, 9, 11, 13, 15, \
1144 16, 17, 18, 19, 20, 21, 22, 23, \
1145 27, 28, 29, 30, 31, 32, 33, 34, \
1146 35, 36, 37, 38, 39, 40, 41, 42, \
1147 43, 44, 45, 46, 47, 48, 49, 50, \
1148 51, 52, 53, 54, 55, 56, 57, 58, \
1149 59, 60, 61, 62, \
1150 24, 25, 26, \
1151 95, 96, 97, 98, 99, 100, 101, 102, \
1152 103, 104, 105, 106, 107, 108, 109, 110, \
1153 111, 112, 113, 114, 115, 116, 117, 118, \
1154 119, 120, 121, 122, 123, 124, 125, 126, \
1155 78, 77, 76, 75, 74, 73, 72, 71, \
1156 70, 69, 68, 67, 66, 65, 64, 63, \
1157 79, 80, 81, 82, 83, 84, 85, 86, \
1158 87, 88, 89, 90, 91, 92, 93, 94, \
1159 127 \
35d965d5 1160}
9338ffe6 1161
795dc4fc 1162/* Use different register alloc ordering for Thumb. */
5a733826
BS		 1163#define ADJUST_REG_ALLOC_ORDER arm_order_regs_for_local_alloc ()
1164
1165/* Tell IRA to use the order we define rather than messing it up with its
1166 own cost calculations. */
1167#define HONOR_REG_ALLOC_ORDER
795dc4fc 1168
9338ffe6
PB		 1169/* Interrupt functions can only use registers that have already been
1170 saved by the prologue, even if they would normally be
1171 call-clobbered. */
1172#define HARD_REGNO_RENAME_OK(SRC, DST) \
1173 (! IS_INTERRUPT (cfun->machine->func_type) || \
6fb5fa3c 1174 df_regs_ever_live_p (DST))
35d965d5
RS		 1175\f
1176/* Register and constant classes. */
1177
3b684012 1178/* Register classes: used to be simple, just all ARM regs or all FPA regs
d6a7951f 1179 Now that the Thumb is involved it has become more complicated. */
35d965d5
RS		 1180enum reg_class
1181{
1182 NO_REGS,
3b684012 1183 FPA_REGS,
9b6b54e2 1184 CIRRUS_REGS,
f1adb0a9
JB		 1185 VFP_D0_D7_REGS,
1186 VFP_LO_REGS,
1187 VFP_HI_REGS,
9b66ebb1 1188 VFP_REGS,
5a9335ef
NC		 1189 IWMMXT_GR_REGS,
1190 IWMMXT_REGS,
d5b7b3ae
RE		 1191 LO_REGS,
1192 STACK_REG,
1193 BASE_REGS,
1194 HI_REGS,
1195 CC_REG,
9b66ebb1 1196 VFPCC_REG,
35d965d5 1197 GENERAL_REGS,
f5c630c3 1198 CORE_REGS,
35d965d5
RS		 1199 ALL_REGS,
1200 LIM_REG_CLASSES
1201};
1202
1203#define N_REG_CLASSES (int) LIM_REG_CLASSES
1204
d6b4baa4 1205/* Give names of register classes as strings for dump file. */
35d965d5
RS		 1206#define REG_CLASS_NAMES \
1207{ \
1208 "NO_REGS", \
3b684012 1209 "FPA_REGS", \
9b6b54e2 1210 "CIRRUS_REGS", \
f1adb0a9
JB		 1211 "VFP_D0_D7_REGS", \
1212 "VFP_LO_REGS", \
1213 "VFP_HI_REGS", \
9b66ebb1 1214 "VFP_REGS", \
5a9335ef
NC		 1215 "IWMMXT_GR_REGS", \
1216 "IWMMXT_REGS", \
d5b7b3ae
RE		 1217 "LO_REGS", \
1218 "STACK_REG", \
1219 "BASE_REGS", \
1220 "HI_REGS", \
1221 "CC_REG", \
5384443a 1222 "VFPCC_REG", \
35d965d5 1223 "GENERAL_REGS", \
f5c630c3 1224 "CORE_REGS", \
35d965d5
RS		 1225 "ALL_REGS", \
1226}
1227
1228/* Define which registers fit in which classes.
1229 This is an initializer for a vector of HARD_REG_SET
1230 of length N_REG_CLASSES. */
f1adb0a9
JB		 1231#define REG_CLASS_CONTENTS \
1232{ \
1233 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1234 { 0x00FF0000, 0x00000000, 0x00000000, 0x00000000 }, /* FPA_REGS */ \
1235 { 0xF8000000, 0x000007FF, 0x00000000, 0x00000000 }, /* CIRRUS_REGS */ \
1236 { 0x00000000, 0x80000000, 0x00007FFF, 0x00000000 }, /* VFP_D0_D7_REGS */ \
1237 { 0x00000000, 0x80000000, 0x7FFFFFFF, 0x00000000 }, /* VFP_LO_REGS */ \
1238 { 0x00000000, 0x00000000, 0x80000000, 0x7FFFFFFF }, /* VFP_HI_REGS */ \
1239 { 0x00000000, 0x80000000, 0xFFFFFFFF, 0x7FFFFFFF }, /* VFP_REGS */ \
1240 { 0x00000000, 0x00007800, 0x00000000, 0x00000000 }, /* IWMMXT_GR_REGS */ \
1241 { 0x00000000, 0x7FFF8000, 0x00000000, 0x00000000 }, /* IWMMXT_REGS */ \
1242 { 0x000000FF, 0x00000000, 0x00000000, 0x00000000 }, /* LO_REGS */ \
1243 { 0x00002000, 0x00000000, 0x00000000, 0x00000000 }, /* STACK_REG */ \
1244 { 0x000020FF, 0x00000000, 0x00000000, 0x00000000 }, /* BASE_REGS */ \
f5c630c3 1245 { 0x0000DF00, 0x00000000, 0x00000000, 0x00000000 }, /* HI_REGS */ \
f1adb0a9
JB		 1246 { 0x01000000, 0x00000000, 0x00000000, 0x00000000 }, /* CC_REG */ \
1247 { 0x00000000, 0x00000000, 0x00000000, 0x80000000 }, /* VFPCC_REG */ \
f5c630c3
PB		 1248 { 0x0200DFFF, 0x00000000, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \
1249 { 0x0200FFFF, 0x00000000, 0x00000000, 0x00000000 }, /* CORE_REGS */ \
f1adb0a9 1250 { 0xFAFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x7FFFFFFF } /* ALL_REGS */ \
35d965d5 1251}
4b02997f 1252
f1adb0a9
JB		 1253/* Any of the VFP register classes. */
1254#define IS_VFP_CLASS(X) \
1255 ((X) == VFP_D0_D7_REGS || (X) == VFP_LO_REGS \
1256 || (X) == VFP_HI_REGS || (X) == VFP_REGS)
1257
35d965d5
RS		 1258/* The same information, inverted:
1259 Return the class number of the smallest class containing
1260 reg number REGNO. This could be a conditional expression
1261 or could index an array. */
d5b7b3ae 1262#define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO)
35d965d5 1263
058e97ec
VM		 1264/* The following macro defines cover classes for Integrated Register
1265 Allocator. Cover classes is a set of non-intersected register
1266 classes covering all hard registers used for register allocation
1267 purpose. Any move between two registers of a cover class should be
1268 cheaper than load or store of the registers. The macro value is
1269 array of register classes with LIM_REG_CLASSES used as the end
1270 marker. */
1271
1272#define IRA_COVER_CLASSES \
1273{ \
1274 GENERAL_REGS, FPA_REGS, CIRRUS_REGS, VFP_REGS, IWMMXT_GR_REGS, IWMMXT_REGS,\
1275 LIM_REG_CLASSES \
1276}
1277
9b66ebb1 1278/* FPA registers can't do subreg as all values are reformatted to internal
59b9a953 1279 precision. VFP registers may only be accessed in the mode they
9b66ebb1 1280 were set. */
75d2580c
RE		 1281#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1282 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
9b66ebb1
PB		 1283 ? reg_classes_intersect_p (FPA_REGS, (CLASS)) \
1284 || reg_classes_intersect_p (VFP_REGS, (CLASS)) \
1285 : 0)
75d2580c 1286
35d965d5 1287/* The class value for index registers, and the one for base regs. */
5b3e6663 1288#define INDEX_REG_CLASS (TARGET_THUMB1 ? LO_REGS : GENERAL_REGS)
f5c630c3 1289#define BASE_REG_CLASS (TARGET_THUMB1 ? LO_REGS : CORE_REGS)
d5b7b3ae 1290
b93a0fe6 1291/* For the Thumb the high registers cannot be used as base registers
6bc82793 1292 when addressing quantities in QI or HI mode; if we don't know the
888d2cd6 1293 mode, then we must be conservative. */
3dcc68a4 1294#define MODE_BASE_REG_CLASS(MODE) \
f5c630c3 1295 (TARGET_32BIT ? CORE_REGS : \
888d2cd6
DJ		 1296 (((MODE) == SImode) ? BASE_REGS : LO_REGS))
1297
1298/* For Thumb we can not support SP+reg addressing, so we return LO_REGS
1299 instead of BASE_REGS. */
1300#define MODE_BASE_REG_REG_CLASS(MODE) BASE_REG_CLASS
3dcc68a4 1301
42db504c 1302/* When this hook returns true for MODE, the compiler allows
d5b7b3ae
RE		 1303 registers explicitly used in the rtl to be used as spill registers
1304 but prevents the compiler from extending the lifetime of these
d6b4baa4 1305 registers. */
42db504c
SB		 1306#define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \
1307 arm_small_register_classes_for_mode_p
35d965d5 1308
35d965d5
RS		 1309/* Given an rtx X being reloaded into a reg required to be
1310 in class CLASS, return the class of reg to actually use.
5b3e6663
PB		 1311 In general this is just CLASS, but for the Thumb core registers and
1312 immediate constants we prefer a LO_REGS class or a subset. */
1313#define PREFERRED_RELOAD_CLASS(X, CLASS) \
12d210d9 1314 (TARGET_32BIT ? (CLASS) : \
5b3e6663 1315 ((CLASS) == GENERAL_REGS || (CLASS) == HI_REGS \
f5c630c3
PB		 1316 || (CLASS) == NO_REGS || (CLASS) == STACK_REG \
1317 ? LO_REGS : (CLASS)))
d5b7b3ae
RE		 1318
1319/* Must leave BASE_REGS reloads alone */
1320#define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1321 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1322 ? ((true_regnum (X) == -1 ? LO_REGS \
1323 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1324 : NO_REGS)) \
1325 : NO_REGS)
1326
1327#define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
97358092 1328 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
d5b7b3ae
RE		 1329 ? ((true_regnum (X) == -1 ? LO_REGS \
1330 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1331 : NO_REGS)) \
1332 : NO_REGS)
35d965d5 1333
ff9940b0
RE		 1334/* Return the register class of a scratch register needed to copy IN into
1335 or out of a register in CLASS in MODE. If it can be done directly,
1336 NO_REGS is returned. */
d5b7b3ae 1337#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
fe2d934b 1338 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \
9b66ebb1 1339 ((TARGET_VFP && TARGET_HARD_FLOAT \
f1adb0a9 1340 && IS_VFP_CLASS (CLASS)) \
fe2d934b
PB		 1341 ? coproc_secondary_reload_class (MODE, X, FALSE) \
1342 : (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) \
1343 ? coproc_secondary_reload_class (MODE, X, TRUE) \
5b3e6663 1344 : TARGET_32BIT \
9b66ebb1 1345 ? (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \
d5b7b3ae
RE		 1346 ? GENERAL_REGS : NO_REGS) \
1347 : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X))
f676971a 1348
d6b4baa4 1349/* If we need to load shorts byte-at-a-time, then we need a scratch. */
d5b7b3ae 1350#define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
fe2d934b 1351 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \
9b66ebb1 1352 ((TARGET_VFP && TARGET_HARD_FLOAT \
f1adb0a9 1353 && IS_VFP_CLASS (CLASS)) \
fe2d934b
PB		 1354 ? coproc_secondary_reload_class (MODE, X, FALSE) : \
1355 (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) ? \
1356 coproc_secondary_reload_class (MODE, X, TRUE) : \
9b6b54e2 1357 /* Cannot load constants into Cirrus registers. */ \
9b66ebb1 1358 (TARGET_MAVERICK && TARGET_HARD_FLOAT \
9b6b54e2
NC		 1359 && (CLASS) == CIRRUS_REGS \
1360 && (CONSTANT_P (X) || GET_CODE (X) == SYMBOL_REF)) \
1361 ? GENERAL_REGS : \
5b3e6663 1362 (TARGET_32BIT ? \
5a9335ef
NC		 1363 (((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \
1364 && CONSTANT_P (X)) \
1365 ? GENERAL_REGS : \
61f0ccff 1366 (((MODE) == HImode && ! arm_arch4 \
d5b7b3ae
RE		 1367 && (GET_CODE (X) == MEM \
1368 || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \
1369 && true_regnum (X) == -1))) \
1370 ? GENERAL_REGS : NO_REGS) \
9b6b54e2 1371 : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X)))
2ce9c1b9 1372
6f734908
RE		 1373/* Try a machine-dependent way of reloading an illegitimate address
1374 operand. If we find one, push the reload and jump to WIN. This
1375 macro is used in only one place: `find_reloads_address' in reload.c.
1376
1377 For the ARM, we wish to handle large displacements off a base
1378 register by splitting the addend across a MOV and the mem insn.
d5b7b3ae
RE		 1379 This can cut the number of reloads needed. */
1380#define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN) \
1381 do \
1382 { \
1383 if (GET_CODE (X) == PLUS \
1384 && GET_CODE (XEXP (X, 0)) == REG \
1385 && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \
1386 && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \
1387 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1388 { \
1389 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1390 HOST_WIDE_INT low, high; \
1391 \
de6f27a8 1392 if (MODE == DImode || (MODE == DFmode && TARGET_SOFT_FLOAT)) \
d5b7b3ae 1393 low = ((val & 0xf) ^ 0x8) - 0x8; \
9b66ebb1 1394 else if (TARGET_MAVERICK && TARGET_HARD_FLOAT) \
9b6b54e2
NC		 1395 /* Need to be careful, -256 is not a valid offset. */ \
1396 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
d5b7b3ae 1397 else if (MODE == SImode \
de6f27a8 1398 || (MODE == SFmode && TARGET_SOFT_FLOAT) \
d5b7b3ae
RE		 1399 || ((MODE == HImode || MODE == QImode) && ! arm_arch4)) \
1400 /* Need to be careful, -4096 is not a valid offset. */ \
1401 low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff); \
1402 else if ((MODE == HImode || MODE == QImode) && arm_arch4) \
1403 /* Need to be careful, -256 is not a valid offset. */ \
1404 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1405 else if (GET_MODE_CLASS (MODE) == MODE_FLOAT \
9b66ebb1 1406 && TARGET_HARD_FLOAT && TARGET_FPA) \
d5b7b3ae
RE		 1407 /* Need to be careful, -1024 is not a valid offset. */ \
1408 low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \
1409 else \
1410 break; \
1411 \
30cf4896
KG		 1412 high = ((((val - low) & (unsigned HOST_WIDE_INT) 0xffffffff) \
1413 ^ (unsigned HOST_WIDE_INT) 0x80000000) \
1414 - (unsigned HOST_WIDE_INT) 0x80000000); \
d5b7b3ae
RE		 1415 /* Check for overflow or zero */ \
1416 if (low == 0 || high == 0 || (high + low != val)) \
1417 break; \
1418 \
1419 /* Reload the high part into a base reg; leave the low part \
1420 in the mem. */ \
1421 X = gen_rtx_PLUS (GET_MODE (X), \
1422 gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \
1423 GEN_INT (high)), \
1424 GEN_INT (low)); \
df4ae160 1425 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
4a692617
NC		 1426 MODE_BASE_REG_CLASS (MODE), GET_MODE (X), \
1427 VOIDmode, 0, 0, OPNUM, TYPE); \
d5b7b3ae
RE		 1428 goto WIN; \
1429 } \
1430 } \
62b10bbc 1431 while (0)
6f734908 1432
27847754 1433/* XXX If an HImode FP+large_offset address is converted to an HImode
d5b7b3ae
RE		 1434 SP+large_offset address, then reload won't know how to fix it. It sees
1435 only that SP isn't valid for HImode, and so reloads the SP into an index
1436 register, but the resulting address is still invalid because the offset
1437 is too big. We fix it here instead by reloading the entire address. */
1438/* We could probably achieve better results by defining PROMOTE_MODE to help
1439 cope with the variances between the Thumb's signed and unsigned byte and
1440 halfword load instructions. */
5b3e6663 1441/* ??? This should be safe for thumb2, but we may be able to do better. */
a132dad6
RE		 1442#define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_L, WIN) \
1443do { \
1444 rtx new_x = thumb_legitimize_reload_address (&X, MODE, OPNUM, TYPE, IND_L); \
1445 if (new_x) \
1446 { \
1447 X = new_x; \
1448 goto WIN; \
1449 } \
1450} while (0)
d5b7b3ae
RE		 1451
1452#define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1453 if (TARGET_ARM) \
1454 ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \
1455 else \
1456 THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN)
f676971a 1457
35d965d5
RS		 1458/* Return the maximum number of consecutive registers
1459 needed to represent mode MODE in a register of class CLASS.
3b684012 1460 ARM regs are UNITS_PER_WORD bits while FPA regs can hold any FP mode */
35d965d5 1461#define CLASS_MAX_NREGS(CLASS, MODE) \
3b684012 1462 (((CLASS) == FPA_REGS || (CLASS) == CIRRUS_REGS) ? 1 : ARM_NUM_REGS (MODE))
9b6b54e2
NC		 1463
1464/* If defined, gives a class of registers that cannot be used as the
1465 operand of a SUBREG that changes the mode of the object illegally. */
35d965d5 1466
356ecb15
DJ		 1467/* Moves between FPA_REGS and GENERAL_REGS are two memory insns.
1468 Moves between VFP_REGS and GENERAL_REGS are a single insn, but
1469 it is typically more expensive than a single memory access. We set
1470 the cost to less than two memory accesses so that floating
1471 point to integer conversion does not go through memory. */
cf011243 1472#define REGISTER_MOVE_COST(MODE, FROM, TO) \
5b3e6663 1473 (TARGET_32BIT ? \
3b684012
RE		 1474 ((FROM) == FPA_REGS && (TO) != FPA_REGS ? 20 : \
1475 (FROM) != FPA_REGS && (TO) == FPA_REGS ? 20 : \
356ecb15
DJ		 1476 IS_VFP_CLASS (FROM) && !IS_VFP_CLASS (TO) ? 15 : \
1477 !IS_VFP_CLASS (FROM) && IS_VFP_CLASS (TO) ? 15 : \
5a9335ef
NC		 1478 (FROM) == IWMMXT_REGS && (TO) != IWMMXT_REGS ? 4 : \
1479 (FROM) != IWMMXT_REGS && (TO) == IWMMXT_REGS ? 4 : \
1480 (FROM) == IWMMXT_GR_REGS || (TO) == IWMMXT_GR_REGS ? 20 : \
9b6b54e2
NC		 1481 (FROM) == CIRRUS_REGS && (TO) != CIRRUS_REGS ? 20 : \
1482 (FROM) != CIRRUS_REGS && (TO) == CIRRUS_REGS ? 20 : \
1483 2) \
d5b7b3ae
RE		 1484 : \
1485 ((FROM) == HI_REGS || (TO) == HI_REGS) ? 4 : 2)
35d965d5
RS		 1486\f
1487/* Stack layout; function entry, exit and calling. */
1488
1489/* Define this if pushing a word on the stack
1490 makes the stack pointer a smaller address. */
1491#define STACK_GROWS_DOWNWARD 1
1492
a4d05547 1493/* Define this to nonzero if the nominal address of the stack frame
35d965d5
RS		 1494 is at the high-address end of the local variables;
1495 that is, each additional local variable allocated
1496 goes at a more negative offset in the frame. */
1497#define FRAME_GROWS_DOWNWARD 1
1498
a2503645
RS		 1499/* The amount of scratch space needed by _interwork_{r7,r11}_call_via_rN().
1500 When present, it is one word in size, and sits at the top of the frame,
1501 between the soft frame pointer and either r7 or r11.
1502
1503 We only need _interwork_rM_call_via_rN() for -mcaller-super-interworking,
1504 and only then if some outgoing arguments are passed on the stack. It would
1505 be tempting to also check whether the stack arguments are passed by indirect
1506 calls, but there seems to be no reason in principle why a post-reload pass
1507 couldn't convert a direct call into an indirect one. */
1508#define CALLER_INTERWORKING_SLOT_SIZE \
1509 (TARGET_CALLER_INTERWORKING \
38173d38 1510 && crtl->outgoing_args_size != 0 \
a2503645
RS		 1511 ? UNITS_PER_WORD : 0)
1512
35d965d5
RS		 1513/* Offset within stack frame to start allocating local variables at.
1514 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1515 first local allocated. Otherwise, it is the offset to the BEGINNING
1516 of the first local allocated. */
1517#define STARTING_FRAME_OFFSET 0
1518
1519/* If we generate an insn to push BYTES bytes,
1520 this says how many the stack pointer really advances by. */
d5b7b3ae 1521/* The push insns do not do this rounding implicitly.
d6b4baa4 1522 So don't define this. */
0c2ca901 1523/* #define PUSH_ROUNDING(NPUSHED) ROUND_UP_WORD (NPUSHED) */
18543a22
ILT		 1524
1525/* Define this if the maximum size of all the outgoing args is to be
1526 accumulated and pushed during the prologue. The amount can be
38173d38 1527 found in the variable crtl->outgoing_args_size. */
6cfc7210 1528#define ACCUMULATE_OUTGOING_ARGS 1
35d965d5
RS		 1529
1530/* Offset of first parameter from the argument pointer register value. */
d5b7b3ae 1531#define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0)
35d965d5 1532
35d965d5
RS		 1533/* Define how to find the value returned by a library function
1534 assuming the value has mode MODE. */
390b17c2
RE		 1535#define LIBCALL_VALUE(MODE) \
1536 (TARGET_AAPCS_BASED ? aapcs_libcall_value (MODE) \
1537 : (TARGET_32BIT && TARGET_HARD_FLOAT_ABI && TARGET_FPA \
1538 && GET_MODE_CLASS (MODE) == MODE_FLOAT) \
9b66ebb1 1539 ? gen_rtx_REG (MODE, FIRST_FPA_REGNUM) \
5b3e6663 1540 : TARGET_32BIT && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK \
9b66ebb1 1541 && GET_MODE_CLASS (MODE) == MODE_FLOAT \
9b6b54e2 1542 ? gen_rtx_REG (MODE, FIRST_CIRRUS_FP_REGNUM) \
f676971a 1543 : TARGET_IWMMXT_ABI && arm_vector_mode_supported_p (MODE) \
5a9335ef 1544 ? gen_rtx_REG (MODE, FIRST_IWMMXT_REGNUM) \
d5b7b3ae 1545 : gen_rtx_REG (MODE, ARG_REGISTER (1)))
35d965d5 1546
390b17c2
RE		 1547/* 1 if REGNO is a possible register number for a function value. */
1548#define FUNCTION_VALUE_REGNO_P(REGNO) \
1549 ((REGNO) == ARG_REGISTER (1) \
1550 || (TARGET_AAPCS_BASED && TARGET_32BIT \
1551 && TARGET_VFP && TARGET_HARD_FLOAT \
1552 && (REGNO) == FIRST_VFP_REGNUM) \
1553 || (TARGET_32BIT && ((REGNO) == FIRST_CIRRUS_FP_REGNUM) \
1554 && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK) \
1555 || ((REGNO) == FIRST_IWMMXT_REGNUM && TARGET_IWMMXT_ABI) \
1556 || (TARGET_32BIT && ((REGNO) == FIRST_FPA_REGNUM) \
72cdc543 1557 && TARGET_HARD_FLOAT_ABI && TARGET_FPA))
35d965d5 1558
9f7bf991
RE		 1559/* Amount of memory needed for an untyped call to save all possible return
1560 registers. */
1561#define APPLY_RESULT_SIZE arm_apply_result_size()
1562
11c1a207
RE		 1563/* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return
1564 values must be in memory. On the ARM, they need only do so if larger
d6b4baa4 1565 than a word, or if they contain elements offset from zero in the struct. */
11c1a207
RE		 1566#define DEFAULT_PCC_STRUCT_RETURN 0
1567
6d3d9133 1568/* These bits describe the different types of function supported
112cdef5 1569 by the ARM backend. They are exclusive. i.e. a function cannot be both a
6d3d9133
NC		 1570 normal function and an interworked function, for example. Knowing the
1571 type of a function is important for determining its prologue and
1572 epilogue sequences.
1573 Note value 7 is currently unassigned. Also note that the interrupt
1574 function types all have bit 2 set, so that they can be tested for easily.
1575 Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the
4912a07c 1576 machine_function structure is initialized (to zero) func_type will
6d3d9133
NC		 1577 default to unknown. This will force the first use of arm_current_func_type
1578 to call arm_compute_func_type. */
1579#define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */
1580#define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */
1581#define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */
6d3d9133
NC		 1582#define ARM_FT_ISR 4 /* An interrupt service routine. */
1583#define ARM_FT_FIQ 5 /* A fast interrupt service routine. */
1584#define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */
1585
1586#define ARM_FT_TYPE_MASK ((1 << 3) - 1)
1587
1588/* In addition functions can have several type modifiers,
1589 outlined by these bit masks: */
1590#define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */
1591#define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */
1592#define ARM_FT_VOLATILE (1 << 4) /* Does not return. */
d6b4baa4 1593#define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */
5b3e6663 1594#define ARM_FT_STACKALIGN (1 << 6) /* Called with misaligned stack. */
6d3d9133
NC		 1595
1596/* Some macros to test these flags. */
1597#define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK)
1598#define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT)
1599#define IS_VOLATILE(t) (t & ARM_FT_VOLATILE)
1600#define IS_NAKED(t) (t & ARM_FT_NAKED)
1601#define IS_NESTED(t) (t & ARM_FT_NESTED)
5b3e6663 1602#define IS_STACKALIGN(t) (t & ARM_FT_STACKALIGN)
6d3d9133 1603
5848830f
PB		 1604
1605/* Structure used to hold the function stack frame layout. Offsets are
1606 relative to the stack pointer on function entry. Positive offsets are
1607 in the direction of stack growth.
1608 Only soft_frame is used in thumb mode. */
1609
d1b38208 1610typedef struct GTY(()) arm_stack_offsets
5848830f
PB		 1611{
1612 int saved_args; /* ARG_POINTER_REGNUM. */
1613 int frame; /* ARM_HARD_FRAME_POINTER_REGNUM. */
1614 int saved_regs;
1615 int soft_frame; /* FRAME_POINTER_REGNUM. */
2591db65 1616 int locals_base; /* THUMB_HARD_FRAME_POINTER_REGNUM. */
5848830f 1617 int outgoing_args; /* STACK_POINTER_REGNUM. */
954954d1 1618 unsigned int saved_regs_mask;
5848830f
PB		 1619}
1620arm_stack_offsets;
1621
906668bb 1622#ifndef GENERATOR_FILE
6d3d9133
NC		 1623/* A C structure for machine-specific, per-function data.
1624 This is added to the cfun structure. */
d1b38208 1625typedef struct GTY(()) machine_function
d5b7b3ae 1626{
6bc82793 1627 /* Additional stack adjustment in __builtin_eh_throw. */
e2500fed 1628 rtx eh_epilogue_sp_ofs;
d5b7b3ae
RE		 1629 /* Records if LR has to be saved for far jumps. */
1630 int far_jump_used;
1631 /* Records if ARG_POINTER was ever live. */
1632 int arg_pointer_live;
6f7ebcbb
NC		 1633 /* Records if the save of LR has been eliminated. */
1634 int lr_save_eliminated;
0977774b 1635 /* The size of the stack frame. Only valid after reload. */
5848830f 1636 arm_stack_offsets stack_offsets;
6d3d9133
NC		 1637 /* Records the type of the current function. */
1638 unsigned long func_type;
3cb66fd7
NC		 1639 /* Record if the function has a variable argument list. */
1640 int uses_anonymous_args;
5a9335ef
NC		 1641 /* Records if sibcalls are blocked because an argument
1642 register is needed to preserve stack alignment. */
1643 int sibcall_blocked;
020a4035
RE		 1644 /* The PIC register for this function. This might be a pseudo. */
1645 rtx pic_reg;
b12a00f1 1646 /* Labels for per-function Thumb call-via stubs. One per potential calling
57ecec57
PB		 1647 register. We can never call via LR or PC. We can call via SP if a
1648 trampoline happens to be on the top of the stack. */
1649 rtx call_via[14];
934c2060
RR		 1650 /* Set to 1 when a return insn is output, this means that the epilogue
1651 is not needed. */
1652 int return_used_this_function;
906668bb
BS		 1653 /* When outputting Thumb-1 code, record the last insn that provides
1654 information about condition codes, and the comparison operands. */
1655 rtx thumb1_cc_insn;
1656 rtx thumb1_cc_op0;
1657 rtx thumb1_cc_op1;
1658 /* Also record the CC mode that is supported. */
1659 enum machine_mode thumb1_cc_mode;
6d3d9133
NC		 1660}
1661machine_function;
906668bb 1662#endif
d5b7b3ae 1663
b12a00f1 1664/* As in the machine_function, a global set of call-via labels, for code
d6b5193b 1665 that is in text_section. */
57ecec57 1666extern GTY(()) rtx thumb_call_via_label[14];
b12a00f1 1667
390b17c2
RE		 1668/* The number of potential ways of assigning to a co-processor. */
1669#define ARM_NUM_COPROC_SLOTS 1
1670
1671/* Enumeration of procedure calling standard variants. We don't really
1672 support all of these yet. */
1673enum arm_pcs
1674{
1675 ARM_PCS_AAPCS, /* Base standard AAPCS. */
1676 ARM_PCS_AAPCS_VFP, /* Use VFP registers for floating point values. */
1677 ARM_PCS_AAPCS_IWMMXT, /* Use iWMMXT registers for vectors. */
1678 /* This must be the last AAPCS variant. */
1679 ARM_PCS_AAPCS_LOCAL, /* Private call within this compilation unit. */
1680 ARM_PCS_ATPCS, /* ATPCS. */
1681 ARM_PCS_APCS, /* APCS (legacy Linux etc). */
1682 ARM_PCS_UNKNOWN
1683};
1684
12ffc7d5
CLT		 1685/* Default procedure calling standard of current compilation unit. */
1686extern enum arm_pcs arm_pcs_default;
1687
82e9d970 1688/* A C type for declaring a variable that is used as the first argument of
390b17c2 1689 `FUNCTION_ARG' and other related values. */
82e9d970
PB		 1690typedef struct
1691{
d5b7b3ae 1692 /* This is the number of registers of arguments scanned so far. */
82e9d970 1693 int nregs;
5a9335ef
NC		 1694 /* This is the number of iWMMXt register arguments scanned so far. */
1695 int iwmmxt_nregs;
1696 int named_count;
1697 int nargs;
390b17c2
RE		 1698 /* Which procedure call variant to use for this call. */
1699 enum arm_pcs pcs_variant;
1700
1701 /* AAPCS related state tracking. */
1702 int aapcs_arg_processed; /* No need to lay out this argument again. */
1703 int aapcs_cprc_slot; /* Index of co-processor rules to handle
1704 this argument, or -1 if using core
1705 registers. */
1706 int aapcs_ncrn;
1707 int aapcs_next_ncrn;
1708 rtx aapcs_reg; /* Register assigned to this argument. */
1709 int aapcs_partial; /* How many bytes are passed in regs (if
1710 split between core regs and stack.
1711 Zero otherwise. */
1712 int aapcs_cprc_failed[ARM_NUM_COPROC_SLOTS];
1713 int can_split; /* Argument can be split between core regs
1714 and the stack. */
1715 /* Private data for tracking VFP register allocation */
1716 unsigned aapcs_vfp_regs_free;
1717 unsigned aapcs_vfp_reg_alloc;
1718 int aapcs_vfp_rcount;
46107b99 1719 MACHMODE aapcs_vfp_rmode;
d5b7b3ae 1720} CUMULATIVE_ARGS;
82e9d970 1721
866af8a9
JB		 1722#define FUNCTION_ARG_PADDING(MODE, TYPE) \
1723 (arm_pad_arg_upward (MODE, TYPE) ? upward : downward)
1724
1725#define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
1726 (arm_pad_reg_upward (MODE, TYPE, FIRST) ? upward : downward)
1727
1728/* For AAPCS, padding should never be below the argument. For other ABIs,
1729 * mimic the default. */
1730#define PAD_VARARGS_DOWN \
1731 ((TARGET_AAPCS_BASED) ? 0 : BYTES_BIG_ENDIAN)
1732
35d965d5
RS		 1733/* Initialize a variable CUM of type CUMULATIVE_ARGS
1734 for a call to a function whose data type is FNTYPE.
1735 For a library call, FNTYPE is 0.
1736 On the ARM, the offset starts at 0. */
0f6937fe 1737#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
563a317a 1738 arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL))
35d965d5 1739
5a9335ef
NC		 1740/* If defined, a C expression that gives the alignment boundary, in bits, of an
1741 argument with the specified mode and type. If it is not defined,
1742 `PARM_BOUNDARY' is used for all arguments. */
1743#define FUNCTION_ARG_BOUNDARY(MODE,TYPE) \
5848830f
PB		 1744 ((ARM_DOUBLEWORD_ALIGN && arm_needs_doubleword_align (MODE, TYPE)) \
1745 ? DOUBLEWORD_ALIGNMENT \
1746 : PARM_BOUNDARY )
5a9335ef 1747
35d965d5
RS		 1748/* 1 if N is a possible register number for function argument passing.
1749 On the ARM, r0-r3 are used to pass args. */
390b17c2
RE		 1750#define FUNCTION_ARG_REGNO_P(REGNO) \
1751 (IN_RANGE ((REGNO), 0, 3) \
1752 || (TARGET_AAPCS_BASED && TARGET_VFP && TARGET_HARD_FLOAT \
1753 && IN_RANGE ((REGNO), FIRST_VFP_REGNUM, FIRST_VFP_REGNUM + 15)) \
1754 || (TARGET_IWMMXT_ABI \
5848830f 1755 && IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9)))
35d965d5 1756
f99fce0c 1757\f
afef3d7a 1758/* If your target environment doesn't prefix user functions with an
96a3900d 1759 underscore, you may wish to re-define this to prevent any conflicts. */
afef3d7a
NC		 1760#ifndef ARM_MCOUNT_NAME
1761#define ARM_MCOUNT_NAME "*mcount"
1762#endif
1763
1764/* Call the function profiler with a given profile label. The Acorn
1765 compiler puts this BEFORE the prolog but gcc puts it afterwards.
1766 On the ARM the full profile code will look like:
1767 .data
1768 LP1
1769 .word 0
1770 .text
1771 mov ip, lr
1772 bl mcount
1773 .word LP1
1774
1775 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER
1776 will output the .text section.
1777
1778 The ``mov ip,lr'' seems like a good idea to stick with cc convention.
59be6073
AN		 1779 ``prof'' doesn't seem to mind about this!
1780
1781 Note - this version of the code is designed to work in both ARM and
1782 Thumb modes. */
be393ecf 1783#ifndef ARM_FUNCTION_PROFILER
d5b7b3ae 1784#define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \
6cfc7210
NC		 1785{ \
1786 char temp[20]; \
1787 rtx sym; \
1788 \
dd18ae56 1789 asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \
d5b7b3ae 1790 IP_REGNUM, LR_REGNUM); \
6cfc7210
NC		 1791 assemble_name (STREAM, ARM_MCOUNT_NAME); \
1792 fputc ('\n', STREAM); \
1793 ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \
f1c25d3b 1794 sym = gen_rtx_SYMBOL_REF (Pmode, temp); \
301d03af 1795 assemble_aligned_integer (UNITS_PER_WORD, sym); \
35d965d5 1796}
be393ecf 1797#endif
35d965d5 1798
59be6073 1799#ifdef THUMB_FUNCTION_PROFILER
d5b7b3ae
RE		 1800#define FUNCTION_PROFILER(STREAM, LABELNO) \
1801 if (TARGET_ARM) \
1802 ARM_FUNCTION_PROFILER (STREAM, LABELNO) \
1803 else \
1804 THUMB_FUNCTION_PROFILER (STREAM, LABELNO)
59be6073
AN		 1805#else
1806#define FUNCTION_PROFILER(STREAM, LABELNO) \
1807 ARM_FUNCTION_PROFILER (STREAM, LABELNO)
1808#endif
d5b7b3ae 1809
35d965d5
RS		 1810/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1811 the stack pointer does not matter. The value is tested only in
1812 functions that have frame pointers.
1813 No definition is equivalent to always zero.
1814
1815 On the ARM, the function epilogue recovers the stack pointer from the
1816 frame. */
1817#define EXIT_IGNORE_STACK 1
1818
6fb5fa3c 1819#define EPILOGUE_USES(REGNO) ((REGNO) == LR_REGNUM)
c7861455 1820
35d965d5
RS		 1821/* Determine if the epilogue should be output as RTL.
1822 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
d5b7b3ae 1823#define USE_RETURN_INSN(ISCOND) \
7c19c715 1824 (TARGET_32BIT ? use_return_insn (ISCOND, NULL) : 0)
ff9940b0
RE		 1825
1826/* Definitions for register eliminations.
1827
1828 This is an array of structures. Each structure initializes one pair
1829 of eliminable registers. The "from" register number is given first,
1830 followed by "to". Eliminations of the same "from" register are listed
1831 in order of preference.
1832
1833 We have two registers that can be eliminated on the ARM. First, the
1834 arg pointer register can often be eliminated in favor of the stack
1835 pointer register. Secondly, the pseudo frame pointer register can always
1836 be eliminated; it is replaced with either the stack or the real frame
d5b7b3ae 1837 pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM
d6a7951f 1838 because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */
ff9940b0 1839
d5b7b3ae
RE		 1840#define ELIMINABLE_REGS \
1841{{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1842 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\
1843 { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1844 { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\
1845 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1846 { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1847 { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }}
ff9940b0 1848
d5b7b3ae
RE		 1849/* Define the offset between two registers, one to be eliminated, and the
1850 other its replacement, at the start of a routine. */
d5b7b3ae
RE		 1851#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1852 if (TARGET_ARM) \
5848830f 1853 (OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \
d5b7b3ae 1854 else \
5848830f
PB		 1855 (OFFSET) = thumb_compute_initial_elimination_offset (FROM, TO)
1856
d5b7b3ae
RE		 1857/* Special case handling of the location of arguments passed on the stack. */
1858#define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr)
f676971a 1859
d5b7b3ae
RE		 1860/* Initialize data used by insn expanders. This is called from insn_emit,
1861 once for every function before code is generated. */
1862#define INIT_EXPANDERS arm_init_expanders ()
1863
35d965d5 1864/* Length in units of the trampoline for entering a nested function. */
5b3e6663 1865#define TRAMPOLINE_SIZE (TARGET_32BIT ? 16 : 20)
35d965d5 1866
006946e4
JM		 1867/* Alignment required for a trampoline in bits. */
1868#define TRAMPOLINE_ALIGNMENT 32
35d965d5
RS		 1869\f
1870/* Addressing modes, and classification of registers for them. */
3cd45774 1871#define HAVE_POST_INCREMENT 1
5b3e6663
PB		 1872#define HAVE_PRE_INCREMENT TARGET_32BIT
1873#define HAVE_POST_DECREMENT TARGET_32BIT
1874#define HAVE_PRE_DECREMENT TARGET_32BIT
1875#define HAVE_PRE_MODIFY_DISP TARGET_32BIT
1876#define HAVE_POST_MODIFY_DISP TARGET_32BIT
1877#define HAVE_PRE_MODIFY_REG TARGET_32BIT
1878#define HAVE_POST_MODIFY_REG TARGET_32BIT
35d965d5
RS		 1879
1880/* Macros to check register numbers against specific register classes. */
1881
1882/* These assume that REGNO is a hard or pseudo reg number.
1883 They give nonzero only if REGNO is a hard reg of the suitable class
1884 or a pseudo reg currently allocated to a suitable hard reg.
1885 Since they use reg_renumber, they are safe only once reg_renumber
d6b4baa4 1886 has been allocated, which happens in local-alloc.c. */
d5b7b3ae
RE		 1887#define TEST_REGNO(R, TEST, VALUE) \
1888 ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE))
1889
5b3e6663 1890/* Don't allow the pc to be used. */
f1008e52
RE		 1891#define ARM_REGNO_OK_FOR_BASE_P(REGNO) \
1892 (TEST_REGNO (REGNO, <, PC_REGNUM) \
1893 || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \
1894 || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM))
1895
5b3e6663 1896#define THUMB1_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
f1008e52
RE		 1897 (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \
1898 || (GET_MODE_SIZE (MODE) >= 4 \
1899 && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)))
1900
1901#define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
5b3e6663
PB		 1902 (TARGET_THUMB1 \
1903 ? THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \
f1008e52
RE		 1904 : ARM_REGNO_OK_FOR_BASE_P (REGNO))
1905
888d2cd6
DJ		 1906/* Nonzero if X can be the base register in a reg+reg addressing mode.
1907 For Thumb, we can not use SP + reg, so reject SP. */
1908#define REGNO_MODE_OK_FOR_REG_BASE_P(X, MODE) \
f5c630c3 1909 REGNO_MODE_OK_FOR_BASE_P (X, QImode)
888d2cd6 1910
f1008e52
RE		 1911/* For ARM code, we don't care about the mode, but for Thumb, the index
1912 must be suitable for use in a QImode load. */
d5b7b3ae 1913#define REGNO_OK_FOR_INDEX_P(REGNO) \
f5c630c3
PB		 1914 (REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode) \
1915 && !TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM))
35d965d5
RS		 1916
1917/* Maximum number of registers that can appear in a valid memory address.
d6b4baa4 1918 Shifts in addresses can't be by a register. */
ff9940b0 1919#define MAX_REGS_PER_ADDRESS 2
35d965d5
RS		 1920
1921/* Recognize any constant value that is a valid address. */
1922/* XXX We can address any constant, eventually... */
5b3e6663 1923/* ??? Should the TARGET_ARM here also apply to thumb2? */
008cf58a
RE		 1924#define CONSTANT_ADDRESS_P(X) \
1925 (GET_CODE (X) == SYMBOL_REF \
1926 && (CONSTANT_POOL_ADDRESS_P (X) \
d5b7b3ae 1927 || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X))))
35d965d5 1928
8426b956
RS		 1929/* True if SYMBOL + OFFSET constants must refer to something within
1930 SYMBOL's section. */
1931#define ARM_OFFSETS_MUST_BE_WITHIN_SECTIONS_P 0
1932
571191af
PB		 1933/* Nonzero if all target requires all absolute relocations be R_ARM_ABS32. */
1934#ifndef TARGET_DEFAULT_WORD_RELOCATIONS
1935#define TARGET_DEFAULT_WORD_RELOCATIONS 0
1936#endif
1937
35d965d5
RS		 1938/* Nonzero if the constant value X is a legitimate general operand.
1939 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1940
1941 On the ARM, allow any integer (invalid ones are removed later by insn
1942 patterns), nice doubles and symbol_refs which refer to the function's
d5b7b3ae 1943 constant pool XXX.
f676971a 1944
82e9d970 1945 When generating pic allow anything. */
d5b7b3ae
RE		 1946#define ARM_LEGITIMATE_CONSTANT_P(X) (flag_pic || ! label_mentioned_p (X))
1947
1948#define THUMB_LEGITIMATE_CONSTANT_P(X) \
1949 ( GET_CODE (X) == CONST_INT \
1950 || GET_CODE (X) == CONST_DOUBLE \
7b8781c8
PB		 1951 || CONSTANT_ADDRESS_P (X) \
1952 || flag_pic)
d5b7b3ae 1953
d3585b76 1954#define LEGITIMATE_CONSTANT_P(X) \
8426b956 1955 (!arm_cannot_force_const_mem (X) \
5b3e6663
PB		 1956 && (TARGET_32BIT ? ARM_LEGITIMATE_CONSTANT_P (X) \
1957 : THUMB_LEGITIMATE_CONSTANT_P (X)))
d5b7b3ae 1958
c27ba912
DM		 1959#ifndef SUBTARGET_NAME_ENCODING_LENGTHS
1960#define SUBTARGET_NAME_ENCODING_LENGTHS
1961#endif
1962
6bc82793 1963/* This is a C fragment for the inside of a switch statement.
c27ba912
DM		 1964 Each case label should return the number of characters to
1965 be stripped from the start of a function's name, if that
1966 name starts with the indicated character. */
1967#define ARM_NAME_ENCODING_LENGTHS \
00fdafef 1968 case '*': return 1; \
f676971a 1969 SUBTARGET_NAME_ENCODING_LENGTHS
c27ba912 1970
c27ba912
DM		 1971/* This is how to output a reference to a user-level label named NAME.
1972 `assemble_name' uses this. */
e5951263 1973#undef ASM_OUTPUT_LABELREF
c27ba912 1974#define ASM_OUTPUT_LABELREF(FILE, NAME) \
e1944073 1975 arm_asm_output_labelref (FILE, NAME)
c27ba912 1976
7a085dce 1977/* Output IT instructions for conditionally executed Thumb-2 instructions. */
5b3e6663
PB		 1978#define ASM_OUTPUT_OPCODE(STREAM, PTR) \
1979 if (TARGET_THUMB2) \
1980 thumb2_asm_output_opcode (STREAM);
1981
7abc66b1
JB		 1982/* The EABI specifies that constructors should go in .init_array.
1983 Other targets use .ctors for compatibility. */
88c6057f 1984#ifndef ARM_EABI_CTORS_SECTION_OP
7abc66b1
JB		 1985#define ARM_EABI_CTORS_SECTION_OP \
1986 "\t.section\t.init_array,\"aw\",%init_array"
88c6057f
MM		 1987#endif
1988#ifndef ARM_EABI_DTORS_SECTION_OP
7abc66b1
JB		 1989#define ARM_EABI_DTORS_SECTION_OP \
1990 "\t.section\t.fini_array,\"aw\",%fini_array"
88c6057f 1991#endif
7abc66b1
JB		 1992#define ARM_CTORS_SECTION_OP \
1993 "\t.section\t.ctors,\"aw\",%progbits"
1994#define ARM_DTORS_SECTION_OP \
1995 "\t.section\t.dtors,\"aw\",%progbits"
1996
1997/* Define CTORS_SECTION_ASM_OP. */
1998#undef CTORS_SECTION_ASM_OP
1999#undef DTORS_SECTION_ASM_OP
2000#ifndef IN_LIBGCC2
2001# define CTORS_SECTION_ASM_OP \
2002 (TARGET_AAPCS_BASED ? ARM_EABI_CTORS_SECTION_OP : ARM_CTORS_SECTION_OP)
2003# define DTORS_SECTION_ASM_OP \
2004 (TARGET_AAPCS_BASED ? ARM_EABI_DTORS_SECTION_OP : ARM_DTORS_SECTION_OP)
2005#else /* !defined (IN_LIBGCC2) */
2006/* In libgcc, CTORS_SECTION_ASM_OP must be a compile-time constant,
2007 so we cannot use the definition above. */
2008# ifdef __ARM_EABI__
2009/* The .ctors section is not part of the EABI, so we do not define
2010 CTORS_SECTION_ASM_OP when in libgcc; that prevents crtstuff
2011 from trying to use it. We do define it when doing normal
2012 compilation, as .init_array can be used instead of .ctors. */
2013/* There is no need to emit begin or end markers when using
2014 init_array; the dynamic linker will compute the size of the
2015 array itself based on special symbols created by the static
2016 linker. However, we do need to arrange to set up
2017 exception-handling here. */
2018# define CTOR_LIST_BEGIN asm (ARM_EABI_CTORS_SECTION_OP)
2019# define CTOR_LIST_END /* empty */
2020# define DTOR_LIST_BEGIN asm (ARM_EABI_DTORS_SECTION_OP)
2021# define DTOR_LIST_END /* empty */
2022# else /* !defined (__ARM_EABI__) */
2023# define CTORS_SECTION_ASM_OP ARM_CTORS_SECTION_OP
2024# define DTORS_SECTION_ASM_OP ARM_DTORS_SECTION_OP
2025# endif /* !defined (__ARM_EABI__) */
2026#endif /* !defined (IN_LIBCC2) */
2027
1e731102
MM		 2028/* True if the operating system can merge entities with vague linkage
2029 (e.g., symbols in COMDAT group) during dynamic linking. */
2030#ifndef TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P
2031#define TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P true
2032#endif
2033
617a1b71
PB		 2034#define ARM_OUTPUT_FN_UNWIND(F, PROLOGUE) arm_output_fn_unwind (F, PROLOGUE)
2035
35d965d5
RS		 2036/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2037 and check its validity for a certain class.
2038 We have two alternate definitions for each of them.
2039 The usual definition accepts all pseudo regs; the other rejects
2040 them unless they have been allocated suitable hard regs.
5b3e6663 2041 The symbol REG_OK_STRICT causes the latter definition to be used.
7a085dce 2042 Thumb-2 has the same restrictions as arm. */
35d965d5 2043#ifndef REG_OK_STRICT
ff9940b0 2044
f1008e52
RE		 2045#define ARM_REG_OK_FOR_BASE_P(X) \
2046 (REGNO (X) <= LAST_ARM_REGNUM \
2047 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
2048 || REGNO (X) == FRAME_POINTER_REGNUM \
2049 || REGNO (X) == ARG_POINTER_REGNUM)
ff9940b0 2050
f5c630c3
PB		 2051#define ARM_REG_OK_FOR_INDEX_P(X) \
2052 ((REGNO (X) <= LAST_ARM_REGNUM \
2053 && REGNO (X) != STACK_POINTER_REGNUM) \
2054 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
2055 || REGNO (X) == FRAME_POINTER_REGNUM \
2056 || REGNO (X) == ARG_POINTER_REGNUM)
2057
5b3e6663 2058#define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \
f1008e52
RE		 2059 (REGNO (X) <= LAST_LO_REGNUM \
2060 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
2061 || (GET_MODE_SIZE (MODE) >= 4 \
2062 && (REGNO (X) == STACK_POINTER_REGNUM \
2063 || (X) == hard_frame_pointer_rtx \
2064 || (X) == arg_pointer_rtx)))
ff9940b0 2065
76a318e9
RE		 2066#define REG_STRICT_P 0
2067
d5b7b3ae 2068#else /* REG_OK_STRICT */
ff9940b0 2069
f1008e52
RE		 2070#define ARM_REG_OK_FOR_BASE_P(X) \
2071 ARM_REGNO_OK_FOR_BASE_P (REGNO (X))
ff9940b0 2072
f5c630c3
PB		 2073#define ARM_REG_OK_FOR_INDEX_P(X) \
2074 ARM_REGNO_OK_FOR_INDEX_P (REGNO (X))
2075
5b3e6663
PB		 2076#define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \
2077 THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE)
ff9940b0 2078
76a318e9
RE		 2079#define REG_STRICT_P 1
2080
d5b7b3ae 2081#endif /* REG_OK_STRICT */
f1008e52
RE		 2082
2083/* Now define some helpers in terms of the above. */
2084
2085#define REG_MODE_OK_FOR_BASE_P(X, MODE) \
5b3e6663
PB		 2086 (TARGET_THUMB1 \
2087 ? THUMB1_REG_MODE_OK_FOR_BASE_P (X, MODE) \
f1008e52
RE		 2088 : ARM_REG_OK_FOR_BASE_P (X))
2089
5b3e6663 2090/* For 16-bit Thumb, a valid index register is anything that can be used in
f1008e52 2091 a byte load instruction. */
5b3e6663
PB		 2092#define THUMB1_REG_OK_FOR_INDEX_P(X) \
2093 THUMB1_REG_MODE_OK_FOR_BASE_P (X, QImode)
f1008e52
RE		 2094
2095/* Nonzero if X is a hard reg that can be used as an index
2096 or if it is a pseudo reg. On the Thumb, the stack pointer
2097 is not suitable. */
2098#define REG_OK_FOR_INDEX_P(X) \
5b3e6663
PB		 2099 (TARGET_THUMB1 \
2100 ? THUMB1_REG_OK_FOR_INDEX_P (X) \
f1008e52
RE		 2101 : ARM_REG_OK_FOR_INDEX_P (X))
2102
888d2cd6
DJ		 2103/* Nonzero if X can be the base register in a reg+reg addressing mode.
2104 For Thumb, we can not use SP + reg, so reject SP. */
2105#define REG_MODE_OK_FOR_REG_BASE_P(X, MODE) \
2106 REG_OK_FOR_INDEX_P (X)
35d965d5 2107\f
f1008e52
RE		 2108#define ARM_BASE_REGISTER_RTX_P(X) \
2109 (GET_CODE (X) == REG && ARM_REG_OK_FOR_BASE_P (X))
35d965d5 2110
f1008e52
RE		 2111#define ARM_INDEX_REGISTER_RTX_P(X) \
2112 (GET_CODE (X) == REG && ARM_REG_OK_FOR_INDEX_P (X))
35d965d5 2113\f
360032ba
JY		 2114/* Define this for compatibility reasons. */
2115#define HANDLE_PRAGMA_PACK_PUSH_POP
d5b7b3ae 2116
35d965d5
RS		 2117/* Specify the machine mode that this machine uses
2118 for the index in the tablejump instruction. */
d5b7b3ae 2119#define CASE_VECTOR_MODE Pmode
35d965d5 2120
907dd0c7 2121#define CASE_VECTOR_PC_RELATIVE (TARGET_THUMB2 \
83c3a2d8 2122 || (TARGET_THUMB1 \
907dd0c7
RE		 2123 && (optimize_size || flag_pic)))
2124
2125#define CASE_VECTOR_SHORTEN_MODE(min, max, body) \
83c3a2d8 2126 (TARGET_THUMB1 \
907dd0c7
RE		 2127 ? (min >= 0 && max < 512 \
2128 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 1, QImode) \
2129 : min >= -256 && max < 256 \
2130 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, QImode) \
2131 : min >= 0 && max < 8192 \
2132 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 1, HImode) \
2133 : min >= -4096 && max < 4096 \
2134 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, HImode) \
2135 : SImode) \
2136 : ((min < 0 || max >= 0x2000 || !TARGET_THUMB2) ? SImode \
2137 : (max >= 0x200) ? HImode \
2138 : QImode))
5b3e6663 2139
ff9940b0
RE		 2140/* signed 'char' is most compatible, but RISC OS wants it unsigned.
2141 unsigned is probably best, but may break some code. */
2142#ifndef DEFAULT_SIGNED_CHAR
3967692c 2143#define DEFAULT_SIGNED_CHAR 0
35d965d5
RS		 2144#endif
2145
35d965d5 2146/* Max number of bytes we can move from memory to memory
d17ce9af
TG		 2147 in one reasonably fast instruction. */
2148#define MOVE_MAX 4
35d965d5 2149
d19fb8e3 2150#undef MOVE_RATIO
e04ad03d 2151#define MOVE_RATIO(speed) (arm_tune_xscale ? 4 : 2)
d19fb8e3 2152
ff9940b0
RE		 2153/* Define if operations between registers always perform the operation
2154 on the full register even if a narrower mode is specified. */
2155#define WORD_REGISTER_OPERATIONS
2156
2157/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2158 will either zero-extend or sign-extend. The value of this macro should
2159 be the code that says which one of the two operations is implicitly
f822d252 2160 done, UNKNOWN if none. */
9c872872 2161#define LOAD_EXTEND_OP(MODE) \
d5b7b3ae
RE		 2162 (TARGET_THUMB ? ZERO_EXTEND : \
2163 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \
f822d252 2164 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : UNKNOWN)))
ff9940b0 2165
35d965d5
RS		 2166/* Nonzero if access to memory by bytes is slow and undesirable. */
2167#define SLOW_BYTE_ACCESS 0
2168
d5b7b3ae 2169#define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1
f676971a 2170
35d965d5
RS		 2171/* Immediate shift counts are truncated by the output routines (or was it
2172 the assembler?). Shift counts in a register are truncated by ARM. Note
2173 that the native compiler puts too large (> 32) immediate shift counts
2174 into a register and shifts by the register, letting the ARM decide what
2175 to do instead of doing that itself. */
ff9940b0
RE		 2176/* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that
2177 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
2178 On the arm, Y in a register is used modulo 256 for the shift. Only for
d6b4baa4 2179 rotates is modulo 32 used. */
ff9940b0 2180/* #define SHIFT_COUNT_TRUNCATED 1 */
35d965d5 2181
35d965d5 2182/* All integers have the same format so truncation is easy. */
d5b7b3ae 2183#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
35d965d5
RS		 2184
2185/* Calling from registers is a massive pain. */
2186#define NO_FUNCTION_CSE 1
2187
35d965d5
RS		 2188/* The machine modes of pointers and functions */
2189#define Pmode SImode
2190#define FUNCTION_MODE Pmode
2191
d5b7b3ae
RE		 2192#define ARM_FRAME_RTX(X) \
2193 ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
3967692c
RE		 2194 || (X) == arg_pointer_rtx)
2195
ff9940b0 2196/* Moves to and from memory are quite expensive */
d5b7b3ae 2197#define MEMORY_MOVE_COST(M, CLASS, IN) \
5b3e6663 2198 (TARGET_32BIT ? 10 : \
d5b7b3ae
RE		 2199 ((GET_MODE_SIZE (M) < 4 ? 8 : 2 * GET_MODE_SIZE (M)) \
2200 * (CLASS == LO_REGS ? 1 : 2)))
f676971a 2201
ff9940b0
RE		 2202/* Try to generate sequences that don't involve branches, we can then use
2203 conditional instructions */
3a4fd356 2204#define BRANCH_COST(speed_p, predictable_p) \
5b3e6663 2205 (TARGET_32BIT ? 4 : (optimize > 0 ? 2 : 0))
7a801826
RE		 2206\f
2207/* Position Independent Code. */
2208/* We decide which register to use based on the compilation options and
2209 the assembler in use; this is more general than the APCS restriction of
2210 using sb (r9) all the time. */
020a4035 2211extern unsigned arm_pic_register;
7a801826
RE		 2212
2213/* The register number of the register used to address a table of static
2214 data addresses in memory. */
2215#define PIC_OFFSET_TABLE_REGNUM arm_pic_register
2216
f5a1b0d2 2217/* We can't directly access anything that contains a symbol,
d3585b76
DJ		 2218 nor can we indirect via the constant pool. One exception is
2219 UNSPEC_TLS, which is always PIC. */
82e9d970 2220#define LEGITIMATE_PIC_OPERAND_P(X) \
1575c31e
JD		 2221 (!(symbol_mentioned_p (X) \
2222 || label_mentioned_p (X) \
2223 || (GET_CODE (X) == SYMBOL_REF \
2224 && CONSTANT_POOL_ADDRESS_P (X) \
2225 && (symbol_mentioned_p (get_pool_constant (X)) \
d3585b76
DJ		 2226 || label_mentioned_p (get_pool_constant (X))))) \
2227 || tls_mentioned_p (X))
1575c31e 2228
13bd191d
PB		 2229/* We need to know when we are making a constant pool; this determines
2230 whether data needs to be in the GOT or can be referenced via a GOT
2231 offset. */
2232extern int making_const_table;
82e9d970 2233\f
c27ba912 2234/* Handle pragmas for compatibility with Intel's compilers. */
b76c3c4b 2235/* Also abuse this to register additional C specific EABI attributes. */
c58b209a
NB		 2236#define REGISTER_TARGET_PRAGMAS() do { \
2237 c_register_pragma (0, "long_calls", arm_pr_long_calls); \
2238 c_register_pragma (0, "no_long_calls", arm_pr_no_long_calls); \
2239 c_register_pragma (0, "long_calls_off", arm_pr_long_calls_off); \
b76c3c4b 2240 arm_lang_object_attributes_init(); \
8b97c5f8
ZW		 2241} while (0)
2242
d6b4baa4 2243/* Condition code information. */
ff9940b0 2244/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
a5381466 2245 return the mode to be used for the comparison. */
d5b7b3ae
RE		 2246
2247#define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y)
ff9940b0 2248
880873be
RE		 2249#define REVERSIBLE_CC_MODE(MODE) 1
2250
2251#define REVERSE_CONDITION(CODE,MODE) \
2252 (((MODE) == CCFPmode || (MODE) == CCFPEmode) \
2253 ? reverse_condition_maybe_unordered (code) \
2254 : reverse_condition (code))
008cf58a 2255
62b10bbc 2256#define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \
73160ba9 2257 (CODE) = arm_canonicalize_comparison (CODE, &(OP0), &(OP1))
62dd06ea 2258
7dba8395
RH		 2259/* The arm5 clz instruction returns 32. */
2260#define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
ca96ed43 2261#define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
35d965d5 2262\f
906668bb
BS		 2263#define CC_STATUS_INIT \
2264 do { cfun->machine->thumb1_cc_insn = NULL_RTX; } while (0)
2265
d5b7b3ae 2266#undef ASM_APP_OFF
5b3e6663
PB		 2267#define ASM_APP_OFF (TARGET_THUMB1 ? "\t.code\t16\n" : \
2268 TARGET_THUMB2 ? "\t.thumb\n" : "")
35d965d5 2269
2ee67fbb
JB		 2270/* Output a push or a pop instruction (only used when profiling).
2271 We can't push STATIC_CHAIN_REGNUM (r12) directly with Thumb-1. We know
2272 that ASM_OUTPUT_REG_PUSH will be matched with ASM_OUTPUT_REG_POP, and
2273 that r7 isn't used by the function profiler, so we can use it as a
2274 scratch reg. WARNING: This isn't safe in the general case! It may be
2275 sensitive to future changes in final.c:profile_function. */
d5b7b3ae 2276#define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \
8a81cc45
RE		 2277 do \
2278 { \
2279 if (TARGET_ARM) \
2280 asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", \
2281 STACK_POINTER_REGNUM, REGNO); \
2ee67fbb
JB		 2282 else if (TARGET_THUMB1 \
2283 && (REGNO) == STATIC_CHAIN_REGNUM) \
2284 { \
2285 asm_fprintf (STREAM, "\tpush\t{r7}\n"); \
2286 asm_fprintf (STREAM, "\tmov\tr7, %r\n", REGNO);\
2287 asm_fprintf (STREAM, "\tpush\t{r7}\n"); \
2288 } \
8a81cc45
RE		 2289 else \
2290 asm_fprintf (STREAM, "\tpush {%r}\n", REGNO); \
2291 } while (0)
d5b7b3ae
RE		 2292
2293
2ee67fbb 2294/* See comment for ASM_OUTPUT_REG_PUSH concerning Thumb-1 issue. */
d5b7b3ae 2295#define ASM_OUTPUT_REG_POP(STREAM, REGNO) \
8a81cc45
RE		 2296 do \
2297 { \
2298 if (TARGET_ARM) \
2299 asm_fprintf (STREAM, "\tldmfd\t%r!,{%r}\n", \
2300 STACK_POINTER_REGNUM, REGNO); \
2ee67fbb
JB		 2301 else if (TARGET_THUMB1 \
2302 && (REGNO) == STATIC_CHAIN_REGNUM) \
2303 { \
2304 asm_fprintf (STREAM, "\tpop\t{r7}\n"); \
2305 asm_fprintf (STREAM, "\tmov\t%r, r7\n", REGNO);\
2306 asm_fprintf (STREAM, "\tpop\t{r7}\n"); \
2307 } \
8a81cc45
RE		 2308 else \
2309 asm_fprintf (STREAM, "\tpop {%r}\n", REGNO); \
2310 } while (0)
d5b7b3ae 2311
5b3e6663
PB		 2312/* Jump table alignment is explicit in ASM_OUTPUT_CASE_LABEL. */
2313#define ADDR_VEC_ALIGN(JUMPTABLE) 0
2314
d5b7b3ae
RE		 2315/* This is how to output a label which precedes a jumptable. Since
2316 Thumb instructions are 2 bytes, we may need explicit alignment here. */
be393ecf 2317#undef ASM_OUTPUT_CASE_LABEL
5b3e6663
PB		 2318#define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, JUMPTABLE) \
2319 do \
2320 { \
2321 if (TARGET_THUMB && GET_MODE (PATTERN (JUMPTABLE)) == SImode) \
2322 ASM_OUTPUT_ALIGN (FILE, 2); \
2323 (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \
2324 } \
2325 while (0)
2326
2327/* Make sure subsequent insns are aligned after a TBB. */
2328#define ASM_OUTPUT_CASE_END(FILE, NUM, JUMPTABLE) \
2329 do \
2330 { \
2331 if (GET_MODE (PATTERN (JUMPTABLE)) == QImode) \
2332 ASM_OUTPUT_ALIGN (FILE, 1); \
2333 } \
d5b7b3ae 2334 while (0)
35d965d5 2335
6cfc7210
NC		 2336#define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \
2337 do \
2338 { \
d5b7b3ae
RE		 2339 if (TARGET_THUMB) \
2340 { \
5b3e6663 2341 if (is_called_in_ARM_mode (DECL) \
bf98ec6c 2342 || (TARGET_THUMB1 && !TARGET_THUMB1_ONLY \
3c072c6b 2343 && cfun->is_thunk)) \
d5b7b3ae 2344 fprintf (STREAM, "\t.code 32\n") ; \
5b3e6663
PB		 2345 else if (TARGET_THUMB1) \
2346 fprintf (STREAM, "\t.code\t16\n\t.thumb_func\n") ; \
d5b7b3ae 2347 else \
5b3e6663 2348 fprintf (STREAM, "\t.thumb\n\t.thumb_func\n") ; \
d5b7b3ae 2349 } \
6cfc7210 2350 if (TARGET_POKE_FUNCTION_NAME) \
586de218 2351 arm_poke_function_name (STREAM, (const char *) NAME); \
6cfc7210
NC		 2352 } \
2353 while (0)
35d965d5 2354
d5b7b3ae
RE		 2355/* For aliases of functions we use .thumb_set instead. */
2356#define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \
2357 do \
2358 { \
91ea4f8d
KG		 2359 const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \
2360 const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \
d5b7b3ae
RE		 2361 \
2362 if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \
2363 { \
2364 fprintf (FILE, "\t.thumb_set "); \
2365 assemble_name (FILE, LABEL1); \
2366 fprintf (FILE, ","); \
2367 assemble_name (FILE, LABEL2); \
2368 fprintf (FILE, "\n"); \
2369 } \
2370 else \
2371 ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \
2372 } \
2373 while (0)
2374
fdc2d3b0
NC		 2375#ifdef HAVE_GAS_MAX_SKIP_P2ALIGN
2376/* To support -falign-* switches we need to use .p2align so
2377 that alignment directives in code sections will be padded
2378 with no-op instructions, rather than zeroes. */
5a9335ef 2379#define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE, LOG, MAX_SKIP) \
fdc2d3b0
NC		 2380 if ((LOG) != 0) \
2381 { \
2382 if ((MAX_SKIP) == 0) \
5a9335ef 2383 fprintf ((FILE), "\t.p2align %d\n", (int) (LOG)); \
fdc2d3b0
NC		 2384 else \
2385 fprintf ((FILE), "\t.p2align %d,,%d\n", \
5a9335ef 2386 (int) (LOG), (int) (MAX_SKIP)); \
fdc2d3b0
NC		 2387 }
2388#endif
35d965d5 2389\f
5b3e6663
PB		 2390/* Add two bytes to the length of conditionally executed Thumb-2
2391 instructions for the IT instruction. */
2392#define ADJUST_INSN_LENGTH(insn, length) \
2393 if (TARGET_THUMB2 && GET_CODE (PATTERN (insn)) == COND_EXEC) \
2394 length += 2;
2395
35d965d5 2396/* Only perform branch elimination (by making instructions conditional) if
5b3e6663
PB		 2397 we're optimizing. For Thumb-2 check if any IT instructions need
2398 outputting. */
d5b7b3ae
RE		 2399#define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2400 if (TARGET_ARM && optimize) \
2401 arm_final_prescan_insn (INSN); \
5b3e6663
PB		 2402 else if (TARGET_THUMB2) \
2403 thumb2_final_prescan_insn (INSN); \
2404 else if (TARGET_THUMB1) \
2405 thumb1_final_prescan_insn (INSN)
35d965d5 2406
7b8b8ade
NC		 2407#define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \
2408 (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \
30cf4896
KG		 2409 : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\
2410 ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \
2411 ? ((~ (unsigned HOST_WIDE_INT) 0) \
2412 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \
7bc7696c 2413 : 0))))
35d965d5 2414
6a5d7526
MS		 2415/* A C expression whose value is RTL representing the value of the return
2416 address for the frame COUNT steps up from the current frame. */
2417
d5b7b3ae
RE		 2418#define RETURN_ADDR_RTX(COUNT, FRAME) \
2419 arm_return_addr (COUNT, FRAME)
2420
f676971a 2421/* Mask of the bits in the PC that contain the real return address
d5b7b3ae
RE		 2422 when running in 26-bit mode. */
2423#define RETURN_ADDR_MASK26 (0x03fffffc)
6a5d7526 2424
2c849145
JM		 2425/* Pick up the return address upon entry to a procedure. Used for
2426 dwarf2 unwind information. This also enables the table driven
2427 mechanism. */
2c849145
JM		 2428#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM)
2429#define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM)
2430
39950dff
MS		 2431/* Used to mask out junk bits from the return address, such as
2432 processor state, interrupt status, condition codes and the like. */
2433#define MASK_RETURN_ADDR \
2434 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \
2435 in 26 bit mode, the condition codes must be masked out of the \
2436 return address. This does not apply to ARM6 and later processors \
2437 when running in 32 bit mode. */ \
61f0ccff
RE		 2438 ((arm_arch4 || TARGET_THUMB) \
2439 ? (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \
fcd53748 2440 : arm_gen_return_addr_mask ())
d5b7b3ae
RE		 2441
2442\f
88f77cba
JB		 2443/* Neon defines builtins from ARM_BUILTIN_MAX upwards, though they don't have
2444 symbolic names defined here (which would require too much duplication).
2445 FIXME? */
5a9335ef
NC		 2446enum arm_builtins
2447{
2448 ARM_BUILTIN_GETWCX,
2449 ARM_BUILTIN_SETWCX,
2450
2451 ARM_BUILTIN_WZERO,
2452
2453 ARM_BUILTIN_WAVG2BR,
2454 ARM_BUILTIN_WAVG2HR,
2455 ARM_BUILTIN_WAVG2B,
2456 ARM_BUILTIN_WAVG2H,
2457
2458 ARM_BUILTIN_WACCB,
2459 ARM_BUILTIN_WACCH,
2460 ARM_BUILTIN_WACCW,
2461
2462 ARM_BUILTIN_WMACS,
2463 ARM_BUILTIN_WMACSZ,
2464 ARM_BUILTIN_WMACU,
2465 ARM_BUILTIN_WMACUZ,
2466
2467 ARM_BUILTIN_WSADB,
2468 ARM_BUILTIN_WSADBZ,
2469 ARM_BUILTIN_WSADH,
2470 ARM_BUILTIN_WSADHZ,
2471
2472 ARM_BUILTIN_WALIGN,
2473
2474 ARM_BUILTIN_TMIA,
2475 ARM_BUILTIN_TMIAPH,
2476 ARM_BUILTIN_TMIABB,
2477 ARM_BUILTIN_TMIABT,
2478 ARM_BUILTIN_TMIATB,
2479 ARM_BUILTIN_TMIATT,
2480
2481 ARM_BUILTIN_TMOVMSKB,
2482 ARM_BUILTIN_TMOVMSKH,
2483 ARM_BUILTIN_TMOVMSKW,
2484
2485 ARM_BUILTIN_TBCSTB,
2486 ARM_BUILTIN_TBCSTH,
2487 ARM_BUILTIN_TBCSTW,
2488
2489 ARM_BUILTIN_WMADDS,
2490 ARM_BUILTIN_WMADDU,
2491
2492 ARM_BUILTIN_WPACKHSS,
2493 ARM_BUILTIN_WPACKWSS,
2494 ARM_BUILTIN_WPACKDSS,
2495 ARM_BUILTIN_WPACKHUS,
2496 ARM_BUILTIN_WPACKWUS,
2497 ARM_BUILTIN_WPACKDUS,
2498
2499 ARM_BUILTIN_WADDB,
2500 ARM_BUILTIN_WADDH,
2501 ARM_BUILTIN_WADDW,
2502 ARM_BUILTIN_WADDSSB,
2503 ARM_BUILTIN_WADDSSH,
2504 ARM_BUILTIN_WADDSSW,
2505 ARM_BUILTIN_WADDUSB,
2506 ARM_BUILTIN_WADDUSH,
2507 ARM_BUILTIN_WADDUSW,
2508 ARM_BUILTIN_WSUBB,
2509 ARM_BUILTIN_WSUBH,
2510 ARM_BUILTIN_WSUBW,
2511 ARM_BUILTIN_WSUBSSB,
2512 ARM_BUILTIN_WSUBSSH,
2513 ARM_BUILTIN_WSUBSSW,
2514 ARM_BUILTIN_WSUBUSB,
2515 ARM_BUILTIN_WSUBUSH,
2516 ARM_BUILTIN_WSUBUSW,
2517
2518 ARM_BUILTIN_WAND,
2519 ARM_BUILTIN_WANDN,
2520 ARM_BUILTIN_WOR,
2521 ARM_BUILTIN_WXOR,
2522
2523 ARM_BUILTIN_WCMPEQB,
2524 ARM_BUILTIN_WCMPEQH,
2525 ARM_BUILTIN_WCMPEQW,
2526 ARM_BUILTIN_WCMPGTUB,
2527 ARM_BUILTIN_WCMPGTUH,
2528 ARM_BUILTIN_WCMPGTUW,
2529 ARM_BUILTIN_WCMPGTSB,
2530 ARM_BUILTIN_WCMPGTSH,
2531 ARM_BUILTIN_WCMPGTSW,
2532
2533 ARM_BUILTIN_TEXTRMSB,
2534 ARM_BUILTIN_TEXTRMSH,
2535 ARM_BUILTIN_TEXTRMSW,
2536 ARM_BUILTIN_TEXTRMUB,
2537 ARM_BUILTIN_TEXTRMUH,
2538 ARM_BUILTIN_TEXTRMUW,
2539 ARM_BUILTIN_TINSRB,
2540 ARM_BUILTIN_TINSRH,
2541 ARM_BUILTIN_TINSRW,
2542
2543 ARM_BUILTIN_WMAXSW,
2544 ARM_BUILTIN_WMAXSH,
2545 ARM_BUILTIN_WMAXSB,
2546 ARM_BUILTIN_WMAXUW,
2547 ARM_BUILTIN_WMAXUH,
2548 ARM_BUILTIN_WMAXUB,
2549 ARM_BUILTIN_WMINSW,
2550 ARM_BUILTIN_WMINSH,
2551 ARM_BUILTIN_WMINSB,
2552 ARM_BUILTIN_WMINUW,
2553 ARM_BUILTIN_WMINUH,
2554 ARM_BUILTIN_WMINUB,
2555
f07a6b21
BE		 2556 ARM_BUILTIN_WMULUM,
2557 ARM_BUILTIN_WMULSM,
5a9335ef
NC		 2558 ARM_BUILTIN_WMULUL,
2559
2560 ARM_BUILTIN_PSADBH,
2561 ARM_BUILTIN_WSHUFH,
2562
2563 ARM_BUILTIN_WSLLH,
2564 ARM_BUILTIN_WSLLW,
2565 ARM_BUILTIN_WSLLD,
2566 ARM_BUILTIN_WSRAH,
2567 ARM_BUILTIN_WSRAW,
2568 ARM_BUILTIN_WSRAD,
2569 ARM_BUILTIN_WSRLH,
2570 ARM_BUILTIN_WSRLW,
2571 ARM_BUILTIN_WSRLD,
2572 ARM_BUILTIN_WRORH,
2573 ARM_BUILTIN_WRORW,
2574 ARM_BUILTIN_WRORD,
2575 ARM_BUILTIN_WSLLHI,
2576 ARM_BUILTIN_WSLLWI,
2577 ARM_BUILTIN_WSLLDI,
2578 ARM_BUILTIN_WSRAHI,
2579 ARM_BUILTIN_WSRAWI,
2580 ARM_BUILTIN_WSRADI,
2581 ARM_BUILTIN_WSRLHI,
2582 ARM_BUILTIN_WSRLWI,
2583 ARM_BUILTIN_WSRLDI,
2584 ARM_BUILTIN_WRORHI,
2585 ARM_BUILTIN_WRORWI,
2586 ARM_BUILTIN_WRORDI,
2587
2588 ARM_BUILTIN_WUNPCKIHB,
2589 ARM_BUILTIN_WUNPCKIHH,
2590 ARM_BUILTIN_WUNPCKIHW,
2591 ARM_BUILTIN_WUNPCKILB,
2592 ARM_BUILTIN_WUNPCKILH,
2593 ARM_BUILTIN_WUNPCKILW,
2594
2595 ARM_BUILTIN_WUNPCKEHSB,
2596 ARM_BUILTIN_WUNPCKEHSH,
2597 ARM_BUILTIN_WUNPCKEHSW,
2598 ARM_BUILTIN_WUNPCKEHUB,
2599 ARM_BUILTIN_WUNPCKEHUH,
2600 ARM_BUILTIN_WUNPCKEHUW,
2601 ARM_BUILTIN_WUNPCKELSB,
2602 ARM_BUILTIN_WUNPCKELSH,
2603 ARM_BUILTIN_WUNPCKELSW,
2604 ARM_BUILTIN_WUNPCKELUB,
2605 ARM_BUILTIN_WUNPCKELUH,
2606 ARM_BUILTIN_WUNPCKELUW,
2607
d3585b76
DJ		 2608 ARM_BUILTIN_THREAD_POINTER,
2609
88f77cba
JB		 2610 ARM_BUILTIN_NEON_BASE,
2611
2612 ARM_BUILTIN_MAX = ARM_BUILTIN_NEON_BASE /* FIXME: Wrong! */
5a9335ef 2613};
978e411f
CD		 2614
2615/* Do not emit .note.GNU-stack by default. */
2616#ifndef NEED_INDICATE_EXEC_STACK
2617#define NEED_INDICATE_EXEC_STACK 0
2618#endif
2619
93b338c3
BS		 2620/* The maximum number of parallel loads or stores we support in an ldm/stm
2621 instruction. */
2622#define MAX_LDM_STM_OPS 4
2623
88657302 2624#endif /* ! GCC_ARM_H */
Mirror of https://gcc.gnu.org/git/gcc.git