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[thirdparty/gcc.git] / gcc / config / arm / arm.h
CommitLineData
f5a1b0d2 1/* Definitions of target machine for GNU compiler, for ARM.
cf011243 2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
b12a00f1 3 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
35d965d5 4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
8b109b37 5 and Martin Simmons (@harleqn.co.uk).
949d79eb 6 More major hacks by Richard Earnshaw (rearnsha@arm.com)
6cfc7210
NC		 7 Minor hacks by Nick Clifton (nickc@cygnus.com)
8
4f448245 9 This file is part of GCC.
35d965d5 10
4f448245
NC		 11 GCC is free software; you can redistribute it and/or modify it
12 under the terms of the GNU General Public License as published
13 by the Free Software Foundation; either version 2, or (at your
14 option) any later version.
35d965d5 15
4f448245
NC		 16 GCC is distributed in the hope that it will be useful, but WITHOUT
17 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
18 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
19 License for more details.
35d965d5 20
4f448245
NC		 21 You should have received a copy of the GNU General Public License
22 along with GCC; see the file COPYING. If not, write to
39d14dda
KC		 23 the Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
24 MA 02110-1301, USA. */
35d965d5 25
88657302
RH		 26#ifndef GCC_ARM_H
27#define GCC_ARM_H
b355a481 28
35fd3193 29/* The architecture define. */
78011587
PB		 30extern char arm_arch_name[];
31
e6471be6
NB		 32/* Target CPU builtins. */
33#define TARGET_CPU_CPP_BUILTINS() \
34 do \
35 { \
9b66ebb1
PB		 36 /* Define __arm__ even when in thumb mode, for \
37 consistency with armcc. */ \
38 builtin_define ("__arm__"); \
61f0ccff 39 builtin_define ("__APCS_32__"); \
9b66ebb1 40 if (TARGET_THUMB) \
e6471be6
NB		 41 builtin_define ("__thumb__"); \
42 \
43 if (TARGET_BIG_END) \
44 { \
45 builtin_define ("__ARMEB__"); \
46 if (TARGET_THUMB) \
47 builtin_define ("__THUMBEB__"); \
48 if (TARGET_LITTLE_WORDS) \
49 builtin_define ("__ARMWEL__"); \
50 } \
51 else \
52 { \
53 builtin_define ("__ARMEL__"); \
54 if (TARGET_THUMB) \
55 builtin_define ("__THUMBEL__"); \
56 } \
57 \
e6471be6
NB		 58 if (TARGET_SOFT_FLOAT) \
59 builtin_define ("__SOFTFP__"); \
60 \
9b66ebb1 61 if (TARGET_VFP) \
b5b620a4
JT		 62 builtin_define ("__VFP_FP__"); \
63 \
e6471be6
NB		 64 /* Add a define for interworking. \
65 Needed when building libgcc.a. */ \
2ad4dcf9 66 if (arm_cpp_interwork) \
e6471be6
NB		 67 builtin_define ("__THUMB_INTERWORK__"); \
68 \
69 builtin_assert ("cpu=arm"); \
70 builtin_assert ("machine=arm"); \
78011587
PB		 71 \
72 builtin_define (arm_arch_name); \
73 if (arm_arch_cirrus) \
74 builtin_define ("__MAVERICK__"); \
75 if (arm_arch_xscale) \
76 builtin_define ("__XSCALE__"); \
77 if (arm_arch_iwmmxt) \
78 builtin_define ("__IWMMXT__"); \
4adf3e34
PB		 79 if (TARGET_AAPCS_BASED) \
80 builtin_define ("__ARM_EABI__"); \
e6471be6
NB		 81 } while (0)
82
9b66ebb1
PB		 83/* The various ARM cores. */
84enum processor_type
85{
d98a72fd
RE		 86#define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
87 IDENT,
9b66ebb1
PB		 88#include "arm-cores.def"
89#undef ARM_CORE
90 /* Used to indicate that no processor has been specified. */
91 arm_none
92};
93
78011587
PB		 94enum target_cpus
95{
d98a72fd
RE		 96#define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
97 TARGET_CPU_##IDENT,
78011587
PB		 98#include "arm-cores.def"
99#undef ARM_CORE
100 TARGET_CPU_generic
101};
102
9b66ebb1
PB		 103/* The processor for which instructions should be scheduled. */
104extern enum processor_type arm_tune;
105
d5b7b3ae 106typedef enum arm_cond_code
89c7ca52
RE		 107{
108 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC,
109 ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV
d5b7b3ae
RE		 110}
111arm_cc;
6cfc7210 112
d5b7b3ae 113extern arm_cc arm_current_cc;
ff9940b0 114
d5b7b3ae 115#define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1))
89c7ca52 116
6cfc7210
NC		 117extern int arm_target_label;
118extern int arm_ccfsm_state;
e2500fed 119extern GTY(()) rtx arm_target_insn;
d5b7b3ae 120/* Define the information needed to generate branch insns. This is
e2500fed
GK		 121 stored from the compare operation. */
122extern GTY(()) rtx arm_compare_op0;
123extern GTY(()) rtx arm_compare_op1;
d5b7b3ae 124/* The label of the current constant pool. */
e2500fed 125extern rtx pool_vector_label;
d5b7b3ae 126/* Set to 1 when a return insn is output, this means that the epilogue
d6b4baa4 127 is not needed. */
d5b7b3ae 128extern int return_used_this_function;
e2500fed
GK		 129/* Used to produce AOF syntax assembler. */
130extern GTY(()) rtx aof_pic_label;
35d965d5 131\f
d6b4baa4 132/* Just in case configure has failed to define anything. */
7a801826
RE		 133#ifndef TARGET_CPU_DEFAULT
134#define TARGET_CPU_DEFAULT TARGET_CPU_generic
135#endif
136
7a801826 137
5742588d 138#undef CPP_SPEC
78011587 139#define CPP_SPEC "%(subtarget_cpp_spec) \
e6471be6
NB		 140%{msoft-float:%{mhard-float: \
141 %e-msoft-float and -mhard_float may not be used together}} \
142%{mbig-endian:%{mlittle-endian: \
143 %e-mbig-endian and -mlittle-endian may not be used together}}"
7a801826 144
be393ecf 145#ifndef CC1_SPEC
dfa08768 146#define CC1_SPEC ""
be393ecf 147#endif
7a801826
RE		 148
149/* This macro defines names of additional specifications to put in the specs
150 that can be used in various specifications like CC1_SPEC. Its definition
151 is an initializer with a subgrouping for each command option.
152
153 Each subgrouping contains a string constant, that defines the
4f448245 154 specification name, and a string constant that used by the GCC driver
7a801826
RE		 155 program.
156
157 Do not define this macro if it does not need to do anything. */
158#define EXTRA_SPECS \
38fc909b 159 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
7a801826
RE		 160 SUBTARGET_EXTRA_SPECS
161
914a3b8c 162#ifndef SUBTARGET_EXTRA_SPECS
7a801826 163#define SUBTARGET_EXTRA_SPECS
914a3b8c
DM		 164#endif
165
6cfc7210 166#ifndef SUBTARGET_CPP_SPEC
38fc909b 167#define SUBTARGET_CPP_SPEC ""
6cfc7210 168#endif
35d965d5
RS		 169\f
170/* Run-time Target Specification. */
ff9940b0 171#ifndef TARGET_VERSION
6cfc7210 172#define TARGET_VERSION fputs (" (ARM/generic)", stderr);
ff9940b0 173#endif
35d965d5 174
9b66ebb1 175#define TARGET_SOFT_FLOAT (arm_float_abi == ARM_FLOAT_ABI_SOFT)
72cdc543
PB		 176/* Use hardware floating point instructions. */
177#define TARGET_HARD_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT)
178/* Use hardware floating point calling convention. */
179#define TARGET_HARD_FLOAT_ABI (arm_float_abi == ARM_FLOAT_ABI_HARD)
9b66ebb1
PB		 180#define TARGET_FPA (arm_fp_model == ARM_FP_MODEL_FPA)
181#define TARGET_MAVERICK (arm_fp_model == ARM_FP_MODEL_MAVERICK)
182#define TARGET_VFP (arm_fp_model == ARM_FP_MODEL_VFP)
5a9335ef
NC		 183#define TARGET_IWMMXT (arm_arch_iwmmxt)
184#define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_ARM)
5848830f 185#define TARGET_IWMMXT_ABI (TARGET_ARM && arm_abi == ARM_ABI_IWMMXT)
d5b7b3ae
RE		 186#define TARGET_ARM (! TARGET_THUMB)
187#define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */
c54c7322
RS		 188#define TARGET_BACKTRACE (leaf_function_p () \
189 ? TARGET_TPCS_LEAF_FRAME \
190 : TARGET_TPCS_FRAME)
fdd695fd 191#define TARGET_LDRD (arm_arch5e && ARM_DOUBLEWORD_ALIGN)
b6685939
PB		 192#define TARGET_AAPCS_BASED \
193 (arm_abi != ARM_ABI_APCS && arm_abi != ARM_ABI_ATPCS)
3ada8e17 194
b3f8d95d
MM		 195/* True iff the full BPABI is being used. If TARGET_BPABI is true,
196 then TARGET_AAPCS_BASED must be true -- but the converse does not
197 hold. TARGET_BPABI implies the use of the BPABI runtime library,
198 etc., in addition to just the AAPCS calling conventions. */
199#ifndef TARGET_BPABI
200#define TARGET_BPABI false
f676971a 201#endif
b3f8d95d 202
7816bea0
DJ		 203/* Support for a compile-time default CPU, et cetera. The rules are:
204 --with-arch is ignored if -march or -mcpu are specified.
205 --with-cpu is ignored if -march or -mcpu are specified, and is overridden
206 by --with-arch.
207 --with-tune is ignored if -mtune or -mcpu are specified (but not affected
208 by -march).
9b66ebb1
PB		 209 --with-float is ignored if -mhard-float, -msoft-float or -mfloat-abi are
210 specified.
5848830f
PB		 211 --with-fpu is ignored if -mfpu is specified.
212 --with-abi is ignored is -mabi is specified. */
7816bea0
DJ		 213#define OPTION_DEFAULT_SPECS \
214 {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \
215 {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \
216 {"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}" }, \
9b66ebb1
PB		 217 {"float", \
218 "%{!msoft-float:%{!mhard-float:%{!mfloat-abi=*:-mfloat-abi=%(VALUE)}}}" }, \
5848830f
PB		 219 {"fpu", "%{!mfpu=*:-mfpu=%(VALUE)}"}, \
220 {"abi", "%{!mabi=*:-mabi=%(VALUE)}"},
7816bea0 221
9b66ebb1
PB		 222/* Which floating point model to use. */
223enum arm_fp_model
224{
225 ARM_FP_MODEL_UNKNOWN,
226 /* FPA model (Hardware or software). */
227 ARM_FP_MODEL_FPA,
228 /* Cirrus Maverick floating point model. */
229 ARM_FP_MODEL_MAVERICK,
230 /* VFP floating point model. */
231 ARM_FP_MODEL_VFP
232};
233
234extern enum arm_fp_model arm_fp_model;
235
236/* Which floating point hardware is available. Also update
237 fp_model_for_fpu in arm.c when adding entries to this list. */
29ad9694 238enum fputype
24f0c1b4 239{
9b66ebb1
PB		 240 /* No FP hardware. */
241 FPUTYPE_NONE,
29ad9694
RE		 242 /* Full FPA support. */
243 FPUTYPE_FPA,
244 /* Emulated FPA hardware, Issue 2 emulator (no LFM/SFM). */
245 FPUTYPE_FPA_EMU2,
246 /* Emulated FPA hardware, Issue 3 emulator. */
247 FPUTYPE_FPA_EMU3,
248 /* Cirrus Maverick floating point co-processor. */
9b66ebb1
PB		 249 FPUTYPE_MAVERICK,
250 /* VFP. */
251 FPUTYPE_VFP
24f0c1b4
RE		 252};
253
254/* Recast the floating point class to be the floating point attribute. */
29ad9694 255#define arm_fpu_attr ((enum attr_fpu) arm_fpu_tune)
24f0c1b4 256
71791e16 257/* What type of floating point to tune for */
29ad9694 258extern enum fputype arm_fpu_tune;
24f0c1b4 259
71791e16 260/* What type of floating point instructions are available */
29ad9694 261extern enum fputype arm_fpu_arch;
71791e16 262
9b66ebb1
PB		 263enum float_abi_type
264{
265 ARM_FLOAT_ABI_SOFT,
266 ARM_FLOAT_ABI_SOFTFP,
267 ARM_FLOAT_ABI_HARD
268};
269
270extern enum float_abi_type arm_float_abi;
271
3d8532aa
PB		 272#ifndef TARGET_DEFAULT_FLOAT_ABI
273#define TARGET_DEFAULT_FLOAT_ABI ARM_FLOAT_ABI_SOFT
274#endif
275
5848830f
PB		 276/* Which ABI to use. */
277enum arm_abi_type
278{
279 ARM_ABI_APCS,
280 ARM_ABI_ATPCS,
281 ARM_ABI_AAPCS,
282 ARM_ABI_IWMMXT
283};
284
285extern enum arm_abi_type arm_abi;
286
287#ifndef ARM_DEFAULT_ABI
288#define ARM_DEFAULT_ABI ARM_ABI_APCS
289#endif
290
9b66ebb1
PB		 291/* Nonzero if this chip supports the ARM Architecture 3M extensions. */
292extern int arm_arch3m;
11c1a207 293
9b66ebb1 294/* Nonzero if this chip supports the ARM Architecture 4 extensions. */
11c1a207
RE		 295extern int arm_arch4;
296
68d560d4
RE		 297/* Nonzero if this chip supports the ARM Architecture 4T extensions. */
298extern int arm_arch4t;
299
9b66ebb1 300/* Nonzero if this chip supports the ARM Architecture 5 extensions. */
62b10bbc
NC		 301extern int arm_arch5;
302
9b66ebb1 303/* Nonzero if this chip supports the ARM Architecture 5E extensions. */
b15bca31
RE		 304extern int arm_arch5e;
305
9b66ebb1
PB		 306/* Nonzero if this chip supports the ARM Architecture 6 extensions. */
307extern int arm_arch6;
308
f5a1b0d2
NC		 309/* Nonzero if this chip can benefit from load scheduling. */
310extern int arm_ld_sched;
311
0616531f
RE		 312/* Nonzero if generating thumb code. */
313extern int thumb_code;
314
f5a1b0d2 315/* Nonzero if this chip is a StrongARM. */
abac3b49 316extern int arm_tune_strongarm;
f5a1b0d2 317
9b6b54e2 318/* Nonzero if this chip is a Cirrus variant. */
78011587 319extern int arm_arch_cirrus;
9b6b54e2 320
5a9335ef
NC		 321/* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */
322extern int arm_arch_iwmmxt;
323
d19fb8e3 324/* Nonzero if this chip is an XScale. */
4b3c2e48
PB		 325extern int arm_arch_xscale;
326
abac3b49 327/* Nonzero if tuning for XScale. */
4b3c2e48 328extern int arm_tune_xscale;
d19fb8e3 329
abac3b49
RE		 330/* Nonzero if tuning for stores via the write buffer. */
331extern int arm_tune_wbuf;
f5a1b0d2 332
2ad4dcf9 333/* Nonzero if we should define __THUMB_INTERWORK__ in the
f676971a 334 preprocessor.
2ad4dcf9
RE		 335 XXX This is a bit of a hack, it's intended to help work around
336 problems in GLD which doesn't understand that armv5t code is
337 interworking clean. */
338extern int arm_cpp_interwork;
339
2ce9c1b9 340#ifndef TARGET_DEFAULT
c54c7322 341#define TARGET_DEFAULT (MASK_APCS_FRAME)
2ce9c1b9 342#endif
35d965d5 343
11c1a207
RE		 344/* The frame pointer register used in gcc has nothing to do with debugging;
345 that is controlled by the APCS-FRAME option. */
d5b7b3ae 346#define CAN_DEBUG_WITHOUT_FP
35d965d5 347
11c1a207 348#define OVERRIDE_OPTIONS arm_override_options ()
86efdc8e
PB		 349
350/* Nonzero if PIC code requires explicit qualifiers to generate
351 PLT and GOT relocs rather than the assembler doing so implicitly.
ed0e6530
PB		 352 Subtargets can override these if required. */
353#ifndef NEED_GOT_RELOC
354#define NEED_GOT_RELOC 0
355#endif
356#ifndef NEED_PLT_RELOC
357#define NEED_PLT_RELOC 0
e2723c62 358#endif
84306176
PB		 359
360/* Nonzero if we need to refer to the GOT with a PC-relative
361 offset. In other words, generate
362
f676971a 363 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)]
84306176
PB		 364
365 rather than
366
367 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8)
368
f676971a 369 The default is true, which matches NetBSD. Subtargets can
84306176
PB		 370 override this if required. */
371#ifndef GOT_PCREL
372#define GOT_PCREL 1
373#endif
35d965d5
RS		 374\f
375/* Target machine storage Layout. */
376
ff9940b0
RE		 377
378/* Define this macro if it is advisable to hold scalars in registers
379 in a wider mode than that declared by the program. In such cases,
380 the value is constrained to be within the bounds of the declared
381 type, but kept valid in the wider mode. The signedness of the
382 extension may differ from that of the type. */
383
384/* It is far faster to zero extend chars than to sign extend them */
385
6cfc7210 386#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
2ce9c1b9
RE		 387 if (GET_MODE_CLASS (MODE) == MODE_INT \
388 && GET_MODE_SIZE (MODE) < 4) \
389 { \
390 if (MODE == QImode) \
391 UNSIGNEDP = 1; \
392 else if (MODE == HImode) \
61f0ccff 393 UNSIGNEDP = 1; \
2ce9c1b9 394 (MODE) = SImode; \
ff9940b0
RE		 395 }
396
d4453b7a 397#define PROMOTE_FUNCTION_MODE(MODE, UNSIGNEDP, TYPE) \
866af8a9
JB		 398 if ((GET_MODE_CLASS (MODE) == MODE_INT \
399 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_INT) \
400 && GET_MODE_SIZE (MODE) < 4) \
401 (MODE) = SImode; \
d4453b7a 402
35d965d5
RS		 403/* Define this if most significant bit is lowest numbered
404 in instructions that operate on numbered bit-fields. */
405#define BITS_BIG_ENDIAN 0
406
f676971a 407/* Define this if most significant byte of a word is the lowest numbered.
3ada8e17
DE		 408 Most ARM processors are run in little endian mode, so that is the default.
409 If you want to have it run-time selectable, change the definition in a
410 cover file to be TARGET_BIG_ENDIAN. */
11c1a207 411#define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
35d965d5
RS		 412
413/* Define this if most significant word of a multiword number is the lowest
11c1a207
RE		 414 numbered.
415 This is always false, even when in big-endian mode. */
ddee6aba
RE		 416#define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS)
417
418/* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based
419 on processor pre-defineds when compiling libgcc2.c. */
420#if defined(__ARMEB__) && !defined(__ARMWEL__)
421#define LIBGCC2_WORDS_BIG_ENDIAN 1
422#else
423#define LIBGCC2_WORDS_BIG_ENDIAN 0
424#endif
35d965d5 425
11c1a207 426/* Define this if most significant word of doubles is the lowest numbered.
f0375c66
NC		 427 The rules are different based on whether or not we use FPA-format,
428 VFP-format or some other floating point co-processor's format doubles. */
b5b620a4 429#define FLOAT_WORDS_BIG_ENDIAN (arm_float_words_big_endian ())
7fc6c9f0 430
35d965d5
RS		 431#define UNITS_PER_WORD 4
432
5848830f 433/* True if natural alignment is used for doubleword types. */
b6685939
PB		 434#define ARM_DOUBLEWORD_ALIGN TARGET_AAPCS_BASED
435
5848830f 436#define DOUBLEWORD_ALIGNMENT 64
35d965d5 437
5848830f 438#define PARM_BOUNDARY 32
5a9335ef 439
5848830f 440#define STACK_BOUNDARY (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
35d965d5 441
5848830f
PB		 442#define PREFERRED_STACK_BOUNDARY \
443 (arm_abi == ARM_ABI_ATPCS ? 64 : STACK_BOUNDARY)
0977774b 444
35d965d5
RS		 445#define FUNCTION_BOUNDARY 32
446
92928d71
AO		 447/* The lowest bit is used to indicate Thumb-mode functions, so the
448 vbit must go into the delta field of pointers to member
449 functions. */
450#define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
451
35d965d5
RS		 452#define EMPTY_FIELD_BOUNDARY 32
453
5848830f 454#define BIGGEST_ALIGNMENT (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
5a9335ef 455
27847754
NC		 456/* XXX Blah -- this macro is used directly by libobjc. Since it
457 supports no vector modes, cut out the complexity and fall back
458 on BIGGEST_FIELD_ALIGNMENT. */
459#ifdef IN_TARGET_LIBS
8fca31a2 460#define BIGGEST_FIELD_ALIGNMENT 64
27847754 461#endif
5a9335ef 462
ff9940b0 463/* Make strings word-aligned so strcpy from constants will be faster. */
591af218 464#define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_tune_xscale ? 1 : 2)
f676971a 465
d19fb8e3 466#define CONSTANT_ALIGNMENT(EXP, ALIGN) \
5848830f
PB		 467 ((TREE_CODE (EXP) == STRING_CST \
468 && (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \
469 ? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN))
ff9940b0 470
723ae7c1
NC		 471/* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the
472 value set in previous versions of this toolchain was 8, which produces more
473 compact structures. The command line option -mstructure_size_boundary=<n>
f710504c 474 can be used to change this value. For compatibility with the ARM SDK
723ae7c1 475 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI
5848830f
PB		 476 0020D) page 2-20 says "Structures are aligned on word boundaries".
477 The AAPCS specifies a value of 8. */
6ead9ba5
NC		 478#define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary
479extern int arm_structure_size_boundary;
723ae7c1 480
4912a07c 481/* This is the value used to initialize arm_structure_size_boundary. If a
723ae7c1 482 particular arm target wants to change the default value it should change
6bc82793 483 the definition of this macro, not STRUCTURE_SIZE_BOUNDARY. See netbsd.h
723ae7c1
NC		 484 for an example of this. */
485#ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY
486#define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32
b355a481 487#endif
2a5307b1 488
825dda42 489/* Nonzero if move instructions will actually fail to work
ff9940b0 490 when given unaligned data. */
35d965d5 491#define STRICT_ALIGNMENT 1
b6685939
PB		 492
493/* wchar_t is unsigned under the AAPCS. */
494#ifndef WCHAR_TYPE
495#define WCHAR_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "int")
496
497#define WCHAR_TYPE_SIZE BITS_PER_WORD
498#endif
499
500#ifndef SIZE_TYPE
501#define SIZE_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "long unsigned int")
502#endif
d81d0bdd
PB		 503
504/* AAPCS requires that structure alignment is affected by bitfields. */
505#ifndef PCC_BITFIELD_TYPE_MATTERS
506#define PCC_BITFIELD_TYPE_MATTERS TARGET_AAPCS_BASED
507#endif
508
35d965d5
RS		 509\f
510/* Standard register usage. */
511
512/* Register allocation in ARM Procedure Call Standard (as used on RISCiX):
513 (S - saved over call).
514
515 r0 * argument word/integer result
516 r1-r3 argument word
517
518 r4-r8 S register variable
519 r9 S (rfp) register variable (real frame pointer)
f676971a 520
f5a1b0d2 521 r10 F S (sl) stack limit (used by -mapcs-stack-check)
35d965d5
RS		 522 r11 F S (fp) argument pointer
523 r12 (ip) temp workspace
524 r13 F S (sp) lower end of current stack frame
525 r14 (lr) link address/workspace
526 r15 F (pc) program counter
527
528 f0 floating point result
529 f1-f3 floating point scratch
530
531 f4-f7 S floating point variable
532
ff9940b0
RE		 533 cc This is NOT a real register, but is used internally
534 to represent things that use or set the condition
535 codes.
536 sfp This isn't either. It is used during rtl generation
537 since the offset between the frame pointer and the
538 auto's isn't known until after register allocation.
539 afp Nor this, we only need this because of non-local
540 goto. Without it fp appears to be used and the
541 elimination code won't get rid of sfp. It tracks
542 fp exactly at all times.
543
35d965d5
RS		 544 *: See CONDITIONAL_REGISTER_USAGE */
545
9b6b54e2
NC		 546/*
547 mvf0 Cirrus floating point result
548 mvf1-mvf3 Cirrus floating point scratch
549 mvf4-mvf15 S Cirrus floating point variable. */
550
9b66ebb1
PB		 551/* s0-s15 VFP scratch (aka d0-d7).
552 s16-s31 S VFP variable (aka d8-d15).
553 vfpcc Not a real register. Represents the VFP condition
554 code flags. */
555
ff9940b0
RE		 556/* The stack backtrace structure is as follows:
557 fp points to here: | save code pointer | [fp]
558 | return link value | [fp, #-4]
559 | return sp value | [fp, #-8]
560 | return fp value | [fp, #-12]
561 [| saved r10 value |]
562 [| saved r9 value |]
563 [| saved r8 value |]
564 [| saved r7 value |]
565 [| saved r6 value |]
566 [| saved r5 value |]
567 [| saved r4 value |]
568 [| saved r3 value |]
569 [| saved r2 value |]
570 [| saved r1 value |]
571 [| saved r0 value |]
572 [| saved f7 value |] three words
573 [| saved f6 value |] three words
574 [| saved f5 value |] three words
575 [| saved f4 value |] three words
576 r0-r3 are not normally saved in a C function. */
577
35d965d5
RS		 578/* 1 for registers that have pervasive standard uses
579 and are not available for the register allocator. */
9b66ebb1
PB		 580#define FIXED_REGISTERS \
581{ \
582 0,0,0,0,0,0,0,0, \
583 0,0,0,0,0,1,0,1, \
584 0,0,0,0,0,0,0,0, \
9b6b54e2
NC		 585 1,1,1, \
586 1,1,1,1,1,1,1,1, \
9b66ebb1
PB		 587 1,1,1,1,1,1,1,1, \
588 1,1,1,1,1,1,1,1, \
589 1,1,1,1,1,1,1,1, \
590 1,1,1,1, \
591 1,1,1,1,1,1,1,1, \
592 1,1,1,1,1,1,1,1, \
593 1,1,1,1,1,1,1,1, \
594 1,1,1,1,1,1,1,1, \
595 1 \
35d965d5
RS		 596}
597
598/* 1 for registers not available across function calls.
599 These must include the FIXED_REGISTERS and also any
600 registers that can be used without being saved.
601 The latter must include the registers where values are returned
602 and the register where structure-value addresses are passed.
ff9940b0 603 Aside from that, you can include as many other registers as you like.
f676971a 604 The CC is not preserved over function calls on the ARM 6, so it is
d6b4baa4 605 easier to assume this for all. SFP is preserved, since FP is. */
35d965d5
RS		 606#define CALL_USED_REGISTERS \
607{ \
608 1,1,1,1,0,0,0,0, \
d5b7b3ae 609 0,0,0,0,1,1,1,1, \
ff9940b0 610 1,1,1,1,0,0,0,0, \
9b6b54e2
NC		 611 1,1,1, \
612 1,1,1,1,1,1,1,1, \
5a9335ef
NC		 613 1,1,1,1,1,1,1,1, \
614 1,1,1,1,1,1,1,1, \
615 1,1,1,1,1,1,1,1, \
9b66ebb1
PB		 616 1,1,1,1, \
617 1,1,1,1,1,1,1,1, \
618 1,1,1,1,1,1,1,1, \
619 1,1,1,1,1,1,1,1, \
620 1,1,1,1,1,1,1,1, \
621 1 \
35d965d5
RS		 622}
623
6cc8c0b3
NC		 624#ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE
625#define SUBTARGET_CONDITIONAL_REGISTER_USAGE
626#endif
627
d5b7b3ae
RE		 628#define CONDITIONAL_REGISTER_USAGE \
629{ \
4b02997f
NC		 630 int regno; \
631 \
9b66ebb1 632 if (TARGET_SOFT_FLOAT || TARGET_THUMB || !TARGET_FPA) \
d5b7b3ae 633 { \
9b66ebb1
PB		 634 for (regno = FIRST_FPA_REGNUM; \
635 regno <= LAST_FPA_REGNUM; ++regno) \
d5b7b3ae
RE		 636 fixed_regs[regno] = call_used_regs[regno] = 1; \
637 } \
9b6b54e2 638 \
c769a35d
RE		 639 if (TARGET_THUMB && optimize_size) \
640 { \
641 /* When optimizing for size, it's better not to use \
642 the HI regs, because of the overhead of stacking \
d6b4baa4 643 them. */ \
c769a35d
RE		 644 for (regno = FIRST_HI_REGNUM; \
645 regno <= LAST_HI_REGNUM; ++regno) \
646 fixed_regs[regno] = call_used_regs[regno] = 1; \
647 } \
648 \
fb14bc89
RE		 649 /* The link register can be clobbered by any branch insn, \
650 but we have no way to track that at present, so mark \
651 it as unavailable. */ \
652 if (TARGET_THUMB) \
653 fixed_regs[LR_REGNUM] = call_used_regs[LR_REGNUM] = 1; \
654 \
9b66ebb1 655 if (TARGET_ARM && TARGET_HARD_FLOAT) \
9b6b54e2 656 { \
9b66ebb1 657 if (TARGET_MAVERICK) \
9b6b54e2 658 { \
9b66ebb1
PB		 659 for (regno = FIRST_FPA_REGNUM; \
660 regno <= LAST_FPA_REGNUM; ++ regno) \
661 fixed_regs[regno] = call_used_regs[regno] = 1; \
662 for (regno = FIRST_CIRRUS_FP_REGNUM; \
663 regno <= LAST_CIRRUS_FP_REGNUM; ++ regno) \
664 { \
665 fixed_regs[regno] = 0; \
666 call_used_regs[regno] = regno < FIRST_CIRRUS_FP_REGNUM + 4; \
667 } \
668 } \
669 if (TARGET_VFP) \
670 { \
671 for (regno = FIRST_VFP_REGNUM; \
672 regno <= LAST_VFP_REGNUM; ++ regno) \
673 { \
674 fixed_regs[regno] = 0; \
675 call_used_regs[regno] = regno < FIRST_VFP_REGNUM + 16; \
676 } \
9b6b54e2
NC		 677 } \
678 } \
679 \
5a9335ef
NC		 680 if (TARGET_REALLY_IWMMXT) \
681 { \
682 regno = FIRST_IWMMXT_GR_REGNUM; \
683 /* The 2002/10/09 revision of the XScale ABI has wCG0 \
684 and wCG1 as call-preserved registers. The 2002/11/21 \
685 revision changed this so that all wCG registers are \
686 scratch registers. */ \
687 for (regno = FIRST_IWMMXT_GR_REGNUM; \
688 regno <= LAST_IWMMXT_GR_REGNUM; ++ regno) \
119bb233 689 fixed_regs[regno] = 0; \
5a9335ef
NC		 690 /* The XScale ABI has wR0 - wR9 as scratch registers, \
691 the rest as call-preserved registers. */ \
692 for (regno = FIRST_IWMMXT_REGNUM; \
693 regno <= LAST_IWMMXT_REGNUM; ++ regno) \
694 { \
695 fixed_regs[regno] = 0; \
696 call_used_regs[regno] = regno < FIRST_IWMMXT_REGNUM + 10; \
697 } \
698 } \
699 \
fc555370 700 if ((unsigned) PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
d5b7b3ae
RE		 701 { \
702 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
703 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
704 } \
705 else if (TARGET_APCS_STACK) \
706 { \
707 fixed_regs[10] = 1; \
708 call_used_regs[10] = 1; \
709 } \
a2503645
RS		 710 /* -mcaller-super-interworking reserves r11 for calls to \
711 _interwork_r11_call_via_rN(). Making the register global \
712 is an easy way of ensuring that it remains valid for all \
713 calls. */ \
685c9c11 714 if (TARGET_APCS_FRAME || TARGET_CALLER_INTERWORKING \
c54c7322 715 || TARGET_TPCS_FRAME || TARGET_TPCS_LEAF_FRAME) \
d5b7b3ae
RE		 716 { \
717 fixed_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
718 call_used_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
a2503645
RS		 719 if (TARGET_CALLER_INTERWORKING) \
720 global_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
d5b7b3ae
RE		 721 } \
722 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
35d965d5 723}
f676971a 724
6bc82793 725/* These are a couple of extensions to the formats accepted
dd18ae56
NC		 726 by asm_fprintf:
727 %@ prints out ASM_COMMENT_START
728 %r prints out REGISTER_PREFIX reg_names[arg] */
729#define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \
730 case '@': \
731 fputs (ASM_COMMENT_START, FILE); \
732 break; \
733 \
734 case 'r': \
735 fputs (REGISTER_PREFIX, FILE); \
736 fputs (reg_names [va_arg (ARGS, int)], FILE); \
737 break;
738
d5b7b3ae 739/* Round X up to the nearest word. */
0c2ca901 740#define ROUND_UP_WORD(X) (((X) + 3) & ~3)
d5b7b3ae 741
6cfc7210 742/* Convert fron bytes to ints. */
e9d7b180 743#define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
6cfc7210 744
9b66ebb1
PB		 745/* The number of (integer) registers required to hold a quantity of type MODE.
746 Also used for VFP registers. */
e9d7b180
JD		 747#define ARM_NUM_REGS(MODE) \
748 ARM_NUM_INTS (GET_MODE_SIZE (MODE))
6cfc7210
NC		 749
750/* The number of (integer) registers required to hold a quantity of TYPE MODE. */
e9d7b180
JD		 751#define ARM_NUM_REGS2(MODE, TYPE) \
752 ARM_NUM_INTS ((MODE) == BLKmode ? \
d5b7b3ae 753 int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE))
6cfc7210
NC		 754
755/* The number of (integer) argument register available. */
d5b7b3ae 756#define NUM_ARG_REGS 4
6cfc7210 757
093354e0 758/* Return the register number of the N'th (integer) argument. */
d5b7b3ae 759#define ARG_REGISTER(N) (N - 1)
6cfc7210 760
d5b7b3ae
RE		 761/* Specify the registers used for certain standard purposes.
762 The values of these macros are register numbers. */
35d965d5 763
d5b7b3ae
RE		 764/* The number of the last argument register. */
765#define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS)
35d965d5 766
c769a35d
RE		 767/* The numbers of the Thumb register ranges. */
768#define FIRST_LO_REGNUM 0
6d3d9133 769#define LAST_LO_REGNUM 7
c769a35d
RE		 770#define FIRST_HI_REGNUM 8
771#define LAST_HI_REGNUM 11
6d3d9133 772
617a1b71 773#ifndef TARGET_UNWIND_INFO
c9ca9b88
PB		 774/* We use sjlj exceptions for backwards compatibility. */
775#define MUST_USE_SJLJ_EXCEPTIONS 1
617a1b71
PB		 776#endif
777
c9ca9b88
PB		 778/* We can generate DWARF2 Unwind info, even though we don't use it. */
779#define DWARF2_UNWIND_INFO 1
f676971a 780
c9ca9b88
PB		 781/* Use r0 and r1 to pass exception handling information. */
782#define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? N : INVALID_REGNUM)
783
6d3d9133 784/* The register that holds the return address in exception handlers. */
c9ca9b88
PB		 785#define ARM_EH_STACKADJ_REGNUM 2
786#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (SImode, ARM_EH_STACKADJ_REGNUM)
35d965d5 787
d5b7b3ae
RE		 788/* The native (Norcroft) Pascal compiler for the ARM passes the static chain
789 as an invisible last argument (possible since varargs don't exist in
790 Pascal), so the following is not true. */
68dfd979 791#define STATIC_CHAIN_REGNUM (TARGET_ARM ? 12 : 9)
35d965d5 792
d5b7b3ae
RE		 793/* Define this to be where the real frame pointer is if it is not possible to
794 work out the offset between the frame pointer and the automatic variables
795 until after register allocation has taken place. FRAME_POINTER_REGNUM
796 should point to a special register that we will make sure is eliminated.
797
798 For the Thumb we have another problem. The TPCS defines the frame pointer
6bc82793 799 as r11, and GCC believes that it is always possible to use the frame pointer
d5b7b3ae
RE		 800 as base register for addressing purposes. (See comments in
801 find_reloads_address()). But - the Thumb does not allow high registers,
802 including r11, to be used as base address registers. Hence our problem.
803
804 The solution used here, and in the old thumb port is to use r7 instead of
805 r11 as the hard frame pointer and to have special code to generate
806 backtrace structures on the stack (if required to do so via a command line
6bc82793 807 option) using r11. This is the only 'user visible' use of r11 as a frame
d5b7b3ae
RE		 808 pointer. */
809#define ARM_HARD_FRAME_POINTER_REGNUM 11
810#define THUMB_HARD_FRAME_POINTER_REGNUM 7
35d965d5 811
b15bca31
RE		 812#define HARD_FRAME_POINTER_REGNUM \
813 (TARGET_ARM \
814 ? ARM_HARD_FRAME_POINTER_REGNUM \
815 : THUMB_HARD_FRAME_POINTER_REGNUM)
d5b7b3ae 816
b15bca31 817#define FP_REGNUM HARD_FRAME_POINTER_REGNUM
d5b7b3ae 818
b15bca31
RE		 819/* Register to use for pushing function arguments. */
820#define STACK_POINTER_REGNUM SP_REGNUM
d5b7b3ae
RE		 821
822/* ARM floating pointer registers. */
9b66ebb1
PB		 823#define FIRST_FPA_REGNUM 16
824#define LAST_FPA_REGNUM 23
2fa330b2
PB		 825#define IS_FPA_REGNUM(REGNUM) \
826 (((REGNUM) >= FIRST_FPA_REGNUM) && ((REGNUM) <= LAST_FPA_REGNUM))
d5b7b3ae 827
5a9335ef
NC		 828#define FIRST_IWMMXT_GR_REGNUM 43
829#define LAST_IWMMXT_GR_REGNUM 46
830#define FIRST_IWMMXT_REGNUM 47
831#define LAST_IWMMXT_REGNUM 62
832#define IS_IWMMXT_REGNUM(REGNUM) \
833 (((REGNUM) >= FIRST_IWMMXT_REGNUM) && ((REGNUM) <= LAST_IWMMXT_REGNUM))
834#define IS_IWMMXT_GR_REGNUM(REGNUM) \
835 (((REGNUM) >= FIRST_IWMMXT_GR_REGNUM) && ((REGNUM) <= LAST_IWMMXT_GR_REGNUM))
836
35d965d5 837/* Base register for access to local variables of the function. */
ff9940b0
RE		 838#define FRAME_POINTER_REGNUM 25
839
d5b7b3ae
RE		 840/* Base register for access to arguments of the function. */
841#define ARG_POINTER_REGNUM 26
62b10bbc 842
9b6b54e2
NC		 843#define FIRST_CIRRUS_FP_REGNUM 27
844#define LAST_CIRRUS_FP_REGNUM 42
845#define IS_CIRRUS_REGNUM(REGNUM) \
846 (((REGNUM) >= FIRST_CIRRUS_FP_REGNUM) && ((REGNUM) <= LAST_CIRRUS_FP_REGNUM))
847
9b66ebb1
PB		 848#define FIRST_VFP_REGNUM 63
849#define LAST_VFP_REGNUM 94
850#define IS_VFP_REGNUM(REGNUM) \
851 (((REGNUM) >= FIRST_VFP_REGNUM) && ((REGNUM) <= LAST_VFP_REGNUM))
852
6f8c9bd1
NC		 853/* The number of hard registers is 16 ARM + 8 FPA + 1 CC + 1 SFP + 1 AFP. */
854/* + 16 Cirrus registers take us up to 43. */
5a9335ef 855/* Intel Wireless MMX Technology registers add 16 + 4 more. */
9b66ebb1
PB		 856/* VFP adds 32 + 1 more. */
857#define FIRST_PSEUDO_REGISTER 96
62b10bbc 858
2fa330b2
PB		 859#define DBX_REGISTER_NUMBER(REGNO) arm_dbx_register_number (REGNO)
860
35d965d5
RS		 861/* Value should be nonzero if functions must have frame pointers.
862 Zero means the frame pointer need not be set up (and parms may be accessed
f676971a 863 via the stack pointer) in functions that seem suitable.
ff9940b0
RE		 864 If we have to have a frame pointer we might as well make use of it.
865 APCS says that the frame pointer does not need to be pushed in leaf
2a5307b1 866 functions, or simple tail call functions. */
a15900b5
DJ		 867
868#ifndef SUBTARGET_FRAME_POINTER_REQUIRED
869#define SUBTARGET_FRAME_POINTER_REQUIRED 0
870#endif
871
7b8b8ade
NC		 872#define FRAME_POINTER_REQUIRED \
873 (current_function_has_nonlocal_label \
a15900b5 874 || SUBTARGET_FRAME_POINTER_REQUIRED \
d5b7b3ae 875 || (TARGET_ARM && TARGET_APCS_FRAME && ! leaf_function_p ()))
35d965d5 876
d5b7b3ae
RE		 877/* Return number of consecutive hard regs needed starting at reg REGNO
878 to hold something of mode MODE.
879 This is ordinarily the length in words of a value of mode MODE
880 but can be less for certain modes in special long registers.
35d965d5 881
3b684012 882 On the ARM regs are UNITS_PER_WORD bits wide; FPA regs can hold any FP
d5b7b3ae
RE		 883 mode. */
884#define HARD_REGNO_NREGS(REGNO, MODE) \
885 ((TARGET_ARM \
9b66ebb1 886 && REGNO >= FIRST_FPA_REGNUM \
d5b7b3ae
RE		 887 && REGNO != FRAME_POINTER_REGNUM \
888 && REGNO != ARG_POINTER_REGNUM) \
9b66ebb1 889 && !IS_VFP_REGNUM (REGNO) \
e9d7b180 890 ? 1 : ARM_NUM_REGS (MODE))
35d965d5 891
4b02997f 892/* Return true if REGNO is suitable for holding a quantity of type MODE. */
d5b7b3ae 893#define HARD_REGNO_MODE_OK(REGNO, MODE) \
4b02997f 894 arm_hard_regno_mode_ok ((REGNO), (MODE))
35d965d5 895
d5b7b3ae
RE		 896/* Value is 1 if it is a good idea to tie two pseudo registers
897 when one has mode MODE1 and one has mode MODE2.
898 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
899 for any hard reg, then this must be 0 for correct output. */
900#define MODES_TIEABLE_P(MODE1, MODE2) \
901 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
ff9940b0 902
5a9335ef 903#define VALID_IWMMXT_REG_MODE(MODE) \
f676971a 904 (arm_vector_mode_supported_p (MODE) || (MODE) == DImode)
5a9335ef 905
35d965d5 906/* The order in which register should be allocated. It is good to use ip
ff9940b0
RE		 907 since no saving is required (though calls clobber it) and it never contains
908 function parameters. It is quite good to use lr since other calls may
f676971a 909 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is
ff9940b0 910 least likely to contain a function parameter; in addition results are
d5b7b3ae 911 returned in r0. */
9b66ebb1 912
ff73fb53 913#define REG_ALLOC_ORDER \
35d965d5 914{ \
ff73fb53
NC		 915 3, 2, 1, 0, 12, 14, 4, 5, \
916 6, 7, 8, 10, 9, 11, 13, 15, \
ff9940b0 917 16, 17, 18, 19, 20, 21, 22, 23, \
9b6b54e2
NC		 918 27, 28, 29, 30, 31, 32, 33, 34, \
919 35, 36, 37, 38, 39, 40, 41, 42, \
5a9335ef
NC		 920 43, 44, 45, 46, 47, 48, 49, 50, \
921 51, 52, 53, 54, 55, 56, 57, 58, \
922 59, 60, 61, 62, \
9b66ebb1
PB		 923 24, 25, 26, \
924 78, 77, 76, 75, 74, 73, 72, 71, \
925 70, 69, 68, 67, 66, 65, 64, 63, \
926 79, 80, 81, 82, 83, 84, 85, 86, \
927 87, 88, 89, 90, 91, 92, 93, 94, \
928 95 \
35d965d5 929}
9338ffe6
PB		 930
931/* Interrupt functions can only use registers that have already been
932 saved by the prologue, even if they would normally be
933 call-clobbered. */
934#define HARD_REGNO_RENAME_OK(SRC, DST) \
935 (! IS_INTERRUPT (cfun->machine->func_type) || \
936 regs_ever_live[DST])
35d965d5
RS		 937\f
938/* Register and constant classes. */
939
3b684012 940/* Register classes: used to be simple, just all ARM regs or all FPA regs
d6a7951f 941 Now that the Thumb is involved it has become more complicated. */
35d965d5
RS		 942enum reg_class
943{
944 NO_REGS,
3b684012 945 FPA_REGS,
9b6b54e2 946 CIRRUS_REGS,
9b66ebb1 947 VFP_REGS,
5a9335ef
NC		 948 IWMMXT_GR_REGS,
949 IWMMXT_REGS,
d5b7b3ae
RE		 950 LO_REGS,
951 STACK_REG,
952 BASE_REGS,
953 HI_REGS,
954 CC_REG,
9b66ebb1 955 VFPCC_REG,
35d965d5
RS		 956 GENERAL_REGS,
957 ALL_REGS,
958 LIM_REG_CLASSES
959};
960
961#define N_REG_CLASSES (int) LIM_REG_CLASSES
962
d6b4baa4 963/* Give names of register classes as strings for dump file. */
35d965d5
RS		 964#define REG_CLASS_NAMES \
965{ \
966 "NO_REGS", \
3b684012 967 "FPA_REGS", \
9b6b54e2 968 "CIRRUS_REGS", \
9b66ebb1 969 "VFP_REGS", \
5a9335ef
NC		 970 "IWMMXT_GR_REGS", \
971 "IWMMXT_REGS", \
d5b7b3ae
RE		 972 "LO_REGS", \
973 "STACK_REG", \
974 "BASE_REGS", \
975 "HI_REGS", \
976 "CC_REG", \
5384443a 977 "VFPCC_REG", \
35d965d5
RS		 978 "GENERAL_REGS", \
979 "ALL_REGS", \
980}
981
982/* Define which registers fit in which classes.
983 This is an initializer for a vector of HARD_REG_SET
984 of length N_REG_CLASSES. */
9b66ebb1
PB		 985#define REG_CLASS_CONTENTS \
986{ \
987 { 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
988 { 0x00FF0000, 0x00000000, 0x00000000 }, /* FPA_REGS */ \
989 { 0xF8000000, 0x000007FF, 0x00000000 }, /* CIRRUS_REGS */ \
990 { 0x00000000, 0x80000000, 0x7FFFFFFF }, /* VFP_REGS */ \
991 { 0x00000000, 0x00007800, 0x00000000 }, /* IWMMXT_GR_REGS */ \
992 { 0x00000000, 0x7FFF8000, 0x00000000 }, /* IWMMXT_REGS */ \
993 { 0x000000FF, 0x00000000, 0x00000000 }, /* LO_REGS */ \
994 { 0x00002000, 0x00000000, 0x00000000 }, /* STACK_REG */ \
995 { 0x000020FF, 0x00000000, 0x00000000 }, /* BASE_REGS */ \
996 { 0x0000FF00, 0x00000000, 0x00000000 }, /* HI_REGS */ \
997 { 0x01000000, 0x00000000, 0x00000000 }, /* CC_REG */ \
998 { 0x00000000, 0x00000000, 0x80000000 }, /* VFPCC_REG */ \
999 { 0x0200FFFF, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \
1000 { 0xFAFFFFFF, 0xFFFFFFFF, 0x7FFFFFFF } /* ALL_REGS */ \
35d965d5 1001}
4b02997f 1002
35d965d5
RS		 1003/* The same information, inverted:
1004 Return the class number of the smallest class containing
1005 reg number REGNO. This could be a conditional expression
1006 or could index an array. */
d5b7b3ae 1007#define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO)
35d965d5 1008
9b66ebb1 1009/* FPA registers can't do subreg as all values are reformatted to internal
59b9a953 1010 precision. VFP registers may only be accessed in the mode they
9b66ebb1 1011 were set. */
75d2580c
RE		 1012#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1013 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
9b66ebb1
PB		 1014 ? reg_classes_intersect_p (FPA_REGS, (CLASS)) \
1015 || reg_classes_intersect_p (VFP_REGS, (CLASS)) \
1016 : 0)
75d2580c 1017
cc81dde8
PB		 1018/* We need to define this for LO_REGS on thumb. Otherwise we can end up
1019 using r0-r4 for function arguments, r7 for the stack frame and don't
1020 have enough left over to do doubleword arithmetic. */
1021#define CLASS_LIKELY_SPILLED_P(CLASS) \
1022 ((TARGET_THUMB && (CLASS) == LO_REGS) \
1023 || (CLASS) == CC_REG)
f676971a 1024
35d965d5 1025/* The class value for index registers, and the one for base regs. */
d5b7b3ae 1026#define INDEX_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS)
b93a0fe6 1027#define BASE_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS)
d5b7b3ae 1028
b93a0fe6 1029/* For the Thumb the high registers cannot be used as base registers
6bc82793 1030 when addressing quantities in QI or HI mode; if we don't know the
888d2cd6 1031 mode, then we must be conservative. */
3dcc68a4 1032#define MODE_BASE_REG_CLASS(MODE) \
b93a0fe6 1033 (TARGET_ARM ? GENERAL_REGS : \
888d2cd6
DJ		 1034 (((MODE) == SImode) ? BASE_REGS : LO_REGS))
1035
1036/* For Thumb we can not support SP+reg addressing, so we return LO_REGS
1037 instead of BASE_REGS. */
1038#define MODE_BASE_REG_REG_CLASS(MODE) BASE_REG_CLASS
3dcc68a4 1039
d5b7b3ae
RE		 1040/* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1041 registers explicitly used in the rtl to be used as spill registers
1042 but prevents the compiler from extending the lifetime of these
d6b4baa4 1043 registers. */
d5b7b3ae 1044#define SMALL_REGISTER_CLASSES TARGET_THUMB
35d965d5
RS		 1045
1046/* Get reg_class from a letter such as appears in the machine description.
3b684012 1047 We only need constraint `f' for FPA_REGS (`r' == GENERAL_REGS) for the
d5b7b3ae
RE		 1048 ARM, but several more letters for the Thumb. */
1049#define REG_CLASS_FROM_LETTER(C) \
3b684012 1050 ( (C) == 'f' ? FPA_REGS \
9b6b54e2 1051 : (C) == 'v' ? CIRRUS_REGS \
9b66ebb1 1052 : (C) == 'w' ? VFP_REGS \
5a9335ef
NC		 1053 : (C) == 'y' ? IWMMXT_REGS \
1054 : (C) == 'z' ? IWMMXT_GR_REGS \
d5b7b3ae
RE		 1055 : (C) == 'l' ? (TARGET_ARM ? GENERAL_REGS : LO_REGS) \
1056 : TARGET_ARM ? NO_REGS \
1057 : (C) == 'h' ? HI_REGS \
1058 : (C) == 'b' ? BASE_REGS \
1059 : (C) == 'k' ? STACK_REG \
1060 : (C) == 'c' ? CC_REG \
1061 : NO_REGS)
35d965d5
RS		 1062
1063/* The letters I, J, K, L and M in a register constraint string
1064 can be used to stand for particular ranges of immediate operands.
1065 This macro defines what the ranges are.
1066 C is the letter, and VALUE is a constant value.
1067 Return 1 if VALUE is in the range specified by C.
b4ac57ab 1068 I: immediate arithmetic operand (i.e. 8 bits shifted as required).
f676971a 1069 J: valid indexing constants.
aef1764c 1070 K: ~value ok in rhs argument of data operand.
f676971a 1071 L: -value ok in rhs argument of data operand.
3967692c 1072 M: 0..32, or a power of 2 (for shifts, or mult done by shift). */
d5b7b3ae 1073#define CONST_OK_FOR_ARM_LETTER(VALUE, C) \
aef1764c
RE		 1074 ((C) == 'I' ? const_ok_for_arm (VALUE) : \
1075 (C) == 'J' ? ((VALUE) < 4096 && (VALUE) > -4096) : \
1076 (C) == 'K' ? (const_ok_for_arm (~(VALUE))) : \
3967692c
RE		 1077 (C) == 'L' ? (const_ok_for_arm (-(VALUE))) : \
1078 (C) == 'M' ? (((VALUE >= 0 && VALUE <= 32)) \
1079 || (((VALUE) & ((VALUE) - 1)) == 0)) \
1080 : 0)
ff9940b0 1081
d5b7b3ae
RE		 1082#define CONST_OK_FOR_THUMB_LETTER(VAL, C) \
1083 ((C) == 'I' ? (unsigned HOST_WIDE_INT) (VAL) < 256 : \
1084 (C) == 'J' ? (VAL) > -256 && (VAL) < 0 : \
1085 (C) == 'K' ? thumb_shiftable_const (VAL) : \
1086 (C) == 'L' ? (VAL) > -8 && (VAL) < 8 : \
1087 (C) == 'M' ? ((unsigned HOST_WIDE_INT) (VAL) < 1024 \
1088 && ((VAL) & 3) == 0) : \
1089 (C) == 'N' ? ((unsigned HOST_WIDE_INT) (VAL) < 32) : \
1090 (C) == 'O' ? ((VAL) >= -508 && (VAL) <= 508) \
1091 : 0)
1092
1093#define CONST_OK_FOR_LETTER_P(VALUE, C) \
1094 (TARGET_ARM ? \
1095 CONST_OK_FOR_ARM_LETTER (VALUE, C) : CONST_OK_FOR_THUMB_LETTER (VALUE, C))
f676971a 1096
9b66ebb1 1097/* Constant letter 'G' for the FP immediate constants.
d5b7b3ae
RE		 1098 'H' means the same constant negated. */
1099#define CONST_DOUBLE_OK_FOR_ARM_LETTER(X, C) \
9b66ebb1 1100 ((C) == 'G' ? arm_const_double_rtx (X) : \
3b684012 1101 (C) == 'H' ? neg_const_double_rtx_ok_for_fpa (X) : 0)
d5b7b3ae
RE		 1102
1103#define CONST_DOUBLE_OK_FOR_LETTER_P(X, C) \
1104 (TARGET_ARM ? \
1105 CONST_DOUBLE_OK_FOR_ARM_LETTER (X, C) : 0)
1106
ff9940b0 1107/* For the ARM, `Q' means that this is a memory operand that is just
f676971a 1108 an offset from a register.
ff9940b0
RE		 1109 `S' means any symbol that has the SYMBOL_REF_FLAG set or a CONSTANT_POOL
1110 address. This means that the symbol is in the text segment and can be
9b66ebb1 1111 accessed without using a load.
2075b05d
RE		 1112 'D' Prefixes a number of const_double operands where:
1113 'Da' is a constant that takes two ARM insns to load.
1114 'Db' takes three ARM insns.
1115 'Dc' takes four ARM insns, if we allow that in this compilation.
edc62122 1116 'U' Prefixes an extended memory constraint where:
f676971a
EC		 1117 'Uv' is an address valid for VFP load/store insns.
1118 'Uy' is an address valid for iwmmxt load/store insns.
edc62122 1119 'Uq' is an address valid for ldrsb. */
ff9940b0 1120
2075b05d 1121#define EXTRA_CONSTRAINT_STR_ARM(OP, C, STR) \
9b901d50
RE		 1122 (((C) == 'D') ? ((GET_CODE (OP) == CONST_DOUBLE \
1123 || GET_CODE (OP) == CONST_INT \
1124 || GET_CODE (OP) == CONST_VECTOR) \
2075b05d
RE		 1125 && (((STR)[1] == 'a' \
1126 && arm_const_double_inline_cost (OP) == 2) \
1127 || ((STR)[1] == 'b' \
1128 && arm_const_double_inline_cost (OP) == 3) \
1129 || ((STR)[1] == 'c' \
1130 && arm_const_double_inline_cost (OP) == 4 \
1131 && !(optimize_size || arm_ld_sched)))) : \
1132 ((C) == 'Q') ? (GET_CODE (OP) == MEM \
1133 && GET_CODE (XEXP (OP, 0)) == REG) : \
1134 ((C) == 'R') ? (GET_CODE (OP) == MEM \
1135 && GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \
1136 && CONSTANT_POOL_ADDRESS_P (XEXP (OP, 0))) : \
1137 ((C) == 'S') ? (optimize > 0 && CONSTANT_ADDRESS_P (OP)) : \
1138 ((C) == 'T') ? cirrus_memory_offset (OP) : \
fdd695fd
PB		 1139 ((C) == 'U' && (STR)[1] == 'v') ? arm_coproc_mem_operand (OP, FALSE) : \
1140 ((C) == 'U' && (STR)[1] == 'y') ? arm_coproc_mem_operand (OP, TRUE) : \
2075b05d
RE		 1141 ((C) == 'U' && (STR)[1] == 'q') \
1142 ? arm_extendqisi_mem_op (OP, GET_MODE (OP)) \
1143 : 0)
1e1ab407
RE		 1144
1145#define CONSTRAINT_LEN(C,STR) \
2075b05d 1146 (((C) == 'U' || (C) == 'D') ? 2 : DEFAULT_CONSTRAINT_LEN (C, STR))
ff9940b0 1147
d5b7b3ae
RE		 1148#define EXTRA_CONSTRAINT_THUMB(X, C) \
1149 ((C) == 'Q' ? (GET_CODE (X) == MEM \
1150 && GET_CODE (XEXP (X, 0)) == LABEL_REF) : 0)
1151
1e1ab407
RE		 1152#define EXTRA_CONSTRAINT_STR(X, C, STR) \
1153 (TARGET_ARM \
1154 ? EXTRA_CONSTRAINT_STR_ARM (X, C, STR) \
1155 : EXTRA_CONSTRAINT_THUMB (X, C))
35d965d5 1156
9b66ebb1
PB		 1157#define EXTRA_MEMORY_CONSTRAINT(C, STR) ((C) == 'U')
1158
35d965d5
RS		 1159/* Given an rtx X being reloaded into a reg required to be
1160 in class CLASS, return the class of reg to actually use.
d5b7b3ae
RE		 1161 In general this is just CLASS, but for the Thumb we prefer
1162 a LO_REGS class or a subset. */
1163#define PREFERRED_RELOAD_CLASS(X, CLASS) \
1164 (TARGET_ARM ? (CLASS) : \
1165 ((CLASS) == BASE_REGS ? (CLASS) : LO_REGS))
1166
1167/* Must leave BASE_REGS reloads alone */
1168#define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1169 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1170 ? ((true_regnum (X) == -1 ? LO_REGS \
1171 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1172 : NO_REGS)) \
1173 : NO_REGS)
1174
1175#define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
97358092 1176 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
d5b7b3ae
RE		 1177 ? ((true_regnum (X) == -1 ? LO_REGS \
1178 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1179 : NO_REGS)) \
1180 : NO_REGS)
35d965d5 1181
ff9940b0
RE		 1182/* Return the register class of a scratch register needed to copy IN into
1183 or out of a register in CLASS in MODE. If it can be done directly,
1184 NO_REGS is returned. */
d5b7b3ae 1185#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
9b66ebb1
PB		 1186 /* Restrict which direct reloads are allowed for VFP regs. */ \
1187 ((TARGET_VFP && TARGET_HARD_FLOAT \
1188 && (CLASS) == VFP_REGS) \
1189 ? vfp_secondary_reload_class (MODE, X) \
1190 : TARGET_ARM \
1191 ? (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \
d5b7b3ae
RE		 1192 ? GENERAL_REGS : NO_REGS) \
1193 : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X))
f676971a 1194
d6b4baa4 1195/* If we need to load shorts byte-at-a-time, then we need a scratch. */
d5b7b3ae 1196#define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
9b66ebb1
PB		 1197 /* Restrict which direct reloads are allowed for VFP regs. */ \
1198 ((TARGET_VFP && TARGET_HARD_FLOAT \
1199 && (CLASS) == VFP_REGS) \
1200 ? vfp_secondary_reload_class (MODE, X) : \
9b6b54e2 1201 /* Cannot load constants into Cirrus registers. */ \
9b66ebb1 1202 (TARGET_MAVERICK && TARGET_HARD_FLOAT \
9b6b54e2
NC		 1203 && (CLASS) == CIRRUS_REGS \
1204 && (CONSTANT_P (X) || GET_CODE (X) == SYMBOL_REF)) \
1205 ? GENERAL_REGS : \
d5b7b3ae 1206 (TARGET_ARM ? \
5a9335ef
NC		 1207 (((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \
1208 && CONSTANT_P (X)) \
1209 ? GENERAL_REGS : \
61f0ccff 1210 (((MODE) == HImode && ! arm_arch4 \
d5b7b3ae
RE		 1211 && (GET_CODE (X) == MEM \
1212 || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \
1213 && true_regnum (X) == -1))) \
1214 ? GENERAL_REGS : NO_REGS) \
9b6b54e2 1215 : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X)))
2ce9c1b9 1216
6f734908
RE		 1217/* Try a machine-dependent way of reloading an illegitimate address
1218 operand. If we find one, push the reload and jump to WIN. This
1219 macro is used in only one place: `find_reloads_address' in reload.c.
1220
1221 For the ARM, we wish to handle large displacements off a base
1222 register by splitting the addend across a MOV and the mem insn.
d5b7b3ae
RE		 1223 This can cut the number of reloads needed. */
1224#define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN) \
1225 do \
1226 { \
1227 if (GET_CODE (X) == PLUS \
1228 && GET_CODE (XEXP (X, 0)) == REG \
1229 && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \
1230 && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \
1231 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1232 { \
1233 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1234 HOST_WIDE_INT low, high; \
1235 \
de6f27a8 1236 if (MODE == DImode || (MODE == DFmode && TARGET_SOFT_FLOAT)) \
d5b7b3ae 1237 low = ((val & 0xf) ^ 0x8) - 0x8; \
9b66ebb1 1238 else if (TARGET_MAVERICK && TARGET_HARD_FLOAT) \
9b6b54e2
NC		 1239 /* Need to be careful, -256 is not a valid offset. */ \
1240 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
d5b7b3ae 1241 else if (MODE == SImode \
de6f27a8 1242 || (MODE == SFmode && TARGET_SOFT_FLOAT) \
d5b7b3ae
RE		 1243 || ((MODE == HImode || MODE == QImode) && ! arm_arch4)) \
1244 /* Need to be careful, -4096 is not a valid offset. */ \
1245 low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff); \
1246 else if ((MODE == HImode || MODE == QImode) && arm_arch4) \
1247 /* Need to be careful, -256 is not a valid offset. */ \
1248 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1249 else if (GET_MODE_CLASS (MODE) == MODE_FLOAT \
9b66ebb1 1250 && TARGET_HARD_FLOAT && TARGET_FPA) \
d5b7b3ae
RE		 1251 /* Need to be careful, -1024 is not a valid offset. */ \
1252 low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \
1253 else \
1254 break; \
1255 \
30cf4896
KG		 1256 high = ((((val - low) & (unsigned HOST_WIDE_INT) 0xffffffff) \
1257 ^ (unsigned HOST_WIDE_INT) 0x80000000) \
1258 - (unsigned HOST_WIDE_INT) 0x80000000); \
d5b7b3ae
RE		 1259 /* Check for overflow or zero */ \
1260 if (low == 0 || high == 0 || (high + low != val)) \
1261 break; \
1262 \
1263 /* Reload the high part into a base reg; leave the low part \
1264 in the mem. */ \
1265 X = gen_rtx_PLUS (GET_MODE (X), \
1266 gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \
1267 GEN_INT (high)), \
1268 GEN_INT (low)); \
df4ae160 1269 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
4a692617
NC		 1270 MODE_BASE_REG_CLASS (MODE), GET_MODE (X), \
1271 VOIDmode, 0, 0, OPNUM, TYPE); \
d5b7b3ae
RE		 1272 goto WIN; \
1273 } \
1274 } \
62b10bbc 1275 while (0)
6f734908 1276
27847754 1277/* XXX If an HImode FP+large_offset address is converted to an HImode
d5b7b3ae
RE		 1278 SP+large_offset address, then reload won't know how to fix it. It sees
1279 only that SP isn't valid for HImode, and so reloads the SP into an index
1280 register, but the resulting address is still invalid because the offset
1281 is too big. We fix it here instead by reloading the entire address. */
1282/* We could probably achieve better results by defining PROMOTE_MODE to help
1283 cope with the variances between the Thumb's signed and unsigned byte and
1284 halfword load instructions. */
1285#define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1286{ \
1287 if (GET_CODE (X) == PLUS \
1288 && GET_MODE_SIZE (MODE) < 4 \
1289 && GET_CODE (XEXP (X, 0)) == REG \
1290 && XEXP (X, 0) == stack_pointer_rtx \
1291 && GET_CODE (XEXP (X, 1)) == CONST_INT \
76a318e9 1292 && ! thumb_legitimate_offset_p (MODE, INTVAL (XEXP (X, 1)))) \
d5b7b3ae
RE		 1293 { \
1294 rtx orig_X = X; \
1295 X = copy_rtx (X); \
df4ae160 1296 push_reload (orig_X, NULL_RTX, &X, NULL, \
4a692617 1297 MODE_BASE_REG_CLASS (MODE), \
d5b7b3ae
RE		 1298 Pmode, VOIDmode, 0, 0, OPNUM, TYPE); \
1299 goto WIN; \
1300 } \
1301}
1302
1303#define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1304 if (TARGET_ARM) \
1305 ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \
1306 else \
1307 THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN)
f676971a 1308
35d965d5
RS		 1309/* Return the maximum number of consecutive registers
1310 needed to represent mode MODE in a register of class CLASS.
3b684012 1311 ARM regs are UNITS_PER_WORD bits while FPA regs can hold any FP mode */
35d965d5 1312#define CLASS_MAX_NREGS(CLASS, MODE) \
3b684012 1313 (((CLASS) == FPA_REGS || (CLASS) == CIRRUS_REGS) ? 1 : ARM_NUM_REGS (MODE))
9b6b54e2
NC		 1314
1315/* If defined, gives a class of registers that cannot be used as the
1316 operand of a SUBREG that changes the mode of the object illegally. */
35d965d5 1317
3b684012 1318/* Moves between FPA_REGS and GENERAL_REGS are two memory insns. */
cf011243 1319#define REGISTER_MOVE_COST(MODE, FROM, TO) \
d5b7b3ae 1320 (TARGET_ARM ? \
3b684012
RE		 1321 ((FROM) == FPA_REGS && (TO) != FPA_REGS ? 20 : \
1322 (FROM) != FPA_REGS && (TO) == FPA_REGS ? 20 : \
9b66ebb1
PB		 1323 (FROM) == VFP_REGS && (TO) != VFP_REGS ? 10 : \
1324 (FROM) != VFP_REGS && (TO) == VFP_REGS ? 10 : \
5a9335ef
NC		 1325 (FROM) == IWMMXT_REGS && (TO) != IWMMXT_REGS ? 4 : \
1326 (FROM) != IWMMXT_REGS && (TO) == IWMMXT_REGS ? 4 : \
1327 (FROM) == IWMMXT_GR_REGS || (TO) == IWMMXT_GR_REGS ? 20 : \
9b6b54e2
NC		 1328 (FROM) == CIRRUS_REGS && (TO) != CIRRUS_REGS ? 20 : \
1329 (FROM) != CIRRUS_REGS && (TO) == CIRRUS_REGS ? 20 : \
1330 2) \
d5b7b3ae
RE		 1331 : \
1332 ((FROM) == HI_REGS || (TO) == HI_REGS) ? 4 : 2)
35d965d5
RS		 1333\f
1334/* Stack layout; function entry, exit and calling. */
1335
1336/* Define this if pushing a word on the stack
1337 makes the stack pointer a smaller address. */
1338#define STACK_GROWS_DOWNWARD 1
1339
f62c8a5c 1340/* Define this to non-zero if the nominal address of the stack frame
35d965d5
RS		 1341 is at the high-address end of the local variables;
1342 that is, each additional local variable allocated
1343 goes at a more negative offset in the frame. */
1344#define FRAME_GROWS_DOWNWARD 1
1345
a2503645
RS		 1346/* The amount of scratch space needed by _interwork_{r7,r11}_call_via_rN().
1347 When present, it is one word in size, and sits at the top of the frame,
1348 between the soft frame pointer and either r7 or r11.
1349
1350 We only need _interwork_rM_call_via_rN() for -mcaller-super-interworking,
1351 and only then if some outgoing arguments are passed on the stack. It would
1352 be tempting to also check whether the stack arguments are passed by indirect
1353 calls, but there seems to be no reason in principle why a post-reload pass
1354 couldn't convert a direct call into an indirect one. */
1355#define CALLER_INTERWORKING_SLOT_SIZE \
1356 (TARGET_CALLER_INTERWORKING \
1357 && current_function_outgoing_args_size != 0 \
1358 ? UNITS_PER_WORD : 0)
1359
35d965d5
RS		 1360/* Offset within stack frame to start allocating local variables at.
1361 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1362 first local allocated. Otherwise, it is the offset to the BEGINNING
1363 of the first local allocated. */
1364#define STARTING_FRAME_OFFSET 0
1365
1366/* If we generate an insn to push BYTES bytes,
1367 this says how many the stack pointer really advances by. */
d5b7b3ae 1368/* The push insns do not do this rounding implicitly.
d6b4baa4 1369 So don't define this. */
0c2ca901 1370/* #define PUSH_ROUNDING(NPUSHED) ROUND_UP_WORD (NPUSHED) */
18543a22
ILT		 1371
1372/* Define this if the maximum size of all the outgoing args is to be
1373 accumulated and pushed during the prologue. The amount can be
1374 found in the variable current_function_outgoing_args_size. */
6cfc7210 1375#define ACCUMULATE_OUTGOING_ARGS 1
35d965d5
RS		 1376
1377/* Offset of first parameter from the argument pointer register value. */
d5b7b3ae 1378#define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0)
35d965d5
RS		 1379
1380/* Value is the number of byte of arguments automatically
1381 popped when returning from a subroutine call.
8b109b37 1382 FUNDECL is the declaration node of the function (as a tree),
35d965d5
RS		 1383 FUNTYPE is the data type of the function (as a tree),
1384 or for a library call it is an identifier node for the subroutine name.
1385 SIZE is the number of bytes of arguments passed on the stack.
1386
1387 On the ARM, the caller does not pop any of its arguments that were passed
1388 on the stack. */
6cfc7210 1389#define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0
35d965d5
RS		 1390
1391/* Define how to find the value returned by a library function
1392 assuming the value has mode MODE. */
1393#define LIBCALL_VALUE(MODE) \
72cdc543 1394 (TARGET_ARM && TARGET_HARD_FLOAT_ABI && TARGET_FPA \
9b66ebb1
PB		 1395 && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1396 ? gen_rtx_REG (MODE, FIRST_FPA_REGNUM) \
72cdc543 1397 : TARGET_ARM && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK \
9b66ebb1 1398 && GET_MODE_CLASS (MODE) == MODE_FLOAT \
9b6b54e2 1399 ? gen_rtx_REG (MODE, FIRST_CIRRUS_FP_REGNUM) \
f676971a 1400 : TARGET_IWMMXT_ABI && arm_vector_mode_supported_p (MODE) \
5a9335ef 1401 ? gen_rtx_REG (MODE, FIRST_IWMMXT_REGNUM) \
d5b7b3ae 1402 : gen_rtx_REG (MODE, ARG_REGISTER (1)))
35d965d5 1403
6cfc7210
NC		 1404/* Define how to find the value returned by a function.
1405 VALTYPE is the data type of the value (as a tree).
1406 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1407 otherwise, FUNC is 0. */
d5b7b3ae 1408#define FUNCTION_VALUE(VALTYPE, FUNC) \
d4453b7a 1409 arm_function_value (VALTYPE, FUNC);
6cfc7210 1410
35d965d5
RS		 1411/* 1 if N is a possible register number for a function value.
1412 On the ARM, only r0 and f0 can return results. */
9b6b54e2 1413/* On a Cirrus chip, mvf0 can return results. */
35d965d5 1414#define FUNCTION_VALUE_REGNO_P(REGNO) \
d5b7b3ae 1415 ((REGNO) == ARG_REGISTER (1) \
9b66ebb1 1416 || (TARGET_ARM && ((REGNO) == FIRST_CIRRUS_FP_REGNUM) \
72cdc543 1417 && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK) \
5848830f 1418 || ((REGNO) == FIRST_IWMMXT_REGNUM && TARGET_IWMMXT_ABI) \
9b66ebb1 1419 || (TARGET_ARM && ((REGNO) == FIRST_FPA_REGNUM) \
72cdc543 1420 && TARGET_HARD_FLOAT_ABI && TARGET_FPA))
35d965d5 1421
9f7bf991
RE		 1422/* Amount of memory needed for an untyped call to save all possible return
1423 registers. */
1424#define APPLY_RESULT_SIZE arm_apply_result_size()
1425
11c1a207
RE		 1426/* How large values are returned */
1427/* A C expression which can inhibit the returning of certain function values
d6b4baa4 1428 in registers, based on the type of value. */
f5a1b0d2 1429#define RETURN_IN_MEMORY(TYPE) arm_return_in_memory (TYPE)
11c1a207
RE		 1430
1431/* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return
1432 values must be in memory. On the ARM, they need only do so if larger
d6b4baa4 1433 than a word, or if they contain elements offset from zero in the struct. */
11c1a207
RE		 1434#define DEFAULT_PCC_STRUCT_RETURN 0
1435
d5b7b3ae
RE		 1436/* Flags for the call/call_value rtl operations set up by function_arg. */
1437#define CALL_NORMAL 0x00000000 /* No special processing. */
1438#define CALL_LONG 0x00000001 /* Always call indirect. */
1439#define CALL_SHORT 0x00000002 /* Never call indirect. */
1440
6d3d9133 1441/* These bits describe the different types of function supported
112cdef5 1442 by the ARM backend. They are exclusive. i.e. a function cannot be both a
6d3d9133
NC		 1443 normal function and an interworked function, for example. Knowing the
1444 type of a function is important for determining its prologue and
1445 epilogue sequences.
1446 Note value 7 is currently unassigned. Also note that the interrupt
1447 function types all have bit 2 set, so that they can be tested for easily.
1448 Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the
4912a07c 1449 machine_function structure is initialized (to zero) func_type will
6d3d9133
NC		 1450 default to unknown. This will force the first use of arm_current_func_type
1451 to call arm_compute_func_type. */
1452#define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */
1453#define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */
1454#define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */
6d3d9133
NC		 1455#define ARM_FT_ISR 4 /* An interrupt service routine. */
1456#define ARM_FT_FIQ 5 /* A fast interrupt service routine. */
1457#define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */
1458
1459#define ARM_FT_TYPE_MASK ((1 << 3) - 1)
1460
1461/* In addition functions can have several type modifiers,
1462 outlined by these bit masks: */
1463#define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */
1464#define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */
1465#define ARM_FT_VOLATILE (1 << 4) /* Does not return. */
d6b4baa4 1466#define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */
6d3d9133
NC		 1467
1468/* Some macros to test these flags. */
1469#define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK)
1470#define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT)
1471#define IS_VOLATILE(t) (t & ARM_FT_VOLATILE)
1472#define IS_NAKED(t) (t & ARM_FT_NAKED)
1473#define IS_NESTED(t) (t & ARM_FT_NESTED)
1474
5848830f
PB		 1475
1476/* Structure used to hold the function stack frame layout. Offsets are
1477 relative to the stack pointer on function entry. Positive offsets are
1478 in the direction of stack growth.
1479 Only soft_frame is used in thumb mode. */
1480
1481typedef struct arm_stack_offsets GTY(())
1482{
1483 int saved_args; /* ARG_POINTER_REGNUM. */
1484 int frame; /* ARM_HARD_FRAME_POINTER_REGNUM. */
1485 int saved_regs;
1486 int soft_frame; /* FRAME_POINTER_REGNUM. */
1487 int outgoing_args; /* STACK_POINTER_REGNUM. */
1488}
1489arm_stack_offsets;
1490
6d3d9133
NC		 1491/* A C structure for machine-specific, per-function data.
1492 This is added to the cfun structure. */
e2500fed 1493typedef struct machine_function GTY(())
d5b7b3ae 1494{
6bc82793 1495 /* Additional stack adjustment in __builtin_eh_throw. */
e2500fed 1496 rtx eh_epilogue_sp_ofs;
d5b7b3ae
RE		 1497 /* Records if LR has to be saved for far jumps. */
1498 int far_jump_used;
1499 /* Records if ARG_POINTER was ever live. */
1500 int arg_pointer_live;
6f7ebcbb
NC		 1501 /* Records if the save of LR has been eliminated. */
1502 int lr_save_eliminated;
0977774b 1503 /* The size of the stack frame. Only valid after reload. */
5848830f 1504 arm_stack_offsets stack_offsets;
6d3d9133
NC		 1505 /* Records the type of the current function. */
1506 unsigned long func_type;
3cb66fd7
NC		 1507 /* Record if the function has a variable argument list. */
1508 int uses_anonymous_args;
5a9335ef
NC		 1509 /* Records if sibcalls are blocked because an argument
1510 register is needed to preserve stack alignment. */
1511 int sibcall_blocked;
b12a00f1 1512 /* Labels for per-function Thumb call-via stubs. One per potential calling
57ecec57
PB		 1513 register. We can never call via LR or PC. We can call via SP if a
1514 trampoline happens to be on the top of the stack. */
1515 rtx call_via[14];
6d3d9133
NC		 1516}
1517machine_function;
d5b7b3ae 1518
b12a00f1
RE		 1519/* As in the machine_function, a global set of call-via labels, for code
1520 that is in text_section(). */
57ecec57 1521extern GTY(()) rtx thumb_call_via_label[14];
b12a00f1 1522
82e9d970
PB		 1523/* A C type for declaring a variable that is used as the first argument of
1524 `FUNCTION_ARG' and other related values. For some target machines, the
1525 type `int' suffices and can hold the number of bytes of argument so far. */
1526typedef struct
1527{
d5b7b3ae 1528 /* This is the number of registers of arguments scanned so far. */
82e9d970 1529 int nregs;
5a9335ef
NC		 1530 /* This is the number of iWMMXt register arguments scanned so far. */
1531 int iwmmxt_nregs;
1532 int named_count;
1533 int nargs;
d6b4baa4 1534 /* One of CALL_NORMAL, CALL_LONG or CALL_SHORT. */
82e9d970 1535 int call_cookie;
5848830f 1536 int can_split;
d5b7b3ae 1537} CUMULATIVE_ARGS;
82e9d970 1538
35d965d5
RS		 1539/* Define where to put the arguments to a function.
1540 Value is zero to push the argument on the stack,
1541 or a hard register in which to store the argument.
1542
1543 MODE is the argument's machine mode.
1544 TYPE is the data type of the argument (as a tree).
1545 This is null for libcalls where that information may
1546 not be available.
1547 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1548 the preceding args and about the function being called.
1549 NAMED is nonzero if this argument is a named parameter
1550 (otherwise it is an extra parameter matching an ellipsis).
1551
1552 On the ARM, normally the first 16 bytes are passed in registers r0-r3; all
1553 other arguments are passed on the stack. If (NAMED == 0) (which happens
1cc9f5f5
KH		 1554 only in assign_parms, since TARGET_SETUP_INCOMING_VARARGS is
1555 defined), say it is passed in the stack (function_prologue will
1556 indeed make it pass in the stack if necessary). */
82e9d970
PB		 1557#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1558 arm_function_arg (&(CUM), (MODE), (TYPE), (NAMED))
35d965d5 1559
866af8a9
JB		 1560#define FUNCTION_ARG_PADDING(MODE, TYPE) \
1561 (arm_pad_arg_upward (MODE, TYPE) ? upward : downward)
1562
1563#define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
1564 (arm_pad_reg_upward (MODE, TYPE, FIRST) ? upward : downward)
1565
1566/* For AAPCS, padding should never be below the argument. For other ABIs,
1567 * mimic the default. */
1568#define PAD_VARARGS_DOWN \
1569 ((TARGET_AAPCS_BASED) ? 0 : BYTES_BIG_ENDIAN)
1570
35d965d5
RS		 1571/* Initialize a variable CUM of type CUMULATIVE_ARGS
1572 for a call to a function whose data type is FNTYPE.
1573 For a library call, FNTYPE is 0.
1574 On the ARM, the offset starts at 0. */
0f6937fe 1575#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
563a317a 1576 arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL))
35d965d5
RS		 1577
1578/* Update the data in CUM to advance over an argument
1579 of mode MODE and data type TYPE.
1580 (TYPE is null for libcalls where that information may not be available.) */
6cfc7210 1581#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
5a9335ef 1582 (CUM).nargs += 1; \
f676971a 1583 if (arm_vector_mode_supported_p (MODE) \
5848830f
PB		 1584 && (CUM).named_count > (CUM).nargs) \
1585 (CUM).iwmmxt_nregs += 1; \
5a9335ef 1586 else \
5848830f 1587 (CUM).nregs += ARM_NUM_REGS2 (MODE, TYPE)
35d965d5 1588
5a9335ef
NC		 1589/* If defined, a C expression that gives the alignment boundary, in bits, of an
1590 argument with the specified mode and type. If it is not defined,
1591 `PARM_BOUNDARY' is used for all arguments. */
1592#define FUNCTION_ARG_BOUNDARY(MODE,TYPE) \
5848830f
PB		 1593 ((ARM_DOUBLEWORD_ALIGN && arm_needs_doubleword_align (MODE, TYPE)) \
1594 ? DOUBLEWORD_ALIGNMENT \
1595 : PARM_BOUNDARY )
5a9335ef 1596
35d965d5
RS		 1597/* 1 if N is a possible register number for function argument passing.
1598 On the ARM, r0-r3 are used to pass args. */
5a9335ef
NC		 1599#define FUNCTION_ARG_REGNO_P(REGNO) \
1600 (IN_RANGE ((REGNO), 0, 3) \
5848830f
PB		 1601 || (TARGET_IWMMXT_ABI \
1602 && IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9)))
35d965d5 1603
f99fce0c 1604\f
afef3d7a
NC		 1605/* If your target environment doesn't prefix user functions with an
1606 underscore, you may wish to re-define this to prevent any conflicts.
1607 e.g. AOF may prefix mcount with an underscore. */
1608#ifndef ARM_MCOUNT_NAME
1609#define ARM_MCOUNT_NAME "*mcount"
1610#endif
1611
1612/* Call the function profiler with a given profile label. The Acorn
1613 compiler puts this BEFORE the prolog but gcc puts it afterwards.
1614 On the ARM the full profile code will look like:
1615 .data
1616 LP1
1617 .word 0
1618 .text
1619 mov ip, lr
1620 bl mcount
1621 .word LP1
1622
1623 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER
1624 will output the .text section.
1625
1626 The ``mov ip,lr'' seems like a good idea to stick with cc convention.
59be6073
AN		 1627 ``prof'' doesn't seem to mind about this!
1628
1629 Note - this version of the code is designed to work in both ARM and
1630 Thumb modes. */
be393ecf 1631#ifndef ARM_FUNCTION_PROFILER
d5b7b3ae 1632#define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \
6cfc7210
NC		 1633{ \
1634 char temp[20]; \
1635 rtx sym; \
1636 \
dd18ae56 1637 asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \
d5b7b3ae 1638 IP_REGNUM, LR_REGNUM); \
6cfc7210
NC		 1639 assemble_name (STREAM, ARM_MCOUNT_NAME); \
1640 fputc ('\n', STREAM); \
1641 ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \
f1c25d3b 1642 sym = gen_rtx_SYMBOL_REF (Pmode, temp); \
301d03af 1643 assemble_aligned_integer (UNITS_PER_WORD, sym); \
35d965d5 1644}
be393ecf 1645#endif
35d965d5 1646
59be6073 1647#ifdef THUMB_FUNCTION_PROFILER
d5b7b3ae
RE		 1648#define FUNCTION_PROFILER(STREAM, LABELNO) \
1649 if (TARGET_ARM) \
1650 ARM_FUNCTION_PROFILER (STREAM, LABELNO) \
1651 else \
1652 THUMB_FUNCTION_PROFILER (STREAM, LABELNO)
59be6073
AN		 1653#else
1654#define FUNCTION_PROFILER(STREAM, LABELNO) \
1655 ARM_FUNCTION_PROFILER (STREAM, LABELNO)
1656#endif
d5b7b3ae 1657
35d965d5
RS		 1658/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1659 the stack pointer does not matter. The value is tested only in
1660 functions that have frame pointers.
1661 No definition is equivalent to always zero.
1662
1663 On the ARM, the function epilogue recovers the stack pointer from the
1664 frame. */
1665#define EXIT_IGNORE_STACK 1
1666
c7861455
RE		 1667#define EPILOGUE_USES(REGNO) (reload_completed && (REGNO) == LR_REGNUM)
1668
35d965d5
RS		 1669/* Determine if the epilogue should be output as RTL.
1670 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
d5b7b3ae 1671#define USE_RETURN_INSN(ISCOND) \
a72d4945 1672 (TARGET_ARM ? use_return_insn (ISCOND, NULL) : 0)
ff9940b0
RE		 1673
1674/* Definitions for register eliminations.
1675
1676 This is an array of structures. Each structure initializes one pair
1677 of eliminable registers. The "from" register number is given first,
1678 followed by "to". Eliminations of the same "from" register are listed
1679 in order of preference.
1680
1681 We have two registers that can be eliminated on the ARM. First, the
1682 arg pointer register can often be eliminated in favor of the stack
1683 pointer register. Secondly, the pseudo frame pointer register can always
1684 be eliminated; it is replaced with either the stack or the real frame
d5b7b3ae 1685 pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM
d6a7951f 1686 because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */
ff9940b0 1687
d5b7b3ae
RE		 1688#define ELIMINABLE_REGS \
1689{{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1690 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\
1691 { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1692 { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\
1693 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1694 { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1695 { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }}
ff9940b0 1696
d5b7b3ae
RE		 1697/* Given FROM and TO register numbers, say whether this elimination is
1698 allowed. Frame pointer elimination is automatically handled.
ff9940b0
RE		 1699
1700 All eliminations are permissible. Note that ARG_POINTER_REGNUM and
abc95ed3 1701 HARD_FRAME_POINTER_REGNUM are in fact the same thing. If we need a frame
ff9940b0 1702 pointer, we must eliminate FRAME_POINTER_REGNUM into
d5b7b3ae
RE		 1703 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM or
1704 ARG_POINTER_REGNUM. */
1705#define CAN_ELIMINATE(FROM, TO) \
1706 (((TO) == FRAME_POINTER_REGNUM && (FROM) == ARG_POINTER_REGNUM) ? 0 : \
1707 ((TO) == STACK_POINTER_REGNUM && frame_pointer_needed) ? 0 : \
1708 ((TO) == ARM_HARD_FRAME_POINTER_REGNUM && TARGET_THUMB) ? 0 : \
1709 ((TO) == THUMB_HARD_FRAME_POINTER_REGNUM && TARGET_ARM) ? 0 : \
1710 1)
aeaf4d25 1711
d5b7b3ae
RE		 1712/* Define the offset between two registers, one to be eliminated, and the
1713 other its replacement, at the start of a routine. */
d5b7b3ae
RE		 1714#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1715 if (TARGET_ARM) \
5848830f 1716 (OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \
d5b7b3ae 1717 else \
5848830f
PB		 1718 (OFFSET) = thumb_compute_initial_elimination_offset (FROM, TO)
1719
d5b7b3ae
RE		 1720/* Special case handling of the location of arguments passed on the stack. */
1721#define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr)
f676971a 1722
d5b7b3ae
RE		 1723/* Initialize data used by insn expanders. This is called from insn_emit,
1724 once for every function before code is generated. */
1725#define INIT_EXPANDERS arm_init_expanders ()
1726
35d965d5
RS		 1727/* Output assembler code for a block containing the constant parts
1728 of a trampoline, leaving space for the variable parts.
1729
1730 On the ARM, (if r8 is the static chain regnum, and remembering that
1731 referencing pc adds an offset of 8) the trampoline looks like:
1732 ldr r8, [pc, #0]
1733 ldr pc, [pc]
1734 .word static chain value
11c1a207 1735 .word function's address
27847754 1736 XXX FIXME: When the trampoline returns, r8 will be clobbered. */
301d03af
RS		 1737#define ARM_TRAMPOLINE_TEMPLATE(FILE) \
1738{ \
1739 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
1740 STATIC_CHAIN_REGNUM, PC_REGNUM); \
1741 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
1742 PC_REGNUM, PC_REGNUM); \
1743 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1744 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
d5b7b3ae
RE		 1745}
1746
1747/* On the Thumb we always switch into ARM mode to execute the trampoline.
1748 Why - because it is easier. This code will always be branched to via
1749 a BX instruction and since the compiler magically generates the address
1750 of the function the linker has no opportunity to ensure that the
1751 bottom bit is set. Thus the processor will be in ARM mode when it
1752 reaches this code. So we duplicate the ARM trampoline code and add
1753 a switch into Thumb mode as well. */
1754#define THUMB_TRAMPOLINE_TEMPLATE(FILE) \
1755{ \
1756 fprintf (FILE, "\t.code 32\n"); \
1757 fprintf (FILE, ".Ltrampoline_start:\n"); \
1758 asm_fprintf (FILE, "\tldr\t%r, [%r, #8]\n", \
1759 STATIC_CHAIN_REGNUM, PC_REGNUM); \
1760 asm_fprintf (FILE, "\tldr\t%r, [%r, #8]\n", \
1761 IP_REGNUM, PC_REGNUM); \
1762 asm_fprintf (FILE, "\torr\t%r, %r, #1\n", \
1763 IP_REGNUM, IP_REGNUM); \
1764 asm_fprintf (FILE, "\tbx\t%r\n", IP_REGNUM); \
1765 fprintf (FILE, "\t.word\t0\n"); \
1766 fprintf (FILE, "\t.word\t0\n"); \
1767 fprintf (FILE, "\t.code 16\n"); \
35d965d5
RS		 1768}
1769
d5b7b3ae
RE		 1770#define TRAMPOLINE_TEMPLATE(FILE) \
1771 if (TARGET_ARM) \
1772 ARM_TRAMPOLINE_TEMPLATE (FILE) \
1773 else \
1774 THUMB_TRAMPOLINE_TEMPLATE (FILE)
f676971a 1775
35d965d5 1776/* Length in units of the trampoline for entering a nested function. */
d5b7b3ae 1777#define TRAMPOLINE_SIZE (TARGET_ARM ? 16 : 24)
35d965d5 1778
006946e4
JM		 1779/* Alignment required for a trampoline in bits. */
1780#define TRAMPOLINE_ALIGNMENT 32
35d965d5 1781
2a86f515 1782
35d965d5
RS		 1783/* Emit RTL insns to initialize the variable parts of a trampoline.
1784 FNADDR is an RTX for the address of the function's pure code.
1785 CXT is an RTX for the static chain value for the function. */
192c8d78
RE		 1786#ifndef INITIALIZE_TRAMPOLINE
1787#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1788{ \
1789 emit_move_insn (gen_rtx_MEM (SImode, \
1790 plus_constant (TRAMP, \
1791 TARGET_ARM ? 8 : 16)), \
1792 CXT); \
1793 emit_move_insn (gen_rtx_MEM (SImode, \
1794 plus_constant (TRAMP, \
1795 TARGET_ARM ? 12 : 20)), \
1796 FNADDR); \
49755603
RE		 1797 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__clear_cache"), \
1798 0, VOIDmode, 2, TRAMP, Pmode, \
1799 plus_constant (TRAMP, TRAMPOLINE_SIZE), Pmode); \
35d965d5 1800}
192c8d78 1801#endif
35d965d5 1802
35d965d5
RS		 1803\f
1804/* Addressing modes, and classification of registers for them. */
3cd45774
RE		 1805#define HAVE_POST_INCREMENT 1
1806#define HAVE_PRE_INCREMENT TARGET_ARM
1807#define HAVE_POST_DECREMENT TARGET_ARM
1808#define HAVE_PRE_DECREMENT TARGET_ARM
1809#define HAVE_PRE_MODIFY_DISP TARGET_ARM
1810#define HAVE_POST_MODIFY_DISP TARGET_ARM
1811#define HAVE_PRE_MODIFY_REG TARGET_ARM
1812#define HAVE_POST_MODIFY_REG TARGET_ARM
35d965d5
RS		 1813
1814/* Macros to check register numbers against specific register classes. */
1815
1816/* These assume that REGNO is a hard or pseudo reg number.
1817 They give nonzero only if REGNO is a hard reg of the suitable class
1818 or a pseudo reg currently allocated to a suitable hard reg.
1819 Since they use reg_renumber, they are safe only once reg_renumber
d6b4baa4 1820 has been allocated, which happens in local-alloc.c. */
d5b7b3ae
RE		 1821#define TEST_REGNO(R, TEST, VALUE) \
1822 ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE))
1823
1824/* On the ARM, don't allow the pc to be used. */
f1008e52
RE		 1825#define ARM_REGNO_OK_FOR_BASE_P(REGNO) \
1826 (TEST_REGNO (REGNO, <, PC_REGNUM) \
1827 || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \
1828 || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM))
1829
1830#define THUMB_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1831 (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \
1832 || (GET_MODE_SIZE (MODE) >= 4 \
1833 && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)))
1834
1835#define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1836 (TARGET_THUMB \
1837 ? THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \
1838 : ARM_REGNO_OK_FOR_BASE_P (REGNO))
1839
888d2cd6
DJ		 1840/* Nonzero if X can be the base register in a reg+reg addressing mode.
1841 For Thumb, we can not use SP + reg, so reject SP. */
1842#define REGNO_MODE_OK_FOR_REG_BASE_P(X, MODE) \
1843 REGNO_OK_FOR_INDEX_P (X)
1844
f1008e52
RE		 1845/* For ARM code, we don't care about the mode, but for Thumb, the index
1846 must be suitable for use in a QImode load. */
d5b7b3ae
RE		 1847#define REGNO_OK_FOR_INDEX_P(REGNO) \
1848 REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode)
35d965d5
RS		 1849
1850/* Maximum number of registers that can appear in a valid memory address.
d6b4baa4 1851 Shifts in addresses can't be by a register. */
ff9940b0 1852#define MAX_REGS_PER_ADDRESS 2
35d965d5
RS		 1853
1854/* Recognize any constant value that is a valid address. */
1855/* XXX We can address any constant, eventually... */
11c1a207
RE		 1856
1857#ifdef AOF_ASSEMBLER
1858
1859#define CONSTANT_ADDRESS_P(X) \
d5b7b3ae 1860 (GET_CODE (X) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (X))
11c1a207
RE		 1861
1862#else
35d965d5 1863
008cf58a
RE		 1864#define CONSTANT_ADDRESS_P(X) \
1865 (GET_CODE (X) == SYMBOL_REF \
1866 && (CONSTANT_POOL_ADDRESS_P (X) \
d5b7b3ae 1867 || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X))))
35d965d5 1868
11c1a207
RE		 1869#endif /* AOF_ASSEMBLER */
1870
35d965d5
RS		 1871/* Nonzero if the constant value X is a legitimate general operand.
1872 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1873
1874 On the ARM, allow any integer (invalid ones are removed later by insn
1875 patterns), nice doubles and symbol_refs which refer to the function's
d5b7b3ae 1876 constant pool XXX.
f676971a 1877
82e9d970 1878 When generating pic allow anything. */
d5b7b3ae
RE		 1879#define ARM_LEGITIMATE_CONSTANT_P(X) (flag_pic || ! label_mentioned_p (X))
1880
1881#define THUMB_LEGITIMATE_CONSTANT_P(X) \
1882 ( GET_CODE (X) == CONST_INT \
1883 || GET_CODE (X) == CONST_DOUBLE \
7b8781c8
PB		 1884 || CONSTANT_ADDRESS_P (X) \
1885 || flag_pic)
d5b7b3ae
RE		 1886
1887#define LEGITIMATE_CONSTANT_P(X) \
1888 (TARGET_ARM ? ARM_LEGITIMATE_CONSTANT_P (X) : THUMB_LEGITIMATE_CONSTANT_P (X))
1889
c27ba912
DM		 1890/* Special characters prefixed to function names
1891 in order to encode attribute like information.
1892 Note, '@' and '*' have already been taken. */
1893#define SHORT_CALL_FLAG_CHAR '^'
1894#define LONG_CALL_FLAG_CHAR '#'
1895
1896#define ENCODED_SHORT_CALL_ATTR_P(SYMBOL_NAME) \
1897 (*(SYMBOL_NAME) == SHORT_CALL_FLAG_CHAR)
1898
1899#define ENCODED_LONG_CALL_ATTR_P(SYMBOL_NAME) \
1900 (*(SYMBOL_NAME) == LONG_CALL_FLAG_CHAR)
1901
1902#ifndef SUBTARGET_NAME_ENCODING_LENGTHS
1903#define SUBTARGET_NAME_ENCODING_LENGTHS
1904#endif
1905
6bc82793 1906/* This is a C fragment for the inside of a switch statement.
c27ba912
DM		 1907 Each case label should return the number of characters to
1908 be stripped from the start of a function's name, if that
1909 name starts with the indicated character. */
1910#define ARM_NAME_ENCODING_LENGTHS \
1911 case SHORT_CALL_FLAG_CHAR: return 1; \
1912 case LONG_CALL_FLAG_CHAR: return 1; \
00fdafef 1913 case '*': return 1; \
f676971a 1914 SUBTARGET_NAME_ENCODING_LENGTHS
c27ba912 1915
c27ba912
DM		 1916/* This is how to output a reference to a user-level label named NAME.
1917 `assemble_name' uses this. */
e5951263 1918#undef ASM_OUTPUT_LABELREF
c27ba912 1919#define ASM_OUTPUT_LABELREF(FILE, NAME) \
e1944073 1920 arm_asm_output_labelref (FILE, NAME)
c27ba912 1921
7abc66b1
JB		 1922/* The EABI specifies that constructors should go in .init_array.
1923 Other targets use .ctors for compatibility. */
88c6057f 1924#ifndef ARM_EABI_CTORS_SECTION_OP
7abc66b1
JB		 1925#define ARM_EABI_CTORS_SECTION_OP \
1926 "\t.section\t.init_array,\"aw\",%init_array"
88c6057f
MM		 1927#endif
1928#ifndef ARM_EABI_DTORS_SECTION_OP
7abc66b1
JB		 1929#define ARM_EABI_DTORS_SECTION_OP \
1930 "\t.section\t.fini_array,\"aw\",%fini_array"
88c6057f 1931#endif
7abc66b1
JB		 1932#define ARM_CTORS_SECTION_OP \
1933 "\t.section\t.ctors,\"aw\",%progbits"
1934#define ARM_DTORS_SECTION_OP \
1935 "\t.section\t.dtors,\"aw\",%progbits"
1936
1937/* Define CTORS_SECTION_ASM_OP. */
1938#undef CTORS_SECTION_ASM_OP
1939#undef DTORS_SECTION_ASM_OP
1940#ifndef IN_LIBGCC2
1941# define CTORS_SECTION_ASM_OP \
1942 (TARGET_AAPCS_BASED ? ARM_EABI_CTORS_SECTION_OP : ARM_CTORS_SECTION_OP)
1943# define DTORS_SECTION_ASM_OP \
1944 (TARGET_AAPCS_BASED ? ARM_EABI_DTORS_SECTION_OP : ARM_DTORS_SECTION_OP)
1945#else /* !defined (IN_LIBGCC2) */
1946/* In libgcc, CTORS_SECTION_ASM_OP must be a compile-time constant,
1947 so we cannot use the definition above. */
1948# ifdef __ARM_EABI__
1949/* The .ctors section is not part of the EABI, so we do not define
1950 CTORS_SECTION_ASM_OP when in libgcc; that prevents crtstuff
1951 from trying to use it. We do define it when doing normal
1952 compilation, as .init_array can be used instead of .ctors. */
1953/* There is no need to emit begin or end markers when using
1954 init_array; the dynamic linker will compute the size of the
1955 array itself based on special symbols created by the static
1956 linker. However, we do need to arrange to set up
1957 exception-handling here. */
1958# define CTOR_LIST_BEGIN asm (ARM_EABI_CTORS_SECTION_OP)
1959# define CTOR_LIST_END /* empty */
1960# define DTOR_LIST_BEGIN asm (ARM_EABI_DTORS_SECTION_OP)
1961# define DTOR_LIST_END /* empty */
1962# else /* !defined (__ARM_EABI__) */
1963# define CTORS_SECTION_ASM_OP ARM_CTORS_SECTION_OP
1964# define DTORS_SECTION_ASM_OP ARM_DTORS_SECTION_OP
1965# endif /* !defined (__ARM_EABI__) */
1966#endif /* !defined (IN_LIBCC2) */
1967
1e731102
MM		 1968/* True if the operating system can merge entities with vague linkage
1969 (e.g., symbols in COMDAT group) during dynamic linking. */
1970#ifndef TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P
1971#define TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P true
1972#endif
1973
a77655b1
NC		 1974/* Set the short-call flag for any function compiled in the current
1975 compilation unit. We skip this for functions with the section
c112cf2b 1976 attribute when long-calls are in effect as this tells the compiler
a77655b1
NC		 1977 that the section might be placed a long way from the caller.
1978 See arm_is_longcall_p() for more information. */
c27ba912 1979#define ARM_DECLARE_FUNCTION_SIZE(STREAM, NAME, DECL) \
a77655b1
NC		 1980 if (!TARGET_LONG_CALLS || ! DECL_SECTION_NAME (DECL)) \
1981 arm_encode_call_attribute (DECL, SHORT_CALL_FLAG_CHAR)
c27ba912 1982
617a1b71
PB		 1983#define ARM_OUTPUT_FN_UNWIND(F, PROLOGUE) arm_output_fn_unwind (F, PROLOGUE)
1984
1985#ifdef TARGET_UNWIND_INFO
1986#define ARM_EABI_UNWIND_TABLES \
1987 ((!USING_SJLJ_EXCEPTIONS && flag_exceptions) || flag_unwind_tables)
1988#else
1989#define ARM_EABI_UNWIND_TABLES 0
1990#endif
1991
35d965d5
RS		 1992/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1993 and check its validity for a certain class.
1994 We have two alternate definitions for each of them.
1995 The usual definition accepts all pseudo regs; the other rejects
1996 them unless they have been allocated suitable hard regs.
1997 The symbol REG_OK_STRICT causes the latter definition to be used. */
1998#ifndef REG_OK_STRICT
ff9940b0 1999
f1008e52
RE		 2000#define ARM_REG_OK_FOR_BASE_P(X) \
2001 (REGNO (X) <= LAST_ARM_REGNUM \
2002 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
2003 || REGNO (X) == FRAME_POINTER_REGNUM \
2004 || REGNO (X) == ARG_POINTER_REGNUM)
ff9940b0 2005
f1008e52
RE		 2006#define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \
2007 (REGNO (X) <= LAST_LO_REGNUM \
2008 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
2009 || (GET_MODE_SIZE (MODE) >= 4 \
2010 && (REGNO (X) == STACK_POINTER_REGNUM \
2011 || (X) == hard_frame_pointer_rtx \
2012 || (X) == arg_pointer_rtx)))
ff9940b0 2013
76a318e9
RE		 2014#define REG_STRICT_P 0
2015
d5b7b3ae 2016#else /* REG_OK_STRICT */
ff9940b0 2017
f1008e52
RE		 2018#define ARM_REG_OK_FOR_BASE_P(X) \
2019 ARM_REGNO_OK_FOR_BASE_P (REGNO (X))
ff9940b0 2020
f1008e52
RE		 2021#define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \
2022 THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE)
ff9940b0 2023
76a318e9
RE		 2024#define REG_STRICT_P 1
2025
d5b7b3ae 2026#endif /* REG_OK_STRICT */
f1008e52
RE		 2027
2028/* Now define some helpers in terms of the above. */
2029
2030#define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2031 (TARGET_THUMB \
2032 ? THUMB_REG_MODE_OK_FOR_BASE_P (X, MODE) \
2033 : ARM_REG_OK_FOR_BASE_P (X))
2034
2035#define ARM_REG_OK_FOR_INDEX_P(X) ARM_REG_OK_FOR_BASE_P (X)
2036
2037/* For Thumb, a valid index register is anything that can be used in
2038 a byte load instruction. */
2039#define THUMB_REG_OK_FOR_INDEX_P(X) THUMB_REG_MODE_OK_FOR_BASE_P (X, QImode)
2040
2041/* Nonzero if X is a hard reg that can be used as an index
2042 or if it is a pseudo reg. On the Thumb, the stack pointer
2043 is not suitable. */
2044#define REG_OK_FOR_INDEX_P(X) \
2045 (TARGET_THUMB \
2046 ? THUMB_REG_OK_FOR_INDEX_P (X) \
2047 : ARM_REG_OK_FOR_INDEX_P (X))
2048
888d2cd6
DJ		 2049/* Nonzero if X can be the base register in a reg+reg addressing mode.
2050 For Thumb, we can not use SP + reg, so reject SP. */
2051#define REG_MODE_OK_FOR_REG_BASE_P(X, MODE) \
2052 REG_OK_FOR_INDEX_P (X)
35d965d5
RS		 2053\f
2054/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2055 that is a valid memory address for an instruction.
2056 The MODE argument is the machine mode for the MEM expression
76a318e9 2057 that wants to use this address. */
f676971a 2058
f1008e52
RE		 2059#define ARM_BASE_REGISTER_RTX_P(X) \
2060 (GET_CODE (X) == REG && ARM_REG_OK_FOR_BASE_P (X))
35d965d5 2061
f1008e52
RE		 2062#define ARM_INDEX_REGISTER_RTX_P(X) \
2063 (GET_CODE (X) == REG && ARM_REG_OK_FOR_INDEX_P (X))
35d965d5 2064
76a318e9
RE		 2065#define ARM_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
2066 { \
1e1ab407 2067 if (arm_legitimate_address_p (MODE, X, SET, REG_STRICT_P)) \
76a318e9 2068 goto WIN; \
6b990f6b 2069 }
d5b7b3ae 2070
76a318e9
RE		 2071#define THUMB_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \
2072 { \
2073 if (thumb_legitimate_address_p (MODE, X, REG_STRICT_P)) \
2074 goto WIN; \
2075 }
d5b7b3ae 2076
d5b7b3ae
RE		 2077#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \
2078 if (TARGET_ARM) \
2079 ARM_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN) \
2080 else /* if (TARGET_THUMB) */ \
f676971a 2081 THUMB_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN)
76a318e9 2082
35d965d5
RS		 2083\f
2084/* Try machine-dependent ways of modifying an illegitimate address
ccf4d512
RE		 2085 to be legitimate. If we find one, return the new, valid address. */
2086#define ARM_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2087do { \
2088 X = arm_legitimize_address (X, OLDX, MODE); \
ccf4d512
RE		 2089} while (0)
2090
6f5b4f3e
RE		 2091#define THUMB_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2092do { \
2093 X = thumb_legitimize_address (X, OLDX, MODE); \
ccf4d512
RE		 2094} while (0)
2095
2096#define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2097do { \
2098 if (TARGET_ARM) \
2099 ARM_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
2100 else \
2101 THUMB_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \
6f5b4f3e
RE		 2102 \
2103 if (memory_address_p (MODE, X)) \
2104 goto WIN; \
ccf4d512 2105} while (0)
f676971a 2106
35d965d5
RS		 2107/* Go to LABEL if ADDR (a legitimate address expression)
2108 has an effect that depends on the machine mode it is used for. */
d5b7b3ae 2109#define ARM_GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
35d965d5 2110{ \
d5b7b3ae
RE		 2111 if ( GET_CODE (ADDR) == PRE_DEC || GET_CODE (ADDR) == POST_DEC \
2112 || GET_CODE (ADDR) == PRE_INC || GET_CODE (ADDR) == POST_INC) \
35d965d5
RS		 2113 goto LABEL; \
2114}
d5b7b3ae
RE		 2115
2116/* Nothing helpful to do for the Thumb */
2117#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2118 if (TARGET_ARM) \
f676971a 2119 ARM_GO_IF_MODE_DEPENDENT_ADDRESS (ADDR, LABEL)
35d965d5 2120\f
d5b7b3ae 2121
35d965d5
RS		 2122/* Specify the machine mode that this machine uses
2123 for the index in the tablejump instruction. */
d5b7b3ae 2124#define CASE_VECTOR_MODE Pmode
35d965d5 2125
ff9940b0
RE		 2126/* signed 'char' is most compatible, but RISC OS wants it unsigned.
2127 unsigned is probably best, but may break some code. */
2128#ifndef DEFAULT_SIGNED_CHAR
3967692c 2129#define DEFAULT_SIGNED_CHAR 0
35d965d5
RS		 2130#endif
2131
35d965d5 2132/* Max number of bytes we can move from memory to memory
d17ce9af
TG		 2133 in one reasonably fast instruction. */
2134#define MOVE_MAX 4
35d965d5 2135
d19fb8e3 2136#undef MOVE_RATIO
591af218 2137#define MOVE_RATIO (arm_tune_xscale ? 4 : 2)
d19fb8e3 2138
ff9940b0
RE		 2139/* Define if operations between registers always perform the operation
2140 on the full register even if a narrower mode is specified. */
2141#define WORD_REGISTER_OPERATIONS
2142
2143/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2144 will either zero-extend or sign-extend. The value of this macro should
2145 be the code that says which one of the two operations is implicitly
f822d252 2146 done, UNKNOWN if none. */
9c872872 2147#define LOAD_EXTEND_OP(MODE) \
d5b7b3ae
RE		 2148 (TARGET_THUMB ? ZERO_EXTEND : \
2149 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \
f822d252 2150 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : UNKNOWN)))
ff9940b0 2151
35d965d5
RS		 2152/* Nonzero if access to memory by bytes is slow and undesirable. */
2153#define SLOW_BYTE_ACCESS 0
2154
d5b7b3ae 2155#define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1
f676971a 2156
35d965d5
RS		 2157/* Immediate shift counts are truncated by the output routines (or was it
2158 the assembler?). Shift counts in a register are truncated by ARM. Note
2159 that the native compiler puts too large (> 32) immediate shift counts
2160 into a register and shifts by the register, letting the ARM decide what
2161 to do instead of doing that itself. */
ff9940b0
RE		 2162/* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that
2163 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
2164 On the arm, Y in a register is used modulo 256 for the shift. Only for
d6b4baa4 2165 rotates is modulo 32 used. */
ff9940b0 2166/* #define SHIFT_COUNT_TRUNCATED 1 */
35d965d5 2167
35d965d5 2168/* All integers have the same format so truncation is easy. */
d5b7b3ae 2169#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
35d965d5
RS		 2170
2171/* Calling from registers is a massive pain. */
2172#define NO_FUNCTION_CSE 1
2173
35d965d5
RS		 2174/* The machine modes of pointers and functions */
2175#define Pmode SImode
2176#define FUNCTION_MODE Pmode
2177
d5b7b3ae
RE		 2178#define ARM_FRAME_RTX(X) \
2179 ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
3967692c
RE		 2180 || (X) == arg_pointer_rtx)
2181
ff9940b0 2182/* Moves to and from memory are quite expensive */
d5b7b3ae
RE		 2183#define MEMORY_MOVE_COST(M, CLASS, IN) \
2184 (TARGET_ARM ? 10 : \
2185 ((GET_MODE_SIZE (M) < 4 ? 8 : 2 * GET_MODE_SIZE (M)) \
2186 * (CLASS == LO_REGS ? 1 : 2)))
f676971a 2187
ff9940b0
RE		 2188/* Try to generate sequences that don't involve branches, we can then use
2189 conditional instructions */
d5b7b3ae
RE		 2190#define BRANCH_COST \
2191 (TARGET_ARM ? 4 : (optimize > 1 ? 1 : 0))
7a801826
RE		 2192\f
2193/* Position Independent Code. */
2194/* We decide which register to use based on the compilation options and
2195 the assembler in use; this is more general than the APCS restriction of
2196 using sb (r9) all the time. */
2197extern int arm_pic_register;
2198
2199/* The register number of the register used to address a table of static
2200 data addresses in memory. */
2201#define PIC_OFFSET_TABLE_REGNUM arm_pic_register
2202
f5a1b0d2
NC		 2203/* We can't directly access anything that contains a symbol,
2204 nor can we indirect via the constant pool. */
82e9d970 2205#define LEGITIMATE_PIC_OPERAND_P(X) \
1575c31e
JD		 2206 (!(symbol_mentioned_p (X) \
2207 || label_mentioned_p (X) \
2208 || (GET_CODE (X) == SYMBOL_REF \
2209 && CONSTANT_POOL_ADDRESS_P (X) \
2210 && (symbol_mentioned_p (get_pool_constant (X)) \
2211 || label_mentioned_p (get_pool_constant (X))))))
2212
13bd191d
PB		 2213/* We need to know when we are making a constant pool; this determines
2214 whether data needs to be in the GOT or can be referenced via a GOT
2215 offset. */
2216extern int making_const_table;
82e9d970 2217\f
c27ba912 2218/* Handle pragmas for compatibility with Intel's compilers. */
c58b209a
NB		 2219#define REGISTER_TARGET_PRAGMAS() do { \
2220 c_register_pragma (0, "long_calls", arm_pr_long_calls); \
2221 c_register_pragma (0, "no_long_calls", arm_pr_no_long_calls); \
2222 c_register_pragma (0, "long_calls_off", arm_pr_long_calls_off); \
8b97c5f8
ZW		 2223} while (0)
2224
d6b4baa4 2225/* Condition code information. */
ff9940b0 2226/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
a5381466 2227 return the mode to be used for the comparison. */
d5b7b3ae
RE		 2228
2229#define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y)
ff9940b0 2230
880873be
RE		 2231#define REVERSIBLE_CC_MODE(MODE) 1
2232
2233#define REVERSE_CONDITION(CODE,MODE) \
2234 (((MODE) == CCFPmode || (MODE) == CCFPEmode) \
2235 ? reverse_condition_maybe_unordered (code) \
2236 : reverse_condition (code))
008cf58a 2237
62b10bbc
NC		 2238#define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \
2239 do \
2240 { \
2241 if (GET_CODE (OP1) == CONST_INT \
2242 && ! (const_ok_for_arm (INTVAL (OP1)) \
2243 || (const_ok_for_arm (- INTVAL (OP1))))) \
2244 { \
2245 rtx const_op = OP1; \
2246 CODE = arm_canonicalize_comparison ((CODE), &const_op); \
2247 OP1 = const_op; \
2248 } \
2249 } \
2250 while (0)
62dd06ea 2251
7dba8395
RH		 2252/* The arm5 clz instruction returns 32. */
2253#define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
35d965d5 2254\f
d5b7b3ae
RE		 2255#undef ASM_APP_OFF
2256#define ASM_APP_OFF (TARGET_THUMB ? "\t.code\t16\n" : "")
35d965d5 2257
35d965d5 2258/* Output a push or a pop instruction (only used when profiling). */
d5b7b3ae 2259#define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \
8a81cc45
RE		 2260 do \
2261 { \
2262 if (TARGET_ARM) \
2263 asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", \
2264 STACK_POINTER_REGNUM, REGNO); \
2265 else \
2266 asm_fprintf (STREAM, "\tpush {%r}\n", REGNO); \
2267 } while (0)
d5b7b3ae
RE		 2268
2269
2270#define ASM_OUTPUT_REG_POP(STREAM, REGNO) \
8a81cc45
RE		 2271 do \
2272 { \
2273 if (TARGET_ARM) \
2274 asm_fprintf (STREAM, "\tldmfd\t%r!,{%r}\n", \
2275 STACK_POINTER_REGNUM, REGNO); \
2276 else \
2277 asm_fprintf (STREAM, "\tpop {%r}\n", REGNO); \
2278 } while (0)
d5b7b3ae
RE		 2279
2280/* This is how to output a label which precedes a jumptable. Since
2281 Thumb instructions are 2 bytes, we may need explicit alignment here. */
be393ecf 2282#undef ASM_OUTPUT_CASE_LABEL
d5b7b3ae
RE		 2283#define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, JUMPTABLE) \
2284 do \
2285 { \
2286 if (TARGET_THUMB) \
2287 ASM_OUTPUT_ALIGN (FILE, 2); \
8a81cc45 2288 (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \
d5b7b3ae
RE		 2289 } \
2290 while (0)
35d965d5 2291
6cfc7210
NC		 2292#define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \
2293 do \
2294 { \
d5b7b3ae
RE		 2295 if (TARGET_THUMB) \
2296 { \
9b66ebb1
PB		 2297 if (is_called_in_ARM_mode (DECL) \
2298 || current_function_is_thunk) \
d5b7b3ae
RE		 2299 fprintf (STREAM, "\t.code 32\n") ; \
2300 else \
9b66ebb1 2301 fprintf (STREAM, "\t.code 16\n\t.thumb_func\n") ; \
d5b7b3ae 2302 } \
6cfc7210 2303 if (TARGET_POKE_FUNCTION_NAME) \
6354dc9b 2304 arm_poke_function_name (STREAM, (char *) NAME); \
6cfc7210
NC		 2305 } \
2306 while (0)
35d965d5 2307
d5b7b3ae
RE		 2308/* For aliases of functions we use .thumb_set instead. */
2309#define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \
2310 do \
2311 { \
91ea4f8d
KG		 2312 const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \
2313 const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \
d5b7b3ae
RE		 2314 \
2315 if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \
2316 { \
2317 fprintf (FILE, "\t.thumb_set "); \
2318 assemble_name (FILE, LABEL1); \
2319 fprintf (FILE, ","); \
2320 assemble_name (FILE, LABEL2); \
2321 fprintf (FILE, "\n"); \
2322 } \
2323 else \
2324 ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \
2325 } \
2326 while (0)
2327
fdc2d3b0
NC		 2328#ifdef HAVE_GAS_MAX_SKIP_P2ALIGN
2329/* To support -falign-* switches we need to use .p2align so
2330 that alignment directives in code sections will be padded
2331 with no-op instructions, rather than zeroes. */
5a9335ef 2332#define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE, LOG, MAX_SKIP) \
fdc2d3b0
NC		 2333 if ((LOG) != 0) \
2334 { \
2335 if ((MAX_SKIP) == 0) \
5a9335ef 2336 fprintf ((FILE), "\t.p2align %d\n", (int) (LOG)); \
fdc2d3b0
NC		 2337 else \
2338 fprintf ((FILE), "\t.p2align %d,,%d\n", \
5a9335ef 2339 (int) (LOG), (int) (MAX_SKIP)); \
fdc2d3b0
NC		 2340 }
2341#endif
35d965d5 2342\f
35d965d5 2343/* Only perform branch elimination (by making instructions conditional) if
72ac76be 2344 we're optimizing. Otherwise it's of no use anyway. */
d5b7b3ae
RE		 2345#define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2346 if (TARGET_ARM && optimize) \
2347 arm_final_prescan_insn (INSN); \
2348 else if (TARGET_THUMB) \
2349 thumb_final_prescan_insn (INSN)
35d965d5 2350
7bc7696c 2351#define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
d5b7b3ae
RE		 2352 (CODE == '@' || CODE == '|' \
2353 || (TARGET_ARM && (CODE == '?')) \
2354 || (TARGET_THUMB && (CODE == '_')))
6cfc7210 2355
7bc7696c 2356/* Output an operand of an instruction. */
35d965d5 2357#define PRINT_OPERAND(STREAM, X, CODE) \
7bc7696c
RE		 2358 arm_print_operand (STREAM, X, CODE)
2359
7b8b8ade
NC		 2360#define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \
2361 (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \
30cf4896
KG		 2362 : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\
2363 ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \
2364 ? ((~ (unsigned HOST_WIDE_INT) 0) \
2365 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \
7bc7696c 2366 : 0))))
35d965d5
RS		 2367
2368/* Output the address of an operand. */
3cd45774
RE		 2369#define ARM_PRINT_OPERAND_ADDRESS(STREAM, X) \
2370{ \
2371 int is_minus = GET_CODE (X) == MINUS; \
2372 \
2373 if (GET_CODE (X) == REG) \
2374 asm_fprintf (STREAM, "[%r, #0]", REGNO (X)); \
2375 else if (GET_CODE (X) == PLUS || is_minus) \
2376 { \
2377 rtx base = XEXP (X, 0); \
2378 rtx index = XEXP (X, 1); \
2379 HOST_WIDE_INT offset = 0; \
2380 if (GET_CODE (base) != REG) \
2381 { \
d6b4baa4
KH		 2382 /* Ensure that BASE is a register. */ \
2383 /* (one of them must be). */ \
3cd45774
RE		 2384 rtx temp = base; \
2385 base = index; \
2386 index = temp; \
2387 } \
2388 switch (GET_CODE (index)) \
2389 { \
2390 case CONST_INT: \
2391 offset = INTVAL (index); \
2392 if (is_minus) \
2393 offset = -offset; \
c53dddc2 2394 asm_fprintf (STREAM, "[%r, #%wd]", \
3cd45774
RE		 2395 REGNO (base), offset); \
2396 break; \
2397 \
2398 case REG: \
2399 asm_fprintf (STREAM, "[%r, %s%r]", \
2400 REGNO (base), is_minus ? "-" : "", \
2401 REGNO (index)); \
2402 break; \
2403 \
2404 case MULT: \
2405 case ASHIFTRT: \
2406 case LSHIFTRT: \
2407 case ASHIFT: \
2408 case ROTATERT: \
2409 { \
2410 asm_fprintf (STREAM, "[%r, %s%r", \
2411 REGNO (base), is_minus ? "-" : "", \
2412 REGNO (XEXP (index, 0))); \
2413 arm_print_operand (STREAM, index, 'S'); \
2414 fputs ("]", STREAM); \
2415 break; \
2416 } \
2417 \
2418 default: \
e6d29d15 2419 gcc_unreachable (); \
3cd45774
RE		 2420 } \
2421 } \
2422 else if (GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC \
2423 || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC) \
2424 { \
2425 extern enum machine_mode output_memory_reference_mode; \
2426 \
e6d29d15 2427 gcc_assert (GET_CODE (XEXP (X, 0)) == REG); \
3cd45774
RE		 2428 \
2429 if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \
2430 asm_fprintf (STREAM, "[%r, #%s%d]!", \
2431 REGNO (XEXP (X, 0)), \
2432 GET_CODE (X) == PRE_DEC ? "-" : "", \
2433 GET_MODE_SIZE (output_memory_reference_mode)); \
2434 else \
2435 asm_fprintf (STREAM, "[%r], #%s%d", \
2436 REGNO (XEXP (X, 0)), \
2437 GET_CODE (X) == POST_DEC ? "-" : "", \
2438 GET_MODE_SIZE (output_memory_reference_mode)); \
2439 } \
2440 else if (GET_CODE (X) == PRE_MODIFY) \
2441 { \
2442 asm_fprintf (STREAM, "[%r, ", REGNO (XEXP (X, 0))); \
2443 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \
c53dddc2 2444 asm_fprintf (STREAM, "#%wd]!", \
3cd45774
RE		 2445 INTVAL (XEXP (XEXP (X, 1), 1))); \
2446 else \
2447 asm_fprintf (STREAM, "%r]!", \
2448 REGNO (XEXP (XEXP (X, 1), 1))); \
2449 } \
2450 else if (GET_CODE (X) == POST_MODIFY) \
2451 { \
2452 asm_fprintf (STREAM, "[%r], ", REGNO (XEXP (X, 0))); \
2453 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \
c53dddc2 2454 asm_fprintf (STREAM, "#%wd", \
3cd45774
RE		 2455 INTVAL (XEXP (XEXP (X, 1), 1))); \
2456 else \
2457 asm_fprintf (STREAM, "%r", \
2458 REGNO (XEXP (XEXP (X, 1), 1))); \
2459 } \
2460 else output_addr_const (STREAM, X); \
35d965d5 2461}
62dd06ea 2462
d5b7b3ae
RE		 2463#define THUMB_PRINT_OPERAND_ADDRESS(STREAM, X) \
2464{ \
2465 if (GET_CODE (X) == REG) \
2466 asm_fprintf (STREAM, "[%r]", REGNO (X)); \
2467 else if (GET_CODE (X) == POST_INC) \
2468 asm_fprintf (STREAM, "%r!", REGNO (XEXP (X, 0))); \
2469 else if (GET_CODE (X) == PLUS) \
2470 { \
e6d29d15 2471 gcc_assert (GET_CODE (XEXP (X, 0)) == REG); \
d5b7b3ae 2472 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
659bdc68 2473 asm_fprintf (STREAM, "[%r, #%wd]", \
d5b7b3ae 2474 REGNO (XEXP (X, 0)), \
659bdc68 2475 INTVAL (XEXP (X, 1))); \
d5b7b3ae
RE		 2476 else \
2477 asm_fprintf (STREAM, "[%r, %r]", \
2478 REGNO (XEXP (X, 0)), \
2479 REGNO (XEXP (X, 1))); \
2480 } \
2481 else \
2482 output_addr_const (STREAM, X); \
2483}
2484
2485#define PRINT_OPERAND_ADDRESS(STREAM, X) \
2486 if (TARGET_ARM) \
2487 ARM_PRINT_OPERAND_ADDRESS (STREAM, X) \
2488 else \
2489 THUMB_PRINT_OPERAND_ADDRESS (STREAM, X)
5a9335ef
NC		 2490
2491#define OUTPUT_ADDR_CONST_EXTRA(FILE, X, FAIL) \
2492 if (GET_CODE (X) != CONST_VECTOR \
2493 || ! arm_emit_vector_const (FILE, X)) \
2494 goto FAIL;
2495
6a5d7526
MS		 2496/* A C expression whose value is RTL representing the value of the return
2497 address for the frame COUNT steps up from the current frame. */
2498
d5b7b3ae
RE		 2499#define RETURN_ADDR_RTX(COUNT, FRAME) \
2500 arm_return_addr (COUNT, FRAME)
2501
f676971a 2502/* Mask of the bits in the PC that contain the real return address
d5b7b3ae
RE		 2503 when running in 26-bit mode. */
2504#define RETURN_ADDR_MASK26 (0x03fffffc)
6a5d7526 2505
2c849145
JM		 2506/* Pick up the return address upon entry to a procedure. Used for
2507 dwarf2 unwind information. This also enables the table driven
2508 mechanism. */
2c849145
JM		 2509#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM)
2510#define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM)
2511
39950dff
MS		 2512/* Used to mask out junk bits from the return address, such as
2513 processor state, interrupt status, condition codes and the like. */
2514#define MASK_RETURN_ADDR \
2515 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \
2516 in 26 bit mode, the condition codes must be masked out of the \
2517 return address. This does not apply to ARM6 and later processors \
2518 when running in 32 bit mode. */ \
61f0ccff
RE		 2519 ((arm_arch4 || TARGET_THUMB) \
2520 ? (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \
fcd53748 2521 : arm_gen_return_addr_mask ())
d5b7b3ae
RE		 2522
2523\f
5a9335ef
NC		 2524enum arm_builtins
2525{
2526 ARM_BUILTIN_GETWCX,
2527 ARM_BUILTIN_SETWCX,
2528
2529 ARM_BUILTIN_WZERO,
2530
2531 ARM_BUILTIN_WAVG2BR,
2532 ARM_BUILTIN_WAVG2HR,
2533 ARM_BUILTIN_WAVG2B,
2534 ARM_BUILTIN_WAVG2H,
2535
2536 ARM_BUILTIN_WACCB,
2537 ARM_BUILTIN_WACCH,
2538 ARM_BUILTIN_WACCW,
2539
2540 ARM_BUILTIN_WMACS,
2541 ARM_BUILTIN_WMACSZ,
2542 ARM_BUILTIN_WMACU,
2543 ARM_BUILTIN_WMACUZ,
2544
2545 ARM_BUILTIN_WSADB,
2546 ARM_BUILTIN_WSADBZ,
2547 ARM_BUILTIN_WSADH,
2548 ARM_BUILTIN_WSADHZ,
2549
2550 ARM_BUILTIN_WALIGN,
2551
2552 ARM_BUILTIN_TMIA,
2553 ARM_BUILTIN_TMIAPH,
2554 ARM_BUILTIN_TMIABB,
2555 ARM_BUILTIN_TMIABT,
2556 ARM_BUILTIN_TMIATB,
2557 ARM_BUILTIN_TMIATT,
2558
2559 ARM_BUILTIN_TMOVMSKB,
2560 ARM_BUILTIN_TMOVMSKH,
2561 ARM_BUILTIN_TMOVMSKW,
2562
2563 ARM_BUILTIN_TBCSTB,
2564 ARM_BUILTIN_TBCSTH,
2565 ARM_BUILTIN_TBCSTW,
2566
2567 ARM_BUILTIN_WMADDS,
2568 ARM_BUILTIN_WMADDU,
2569
2570 ARM_BUILTIN_WPACKHSS,
2571 ARM_BUILTIN_WPACKWSS,
2572 ARM_BUILTIN_WPACKDSS,
2573 ARM_BUILTIN_WPACKHUS,
2574 ARM_BUILTIN_WPACKWUS,
2575 ARM_BUILTIN_WPACKDUS,
2576
2577 ARM_BUILTIN_WADDB,
2578 ARM_BUILTIN_WADDH,
2579 ARM_BUILTIN_WADDW,
2580 ARM_BUILTIN_WADDSSB,
2581 ARM_BUILTIN_WADDSSH,
2582 ARM_BUILTIN_WADDSSW,
2583 ARM_BUILTIN_WADDUSB,
2584 ARM_BUILTIN_WADDUSH,
2585 ARM_BUILTIN_WADDUSW,
2586 ARM_BUILTIN_WSUBB,
2587 ARM_BUILTIN_WSUBH,
2588 ARM_BUILTIN_WSUBW,
2589 ARM_BUILTIN_WSUBSSB,
2590 ARM_BUILTIN_WSUBSSH,
2591 ARM_BUILTIN_WSUBSSW,
2592 ARM_BUILTIN_WSUBUSB,
2593 ARM_BUILTIN_WSUBUSH,
2594 ARM_BUILTIN_WSUBUSW,
2595
2596 ARM_BUILTIN_WAND,
2597 ARM_BUILTIN_WANDN,
2598 ARM_BUILTIN_WOR,
2599 ARM_BUILTIN_WXOR,
2600
2601 ARM_BUILTIN_WCMPEQB,
2602 ARM_BUILTIN_WCMPEQH,
2603 ARM_BUILTIN_WCMPEQW,
2604 ARM_BUILTIN_WCMPGTUB,
2605 ARM_BUILTIN_WCMPGTUH,
2606 ARM_BUILTIN_WCMPGTUW,
2607 ARM_BUILTIN_WCMPGTSB,
2608 ARM_BUILTIN_WCMPGTSH,
2609 ARM_BUILTIN_WCMPGTSW,
2610
2611 ARM_BUILTIN_TEXTRMSB,
2612 ARM_BUILTIN_TEXTRMSH,
2613 ARM_BUILTIN_TEXTRMSW,
2614 ARM_BUILTIN_TEXTRMUB,
2615 ARM_BUILTIN_TEXTRMUH,
2616 ARM_BUILTIN_TEXTRMUW,
2617 ARM_BUILTIN_TINSRB,
2618 ARM_BUILTIN_TINSRH,
2619 ARM_BUILTIN_TINSRW,
2620
2621 ARM_BUILTIN_WMAXSW,
2622 ARM_BUILTIN_WMAXSH,
2623 ARM_BUILTIN_WMAXSB,
2624 ARM_BUILTIN_WMAXUW,
2625 ARM_BUILTIN_WMAXUH,
2626 ARM_BUILTIN_WMAXUB,
2627 ARM_BUILTIN_WMINSW,
2628 ARM_BUILTIN_WMINSH,
2629 ARM_BUILTIN_WMINSB,
2630 ARM_BUILTIN_WMINUW,
2631 ARM_BUILTIN_WMINUH,
2632 ARM_BUILTIN_WMINUB,
2633
f07a6b21
BE		 2634 ARM_BUILTIN_WMULUM,
2635 ARM_BUILTIN_WMULSM,
5a9335ef
NC		 2636 ARM_BUILTIN_WMULUL,
2637
2638 ARM_BUILTIN_PSADBH,
2639 ARM_BUILTIN_WSHUFH,
2640
2641 ARM_BUILTIN_WSLLH,
2642 ARM_BUILTIN_WSLLW,
2643 ARM_BUILTIN_WSLLD,
2644 ARM_BUILTIN_WSRAH,
2645 ARM_BUILTIN_WSRAW,
2646 ARM_BUILTIN_WSRAD,
2647 ARM_BUILTIN_WSRLH,
2648 ARM_BUILTIN_WSRLW,
2649 ARM_BUILTIN_WSRLD,
2650 ARM_BUILTIN_WRORH,
2651 ARM_BUILTIN_WRORW,
2652 ARM_BUILTIN_WRORD,
2653 ARM_BUILTIN_WSLLHI,
2654 ARM_BUILTIN_WSLLWI,
2655 ARM_BUILTIN_WSLLDI,
2656 ARM_BUILTIN_WSRAHI,
2657 ARM_BUILTIN_WSRAWI,
2658 ARM_BUILTIN_WSRADI,
2659 ARM_BUILTIN_WSRLHI,
2660 ARM_BUILTIN_WSRLWI,
2661 ARM_BUILTIN_WSRLDI,
2662 ARM_BUILTIN_WRORHI,
2663 ARM_BUILTIN_WRORWI,
2664 ARM_BUILTIN_WRORDI,
2665
2666 ARM_BUILTIN_WUNPCKIHB,
2667 ARM_BUILTIN_WUNPCKIHH,
2668 ARM_BUILTIN_WUNPCKIHW,
2669 ARM_BUILTIN_WUNPCKILB,
2670 ARM_BUILTIN_WUNPCKILH,
2671 ARM_BUILTIN_WUNPCKILW,
2672
2673 ARM_BUILTIN_WUNPCKEHSB,
2674 ARM_BUILTIN_WUNPCKEHSH,
2675 ARM_BUILTIN_WUNPCKEHSW,
2676 ARM_BUILTIN_WUNPCKEHUB,
2677 ARM_BUILTIN_WUNPCKEHUH,
2678 ARM_BUILTIN_WUNPCKEHUW,
2679 ARM_BUILTIN_WUNPCKELSB,
2680 ARM_BUILTIN_WUNPCKELSH,
2681 ARM_BUILTIN_WUNPCKELSW,
2682 ARM_BUILTIN_WUNPCKELUB,
2683 ARM_BUILTIN_WUNPCKELUH,
2684 ARM_BUILTIN_WUNPCKELUW,
2685
2686 ARM_BUILTIN_MAX
2687};
88657302 2688#endif /* ! GCC_ARM_H */
Mirror of https://gcc.gnu.org/git/gcc.git