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f5a1b0d2 | 1 | /* Definitions of target machine for GNU compiler, for ARM. |
8d9254fc | 2 | Copyright (C) 1991-2020 Free Software Foundation, Inc. |
35d965d5 | 3 | Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl) |
8b109b37 | 4 | and Martin Simmons (@harleqn.co.uk). |
949d79eb | 5 | More major hacks by Richard Earnshaw (rearnsha@arm.com) |
6cfc7210 NC |
6 | Minor hacks by Nick Clifton (nickc@cygnus.com) |
7 | ||
4f448245 | 8 | This file is part of GCC. |
35d965d5 | 9 | |
4f448245 NC |
10 | GCC is free software; you can redistribute it and/or modify it |
11 | under the terms of the GNU General Public License as published | |
2f83c7d6 | 12 | by the Free Software Foundation; either version 3, or (at your |
4f448245 | 13 | option) any later version. |
35d965d5 | 14 | |
4f448245 NC |
15 | GCC is distributed in the hope that it will be useful, but WITHOUT |
16 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
17 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
18 | License for more details. | |
35d965d5 | 19 | |
999db125 GJL |
20 | Under Section 7 of GPL version 3, you are granted additional |
21 | permissions described in the GCC Runtime Library Exception, version | |
22 | 3.1, as published by the Free Software Foundation. | |
23 | ||
c7eca9fe GJL |
24 | You should have received a copy of the GNU General Public License and |
25 | a copy of the GCC Runtime Library Exception along with this program; | |
26 | see the files COPYING3 and COPYING.RUNTIME respectively. If not, see | |
2f83c7d6 | 27 | <http://www.gnu.org/licenses/>. */ |
35d965d5 | 28 | |
88657302 RH |
29 | #ifndef GCC_ARM_H |
30 | #define GCC_ARM_H | |
b355a481 | 31 | |
ef4bddc2 | 32 | /* We can't use machine_mode inside a generator file because it |
46107b99 RE |
33 | hasn't been created yet; we shouldn't be using any code that |
34 | needs the real definition though, so this ought to be safe. */ | |
35 | #ifdef GENERATOR_FILE | |
36 | #define MACHMODE int | |
37 | #else | |
38 | #include "insn-modes.h" | |
2c0122c9 | 39 | #define MACHMODE machine_mode |
46107b99 RE |
40 | #endif |
41 | ||
9403b7f7 RS |
42 | #include "config/vxworks-dummy.h" |
43 | ||
35fd3193 | 44 | /* The architecture define. */ |
78011587 PB |
45 | extern char arm_arch_name[]; |
46 | ||
e6471be6 | 47 | /* Target CPU builtins. */ |
7049e4eb | 48 | #define TARGET_CPU_CPP_BUILTINS() arm_cpu_cpp_builtins (pfile) |
e6471be6 | 49 | |
b4c522fa IB |
50 | /* Target CPU versions for D. */ |
51 | #define TARGET_D_CPU_VERSIONS arm_d_target_versions | |
52 | ||
ad7be009 | 53 | #include "config/arm/arm-opts.h" |
9b66ebb1 PB |
54 | |
55 | /* The processor for which instructions should be scheduled. */ | |
56 | extern enum processor_type arm_tune; | |
57 | ||
d5b7b3ae | 58 | typedef enum arm_cond_code |
89c7ca52 RE |
59 | { |
60 | ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC, | |
61 | ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV | |
d5b7b3ae RE |
62 | } |
63 | arm_cc; | |
6cfc7210 | 64 | |
d5b7b3ae | 65 | extern arm_cc arm_current_cc; |
ff9940b0 | 66 | |
d5b7b3ae | 67 | #define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1)) |
89c7ca52 | 68 | |
cd794ed4 | 69 | /* The maximum number of instructions that is beneficial to |
b24a2ce5 GY |
70 | conditionally execute. */ |
71 | #undef MAX_CONDITIONAL_EXECUTE | |
72 | #define MAX_CONDITIONAL_EXECUTE arm_max_conditional_execute () | |
73 | ||
6cfc7210 NC |
74 | extern int arm_target_label; |
75 | extern int arm_ccfsm_state; | |
e2500fed | 76 | extern GTY(()) rtx arm_target_insn; |
b76c3c4b PB |
77 | /* Callback to output language specific object attributes. */ |
78 | extern void (*arm_lang_output_object_attributes_hook)(void); | |
5774b1fa JG |
79 | |
80 | /* This type is the user-visible __fp16. We need it in a few places in | |
81 | the backend. Defined in arm-builtins.c. */ | |
82 | extern tree arm_fp16_type_node; | |
83 | ||
2e87b2f4 SMW |
84 | /* This type is the user-visible __bf16. We need it in a few places in |
85 | the backend. Defined in arm-builtins.c. */ | |
86 | extern tree arm_bf16_type_node; | |
87 | extern tree arm_bf16_ptr_type_node; | |
88 | ||
35d965d5 | 89 | \f |
5742588d | 90 | #undef CPP_SPEC |
78011587 | 91 | #define CPP_SPEC "%(subtarget_cpp_spec) \ |
5e1b4d5a JM |
92 | %{mfloat-abi=soft:%{mfloat-abi=hard: \ |
93 | %e-mfloat-abi=soft and -mfloat-abi=hard may not be used together}} \ | |
e6471be6 NB |
94 | %{mbig-endian:%{mlittle-endian: \ |
95 | %e-mbig-endian and -mlittle-endian may not be used together}}" | |
7a801826 | 96 | |
be393ecf | 97 | #ifndef CC1_SPEC |
dfa08768 | 98 | #define CC1_SPEC "" |
be393ecf | 99 | #endif |
7a801826 RE |
100 | |
101 | /* This macro defines names of additional specifications to put in the specs | |
102 | that can be used in various specifications like CC1_SPEC. Its definition | |
103 | is an initializer with a subgrouping for each command option. | |
104 | ||
105 | Each subgrouping contains a string constant, that defines the | |
4f448245 | 106 | specification name, and a string constant that used by the GCC driver |
7a801826 RE |
107 | program. |
108 | ||
109 | Do not define this macro if it does not need to do anything. */ | |
110 | #define EXTRA_SPECS \ | |
38fc909b | 111 | { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \ |
54e73f88 | 112 | { "asm_cpu_spec", ASM_CPU_SPEC }, \ |
7a801826 RE |
113 | SUBTARGET_EXTRA_SPECS |
114 | ||
914a3b8c | 115 | #ifndef SUBTARGET_EXTRA_SPECS |
7a801826 | 116 | #define SUBTARGET_EXTRA_SPECS |
914a3b8c DM |
117 | #endif |
118 | ||
6cfc7210 | 119 | #ifndef SUBTARGET_CPP_SPEC |
38fc909b | 120 | #define SUBTARGET_CPP_SPEC "" |
6cfc7210 | 121 | #endif |
35d965d5 | 122 | \f |
1a7ae4ce | 123 | /* Tree Target Specification. */ |
08793a38 CB |
124 | #define TARGET_ARM_P(flags) (!TARGET_THUMB_P (flags)) |
125 | #define TARGET_THUMB1_P(flags) (TARGET_THUMB_P (flags) && !arm_arch_thumb2) | |
126 | #define TARGET_THUMB2_P(flags) (TARGET_THUMB_P (flags) && arm_arch_thumb2) | |
5797378a | 127 | #define TARGET_32BIT_P(flags) (TARGET_ARM_P (flags) || TARGET_THUMB2_P (flags)) |
08793a38 | 128 | |
35d965d5 | 129 | /* Run-time Target Specification. */ |
48528842 RR |
130 | /* Use hardware floating point instructions. -mgeneral-regs-only prevents |
131 | the use of floating point instructions and registers but does not prevent | |
132 | emission of floating point pcs attributes. */ | |
133 | #define TARGET_HARD_FLOAT_SUB (arm_float_abi != ARM_FLOAT_ABI_SOFT \ | |
2e17e319 | 134 | && bitmap_bit_p (arm_active_target.isa, \ |
ec5e6814 TP |
135 | isa_bit_vfpv2) \ |
136 | && TARGET_32BIT) | |
48528842 RR |
137 | |
138 | #define TARGET_HARD_FLOAT (TARGET_HARD_FLOAT_SUB \ | |
139 | && !TARGET_GENERAL_REGS_ONLY) | |
140 | ||
141 | #define TARGET_SOFT_FLOAT (!TARGET_HARD_FLOAT_SUB) | |
2e17e319 RE |
142 | /* User has permitted use of FP instructions, if they exist for this |
143 | target. */ | |
144 | #define TARGET_MAYBE_HARD_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT) | |
72cdc543 PB |
145 | /* Use hardware floating point calling convention. */ |
146 | #define TARGET_HARD_FLOAT_ABI (arm_float_abi == ARM_FLOAT_ABI_HARD) | |
5a9335ef | 147 | #define TARGET_IWMMXT (arm_arch_iwmmxt) |
8fd03515 | 148 | #define TARGET_IWMMXT2 (arm_arch_iwmmxt2) |
48528842 RR |
149 | #define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_32BIT \ |
150 | && !TARGET_GENERAL_REGS_ONLY) | |
151 | #define TARGET_REALLY_IWMMXT2 (TARGET_IWMMXT2 && TARGET_32BIT \ | |
152 | && !TARGET_GENERAL_REGS_ONLY) | |
5b3e6663 | 153 | #define TARGET_IWMMXT_ABI (TARGET_32BIT && arm_abi == ARM_ABI_IWMMXT) |
d5b7b3ae RE |
154 | #define TARGET_ARM (! TARGET_THUMB) |
155 | #define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */ | |
a3038e19 | 156 | #define TARGET_BACKTRACE (crtl->is_leaf \ |
c54c7322 RS |
157 | ? TARGET_TPCS_LEAF_FRAME \ |
158 | : TARGET_TPCS_FRAME) | |
b6685939 PB |
159 | #define TARGET_AAPCS_BASED \ |
160 | (arm_abi != ARM_ABI_APCS && arm_abi != ARM_ABI_ATPCS) | |
3ada8e17 | 161 | |
d3585b76 DJ |
162 | #define TARGET_HARD_TP (target_thread_pointer == TP_CP15) |
163 | #define TARGET_SOFT_TP (target_thread_pointer == TP_SOFT) | |
ccdc2164 | 164 | #define TARGET_GNU2_TLS (target_tls_dialect == TLS_GNU2) |
d3585b76 | 165 | |
5b3e6663 PB |
166 | /* Only 16-bit thumb code. */ |
167 | #define TARGET_THUMB1 (TARGET_THUMB && !arm_arch_thumb2) | |
168 | /* Arm or Thumb-2 32-bit code. */ | |
169 | #define TARGET_32BIT (TARGET_ARM || arm_arch_thumb2) | |
170 | /* 32-bit Thumb-2 code. */ | |
171 | #define TARGET_THUMB2 (TARGET_THUMB && arm_arch_thumb2) | |
bf98ec6c PB |
172 | /* Thumb-1 only. */ |
173 | #define TARGET_THUMB1_ONLY (TARGET_THUMB1 && !arm_arch_notm) | |
5b3e6663 | 174 | |
c3f808d3 | 175 | #define TARGET_LDRD (arm_arch5te && ARM_DOUBLEWORD_ALIGN \ |
3383b7fa GY |
176 | && !TARGET_THUMB1) |
177 | ||
582e2e43 KT |
178 | #define TARGET_CRC32 (arm_arch_crc) |
179 | ||
88f77cba | 180 | /* The following two macros concern the ability to execute coprocessor |
302c3d8e PB |
181 | instructions for VFPv3 or NEON. TARGET_VFP3/TARGET_VFPD32 are currently |
182 | only ever tested when we know we are generating for VFP hardware; we need | |
183 | to be more careful with TARGET_NEON as noted below. */ | |
88f77cba | 184 | |
302c3d8e | 185 | /* FPU is has the full VFPv3/NEON register file of 32 D registers. */ |
091df649 | 186 | #define TARGET_VFPD32 (bitmap_bit_p (arm_active_target.isa, isa_bit_fp_d32)) |
302c3d8e PB |
187 | |
188 | /* FPU supports VFPv3 instructions. */ | |
bdb0828f | 189 | #define TARGET_VFP3 (bitmap_bit_p (arm_active_target.isa, isa_bit_vfpv3)) |
302c3d8e | 190 | |
2f6403f1 | 191 | /* FPU supports FPv5 instructions. */ |
bdb0828f | 192 | #define TARGET_VFP5 (bitmap_bit_p (arm_active_target.isa, isa_bit_fpv5)) |
2f6403f1 | 193 | |
e0dc3601 | 194 | /* FPU only supports VFP single-precision instructions. */ |
091df649 | 195 | #define TARGET_VFP_SINGLE (!TARGET_VFP_DOUBLE) |
e0dc3601 PB |
196 | |
197 | /* FPU supports VFP double-precision instructions. */ | |
091df649 | 198 | #define TARGET_VFP_DOUBLE (bitmap_bit_p (arm_active_target.isa, isa_bit_fp_dbl)) |
e0dc3601 PB |
199 | |
200 | /* FPU supports half-precision floating-point with NEON element load/store. */ | |
00ea1506 | 201 | #define TARGET_NEON_FP16 \ |
091df649 RE |
202 | (bitmap_bit_p (arm_active_target.isa, isa_bit_neon) \ |
203 | && bitmap_bit_p (arm_active_target.isa, isa_bit_fp16conv)) | |
0fd8c3ad | 204 | |
091df649 RE |
205 | /* FPU supports VFP half-precision floating-point conversions. */ |
206 | #define TARGET_FP16 (bitmap_bit_p (arm_active_target.isa, isa_bit_fp16conv)) | |
e0dc3601 | 207 | |
5e0f10a0 JG |
208 | /* FPU supports converting between HFmode and DFmode in a single hardware |
209 | step. */ | |
210 | #define TARGET_FP16_TO_DOUBLE \ | |
f65112f6 | 211 | (TARGET_HARD_FLOAT && TARGET_FP16 && TARGET_VFP5 && TARGET_VFP_DOUBLE) |
5e0f10a0 | 212 | |
9e94a7fc | 213 | /* FPU supports fused-multiply-add operations. */ |
bdb0828f | 214 | #define TARGET_FMA (bitmap_bit_p (arm_active_target.isa, isa_bit_vfpv4)) |
9e94a7fc | 215 | |
595fefee | 216 | /* FPU supports Crypto extensions. */ |
091df649 | 217 | #define TARGET_CRYPTO (bitmap_bit_p (arm_active_target.isa, isa_bit_crypto)) |
595fefee | 218 | |
88f77cba JB |
219 | /* FPU supports Neon instructions. The setting of this macro gets |
220 | revealed via __ARM_NEON__ so we add extra guards upon TARGET_32BIT | |
221 | and TARGET_HARD_FLOAT to ensure that NEON instructions are | |
222 | available. */ | |
cafd2e45 | 223 | #define TARGET_NEON \ |
00ea1506 | 224 | (TARGET_32BIT && TARGET_HARD_FLOAT \ |
091df649 | 225 | && bitmap_bit_p (arm_active_target.isa, isa_bit_neon)) |
cafd2e45 | 226 | |
252e03b5 MW |
227 | /* FPU supports ARMv8.1 Adv.SIMD extensions. */ |
228 | #define TARGET_NEON_RDMA (TARGET_NEON && arm_arch8_1) | |
229 | ||
82896b22 | 230 | /* Supports the Dot Product AdvSIMD extensions. */ |
427071d4 | 231 | #define TARGET_DOTPROD (TARGET_NEON && TARGET_VFP5 \ |
ba09dd21 | 232 | && bitmap_bit_p (arm_active_target.isa, \ |
82896b22 TC |
233 | isa_bit_dotprod) \ |
234 | && arm_arch8_2) | |
ba09dd21 | 235 | |
c2b7062d TC |
236 | /* Supports the Armv8.3-a Complex number AdvSIMD extensions. */ |
237 | #define TARGET_COMPLEX (TARGET_NEON && arm_arch8_3) | |
238 | ||
06e95715 KT |
239 | /* FPU supports the floating point FP16 instructions for ARMv8.2-A |
240 | and later. */ | |
4040b89a | 241 | #define TARGET_VFP_FP16INST \ |
c8d61ab8 | 242 | (TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP5 && arm_fp16_inst) |
4040b89a | 243 | |
06e95715 KT |
244 | /* Target supports the floating point FP16 instructions from ARMv8.2-A |
245 | and later. */ | |
246 | #define TARGET_FP16FML (TARGET_NEON \ | |
247 | && bitmap_bit_p (arm_active_target.isa, \ | |
248 | isa_bit_fp16fml) \ | |
249 | && arm_arch8_2) | |
250 | ||
4040b89a MW |
251 | /* FPU supports the AdvSIMD FP16 instructions for ARMv8.2 and later. */ |
252 | #define TARGET_NEON_FP16INST (TARGET_VFP_FP16INST && TARGET_NEON_RDMA) | |
253 | ||
f782b667 DZ |
254 | /* FPU supports 8-bit Integer Matrix Multiply (I8MM) AdvSIMD extensions. */ |
255 | #define TARGET_I8MM (TARGET_NEON && arm_arch8_2 && arm_arch_i8mm) | |
256 | ||
257 | /* FPU supports Brain half-precision floating-point (BFloat16) extension. */ | |
258 | #define TARGET_BF16_FP (TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP5 \ | |
259 | && arm_arch8_2 && arm_arch_bf16) | |
260 | #define TARGET_BF16_SIMD (TARGET_NEON && TARGET_VFP5 \ | |
261 | && arm_arch8_2 && arm_arch_bf16) | |
262 | ||
9e94a7fc | 263 | /* Q-bit is present. */ |
c8b6aa7c | 264 | #define TARGET_ARM_QBIT \ |
c3f808d3 | 265 | (TARGET_32BIT && arm_arch5te && (arm_arch_notm || arm_arch7)) |
9e94a7fc | 266 | /* Saturation operation, e.g. SSAT. */ |
c8b6aa7c CB |
267 | #define TARGET_ARM_SAT \ |
268 | (TARGET_32BIT && arm_arch6 && (arm_arch_notm || arm_arch7)) | |
5b3e6663 | 269 | /* "DSP" multiply instructions, eg. SMULxy. */ |
c8b6aa7c | 270 | #define TARGET_DSP_MULTIPLY \ |
c3f808d3 | 271 | (TARGET_32BIT && arm_arch5te && (arm_arch_notm || arm_arch7em)) |
5b3e6663 | 272 | /* Integer SIMD instructions, and extend-accumulate instructions. */ |
c8b6aa7c CB |
273 | #define TARGET_INT_SIMD \ |
274 | (TARGET_32BIT && arm_arch6 && (arm_arch_notm || arm_arch7em)) | |
5b3e6663 | 275 | |
571191af | 276 | /* Should MOVW/MOVT be used in preference to a constant pool. */ |
7ec70105 | 277 | #define TARGET_USE_MOVT \ |
33427b46 | 278 | (TARGET_HAVE_MOVT \ |
02231c13 TG |
279 | && (arm_disable_literal_pool \ |
280 | || (!optimize_size && !current_tune->prefer_constant_pool))) | |
571191af | 281 | |
029e79eb | 282 | /* Nonzero if this chip provides the DMB instruction. */ |
9e2a6301 | 283 | #define TARGET_HAVE_DMB (arm_arch6m || arm_arch7) |
029e79eb MS |
284 | |
285 | /* Nonzero if this chip implements a memory barrier via CP15. */ | |
80651d8e DAG |
286 | #define TARGET_HAVE_DMB_MCR (arm_arch6 && ! TARGET_HAVE_DMB \ |
287 | && ! TARGET_THUMB1) | |
029e79eb MS |
288 | |
289 | /* Nonzero if this chip implements a memory barrier instruction. */ | |
290 | #define TARGET_HAVE_MEMORY_BARRIER (TARGET_HAVE_DMB || TARGET_HAVE_DMB_MCR) | |
291 | ||
292 | /* Nonzero if this chip supports ldrex and strex */ | |
ddb92ab9 TP |
293 | #define TARGET_HAVE_LDREX ((arm_arch6 && TARGET_ARM) \ |
294 | || arm_arch7 \ | |
295 | || (arm_arch8 && !arm_arch_notm)) | |
029e79eb | 296 | |
74a00288 | 297 | /* Nonzero if this chip supports LPAE. */ |
bf634d1c | 298 | #define TARGET_HAVE_LPAE (arm_arch_lpae) |
74a00288 | 299 | |
cfe52743 | 300 | /* Nonzero if this chip supports ldrex{bh} and strex{bh}. */ |
ddb92ab9 TP |
301 | #define TARGET_HAVE_LDREXBH ((arm_arch6k && TARGET_ARM) \ |
302 | || arm_arch7 \ | |
303 | || (arm_arch8 && !arm_arch_notm)) | |
cfe52743 DAG |
304 | |
305 | /* Nonzero if this chip supports ldrexd and strexd. */ | |
c8b6aa7c CB |
306 | #define TARGET_HAVE_LDREXD (((arm_arch6k && TARGET_ARM) \ |
307 | || arm_arch7) && arm_arch_notm) | |
5b3e6663 | 308 | |
5ad29f12 | 309 | /* Nonzero if this chip supports load-acquire and store-release. */ |
ddb92ab9 | 310 | #define TARGET_HAVE_LDACQ (TARGET_ARM_ARCH >= 8) |
d62b809c TP |
311 | |
312 | /* Nonzero if this chip supports LDAEXD and STLEXD. */ | |
313 | #define TARGET_HAVE_LDACQEXD (TARGET_ARM_ARCH >= 8 \ | |
314 | && TARGET_32BIT \ | |
315 | && arm_arch_notm) | |
5ad29f12 | 316 | |
2b9509a3 TP |
317 | /* Nonzero if this chip provides the MOVW and MOVT instructions. */ |
318 | #define TARGET_HAVE_MOVT (arm_arch_thumb2 || arm_arch8) | |
33427b46 | 319 | |
5ce15300 TP |
320 | /* Nonzero if this chip provides the CBZ and CBNZ instructions. */ |
321 | #define TARGET_HAVE_CBZ (arm_arch_thumb2 || arm_arch8) | |
322 | ||
e0e4be48 MI |
323 | /* Nonzero if this chip provides Armv8.1-M Mainline Security extensions |
324 | instructions (most are floating-point related). */ | |
325 | #define TARGET_HAVE_FPCXT_CMSE (arm_arch8_1m_main) | |
326 | ||
63c8f7d6 SP |
327 | #define TARGET_HAVE_MVE (arm_float_abi != ARM_FLOAT_ABI_SOFT \ |
328 | && bitmap_bit_p (arm_active_target.isa, \ | |
329 | isa_bit_mve) \ | |
330 | && !TARGET_GENERAL_REGS_ONLY) | |
7b4c373b | 331 | |
63c8f7d6 SP |
332 | #define TARGET_HAVE_MVE_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT \ |
333 | && bitmap_bit_p (arm_active_target.isa, \ | |
334 | isa_bit_mve_float) \ | |
335 | && !TARGET_GENERAL_REGS_ONLY) | |
7b4c373b | 336 | |
c7be0832 SP |
337 | /* MVE have few common instructions as VFP, like VLDM alias VPOP, VLDR, VSTM |
338 | alia VPUSH, VSTR and VMOV, VMSR and VMRS. In the same manner it updates few | |
339 | registers such as FPCAR, FPCCR, FPDSCR, FPSCR, MVFR0, MVFR1 and MVFR2. All | |
340 | the VFP instructions, RTL patterns and register are guarded by | |
341 | TARGET_HARD_FLOAT. But the common instructions, RTL pattern and registers | |
342 | between MVE and VFP will be guarded by the following macro TARGET_VFP_BASE | |
343 | hereafter. */ | |
344 | ||
345 | #define TARGET_VFP_BASE (arm_float_abi != ARM_FLOAT_ABI_SOFT \ | |
346 | && bitmap_bit_p (arm_active_target.isa, \ | |
347 | isa_bit_vfp_base) \ | |
348 | && !TARGET_GENERAL_REGS_ONLY) | |
349 | ||
572070ef | 350 | /* Nonzero if integer division instructions supported. */ |
c8b6aa7c | 351 | #define TARGET_IDIV ((TARGET_ARM && arm_arch_arm_hwdiv) \ |
5ce15300 | 352 | || (TARGET_THUMB && arm_arch_thumb_hwdiv)) |
572070ef | 353 | |
afe006ad TG |
354 | /* Nonzero if disallow volatile memory access in IT block. */ |
355 | #define TARGET_NO_VOLATILE_CE (arm_arch_no_volatile_ce) | |
356 | ||
26c66656 KV |
357 | /* Should constant I be slplit for OP. */ |
358 | #define DONT_EARLY_SPLIT_CONSTANT(i, op) \ | |
359 | ((optimize >= 2) \ | |
360 | && can_create_pseudo_p () \ | |
361 | && !const_ok_for_op (i, op)) | |
362 | ||
b3f8d95d MM |
363 | /* True iff the full BPABI is being used. If TARGET_BPABI is true, |
364 | then TARGET_AAPCS_BASED must be true -- but the converse does not | |
365 | hold. TARGET_BPABI implies the use of the BPABI runtime library, | |
366 | etc., in addition to just the AAPCS calling conventions. */ | |
367 | #ifndef TARGET_BPABI | |
368 | #define TARGET_BPABI false | |
f676971a | 369 | #endif |
b3f8d95d | 370 | |
2f7d18dd CB |
371 | /* Transform lane numbers on big endian targets. This is used to allow for the |
372 | endianness difference between NEON architectural lane numbers and those | |
373 | used in RTL */ | |
374 | #define NEON_ENDIAN_LANE_N(mode, n) \ | |
375 | (BYTES_BIG_ENDIAN ? GET_MODE_NUNITS (mode) - 1 - n : n) | |
376 | ||
7816bea0 DJ |
377 | /* Support for a compile-time default CPU, et cetera. The rules are: |
378 | --with-arch is ignored if -march or -mcpu are specified. | |
379 | --with-cpu is ignored if -march or -mcpu are specified, and is overridden | |
380 | by --with-arch. | |
381 | --with-tune is ignored if -mtune or -mcpu are specified (but not affected | |
382 | by -march). | |
5e1b4d5a | 383 | --with-float is ignored if -mfloat-abi is specified. |
5848830f | 384 | --with-fpu is ignored if -mfpu is specified. |
ccdc2164 NS |
385 | --with-abi is ignored if -mabi is specified. |
386 | --with-tls is ignored if -mtls-dialect is specified. */ | |
7816bea0 DJ |
387 | #define OPTION_DEFAULT_SPECS \ |
388 | {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \ | |
389 | {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \ | |
390 | {"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}" }, \ | |
5e1b4d5a | 391 | {"float", "%{!mfloat-abi=*:-mfloat-abi=%(VALUE)}" }, \ |
5848830f | 392 | {"fpu", "%{!mfpu=*:-mfpu=%(VALUE)}"}, \ |
3cf94279 | 393 | {"abi", "%{!mabi=*:-mabi=%(VALUE)}"}, \ |
ccdc2164 | 394 | {"mode", "%{!marm:%{!mthumb:-m%(VALUE)}}"}, \ |
7cf13d1f | 395 | {"tls", "%{!mtls-dialect=*:-mtls-dialect=%(VALUE)}"}, |
7816bea0 | 396 | |
d79f3032 PB |
397 | extern const struct arm_fpu_desc |
398 | { | |
399 | const char *name; | |
066416da | 400 | enum isa_feature isa_bits[isa_num_bits]; |
19708abc CB |
401 | } all_fpus[]; |
402 | ||
d79f3032 PB |
403 | /* Which floating point hardware to schedule for. */ |
404 | extern int arm_fpu_attr; | |
71791e16 | 405 | |
3d8532aa PB |
406 | #ifndef TARGET_DEFAULT_FLOAT_ABI |
407 | #define TARGET_DEFAULT_FLOAT_ABI ARM_FLOAT_ABI_SOFT | |
408 | #endif | |
409 | ||
5848830f PB |
410 | #ifndef ARM_DEFAULT_ABI |
411 | #define ARM_DEFAULT_ABI ARM_ABI_APCS | |
412 | #endif | |
413 | ||
1ca92bdc SH |
414 | /* AAPCS based ABIs use short enums by default. */ |
415 | #ifndef ARM_DEFAULT_SHORT_ENUMS | |
416 | #define ARM_DEFAULT_SHORT_ENUMS \ | |
417 | (TARGET_AAPCS_BASED && arm_abi != ARM_ABI_AAPCS_LINUX) | |
418 | #endif | |
419 | ||
9e94a7fc MGD |
420 | /* Map each of the micro-architecture variants to their corresponding |
421 | major architecture revision. */ | |
422 | ||
423 | enum base_architecture | |
424 | { | |
425 | BASE_ARCH_0 = 0, | |
426 | BASE_ARCH_2 = 2, | |
427 | BASE_ARCH_3 = 3, | |
428 | BASE_ARCH_3M = 3, | |
429 | BASE_ARCH_4 = 4, | |
430 | BASE_ARCH_4T = 4, | |
9e94a7fc MGD |
431 | BASE_ARCH_5T = 5, |
432 | BASE_ARCH_5TE = 5, | |
433 | BASE_ARCH_5TEJ = 5, | |
434 | BASE_ARCH_6 = 6, | |
435 | BASE_ARCH_6J = 6, | |
39c12541 | 436 | BASE_ARCH_6KZ = 6, |
9e94a7fc MGD |
437 | BASE_ARCH_6K = 6, |
438 | BASE_ARCH_6T2 = 6, | |
439 | BASE_ARCH_6M = 6, | |
440 | BASE_ARCH_6Z = 6, | |
441 | BASE_ARCH_7 = 7, | |
442 | BASE_ARCH_7A = 7, | |
443 | BASE_ARCH_7R = 7, | |
444 | BASE_ARCH_7M = 7, | |
595fefee | 445 | BASE_ARCH_7EM = 7, |
05a437c1 TP |
446 | BASE_ARCH_8A = 8, |
447 | BASE_ARCH_8M_BASE = 8, | |
9296dd9b TP |
448 | BASE_ARCH_8M_MAIN = 8, |
449 | BASE_ARCH_8R = 8 | |
9e94a7fc MGD |
450 | }; |
451 | ||
452 | /* The major revision number of the ARM Architecture implemented by the target. */ | |
453 | extern enum base_architecture arm_base_arch; | |
454 | ||
9b66ebb1 | 455 | /* Nonzero if this chip supports the ARM Architecture 4 extensions. */ |
11c1a207 RE |
456 | extern int arm_arch4; |
457 | ||
68d560d4 RE |
458 | /* Nonzero if this chip supports the ARM Architecture 4T extensions. */ |
459 | extern int arm_arch4t; | |
460 | ||
c3f808d3 KT |
461 | /* Nonzero if this chip supports the ARM Architecture 5T extensions. */ |
462 | extern int arm_arch5t; | |
62b10bbc | 463 | |
c3f808d3 KT |
464 | /* Nonzero if this chip supports the ARM Architecture 5TE extensions. */ |
465 | extern int arm_arch5te; | |
b15bca31 | 466 | |
9b66ebb1 PB |
467 | /* Nonzero if this chip supports the ARM Architecture 6 extensions. */ |
468 | extern int arm_arch6; | |
469 | ||
029e79eb MS |
470 | /* Nonzero if this chip supports the ARM Architecture 6k extensions. */ |
471 | extern int arm_arch6k; | |
472 | ||
9e2a6301 TG |
473 | /* Nonzero if instructions present in ARMv6-M can be used. */ |
474 | extern int arm_arch6m; | |
475 | ||
029e79eb MS |
476 | /* Nonzero if this chip supports the ARM Architecture 7 extensions. */ |
477 | extern int arm_arch7; | |
478 | ||
5b3e6663 PB |
479 | /* Nonzero if instructions not present in the 'M' profile can be used. */ |
480 | extern int arm_arch_notm; | |
481 | ||
60bd3528 PB |
482 | /* Nonzero if instructions present in ARMv7E-M can be used. */ |
483 | extern int arm_arch7em; | |
484 | ||
595fefee MGD |
485 | /* Nonzero if this chip supports the ARM Architecture 8 extensions. */ |
486 | extern int arm_arch8; | |
487 | ||
252e03b5 MW |
488 | /* Nonzero if this chip supports the ARM Architecture 8.1 extensions. */ |
489 | extern int arm_arch8_1; | |
490 | ||
4040b89a MW |
491 | /* Nonzero if this chip supports the ARM Architecture 8.2 extensions. */ |
492 | extern int arm_arch8_2; | |
493 | ||
c2b7062d TC |
494 | /* Nonzero if this chip supports the ARM Architecture 8.3 extensions. */ |
495 | extern int arm_arch8_3; | |
496 | ||
497 | /* Nonzero if this chip supports the ARM Architecture 8.4 extensions. */ | |
498 | extern int arm_arch8_4; | |
499 | ||
e27cf2e3 MI |
500 | /* Nonzero if this chip supports the ARM Architecture 8.1-M Mainline |
501 | extensions. */ | |
502 | extern int arm_arch8_1m_main; | |
503 | ||
4040b89a MW |
504 | /* Nonzero if this chip supports the FP16 instructions extension of ARM |
505 | Architecture 8.2. */ | |
506 | extern int arm_fp16_inst; | |
507 | ||
f5a1b0d2 NC |
508 | /* Nonzero if this chip can benefit from load scheduling. */ |
509 | extern int arm_ld_sched; | |
510 | ||
511 | /* Nonzero if this chip is a StrongARM. */ | |
abac3b49 | 512 | extern int arm_tune_strongarm; |
f5a1b0d2 | 513 | |
5a9335ef NC |
514 | /* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */ |
515 | extern int arm_arch_iwmmxt; | |
516 | ||
8fd03515 XQ |
517 | /* Nonzero if this chip supports Intel Wireless MMX2 technology. */ |
518 | extern int arm_arch_iwmmxt2; | |
519 | ||
d19fb8e3 | 520 | /* Nonzero if this chip is an XScale. */ |
4b3c2e48 PB |
521 | extern int arm_arch_xscale; |
522 | ||
abac3b49 | 523 | /* Nonzero if tuning for XScale. */ |
4b3c2e48 | 524 | extern int arm_tune_xscale; |
d19fb8e3 | 525 | |
abac3b49 RE |
526 | /* Nonzero if tuning for stores via the write buffer. */ |
527 | extern int arm_tune_wbuf; | |
f5a1b0d2 | 528 | |
7612f14d PB |
529 | /* Nonzero if tuning for Cortex-A9. */ |
530 | extern int arm_tune_cortex_a9; | |
531 | ||
2ad4dcf9 | 532 | /* Nonzero if we should define __THUMB_INTERWORK__ in the |
f676971a | 533 | preprocessor. |
2ad4dcf9 RE |
534 | XXX This is a bit of a hack, it's intended to help work around |
535 | problems in GLD which doesn't understand that armv5t code is | |
536 | interworking clean. */ | |
537 | extern int arm_cpp_interwork; | |
538 | ||
52545641 TP |
539 | /* Nonzero if chip supports Thumb 1. */ |
540 | extern int arm_arch_thumb1; | |
541 | ||
5b3e6663 PB |
542 | /* Nonzero if chip supports Thumb 2. */ |
543 | extern int arm_arch_thumb2; | |
544 | ||
572070ef PB |
545 | /* Nonzero if chip supports integer division instruction in ARM mode. */ |
546 | extern int arm_arch_arm_hwdiv; | |
547 | ||
548 | /* Nonzero if chip supports integer division instruction in Thumb mode. */ | |
549 | extern int arm_arch_thumb_hwdiv; | |
5b3e6663 | 550 | |
afe006ad TG |
551 | /* Nonzero if chip disallows volatile memory access in IT block. */ |
552 | extern int arm_arch_no_volatile_ce; | |
553 | ||
02231c13 TG |
554 | /* Nonzero if we shouldn't use literal pools. */ |
555 | #ifndef USED_FOR_TARGET | |
556 | extern bool arm_disable_literal_pool; | |
557 | #endif | |
558 | ||
582e2e43 KT |
559 | /* Nonzero if chip supports the ARMv8 CRC instructions. */ |
560 | extern int arm_arch_crc; | |
561 | ||
de7b5723 AV |
562 | /* Nonzero if chip supports the ARMv8-M Security Extensions. */ |
563 | extern int arm_arch_cmse; | |
564 | ||
f782b667 DZ |
565 | /* Nonzero if chip supports the I8MM instructions. */ |
566 | extern int arm_arch_i8mm; | |
567 | ||
568 | /* Nonzero if chip supports the BFloat16 instructions. */ | |
569 | extern int arm_arch_bf16; | |
570 | ||
2ce9c1b9 | 571 | #ifndef TARGET_DEFAULT |
c54c7322 | 572 | #define TARGET_DEFAULT (MASK_APCS_FRAME) |
2ce9c1b9 | 573 | #endif |
35d965d5 | 574 | |
86efdc8e PB |
575 | /* Nonzero if PIC code requires explicit qualifiers to generate |
576 | PLT and GOT relocs rather than the assembler doing so implicitly. | |
ed0e6530 PB |
577 | Subtargets can override these if required. */ |
578 | #ifndef NEED_GOT_RELOC | |
579 | #define NEED_GOT_RELOC 0 | |
580 | #endif | |
581 | #ifndef NEED_PLT_RELOC | |
582 | #define NEED_PLT_RELOC 0 | |
e2723c62 | 583 | #endif |
84306176 | 584 | |
32d6e6c0 JY |
585 | #ifndef TARGET_DEFAULT_PIC_DATA_IS_TEXT_RELATIVE |
586 | #define TARGET_DEFAULT_PIC_DATA_IS_TEXT_RELATIVE 1 | |
587 | #endif | |
588 | ||
84306176 PB |
589 | /* Nonzero if we need to refer to the GOT with a PC-relative |
590 | offset. In other words, generate | |
591 | ||
f676971a | 592 | .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)] |
84306176 PB |
593 | |
594 | rather than | |
595 | ||
596 | .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8) | |
597 | ||
f676971a | 598 | The default is true, which matches NetBSD. Subtargets can |
84306176 PB |
599 | override this if required. */ |
600 | #ifndef GOT_PCREL | |
601 | #define GOT_PCREL 1 | |
602 | #endif | |
35d965d5 RS |
603 | \f |
604 | /* Target machine storage Layout. */ | |
605 | ||
ff9940b0 RE |
606 | |
607 | /* Define this macro if it is advisable to hold scalars in registers | |
608 | in a wider mode than that declared by the program. In such cases, | |
609 | the value is constrained to be within the bounds of the declared | |
610 | type, but kept valid in the wider mode. The signedness of the | |
611 | extension may differ from that of the type. */ | |
612 | ||
6cfc7210 | 613 | #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ |
2ce9c1b9 RE |
614 | if (GET_MODE_CLASS (MODE) == MODE_INT \ |
615 | && GET_MODE_SIZE (MODE) < 4) \ | |
616 | { \ | |
2ce9c1b9 | 617 | (MODE) = SImode; \ |
ff9940b0 RE |
618 | } |
619 | ||
35d965d5 RS |
620 | /* Define this if most significant bit is lowest numbered |
621 | in instructions that operate on numbered bit-fields. */ | |
622 | #define BITS_BIG_ENDIAN 0 | |
623 | ||
f676971a | 624 | /* Define this if most significant byte of a word is the lowest numbered. |
3ada8e17 DE |
625 | Most ARM processors are run in little endian mode, so that is the default. |
626 | If you want to have it run-time selectable, change the definition in a | |
627 | cover file to be TARGET_BIG_ENDIAN. */ | |
11c1a207 | 628 | #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0) |
35d965d5 RS |
629 | |
630 | /* Define this if most significant word of a multiword number is the lowest | |
8adb5dc7 KT |
631 | numbered. */ |
632 | #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN) | |
ddee6aba | 633 | |
35d965d5 RS |
634 | #define UNITS_PER_WORD 4 |
635 | ||
5848830f | 636 | /* True if natural alignment is used for doubleword types. */ |
b6685939 PB |
637 | #define ARM_DOUBLEWORD_ALIGN TARGET_AAPCS_BASED |
638 | ||
5848830f | 639 | #define DOUBLEWORD_ALIGNMENT 64 |
35d965d5 | 640 | |
5848830f | 641 | #define PARM_BOUNDARY 32 |
5a9335ef | 642 | |
5848830f | 643 | #define STACK_BOUNDARY (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32) |
35d965d5 | 644 | |
5848830f PB |
645 | #define PREFERRED_STACK_BOUNDARY \ |
646 | (arm_abi == ARM_ABI_ATPCS ? 64 : STACK_BOUNDARY) | |
0977774b | 647 | |
63b0cb04 CB |
648 | #define FUNCTION_BOUNDARY_P(flags) (TARGET_THUMB_P (flags) ? 16 : 32) |
649 | #define FUNCTION_BOUNDARY (FUNCTION_BOUNDARY_P (target_flags)) | |
35d965d5 | 650 | |
92928d71 AO |
651 | /* The lowest bit is used to indicate Thumb-mode functions, so the |
652 | vbit must go into the delta field of pointers to member | |
653 | functions. */ | |
654 | #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta | |
655 | ||
35d965d5 RS |
656 | #define EMPTY_FIELD_BOUNDARY 32 |
657 | ||
5848830f | 658 | #define BIGGEST_ALIGNMENT (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32) |
5a9335ef | 659 | |
f276d31d BE |
660 | #define MALLOC_ABI_ALIGNMENT BIGGEST_ALIGNMENT |
661 | ||
27847754 NC |
662 | /* XXX Blah -- this macro is used directly by libobjc. Since it |
663 | supports no vector modes, cut out the complexity and fall back | |
664 | on BIGGEST_FIELD_ALIGNMENT. */ | |
665 | #ifdef IN_TARGET_LIBS | |
8fca31a2 | 666 | #define BIGGEST_FIELD_ALIGNMENT 64 |
27847754 | 667 | #endif |
5a9335ef | 668 | |
96339268 RE |
669 | /* Align definitions of arrays, unions and structures so that |
670 | initializations and copies can be made more efficient. This is not | |
671 | ABI-changing, so it only affects places where we can see the | |
0c86e0dd CLT |
672 | definition. Increasing the alignment tends to introduce padding, |
673 | so don't do this when optimizing for size/conserving stack space. */ | |
674 | #define ARM_EXPAND_ALIGNMENT(COND, EXP, ALIGN) \ | |
675 | (((COND) && ((ALIGN) < BITS_PER_WORD) \ | |
96339268 RE |
676 | && (TREE_CODE (EXP) == ARRAY_TYPE \ |
677 | || TREE_CODE (EXP) == UNION_TYPE \ | |
678 | || TREE_CODE (EXP) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN)) | |
679 | ||
0c86e0dd CLT |
680 | /* Align global data. */ |
681 | #define DATA_ALIGNMENT(EXP, ALIGN) \ | |
682 | ARM_EXPAND_ALIGNMENT(!optimize_size, EXP, ALIGN) | |
683 | ||
96339268 | 684 | /* Similarly, make sure that objects on the stack are sensibly aligned. */ |
0c86e0dd CLT |
685 | #define LOCAL_ALIGNMENT(EXP, ALIGN) \ |
686 | ARM_EXPAND_ALIGNMENT(!flag_conserve_stack, EXP, ALIGN) | |
96339268 | 687 | |
723ae7c1 NC |
688 | /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the |
689 | value set in previous versions of this toolchain was 8, which produces more | |
690 | compact structures. The command line option -mstructure_size_boundary=<n> | |
f710504c | 691 | can be used to change this value. For compatibility with the ARM SDK |
723ae7c1 | 692 | however the value should be left at 32. ARM SDT Reference Manual (ARM DUI |
5848830f PB |
693 | 0020D) page 2-20 says "Structures are aligned on word boundaries". |
694 | The AAPCS specifies a value of 8. */ | |
6ead9ba5 | 695 | #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary |
723ae7c1 | 696 | |
4912a07c | 697 | /* This is the value used to initialize arm_structure_size_boundary. If a |
723ae7c1 | 698 | particular arm target wants to change the default value it should change |
6bc82793 | 699 | the definition of this macro, not STRUCTURE_SIZE_BOUNDARY. See netbsd.h |
723ae7c1 NC |
700 | for an example of this. */ |
701 | #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY | |
702 | #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32 | |
b355a481 | 703 | #endif |
2a5307b1 | 704 | |
825dda42 | 705 | /* Nonzero if move instructions will actually fail to work |
ff9940b0 | 706 | when given unaligned data. */ |
35d965d5 | 707 | #define STRICT_ALIGNMENT 1 |
b6685939 PB |
708 | |
709 | /* wchar_t is unsigned under the AAPCS. */ | |
710 | #ifndef WCHAR_TYPE | |
711 | #define WCHAR_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "int") | |
712 | ||
713 | #define WCHAR_TYPE_SIZE BITS_PER_WORD | |
714 | #endif | |
715 | ||
655b30bf JB |
716 | /* Sized for fixed-point types. */ |
717 | ||
718 | #define SHORT_FRACT_TYPE_SIZE 8 | |
719 | #define FRACT_TYPE_SIZE 16 | |
720 | #define LONG_FRACT_TYPE_SIZE 32 | |
721 | #define LONG_LONG_FRACT_TYPE_SIZE 64 | |
722 | ||
723 | #define SHORT_ACCUM_TYPE_SIZE 16 | |
724 | #define ACCUM_TYPE_SIZE 32 | |
725 | #define LONG_ACCUM_TYPE_SIZE 64 | |
726 | #define LONG_LONG_ACCUM_TYPE_SIZE 64 | |
727 | ||
728 | #define MAX_FIXED_MODE_SIZE 64 | |
729 | ||
b6685939 PB |
730 | #ifndef SIZE_TYPE |
731 | #define SIZE_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "long unsigned int") | |
732 | #endif | |
d81d0bdd | 733 | |
077fc835 KH |
734 | #ifndef PTRDIFF_TYPE |
735 | #define PTRDIFF_TYPE (TARGET_AAPCS_BASED ? "int" : "long int") | |
736 | #endif | |
737 | ||
d81d0bdd PB |
738 | /* AAPCS requires that structure alignment is affected by bitfields. */ |
739 | #ifndef PCC_BITFIELD_TYPE_MATTERS | |
740 | #define PCC_BITFIELD_TYPE_MATTERS TARGET_AAPCS_BASED | |
741 | #endif | |
742 | ||
82a19768 AT |
743 | /* The maximum size of the sync library functions supported. */ |
744 | #ifndef MAX_SYNC_LIBFUNC_SIZE | |
5357406f | 745 | #define MAX_SYNC_LIBFUNC_SIZE (2 * UNITS_PER_WORD) |
82a19768 AT |
746 | #endif |
747 | ||
35d965d5 RS |
748 | \f |
749 | /* Standard register usage. */ | |
750 | ||
0be8bd1a | 751 | /* Register allocation in ARM Procedure Call Standard |
3c5a5b93 | 752 | (S - saved over call, F - Frame-related). |
35d965d5 RS |
753 | |
754 | r0 * argument word/integer result | |
755 | r1-r3 argument word | |
756 | ||
757 | r4-r8 S register variable | |
758 | r9 S (rfp) register variable (real frame pointer) | |
f676971a | 759 | |
f5a1b0d2 | 760 | r10 F S (sl) stack limit (used by -mapcs-stack-check) |
35d965d5 RS |
761 | r11 F S (fp) argument pointer |
762 | r12 (ip) temp workspace | |
763 | r13 F S (sp) lower end of current stack frame | |
764 | r14 (lr) link address/workspace | |
765 | r15 F (pc) program counter | |
766 | ||
ff9940b0 RE |
767 | cc This is NOT a real register, but is used internally |
768 | to represent things that use or set the condition | |
769 | codes. | |
770 | sfp This isn't either. It is used during rtl generation | |
771 | since the offset between the frame pointer and the | |
772 | auto's isn't known until after register allocation. | |
773 | afp Nor this, we only need this because of non-local | |
774 | goto. Without it fp appears to be used and the | |
775 | elimination code won't get rid of sfp. It tracks | |
776 | fp exactly at all times. | |
cf16f980 KT |
777 | apsrq Nor this, it is used to track operations on the Q bit |
778 | of APSR by ACLE saturating intrinsics. | |
16155ccf KT |
779 | apsrge Nor this, it is used to track operations on the GE bits |
780 | of APSR by ACLE SIMD32 intrinsics | |
ff9940b0 | 781 | |
5efd84c5 | 782 | *: See TARGET_CONDITIONAL_REGISTER_USAGE */ |
35d965d5 | 783 | |
9b66ebb1 PB |
784 | /* s0-s15 VFP scratch (aka d0-d7). |
785 | s16-s31 S VFP variable (aka d8-d15). | |
786 | vfpcc Not a real register. Represents the VFP condition | |
63c8f7d6 SP |
787 | code flags. |
788 | vpr Used to represent MVE VPR predication. */ | |
9b66ebb1 | 789 | |
ff9940b0 RE |
790 | /* The stack backtrace structure is as follows: |
791 | fp points to here: | save code pointer | [fp] | |
792 | | return link value | [fp, #-4] | |
793 | | return sp value | [fp, #-8] | |
794 | | return fp value | [fp, #-12] | |
795 | [| saved r10 value |] | |
796 | [| saved r9 value |] | |
797 | [| saved r8 value |] | |
798 | [| saved r7 value |] | |
799 | [| saved r6 value |] | |
800 | [| saved r5 value |] | |
801 | [| saved r4 value |] | |
802 | [| saved r3 value |] | |
803 | [| saved r2 value |] | |
804 | [| saved r1 value |] | |
805 | [| saved r0 value |] | |
ff9940b0 RE |
806 | r0-r3 are not normally saved in a C function. */ |
807 | ||
35d965d5 RS |
808 | /* 1 for registers that have pervasive standard uses |
809 | and are not available for the register allocator. */ | |
0be8bd1a RE |
810 | #define FIXED_REGISTERS \ |
811 | { \ | |
812 | /* Core regs. */ \ | |
813 | 0,0,0,0,0,0,0,0, \ | |
814 | 0,0,0,0,0,1,0,1, \ | |
815 | /* VFP regs. */ \ | |
816 | 1,1,1,1,1,1,1,1, \ | |
817 | 1,1,1,1,1,1,1,1, \ | |
818 | 1,1,1,1,1,1,1,1, \ | |
819 | 1,1,1,1,1,1,1,1, \ | |
820 | 1,1,1,1,1,1,1,1, \ | |
821 | 1,1,1,1,1,1,1,1, \ | |
822 | 1,1,1,1,1,1,1,1, \ | |
823 | 1,1,1,1,1,1,1,1, \ | |
824 | /* IWMMXT regs. */ \ | |
825 | 1,1,1,1,1,1,1,1, \ | |
826 | 1,1,1,1,1,1,1,1, \ | |
827 | 1,1,1,1, \ | |
828 | /* Specials. */ \ | |
63c8f7d6 | 829 | 1,1,1,1,1,1,1 \ |
35d965d5 RS |
830 | } |
831 | ||
832 | /* 1 for registers not available across function calls. | |
833 | These must include the FIXED_REGISTERS and also any | |
834 | registers that can be used without being saved. | |
835 | The latter must include the registers where values are returned | |
836 | and the register where structure-value addresses are passed. | |
ff9940b0 | 837 | Aside from that, you can include as many other registers as you like. |
f676971a | 838 | The CC is not preserved over function calls on the ARM 6, so it is |
d6b4baa4 | 839 | easier to assume this for all. SFP is preserved, since FP is. */ |
0be8bd1a RE |
840 | #define CALL_USED_REGISTERS \ |
841 | { \ | |
842 | /* Core regs. */ \ | |
843 | 1,1,1,1,0,0,0,0, \ | |
844 | 0,0,0,0,1,1,1,1, \ | |
845 | /* VFP Regs. */ \ | |
846 | 1,1,1,1,1,1,1,1, \ | |
847 | 1,1,1,1,1,1,1,1, \ | |
848 | 1,1,1,1,1,1,1,1, \ | |
849 | 1,1,1,1,1,1,1,1, \ | |
850 | 1,1,1,1,1,1,1,1, \ | |
851 | 1,1,1,1,1,1,1,1, \ | |
852 | 1,1,1,1,1,1,1,1, \ | |
853 | 1,1,1,1,1,1,1,1, \ | |
854 | /* IWMMXT regs. */ \ | |
855 | 1,1,1,1,1,1,1,1, \ | |
856 | 1,1,1,1,1,1,1,1, \ | |
857 | 1,1,1,1, \ | |
858 | /* Specials. */ \ | |
63c8f7d6 | 859 | 1,1,1,1,1,1,1 \ |
35d965d5 RS |
860 | } |
861 | ||
6cc8c0b3 NC |
862 | #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE |
863 | #define SUBTARGET_CONDITIONAL_REGISTER_USAGE | |
864 | #endif | |
865 | ||
6bc82793 | 866 | /* These are a couple of extensions to the formats accepted |
dd18ae56 NC |
867 | by asm_fprintf: |
868 | %@ prints out ASM_COMMENT_START | |
869 | %r prints out REGISTER_PREFIX reg_names[arg] */ | |
870 | #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \ | |
871 | case '@': \ | |
872 | fputs (ASM_COMMENT_START, FILE); \ | |
873 | break; \ | |
874 | \ | |
875 | case 'r': \ | |
876 | fputs (REGISTER_PREFIX, FILE); \ | |
877 | fputs (reg_names [va_arg (ARGS, int)], FILE); \ | |
878 | break; | |
879 | ||
d5b7b3ae | 880 | /* Round X up to the nearest word. */ |
0c2ca901 | 881 | #define ROUND_UP_WORD(X) (((X) + 3) & ~3) |
d5b7b3ae | 882 | |
6cfc7210 | 883 | /* Convert fron bytes to ints. */ |
e9d7b180 | 884 | #define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) |
6cfc7210 | 885 | |
9b66ebb1 PB |
886 | /* The number of (integer) registers required to hold a quantity of type MODE. |
887 | Also used for VFP registers. */ | |
e9d7b180 JD |
888 | #define ARM_NUM_REGS(MODE) \ |
889 | ARM_NUM_INTS (GET_MODE_SIZE (MODE)) | |
6cfc7210 NC |
890 | |
891 | /* The number of (integer) registers required to hold a quantity of TYPE MODE. */ | |
e9d7b180 JD |
892 | #define ARM_NUM_REGS2(MODE, TYPE) \ |
893 | ARM_NUM_INTS ((MODE) == BLKmode ? \ | |
d5b7b3ae | 894 | int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE)) |
6cfc7210 NC |
895 | |
896 | /* The number of (integer) argument register available. */ | |
d5b7b3ae | 897 | #define NUM_ARG_REGS 4 |
6cfc7210 | 898 | |
390b17c2 RE |
899 | /* And similarly for the VFP. */ |
900 | #define NUM_VFP_ARG_REGS 16 | |
901 | ||
093354e0 | 902 | /* Return the register number of the N'th (integer) argument. */ |
d5b7b3ae | 903 | #define ARG_REGISTER(N) (N - 1) |
6cfc7210 | 904 | |
d5b7b3ae RE |
905 | /* Specify the registers used for certain standard purposes. |
906 | The values of these macros are register numbers. */ | |
35d965d5 | 907 | |
d5b7b3ae RE |
908 | /* The number of the last argument register. */ |
909 | #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS) | |
35d965d5 | 910 | |
c769a35d RE |
911 | /* The numbers of the Thumb register ranges. */ |
912 | #define FIRST_LO_REGNUM 0 | |
6d3d9133 | 913 | #define LAST_LO_REGNUM 7 |
c769a35d RE |
914 | #define FIRST_HI_REGNUM 8 |
915 | #define LAST_HI_REGNUM 11 | |
6d3d9133 | 916 | |
f0a0390e RH |
917 | /* Overridden by config/arm/bpabi.h. */ |
918 | #ifndef ARM_UNWIND_INFO | |
919 | #define ARM_UNWIND_INFO 0 | |
617a1b71 PB |
920 | #endif |
921 | ||
c9ca9b88 PB |
922 | /* Use r0 and r1 to pass exception handling information. */ |
923 | #define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? N : INVALID_REGNUM) | |
924 | ||
6d3d9133 | 925 | /* The register that holds the return address in exception handlers. */ |
c9ca9b88 PB |
926 | #define ARM_EH_STACKADJ_REGNUM 2 |
927 | #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (SImode, ARM_EH_STACKADJ_REGNUM) | |
35d965d5 | 928 | |
1e874273 PB |
929 | #ifndef ARM_TARGET2_DWARF_FORMAT |
930 | #define ARM_TARGET2_DWARF_FORMAT DW_EH_PE_pcrel | |
3f2f838e | 931 | #endif |
1e874273 PB |
932 | |
933 | /* ttype entries (the only interesting data references used) | |
934 | use TARGET2 relocations. */ | |
935 | #define ASM_PREFERRED_EH_DATA_FORMAT(code, data) \ | |
936 | (((code) == 0 && (data) == 1 && ARM_UNWIND_INFO) ? ARM_TARGET2_DWARF_FORMAT \ | |
937 | : DW_EH_PE_absptr) | |
1e874273 | 938 | |
d5b7b3ae RE |
939 | /* The native (Norcroft) Pascal compiler for the ARM passes the static chain |
940 | as an invisible last argument (possible since varargs don't exist in | |
941 | Pascal), so the following is not true. */ | |
5b3e6663 | 942 | #define STATIC_CHAIN_REGNUM 12 |
35d965d5 | 943 | |
8b63716e CL |
944 | /* r9 is the FDPIC register (base register for GOT and FUNCDESC accesses). */ |
945 | #define FDPIC_REGNUM 9 | |
946 | ||
d5b7b3ae RE |
947 | /* Define this to be where the real frame pointer is if it is not possible to |
948 | work out the offset between the frame pointer and the automatic variables | |
949 | until after register allocation has taken place. FRAME_POINTER_REGNUM | |
950 | should point to a special register that we will make sure is eliminated. | |
951 | ||
952 | For the Thumb we have another problem. The TPCS defines the frame pointer | |
6bc82793 | 953 | as r11, and GCC believes that it is always possible to use the frame pointer |
d5b7b3ae RE |
954 | as base register for addressing purposes. (See comments in |
955 | find_reloads_address()). But - the Thumb does not allow high registers, | |
956 | including r11, to be used as base address registers. Hence our problem. | |
957 | ||
958 | The solution used here, and in the old thumb port is to use r7 instead of | |
959 | r11 as the hard frame pointer and to have special code to generate | |
960 | backtrace structures on the stack (if required to do so via a command line | |
6bc82793 | 961 | option) using r11. This is the only 'user visible' use of r11 as a frame |
d5b7b3ae RE |
962 | pointer. */ |
963 | #define ARM_HARD_FRAME_POINTER_REGNUM 11 | |
964 | #define THUMB_HARD_FRAME_POINTER_REGNUM 7 | |
35d965d5 | 965 | |
b15bca31 RE |
966 | #define HARD_FRAME_POINTER_REGNUM \ |
967 | (TARGET_ARM \ | |
968 | ? ARM_HARD_FRAME_POINTER_REGNUM \ | |
969 | : THUMB_HARD_FRAME_POINTER_REGNUM) | |
d5b7b3ae | 970 | |
e3339d0f JM |
971 | #define HARD_FRAME_POINTER_IS_FRAME_POINTER 0 |
972 | #define HARD_FRAME_POINTER_IS_ARG_POINTER 0 | |
973 | ||
b15bca31 | 974 | #define FP_REGNUM HARD_FRAME_POINTER_REGNUM |
d5b7b3ae | 975 | |
b15bca31 RE |
976 | /* Register to use for pushing function arguments. */ |
977 | #define STACK_POINTER_REGNUM SP_REGNUM | |
d5b7b3ae | 978 | |
0be8bd1a RE |
979 | #define FIRST_IWMMXT_REGNUM (LAST_HI_VFP_REGNUM + 1) |
980 | #define LAST_IWMMXT_REGNUM (FIRST_IWMMXT_REGNUM + 15) | |
a76213b9 XQ |
981 | |
982 | /* Need to sync with WCGR in iwmmxt.md. */ | |
0be8bd1a RE |
983 | #define FIRST_IWMMXT_GR_REGNUM (LAST_IWMMXT_REGNUM + 1) |
984 | #define LAST_IWMMXT_GR_REGNUM (FIRST_IWMMXT_GR_REGNUM + 3) | |
d5b7b3ae | 985 | |
5a9335ef NC |
986 | #define IS_IWMMXT_REGNUM(REGNUM) \ |
987 | (((REGNUM) >= FIRST_IWMMXT_REGNUM) && ((REGNUM) <= LAST_IWMMXT_REGNUM)) | |
988 | #define IS_IWMMXT_GR_REGNUM(REGNUM) \ | |
989 | (((REGNUM) >= FIRST_IWMMXT_GR_REGNUM) && ((REGNUM) <= LAST_IWMMXT_GR_REGNUM)) | |
990 | ||
35d965d5 | 991 | /* Base register for access to local variables of the function. */ |
0be8bd1a | 992 | #define FRAME_POINTER_REGNUM 102 |
ff9940b0 | 993 | |
d5b7b3ae | 994 | /* Base register for access to arguments of the function. */ |
0be8bd1a | 995 | #define ARG_POINTER_REGNUM 103 |
62b10bbc | 996 | |
0be8bd1a RE |
997 | #define FIRST_VFP_REGNUM 16 |
998 | #define D7_VFP_REGNUM (FIRST_VFP_REGNUM + 15) | |
f1adb0a9 | 999 | #define LAST_VFP_REGNUM \ |
302c3d8e | 1000 | (TARGET_VFPD32 ? LAST_HI_VFP_REGNUM : LAST_LO_VFP_REGNUM) |
f1adb0a9 | 1001 | |
9b66ebb1 PB |
1002 | #define IS_VFP_REGNUM(REGNUM) \ |
1003 | (((REGNUM) >= FIRST_VFP_REGNUM) && ((REGNUM) <= LAST_VFP_REGNUM)) | |
1004 | ||
f1adb0a9 JB |
1005 | /* VFP registers are split into two types: those defined by VFP versions < 3 |
1006 | have D registers overlaid on consecutive pairs of S registers. VFP version 3 | |
1007 | defines 16 new D registers (d16-d31) which, for simplicity and correctness | |
1008 | in various parts of the backend, we implement as "fake" single-precision | |
1009 | registers (which would be S32-S63, but cannot be used in that way). The | |
1010 | following macros define these ranges of registers. */ | |
0be8bd1a RE |
1011 | #define LAST_LO_VFP_REGNUM (FIRST_VFP_REGNUM + 31) |
1012 | #define FIRST_HI_VFP_REGNUM (LAST_LO_VFP_REGNUM + 1) | |
1013 | #define LAST_HI_VFP_REGNUM (FIRST_HI_VFP_REGNUM + 31) | |
f1adb0a9 JB |
1014 | |
1015 | #define VFP_REGNO_OK_FOR_SINGLE(REGNUM) \ | |
1016 | ((REGNUM) <= LAST_LO_VFP_REGNUM) | |
1017 | ||
1018 | /* DFmode values are only valid in even register pairs. */ | |
1019 | #define VFP_REGNO_OK_FOR_DOUBLE(REGNUM) \ | |
1020 | ((((REGNUM) - FIRST_VFP_REGNUM) & 1) == 0) | |
1021 | ||
88f77cba JB |
1022 | /* Neon Quad values must start at a multiple of four registers. */ |
1023 | #define NEON_REGNO_OK_FOR_QUAD(REGNUM) \ | |
1024 | ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0) | |
1025 | ||
1026 | /* Neon structures of vectors must be in even register pairs and there | |
1027 | must be enough registers available. Because of various patterns | |
1028 | requiring quad registers, we require them to start at a multiple of | |
1029 | four. */ | |
1030 | #define NEON_REGNO_OK_FOR_NREGS(REGNUM, N) \ | |
1031 | ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0 \ | |
1032 | && (LAST_VFP_REGNUM - (REGNUM) >= 2 * (N) - 1)) | |
1033 | ||
16155ccf | 1034 | /* The number of hard registers is 16 ARM + 1 CC + 1 SFP + 1 AFP |
63c8f7d6 | 1035 | + 1 APSRQ + 1 APSRGE + 1 VPR. */ |
5a9335ef | 1036 | /* Intel Wireless MMX Technology registers add 16 + 4 more. */ |
0be8bd1a | 1037 | /* VFP (VFP3) adds 32 (64) + 1 VFPCC. */ |
63c8f7d6 | 1038 | #define FIRST_PSEUDO_REGISTER 107 |
62b10bbc | 1039 | |
2fa330b2 PB |
1040 | #define DBX_REGISTER_NUMBER(REGNO) arm_dbx_register_number (REGNO) |
1041 | ||
35d965d5 RS |
1042 | /* Value should be nonzero if functions must have frame pointers. |
1043 | Zero means the frame pointer need not be set up (and parms may be accessed | |
f676971a | 1044 | via the stack pointer) in functions that seem suitable. |
ff9940b0 RE |
1045 | If we have to have a frame pointer we might as well make use of it. |
1046 | APCS says that the frame pointer does not need to be pushed in leaf | |
2a5307b1 | 1047 | functions, or simple tail call functions. */ |
a15900b5 DJ |
1048 | |
1049 | #ifndef SUBTARGET_FRAME_POINTER_REQUIRED | |
1050 | #define SUBTARGET_FRAME_POINTER_REQUIRED 0 | |
1051 | #endif | |
1052 | ||
5a9335ef | 1053 | #define VALID_IWMMXT_REG_MODE(MODE) \ |
f676971a | 1054 | (arm_vector_mode_supported_p (MODE) || (MODE) == DImode) |
5a9335ef | 1055 | |
88f77cba JB |
1056 | /* Modes valid for Neon D registers. */ |
1057 | #define VALID_NEON_DREG_MODE(MODE) \ | |
1058 | ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode \ | |
2e87b2f4 SMW |
1059 | || (MODE) == V4HFmode || (MODE) == V2SFmode || (MODE) == DImode \ |
1060 | || (MODE) == V4BFmode) | |
88f77cba JB |
1061 | |
1062 | /* Modes valid for Neon Q registers. */ | |
1063 | #define VALID_NEON_QREG_MODE(MODE) \ | |
1064 | ((MODE) == V4SImode || (MODE) == V8HImode || (MODE) == V16QImode \ | |
2e87b2f4 SMW |
1065 | || (MODE) == V8HFmode || (MODE) == V4SFmode || (MODE) == V2DImode \ |
1066 | || (MODE) == V8BFmode) | |
88f77cba | 1067 | |
63c8f7d6 SP |
1068 | #define VALID_MVE_MODE(MODE) \ |
1069 | ((MODE) == V2DImode ||(MODE) == V4SImode || (MODE) == V8HImode \ | |
1070 | || (MODE) == V16QImode || (MODE) == V8HFmode || (MODE) == V4SFmode \ | |
1071 | || (MODE) == V2DFmode) | |
1072 | ||
1073 | #define VALID_MVE_SI_MODE(MODE) \ | |
1074 | ((MODE) == V2DImode ||(MODE) == V4SImode || (MODE) == V8HImode \ | |
1075 | || (MODE) == V16QImode) | |
1076 | ||
1077 | #define VALID_MVE_SF_MODE(MODE) \ | |
1078 | ((MODE) == V8HFmode || (MODE) == V4SFmode || (MODE) == V2DFmode) | |
1079 | ||
88f77cba JB |
1080 | /* Structure modes valid for Neon registers. */ |
1081 | #define VALID_NEON_STRUCT_MODE(MODE) \ | |
1082 | ((MODE) == TImode || (MODE) == EImode || (MODE) == OImode \ | |
1083 | || (MODE) == CImode || (MODE) == XImode) | |
1084 | ||
63c8f7d6 SP |
1085 | #define VALID_MVE_STRUCT_MODE(MODE) \ |
1086 | ((MODE) == TImode || (MODE) == OImode || (MODE) == XImode) | |
1087 | ||
37119410 BS |
1088 | /* The register numbers in sequence, for passing to arm_gen_load_multiple. */ |
1089 | extern int arm_regs_in_sequence[]; | |
1090 | ||
35d965d5 | 1091 | /* The order in which register should be allocated. It is good to use ip |
ff9940b0 RE |
1092 | since no saving is required (though calls clobber it) and it never contains |
1093 | function parameters. It is quite good to use lr since other calls may | |
f676971a | 1094 | clobber it anyway. Allocate r0 through r3 in reverse order since r3 is |
ff9940b0 | 1095 | least likely to contain a function parameter; in addition results are |
f1adb0a9 JB |
1096 | returned in r0. |
1097 | For VFP/VFPv3, allocate D16-D31 first, then caller-saved registers (D0-D7), | |
1098 | then D8-D15. The reason for doing this is to attempt to reduce register | |
1099 | pressure when both single- and double-precision registers are used in a | |
1100 | function. */ | |
1101 | ||
0be8bd1a RE |
1102 | #define VREG(X) (FIRST_VFP_REGNUM + (X)) |
1103 | #define WREG(X) (FIRST_IWMMXT_REGNUM + (X)) | |
1104 | #define WGREG(X) (FIRST_IWMMXT_GR_REGNUM + (X)) | |
1105 | ||
f1adb0a9 JB |
1106 | #define REG_ALLOC_ORDER \ |
1107 | { \ | |
0be8bd1a RE |
1108 | /* General registers. */ \ |
1109 | 3, 2, 1, 0, 12, 14, 4, 5, \ | |
1110 | 6, 7, 8, 9, 10, 11, \ | |
1111 | /* High VFP registers. */ \ | |
1112 | VREG(32), VREG(33), VREG(34), VREG(35), \ | |
1113 | VREG(36), VREG(37), VREG(38), VREG(39), \ | |
1114 | VREG(40), VREG(41), VREG(42), VREG(43), \ | |
1115 | VREG(44), VREG(45), VREG(46), VREG(47), \ | |
1116 | VREG(48), VREG(49), VREG(50), VREG(51), \ | |
1117 | VREG(52), VREG(53), VREG(54), VREG(55), \ | |
1118 | VREG(56), VREG(57), VREG(58), VREG(59), \ | |
1119 | VREG(60), VREG(61), VREG(62), VREG(63), \ | |
1120 | /* VFP argument registers. */ \ | |
1121 | VREG(15), VREG(14), VREG(13), VREG(12), \ | |
1122 | VREG(11), VREG(10), VREG(9), VREG(8), \ | |
1123 | VREG(7), VREG(6), VREG(5), VREG(4), \ | |
1124 | VREG(3), VREG(2), VREG(1), VREG(0), \ | |
1125 | /* VFP call-saved registers. */ \ | |
1126 | VREG(16), VREG(17), VREG(18), VREG(19), \ | |
1127 | VREG(20), VREG(21), VREG(22), VREG(23), \ | |
1128 | VREG(24), VREG(25), VREG(26), VREG(27), \ | |
1129 | VREG(28), VREG(29), VREG(30), VREG(31), \ | |
1130 | /* IWMMX registers. */ \ | |
1131 | WREG(0), WREG(1), WREG(2), WREG(3), \ | |
1132 | WREG(4), WREG(5), WREG(6), WREG(7), \ | |
1133 | WREG(8), WREG(9), WREG(10), WREG(11), \ | |
1134 | WREG(12), WREG(13), WREG(14), WREG(15), \ | |
1135 | WGREG(0), WGREG(1), WGREG(2), WGREG(3), \ | |
1136 | /* Registers not for general use. */ \ | |
1137 | CC_REGNUM, VFPCC_REGNUM, \ | |
1138 | FRAME_POINTER_REGNUM, ARG_POINTER_REGNUM, \ | |
63c8f7d6 SP |
1139 | SP_REGNUM, PC_REGNUM, APSRQ_REGNUM, \ |
1140 | APSRGE_REGNUM, VPR_REGNUM \ | |
35d965d5 | 1141 | } |
9338ffe6 | 1142 | |
63c8f7d6 SP |
1143 | #define IS_VPR_REGNUM(REGNUM) \ |
1144 | ((REGNUM) == VPR_REGNUM) | |
1145 | ||
795dc4fc | 1146 | /* Use different register alloc ordering for Thumb. */ |
5a733826 BS |
1147 | #define ADJUST_REG_ALLOC_ORDER arm_order_regs_for_local_alloc () |
1148 | ||
3635c2bf WD |
1149 | /* Tell IRA to use the order we define when optimizing for size. */ |
1150 | #define HONOR_REG_ALLOC_ORDER optimize_function_for_size_p (cfun) | |
795dc4fc | 1151 | |
9338ffe6 PB |
1152 | /* Interrupt functions can only use registers that have already been |
1153 | saved by the prologue, even if they would normally be | |
1154 | call-clobbered. */ | |
1155 | #define HARD_REGNO_RENAME_OK(SRC, DST) \ | |
1156 | (! IS_INTERRUPT (cfun->machine->func_type) || \ | |
6fb5fa3c | 1157 | df_regs_ever_live_p (DST)) |
35d965d5 RS |
1158 | \f |
1159 | /* Register and constant classes. */ | |
1160 | ||
0be8bd1a | 1161 | /* Register classes. */ |
35d965d5 RS |
1162 | enum reg_class |
1163 | { | |
1164 | NO_REGS, | |
0be8bd1a RE |
1165 | LO_REGS, |
1166 | STACK_REG, | |
1167 | BASE_REGS, | |
1168 | HI_REGS, | |
9adcfa3c | 1169 | CALLER_SAVE_REGS, |
6df4618c | 1170 | EVEN_REG, |
0be8bd1a RE |
1171 | GENERAL_REGS, |
1172 | CORE_REGS, | |
f1adb0a9 JB |
1173 | VFP_D0_D7_REGS, |
1174 | VFP_LO_REGS, | |
1175 | VFP_HI_REGS, | |
9b66ebb1 | 1176 | VFP_REGS, |
5a9335ef | 1177 | IWMMXT_REGS, |
0be8bd1a | 1178 | IWMMXT_GR_REGS, |
d5b7b3ae | 1179 | CC_REG, |
9b66ebb1 | 1180 | VFPCC_REG, |
0be8bd1a RE |
1181 | SFP_REG, |
1182 | AFP_REG, | |
63c8f7d6 | 1183 | VPR_REG, |
35d965d5 RS |
1184 | ALL_REGS, |
1185 | LIM_REG_CLASSES | |
1186 | }; | |
1187 | ||
1188 | #define N_REG_CLASSES (int) LIM_REG_CLASSES | |
1189 | ||
d6b4baa4 | 1190 | /* Give names of register classes as strings for dump file. */ |
63c8f7d6 | 1191 | #define REG_CLASS_NAMES \ |
35d965d5 RS |
1192 | { \ |
1193 | "NO_REGS", \ | |
0be8bd1a RE |
1194 | "LO_REGS", \ |
1195 | "STACK_REG", \ | |
1196 | "BASE_REGS", \ | |
1197 | "HI_REGS", \ | |
9adcfa3c | 1198 | "CALLER_SAVE_REGS", \ |
6df4618c | 1199 | "EVEN_REG", \ |
0be8bd1a RE |
1200 | "GENERAL_REGS", \ |
1201 | "CORE_REGS", \ | |
f1adb0a9 JB |
1202 | "VFP_D0_D7_REGS", \ |
1203 | "VFP_LO_REGS", \ | |
1204 | "VFP_HI_REGS", \ | |
9b66ebb1 | 1205 | "VFP_REGS", \ |
5a9335ef | 1206 | "IWMMXT_REGS", \ |
0be8bd1a | 1207 | "IWMMXT_GR_REGS", \ |
d5b7b3ae | 1208 | "CC_REG", \ |
5384443a | 1209 | "VFPCC_REG", \ |
9f4f1735 JJ |
1210 | "SFP_REG", \ |
1211 | "AFP_REG", \ | |
63c8f7d6 | 1212 | "VPR_REG", \ |
9f4f1735 | 1213 | "ALL_REGS" \ |
35d965d5 RS |
1214 | } |
1215 | ||
1216 | /* Define which registers fit in which classes. | |
1217 | This is an initializer for a vector of HARD_REG_SET | |
1218 | of length N_REG_CLASSES. */ | |
f1adb0a9 JB |
1219 | #define REG_CLASS_CONTENTS \ |
1220 | { \ | |
1221 | { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \ | |
f1adb0a9 JB |
1222 | { 0x000000FF, 0x00000000, 0x00000000, 0x00000000 }, /* LO_REGS */ \ |
1223 | { 0x00002000, 0x00000000, 0x00000000, 0x00000000 }, /* STACK_REG */ \ | |
1224 | { 0x000020FF, 0x00000000, 0x00000000, 0x00000000 }, /* BASE_REGS */ \ | |
0be8bd1a | 1225 | { 0x00005F00, 0x00000000, 0x00000000, 0x00000000 }, /* HI_REGS */ \ |
9adcfa3c | 1226 | { 0x0000100F, 0x00000000, 0x00000000, 0x00000000 }, /* CALLER_SAVE_REGS */ \ |
6df4618c | 1227 | { 0x00005555, 0x00000000, 0x00000000, 0x00000000 }, /* EVEN_REGS. */ \ |
0be8bd1a RE |
1228 | { 0x00005FFF, 0x00000000, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \ |
1229 | { 0x00007FFF, 0x00000000, 0x00000000, 0x00000000 }, /* CORE_REGS */ \ | |
1230 | { 0xFFFF0000, 0x00000000, 0x00000000, 0x00000000 }, /* VFP_D0_D7_REGS */ \ | |
1231 | { 0xFFFF0000, 0x0000FFFF, 0x00000000, 0x00000000 }, /* VFP_LO_REGS */ \ | |
1232 | { 0x00000000, 0xFFFF0000, 0x0000FFFF, 0x00000000 }, /* VFP_HI_REGS */ \ | |
1233 | { 0xFFFF0000, 0xFFFFFFFF, 0x0000FFFF, 0x00000000 }, /* VFP_REGS */ \ | |
1234 | { 0x00000000, 0x00000000, 0xFFFF0000, 0x00000000 }, /* IWMMXT_REGS */ \ | |
1235 | { 0x00000000, 0x00000000, 0x00000000, 0x0000000F }, /* IWMMXT_GR_REGS */ \ | |
1236 | { 0x00000000, 0x00000000, 0x00000000, 0x00000010 }, /* CC_REG */ \ | |
1237 | { 0x00000000, 0x00000000, 0x00000000, 0x00000020 }, /* VFPCC_REG */ \ | |
1238 | { 0x00000000, 0x00000000, 0x00000000, 0x00000040 }, /* SFP_REG */ \ | |
1239 | { 0x00000000, 0x00000000, 0x00000000, 0x00000080 }, /* AFP_REG */ \ | |
63c8f7d6 SP |
1240 | { 0x00000000, 0x00000000, 0x00000000, 0x00000400 }, /* VPR_REG. */ \ |
1241 | { 0xFFFF7FFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x0000000F } /* ALL_REGS. */ \ | |
35d965d5 | 1242 | } |
4b02997f | 1243 | |
e0e4be48 MI |
1244 | #define FP_SYSREGS \ |
1245 | DEF_FP_SYSREG (FPSCR) \ | |
1246 | DEF_FP_SYSREG (FPSCR_nzcvqc) \ | |
1247 | DEF_FP_SYSREG (VPR) \ | |
1248 | DEF_FP_SYSREG (P0) \ | |
1249 | DEF_FP_SYSREG (FPCXTNS) \ | |
1250 | DEF_FP_SYSREG (FPCXTS) | |
1251 | ||
1252 | #define DEF_FP_SYSREG(reg) reg ## _ENUM, | |
1253 | enum vfp_sysregs_encoding { | |
1254 | FP_SYSREGS | |
1255 | NB_FP_SYSREGS | |
1256 | }; | |
1257 | #undef DEF_FP_SYSREG | |
1258 | extern const char *fp_sysreg_names[NB_FP_SYSREGS]; | |
1259 | ||
f1adb0a9 JB |
1260 | /* Any of the VFP register classes. */ |
1261 | #define IS_VFP_CLASS(X) \ | |
1262 | ((X) == VFP_D0_D7_REGS || (X) == VFP_LO_REGS \ | |
1263 | || (X) == VFP_HI_REGS || (X) == VFP_REGS) | |
1264 | ||
35d965d5 RS |
1265 | /* The same information, inverted: |
1266 | Return the class number of the smallest class containing | |
1267 | reg number REGNO. This could be a conditional expression | |
1268 | or could index an array. */ | |
d5b7b3ae | 1269 | #define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO) |
35d965d5 RS |
1270 | |
1271 | /* The class value for index registers, and the one for base regs. */ | |
5b3e6663 | 1272 | #define INDEX_REG_CLASS (TARGET_THUMB1 ? LO_REGS : GENERAL_REGS) |
f5c630c3 | 1273 | #define BASE_REG_CLASS (TARGET_THUMB1 ? LO_REGS : CORE_REGS) |
d5b7b3ae | 1274 | |
b93a0fe6 | 1275 | /* For the Thumb the high registers cannot be used as base registers |
6bc82793 | 1276 | when addressing quantities in QI or HI mode; if we don't know the |
888d2cd6 | 1277 | mode, then we must be conservative. */ |
c896d4b4 MW |
1278 | #define MODE_BASE_REG_CLASS(MODE) \ |
1279 | (TARGET_32BIT ? CORE_REGS \ | |
1280 | : GET_MODE_SIZE (MODE) >= 4 ? BASE_REGS \ | |
1281 | : LO_REGS) | |
888d2cd6 | 1282 | |
67914693 | 1283 | /* For Thumb we cannot support SP+reg addressing, so we return LO_REGS |
888d2cd6 DJ |
1284 | instead of BASE_REGS. */ |
1285 | #define MODE_BASE_REG_REG_CLASS(MODE) BASE_REG_CLASS | |
3dcc68a4 | 1286 | |
42db504c | 1287 | /* When this hook returns true for MODE, the compiler allows |
d5b7b3ae RE |
1288 | registers explicitly used in the rtl to be used as spill registers |
1289 | but prevents the compiler from extending the lifetime of these | |
d6b4baa4 | 1290 | registers. */ |
42db504c SB |
1291 | #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \ |
1292 | arm_small_register_classes_for_mode_p | |
35d965d5 | 1293 | |
d5b7b3ae RE |
1294 | /* Must leave BASE_REGS reloads alone */ |
1295 | #define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \ | |
78a14aa8 YR |
1296 | (lra_in_progress ? NO_REGS \ |
1297 | : ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \ | |
1298 | ? ((true_regnum (X) == -1 ? LO_REGS \ | |
a93072ca | 1299 | : (true_regnum (X) + hard_regno_nregs (0, MODE) > 8) ? LO_REGS \ |
78a14aa8 YR |
1300 | : NO_REGS)) \ |
1301 | : NO_REGS)) | |
d5b7b3ae RE |
1302 | |
1303 | #define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \ | |
1fc017b6 VM |
1304 | (lra_in_progress ? NO_REGS \ |
1305 | : (CLASS) != LO_REGS && (CLASS) != BASE_REGS \ | |
1306 | ? ((true_regnum (X) == -1 ? LO_REGS \ | |
a93072ca | 1307 | : (true_regnum (X) + hard_regno_nregs (0, MODE) > 8) ? LO_REGS \ |
1fc017b6 VM |
1308 | : NO_REGS)) \ |
1309 | : NO_REGS) | |
35d965d5 | 1310 | |
ff9940b0 RE |
1311 | /* Return the register class of a scratch register needed to copy IN into |
1312 | or out of a register in CLASS in MODE. If it can be done directly, | |
1313 | NO_REGS is returned. */ | |
d5b7b3ae | 1314 | #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \ |
fe2d934b | 1315 | /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \ |
00ea1506 | 1316 | ((TARGET_HARD_FLOAT && IS_VFP_CLASS (CLASS)) \ |
fe2d934b PB |
1317 | ? coproc_secondary_reload_class (MODE, X, FALSE) \ |
1318 | : (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) \ | |
1319 | ? coproc_secondary_reload_class (MODE, X, TRUE) \ | |
5b3e6663 | 1320 | : TARGET_32BIT \ |
9b66ebb1 | 1321 | ? (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \ |
d5b7b3ae RE |
1322 | ? GENERAL_REGS : NO_REGS) \ |
1323 | : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X)) | |
f676971a | 1324 | |
d6b4baa4 | 1325 | /* If we need to load shorts byte-at-a-time, then we need a scratch. */ |
d5b7b3ae | 1326 | #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \ |
fe2d934b | 1327 | /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \ |
00ea1506 | 1328 | ((TARGET_HARD_FLOAT && IS_VFP_CLASS (CLASS)) \ |
fe2d934b PB |
1329 | ? coproc_secondary_reload_class (MODE, X, FALSE) : \ |
1330 | (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) ? \ | |
1331 | coproc_secondary_reload_class (MODE, X, TRUE) : \ | |
0be8bd1a RE |
1332 | (TARGET_32BIT ? \ |
1333 | (((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \ | |
1334 | && CONSTANT_P (X)) \ | |
9b6b54e2 | 1335 | ? GENERAL_REGS : \ |
0be8bd1a | 1336 | (((MODE) == HImode && ! arm_arch4 \ |
d435a4be KT |
1337 | && (MEM_P (X) \ |
1338 | || ((REG_P (X) || GET_CODE (X) == SUBREG) \ | |
0be8bd1a RE |
1339 | && true_regnum (X) == -1))) \ |
1340 | ? GENERAL_REGS : NO_REGS) \ | |
1341 | : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X))) | |
2ce9c1b9 | 1342 | |
35d965d5 RS |
1343 | /* Return the maximum number of consecutive registers |
1344 | needed to represent mode MODE in a register of class CLASS. | |
0be8bd1a RE |
1345 | ARM regs are UNITS_PER_WORD bits. |
1346 | FIXME: Is this true for iWMMX? */ | |
35d965d5 | 1347 | #define CLASS_MAX_NREGS(CLASS, MODE) \ |
0be8bd1a | 1348 | (ARM_NUM_REGS (MODE)) |
9b6b54e2 NC |
1349 | |
1350 | /* If defined, gives a class of registers that cannot be used as the | |
1351 | operand of a SUBREG that changes the mode of the object illegally. */ | |
35d965d5 RS |
1352 | \f |
1353 | /* Stack layout; function entry, exit and calling. */ | |
1354 | ||
1355 | /* Define this if pushing a word on the stack | |
1356 | makes the stack pointer a smaller address. */ | |
1357 | #define STACK_GROWS_DOWNWARD 1 | |
1358 | ||
a4d05547 | 1359 | /* Define this to nonzero if the nominal address of the stack frame |
35d965d5 RS |
1360 | is at the high-address end of the local variables; |
1361 | that is, each additional local variable allocated | |
1362 | goes at a more negative offset in the frame. */ | |
1363 | #define FRAME_GROWS_DOWNWARD 1 | |
1364 | ||
a2503645 RS |
1365 | /* The amount of scratch space needed by _interwork_{r7,r11}_call_via_rN(). |
1366 | When present, it is one word in size, and sits at the top of the frame, | |
1367 | between the soft frame pointer and either r7 or r11. | |
1368 | ||
1369 | We only need _interwork_rM_call_via_rN() for -mcaller-super-interworking, | |
1370 | and only then if some outgoing arguments are passed on the stack. It would | |
1371 | be tempting to also check whether the stack arguments are passed by indirect | |
1372 | calls, but there seems to be no reason in principle why a post-reload pass | |
1373 | couldn't convert a direct call into an indirect one. */ | |
1374 | #define CALLER_INTERWORKING_SLOT_SIZE \ | |
1375 | (TARGET_CALLER_INTERWORKING \ | |
a20c5714 | 1376 | && maybe_ne (crtl->outgoing_args_size, 0) \ |
a2503645 RS |
1377 | ? UNITS_PER_WORD : 0) |
1378 | ||
35d965d5 RS |
1379 | /* If we generate an insn to push BYTES bytes, |
1380 | this says how many the stack pointer really advances by. */ | |
d5b7b3ae | 1381 | /* The push insns do not do this rounding implicitly. |
d6b4baa4 | 1382 | So don't define this. */ |
0c2ca901 | 1383 | /* #define PUSH_ROUNDING(NPUSHED) ROUND_UP_WORD (NPUSHED) */ |
18543a22 ILT |
1384 | |
1385 | /* Define this if the maximum size of all the outgoing args is to be | |
1386 | accumulated and pushed during the prologue. The amount can be | |
38173d38 | 1387 | found in the variable crtl->outgoing_args_size. */ |
6cfc7210 | 1388 | #define ACCUMULATE_OUTGOING_ARGS 1 |
35d965d5 RS |
1389 | |
1390 | /* Offset of first parameter from the argument pointer register value. */ | |
d5b7b3ae | 1391 | #define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0) |
35d965d5 | 1392 | |
9f7bf991 RE |
1393 | /* Amount of memory needed for an untyped call to save all possible return |
1394 | registers. */ | |
1395 | #define APPLY_RESULT_SIZE arm_apply_result_size() | |
1396 | ||
11c1a207 RE |
1397 | /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return |
1398 | values must be in memory. On the ARM, they need only do so if larger | |
d6b4baa4 | 1399 | than a word, or if they contain elements offset from zero in the struct. */ |
11c1a207 RE |
1400 | #define DEFAULT_PCC_STRUCT_RETURN 0 |
1401 | ||
6d3d9133 | 1402 | /* These bits describe the different types of function supported |
112cdef5 | 1403 | by the ARM backend. They are exclusive. i.e. a function cannot be both a |
6d3d9133 NC |
1404 | normal function and an interworked function, for example. Knowing the |
1405 | type of a function is important for determining its prologue and | |
1406 | epilogue sequences. | |
1407 | Note value 7 is currently unassigned. Also note that the interrupt | |
1408 | function types all have bit 2 set, so that they can be tested for easily. | |
1409 | Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the | |
4912a07c | 1410 | machine_function structure is initialized (to zero) func_type will |
6d3d9133 NC |
1411 | default to unknown. This will force the first use of arm_current_func_type |
1412 | to call arm_compute_func_type. */ | |
1413 | #define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */ | |
1414 | #define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */ | |
1415 | #define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */ | |
6d3d9133 NC |
1416 | #define ARM_FT_ISR 4 /* An interrupt service routine. */ |
1417 | #define ARM_FT_FIQ 5 /* A fast interrupt service routine. */ | |
1418 | #define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */ | |
1419 | ||
1420 | #define ARM_FT_TYPE_MASK ((1 << 3) - 1) | |
1421 | ||
1422 | /* In addition functions can have several type modifiers, | |
1423 | outlined by these bit masks: */ | |
1424 | #define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */ | |
1425 | #define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */ | |
1426 | #define ARM_FT_VOLATILE (1 << 4) /* Does not return. */ | |
d6b4baa4 | 1427 | #define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */ |
5b3e6663 | 1428 | #define ARM_FT_STACKALIGN (1 << 6) /* Called with misaligned stack. */ |
97b0656d | 1429 | #define ARM_FT_CMSE_ENTRY (1 << 7) /* ARMv8-M non-secure entry function. */ |
6d3d9133 NC |
1430 | |
1431 | /* Some macros to test these flags. */ | |
1432 | #define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK) | |
1433 | #define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT) | |
1434 | #define IS_VOLATILE(t) (t & ARM_FT_VOLATILE) | |
1435 | #define IS_NAKED(t) (t & ARM_FT_NAKED) | |
1436 | #define IS_NESTED(t) (t & ARM_FT_NESTED) | |
5b3e6663 | 1437 | #define IS_STACKALIGN(t) (t & ARM_FT_STACKALIGN) |
97b0656d | 1438 | #define IS_CMSE_ENTRY(t) (t & ARM_FT_CMSE_ENTRY) |
6d3d9133 | 1439 | |
5848830f PB |
1440 | |
1441 | /* Structure used to hold the function stack frame layout. Offsets are | |
1442 | relative to the stack pointer on function entry. Positive offsets are | |
1443 | in the direction of stack growth. | |
1444 | Only soft_frame is used in thumb mode. */ | |
1445 | ||
d1b38208 | 1446 | typedef struct GTY(()) arm_stack_offsets |
5848830f PB |
1447 | { |
1448 | int saved_args; /* ARG_POINTER_REGNUM. */ | |
1449 | int frame; /* ARM_HARD_FRAME_POINTER_REGNUM. */ | |
1450 | int saved_regs; | |
1451 | int soft_frame; /* FRAME_POINTER_REGNUM. */ | |
2591db65 | 1452 | int locals_base; /* THUMB_HARD_FRAME_POINTER_REGNUM. */ |
5848830f | 1453 | int outgoing_args; /* STACK_POINTER_REGNUM. */ |
954954d1 | 1454 | unsigned int saved_regs_mask; |
5848830f PB |
1455 | } |
1456 | arm_stack_offsets; | |
1457 | ||
2c0122c9 | 1458 | #if !defined(GENERATOR_FILE) && !defined (USED_FOR_TARGET) |
6d3d9133 NC |
1459 | /* A C structure for machine-specific, per-function data. |
1460 | This is added to the cfun structure. */ | |
d1b38208 | 1461 | typedef struct GTY(()) machine_function |
d5b7b3ae | 1462 | { |
6bc82793 | 1463 | /* Additional stack adjustment in __builtin_eh_throw. */ |
e2500fed | 1464 | rtx eh_epilogue_sp_ofs; |
d5b7b3ae RE |
1465 | /* Records if LR has to be saved for far jumps. */ |
1466 | int far_jump_used; | |
1467 | /* Records if ARG_POINTER was ever live. */ | |
1468 | int arg_pointer_live; | |
6f7ebcbb NC |
1469 | /* Records if the save of LR has been eliminated. */ |
1470 | int lr_save_eliminated; | |
0977774b | 1471 | /* The size of the stack frame. Only valid after reload. */ |
5848830f | 1472 | arm_stack_offsets stack_offsets; |
6d3d9133 NC |
1473 | /* Records the type of the current function. */ |
1474 | unsigned long func_type; | |
3cb66fd7 NC |
1475 | /* Record if the function has a variable argument list. */ |
1476 | int uses_anonymous_args; | |
5a9335ef NC |
1477 | /* Records if sibcalls are blocked because an argument |
1478 | register is needed to preserve stack alignment. */ | |
1479 | int sibcall_blocked; | |
020a4035 RE |
1480 | /* The PIC register for this function. This might be a pseudo. */ |
1481 | rtx pic_reg; | |
b12a00f1 | 1482 | /* Labels for per-function Thumb call-via stubs. One per potential calling |
57ecec57 PB |
1483 | register. We can never call via LR or PC. We can call via SP if a |
1484 | trampoline happens to be on the top of the stack. */ | |
1485 | rtx call_via[14]; | |
934c2060 RR |
1486 | /* Set to 1 when a return insn is output, this means that the epilogue |
1487 | is not needed. */ | |
1488 | int return_used_this_function; | |
906668bb BS |
1489 | /* When outputting Thumb-1 code, record the last insn that provides |
1490 | information about condition codes, and the comparison operands. */ | |
1491 | rtx thumb1_cc_insn; | |
1492 | rtx thumb1_cc_op0; | |
1493 | rtx thumb1_cc_op1; | |
1494 | /* Also record the CC mode that is supported. */ | |
ef4bddc2 | 1495 | machine_mode thumb1_cc_mode; |
b0419491 TG |
1496 | /* Set to 1 after arm_reorg has started. */ |
1497 | int after_arm_reorg; | |
bb4ac03b SD |
1498 | /* The number of bytes used to store the static chain register on the |
1499 | stack, above the stack frame. */ | |
1500 | int static_chain_stack_bytes; | |
6d3d9133 NC |
1501 | } |
1502 | machine_function; | |
906668bb | 1503 | #endif |
d5b7b3ae | 1504 | |
cf16f980 | 1505 | #define ARM_Q_BIT_READ (arm_q_bit_access ()) |
16155ccf | 1506 | #define ARM_GE_BITS_READ (arm_ge_bits_access ()) |
cf16f980 | 1507 | |
b12a00f1 | 1508 | /* As in the machine_function, a global set of call-via labels, for code |
d6b5193b | 1509 | that is in text_section. */ |
57ecec57 | 1510 | extern GTY(()) rtx thumb_call_via_label[14]; |
b12a00f1 | 1511 | |
390b17c2 RE |
1512 | /* The number of potential ways of assigning to a co-processor. */ |
1513 | #define ARM_NUM_COPROC_SLOTS 1 | |
1514 | ||
1515 | /* Enumeration of procedure calling standard variants. We don't really | |
1516 | support all of these yet. */ | |
1517 | enum arm_pcs | |
1518 | { | |
1519 | ARM_PCS_AAPCS, /* Base standard AAPCS. */ | |
1520 | ARM_PCS_AAPCS_VFP, /* Use VFP registers for floating point values. */ | |
1521 | ARM_PCS_AAPCS_IWMMXT, /* Use iWMMXT registers for vectors. */ | |
1522 | /* This must be the last AAPCS variant. */ | |
1523 | ARM_PCS_AAPCS_LOCAL, /* Private call within this compilation unit. */ | |
1524 | ARM_PCS_ATPCS, /* ATPCS. */ | |
1525 | ARM_PCS_APCS, /* APCS (legacy Linux etc). */ | |
1526 | ARM_PCS_UNKNOWN | |
1527 | }; | |
1528 | ||
12ffc7d5 CLT |
1529 | /* Default procedure calling standard of current compilation unit. */ |
1530 | extern enum arm_pcs arm_pcs_default; | |
1531 | ||
2c0122c9 | 1532 | #if !defined (USED_FOR_TARGET) |
82e9d970 | 1533 | /* A C type for declaring a variable that is used as the first argument of |
390b17c2 | 1534 | `FUNCTION_ARG' and other related values. */ |
82e9d970 PB |
1535 | typedef struct |
1536 | { | |
d5b7b3ae | 1537 | /* This is the number of registers of arguments scanned so far. */ |
82e9d970 | 1538 | int nregs; |
5a9335ef NC |
1539 | /* This is the number of iWMMXt register arguments scanned so far. */ |
1540 | int iwmmxt_nregs; | |
1541 | int named_count; | |
1542 | int nargs; | |
390b17c2 RE |
1543 | /* Which procedure call variant to use for this call. */ |
1544 | enum arm_pcs pcs_variant; | |
1545 | ||
1546 | /* AAPCS related state tracking. */ | |
1547 | int aapcs_arg_processed; /* No need to lay out this argument again. */ | |
1548 | int aapcs_cprc_slot; /* Index of co-processor rules to handle | |
1549 | this argument, or -1 if using core | |
1550 | registers. */ | |
1551 | int aapcs_ncrn; | |
1552 | int aapcs_next_ncrn; | |
1553 | rtx aapcs_reg; /* Register assigned to this argument. */ | |
1554 | int aapcs_partial; /* How many bytes are passed in regs (if | |
1555 | split between core regs and stack. | |
1556 | Zero otherwise. */ | |
1557 | int aapcs_cprc_failed[ARM_NUM_COPROC_SLOTS]; | |
1558 | int can_split; /* Argument can be split between core regs | |
1559 | and the stack. */ | |
1560 | /* Private data for tracking VFP register allocation */ | |
1561 | unsigned aapcs_vfp_regs_free; | |
1562 | unsigned aapcs_vfp_reg_alloc; | |
1563 | int aapcs_vfp_rcount; | |
46107b99 | 1564 | MACHMODE aapcs_vfp_rmode; |
d5b7b3ae | 1565 | } CUMULATIVE_ARGS; |
2c0122c9 | 1566 | #endif |
82e9d970 | 1567 | |
866af8a9 | 1568 | #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \ |
76b0cbf8 | 1569 | (arm_pad_reg_upward (MODE, TYPE, FIRST) ? PAD_UPWARD : PAD_DOWNWARD) |
866af8a9 JB |
1570 | |
1571 | /* For AAPCS, padding should never be below the argument. For other ABIs, | |
1572 | * mimic the default. */ | |
1573 | #define PAD_VARARGS_DOWN \ | |
1574 | ((TARGET_AAPCS_BASED) ? 0 : BYTES_BIG_ENDIAN) | |
1575 | ||
35d965d5 RS |
1576 | /* Initialize a variable CUM of type CUMULATIVE_ARGS |
1577 | for a call to a function whose data type is FNTYPE. | |
1578 | For a library call, FNTYPE is 0. | |
1579 | On the ARM, the offset starts at 0. */ | |
0f6937fe | 1580 | #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ |
563a317a | 1581 | arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL)) |
35d965d5 | 1582 | |
35d965d5 RS |
1583 | /* 1 if N is a possible register number for function argument passing. |
1584 | On the ARM, r0-r3 are used to pass args. */ | |
390b17c2 RE |
1585 | #define FUNCTION_ARG_REGNO_P(REGNO) \ |
1586 | (IN_RANGE ((REGNO), 0, 3) \ | |
00ea1506 | 1587 | || (TARGET_AAPCS_BASED && TARGET_HARD_FLOAT \ |
390b17c2 RE |
1588 | && IN_RANGE ((REGNO), FIRST_VFP_REGNUM, FIRST_VFP_REGNUM + 15)) \ |
1589 | || (TARGET_IWMMXT_ABI \ | |
5848830f | 1590 | && IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9))) |
35d965d5 | 1591 | |
f99fce0c | 1592 | \f |
afef3d7a | 1593 | /* If your target environment doesn't prefix user functions with an |
96a3900d | 1594 | underscore, you may wish to re-define this to prevent any conflicts. */ |
afef3d7a NC |
1595 | #ifndef ARM_MCOUNT_NAME |
1596 | #define ARM_MCOUNT_NAME "*mcount" | |
1597 | #endif | |
1598 | ||
1599 | /* Call the function profiler with a given profile label. The Acorn | |
1600 | compiler puts this BEFORE the prolog but gcc puts it afterwards. | |
1601 | On the ARM the full profile code will look like: | |
1602 | .data | |
1603 | LP1 | |
1604 | .word 0 | |
1605 | .text | |
1606 | mov ip, lr | |
1607 | bl mcount | |
1608 | .word LP1 | |
1609 | ||
1610 | profile_function() in final.c outputs the .data section, FUNCTION_PROFILER | |
1611 | will output the .text section. | |
1612 | ||
1613 | The ``mov ip,lr'' seems like a good idea to stick with cc convention. | |
59be6073 AN |
1614 | ``prof'' doesn't seem to mind about this! |
1615 | ||
1616 | Note - this version of the code is designed to work in both ARM and | |
1617 | Thumb modes. */ | |
be393ecf | 1618 | #ifndef ARM_FUNCTION_PROFILER |
d5b7b3ae | 1619 | #define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \ |
6cfc7210 NC |
1620 | { \ |
1621 | char temp[20]; \ | |
1622 | rtx sym; \ | |
1623 | \ | |
dd18ae56 | 1624 | asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \ |
d5b7b3ae | 1625 | IP_REGNUM, LR_REGNUM); \ |
6cfc7210 NC |
1626 | assemble_name (STREAM, ARM_MCOUNT_NAME); \ |
1627 | fputc ('\n', STREAM); \ | |
1628 | ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \ | |
f1c25d3b | 1629 | sym = gen_rtx_SYMBOL_REF (Pmode, temp); \ |
301d03af | 1630 | assemble_aligned_integer (UNITS_PER_WORD, sym); \ |
35d965d5 | 1631 | } |
be393ecf | 1632 | #endif |
35d965d5 | 1633 | |
59be6073 | 1634 | #ifdef THUMB_FUNCTION_PROFILER |
d5b7b3ae RE |
1635 | #define FUNCTION_PROFILER(STREAM, LABELNO) \ |
1636 | if (TARGET_ARM) \ | |
1637 | ARM_FUNCTION_PROFILER (STREAM, LABELNO) \ | |
1638 | else \ | |
1639 | THUMB_FUNCTION_PROFILER (STREAM, LABELNO) | |
59be6073 AN |
1640 | #else |
1641 | #define FUNCTION_PROFILER(STREAM, LABELNO) \ | |
1642 | ARM_FUNCTION_PROFILER (STREAM, LABELNO) | |
1643 | #endif | |
d5b7b3ae | 1644 | |
35d965d5 RS |
1645 | /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, |
1646 | the stack pointer does not matter. The value is tested only in | |
1647 | functions that have frame pointers. | |
1648 | No definition is equivalent to always zero. | |
1649 | ||
1650 | On the ARM, the function epilogue recovers the stack pointer from the | |
1651 | frame. */ | |
1652 | #define EXIT_IGNORE_STACK 1 | |
1653 | ||
2b261262 | 1654 | #define EPILOGUE_USES(REGNO) (epilogue_completed && (REGNO) == LR_REGNUM) |
c7861455 | 1655 | |
35d965d5 RS |
1656 | /* Determine if the epilogue should be output as RTL. |
1657 | You should override this if you define FUNCTION_EXTRA_EPILOGUE. */ | |
d5b7b3ae | 1658 | #define USE_RETURN_INSN(ISCOND) \ |
7c19c715 | 1659 | (TARGET_32BIT ? use_return_insn (ISCOND, NULL) : 0) |
ff9940b0 RE |
1660 | |
1661 | /* Definitions for register eliminations. | |
1662 | ||
1663 | This is an array of structures. Each structure initializes one pair | |
1664 | of eliminable registers. The "from" register number is given first, | |
1665 | followed by "to". Eliminations of the same "from" register are listed | |
1666 | in order of preference. | |
1667 | ||
1668 | We have two registers that can be eliminated on the ARM. First, the | |
1669 | arg pointer register can often be eliminated in favor of the stack | |
1670 | pointer register. Secondly, the pseudo frame pointer register can always | |
1671 | be eliminated; it is replaced with either the stack or the real frame | |
d5b7b3ae | 1672 | pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM |
d6a7951f | 1673 | because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */ |
ff9940b0 | 1674 | |
d5b7b3ae RE |
1675 | #define ELIMINABLE_REGS \ |
1676 | {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\ | |
1677 | { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\ | |
1678 | { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\ | |
1679 | { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\ | |
1680 | { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\ | |
1681 | { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\ | |
1682 | { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }} | |
ff9940b0 | 1683 | |
d5b7b3ae RE |
1684 | /* Define the offset between two registers, one to be eliminated, and the |
1685 | other its replacement, at the start of a routine. */ | |
d5b7b3ae RE |
1686 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ |
1687 | if (TARGET_ARM) \ | |
5848830f | 1688 | (OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \ |
d5b7b3ae | 1689 | else \ |
5848830f PB |
1690 | (OFFSET) = thumb_compute_initial_elimination_offset (FROM, TO) |
1691 | ||
d5b7b3ae RE |
1692 | /* Special case handling of the location of arguments passed on the stack. */ |
1693 | #define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr) | |
f676971a | 1694 | |
d5b7b3ae RE |
1695 | /* Initialize data used by insn expanders. This is called from insn_emit, |
1696 | once for every function before code is generated. */ | |
1697 | #define INIT_EXPANDERS arm_init_expanders () | |
1698 | ||
35d965d5 | 1699 | /* Length in units of the trampoline for entering a nested function. */ |
bc87cffb | 1700 | #define TRAMPOLINE_SIZE (TARGET_FDPIC ? 32 : (TARGET_32BIT ? 16 : 20)) |
35d965d5 | 1701 | |
006946e4 JM |
1702 | /* Alignment required for a trampoline in bits. */ |
1703 | #define TRAMPOLINE_ALIGNMENT 32 | |
35d965d5 RS |
1704 | \f |
1705 | /* Addressing modes, and classification of registers for them. */ | |
3cd45774 | 1706 | #define HAVE_POST_INCREMENT 1 |
5b3e6663 PB |
1707 | #define HAVE_PRE_INCREMENT TARGET_32BIT |
1708 | #define HAVE_POST_DECREMENT TARGET_32BIT | |
1709 | #define HAVE_PRE_DECREMENT TARGET_32BIT | |
1710 | #define HAVE_PRE_MODIFY_DISP TARGET_32BIT | |
1711 | #define HAVE_POST_MODIFY_DISP TARGET_32BIT | |
1712 | #define HAVE_PRE_MODIFY_REG TARGET_32BIT | |
1713 | #define HAVE_POST_MODIFY_REG TARGET_32BIT | |
35d965d5 | 1714 | |
8875e939 RR |
1715 | enum arm_auto_incmodes |
1716 | { | |
1717 | ARM_POST_INC, | |
1718 | ARM_PRE_INC, | |
1719 | ARM_POST_DEC, | |
1720 | ARM_PRE_DEC | |
1721 | }; | |
1722 | ||
1723 | #define ARM_AUTOINC_VALID_FOR_MODE_P(mode, code) \ | |
1724 | (TARGET_32BIT && arm_autoinc_modes_ok_p (mode, code)) | |
1725 | #define USE_LOAD_POST_INCREMENT(mode) \ | |
1726 | ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_POST_INC) | |
1727 | #define USE_LOAD_PRE_INCREMENT(mode) \ | |
1728 | ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_PRE_INC) | |
1729 | #define USE_LOAD_POST_DECREMENT(mode) \ | |
1730 | ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_POST_DEC) | |
1731 | #define USE_LOAD_PRE_DECREMENT(mode) \ | |
1732 | ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_PRE_DEC) | |
1733 | ||
1734 | #define USE_STORE_PRE_DECREMENT(mode) USE_LOAD_PRE_DECREMENT(mode) | |
1735 | #define USE_STORE_PRE_INCREMENT(mode) USE_LOAD_PRE_INCREMENT(mode) | |
1736 | #define USE_STORE_POST_DECREMENT(mode) USE_LOAD_POST_DECREMENT(mode) | |
1737 | #define USE_STORE_POST_INCREMENT(mode) USE_LOAD_POST_INCREMENT(mode) | |
1738 | ||
35d965d5 RS |
1739 | /* Macros to check register numbers against specific register classes. */ |
1740 | ||
1741 | /* These assume that REGNO is a hard or pseudo reg number. | |
1742 | They give nonzero only if REGNO is a hard reg of the suitable class | |
378056b2 | 1743 | or a pseudo reg currently allocated to a suitable hard reg. */ |
d5b7b3ae | 1744 | #define TEST_REGNO(R, TEST, VALUE) \ |
3a3a8086 KT |
1745 | ((R TEST VALUE) \ |
1746 | || (reg_renumber && ((unsigned) reg_renumber[R] TEST VALUE))) | |
d5b7b3ae | 1747 | |
5b3e6663 | 1748 | /* Don't allow the pc to be used. */ |
f1008e52 RE |
1749 | #define ARM_REGNO_OK_FOR_BASE_P(REGNO) \ |
1750 | (TEST_REGNO (REGNO, <, PC_REGNUM) \ | |
1751 | || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \ | |
1752 | || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM)) | |
1753 | ||
5b3e6663 | 1754 | #define THUMB1_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \ |
f1008e52 RE |
1755 | (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \ |
1756 | || (GET_MODE_SIZE (MODE) >= 4 \ | |
1757 | && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM))) | |
1758 | ||
1759 | #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \ | |
5b3e6663 PB |
1760 | (TARGET_THUMB1 \ |
1761 | ? THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \ | |
f1008e52 RE |
1762 | : ARM_REGNO_OK_FOR_BASE_P (REGNO)) |
1763 | ||
888d2cd6 | 1764 | /* Nonzero if X can be the base register in a reg+reg addressing mode. |
67914693 | 1765 | For Thumb, we cannot use SP + reg, so reject SP. */ |
888d2cd6 | 1766 | #define REGNO_MODE_OK_FOR_REG_BASE_P(X, MODE) \ |
f5c630c3 | 1767 | REGNO_MODE_OK_FOR_BASE_P (X, QImode) |
888d2cd6 | 1768 | |
f1008e52 RE |
1769 | /* For ARM code, we don't care about the mode, but for Thumb, the index |
1770 | must be suitable for use in a QImode load. */ | |
d5b7b3ae | 1771 | #define REGNO_OK_FOR_INDEX_P(REGNO) \ |
f5c630c3 PB |
1772 | (REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode) \ |
1773 | && !TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)) | |
35d965d5 RS |
1774 | |
1775 | /* Maximum number of registers that can appear in a valid memory address. | |
d6b4baa4 | 1776 | Shifts in addresses can't be by a register. */ |
ff9940b0 | 1777 | #define MAX_REGS_PER_ADDRESS 2 |
35d965d5 RS |
1778 | |
1779 | /* Recognize any constant value that is a valid address. */ | |
1780 | /* XXX We can address any constant, eventually... */ | |
5b3e6663 | 1781 | /* ??? Should the TARGET_ARM here also apply to thumb2? */ |
008cf58a RE |
1782 | #define CONSTANT_ADDRESS_P(X) \ |
1783 | (GET_CODE (X) == SYMBOL_REF \ | |
1784 | && (CONSTANT_POOL_ADDRESS_P (X) \ | |
d5b7b3ae | 1785 | || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X)))) |
35d965d5 | 1786 | |
8426b956 RS |
1787 | /* True if SYMBOL + OFFSET constants must refer to something within |
1788 | SYMBOL's section. */ | |
1789 | #define ARM_OFFSETS_MUST_BE_WITHIN_SECTIONS_P 0 | |
1790 | ||
571191af PB |
1791 | /* Nonzero if all target requires all absolute relocations be R_ARM_ABS32. */ |
1792 | #ifndef TARGET_DEFAULT_WORD_RELOCATIONS | |
1793 | #define TARGET_DEFAULT_WORD_RELOCATIONS 0 | |
1794 | #endif | |
1795 | ||
c27ba912 DM |
1796 | #ifndef SUBTARGET_NAME_ENCODING_LENGTHS |
1797 | #define SUBTARGET_NAME_ENCODING_LENGTHS | |
1798 | #endif | |
1799 | ||
6bc82793 | 1800 | /* This is a C fragment for the inside of a switch statement. |
c27ba912 DM |
1801 | Each case label should return the number of characters to |
1802 | be stripped from the start of a function's name, if that | |
1803 | name starts with the indicated character. */ | |
1804 | #define ARM_NAME_ENCODING_LENGTHS \ | |
00fdafef | 1805 | case '*': return 1; \ |
f676971a | 1806 | SUBTARGET_NAME_ENCODING_LENGTHS |
c27ba912 | 1807 | |
c27ba912 DM |
1808 | /* This is how to output a reference to a user-level label named NAME. |
1809 | `assemble_name' uses this. */ | |
e5951263 | 1810 | #undef ASM_OUTPUT_LABELREF |
c27ba912 | 1811 | #define ASM_OUTPUT_LABELREF(FILE, NAME) \ |
e1944073 | 1812 | arm_asm_output_labelref (FILE, NAME) |
c27ba912 | 1813 | |
7a085dce | 1814 | /* Output IT instructions for conditionally executed Thumb-2 instructions. */ |
5b3e6663 PB |
1815 | #define ASM_OUTPUT_OPCODE(STREAM, PTR) \ |
1816 | if (TARGET_THUMB2) \ | |
1817 | thumb2_asm_output_opcode (STREAM); | |
1818 | ||
7abc66b1 JB |
1819 | /* The EABI specifies that constructors should go in .init_array. |
1820 | Other targets use .ctors for compatibility. */ | |
88c6057f | 1821 | #ifndef ARM_EABI_CTORS_SECTION_OP |
7abc66b1 JB |
1822 | #define ARM_EABI_CTORS_SECTION_OP \ |
1823 | "\t.section\t.init_array,\"aw\",%init_array" | |
88c6057f MM |
1824 | #endif |
1825 | #ifndef ARM_EABI_DTORS_SECTION_OP | |
7abc66b1 JB |
1826 | #define ARM_EABI_DTORS_SECTION_OP \ |
1827 | "\t.section\t.fini_array,\"aw\",%fini_array" | |
88c6057f | 1828 | #endif |
7abc66b1 JB |
1829 | #define ARM_CTORS_SECTION_OP \ |
1830 | "\t.section\t.ctors,\"aw\",%progbits" | |
1831 | #define ARM_DTORS_SECTION_OP \ | |
1832 | "\t.section\t.dtors,\"aw\",%progbits" | |
1833 | ||
1834 | /* Define CTORS_SECTION_ASM_OP. */ | |
1835 | #undef CTORS_SECTION_ASM_OP | |
1836 | #undef DTORS_SECTION_ASM_OP | |
1837 | #ifndef IN_LIBGCC2 | |
1838 | # define CTORS_SECTION_ASM_OP \ | |
1839 | (TARGET_AAPCS_BASED ? ARM_EABI_CTORS_SECTION_OP : ARM_CTORS_SECTION_OP) | |
1840 | # define DTORS_SECTION_ASM_OP \ | |
1841 | (TARGET_AAPCS_BASED ? ARM_EABI_DTORS_SECTION_OP : ARM_DTORS_SECTION_OP) | |
1842 | #else /* !defined (IN_LIBGCC2) */ | |
1843 | /* In libgcc, CTORS_SECTION_ASM_OP must be a compile-time constant, | |
1844 | so we cannot use the definition above. */ | |
1845 | # ifdef __ARM_EABI__ | |
1846 | /* The .ctors section is not part of the EABI, so we do not define | |
1847 | CTORS_SECTION_ASM_OP when in libgcc; that prevents crtstuff | |
1848 | from trying to use it. We do define it when doing normal | |
1849 | compilation, as .init_array can be used instead of .ctors. */ | |
1850 | /* There is no need to emit begin or end markers when using | |
1851 | init_array; the dynamic linker will compute the size of the | |
1852 | array itself based on special symbols created by the static | |
1853 | linker. However, we do need to arrange to set up | |
1854 | exception-handling here. */ | |
1855 | # define CTOR_LIST_BEGIN asm (ARM_EABI_CTORS_SECTION_OP) | |
1856 | # define CTOR_LIST_END /* empty */ | |
1857 | # define DTOR_LIST_BEGIN asm (ARM_EABI_DTORS_SECTION_OP) | |
1858 | # define DTOR_LIST_END /* empty */ | |
1859 | # else /* !defined (__ARM_EABI__) */ | |
1860 | # define CTORS_SECTION_ASM_OP ARM_CTORS_SECTION_OP | |
1861 | # define DTORS_SECTION_ASM_OP ARM_DTORS_SECTION_OP | |
1862 | # endif /* !defined (__ARM_EABI__) */ | |
1863 | #endif /* !defined (IN_LIBCC2) */ | |
1864 | ||
1e731102 MM |
1865 | /* True if the operating system can merge entities with vague linkage |
1866 | (e.g., symbols in COMDAT group) during dynamic linking. */ | |
1867 | #ifndef TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P | |
1868 | #define TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P true | |
1869 | #endif | |
1870 | ||
617a1b71 PB |
1871 | #define ARM_OUTPUT_FN_UNWIND(F, PROLOGUE) arm_output_fn_unwind (F, PROLOGUE) |
1872 | ||
35d965d5 RS |
1873 | /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx |
1874 | and check its validity for a certain class. | |
1875 | We have two alternate definitions for each of them. | |
1876 | The usual definition accepts all pseudo regs; the other rejects | |
1877 | them unless they have been allocated suitable hard regs. | |
5b3e6663 | 1878 | The symbol REG_OK_STRICT causes the latter definition to be used. |
7a085dce | 1879 | Thumb-2 has the same restrictions as arm. */ |
35d965d5 | 1880 | #ifndef REG_OK_STRICT |
ff9940b0 | 1881 | |
f1008e52 RE |
1882 | #define ARM_REG_OK_FOR_BASE_P(X) \ |
1883 | (REGNO (X) <= LAST_ARM_REGNUM \ | |
1884 | || REGNO (X) >= FIRST_PSEUDO_REGISTER \ | |
1885 | || REGNO (X) == FRAME_POINTER_REGNUM \ | |
1886 | || REGNO (X) == ARG_POINTER_REGNUM) | |
ff9940b0 | 1887 | |
f5c630c3 PB |
1888 | #define ARM_REG_OK_FOR_INDEX_P(X) \ |
1889 | ((REGNO (X) <= LAST_ARM_REGNUM \ | |
1890 | && REGNO (X) != STACK_POINTER_REGNUM) \ | |
1891 | || REGNO (X) >= FIRST_PSEUDO_REGISTER \ | |
1892 | || REGNO (X) == FRAME_POINTER_REGNUM \ | |
1893 | || REGNO (X) == ARG_POINTER_REGNUM) | |
1894 | ||
5b3e6663 | 1895 | #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \ |
f1008e52 RE |
1896 | (REGNO (X) <= LAST_LO_REGNUM \ |
1897 | || REGNO (X) >= FIRST_PSEUDO_REGISTER \ | |
1898 | || (GET_MODE_SIZE (MODE) >= 4 \ | |
1899 | && (REGNO (X) == STACK_POINTER_REGNUM \ | |
1900 | || (X) == hard_frame_pointer_rtx \ | |
1901 | || (X) == arg_pointer_rtx))) | |
ff9940b0 | 1902 | |
76a318e9 RE |
1903 | #define REG_STRICT_P 0 |
1904 | ||
d5b7b3ae | 1905 | #else /* REG_OK_STRICT */ |
ff9940b0 | 1906 | |
f1008e52 RE |
1907 | #define ARM_REG_OK_FOR_BASE_P(X) \ |
1908 | ARM_REGNO_OK_FOR_BASE_P (REGNO (X)) | |
ff9940b0 | 1909 | |
f5c630c3 PB |
1910 | #define ARM_REG_OK_FOR_INDEX_P(X) \ |
1911 | ARM_REGNO_OK_FOR_INDEX_P (REGNO (X)) | |
1912 | ||
5b3e6663 PB |
1913 | #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \ |
1914 | THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE) | |
ff9940b0 | 1915 | |
76a318e9 RE |
1916 | #define REG_STRICT_P 1 |
1917 | ||
d5b7b3ae | 1918 | #endif /* REG_OK_STRICT */ |
f1008e52 RE |
1919 | |
1920 | /* Now define some helpers in terms of the above. */ | |
1921 | ||
1922 | #define REG_MODE_OK_FOR_BASE_P(X, MODE) \ | |
5b3e6663 PB |
1923 | (TARGET_THUMB1 \ |
1924 | ? THUMB1_REG_MODE_OK_FOR_BASE_P (X, MODE) \ | |
f1008e52 RE |
1925 | : ARM_REG_OK_FOR_BASE_P (X)) |
1926 | ||
5b3e6663 | 1927 | /* For 16-bit Thumb, a valid index register is anything that can be used in |
f1008e52 | 1928 | a byte load instruction. */ |
5b3e6663 PB |
1929 | #define THUMB1_REG_OK_FOR_INDEX_P(X) \ |
1930 | THUMB1_REG_MODE_OK_FOR_BASE_P (X, QImode) | |
f1008e52 RE |
1931 | |
1932 | /* Nonzero if X is a hard reg that can be used as an index | |
1933 | or if it is a pseudo reg. On the Thumb, the stack pointer | |
1934 | is not suitable. */ | |
1935 | #define REG_OK_FOR_INDEX_P(X) \ | |
5b3e6663 PB |
1936 | (TARGET_THUMB1 \ |
1937 | ? THUMB1_REG_OK_FOR_INDEX_P (X) \ | |
f1008e52 RE |
1938 | : ARM_REG_OK_FOR_INDEX_P (X)) |
1939 | ||
888d2cd6 | 1940 | /* Nonzero if X can be the base register in a reg+reg addressing mode. |
67914693 | 1941 | For Thumb, we cannot use SP + reg, so reject SP. */ |
888d2cd6 DJ |
1942 | #define REG_MODE_OK_FOR_REG_BASE_P(X, MODE) \ |
1943 | REG_OK_FOR_INDEX_P (X) | |
35d965d5 | 1944 | \f |
f1008e52 | 1945 | #define ARM_BASE_REGISTER_RTX_P(X) \ |
d435a4be | 1946 | (REG_P (X) && ARM_REG_OK_FOR_BASE_P (X)) |
35d965d5 | 1947 | |
f1008e52 | 1948 | #define ARM_INDEX_REGISTER_RTX_P(X) \ |
d435a4be | 1949 | (REG_P (X) && ARM_REG_OK_FOR_INDEX_P (X)) |
35d965d5 | 1950 | \f |
35d965d5 RS |
1951 | /* Specify the machine mode that this machine uses |
1952 | for the index in the tablejump instruction. */ | |
d5b7b3ae | 1953 | #define CASE_VECTOR_MODE Pmode |
35d965d5 | 1954 | |
e24f6408 CL |
1955 | #define CASE_VECTOR_PC_RELATIVE ((TARGET_THUMB2 \ |
1956 | || (TARGET_THUMB1 \ | |
1957 | && (optimize_size || flag_pic))) \ | |
1958 | && (!target_pure_code)) | |
1959 | ||
907dd0c7 RE |
1960 | |
1961 | #define CASE_VECTOR_SHORTEN_MODE(min, max, body) \ | |
83c3a2d8 | 1962 | (TARGET_THUMB1 \ |
907dd0c7 RE |
1963 | ? (min >= 0 && max < 512 \ |
1964 | ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 1, QImode) \ | |
1965 | : min >= -256 && max < 256 \ | |
1966 | ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, QImode) \ | |
1967 | : min >= 0 && max < 8192 \ | |
1968 | ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 1, HImode) \ | |
1969 | : min >= -4096 && max < 4096 \ | |
1970 | ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, HImode) \ | |
1971 | : SImode) \ | |
10c241af | 1972 | : ((min < 0 || max >= 0x20000 || !TARGET_THUMB2) ? SImode \ |
907dd0c7 RE |
1973 | : (max >= 0x200) ? HImode \ |
1974 | : QImode)) | |
5b3e6663 | 1975 | |
ff9940b0 RE |
1976 | /* signed 'char' is most compatible, but RISC OS wants it unsigned. |
1977 | unsigned is probably best, but may break some code. */ | |
1978 | #ifndef DEFAULT_SIGNED_CHAR | |
3967692c | 1979 | #define DEFAULT_SIGNED_CHAR 0 |
35d965d5 RS |
1980 | #endif |
1981 | ||
35d965d5 | 1982 | /* Max number of bytes we can move from memory to memory |
d17ce9af TG |
1983 | in one reasonably fast instruction. */ |
1984 | #define MOVE_MAX 4 | |
35d965d5 | 1985 | |
d19fb8e3 | 1986 | #undef MOVE_RATIO |
e04ad03d | 1987 | #define MOVE_RATIO(speed) (arm_tune_xscale ? 4 : 2) |
d19fb8e3 | 1988 | |
ff9940b0 RE |
1989 | /* Define if operations between registers always perform the operation |
1990 | on the full register even if a narrower mode is specified. */ | |
9e11bfef | 1991 | #define WORD_REGISTER_OPERATIONS 1 |
ff9940b0 RE |
1992 | |
1993 | /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD | |
1994 | will either zero-extend or sign-extend. The value of this macro should | |
1995 | be the code that says which one of the two operations is implicitly | |
f822d252 | 1996 | done, UNKNOWN if none. */ |
9c872872 | 1997 | #define LOAD_EXTEND_OP(MODE) \ |
d5b7b3ae RE |
1998 | (TARGET_THUMB ? ZERO_EXTEND : \ |
1999 | ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \ | |
f822d252 | 2000 | : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : UNKNOWN))) |
ff9940b0 | 2001 | |
35d965d5 RS |
2002 | /* Nonzero if access to memory by bytes is slow and undesirable. */ |
2003 | #define SLOW_BYTE_ACCESS 0 | |
2004 | ||
2005 | /* Immediate shift counts are truncated by the output routines (or was it | |
2006 | the assembler?). Shift counts in a register are truncated by ARM. Note | |
2007 | that the native compiler puts too large (> 32) immediate shift counts | |
2008 | into a register and shifts by the register, letting the ARM decide what | |
2009 | to do instead of doing that itself. */ | |
ff9940b0 RE |
2010 | /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that |
2011 | code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y). | |
2012 | On the arm, Y in a register is used modulo 256 for the shift. Only for | |
d6b4baa4 | 2013 | rotates is modulo 32 used. */ |
ff9940b0 | 2014 | /* #define SHIFT_COUNT_TRUNCATED 1 */ |
35d965d5 | 2015 | |
35d965d5 RS |
2016 | /* Calling from registers is a massive pain. */ |
2017 | #define NO_FUNCTION_CSE 1 | |
2018 | ||
35d965d5 RS |
2019 | /* The machine modes of pointers and functions */ |
2020 | #define Pmode SImode | |
2021 | #define FUNCTION_MODE Pmode | |
2022 | ||
d5b7b3ae RE |
2023 | #define ARM_FRAME_RTX(X) \ |
2024 | ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \ | |
3967692c RE |
2025 | || (X) == arg_pointer_rtx) |
2026 | ||
ff9940b0 | 2027 | /* Try to generate sequences that don't involve branches, we can then use |
a51fb17f | 2028 | conditional instructions. */ |
227e5798 CL |
2029 | #define BRANCH_COST(speed_p, predictable_p) \ |
2030 | ((arm_branch_cost != -1) ? arm_branch_cost : \ | |
2031 | (current_tune->branch_cost (speed_p, predictable_p))) | |
153668ec | 2032 | |
a51fb17f | 2033 | /* False if short circuit operation is preferred. */ |
52c266ba RE |
2034 | #define LOGICAL_OP_NON_SHORT_CIRCUIT \ |
2035 | ((optimize_size) \ | |
2036 | ? (TARGET_THUMB ? false : true) \ | |
4cbd1e61 RR |
2037 | : TARGET_THUMB ? static_cast<bool> (current_tune->logical_op_non_short_circuit_thumb) \ |
2038 | : static_cast<bool> (current_tune->logical_op_non_short_circuit_arm)) | |
a51fb17f | 2039 | |
7a801826 RE |
2040 | \f |
2041 | /* Position Independent Code. */ | |
2042 | /* We decide which register to use based on the compilation options and | |
2043 | the assembler in use; this is more general than the APCS restriction of | |
2044 | using sb (r9) all the time. */ | |
020a4035 | 2045 | extern unsigned arm_pic_register; |
7a801826 RE |
2046 | |
2047 | /* The register number of the register used to address a table of static | |
2048 | data addresses in memory. */ | |
2049 | #define PIC_OFFSET_TABLE_REGNUM arm_pic_register | |
2050 | ||
8b63716e CL |
2051 | /* For FDPIC, the FDPIC register is call-clobbered (otherwise PLT |
2052 | entries would need to handle saving and restoring it). */ | |
2053 | #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED TARGET_FDPIC | |
2054 | ||
f5a1b0d2 | 2055 | /* We can't directly access anything that contains a symbol, |
d3585b76 DJ |
2056 | nor can we indirect via the constant pool. One exception is |
2057 | UNSPEC_TLS, which is always PIC. */ | |
82e9d970 | 2058 | #define LEGITIMATE_PIC_OPERAND_P(X) \ |
1575c31e JD |
2059 | (!(symbol_mentioned_p (X) \ |
2060 | || label_mentioned_p (X) \ | |
2061 | || (GET_CODE (X) == SYMBOL_REF \ | |
2062 | && CONSTANT_POOL_ADDRESS_P (X) \ | |
2063 | && (symbol_mentioned_p (get_pool_constant (X)) \ | |
d3585b76 DJ |
2064 | || label_mentioned_p (get_pool_constant (X))))) \ |
2065 | || tls_mentioned_p (X)) | |
1575c31e | 2066 | |
4997c9ae CL |
2067 | /* We may want to save the PIC register if it is a dedicated one. */ |
2068 | #define PIC_REGISTER_MAY_NEED_SAVING \ | |
2069 | (flag_pic \ | |
2070 | && !TARGET_SINGLE_PIC_BASE \ | |
2071 | && !TARGET_FDPIC \ | |
2072 | && arm_pic_register != INVALID_REGNUM) | |
2073 | ||
13bd191d PB |
2074 | /* We need to know when we are making a constant pool; this determines |
2075 | whether data needs to be in the GOT or can be referenced via a GOT | |
2076 | offset. */ | |
2077 | extern int making_const_table; | |
82e9d970 | 2078 | \f |
c27ba912 | 2079 | /* Handle pragmas for compatibility with Intel's compilers. */ |
b76c3c4b | 2080 | /* Also abuse this to register additional C specific EABI attributes. */ |
c58b209a NB |
2081 | #define REGISTER_TARGET_PRAGMAS() do { \ |
2082 | c_register_pragma (0, "long_calls", arm_pr_long_calls); \ | |
2083 | c_register_pragma (0, "no_long_calls", arm_pr_no_long_calls); \ | |
2084 | c_register_pragma (0, "long_calls_off", arm_pr_long_calls_off); \ | |
c84f825c CB |
2085 | arm_lang_object_attributes_init(); \ |
2086 | arm_register_target_pragmas(); \ | |
8b97c5f8 ZW |
2087 | } while (0) |
2088 | ||
d6b4baa4 | 2089 | /* Condition code information. */ |
ff9940b0 | 2090 | /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, |
a5381466 | 2091 | return the mode to be used for the comparison. */ |
d5b7b3ae RE |
2092 | |
2093 | #define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y) | |
ff9940b0 | 2094 | |
880873be RE |
2095 | #define REVERSIBLE_CC_MODE(MODE) 1 |
2096 | ||
2097 | #define REVERSE_CONDITION(CODE,MODE) \ | |
2098 | (((MODE) == CCFPmode || (MODE) == CCFPEmode) \ | |
2099 | ? reverse_condition_maybe_unordered (code) \ | |
2100 | : reverse_condition (code)) | |
008cf58a | 2101 | |
9b227e35 | 2102 | #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ |
41197ad4 | 2103 | ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2) |
9b227e35 | 2104 | #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ |
41197ad4 | 2105 | ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2) |
35d965d5 | 2106 | \f |
906668bb BS |
2107 | #define CC_STATUS_INIT \ |
2108 | do { cfun->machine->thumb1_cc_insn = NULL_RTX; } while (0) | |
2109 | ||
decfc6e1 TG |
2110 | #undef ASM_APP_ON |
2111 | #define ASM_APP_ON (inline_asm_unified ? "\t.syntax unified\n" : \ | |
2112 | "\t.syntax divided\n") | |
2113 | ||
d5b7b3ae | 2114 | #undef ASM_APP_OFF |
41d14659 RR |
2115 | #define ASM_APP_OFF (TARGET_ARM ? "\t.arm\n\t.syntax unified\n" : \ |
2116 | "\t.thumb\n\t.syntax unified\n") | |
35d965d5 | 2117 | |
2ee67fbb JB |
2118 | /* Output a push or a pop instruction (only used when profiling). |
2119 | We can't push STATIC_CHAIN_REGNUM (r12) directly with Thumb-1. We know | |
2120 | that ASM_OUTPUT_REG_PUSH will be matched with ASM_OUTPUT_REG_POP, and | |
2121 | that r7 isn't used by the function profiler, so we can use it as a | |
2122 | scratch reg. WARNING: This isn't safe in the general case! It may be | |
2123 | sensitive to future changes in final.c:profile_function. */ | |
d5b7b3ae | 2124 | #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \ |
8a81cc45 RE |
2125 | do \ |
2126 | { \ | |
bae4ce0f | 2127 | if (TARGET_THUMB1 \ |
2ee67fbb JB |
2128 | && (REGNO) == STATIC_CHAIN_REGNUM) \ |
2129 | { \ | |
2130 | asm_fprintf (STREAM, "\tpush\t{r7}\n"); \ | |
2131 | asm_fprintf (STREAM, "\tmov\tr7, %r\n", REGNO);\ | |
2132 | asm_fprintf (STREAM, "\tpush\t{r7}\n"); \ | |
2133 | } \ | |
8a81cc45 RE |
2134 | else \ |
2135 | asm_fprintf (STREAM, "\tpush {%r}\n", REGNO); \ | |
2136 | } while (0) | |
d5b7b3ae RE |
2137 | |
2138 | ||
2ee67fbb | 2139 | /* See comment for ASM_OUTPUT_REG_PUSH concerning Thumb-1 issue. */ |
d5b7b3ae | 2140 | #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \ |
8a81cc45 RE |
2141 | do \ |
2142 | { \ | |
bae4ce0f RR |
2143 | if (TARGET_THUMB1 \ |
2144 | && (REGNO) == STATIC_CHAIN_REGNUM) \ | |
2ee67fbb JB |
2145 | { \ |
2146 | asm_fprintf (STREAM, "\tpop\t{r7}\n"); \ | |
2147 | asm_fprintf (STREAM, "\tmov\t%r, r7\n", REGNO);\ | |
2148 | asm_fprintf (STREAM, "\tpop\t{r7}\n"); \ | |
2149 | } \ | |
8a81cc45 RE |
2150 | else \ |
2151 | asm_fprintf (STREAM, "\tpop {%r}\n", REGNO); \ | |
2152 | } while (0) | |
d5b7b3ae | 2153 | |
b0fe107e JM |
2154 | #define ADDR_VEC_ALIGN(JUMPTABLE) \ |
2155 | ((TARGET_THUMB && GET_MODE (PATTERN (JUMPTABLE)) == SImode) ? 2 : 0) | |
2156 | ||
2157 | /* Alignment for case labels comes from ADDR_VEC_ALIGN; avoid the | |
2158 | default alignment from elfos.h. */ | |
2159 | #undef ASM_OUTPUT_BEFORE_CASE_LABEL | |
2160 | #define ASM_OUTPUT_BEFORE_CASE_LABEL(FILE, PREFIX, NUM, TABLE) /* Empty. */ | |
5b3e6663 | 2161 | |
e75c1617 CB |
2162 | #define LABEL_ALIGN_AFTER_BARRIER(LABEL) \ |
2163 | (GET_CODE (PATTERN (prev_active_insn (LABEL))) == ADDR_DIFF_VEC \ | |
2164 | ? 1 : 0) | |
35d965d5 | 2165 | |
6cfc7210 | 2166 | #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \ |
258619bb | 2167 | arm_declare_function_name ((STREAM), (NAME), (DECL)); |
35d965d5 | 2168 | |
d5b7b3ae RE |
2169 | /* For aliases of functions we use .thumb_set instead. */ |
2170 | #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \ | |
2171 | do \ | |
2172 | { \ | |
91ea4f8d KG |
2173 | const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \ |
2174 | const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \ | |
d5b7b3ae RE |
2175 | \ |
2176 | if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \ | |
2177 | { \ | |
2178 | fprintf (FILE, "\t.thumb_set "); \ | |
2179 | assemble_name (FILE, LABEL1); \ | |
2180 | fprintf (FILE, ","); \ | |
2181 | assemble_name (FILE, LABEL2); \ | |
2182 | fprintf (FILE, "\n"); \ | |
2183 | } \ | |
2184 | else \ | |
2185 | ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \ | |
2186 | } \ | |
2187 | while (0) | |
2188 | ||
fdc2d3b0 NC |
2189 | #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN |
2190 | /* To support -falign-* switches we need to use .p2align so | |
2191 | that alignment directives in code sections will be padded | |
2192 | with no-op instructions, rather than zeroes. */ | |
5a9335ef | 2193 | #define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE, LOG, MAX_SKIP) \ |
fdc2d3b0 NC |
2194 | if ((LOG) != 0) \ |
2195 | { \ | |
2196 | if ((MAX_SKIP) == 0) \ | |
5a9335ef | 2197 | fprintf ((FILE), "\t.p2align %d\n", (int) (LOG)); \ |
fdc2d3b0 NC |
2198 | else \ |
2199 | fprintf ((FILE), "\t.p2align %d,,%d\n", \ | |
5a9335ef | 2200 | (int) (LOG), (int) (MAX_SKIP)); \ |
fdc2d3b0 NC |
2201 | } |
2202 | #endif | |
35d965d5 | 2203 | \f |
5b3e6663 PB |
2204 | /* Add two bytes to the length of conditionally executed Thumb-2 |
2205 | instructions for the IT instruction. */ | |
2206 | #define ADJUST_INSN_LENGTH(insn, length) \ | |
2207 | if (TARGET_THUMB2 && GET_CODE (PATTERN (insn)) == COND_EXEC) \ | |
2208 | length += 2; | |
2209 | ||
35d965d5 | 2210 | /* Only perform branch elimination (by making instructions conditional) if |
5b3e6663 PB |
2211 | we're optimizing. For Thumb-2 check if any IT instructions need |
2212 | outputting. */ | |
d5b7b3ae RE |
2213 | #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \ |
2214 | if (TARGET_ARM && optimize) \ | |
2215 | arm_final_prescan_insn (INSN); \ | |
5b3e6663 PB |
2216 | else if (TARGET_THUMB2) \ |
2217 | thumb2_final_prescan_insn (INSN); \ | |
2218 | else if (TARGET_THUMB1) \ | |
2219 | thumb1_final_prescan_insn (INSN) | |
35d965d5 | 2220 | |
7b8b8ade NC |
2221 | #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \ |
2222 | (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \ | |
30cf4896 KG |
2223 | : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\ |
2224 | ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \ | |
2225 | ? ((~ (unsigned HOST_WIDE_INT) 0) \ | |
2226 | & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \ | |
7bc7696c | 2227 | : 0)))) |
35d965d5 | 2228 | |
6a5d7526 MS |
2229 | /* A C expression whose value is RTL representing the value of the return |
2230 | address for the frame COUNT steps up from the current frame. */ | |
2231 | ||
d5b7b3ae RE |
2232 | #define RETURN_ADDR_RTX(COUNT, FRAME) \ |
2233 | arm_return_addr (COUNT, FRAME) | |
2234 | ||
f676971a | 2235 | /* Mask of the bits in the PC that contain the real return address |
d5b7b3ae RE |
2236 | when running in 26-bit mode. */ |
2237 | #define RETURN_ADDR_MASK26 (0x03fffffc) | |
6a5d7526 | 2238 | |
2c849145 JM |
2239 | /* Pick up the return address upon entry to a procedure. Used for |
2240 | dwarf2 unwind information. This also enables the table driven | |
2241 | mechanism. */ | |
2c849145 JM |
2242 | #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM) |
2243 | #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM) | |
2244 | ||
39950dff MS |
2245 | /* Used to mask out junk bits from the return address, such as |
2246 | processor state, interrupt status, condition codes and the like. */ | |
2247 | #define MASK_RETURN_ADDR \ | |
2248 | /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \ | |
2249 | in 26 bit mode, the condition codes must be masked out of the \ | |
2250 | return address. This does not apply to ARM6 and later processors \ | |
2251 | when running in 32 bit mode. */ \ | |
61f0ccff RE |
2252 | ((arm_arch4 || TARGET_THUMB) \ |
2253 | ? (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \ | |
fcd53748 | 2254 | : arm_gen_return_addr_mask ()) |
d5b7b3ae RE |
2255 | |
2256 | \f | |
978e411f CD |
2257 | /* Do not emit .note.GNU-stack by default. */ |
2258 | #ifndef NEED_INDICATE_EXEC_STACK | |
2259 | #define NEED_INDICATE_EXEC_STACK 0 | |
2260 | #endif | |
2261 | ||
9e94a7fc MGD |
2262 | #define TARGET_ARM_ARCH \ |
2263 | (arm_base_arch) \ | |
2264 | ||
9e94a7fc | 2265 | /* The highest Thumb instruction set version supported by the chip. */ |
52545641 TP |
2266 | #define TARGET_ARM_ARCH_ISA_THUMB \ |
2267 | (arm_arch_thumb2 ? 2 : (arm_arch_thumb1 ? 1 : 0)) | |
9e94a7fc MGD |
2268 | |
2269 | /* Expands to an upper-case char of the target's architectural | |
2270 | profile. */ | |
2271 | #define TARGET_ARM_ARCH_PROFILE \ | |
8afb5358 | 2272 | (arm_active_target.profile) |
9e94a7fc MGD |
2273 | |
2274 | /* Bit-field indicating what size LDREX/STREX loads/stores are available. | |
2275 | Bit 0 for bytes, up to bit 3 for double-words. */ | |
2276 | #define TARGET_ARM_FEATURE_LDREX \ | |
2277 | ((TARGET_HAVE_LDREX ? 4 : 0) \ | |
2278 | | (TARGET_HAVE_LDREXBH ? 3 : 0) \ | |
2279 | | (TARGET_HAVE_LDREXD ? 8 : 0)) | |
2280 | ||
2281 | /* Set as a bit mask indicating the available widths of hardware floating | |
2282 | point types. Where bit 1 indicates 16-bit support, bit 2 indicates | |
2283 | 32-bit support, bit 3 indicates 64-bit support. */ | |
2284 | #define TARGET_ARM_FP \ | |
29e1d31b MM |
2285 | (!TARGET_SOFT_FLOAT ? (TARGET_VFP_SINGLE ? 4 \ |
2286 | : (TARGET_VFP_DOUBLE ? (TARGET_FP16 ? 14 : 12) : 0)) \ | |
2287 | : 0) | |
9e94a7fc MGD |
2288 | |
2289 | ||
2290 | /* Set as a bit mask indicating the available widths of floating point | |
2291 | types for hardware NEON floating point. This is the same as | |
2292 | TARGET_ARM_FP without the 64-bit bit set. */ | |
29e1d31b MM |
2293 | #define TARGET_NEON_FP \ |
2294 | (TARGET_NEON ? (TARGET_ARM_FP & (0xff ^ 0x08)) \ | |
2295 | : 0) | |
9e94a7fc | 2296 | |
11389610 RE |
2297 | /* Name of the automatic fpu-selection option. */ |
2298 | #define FPUTYPE_AUTO "auto" | |
2299 | ||
93b338c3 BS |
2300 | /* The maximum number of parallel loads or stores we support in an ldm/stm |
2301 | instruction. */ | |
2302 | #define MAX_LDM_STM_OPS 4 | |
2303 | ||
b848e289 | 2304 | extern const char *arm_rewrite_mcpu (int argc, const char **argv); |
86794453 | 2305 | extern const char *arm_rewrite_march (int argc, const char **argv); |
940269b6 | 2306 | extern const char *arm_asm_auto_mfpu (int argc, const char **argv); |
86794453 RE |
2307 | #define ASM_CPU_SPEC_FUNCTIONS \ |
2308 | { "rewrite_mcpu", arm_rewrite_mcpu }, \ | |
940269b6 RE |
2309 | { "rewrite_march", arm_rewrite_march }, \ |
2310 | { "asm_auto_mfpu", arm_asm_auto_mfpu }, | |
b848e289 | 2311 | |
86794453 | 2312 | #define ASM_CPU_SPEC \ |
940269b6 | 2313 | " %{mfpu=auto:%<mfpu=auto %:asm_auto_mfpu(%{march=*: arch %*})}" \ |
86794453 | 2314 | " %{mcpu=generic-*:-march=%:rewrite_march(%{mcpu=generic-*:%*});" \ |
940269b6 | 2315 | " march=*:-march=%:rewrite_march(%{march=*:%*});" \ |
86794453 RE |
2316 | " mcpu=*:-mcpu=%:rewrite_mcpu(%{mcpu=*:%*})" \ |
2317 | " }" | |
54e73f88 | 2318 | |
70e73d3c | 2319 | extern const char *arm_target_thumb_only (int argc, const char **argv); |
86794453 | 2320 | #define TARGET_MODE_SPEC_FUNCTIONS \ |
70e73d3c TP |
2321 | { "target_mode_check", arm_target_thumb_only }, |
2322 | ||
33aa08b3 AS |
2323 | /* -mcpu=native handling only makes sense with compiler running on |
2324 | an ARM chip. */ | |
2325 | #if defined(__arm__) | |
2326 | extern const char *host_detect_local_cpu (int argc, const char **argv); | |
a646fe9c | 2327 | #define HAVE_LOCAL_CPU_DETECT |
86794453 RE |
2328 | # define MCPU_MTUNE_NATIVE_FUNCTIONS \ |
2329 | { "local_cpu_detect", host_detect_local_cpu }, | |
2330 | # define MCPU_MTUNE_NATIVE_SPECS \ | |
2331 | " %{march=native:%<march=native %:local_cpu_detect(arch)}" \ | |
2332 | " %{mcpu=native:%<mcpu=native %:local_cpu_detect(cpu)}" \ | |
33aa08b3 AS |
2333 | " %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}" |
2334 | #else | |
86794453 | 2335 | # define MCPU_MTUNE_NATIVE_FUNCTIONS |
33aa08b3 AS |
2336 | # define MCPU_MTUNE_NATIVE_SPECS "" |
2337 | #endif | |
2338 | ||
0b97b8f8 RE |
2339 | const char *arm_canon_arch_option (int argc, const char **argv); |
2340 | ||
2341 | #define CANON_ARCH_SPEC_FUNCTION \ | |
2342 | { "canon_arch", arm_canon_arch_option }, | |
2343 | ||
63d03dce RE |
2344 | const char *arm_be8_option (int argc, const char **argv); |
2345 | #define BE8_SPEC_FUNCTION \ | |
2346 | { "be8_linkopt", arm_be8_option }, | |
2347 | ||
86794453 RE |
2348 | # define EXTRA_SPEC_FUNCTIONS \ |
2349 | MCPU_MTUNE_NATIVE_FUNCTIONS \ | |
2350 | ASM_CPU_SPEC_FUNCTIONS \ | |
0b97b8f8 | 2351 | CANON_ARCH_SPEC_FUNCTION \ |
63d03dce RE |
2352 | TARGET_MODE_SPEC_FUNCTIONS \ |
2353 | BE8_SPEC_FUNCTION | |
86794453 | 2354 | |
70e73d3c TP |
2355 | /* Automatically add -mthumb for Thumb-only targets if mode isn't specified |
2356 | via the configuration option --with-mode or via the command line. The | |
2357 | function target_mode_check is called to do the check with either: | |
2358 | - an array of -march values if any is given; | |
2359 | - an array of -mcpu values if any is given; | |
2360 | - an empty array. */ | |
2361 | #define TARGET_MODE_SPECS \ | |
e53993ef | 2362 | " %{!marm:%{!mthumb:%:target_mode_check(%{march=*:arch %*;mcpu=*:cpu %*;:})}}" |
70e73d3c | 2363 | |
0b97b8f8 RE |
2364 | /* Generate a canonical string to represent the architecture selected. */ |
2365 | #define ARCH_CANONICAL_SPECS \ | |
2366 | " -march=%:canon_arch(%{mcpu=*: cpu %*} " \ | |
2367 | " %{march=*: arch %*} " \ | |
2368 | " %{mfpu=*: fpu %*} " \ | |
2369 | " %{mfloat-abi=*: abi %*}" \ | |
2370 | " %<march=*) " | |
2371 | ||
59aab79a RE |
2372 | /* Complete set of specs for the driver. Commas separate the |
2373 | individual rules so that any option suppression (%<opt...)is | |
2374 | completed before starting subsequent rules. */ | |
0b97b8f8 | 2375 | #define DRIVER_SELF_SPECS \ |
59aab79a RE |
2376 | MCPU_MTUNE_NATIVE_SPECS, \ |
2377 | TARGET_MODE_SPECS, \ | |
0b97b8f8 RE |
2378 | ARCH_CANONICAL_SPECS |
2379 | ||
27e83a44 | 2380 | #define TARGET_SUPPORTS_WIDE_INT 1 |
d5524d52 CB |
2381 | |
2382 | /* For switching between functions with different target attributes. */ | |
2383 | #define SWITCHABLE_TARGET 1 | |
2384 | ||
0ee70cc0 AV |
2385 | /* Define SECTION_ARM_PURECODE as the ARM specific section attribute |
2386 | representation for SHF_ARM_PURECODE in GCC. */ | |
2387 | #define SECTION_ARM_PURECODE SECTION_MACH_DEP | |
2388 | ||
88657302 | 2389 | #endif /* ! GCC_ARM_H */ |