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f5a1b0d2 | 1 | /* Definitions of target machine for GNU compiler, for ARM. |
cf011243 AO |
2 | Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, |
3 | 2001 Free Software Foundation, Inc. | |
35d965d5 | 4 | Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl) |
8b109b37 | 5 | and Martin Simmons (@harleqn.co.uk). |
949d79eb | 6 | More major hacks by Richard Earnshaw (rearnsha@arm.com) |
6cfc7210 NC |
7 | Minor hacks by Nick Clifton (nickc@cygnus.com) |
8 | ||
35d965d5 RS |
9 | This file is part of GNU CC. |
10 | ||
11 | GNU CC is free software; you can redistribute it and/or modify | |
12 | it under the terms of the GNU General Public License as published by | |
13 | the Free Software Foundation; either version 2, or (at your option) | |
14 | any later version. | |
15 | ||
16 | GNU CC is distributed in the hope that it will be useful, | |
17 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | GNU General Public License for more details. | |
20 | ||
21 | You should have received a copy of the GNU General Public License | |
22 | along with GNU CC; see the file COPYING. If not, write to | |
8fb289e7 RK |
23 | the Free Software Foundation, 59 Temple Place - Suite 330, |
24 | Boston, MA 02111-1307, USA. */ | |
35d965d5 | 25 | |
b355a481 NC |
26 | #ifndef __ARM_H__ |
27 | #define __ARM_H__ | |
28 | ||
7a801826 RE |
29 | #define TARGET_CPU_arm2 0x0000 |
30 | #define TARGET_CPU_arm250 0x0000 | |
31 | #define TARGET_CPU_arm3 0x0000 | |
32 | #define TARGET_CPU_arm6 0x0001 | |
33 | #define TARGET_CPU_arm600 0x0001 | |
34 | #define TARGET_CPU_arm610 0x0002 | |
35 | #define TARGET_CPU_arm7 0x0001 | |
36 | #define TARGET_CPU_arm7m 0x0004 | |
37 | #define TARGET_CPU_arm7dm 0x0004 | |
38 | #define TARGET_CPU_arm7dmi 0x0004 | |
39 | #define TARGET_CPU_arm700 0x0001 | |
40 | #define TARGET_CPU_arm710 0x0002 | |
41 | #define TARGET_CPU_arm7100 0x0002 | |
42 | #define TARGET_CPU_arm7500 0x0002 | |
43 | #define TARGET_CPU_arm7500fe 0x1001 | |
44 | #define TARGET_CPU_arm7tdmi 0x0008 | |
45 | #define TARGET_CPU_arm8 0x0010 | |
46 | #define TARGET_CPU_arm810 0x0020 | |
47 | #define TARGET_CPU_strongarm 0x0040 | |
48 | #define TARGET_CPU_strongarm110 0x0040 | |
f5a1b0d2 | 49 | #define TARGET_CPU_strongarm1100 0x0040 |
b36ba79f RE |
50 | #define TARGET_CPU_arm9 0x0080 |
51 | #define TARGET_CPU_arm9tdmi 0x0080 | |
d19fb8e3 | 52 | #define TARGET_CPU_xscale 0x0100 |
82e9d970 | 53 | /* Configure didn't specify. */ |
7a801826 | 54 | #define TARGET_CPU_generic 0x8000 |
ff9940b0 | 55 | |
d5b7b3ae | 56 | typedef enum arm_cond_code |
89c7ca52 RE |
57 | { |
58 | ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC, | |
59 | ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV | |
d5b7b3ae RE |
60 | } |
61 | arm_cc; | |
6cfc7210 | 62 | |
d5b7b3ae | 63 | extern arm_cc arm_current_cc; |
cd2b33d0 | 64 | extern const char * arm_condition_codes[]; |
ff9940b0 | 65 | |
d5b7b3ae | 66 | #define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1)) |
89c7ca52 | 67 | |
6cfc7210 NC |
68 | extern int arm_target_label; |
69 | extern int arm_ccfsm_state; | |
70 | extern struct rtx_def * arm_target_insn; | |
6cfc7210 NC |
71 | /* Run-time compilation parameters selecting different hardware subsets. */ |
72 | extern int target_flags; | |
73 | /* The floating point instruction architecture, can be 2 or 3 */ | |
74 | extern const char * target_fp_name; | |
d5b7b3ae RE |
75 | /* Define the information needed to generate branch insns. This is |
76 | stored from the compare operation. Note that we can't use "rtx" here | |
77 | since it hasn't been defined! */ | |
78 | extern struct rtx_def * arm_compare_op0; | |
79 | extern struct rtx_def * arm_compare_op1; | |
80 | /* The label of the current constant pool. */ | |
81 | extern struct rtx_def * pool_vector_label; | |
82 | /* Set to 1 when a return insn is output, this means that the epilogue | |
83 | is not needed. */ | |
84 | extern int return_used_this_function; | |
85 | /* Nonzero if the prologue must setup `fp'. */ | |
86 | extern int current_function_anonymous_args; | |
35d965d5 | 87 | \f |
7a801826 RE |
88 | /* Just in case configure has failed to define anything. */ |
89 | #ifndef TARGET_CPU_DEFAULT | |
90 | #define TARGET_CPU_DEFAULT TARGET_CPU_generic | |
91 | #endif | |
92 | ||
93 | /* If the configuration file doesn't specify the cpu, the subtarget may | |
70f24e49 | 94 | override it. If it doesn't, then default to an ARM6. */ |
7a801826 RE |
95 | #if TARGET_CPU_DEFAULT == TARGET_CPU_generic |
96 | #undef TARGET_CPU_DEFAULT | |
70f24e49 | 97 | |
7a801826 RE |
98 | #ifdef SUBTARGET_CPU_DEFAULT |
99 | #define TARGET_CPU_DEFAULT SUBTARGET_CPU_DEFAULT | |
100 | #else | |
101 | #define TARGET_CPU_DEFAULT TARGET_CPU_arm6 | |
102 | #endif | |
103 | #endif | |
104 | ||
105 | #if TARGET_CPU_DEFAULT == TARGET_CPU_arm2 | |
106 | #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_2__" | |
107 | #else | |
18543a22 | 108 | #if TARGET_CPU_DEFAULT == TARGET_CPU_arm6 || TARGET_CPU_DEFAULT == TARGET_CPU_arm610 || TARGET_CPU_DEFAULT == TARGET_CPU_arm7500fe |
7a801826 RE |
109 | #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_3__" |
110 | #else | |
111 | #if TARGET_CPU_DEFAULT == TARGET_CPU_arm7m | |
112 | #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_3M__" | |
113 | #else | |
70f24e49 | 114 | #if TARGET_CPU_DEFAULT == TARGET_CPU_arm7tdmi || TARGET_CPU_DEFAULT == TARGET_CPU_arm9 || TARGET_CPU_DEFAULT == TARGET_CPU_arm9tdmi |
7a801826 RE |
115 | #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4T__" |
116 | #else | |
dc60a41b | 117 | #if TARGET_CPU_DEFAULT == TARGET_CPU_arm8 || TARGET_CPU_DEFAULT == TARGET_CPU_arm810 || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm110 || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm1100 |
7a801826 RE |
118 | #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4__" |
119 | #else | |
d19fb8e3 NC |
120 | #if TARGET_CPU_DEFAULT == TARGET_CPU_xscale |
121 | #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_5TE__ -D__XSCALE__" | |
122 | #else | |
7a801826 RE |
123 | Unrecognized value in TARGET_CPU_DEFAULT. |
124 | #endif | |
125 | #endif | |
126 | #endif | |
127 | #endif | |
128 | #endif | |
d19fb8e3 | 129 | #endif |
7a801826 | 130 | |
ff9940b0 | 131 | #ifndef CPP_PREDEFINES |
2b57e919 | 132 | #define CPP_PREDEFINES "-Acpu=arm -Amachine=arm" |
ff9940b0 | 133 | #endif |
35d965d5 | 134 | |
38fc909b RE |
135 | #define CPP_SPEC "\ |
136 | %(cpp_cpu_arch) %(cpp_apcs_pc) %(cpp_float) \ | |
6dcd26ea | 137 | %(cpp_endian) %(subtarget_cpp_spec) %(cpp_isa) %(cpp_interwork)" |
d5b7b3ae | 138 | |
75d8aea7 | 139 | #define CPP_ISA_SPEC "%{mthumb:-D__thumb__} %{!mthumb:-D__arm__}" |
7a801826 | 140 | |
71791e16 RE |
141 | /* Set the architecture define -- if -march= is set, then it overrides |
142 | the -mcpu= setting. */ | |
7a801826 | 143 | #define CPP_CPU_ARCH_SPEC "\ |
71791e16 RE |
144 | %{march=arm2:-D__ARM_ARCH_2__} \ |
145 | %{march=arm250:-D__ARM_ARCH_2__} \ | |
146 | %{march=arm3:-D__ARM_ARCH_2__} \ | |
147 | %{march=arm6:-D__ARM_ARCH_3__} \ | |
148 | %{march=arm600:-D__ARM_ARCH_3__} \ | |
149 | %{march=arm610:-D__ARM_ARCH_3__} \ | |
150 | %{march=arm7:-D__ARM_ARCH_3__} \ | |
151 | %{march=arm700:-D__ARM_ARCH_3__} \ | |
152 | %{march=arm710:-D__ARM_ARCH_3__} \ | |
a120a3bd | 153 | %{march=arm720:-D__ARM_ARCH_3__} \ |
71791e16 RE |
154 | %{march=arm7100:-D__ARM_ARCH_3__} \ |
155 | %{march=arm7500:-D__ARM_ARCH_3__} \ | |
156 | %{march=arm7500fe:-D__ARM_ARCH_3__} \ | |
157 | %{march=arm7m:-D__ARM_ARCH_3M__} \ | |
158 | %{march=arm7dm:-D__ARM_ARCH_3M__} \ | |
159 | %{march=arm7dmi:-D__ARM_ARCH_3M__} \ | |
160 | %{march=arm7tdmi:-D__ARM_ARCH_4T__} \ | |
161 | %{march=arm8:-D__ARM_ARCH_4__} \ | |
162 | %{march=arm810:-D__ARM_ARCH_4__} \ | |
b36ba79f | 163 | %{march=arm9:-D__ARM_ARCH_4T__} \ |
60d0536b NC |
164 | %{march=arm920:-D__ARM_ARCH_4__} \ |
165 | %{march=arm920t:-D__ARM_ARCH_4T__} \ | |
b36ba79f | 166 | %{march=arm9tdmi:-D__ARM_ARCH_4T__} \ |
71791e16 RE |
167 | %{march=strongarm:-D__ARM_ARCH_4__} \ |
168 | %{march=strongarm110:-D__ARM_ARCH_4__} \ | |
f5a1b0d2 | 169 | %{march=strongarm1100:-D__ARM_ARCH_4__} \ |
d19fb8e3 NC |
170 | %{march=xscale:-D__ARM_ARCH_5TE__} \ |
171 | %{march=xscale:-D__XSCALE__} \ | |
71791e16 RE |
172 | %{march=armv2:-D__ARM_ARCH_2__} \ |
173 | %{march=armv2a:-D__ARM_ARCH_2__} \ | |
174 | %{march=armv3:-D__ARM_ARCH_3__} \ | |
175 | %{march=armv3m:-D__ARM_ARCH_3M__} \ | |
176 | %{march=armv4:-D__ARM_ARCH_4__} \ | |
177 | %{march=armv4t:-D__ARM_ARCH_4T__} \ | |
62b10bbc | 178 | %{march=armv5:-D__ARM_ARCH_5__} \ |
d5b7b3ae RE |
179 | %{march=armv5t:-D__ARM_ARCH_5T__} \ |
180 | %{march=armv5e:-D__ARM_ARCH_5E__} \ | |
181 | %{march=armv5te:-D__ARM_ARCH_5TE__} \ | |
71791e16 RE |
182 | %{!march=*: \ |
183 | %{mcpu=arm2:-D__ARM_ARCH_2__} \ | |
184 | %{mcpu=arm250:-D__ARM_ARCH_2__} \ | |
185 | %{mcpu=arm3:-D__ARM_ARCH_2__} \ | |
186 | %{mcpu=arm6:-D__ARM_ARCH_3__} \ | |
187 | %{mcpu=arm600:-D__ARM_ARCH_3__} \ | |
188 | %{mcpu=arm610:-D__ARM_ARCH_3__} \ | |
189 | %{mcpu=arm7:-D__ARM_ARCH_3__} \ | |
190 | %{mcpu=arm700:-D__ARM_ARCH_3__} \ | |
191 | %{mcpu=arm710:-D__ARM_ARCH_3__} \ | |
a120a3bd | 192 | %{mcpu=arm720:-D__ARM_ARCH_3__} \ |
71791e16 RE |
193 | %{mcpu=arm7100:-D__ARM_ARCH_3__} \ |
194 | %{mcpu=arm7500:-D__ARM_ARCH_3__} \ | |
195 | %{mcpu=arm7500fe:-D__ARM_ARCH_3__} \ | |
196 | %{mcpu=arm7m:-D__ARM_ARCH_3M__} \ | |
197 | %{mcpu=arm7dm:-D__ARM_ARCH_3M__} \ | |
198 | %{mcpu=arm7dmi:-D__ARM_ARCH_3M__} \ | |
199 | %{mcpu=arm7tdmi:-D__ARM_ARCH_4T__} \ | |
200 | %{mcpu=arm8:-D__ARM_ARCH_4__} \ | |
201 | %{mcpu=arm810:-D__ARM_ARCH_4__} \ | |
b36ba79f | 202 | %{mcpu=arm9:-D__ARM_ARCH_4T__} \ |
60d0536b NC |
203 | %{mcpu=arm920:-D__ARM_ARCH_4__} \ |
204 | %{mcpu=arm920t:-D__ARM_ARCH_4T__} \ | |
b36ba79f | 205 | %{mcpu=arm9tdmi:-D__ARM_ARCH_4T__} \ |
71791e16 RE |
206 | %{mcpu=strongarm:-D__ARM_ARCH_4__} \ |
207 | %{mcpu=strongarm110:-D__ARM_ARCH_4__} \ | |
f5a1b0d2 | 208 | %{mcpu=strongarm1100:-D__ARM_ARCH_4__} \ |
d19fb8e3 NC |
209 | %{mcpu=xscale:-D__ARM_ARCH_5TE__} \ |
210 | %{mcpu=xscale:-D__XSCALE__} \ | |
dfa08768 | 211 | %{!mcpu*:%(cpp_cpu_arch_default)}} \ |
11c1a207 | 212 | " |
7a801826 RE |
213 | |
214 | /* Define __APCS_26__ if the PC also contains the PSR */ | |
7a801826 RE |
215 | #define CPP_APCS_PC_SPEC "\ |
216 | %{mapcs-32:%{mapcs-26:%e-mapcs-26 and -mapcs-32 may not be used together} \ | |
217 | -D__APCS_32__} \ | |
218 | %{mapcs-26:-D__APCS_26__} \ | |
dfa08768 | 219 | %{!mapcs-32: %{!mapcs-26:%(cpp_apcs_pc_default)}} \ |
7a801826 RE |
220 | " |
221 | ||
b355a481 | 222 | #ifndef CPP_APCS_PC_DEFAULT_SPEC |
7a801826 | 223 | #define CPP_APCS_PC_DEFAULT_SPEC "-D__APCS_26__" |
b355a481 | 224 | #endif |
7a801826 RE |
225 | |
226 | #define CPP_FLOAT_SPEC "\ | |
227 | %{msoft-float:\ | |
228 | %{mhard-float:%e-msoft-float and -mhard_float may not be used together} \ | |
229 | -D__SOFTFP__} \ | |
230 | %{!mhard-float:%{!msoft-float:%(cpp_float_default)}} \ | |
231 | " | |
232 | ||
233 | /* Default is hard float, which doesn't define anything */ | |
234 | #define CPP_FLOAT_DEFAULT_SPEC "" | |
235 | ||
236 | #define CPP_ENDIAN_SPEC "\ | |
6cfc7210 NC |
237 | %{mbig-endian: \ |
238 | %{mlittle-endian: \ | |
239 | %e-mbig-endian and -mlittle-endian may not be used together} \ | |
d5b7b3ae RE |
240 | -D__ARMEB__ %{mwords-little-endian:-D__ARMWEL__} %{mthumb:-D__THUMBEB__}}\ |
241 | %{mlittle-endian:-D__ARMEL__ %{mthumb:-D__THUMBEL__}} \ | |
6cfc7210 | 242 | %{!mlittle-endian:%{!mbig-endian:%(cpp_endian_default)}} \ |
7a801826 RE |
243 | " |
244 | ||
d5b7b3ae RE |
245 | /* Default is little endian. */ |
246 | #define CPP_ENDIAN_DEFAULT_SPEC "-D__ARMEL__ %{mthumb:-D__THUMBEL__}" | |
7a801826 | 247 | |
6dcd26ea RE |
248 | /* Add a define for interworking. Needed when building libgcc.a. |
249 | This must define __THUMB_INTERWORK__ to the pre-processor if | |
250 | interworking is enabled by default. */ | |
251 | #ifndef CPP_INTERWORK_DEFAULT_SPEC | |
252 | #define CPP_INTERWORK_DEFAULT_SPEC "" | |
253 | #endif | |
254 | ||
255 | #define CPP_INTERWORK_SPEC " \ | |
256 | %{mthumb-interwork: \ | |
257 | %{mno-thumb-interwork: %eIncompatible interworking options} \ | |
258 | -D__THUMB_INTERWORK__} \ | |
259 | %{!mthumb-interwork:%{!mno-thumb-interwork:%(cpp_interwork_default)}} \ | |
260 | " | |
261 | ||
dfa08768 | 262 | #define CC1_SPEC "" |
7a801826 RE |
263 | |
264 | /* This macro defines names of additional specifications to put in the specs | |
265 | that can be used in various specifications like CC1_SPEC. Its definition | |
266 | is an initializer with a subgrouping for each command option. | |
267 | ||
268 | Each subgrouping contains a string constant, that defines the | |
269 | specification name, and a string constant that used by the GNU CC driver | |
270 | program. | |
271 | ||
272 | Do not define this macro if it does not need to do anything. */ | |
273 | #define EXTRA_SPECS \ | |
274 | { "cpp_cpu_arch", CPP_CPU_ARCH_SPEC }, \ | |
275 | { "cpp_cpu_arch_default", CPP_ARCH_DEFAULT_SPEC }, \ | |
276 | { "cpp_apcs_pc", CPP_APCS_PC_SPEC }, \ | |
277 | { "cpp_apcs_pc_default", CPP_APCS_PC_DEFAULT_SPEC }, \ | |
278 | { "cpp_float", CPP_FLOAT_SPEC }, \ | |
279 | { "cpp_float_default", CPP_FLOAT_DEFAULT_SPEC }, \ | |
280 | { "cpp_endian", CPP_ENDIAN_SPEC }, \ | |
281 | { "cpp_endian_default", CPP_ENDIAN_DEFAULT_SPEC }, \ | |
d5b7b3ae | 282 | { "cpp_isa", CPP_ISA_SPEC }, \ |
6dcd26ea RE |
283 | { "cpp_interwork", CPP_INTERWORK_SPEC }, \ |
284 | { "cpp_interwork_default", CPP_INTERWORK_DEFAULT_SPEC }, \ | |
38fc909b | 285 | { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \ |
7a801826 RE |
286 | SUBTARGET_EXTRA_SPECS |
287 | ||
914a3b8c | 288 | #ifndef SUBTARGET_EXTRA_SPECS |
7a801826 | 289 | #define SUBTARGET_EXTRA_SPECS |
914a3b8c DM |
290 | #endif |
291 | ||
6cfc7210 | 292 | #ifndef SUBTARGET_CPP_SPEC |
38fc909b | 293 | #define SUBTARGET_CPP_SPEC "" |
6cfc7210 | 294 | #endif |
35d965d5 RS |
295 | \f |
296 | /* Run-time Target Specification. */ | |
ff9940b0 | 297 | #ifndef TARGET_VERSION |
6cfc7210 | 298 | #define TARGET_VERSION fputs (" (ARM/generic)", stderr); |
ff9940b0 | 299 | #endif |
35d965d5 | 300 | |
35d965d5 RS |
301 | /* Nonzero if the function prologue (and epilogue) should obey |
302 | the ARM Procedure Call Standard. */ | |
6cfc7210 | 303 | #define ARM_FLAG_APCS_FRAME (1 << 0) |
35d965d5 RS |
304 | |
305 | /* Nonzero if the function prologue should output the function name to enable | |
306 | the post mortem debugger to print a backtrace (very useful on RISCOS, | |
11c1a207 RE |
307 | unused on RISCiX). Specifying this flag also enables |
308 | -fno-omit-frame-pointer. | |
35d965d5 | 309 | XXX Must still be implemented in the prologue. */ |
6cfc7210 | 310 | #define ARM_FLAG_POKE (1 << 1) |
35d965d5 RS |
311 | |
312 | /* Nonzero if floating point instructions are emulated by the FPE, in which | |
313 | case instruction scheduling becomes very uninteresting. */ | |
6cfc7210 | 314 | #define ARM_FLAG_FPE (1 << 2) |
35d965d5 | 315 | |
11c1a207 RE |
316 | /* Nonzero if destined for a processor in 32-bit program mode. Takes out bit |
317 | that assume restoration of the condition flags when returning from a | |
318 | branch and link (ie a function). */ | |
6cfc7210 | 319 | #define ARM_FLAG_APCS_32 (1 << 3) |
11c1a207 | 320 | |
dfa08768 RE |
321 | /* FLAGS 0x0008 and 0x0010 are now spare (used to be arm3/6 selection). */ |
322 | ||
11c1a207 RE |
323 | /* Nonzero if stack checking should be performed on entry to each function |
324 | which allocates temporary variables on the stack. */ | |
6cfc7210 | 325 | #define ARM_FLAG_APCS_STACK (1 << 4) |
11c1a207 RE |
326 | |
327 | /* Nonzero if floating point parameters should be passed to functions in | |
328 | floating point registers. */ | |
6cfc7210 | 329 | #define ARM_FLAG_APCS_FLOAT (1 << 5) |
11c1a207 RE |
330 | |
331 | /* Nonzero if re-entrant, position independent code should be generated. | |
332 | This is equivalent to -fpic. */ | |
6cfc7210 | 333 | #define ARM_FLAG_APCS_REENT (1 << 6) |
11c1a207 | 334 | |
5f1e6755 NC |
335 | /* Nonzero if the MMU will trap unaligned word accesses, so shorts must |
336 | be loaded using either LDRH or LDRB instructions. */ | |
337 | #define ARM_FLAG_MMU_TRAPS (1 << 7) | |
11c1a207 RE |
338 | |
339 | /* Nonzero if all floating point instructions are missing (and there is no | |
340 | emulator either). Generate function calls for all ops in this case. */ | |
6cfc7210 | 341 | #define ARM_FLAG_SOFT_FLOAT (1 << 8) |
11c1a207 RE |
342 | |
343 | /* Nonzero if we should compile with BYTES_BIG_ENDIAN set to 1. */ | |
6cfc7210 | 344 | #define ARM_FLAG_BIG_END (1 << 9) |
11c1a207 RE |
345 | |
346 | /* Nonzero if we should compile for Thumb interworking. */ | |
6cfc7210 | 347 | #define ARM_FLAG_INTERWORK (1 << 10) |
11c1a207 | 348 | |
ddee6aba RE |
349 | /* Nonzero if we should have little-endian words even when compiling for |
350 | big-endian (for backwards compatibility with older versions of GCC). */ | |
6cfc7210 | 351 | #define ARM_FLAG_LITTLE_WORDS (1 << 11) |
ddee6aba | 352 | |
f5a1b0d2 | 353 | /* Nonzero if we need to protect the prolog from scheduling */ |
6cfc7210 | 354 | #define ARM_FLAG_NO_SCHED_PRO (1 << 12) |
f5a1b0d2 | 355 | |
c11145f6 | 356 | /* Nonzero if a call to abort should be generated if a noreturn |
dd18ae56 | 357 | function tries to return. */ |
6cfc7210 | 358 | #define ARM_FLAG_ABORT_NORETURN (1 << 13) |
c11145f6 | 359 | |
ed0e6530 | 360 | /* Nonzero if function prologues should not load the PIC register. */ |
dd18ae56 | 361 | #define ARM_FLAG_SINGLE_PIC_BASE (1 << 14) |
ed0e6530 | 362 | |
b020fd92 NC |
363 | /* Nonzero if all call instructions should be indirect. */ |
364 | #define ARM_FLAG_LONG_CALLS (1 << 15) | |
d5b7b3ae RE |
365 | |
366 | /* Nonzero means that the target ISA is the THUMB, not the ARM. */ | |
367 | #define ARM_FLAG_THUMB (1 << 16) | |
368 | ||
369 | /* Set if a TPCS style stack frame should be generated, for non-leaf | |
370 | functions, even if they do not need one. */ | |
371 | #define THUMB_FLAG_BACKTRACE (1 << 17) | |
b020fd92 | 372 | |
d5b7b3ae RE |
373 | /* Set if a TPCS style stack frame should be generated, for leaf |
374 | functions, even if they do not need one. */ | |
375 | #define THUMB_FLAG_LEAF_BACKTRACE (1 << 18) | |
376 | ||
377 | /* Set if externally visible functions should assume that they | |
378 | might be called in ARM mode, from a non-thumb aware code. */ | |
379 | #define THUMB_FLAG_CALLEE_SUPER_INTERWORKING (1 << 19) | |
380 | ||
381 | /* Set if calls via function pointers should assume that their | |
382 | destination is non-Thumb aware. */ | |
383 | #define THUMB_FLAG_CALLER_SUPER_INTERWORKING (1 << 20) | |
384 | ||
385 | #define TARGET_APCS_FRAME (target_flags & ARM_FLAG_APCS_FRAME) | |
11c1a207 RE |
386 | #define TARGET_POKE_FUNCTION_NAME (target_flags & ARM_FLAG_POKE) |
387 | #define TARGET_FPE (target_flags & ARM_FLAG_FPE) | |
11c1a207 RE |
388 | #define TARGET_APCS_32 (target_flags & ARM_FLAG_APCS_32) |
389 | #define TARGET_APCS_STACK (target_flags & ARM_FLAG_APCS_STACK) | |
390 | #define TARGET_APCS_FLOAT (target_flags & ARM_FLAG_APCS_FLOAT) | |
391 | #define TARGET_APCS_REENT (target_flags & ARM_FLAG_APCS_REENT) | |
5f1e6755 | 392 | #define TARGET_MMU_TRAPS (target_flags & ARM_FLAG_MMU_TRAPS) |
11c1a207 RE |
393 | #define TARGET_SOFT_FLOAT (target_flags & ARM_FLAG_SOFT_FLOAT) |
394 | #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT) | |
395 | #define TARGET_BIG_END (target_flags & ARM_FLAG_BIG_END) | |
6cfc7210 | 396 | #define TARGET_INTERWORK (target_flags & ARM_FLAG_INTERWORK) |
ddee6aba | 397 | #define TARGET_LITTLE_WORDS (target_flags & ARM_FLAG_LITTLE_WORDS) |
f5a1b0d2 | 398 | #define TARGET_NO_SCHED_PRO (target_flags & ARM_FLAG_NO_SCHED_PRO) |
dd18ae56 | 399 | #define TARGET_ABORT_NORETURN (target_flags & ARM_FLAG_ABORT_NORETURN) |
ed0e6530 | 400 | #define TARGET_SINGLE_PIC_BASE (target_flags & ARM_FLAG_SINGLE_PIC_BASE) |
b020fd92 | 401 | #define TARGET_LONG_CALLS (target_flags & ARM_FLAG_LONG_CALLS) |
d5b7b3ae RE |
402 | #define TARGET_THUMB (target_flags & ARM_FLAG_THUMB) |
403 | #define TARGET_ARM (! TARGET_THUMB) | |
404 | #define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */ | |
405 | #define TARGET_CALLEE_INTERWORKING (target_flags & THUMB_FLAG_CALLEE_SUPER_INTERWORKING) | |
406 | #define TARGET_CALLER_INTERWORKING (target_flags & THUMB_FLAG_CALLER_SUPER_INTERWORKING) | |
407 | #define TARGET_BACKTRACE (leaf_function_p () \ | |
408 | ? (target_flags & THUMB_FLAG_LEAF_BACKTRACE) \ | |
409 | : (target_flags & THUMB_FLAG_BACKTRACE)) | |
3ada8e17 DE |
410 | |
411 | /* SUBTARGET_SWITCHES is used to add flags on a per-config basis. | |
412 | Bit 31 is reserved. See riscix.h. */ | |
413 | #ifndef SUBTARGET_SWITCHES | |
414 | #define SUBTARGET_SWITCHES | |
ff9940b0 RE |
415 | #endif |
416 | ||
047142d3 PT |
417 | #define TARGET_SWITCHES \ |
418 | { \ | |
419 | {"apcs", ARM_FLAG_APCS_FRAME, "" }, \ | |
420 | {"apcs-frame", ARM_FLAG_APCS_FRAME, \ | |
421 | N_("Generate APCS conformant stack frames") }, \ | |
422 | {"no-apcs-frame", -ARM_FLAG_APCS_FRAME, "" }, \ | |
423 | {"poke-function-name", ARM_FLAG_POKE, \ | |
424 | N_("Store function names in object code") }, \ | |
425 | {"no-poke-function-name", -ARM_FLAG_POKE, "" }, \ | |
426 | {"fpe", ARM_FLAG_FPE, "" }, \ | |
427 | {"apcs-32", ARM_FLAG_APCS_32, \ | |
428 | N_("Use the 32bit version of the APCS") }, \ | |
429 | {"apcs-26", -ARM_FLAG_APCS_32, \ | |
430 | N_("Use the 26bit version of the APCS") }, \ | |
431 | {"apcs-stack-check", ARM_FLAG_APCS_STACK, "" }, \ | |
432 | {"no-apcs-stack-check", -ARM_FLAG_APCS_STACK, "" }, \ | |
433 | {"apcs-float", ARM_FLAG_APCS_FLOAT, \ | |
434 | N_("Pass FP arguments in FP registers") }, \ | |
435 | {"no-apcs-float", -ARM_FLAG_APCS_FLOAT, "" }, \ | |
436 | {"apcs-reentrant", ARM_FLAG_APCS_REENT, \ | |
437 | N_("Generate re-entrant, PIC code") }, \ | |
438 | {"no-apcs-reentrant", -ARM_FLAG_APCS_REENT, "" }, \ | |
439 | {"alignment-traps", ARM_FLAG_MMU_TRAPS, \ | |
440 | N_("The MMU will trap on unaligned accesses") }, \ | |
441 | {"no-alignment-traps", -ARM_FLAG_MMU_TRAPS, "" }, \ | |
442 | {"short-load-bytes", ARM_FLAG_MMU_TRAPS, "" }, \ | |
443 | {"no-short-load-bytes", -ARM_FLAG_MMU_TRAPS, "" }, \ | |
444 | {"short-load-words", -ARM_FLAG_MMU_TRAPS, "" }, \ | |
445 | {"no-short-load-words", ARM_FLAG_MMU_TRAPS, "" }, \ | |
446 | {"soft-float", ARM_FLAG_SOFT_FLOAT, \ | |
447 | N_("Use library calls to perform FP operations") }, \ | |
448 | {"hard-float", -ARM_FLAG_SOFT_FLOAT, \ | |
449 | N_("Use hardware floating point instructions") }, \ | |
450 | {"big-endian", ARM_FLAG_BIG_END, \ | |
451 | N_("Assume target CPU is configured as big endian") }, \ | |
452 | {"little-endian", -ARM_FLAG_BIG_END, \ | |
453 | N_("Assume target CPU is configured as little endian") }, \ | |
454 | {"words-little-endian", ARM_FLAG_LITTLE_WORDS, \ | |
455 | N_("Assume big endian bytes, little endian words") }, \ | |
456 | {"thumb-interwork", ARM_FLAG_INTERWORK, \ | |
457 | N_("Support calls between THUMB and ARM instructions sets") }, \ | |
458 | {"no-thumb-interwork", -ARM_FLAG_INTERWORK, "" }, \ | |
459 | {"abort-on-noreturn", ARM_FLAG_ABORT_NORETURN, \ | |
460 | N_("Generate a call to abort if a noreturn function returns")}, \ | |
461 | {"no-abort-on-noreturn", -ARM_FLAG_ABORT_NORETURN, "" }, \ | |
462 | {"sched-prolog", -ARM_FLAG_NO_SCHED_PRO, \ | |
463 | N_("Do not move instructions into a function's prologue") }, \ | |
464 | {"no-sched-prolog", ARM_FLAG_NO_SCHED_PRO, "" }, \ | |
465 | {"single-pic-base", ARM_FLAG_SINGLE_PIC_BASE, \ | |
466 | N_("Do not load the PIC register in function prologues") }, \ | |
467 | {"no-single-pic-base", -ARM_FLAG_SINGLE_PIC_BASE, "" }, \ | |
468 | {"long-calls", ARM_FLAG_LONG_CALLS, \ | |
469 | N_("Generate call insns as indirect calls, if necessary") }, \ | |
470 | {"no-long-calls", -ARM_FLAG_LONG_CALLS, "" }, \ | |
471 | {"thumb", ARM_FLAG_THUMB, \ | |
472 | N_("Compile for the Thumb not the ARM") }, \ | |
473 | {"no-thumb", -ARM_FLAG_THUMB, "" }, \ | |
474 | {"arm", -ARM_FLAG_THUMB, "" }, \ | |
475 | {"tpcs-frame", THUMB_FLAG_BACKTRACE, \ | |
476 | N_("Thumb: Generate (non-leaf) stack frames even if not needed") }, \ | |
477 | {"no-tpcs-frame", -THUMB_FLAG_BACKTRACE, "" }, \ | |
478 | {"tpcs-leaf-frame", THUMB_FLAG_LEAF_BACKTRACE, \ | |
479 | N_("Thumb: Generate (leaf) stack frames even if not needed") }, \ | |
480 | {"no-tpcs-leaf-frame", -THUMB_FLAG_LEAF_BACKTRACE, "" }, \ | |
481 | {"callee-super-interworking", THUMB_FLAG_CALLEE_SUPER_INTERWORKING, \ | |
482 | N_("Thumb: Assume non-static functions may be called from ARM code") }, \ | |
483 | {"no-callee-super-interworking", -THUMB_FLAG_CALLEE_SUPER_INTERWORKING, \ | |
484 | "" }, \ | |
485 | {"caller-super-interworking", THUMB_FLAG_CALLER_SUPER_INTERWORKING, \ | |
486 | N_("Thumb: Assume function pointers may go to non-Thumb aware code") }, \ | |
487 | {"no-caller-super-interworking", -THUMB_FLAG_CALLER_SUPER_INTERWORKING, \ | |
488 | "" }, \ | |
489 | SUBTARGET_SWITCHES \ | |
490 | {"", TARGET_DEFAULT, "" } \ | |
35d965d5 RS |
491 | } |
492 | ||
43cffd11 RE |
493 | #define TARGET_OPTIONS \ |
494 | { \ | |
f5a1b0d2 | 495 | {"cpu=", & arm_select[0].string, \ |
047142d3 | 496 | N_("Specify the name of the target CPU") }, \ |
f5a1b0d2 | 497 | {"arch=", & arm_select[1].string, \ |
047142d3 | 498 | N_("Specify the name of the target architecture") }, \ |
f5a1b0d2 NC |
499 | {"tune=", & arm_select[2].string, "" }, \ |
500 | {"fpe=", & target_fp_name, "" }, \ | |
501 | {"fp=", & target_fp_name, \ | |
047142d3 PT |
502 | N_("Specify the version of the floating point emulator") }, \ |
503 | {"structure-size-boundary=", & structure_size_string, \ | |
504 | N_("Specify the minimum bit alignment of structures") }, \ | |
505 | {"pic-register=", & arm_pic_register_string, \ | |
506 | N_("Specify the register to be used for PIC addressing") } \ | |
11c1a207 | 507 | } |
ff9940b0 | 508 | |
62dd06ea RE |
509 | struct arm_cpu_select |
510 | { | |
f9cc092a RE |
511 | const char * string; |
512 | const char * name; | |
513 | const struct processors * processors; | |
62dd06ea RE |
514 | }; |
515 | ||
f5a1b0d2 NC |
516 | /* This is a magic array. If the user specifies a command line switch |
517 | which matches one of the entries in TARGET_OPTIONS then the corresponding | |
518 | string pointer will be set to the value specified by the user. */ | |
62dd06ea RE |
519 | extern struct arm_cpu_select arm_select[]; |
520 | ||
11c1a207 RE |
521 | enum prog_mode_type |
522 | { | |
523 | prog_mode26, | |
524 | prog_mode32 | |
525 | }; | |
526 | ||
527 | /* Recast the program mode class to be the prog_mode attribute */ | |
528 | #define arm_prog_mode ((enum attr_prog_mode) arm_prgmode) | |
529 | ||
530 | extern enum prog_mode_type arm_prgmode; | |
531 | ||
532 | /* What sort of floating point unit do we have? Hardware or software. | |
533 | If software, is it issue 2 or issue 3? */ | |
24f0c1b4 RE |
534 | enum floating_point_type |
535 | { | |
536 | FP_HARD, | |
11c1a207 RE |
537 | FP_SOFT2, |
538 | FP_SOFT3 | |
24f0c1b4 RE |
539 | }; |
540 | ||
541 | /* Recast the floating point class to be the floating point attribute. */ | |
542 | #define arm_fpu_attr ((enum attr_fpu) arm_fpu) | |
543 | ||
71791e16 | 544 | /* What type of floating point to tune for */ |
24f0c1b4 RE |
545 | extern enum floating_point_type arm_fpu; |
546 | ||
71791e16 RE |
547 | /* What type of floating point instructions are available */ |
548 | extern enum floating_point_type arm_fpu_arch; | |
549 | ||
18543a22 | 550 | /* Default floating point architecture. Override in sub-target if |
71791e16 RE |
551 | necessary. */ |
552 | #define FP_DEFAULT FP_SOFT2 | |
553 | ||
11c1a207 RE |
554 | /* Nonzero if the processor has a fast multiply insn, and one that does |
555 | a 64-bit multiply of two 32-bit values. */ | |
556 | extern int arm_fast_multiply; | |
557 | ||
71791e16 | 558 | /* Nonzero if this chip supports the ARM Architecture 4 extensions */ |
11c1a207 RE |
559 | extern int arm_arch4; |
560 | ||
62b10bbc NC |
561 | /* Nonzero if this chip supports the ARM Architecture 5 extensions */ |
562 | extern int arm_arch5; | |
563 | ||
f5a1b0d2 NC |
564 | /* Nonzero if this chip can benefit from load scheduling. */ |
565 | extern int arm_ld_sched; | |
566 | ||
0616531f RE |
567 | /* Nonzero if generating thumb code. */ |
568 | extern int thumb_code; | |
569 | ||
f5a1b0d2 NC |
570 | /* Nonzero if this chip is a StrongARM. */ |
571 | extern int arm_is_strong; | |
572 | ||
d19fb8e3 NC |
573 | /* Nonzero if this chip is an XScale. */ |
574 | extern int arm_is_xscale; | |
575 | ||
f5a1b0d2 NC |
576 | /* Nonzero if this chip is a an ARM6 or an ARM7. */ |
577 | extern int arm_is_6_or_7; | |
578 | ||
2ce9c1b9 | 579 | #ifndef TARGET_DEFAULT |
d5b7b3ae | 580 | #define TARGET_DEFAULT (ARM_FLAG_APCS_FRAME) |
2ce9c1b9 | 581 | #endif |
35d965d5 | 582 | |
11c1a207 RE |
583 | /* The frame pointer register used in gcc has nothing to do with debugging; |
584 | that is controlled by the APCS-FRAME option. */ | |
d5b7b3ae | 585 | #define CAN_DEBUG_WITHOUT_FP |
35d965d5 | 586 | |
11c1a207 RE |
587 | #define TARGET_MEM_FUNCTIONS 1 |
588 | ||
589 | #define OVERRIDE_OPTIONS arm_override_options () | |
86efdc8e PB |
590 | |
591 | /* Nonzero if PIC code requires explicit qualifiers to generate | |
592 | PLT and GOT relocs rather than the assembler doing so implicitly. | |
ed0e6530 PB |
593 | Subtargets can override these if required. */ |
594 | #ifndef NEED_GOT_RELOC | |
595 | #define NEED_GOT_RELOC 0 | |
596 | #endif | |
597 | #ifndef NEED_PLT_RELOC | |
598 | #define NEED_PLT_RELOC 0 | |
e2723c62 | 599 | #endif |
84306176 PB |
600 | |
601 | /* Nonzero if we need to refer to the GOT with a PC-relative | |
602 | offset. In other words, generate | |
603 | ||
604 | .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)] | |
605 | ||
606 | rather than | |
607 | ||
608 | .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8) | |
609 | ||
610 | The default is true, which matches NetBSD. Subtargets can | |
611 | override this if required. */ | |
612 | #ifndef GOT_PCREL | |
613 | #define GOT_PCREL 1 | |
614 | #endif | |
35d965d5 RS |
615 | \f |
616 | /* Target machine storage Layout. */ | |
617 | ||
ff9940b0 RE |
618 | |
619 | /* Define this macro if it is advisable to hold scalars in registers | |
620 | in a wider mode than that declared by the program. In such cases, | |
621 | the value is constrained to be within the bounds of the declared | |
622 | type, but kept valid in the wider mode. The signedness of the | |
623 | extension may differ from that of the type. */ | |
624 | ||
625 | /* It is far faster to zero extend chars than to sign extend them */ | |
626 | ||
6cfc7210 | 627 | #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ |
2ce9c1b9 RE |
628 | if (GET_MODE_CLASS (MODE) == MODE_INT \ |
629 | && GET_MODE_SIZE (MODE) < 4) \ | |
630 | { \ | |
631 | if (MODE == QImode) \ | |
632 | UNSIGNEDP = 1; \ | |
633 | else if (MODE == HImode) \ | |
5f1e6755 | 634 | UNSIGNEDP = TARGET_MMU_TRAPS != 0; \ |
2ce9c1b9 | 635 | (MODE) = SImode; \ |
ff9940b0 RE |
636 | } |
637 | ||
18543a22 ILT |
638 | /* Define this macro if the promotion described by `PROMOTE_MODE' |
639 | should also be done for outgoing function arguments. */ | |
640 | /* This is required to ensure that push insns always push a word. */ | |
641 | #define PROMOTE_FUNCTION_ARGS | |
642 | ||
ff9940b0 RE |
643 | /* Define for XFmode extended real floating point support. |
644 | This will automatically cause REAL_ARITHMETIC to be defined. */ | |
645 | /* For the ARM: | |
646 | I think I have added all the code to make this work. Unfortunately, | |
647 | early releases of the floating point emulation code on RISCiX used a | |
648 | different format for extended precision numbers. On my RISCiX box there | |
649 | is a bug somewhere which causes the machine to lock up when running enquire | |
650 | with long doubles. There is the additional aspect that Norcroft C | |
651 | treats long doubles as doubles and we ought to remain compatible. | |
652 | Perhaps someone with an FPA coprocessor and not running RISCiX would like | |
653 | to try this someday. */ | |
654 | /* #define LONG_DOUBLE_TYPE_SIZE 96 */ | |
655 | ||
656 | /* Disable XFmode patterns in md file */ | |
657 | #define ENABLE_XF_PATTERNS 0 | |
658 | ||
659 | /* Define if you don't want extended real, but do want to use the | |
660 | software floating point emulator for REAL_ARITHMETIC and | |
661 | decimal <-> binary conversion. */ | |
662 | /* See comment above */ | |
663 | #define REAL_ARITHMETIC | |
664 | ||
35d965d5 RS |
665 | /* Define this if most significant bit is lowest numbered |
666 | in instructions that operate on numbered bit-fields. */ | |
667 | #define BITS_BIG_ENDIAN 0 | |
668 | ||
9c872872 | 669 | /* Define this if most significant byte of a word is the lowest numbered. |
3ada8e17 DE |
670 | Most ARM processors are run in little endian mode, so that is the default. |
671 | If you want to have it run-time selectable, change the definition in a | |
672 | cover file to be TARGET_BIG_ENDIAN. */ | |
11c1a207 | 673 | #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0) |
35d965d5 RS |
674 | |
675 | /* Define this if most significant word of a multiword number is the lowest | |
11c1a207 RE |
676 | numbered. |
677 | This is always false, even when in big-endian mode. */ | |
ddee6aba RE |
678 | #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS) |
679 | ||
680 | /* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based | |
681 | on processor pre-defineds when compiling libgcc2.c. */ | |
682 | #if defined(__ARMEB__) && !defined(__ARMWEL__) | |
683 | #define LIBGCC2_WORDS_BIG_ENDIAN 1 | |
684 | #else | |
685 | #define LIBGCC2_WORDS_BIG_ENDIAN 0 | |
686 | #endif | |
35d965d5 | 687 | |
11c1a207 RE |
688 | /* Define this if most significant word of doubles is the lowest numbered. |
689 | This is always true, even when in little-endian mode. */ | |
7fc6c9f0 RK |
690 | #define FLOAT_WORDS_BIG_ENDIAN 1 |
691 | ||
b4ac57ab | 692 | /* Number of bits in an addressable storage unit */ |
35d965d5 RS |
693 | #define BITS_PER_UNIT 8 |
694 | ||
695 | #define BITS_PER_WORD 32 | |
696 | ||
697 | #define UNITS_PER_WORD 4 | |
698 | ||
699 | #define POINTER_SIZE 32 | |
700 | ||
701 | #define PARM_BOUNDARY 32 | |
702 | ||
703 | #define STACK_BOUNDARY 32 | |
704 | ||
705 | #define FUNCTION_BOUNDARY 32 | |
706 | ||
707 | #define EMPTY_FIELD_BOUNDARY 32 | |
708 | ||
709 | #define BIGGEST_ALIGNMENT 32 | |
710 | ||
ff9940b0 | 711 | /* Make strings word-aligned so strcpy from constants will be faster. */ |
d19fb8e3 NC |
712 | #define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_is_xscale ? 1 : 2) |
713 | ||
714 | #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ | |
715 | ((TREE_CODE (EXP) == STRING_CST \ | |
716 | && (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \ | |
717 | ? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN)) | |
ff9940b0 | 718 | |
723ae7c1 NC |
719 | /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the |
720 | value set in previous versions of this toolchain was 8, which produces more | |
721 | compact structures. The command line option -mstructure_size_boundary=<n> | |
722 | can be used to change this value. For compatability with the ARM SDK | |
723 | however the value should be left at 32. ARM SDT Reference Manual (ARM DUI | |
724 | 0020D) page 2-20 says "Structures are aligned on word boundaries". */ | |
6ead9ba5 NC |
725 | #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary |
726 | extern int arm_structure_size_boundary; | |
723ae7c1 NC |
727 | |
728 | /* This is the value used to initialise arm_structure_size_boundary. If a | |
729 | particular arm target wants to change the default value it should change | |
730 | the definition of this macro, not STRUCTRUE_SIZE_BOUNDARY. See netbsd.h | |
731 | for an example of this. */ | |
732 | #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY | |
733 | #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32 | |
b355a481 | 734 | #endif |
2a5307b1 | 735 | |
b355a481 | 736 | /* Used when parsing command line option -mstructure_size_boundary. */ |
f9cc092a | 737 | extern const char * structure_size_string; |
b4ac57ab | 738 | |
ff9940b0 RE |
739 | /* Non-zero if move instructions will actually fail to work |
740 | when given unaligned data. */ | |
35d965d5 RS |
741 | #define STRICT_ALIGNMENT 1 |
742 | ||
ff9940b0 RE |
743 | #define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT |
744 | ||
35d965d5 RS |
745 | \f |
746 | /* Standard register usage. */ | |
747 | ||
748 | /* Register allocation in ARM Procedure Call Standard (as used on RISCiX): | |
749 | (S - saved over call). | |
750 | ||
751 | r0 * argument word/integer result | |
752 | r1-r3 argument word | |
753 | ||
754 | r4-r8 S register variable | |
755 | r9 S (rfp) register variable (real frame pointer) | |
f5a1b0d2 NC |
756 | |
757 | r10 F S (sl) stack limit (used by -mapcs-stack-check) | |
35d965d5 RS |
758 | r11 F S (fp) argument pointer |
759 | r12 (ip) temp workspace | |
760 | r13 F S (sp) lower end of current stack frame | |
761 | r14 (lr) link address/workspace | |
762 | r15 F (pc) program counter | |
763 | ||
764 | f0 floating point result | |
765 | f1-f3 floating point scratch | |
766 | ||
767 | f4-f7 S floating point variable | |
768 | ||
ff9940b0 RE |
769 | cc This is NOT a real register, but is used internally |
770 | to represent things that use or set the condition | |
771 | codes. | |
772 | sfp This isn't either. It is used during rtl generation | |
773 | since the offset between the frame pointer and the | |
774 | auto's isn't known until after register allocation. | |
775 | afp Nor this, we only need this because of non-local | |
776 | goto. Without it fp appears to be used and the | |
777 | elimination code won't get rid of sfp. It tracks | |
778 | fp exactly at all times. | |
779 | ||
35d965d5 RS |
780 | *: See CONDITIONAL_REGISTER_USAGE */ |
781 | ||
ff9940b0 RE |
782 | /* The stack backtrace structure is as follows: |
783 | fp points to here: | save code pointer | [fp] | |
784 | | return link value | [fp, #-4] | |
785 | | return sp value | [fp, #-8] | |
786 | | return fp value | [fp, #-12] | |
787 | [| saved r10 value |] | |
788 | [| saved r9 value |] | |
789 | [| saved r8 value |] | |
790 | [| saved r7 value |] | |
791 | [| saved r6 value |] | |
792 | [| saved r5 value |] | |
793 | [| saved r4 value |] | |
794 | [| saved r3 value |] | |
795 | [| saved r2 value |] | |
796 | [| saved r1 value |] | |
797 | [| saved r0 value |] | |
798 | [| saved f7 value |] three words | |
799 | [| saved f6 value |] three words | |
800 | [| saved f5 value |] three words | |
801 | [| saved f4 value |] three words | |
802 | r0-r3 are not normally saved in a C function. */ | |
803 | ||
35d965d5 RS |
804 | /* 1 for registers that have pervasive standard uses |
805 | and are not available for the register allocator. */ | |
806 | #define FIXED_REGISTERS \ | |
807 | { \ | |
808 | 0,0,0,0,0,0,0,0, \ | |
d5b7b3ae | 809 | 0,0,0,0,0,1,0,1, \ |
ff9940b0 RE |
810 | 0,0,0,0,0,0,0,0, \ |
811 | 1,1,1 \ | |
35d965d5 RS |
812 | } |
813 | ||
814 | /* 1 for registers not available across function calls. | |
815 | These must include the FIXED_REGISTERS and also any | |
816 | registers that can be used without being saved. | |
817 | The latter must include the registers where values are returned | |
818 | and the register where structure-value addresses are passed. | |
ff9940b0 RE |
819 | Aside from that, you can include as many other registers as you like. |
820 | The CC is not preserved over function calls on the ARM 6, so it is | |
821 | easier to assume this for all. SFP is preserved, since FP is. */ | |
35d965d5 RS |
822 | #define CALL_USED_REGISTERS \ |
823 | { \ | |
824 | 1,1,1,1,0,0,0,0, \ | |
d5b7b3ae | 825 | 0,0,0,0,1,1,1,1, \ |
ff9940b0 RE |
826 | 1,1,1,1,0,0,0,0, \ |
827 | 1,1,1 \ | |
35d965d5 RS |
828 | } |
829 | ||
6cc8c0b3 NC |
830 | #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE |
831 | #define SUBTARGET_CONDITIONAL_REGISTER_USAGE | |
832 | #endif | |
833 | ||
d5b7b3ae RE |
834 | #define CONDITIONAL_REGISTER_USAGE \ |
835 | { \ | |
836 | if (TARGET_SOFT_FLOAT || TARGET_THUMB) \ | |
837 | { \ | |
838 | int regno; \ | |
839 | for (regno = FIRST_ARM_FP_REGNUM; \ | |
840 | regno <= LAST_ARM_FP_REGNUM; ++regno) \ | |
841 | fixed_regs[regno] = call_used_regs[regno] = 1; \ | |
842 | } \ | |
843 | if (flag_pic) \ | |
844 | { \ | |
845 | fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ | |
846 | call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ | |
847 | } \ | |
848 | else if (TARGET_APCS_STACK) \ | |
849 | { \ | |
850 | fixed_regs[10] = 1; \ | |
851 | call_used_regs[10] = 1; \ | |
852 | } \ | |
853 | if (TARGET_APCS_FRAME) \ | |
854 | { \ | |
855 | fixed_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \ | |
856 | call_used_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \ | |
857 | } \ | |
858 | SUBTARGET_CONDITIONAL_REGISTER_USAGE \ | |
35d965d5 | 859 | } |
d5b7b3ae | 860 | |
dd18ae56 NC |
861 | /* These are a couple of extensions to the formats accecpted |
862 | by asm_fprintf: | |
863 | %@ prints out ASM_COMMENT_START | |
864 | %r prints out REGISTER_PREFIX reg_names[arg] */ | |
865 | #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \ | |
866 | case '@': \ | |
867 | fputs (ASM_COMMENT_START, FILE); \ | |
868 | break; \ | |
869 | \ | |
870 | case 'r': \ | |
871 | fputs (REGISTER_PREFIX, FILE); \ | |
872 | fputs (reg_names [va_arg (ARGS, int)], FILE); \ | |
873 | break; | |
874 | ||
d5b7b3ae RE |
875 | /* Round X up to the nearest word. */ |
876 | #define ROUND_UP(X) (((X) + 3) & ~3) | |
877 | ||
6cfc7210 NC |
878 | /* Convert fron bytes to ints. */ |
879 | #define NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) | |
880 | ||
881 | /* The number of (integer) registers required to hold a quantity of type MODE. */ | |
882 | #define NUM_REGS(MODE) \ | |
883 | NUM_INTS (GET_MODE_SIZE (MODE)) | |
884 | ||
885 | /* The number of (integer) registers required to hold a quantity of TYPE MODE. */ | |
886 | #define NUM_REGS2(MODE, TYPE) \ | |
d5b7b3ae RE |
887 | NUM_INTS ((MODE) == BLKmode ? \ |
888 | int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE)) | |
6cfc7210 NC |
889 | |
890 | /* The number of (integer) argument register available. */ | |
d5b7b3ae | 891 | #define NUM_ARG_REGS 4 |
6cfc7210 NC |
892 | |
893 | /* Return the regiser number of the N'th (integer) argument. */ | |
d5b7b3ae | 894 | #define ARG_REGISTER(N) (N - 1) |
6cfc7210 | 895 | |
64a7723d | 896 | /* RTX for structure returns. NULL means use a hidden first argument. */ |
31448271 | 897 | #define STRUCT_VALUE 0 |
6cfc7210 | 898 | |
d5b7b3ae RE |
899 | /* Specify the registers used for certain standard purposes. |
900 | The values of these macros are register numbers. */ | |
35d965d5 | 901 | |
d5b7b3ae RE |
902 | /* The number of the last argument register. */ |
903 | #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS) | |
35d965d5 | 904 | |
d5b7b3ae | 905 | /* The number of the last "lo" register (thumb). */ |
6d3d9133 NC |
906 | #define LAST_LO_REGNUM 7 |
907 | ||
908 | /* The register that holds the return address in exception handlers. */ | |
909 | #define EXCEPTION_LR_REGNUM 2 | |
35d965d5 | 910 | |
d5b7b3ae RE |
911 | /* The native (Norcroft) Pascal compiler for the ARM passes the static chain |
912 | as an invisible last argument (possible since varargs don't exist in | |
913 | Pascal), so the following is not true. */ | |
68dfd979 | 914 | #define STATIC_CHAIN_REGNUM (TARGET_ARM ? 12 : 9) |
35d965d5 | 915 | |
d5b7b3ae RE |
916 | /* Define this to be where the real frame pointer is if it is not possible to |
917 | work out the offset between the frame pointer and the automatic variables | |
918 | until after register allocation has taken place. FRAME_POINTER_REGNUM | |
919 | should point to a special register that we will make sure is eliminated. | |
920 | ||
921 | For the Thumb we have another problem. The TPCS defines the frame pointer | |
922 | as r11, and GCC belives that it is always possible to use the frame pointer | |
923 | as base register for addressing purposes. (See comments in | |
924 | find_reloads_address()). But - the Thumb does not allow high registers, | |
925 | including r11, to be used as base address registers. Hence our problem. | |
926 | ||
927 | The solution used here, and in the old thumb port is to use r7 instead of | |
928 | r11 as the hard frame pointer and to have special code to generate | |
929 | backtrace structures on the stack (if required to do so via a command line | |
930 | option) using r11. This is the only 'user visable' use of r11 as a frame | |
931 | pointer. */ | |
932 | #define ARM_HARD_FRAME_POINTER_REGNUM 11 | |
933 | #define THUMB_HARD_FRAME_POINTER_REGNUM 7 | |
934 | #define HARD_FRAME_POINTER_REGNUM (TARGET_ARM ? ARM_HARD_FRAME_POINTER_REGNUM : THUMB_HARD_FRAME_POINTER_REGNUM) | |
935 | #define FP_REGNUM HARD_FRAME_POINTER_REGNUM | |
35d965d5 | 936 | |
d5b7b3ae RE |
937 | /* Scratch register - used in all kinds of places, eg trampolines. */ |
938 | #define IP_REGNUM 12 | |
35d965d5 RS |
939 | |
940 | /* Register to use for pushing function arguments. */ | |
941 | #define STACK_POINTER_REGNUM 13 | |
6cfc7210 | 942 | #define SP_REGNUM STACK_POINTER_REGNUM |
35d965d5 | 943 | |
d5b7b3ae RE |
944 | /* Register which holds return address from a subroutine call. */ |
945 | #define LR_REGNUM 14 | |
946 | ||
947 | /* Define this if the program counter is overloaded on a register. */ | |
948 | #define PC_REGNUM 15 | |
949 | ||
950 | /* The number of the last ARM (integer) register. */ | |
951 | #define LAST_ARM_REGNUM 15 | |
952 | ||
953 | /* ARM floating pointer registers. */ | |
954 | #define FIRST_ARM_FP_REGNUM 16 | |
955 | #define LAST_ARM_FP_REGNUM 23 | |
956 | ||
957 | /* Internal, so that we don't need to refer to a raw number */ | |
958 | #define CC_REGNUM 24 | |
959 | ||
35d965d5 | 960 | /* Base register for access to local variables of the function. */ |
ff9940b0 RE |
961 | #define FRAME_POINTER_REGNUM 25 |
962 | ||
d5b7b3ae RE |
963 | /* Base register for access to arguments of the function. */ |
964 | #define ARG_POINTER_REGNUM 26 | |
62b10bbc | 965 | |
d5b7b3ae RE |
966 | /* The number of hard registers is 16 ARM + 8 FPU + 1 CC + 1 SFP. */ |
967 | #define FIRST_PSEUDO_REGISTER 27 | |
62b10bbc | 968 | |
35d965d5 RS |
969 | /* Value should be nonzero if functions must have frame pointers. |
970 | Zero means the frame pointer need not be set up (and parms may be accessed | |
ff9940b0 RE |
971 | via the stack pointer) in functions that seem suitable. |
972 | If we have to have a frame pointer we might as well make use of it. | |
973 | APCS says that the frame pointer does not need to be pushed in leaf | |
2a5307b1 | 974 | functions, or simple tail call functions. */ |
d5b7b3ae RE |
975 | #define FRAME_POINTER_REQUIRED \ |
976 | (current_function_has_nonlocal_label \ | |
977 | || (TARGET_ARM && TARGET_APCS_FRAME && ! leaf_function_p ())) | |
35d965d5 | 978 | |
d5b7b3ae RE |
979 | /* Return number of consecutive hard regs needed starting at reg REGNO |
980 | to hold something of mode MODE. | |
981 | This is ordinarily the length in words of a value of mode MODE | |
982 | but can be less for certain modes in special long registers. | |
35d965d5 | 983 | |
d5b7b3ae RE |
984 | On the ARM regs are UNITS_PER_WORD bits wide; FPU regs can hold any FP |
985 | mode. */ | |
986 | #define HARD_REGNO_NREGS(REGNO, MODE) \ | |
987 | ((TARGET_ARM \ | |
988 | && REGNO >= FIRST_ARM_FP_REGNUM \ | |
989 | && REGNO != FRAME_POINTER_REGNUM \ | |
990 | && REGNO != ARG_POINTER_REGNUM) \ | |
991 | ? 1 : NUM_REGS (MODE)) | |
35d965d5 | 992 | |
d5b7b3ae RE |
993 | /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. |
994 | This is TRUE for ARM regs since they can hold anything, and TRUE for FPU | |
995 | regs holding FP. | |
996 | For the Thumb we only allow values bigger than SImode in registers 0 - 6, | |
997 | so that there is always a second lo register available to hold the upper | |
998 | part of the value. Probably we ought to ensure that the register is the | |
999 | start of an even numbered register pair. */ | |
1000 | #define HARD_REGNO_MODE_OK(REGNO, MODE) \ | |
1001 | (TARGET_ARM ? \ | |
1002 | ((GET_MODE_CLASS (MODE) == MODE_CC) ? (REGNO == CC_REGNUM) : \ | |
1003 | ( REGNO <= LAST_ARM_REGNUM \ | |
1004 | || REGNO == FRAME_POINTER_REGNUM \ | |
1005 | || REGNO == ARG_POINTER_REGNUM \ | |
1006 | || GET_MODE_CLASS (MODE) == MODE_FLOAT)) \ | |
1007 | : \ | |
1008 | ((GET_MODE_CLASS (MODE) == MODE_CC) ? (REGNO == CC_REGNUM) : \ | |
1009 | (NUM_REGS (MODE) < 2 || REGNO < LAST_LO_REGNUM))) | |
35d965d5 | 1010 | |
d5b7b3ae RE |
1011 | /* Value is 1 if it is a good idea to tie two pseudo registers |
1012 | when one has mode MODE1 and one has mode MODE2. | |
1013 | If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, | |
1014 | for any hard reg, then this must be 0 for correct output. */ | |
1015 | #define MODES_TIEABLE_P(MODE1, MODE2) \ | |
1016 | (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2)) | |
ff9940b0 | 1017 | |
35d965d5 | 1018 | /* The order in which register should be allocated. It is good to use ip |
ff9940b0 RE |
1019 | since no saving is required (though calls clobber it) and it never contains |
1020 | function parameters. It is quite good to use lr since other calls may | |
1021 | clobber it anyway. Allocate r0 through r3 in reverse order since r3 is | |
1022 | least likely to contain a function parameter; in addition results are | |
d5b7b3ae | 1023 | returned in r0. */ |
ff73fb53 | 1024 | #define REG_ALLOC_ORDER \ |
35d965d5 | 1025 | { \ |
ff73fb53 NC |
1026 | 3, 2, 1, 0, 12, 14, 4, 5, \ |
1027 | 6, 7, 8, 10, 9, 11, 13, 15, \ | |
ff9940b0 | 1028 | 16, 17, 18, 19, 20, 21, 22, 23, \ |
ff73fb53 | 1029 | 24, 25, 26 \ |
35d965d5 RS |
1030 | } |
1031 | \f | |
1032 | /* Register and constant classes. */ | |
1033 | ||
d5b7b3ae RE |
1034 | /* Register classes: used to be simple, just all ARM regs or all FPU regs |
1035 | Now that the Thumb is involved it has become more compilcated. */ | |
35d965d5 RS |
1036 | enum reg_class |
1037 | { | |
1038 | NO_REGS, | |
1039 | FPU_REGS, | |
d5b7b3ae RE |
1040 | LO_REGS, |
1041 | STACK_REG, | |
1042 | BASE_REGS, | |
1043 | HI_REGS, | |
1044 | CC_REG, | |
35d965d5 RS |
1045 | GENERAL_REGS, |
1046 | ALL_REGS, | |
1047 | LIM_REG_CLASSES | |
1048 | }; | |
1049 | ||
1050 | #define N_REG_CLASSES (int) LIM_REG_CLASSES | |
1051 | ||
1052 | /* Give names of register classes as strings for dump file. */ | |
1053 | #define REG_CLASS_NAMES \ | |
1054 | { \ | |
1055 | "NO_REGS", \ | |
1056 | "FPU_REGS", \ | |
d5b7b3ae RE |
1057 | "LO_REGS", \ |
1058 | "STACK_REG", \ | |
1059 | "BASE_REGS", \ | |
1060 | "HI_REGS", \ | |
1061 | "CC_REG", \ | |
35d965d5 RS |
1062 | "GENERAL_REGS", \ |
1063 | "ALL_REGS", \ | |
1064 | } | |
1065 | ||
1066 | /* Define which registers fit in which classes. | |
1067 | This is an initializer for a vector of HARD_REG_SET | |
1068 | of length N_REG_CLASSES. */ | |
aec3cfba NC |
1069 | #define REG_CLASS_CONTENTS \ |
1070 | { \ | |
1071 | { 0x0000000 }, /* NO_REGS */ \ | |
1072 | { 0x0FF0000 }, /* FPU_REGS */ \ | |
d5b7b3ae RE |
1073 | { 0x00000FF }, /* LO_REGS */ \ |
1074 | { 0x0002000 }, /* STACK_REG */ \ | |
1075 | { 0x00020FF }, /* BASE_REGS */ \ | |
1076 | { 0x000FF00 }, /* HI_REGS */ \ | |
1077 | { 0x1000000 }, /* CC_REG */ \ | |
aec3cfba NC |
1078 | { 0x200FFFF }, /* GENERAL_REGS */ \ |
1079 | { 0x2FFFFFF } /* ALL_REGS */ \ | |
35d965d5 | 1080 | } |
d5b7b3ae | 1081 | |
35d965d5 RS |
1082 | /* The same information, inverted: |
1083 | Return the class number of the smallest class containing | |
1084 | reg number REGNO. This could be a conditional expression | |
1085 | or could index an array. */ | |
d5b7b3ae | 1086 | #define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO) |
35d965d5 RS |
1087 | |
1088 | /* The class value for index registers, and the one for base regs. */ | |
d5b7b3ae RE |
1089 | #define INDEX_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS) |
1090 | #define BASE_REG_CLASS (TARGET_THUMB ? BASE_REGS : GENERAL_REGS) | |
1091 | ||
1092 | /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows | |
1093 | registers explicitly used in the rtl to be used as spill registers | |
1094 | but prevents the compiler from extending the lifetime of these | |
1095 | registers. */ | |
1096 | #define SMALL_REGISTER_CLASSES TARGET_THUMB | |
35d965d5 RS |
1097 | |
1098 | /* Get reg_class from a letter such as appears in the machine description. | |
d5b7b3ae RE |
1099 | We only need constraint `f' for FPU_REGS (`r' == GENERAL_REGS) for the |
1100 | ARM, but several more letters for the Thumb. */ | |
1101 | #define REG_CLASS_FROM_LETTER(C) \ | |
1102 | ( (C) == 'f' ? FPU_REGS \ | |
1103 | : (C) == 'l' ? (TARGET_ARM ? GENERAL_REGS : LO_REGS) \ | |
1104 | : TARGET_ARM ? NO_REGS \ | |
1105 | : (C) == 'h' ? HI_REGS \ | |
1106 | : (C) == 'b' ? BASE_REGS \ | |
1107 | : (C) == 'k' ? STACK_REG \ | |
1108 | : (C) == 'c' ? CC_REG \ | |
1109 | : NO_REGS) | |
35d965d5 RS |
1110 | |
1111 | /* The letters I, J, K, L and M in a register constraint string | |
1112 | can be used to stand for particular ranges of immediate operands. | |
1113 | This macro defines what the ranges are. | |
1114 | C is the letter, and VALUE is a constant value. | |
1115 | Return 1 if VALUE is in the range specified by C. | |
b4ac57ab | 1116 | I: immediate arithmetic operand (i.e. 8 bits shifted as required). |
ff9940b0 | 1117 | J: valid indexing constants. |
aef1764c | 1118 | K: ~value ok in rhs argument of data operand. |
3967692c RE |
1119 | L: -value ok in rhs argument of data operand. |
1120 | M: 0..32, or a power of 2 (for shifts, or mult done by shift). */ | |
d5b7b3ae | 1121 | #define CONST_OK_FOR_ARM_LETTER(VALUE, C) \ |
aef1764c RE |
1122 | ((C) == 'I' ? const_ok_for_arm (VALUE) : \ |
1123 | (C) == 'J' ? ((VALUE) < 4096 && (VALUE) > -4096) : \ | |
1124 | (C) == 'K' ? (const_ok_for_arm (~(VALUE))) : \ | |
3967692c RE |
1125 | (C) == 'L' ? (const_ok_for_arm (-(VALUE))) : \ |
1126 | (C) == 'M' ? (((VALUE >= 0 && VALUE <= 32)) \ | |
1127 | || (((VALUE) & ((VALUE) - 1)) == 0)) \ | |
1128 | : 0) | |
ff9940b0 | 1129 | |
d5b7b3ae RE |
1130 | #define CONST_OK_FOR_THUMB_LETTER(VAL, C) \ |
1131 | ((C) == 'I' ? (unsigned HOST_WIDE_INT) (VAL) < 256 : \ | |
1132 | (C) == 'J' ? (VAL) > -256 && (VAL) < 0 : \ | |
1133 | (C) == 'K' ? thumb_shiftable_const (VAL) : \ | |
1134 | (C) == 'L' ? (VAL) > -8 && (VAL) < 8 : \ | |
1135 | (C) == 'M' ? ((unsigned HOST_WIDE_INT) (VAL) < 1024 \ | |
1136 | && ((VAL) & 3) == 0) : \ | |
1137 | (C) == 'N' ? ((unsigned HOST_WIDE_INT) (VAL) < 32) : \ | |
1138 | (C) == 'O' ? ((VAL) >= -508 && (VAL) <= 508) \ | |
1139 | : 0) | |
1140 | ||
1141 | #define CONST_OK_FOR_LETTER_P(VALUE, C) \ | |
1142 | (TARGET_ARM ? \ | |
1143 | CONST_OK_FOR_ARM_LETTER (VALUE, C) : CONST_OK_FOR_THUMB_LETTER (VALUE, C)) | |
1144 | ||
1145 | /* Constant letter 'G' for the FPU immediate constants. | |
1146 | 'H' means the same constant negated. */ | |
1147 | #define CONST_DOUBLE_OK_FOR_ARM_LETTER(X, C) \ | |
1148 | ((C) == 'G' ? const_double_rtx_ok_for_fpu (X) : \ | |
1149 | (C) == 'H' ? neg_const_double_rtx_ok_for_fpu (X) : 0) | |
1150 | ||
1151 | #define CONST_DOUBLE_OK_FOR_LETTER_P(X, C) \ | |
1152 | (TARGET_ARM ? \ | |
1153 | CONST_DOUBLE_OK_FOR_ARM_LETTER (X, C) : 0) | |
1154 | ||
ff9940b0 RE |
1155 | /* For the ARM, `Q' means that this is a memory operand that is just |
1156 | an offset from a register. | |
1157 | `S' means any symbol that has the SYMBOL_REF_FLAG set or a CONSTANT_POOL | |
1158 | address. This means that the symbol is in the text segment and can be | |
1159 | accessed without using a load. */ | |
1160 | ||
d5b7b3ae RE |
1161 | #define EXTRA_CONSTRAINT_ARM(OP, C) \ |
1162 | ((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG : \ | |
1163 | (C) == 'R' ? (GET_CODE (OP) == MEM \ | |
1164 | && GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \ | |
1165 | && CONSTANT_POOL_ADDRESS_P (XEXP (OP, 0))) : \ | |
1166 | (C) == 'S' ? (optimize > 0 && CONSTANT_ADDRESS_P (OP)) \ | |
7a801826 | 1167 | : 0) |
ff9940b0 | 1168 | |
d5b7b3ae RE |
1169 | #define EXTRA_CONSTRAINT_THUMB(X, C) \ |
1170 | ((C) == 'Q' ? (GET_CODE (X) == MEM \ | |
1171 | && GET_CODE (XEXP (X, 0)) == LABEL_REF) : 0) | |
1172 | ||
1173 | #define EXTRA_CONSTRAINT(X, C) \ | |
1174 | (TARGET_ARM ? \ | |
1175 | EXTRA_CONSTRAINT_ARM (X, C) : EXTRA_CONSTRAINT_THUMB (X, C)) | |
35d965d5 RS |
1176 | |
1177 | /* Given an rtx X being reloaded into a reg required to be | |
1178 | in class CLASS, return the class of reg to actually use. | |
d5b7b3ae RE |
1179 | In general this is just CLASS, but for the Thumb we prefer |
1180 | a LO_REGS class or a subset. */ | |
1181 | #define PREFERRED_RELOAD_CLASS(X, CLASS) \ | |
1182 | (TARGET_ARM ? (CLASS) : \ | |
1183 | ((CLASS) == BASE_REGS ? (CLASS) : LO_REGS)) | |
1184 | ||
1185 | /* Must leave BASE_REGS reloads alone */ | |
1186 | #define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \ | |
1187 | ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \ | |
1188 | ? ((true_regnum (X) == -1 ? LO_REGS \ | |
1189 | : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \ | |
1190 | : NO_REGS)) \ | |
1191 | : NO_REGS) | |
1192 | ||
1193 | #define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \ | |
1194 | ((CLASS) != LO_REGS \ | |
1195 | ? ((true_regnum (X) == -1 ? LO_REGS \ | |
1196 | : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \ | |
1197 | : NO_REGS)) \ | |
1198 | : NO_REGS) | |
35d965d5 | 1199 | |
ff9940b0 RE |
1200 | /* Return the register class of a scratch register needed to copy IN into |
1201 | or out of a register in CLASS in MODE. If it can be done directly, | |
1202 | NO_REGS is returned. */ | |
d5b7b3ae RE |
1203 | #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \ |
1204 | (TARGET_ARM ? \ | |
1205 | (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \ | |
1206 | ? GENERAL_REGS : NO_REGS) \ | |
1207 | : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X)) | |
1208 | ||
2ce9c1b9 | 1209 | /* If we need to load shorts byte-at-a-time, then we need a scratch. */ |
d5b7b3ae RE |
1210 | #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \ |
1211 | (TARGET_ARM ? \ | |
1212 | (((MODE) == HImode && ! arm_arch4 && TARGET_MMU_TRAPS \ | |
1213 | && (GET_CODE (X) == MEM \ | |
1214 | || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \ | |
1215 | && true_regnum (X) == -1))) \ | |
1216 | ? GENERAL_REGS : NO_REGS) \ | |
1217 | : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X)) | |
2ce9c1b9 | 1218 | |
6f734908 RE |
1219 | /* Try a machine-dependent way of reloading an illegitimate address |
1220 | operand. If we find one, push the reload and jump to WIN. This | |
1221 | macro is used in only one place: `find_reloads_address' in reload.c. | |
1222 | ||
1223 | For the ARM, we wish to handle large displacements off a base | |
1224 | register by splitting the addend across a MOV and the mem insn. | |
d5b7b3ae RE |
1225 | This can cut the number of reloads needed. */ |
1226 | #define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN) \ | |
1227 | do \ | |
1228 | { \ | |
1229 | if (GET_CODE (X) == PLUS \ | |
1230 | && GET_CODE (XEXP (X, 0)) == REG \ | |
1231 | && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \ | |
1232 | && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \ | |
1233 | && GET_CODE (XEXP (X, 1)) == CONST_INT) \ | |
1234 | { \ | |
1235 | HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \ | |
1236 | HOST_WIDE_INT low, high; \ | |
1237 | \ | |
1238 | if (MODE == DImode || (TARGET_SOFT_FLOAT && MODE == DFmode)) \ | |
1239 | low = ((val & 0xf) ^ 0x8) - 0x8; \ | |
1240 | else if (MODE == SImode \ | |
1241 | || (MODE == SFmode && TARGET_SOFT_FLOAT) \ | |
1242 | || ((MODE == HImode || MODE == QImode) && ! arm_arch4)) \ | |
1243 | /* Need to be careful, -4096 is not a valid offset. */ \ | |
1244 | low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff); \ | |
1245 | else if ((MODE == HImode || MODE == QImode) && arm_arch4) \ | |
1246 | /* Need to be careful, -256 is not a valid offset. */ \ | |
1247 | low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \ | |
1248 | else if (GET_MODE_CLASS (MODE) == MODE_FLOAT \ | |
1249 | && TARGET_HARD_FLOAT) \ | |
1250 | /* Need to be careful, -1024 is not a valid offset. */ \ | |
1251 | low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \ | |
1252 | else \ | |
1253 | break; \ | |
1254 | \ | |
e5951263 NC |
1255 | high = ((((val - low) & HOST_UINT (0xffffffff)) \ |
1256 | ^ HOST_UINT (0x80000000)) \ | |
1257 | - HOST_UINT (0x80000000)); \ | |
d5b7b3ae RE |
1258 | /* Check for overflow or zero */ \ |
1259 | if (low == 0 || high == 0 || (high + low != val)) \ | |
1260 | break; \ | |
1261 | \ | |
1262 | /* Reload the high part into a base reg; leave the low part \ | |
1263 | in the mem. */ \ | |
1264 | X = gen_rtx_PLUS (GET_MODE (X), \ | |
1265 | gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \ | |
1266 | GEN_INT (high)), \ | |
1267 | GEN_INT (low)); \ | |
1268 | push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL_PTR, \ | |
1269 | BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \ | |
1270 | OPNUM, TYPE); \ | |
1271 | goto WIN; \ | |
1272 | } \ | |
1273 | } \ | |
62b10bbc | 1274 | while (0) |
6f734908 | 1275 | |
d5b7b3ae RE |
1276 | /* ??? If an HImode FP+large_offset address is converted to an HImode |
1277 | SP+large_offset address, then reload won't know how to fix it. It sees | |
1278 | only that SP isn't valid for HImode, and so reloads the SP into an index | |
1279 | register, but the resulting address is still invalid because the offset | |
1280 | is too big. We fix it here instead by reloading the entire address. */ | |
1281 | /* We could probably achieve better results by defining PROMOTE_MODE to help | |
1282 | cope with the variances between the Thumb's signed and unsigned byte and | |
1283 | halfword load instructions. */ | |
1284 | #define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \ | |
1285 | { \ | |
1286 | if (GET_CODE (X) == PLUS \ | |
1287 | && GET_MODE_SIZE (MODE) < 4 \ | |
1288 | && GET_CODE (XEXP (X, 0)) == REG \ | |
1289 | && XEXP (X, 0) == stack_pointer_rtx \ | |
1290 | && GET_CODE (XEXP (X, 1)) == CONST_INT \ | |
f1008e52 | 1291 | && ! THUMB_LEGITIMATE_OFFSET (MODE, INTVAL (XEXP (X, 1)))) \ |
d5b7b3ae RE |
1292 | { \ |
1293 | rtx orig_X = X; \ | |
1294 | X = copy_rtx (X); \ | |
1295 | push_reload (orig_X, NULL_RTX, &X, NULL_PTR, \ | |
1296 | BASE_REG_CLASS, \ | |
1297 | Pmode, VOIDmode, 0, 0, OPNUM, TYPE); \ | |
1298 | goto WIN; \ | |
1299 | } \ | |
1300 | } | |
1301 | ||
1302 | #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \ | |
1303 | if (TARGET_ARM) \ | |
1304 | ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \ | |
1305 | else \ | |
1306 | THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) | |
1307 | ||
35d965d5 RS |
1308 | /* Return the maximum number of consecutive registers |
1309 | needed to represent mode MODE in a register of class CLASS. | |
1310 | ARM regs are UNITS_PER_WORD bits while FPU regs can hold any FP mode */ | |
1311 | #define CLASS_MAX_NREGS(CLASS, MODE) \ | |
6cfc7210 | 1312 | ((CLASS) == FPU_REGS ? 1 : NUM_REGS (MODE)) |
35d965d5 | 1313 | |
ff9940b0 | 1314 | /* Moves between FPU_REGS and GENERAL_REGS are two memory insns. */ |
cf011243 | 1315 | #define REGISTER_MOVE_COST(MODE, FROM, TO) \ |
d5b7b3ae RE |
1316 | (TARGET_ARM ? \ |
1317 | ((FROM) == FPU_REGS && (TO) != FPU_REGS ? 20 : \ | |
1318 | (FROM) != FPU_REGS && (TO) == FPU_REGS ? 20 : 2) \ | |
1319 | : \ | |
1320 | ((FROM) == HI_REGS || (TO) == HI_REGS) ? 4 : 2) | |
35d965d5 | 1321 | \f |
b0888988 RE |
1322 | /* Register Renaming Parameters. */ |
1323 | ||
1324 | /* A C expression that is nonzero if hard register number TO can be | |
1325 | considered for use as a rename register for FROM. | |
1326 | ||
1327 | If the return register isn't already live, we mustn't use it. */ | |
1328 | ||
1329 | #define HARD_REGNO_RENAME_OK(FROM,TO) \ | |
1330 | ((TO) != LR_REGNUM || regs_ever_live[LR_REGNUM]) | |
1331 | ||
1332 | \f | |
35d965d5 RS |
1333 | /* Stack layout; function entry, exit and calling. */ |
1334 | ||
1335 | /* Define this if pushing a word on the stack | |
1336 | makes the stack pointer a smaller address. */ | |
1337 | #define STACK_GROWS_DOWNWARD 1 | |
1338 | ||
1339 | /* Define this if the nominal address of the stack frame | |
1340 | is at the high-address end of the local variables; | |
1341 | that is, each additional local variable allocated | |
1342 | goes at a more negative offset in the frame. */ | |
1343 | #define FRAME_GROWS_DOWNWARD 1 | |
1344 | ||
1345 | /* Offset within stack frame to start allocating local variables at. | |
1346 | If FRAME_GROWS_DOWNWARD, this is the offset to the END of the | |
1347 | first local allocated. Otherwise, it is the offset to the BEGINNING | |
1348 | of the first local allocated. */ | |
1349 | #define STARTING_FRAME_OFFSET 0 | |
1350 | ||
1351 | /* If we generate an insn to push BYTES bytes, | |
1352 | this says how many the stack pointer really advances by. */ | |
d5b7b3ae RE |
1353 | /* The push insns do not do this rounding implicitly. |
1354 | So don't define this. */ | |
1355 | /* #define PUSH_ROUNDING(NPUSHED) ROUND_UP (NPUSHED) */ | |
18543a22 ILT |
1356 | |
1357 | /* Define this if the maximum size of all the outgoing args is to be | |
1358 | accumulated and pushed during the prologue. The amount can be | |
1359 | found in the variable current_function_outgoing_args_size. */ | |
6cfc7210 | 1360 | #define ACCUMULATE_OUTGOING_ARGS 1 |
35d965d5 RS |
1361 | |
1362 | /* Offset of first parameter from the argument pointer register value. */ | |
d5b7b3ae | 1363 | #define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0) |
35d965d5 RS |
1364 | |
1365 | /* Value is the number of byte of arguments automatically | |
1366 | popped when returning from a subroutine call. | |
8b109b37 | 1367 | FUNDECL is the declaration node of the function (as a tree), |
35d965d5 RS |
1368 | FUNTYPE is the data type of the function (as a tree), |
1369 | or for a library call it is an identifier node for the subroutine name. | |
1370 | SIZE is the number of bytes of arguments passed on the stack. | |
1371 | ||
1372 | On the ARM, the caller does not pop any of its arguments that were passed | |
1373 | on the stack. */ | |
6cfc7210 | 1374 | #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0 |
35d965d5 RS |
1375 | |
1376 | /* Define how to find the value returned by a library function | |
1377 | assuming the value has mode MODE. */ | |
1378 | #define LIBCALL_VALUE(MODE) \ | |
d5b7b3ae RE |
1379 | (TARGET_ARM && TARGET_HARD_FLOAT && GET_MODE_CLASS (MODE) == MODE_FLOAT \ |
1380 | ? gen_rtx_REG (MODE, FIRST_ARM_FP_REGNUM) \ | |
1381 | : gen_rtx_REG (MODE, ARG_REGISTER (1))) | |
35d965d5 | 1382 | |
6cfc7210 NC |
1383 | /* Define how to find the value returned by a function. |
1384 | VALTYPE is the data type of the value (as a tree). | |
1385 | If the precise function being called is known, FUNC is its FUNCTION_DECL; | |
1386 | otherwise, FUNC is 0. */ | |
d5b7b3ae | 1387 | #define FUNCTION_VALUE(VALTYPE, FUNC) \ |
6cfc7210 NC |
1388 | LIBCALL_VALUE (TYPE_MODE (VALTYPE)) |
1389 | ||
35d965d5 RS |
1390 | /* 1 if N is a possible register number for a function value. |
1391 | On the ARM, only r0 and f0 can return results. */ | |
1392 | #define FUNCTION_VALUE_REGNO_P(REGNO) \ | |
d5b7b3ae RE |
1393 | ((REGNO) == ARG_REGISTER (1) \ |
1394 | || (TARGET_ARM && ((REGNO) == FIRST_ARM_FP_REGNUM) && TARGET_HARD_FLOAT)) | |
35d965d5 | 1395 | |
11c1a207 RE |
1396 | /* How large values are returned */ |
1397 | /* A C expression which can inhibit the returning of certain function values | |
1398 | in registers, based on the type of value. */ | |
f5a1b0d2 | 1399 | #define RETURN_IN_MEMORY(TYPE) arm_return_in_memory (TYPE) |
11c1a207 RE |
1400 | |
1401 | /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return | |
1402 | values must be in memory. On the ARM, they need only do so if larger | |
1403 | than a word, or if they contain elements offset from zero in the struct. */ | |
1404 | #define DEFAULT_PCC_STRUCT_RETURN 0 | |
1405 | ||
d5b7b3ae RE |
1406 | /* Flags for the call/call_value rtl operations set up by function_arg. */ |
1407 | #define CALL_NORMAL 0x00000000 /* No special processing. */ | |
1408 | #define CALL_LONG 0x00000001 /* Always call indirect. */ | |
1409 | #define CALL_SHORT 0x00000002 /* Never call indirect. */ | |
1410 | ||
6d3d9133 NC |
1411 | /* These bits describe the different types of function supported |
1412 | by the ARM backend. They are exclusive. ie a function cannot be both a | |
1413 | normal function and an interworked function, for example. Knowing the | |
1414 | type of a function is important for determining its prologue and | |
1415 | epilogue sequences. | |
1416 | Note value 7 is currently unassigned. Also note that the interrupt | |
1417 | function types all have bit 2 set, so that they can be tested for easily. | |
1418 | Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the | |
1419 | machine_function structure is initialised (to zero) func_type will | |
1420 | default to unknown. This will force the first use of arm_current_func_type | |
1421 | to call arm_compute_func_type. */ | |
1422 | #define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */ | |
1423 | #define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */ | |
1424 | #define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */ | |
1425 | #define ARM_FT_EXCEPTION_HANDLER 3 /* A C++ exception handler. */ | |
1426 | #define ARM_FT_ISR 4 /* An interrupt service routine. */ | |
1427 | #define ARM_FT_FIQ 5 /* A fast interrupt service routine. */ | |
1428 | #define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */ | |
1429 | ||
1430 | #define ARM_FT_TYPE_MASK ((1 << 3) - 1) | |
1431 | ||
1432 | /* In addition functions can have several type modifiers, | |
1433 | outlined by these bit masks: */ | |
1434 | #define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */ | |
1435 | #define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */ | |
1436 | #define ARM_FT_VOLATILE (1 << 4) /* Does not return. */ | |
1437 | #define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */ | |
1438 | ||
1439 | /* Some macros to test these flags. */ | |
1440 | #define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK) | |
1441 | #define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT) | |
1442 | #define IS_VOLATILE(t) (t & ARM_FT_VOLATILE) | |
1443 | #define IS_NAKED(t) (t & ARM_FT_NAKED) | |
1444 | #define IS_NESTED(t) (t & ARM_FT_NESTED) | |
1445 | ||
1446 | /* A C structure for machine-specific, per-function data. | |
1447 | This is added to the cfun structure. */ | |
1448 | typedef struct machine_function | |
d5b7b3ae RE |
1449 | { |
1450 | /* Records __builtin_return address. */ | |
1451 | struct rtx_def *ra_rtx; | |
1452 | /* Additionsl stack adjustment in __builtin_eh_throw. */ | |
1453 | struct rtx_def *eh_epilogue_sp_ofs; | |
1454 | /* Records if LR has to be saved for far jumps. */ | |
1455 | int far_jump_used; | |
1456 | /* Records if ARG_POINTER was ever live. */ | |
1457 | int arg_pointer_live; | |
6f7ebcbb NC |
1458 | /* Records if the save of LR has been eliminated. */ |
1459 | int lr_save_eliminated; | |
6d3d9133 NC |
1460 | /* Records the type of the current function. */ |
1461 | unsigned long func_type; | |
1462 | } | |
1463 | machine_function; | |
d5b7b3ae | 1464 | |
82e9d970 PB |
1465 | /* A C type for declaring a variable that is used as the first argument of |
1466 | `FUNCTION_ARG' and other related values. For some target machines, the | |
1467 | type `int' suffices and can hold the number of bytes of argument so far. */ | |
1468 | typedef struct | |
1469 | { | |
d5b7b3ae | 1470 | /* This is the number of registers of arguments scanned so far. */ |
82e9d970 | 1471 | int nregs; |
d5b7b3ae | 1472 | /* One of CALL_NORMAL, CALL_LONG or CALL_SHORT . */ |
82e9d970 | 1473 | int call_cookie; |
d5b7b3ae | 1474 | } CUMULATIVE_ARGS; |
82e9d970 | 1475 | |
35d965d5 RS |
1476 | /* Define where to put the arguments to a function. |
1477 | Value is zero to push the argument on the stack, | |
1478 | or a hard register in which to store the argument. | |
1479 | ||
1480 | MODE is the argument's machine mode. | |
1481 | TYPE is the data type of the argument (as a tree). | |
1482 | This is null for libcalls where that information may | |
1483 | not be available. | |
1484 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
1485 | the preceding args and about the function being called. | |
1486 | NAMED is nonzero if this argument is a named parameter | |
1487 | (otherwise it is an extra parameter matching an ellipsis). | |
1488 | ||
1489 | On the ARM, normally the first 16 bytes are passed in registers r0-r3; all | |
1490 | other arguments are passed on the stack. If (NAMED == 0) (which happens | |
1491 | only in assign_parms, since SETUP_INCOMING_VARARGS is defined), say it is | |
1492 | passed in the stack (function_prologue will indeed make it pass in the | |
1493 | stack if necessary). */ | |
82e9d970 PB |
1494 | #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ |
1495 | arm_function_arg (&(CUM), (MODE), (TYPE), (NAMED)) | |
35d965d5 RS |
1496 | |
1497 | /* For an arg passed partly in registers and partly in memory, | |
1498 | this is the number of registers used. | |
1499 | For args passed entirely in registers or entirely in memory, zero. */ | |
6cfc7210 | 1500 | #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \ |
82e9d970 PB |
1501 | ( NUM_ARG_REGS > (CUM).nregs \ |
1502 | && (NUM_ARG_REGS < ((CUM).nregs + NUM_REGS2 (MODE, TYPE))) \ | |
1503 | ? NUM_ARG_REGS - (CUM).nregs : 0) | |
35d965d5 RS |
1504 | |
1505 | /* Initialize a variable CUM of type CUMULATIVE_ARGS | |
1506 | for a call to a function whose data type is FNTYPE. | |
1507 | For a library call, FNTYPE is 0. | |
1508 | On the ARM, the offset starts at 0. */ | |
82e9d970 PB |
1509 | #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \ |
1510 | arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (INDIRECT)) | |
35d965d5 RS |
1511 | |
1512 | /* Update the data in CUM to advance over an argument | |
1513 | of mode MODE and data type TYPE. | |
1514 | (TYPE is null for libcalls where that information may not be available.) */ | |
6cfc7210 | 1515 | #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ |
82e9d970 | 1516 | (CUM).nregs += NUM_REGS2 (MODE, TYPE) |
35d965d5 RS |
1517 | |
1518 | /* 1 if N is a possible register number for function argument passing. | |
1519 | On the ARM, r0-r3 are used to pass args. */ | |
1520 | #define FUNCTION_ARG_REGNO_P(REGNO) \ | |
1521 | ((REGNO) >= 0 && (REGNO) <= 3) | |
1522 | ||
f99fce0c RE |
1523 | \f |
1524 | /* Tail calling. */ | |
1525 | ||
1526 | /* A C expression that evaluates to true if it is ok to perform a sibling | |
1527 | call to DECL. */ | |
1528 | #define FUNCTION_OK_FOR_SIBCALL(DECL) arm_function_ok_for_sibcall ((DECL)) | |
1529 | ||
35d965d5 RS |
1530 | /* Perform any actions needed for a function that is receiving a variable |
1531 | number of arguments. CUM is as above. MODE and TYPE are the mode and type | |
1532 | of the current parameter. PRETEND_SIZE is a variable that should be set to | |
1533 | the amount of stack that must be pushed by the prolog to pretend that our | |
1534 | caller pushed it. | |
1535 | ||
1536 | Normally, this macro will push all remaining incoming registers on the | |
1537 | stack and set PRETEND_SIZE to the length of the registers pushed. | |
1538 | ||
1539 | On the ARM, PRETEND_SIZE is set in order to have the prologue push the last | |
1540 | named arg and all anonymous args onto the stack. | |
1541 | XXX I know the prologue shouldn't be pushing registers, but it is faster | |
1542 | that way. */ | |
6cfc7210 | 1543 | #define SETUP_INCOMING_VARARGS(CUM, MODE, TYPE, PRETEND_SIZE, NO_RTL) \ |
35d965d5 RS |
1544 | { \ |
1545 | extern int current_function_anonymous_args; \ | |
1546 | current_function_anonymous_args = 1; \ | |
82e9d970 PB |
1547 | if ((CUM).nregs < NUM_ARG_REGS) \ |
1548 | (PRETEND_SIZE) = (NUM_ARG_REGS - (CUM).nregs) * UNITS_PER_WORD; \ | |
35d965d5 RS |
1549 | } |
1550 | ||
1551 | /* Generate assembly output for the start of a function. */ | |
d5b7b3ae RE |
1552 | #define FUNCTION_PROLOGUE(STREAM, SIZE) \ |
1553 | do \ | |
1554 | { \ | |
1555 | if (TARGET_ARM) \ | |
1556 | output_arm_prologue (STREAM, SIZE); \ | |
1557 | else \ | |
1558 | output_thumb_prologue (STREAM); \ | |
1559 | } \ | |
1560 | while (0) | |
35d965d5 | 1561 | |
afef3d7a NC |
1562 | /* If your target environment doesn't prefix user functions with an |
1563 | underscore, you may wish to re-define this to prevent any conflicts. | |
1564 | e.g. AOF may prefix mcount with an underscore. */ | |
1565 | #ifndef ARM_MCOUNT_NAME | |
1566 | #define ARM_MCOUNT_NAME "*mcount" | |
1567 | #endif | |
1568 | ||
1569 | /* Call the function profiler with a given profile label. The Acorn | |
1570 | compiler puts this BEFORE the prolog but gcc puts it afterwards. | |
1571 | On the ARM the full profile code will look like: | |
1572 | .data | |
1573 | LP1 | |
1574 | .word 0 | |
1575 | .text | |
1576 | mov ip, lr | |
1577 | bl mcount | |
1578 | .word LP1 | |
1579 | ||
1580 | profile_function() in final.c outputs the .data section, FUNCTION_PROFILER | |
1581 | will output the .text section. | |
1582 | ||
1583 | The ``mov ip,lr'' seems like a good idea to stick with cc convention. | |
1584 | ``prof'' doesn't seem to mind about this! */ | |
d5b7b3ae | 1585 | #define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \ |
6cfc7210 NC |
1586 | { \ |
1587 | char temp[20]; \ | |
1588 | rtx sym; \ | |
1589 | \ | |
dd18ae56 | 1590 | asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \ |
d5b7b3ae | 1591 | IP_REGNUM, LR_REGNUM); \ |
6cfc7210 NC |
1592 | assemble_name (STREAM, ARM_MCOUNT_NAME); \ |
1593 | fputc ('\n', STREAM); \ | |
1594 | ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \ | |
1595 | sym = gen_rtx (SYMBOL_REF, Pmode, temp); \ | |
1596 | ASM_OUTPUT_INT (STREAM, sym); \ | |
35d965d5 RS |
1597 | } |
1598 | ||
d5b7b3ae RE |
1599 | #define THUMB_FUNCTION_PROFILER(STREAM, LABELNO) \ |
1600 | { \ | |
1601 | fprintf (STREAM, "\tmov\\tip, lr\n"); \ | |
1602 | fprintf (STREAM, "\tbl\tmcount\n"); \ | |
1603 | fprintf (STREAM, "\t.word\tLP%d\n", LABELNO); \ | |
1604 | } | |
1605 | ||
1606 | #define FUNCTION_PROFILER(STREAM, LABELNO) \ | |
1607 | if (TARGET_ARM) \ | |
1608 | ARM_FUNCTION_PROFILER (STREAM, LABELNO) \ | |
1609 | else \ | |
1610 | THUMB_FUNCTION_PROFILER (STREAM, LABELNO) | |
1611 | ||
35d965d5 RS |
1612 | /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, |
1613 | the stack pointer does not matter. The value is tested only in | |
1614 | functions that have frame pointers. | |
1615 | No definition is equivalent to always zero. | |
1616 | ||
1617 | On the ARM, the function epilogue recovers the stack pointer from the | |
1618 | frame. */ | |
1619 | #define EXIT_IGNORE_STACK 1 | |
1620 | ||
1621 | /* Generate the assembly code for function exit. */ | |
d5b7b3ae | 1622 | #define FUNCTION_EPILOGUE(STREAM, SIZE) \ |
eb3921e8 | 1623 | output_func_epilogue (SIZE) |
35d965d5 RS |
1624 | |
1625 | /* Determine if the epilogue should be output as RTL. | |
1626 | You should override this if you define FUNCTION_EXTRA_EPILOGUE. */ | |
d5b7b3ae RE |
1627 | #define USE_RETURN_INSN(ISCOND) \ |
1628 | (TARGET_ARM ? use_return_insn (ISCOND) : 0) | |
ff9940b0 RE |
1629 | |
1630 | /* Definitions for register eliminations. | |
1631 | ||
1632 | This is an array of structures. Each structure initializes one pair | |
1633 | of eliminable registers. The "from" register number is given first, | |
1634 | followed by "to". Eliminations of the same "from" register are listed | |
1635 | in order of preference. | |
1636 | ||
1637 | We have two registers that can be eliminated on the ARM. First, the | |
1638 | arg pointer register can often be eliminated in favor of the stack | |
1639 | pointer register. Secondly, the pseudo frame pointer register can always | |
1640 | be eliminated; it is replaced with either the stack or the real frame | |
d5b7b3ae RE |
1641 | pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM |
1642 | because the defintion of HARD_FRAME_POINTER_REGNUM is not a constant. */ | |
ff9940b0 | 1643 | |
d5b7b3ae RE |
1644 | #define ELIMINABLE_REGS \ |
1645 | {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\ | |
1646 | { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\ | |
1647 | { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\ | |
1648 | { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\ | |
1649 | { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\ | |
1650 | { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\ | |
1651 | { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }} | |
ff9940b0 | 1652 | |
d5b7b3ae RE |
1653 | /* Given FROM and TO register numbers, say whether this elimination is |
1654 | allowed. Frame pointer elimination is automatically handled. | |
ff9940b0 RE |
1655 | |
1656 | All eliminations are permissible. Note that ARG_POINTER_REGNUM and | |
abc95ed3 | 1657 | HARD_FRAME_POINTER_REGNUM are in fact the same thing. If we need a frame |
ff9940b0 | 1658 | pointer, we must eliminate FRAME_POINTER_REGNUM into |
d5b7b3ae RE |
1659 | HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM or |
1660 | ARG_POINTER_REGNUM. */ | |
1661 | #define CAN_ELIMINATE(FROM, TO) \ | |
1662 | (((TO) == FRAME_POINTER_REGNUM && (FROM) == ARG_POINTER_REGNUM) ? 0 : \ | |
1663 | ((TO) == STACK_POINTER_REGNUM && frame_pointer_needed) ? 0 : \ | |
1664 | ((TO) == ARM_HARD_FRAME_POINTER_REGNUM && TARGET_THUMB) ? 0 : \ | |
1665 | ((TO) == THUMB_HARD_FRAME_POINTER_REGNUM && TARGET_ARM) ? 0 : \ | |
1666 | 1) | |
1667 | ||
1668 | /* Define the offset between two registers, one to be eliminated, and the | |
1669 | other its replacement, at the start of a routine. */ | |
1670 | #define ARM_INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ | |
ff9940b0 | 1671 | { \ |
6d3d9133 | 1672 | int volatile_func = IS_VOLATILE (arm_current_func_type ()); \ |
ff9940b0 | 1673 | if ((FROM) == ARG_POINTER_REGNUM && (TO) == HARD_FRAME_POINTER_REGNUM)\ |
68dfd979 NC |
1674 | { \ |
1675 | if (! current_function_needs_context || ! frame_pointer_needed) \ | |
1676 | (OFFSET) = 0; \ | |
1677 | else \ | |
1678 | (OFFSET) = 4; \ | |
1679 | } \ | |
18543a22 ILT |
1680 | else if ((FROM) == FRAME_POINTER_REGNUM \ |
1681 | && (TO) == STACK_POINTER_REGNUM) \ | |
9daca635 | 1682 | (OFFSET) = current_function_outgoing_args_size \ |
d5b7b3ae | 1683 | + ROUND_UP (get_frame_size ()); \ |
ff9940b0 RE |
1684 | else \ |
1685 | { \ | |
1686 | int regno; \ | |
1687 | int offset = 12; \ | |
008cf58a | 1688 | int saved_hard_reg = 0; \ |
ff9940b0 | 1689 | \ |
3967692c RE |
1690 | if (! volatile_func) \ |
1691 | { \ | |
1692 | for (regno = 0; regno <= 10; regno++) \ | |
1693 | if (regs_ever_live[regno] && ! call_used_regs[regno]) \ | |
1694 | saved_hard_reg = 1, offset += 4; \ | |
d5b7b3ae RE |
1695 | if (! TARGET_APCS_FRAME \ |
1696 | && ! frame_pointer_needed \ | |
1697 | && regs_ever_live[HARD_FRAME_POINTER_REGNUM] \ | |
1698 | && ! call_used_regs[HARD_FRAME_POINTER_REGNUM]) \ | |
1699 | saved_hard_reg = 1, offset += 4; \ | |
6ed30148 RE |
1700 | /* PIC register is a fixed reg, so call_used_regs set. */ \ |
1701 | if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM]) \ | |
1702 | saved_hard_reg = 1, offset += 4; \ | |
d5b7b3ae RE |
1703 | for (regno = FIRST_ARM_FP_REGNUM; \ |
1704 | regno <= LAST_ARM_FP_REGNUM; regno++) \ | |
3967692c RE |
1705 | if (regs_ever_live[regno] && ! call_used_regs[regno]) \ |
1706 | offset += 12; \ | |
1707 | } \ | |
ff9940b0 | 1708 | if ((FROM) == FRAME_POINTER_REGNUM) \ |
d5b7b3ae | 1709 | (OFFSET) = - offset; \ |
ff9940b0 RE |
1710 | else \ |
1711 | { \ | |
bd4d60ce | 1712 | if (! frame_pointer_needed) \ |
ff9940b0 | 1713 | offset -= 16; \ |
18543a22 | 1714 | if (! volatile_func \ |
62b10bbc | 1715 | && (regs_ever_live[LR_REGNUM] || saved_hard_reg)) \ |
ff9940b0 | 1716 | offset += 4; \ |
18543a22 | 1717 | offset += current_function_outgoing_args_size; \ |
d5b7b3ae | 1718 | (OFFSET) = ROUND_UP (get_frame_size ()) + offset; \ |
ff9940b0 RE |
1719 | } \ |
1720 | } \ | |
1721 | } | |
35d965d5 | 1722 | |
d5b7b3ae RE |
1723 | /* Note: This macro must match the code in thumb_function_prologue(). */ |
1724 | #define THUMB_INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ | |
1725 | { \ | |
1726 | (OFFSET) = 0; \ | |
1727 | if ((FROM) == ARG_POINTER_REGNUM) \ | |
1728 | { \ | |
1729 | int count_regs = 0; \ | |
1730 | int regno; \ | |
1731 | for (regno = 8; regno < 13; regno ++) \ | |
1732 | if (regs_ever_live[regno] && ! call_used_regs[regno]) \ | |
1733 | count_regs ++; \ | |
1734 | if (count_regs) \ | |
1735 | (OFFSET) += 4 * count_regs; \ | |
1736 | count_regs = 0; \ | |
1737 | for (regno = 0; regno <= LAST_LO_REGNUM; regno ++) \ | |
1738 | if (regs_ever_live[regno] && ! call_used_regs[regno]) \ | |
1739 | count_regs ++; \ | |
1740 | if (count_regs || ! leaf_function_p () || thumb_far_jump_used_p (0))\ | |
1741 | (OFFSET) += 4 * (count_regs + 1); \ | |
1742 | if (TARGET_BACKTRACE) \ | |
1743 | { \ | |
1744 | if ((count_regs & 0xFF) == 0 && (regs_ever_live[3] != 0)) \ | |
1745 | (OFFSET) += 20; \ | |
1746 | else \ | |
1747 | (OFFSET) += 16; \ | |
1748 | } \ | |
1749 | } \ | |
1750 | if ((TO) == STACK_POINTER_REGNUM) \ | |
1751 | { \ | |
1752 | (OFFSET) += current_function_outgoing_args_size; \ | |
1753 | (OFFSET) += ROUND_UP (get_frame_size ()); \ | |
1754 | } \ | |
1755 | } | |
1756 | ||
1757 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ | |
1758 | if (TARGET_ARM) \ | |
1759 | ARM_INITIAL_ELIMINATION_OFFSET (FROM, TO, OFFSET) \ | |
1760 | else \ | |
1761 | THUMB_INITIAL_ELIMINATION_OFFSET (FROM, TO, OFFSET) | |
1762 | ||
1763 | /* Special case handling of the location of arguments passed on the stack. */ | |
1764 | #define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr) | |
1765 | ||
1766 | /* Initialize data used by insn expanders. This is called from insn_emit, | |
1767 | once for every function before code is generated. */ | |
1768 | #define INIT_EXPANDERS arm_init_expanders () | |
1769 | ||
35d965d5 RS |
1770 | /* Output assembler code for a block containing the constant parts |
1771 | of a trampoline, leaving space for the variable parts. | |
1772 | ||
1773 | On the ARM, (if r8 is the static chain regnum, and remembering that | |
1774 | referencing pc adds an offset of 8) the trampoline looks like: | |
1775 | ldr r8, [pc, #0] | |
1776 | ldr pc, [pc] | |
1777 | .word static chain value | |
11c1a207 RE |
1778 | .word function's address |
1779 | ??? FIXME: When the trampoline returns, r8 will be clobbered. */ | |
d5b7b3ae RE |
1780 | #define ARM_TRAMPOLINE_TEMPLATE(FILE) \ |
1781 | { \ | |
1782 | asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \ | |
1783 | STATIC_CHAIN_REGNUM, PC_REGNUM); \ | |
1784 | asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \ | |
1785 | PC_REGNUM, PC_REGNUM); \ | |
1786 | ASM_OUTPUT_INT (FILE, const0_rtx); \ | |
1787 | ASM_OUTPUT_INT (FILE, const0_rtx); \ | |
1788 | } | |
1789 | ||
1790 | /* On the Thumb we always switch into ARM mode to execute the trampoline. | |
1791 | Why - because it is easier. This code will always be branched to via | |
1792 | a BX instruction and since the compiler magically generates the address | |
1793 | of the function the linker has no opportunity to ensure that the | |
1794 | bottom bit is set. Thus the processor will be in ARM mode when it | |
1795 | reaches this code. So we duplicate the ARM trampoline code and add | |
1796 | a switch into Thumb mode as well. */ | |
1797 | #define THUMB_TRAMPOLINE_TEMPLATE(FILE) \ | |
1798 | { \ | |
1799 | fprintf (FILE, "\t.code 32\n"); \ | |
1800 | fprintf (FILE, ".Ltrampoline_start:\n"); \ | |
1801 | asm_fprintf (FILE, "\tldr\t%r, [%r, #8]\n", \ | |
1802 | STATIC_CHAIN_REGNUM, PC_REGNUM); \ | |
1803 | asm_fprintf (FILE, "\tldr\t%r, [%r, #8]\n", \ | |
1804 | IP_REGNUM, PC_REGNUM); \ | |
1805 | asm_fprintf (FILE, "\torr\t%r, %r, #1\n", \ | |
1806 | IP_REGNUM, IP_REGNUM); \ | |
1807 | asm_fprintf (FILE, "\tbx\t%r\n", IP_REGNUM); \ | |
1808 | fprintf (FILE, "\t.word\t0\n"); \ | |
1809 | fprintf (FILE, "\t.word\t0\n"); \ | |
1810 | fprintf (FILE, "\t.code 16\n"); \ | |
35d965d5 RS |
1811 | } |
1812 | ||
d5b7b3ae RE |
1813 | #define TRAMPOLINE_TEMPLATE(FILE) \ |
1814 | if (TARGET_ARM) \ | |
1815 | ARM_TRAMPOLINE_TEMPLATE (FILE) \ | |
1816 | else \ | |
1817 | THUMB_TRAMPOLINE_TEMPLATE (FILE) | |
1818 | ||
35d965d5 | 1819 | /* Length in units of the trampoline for entering a nested function. */ |
d5b7b3ae | 1820 | #define TRAMPOLINE_SIZE (TARGET_ARM ? 16 : 24) |
35d965d5 RS |
1821 | |
1822 | /* Alignment required for a trampoline in units. */ | |
1823 | #define TRAMPOLINE_ALIGN 4 | |
1824 | ||
1825 | /* Emit RTL insns to initialize the variable parts of a trampoline. | |
1826 | FNADDR is an RTX for the address of the function's pure code. | |
1827 | CXT is an RTX for the static chain value for the function. */ | |
d5b7b3ae RE |
1828 | #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ |
1829 | { \ | |
1830 | emit_move_insn \ | |
1831 | (gen_rtx_MEM (SImode, plus_constant (TRAMP, TARGET_ARM ? 8 : 16)), CXT); \ | |
1832 | emit_move_insn \ | |
1833 | (gen_rtx_MEM (SImode, plus_constant (TRAMP, TARGET_ARM ? 12 : 20)), FNADDR); \ | |
35d965d5 RS |
1834 | } |
1835 | ||
35d965d5 RS |
1836 | \f |
1837 | /* Addressing modes, and classification of registers for them. */ | |
35d965d5 | 1838 | #define HAVE_POST_INCREMENT 1 |
d5b7b3ae RE |
1839 | #define HAVE_PRE_INCREMENT TARGET_ARM |
1840 | #define HAVE_POST_DECREMENT TARGET_ARM | |
1841 | #define HAVE_PRE_DECREMENT TARGET_ARM | |
35d965d5 RS |
1842 | |
1843 | /* Macros to check register numbers against specific register classes. */ | |
1844 | ||
1845 | /* These assume that REGNO is a hard or pseudo reg number. | |
1846 | They give nonzero only if REGNO is a hard reg of the suitable class | |
1847 | or a pseudo reg currently allocated to a suitable hard reg. | |
1848 | Since they use reg_renumber, they are safe only once reg_renumber | |
d5b7b3ae RE |
1849 | has been allocated, which happens in local-alloc.c. */ |
1850 | #define TEST_REGNO(R, TEST, VALUE) \ | |
1851 | ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE)) | |
1852 | ||
1853 | /* On the ARM, don't allow the pc to be used. */ | |
f1008e52 RE |
1854 | #define ARM_REGNO_OK_FOR_BASE_P(REGNO) \ |
1855 | (TEST_REGNO (REGNO, <, PC_REGNUM) \ | |
1856 | || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \ | |
1857 | || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM)) | |
1858 | ||
1859 | #define THUMB_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \ | |
1860 | (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \ | |
1861 | || (GET_MODE_SIZE (MODE) >= 4 \ | |
1862 | && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM))) | |
1863 | ||
1864 | #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \ | |
1865 | (TARGET_THUMB \ | |
1866 | ? THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \ | |
1867 | : ARM_REGNO_OK_FOR_BASE_P (REGNO)) | |
1868 | ||
1869 | /* For ARM code, we don't care about the mode, but for Thumb, the index | |
1870 | must be suitable for use in a QImode load. */ | |
d5b7b3ae RE |
1871 | #define REGNO_OK_FOR_INDEX_P(REGNO) \ |
1872 | REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode) | |
35d965d5 RS |
1873 | |
1874 | /* Maximum number of registers that can appear in a valid memory address. | |
ff9940b0 | 1875 | Shifts in addresses can't be by a register. */ |
ff9940b0 | 1876 | #define MAX_REGS_PER_ADDRESS 2 |
35d965d5 RS |
1877 | |
1878 | /* Recognize any constant value that is a valid address. */ | |
1879 | /* XXX We can address any constant, eventually... */ | |
11c1a207 RE |
1880 | |
1881 | #ifdef AOF_ASSEMBLER | |
1882 | ||
1883 | #define CONSTANT_ADDRESS_P(X) \ | |
d5b7b3ae | 1884 | (GET_CODE (X) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (X)) |
11c1a207 RE |
1885 | |
1886 | #else | |
35d965d5 | 1887 | |
008cf58a RE |
1888 | #define CONSTANT_ADDRESS_P(X) \ |
1889 | (GET_CODE (X) == SYMBOL_REF \ | |
1890 | && (CONSTANT_POOL_ADDRESS_P (X) \ | |
d5b7b3ae | 1891 | || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X)))) |
35d965d5 | 1892 | |
11c1a207 RE |
1893 | #endif /* AOF_ASSEMBLER */ |
1894 | ||
35d965d5 RS |
1895 | /* Nonzero if the constant value X is a legitimate general operand. |
1896 | It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. | |
1897 | ||
1898 | On the ARM, allow any integer (invalid ones are removed later by insn | |
1899 | patterns), nice doubles and symbol_refs which refer to the function's | |
d5b7b3ae | 1900 | constant pool XXX. |
82e9d970 PB |
1901 | |
1902 | When generating pic allow anything. */ | |
d5b7b3ae RE |
1903 | #define ARM_LEGITIMATE_CONSTANT_P(X) (flag_pic || ! label_mentioned_p (X)) |
1904 | ||
1905 | #define THUMB_LEGITIMATE_CONSTANT_P(X) \ | |
1906 | ( GET_CODE (X) == CONST_INT \ | |
1907 | || GET_CODE (X) == CONST_DOUBLE \ | |
1908 | || CONSTANT_ADDRESS_P (X)) | |
1909 | ||
1910 | #define LEGITIMATE_CONSTANT_P(X) \ | |
1911 | (TARGET_ARM ? ARM_LEGITIMATE_CONSTANT_P (X) : THUMB_LEGITIMATE_CONSTANT_P (X)) | |
1912 | ||
c27ba912 DM |
1913 | /* Special characters prefixed to function names |
1914 | in order to encode attribute like information. | |
1915 | Note, '@' and '*' have already been taken. */ | |
1916 | #define SHORT_CALL_FLAG_CHAR '^' | |
1917 | #define LONG_CALL_FLAG_CHAR '#' | |
1918 | ||
1919 | #define ENCODED_SHORT_CALL_ATTR_P(SYMBOL_NAME) \ | |
1920 | (*(SYMBOL_NAME) == SHORT_CALL_FLAG_CHAR) | |
1921 | ||
1922 | #define ENCODED_LONG_CALL_ATTR_P(SYMBOL_NAME) \ | |
1923 | (*(SYMBOL_NAME) == LONG_CALL_FLAG_CHAR) | |
1924 | ||
1925 | #ifndef SUBTARGET_NAME_ENCODING_LENGTHS | |
1926 | #define SUBTARGET_NAME_ENCODING_LENGTHS | |
1927 | #endif | |
1928 | ||
1929 | /* This is a C fragement for the inside of a switch statement. | |
1930 | Each case label should return the number of characters to | |
1931 | be stripped from the start of a function's name, if that | |
1932 | name starts with the indicated character. */ | |
1933 | #define ARM_NAME_ENCODING_LENGTHS \ | |
1934 | case SHORT_CALL_FLAG_CHAR: return 1; \ | |
1935 | case LONG_CALL_FLAG_CHAR: return 1; \ | |
00fdafef | 1936 | case '*': return 1; \ |
c27ba912 DM |
1937 | SUBTARGET_NAME_ENCODING_LENGTHS |
1938 | ||
1939 | /* This has to be handled by a function because more than part of the | |
6d77b53e | 1940 | ARM backend uses function name prefixes to encode attributes. */ |
e5951263 | 1941 | #undef STRIP_NAME_ENCODING |
c27ba912 DM |
1942 | #define STRIP_NAME_ENCODING(VAR, SYMBOL_NAME) \ |
1943 | (VAR) = arm_strip_name_encoding (SYMBOL_NAME) | |
1944 | ||
1945 | /* This is how to output a reference to a user-level label named NAME. | |
1946 | `assemble_name' uses this. */ | |
e5951263 | 1947 | #undef ASM_OUTPUT_LABELREF |
c27ba912 DM |
1948 | #define ASM_OUTPUT_LABELREF(FILE, NAME) \ |
1949 | fprintf (FILE, "%s%s", USER_LABEL_PREFIX, arm_strip_name_encoding (NAME)) | |
1950 | ||
1951 | /* If we are referencing a function that is weak then encode a long call | |
1952 | flag in the function name, otherwise if the function is static or | |
1953 | or known to be defined in this file then encode a short call flag. | |
1954 | This macro is used inside the ENCODE_SECTION macro. */ | |
1955 | #define ARM_ENCODE_CALL_TYPE(decl) \ | |
1956 | if (TREE_CODE (decl) == FUNCTION_DECL) \ | |
1957 | { \ | |
1958 | if (DECL_WEAK (decl)) \ | |
1959 | arm_encode_call_attribute (decl, LONG_CALL_FLAG_CHAR); \ | |
1960 | else if (! TREE_PUBLIC (decl)) \ | |
1961 | arm_encode_call_attribute (decl, SHORT_CALL_FLAG_CHAR); \ | |
1962 | } \ | |
82e9d970 | 1963 | |
ff9940b0 RE |
1964 | /* Symbols in the text segment can be accessed without indirecting via the |
1965 | constant pool; it may take an extra binary operation, but this is still | |
008cf58a RE |
1966 | faster than indirecting via memory. Don't do this when not optimizing, |
1967 | since we won't be calculating al of the offsets necessary to do this | |
1968 | simplification. */ | |
11c1a207 RE |
1969 | /* This doesn't work with AOF syntax, since the string table may be in |
1970 | a different AREA. */ | |
1971 | #ifndef AOF_ASSEMBLER | |
ff9940b0 RE |
1972 | #define ENCODE_SECTION_INFO(decl) \ |
1973 | { \ | |
008cf58a | 1974 | if (optimize > 0 && TREE_CONSTANT (decl) \ |
ff9940b0 | 1975 | && (!flag_writable_strings || TREE_CODE (decl) != STRING_CST)) \ |
228b6a3f RS |
1976 | { \ |
1977 | rtx rtl = (TREE_CODE_CLASS (TREE_CODE (decl)) != 'd' \ | |
1978 | ? TREE_CST_RTL (decl) : DECL_RTL (decl)); \ | |
1979 | SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1; \ | |
1980 | } \ | |
c27ba912 DM |
1981 | ARM_ENCODE_CALL_TYPE (decl) \ |
1982 | } | |
1983 | #else | |
1984 | #define ENCODE_SECTION_INFO(decl) \ | |
1985 | { \ | |
1986 | ARM_ENCODE_CALL_TYPE (decl) \ | |
ff9940b0 | 1987 | } |
11c1a207 | 1988 | #endif |
7a801826 | 1989 | |
c27ba912 DM |
1990 | #define ARM_DECLARE_FUNCTION_SIZE(STREAM, NAME, DECL) \ |
1991 | arm_encode_call_attribute (DECL, SHORT_CALL_FLAG_CHAR) | |
1992 | ||
35d965d5 RS |
1993 | /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx |
1994 | and check its validity for a certain class. | |
1995 | We have two alternate definitions for each of them. | |
1996 | The usual definition accepts all pseudo regs; the other rejects | |
1997 | them unless they have been allocated suitable hard regs. | |
1998 | The symbol REG_OK_STRICT causes the latter definition to be used. */ | |
1999 | #ifndef REG_OK_STRICT | |
ff9940b0 | 2000 | |
f1008e52 RE |
2001 | #define ARM_REG_OK_FOR_BASE_P(X) \ |
2002 | (REGNO (X) <= LAST_ARM_REGNUM \ | |
2003 | || REGNO (X) >= FIRST_PSEUDO_REGISTER \ | |
2004 | || REGNO (X) == FRAME_POINTER_REGNUM \ | |
2005 | || REGNO (X) == ARG_POINTER_REGNUM) | |
ff9940b0 | 2006 | |
f1008e52 RE |
2007 | #define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \ |
2008 | (REGNO (X) <= LAST_LO_REGNUM \ | |
2009 | || REGNO (X) >= FIRST_PSEUDO_REGISTER \ | |
2010 | || (GET_MODE_SIZE (MODE) >= 4 \ | |
2011 | && (REGNO (X) == STACK_POINTER_REGNUM \ | |
2012 | || (X) == hard_frame_pointer_rtx \ | |
2013 | || (X) == arg_pointer_rtx))) | |
ff9940b0 | 2014 | |
d5b7b3ae | 2015 | #else /* REG_OK_STRICT */ |
ff9940b0 | 2016 | |
f1008e52 RE |
2017 | #define ARM_REG_OK_FOR_BASE_P(X) \ |
2018 | ARM_REGNO_OK_FOR_BASE_P (REGNO (X)) | |
ff9940b0 | 2019 | |
f1008e52 RE |
2020 | #define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \ |
2021 | THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE) | |
ff9940b0 | 2022 | |
d5b7b3ae | 2023 | #endif /* REG_OK_STRICT */ |
f1008e52 RE |
2024 | |
2025 | /* Now define some helpers in terms of the above. */ | |
2026 | ||
2027 | #define REG_MODE_OK_FOR_BASE_P(X, MODE) \ | |
2028 | (TARGET_THUMB \ | |
2029 | ? THUMB_REG_MODE_OK_FOR_BASE_P (X, MODE) \ | |
2030 | : ARM_REG_OK_FOR_BASE_P (X)) | |
2031 | ||
2032 | #define ARM_REG_OK_FOR_INDEX_P(X) ARM_REG_OK_FOR_BASE_P (X) | |
2033 | ||
2034 | /* For Thumb, a valid index register is anything that can be used in | |
2035 | a byte load instruction. */ | |
2036 | #define THUMB_REG_OK_FOR_INDEX_P(X) THUMB_REG_MODE_OK_FOR_BASE_P (X, QImode) | |
2037 | ||
2038 | /* Nonzero if X is a hard reg that can be used as an index | |
2039 | or if it is a pseudo reg. On the Thumb, the stack pointer | |
2040 | is not suitable. */ | |
2041 | #define REG_OK_FOR_INDEX_P(X) \ | |
2042 | (TARGET_THUMB \ | |
2043 | ? THUMB_REG_OK_FOR_INDEX_P (X) \ | |
2044 | : ARM_REG_OK_FOR_INDEX_P (X)) | |
2045 | ||
35d965d5 RS |
2046 | \f |
2047 | /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression | |
2048 | that is a valid memory address for an instruction. | |
2049 | The MODE argument is the machine mode for the MEM expression | |
2050 | that wants to use this address. | |
2051 | ||
d5b7b3ae RE |
2052 | The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */ |
2053 | ||
2054 | /* --------------------------------arm version----------------------------- */ | |
f1008e52 RE |
2055 | #define ARM_BASE_REGISTER_RTX_P(X) \ |
2056 | (GET_CODE (X) == REG && ARM_REG_OK_FOR_BASE_P (X)) | |
35d965d5 | 2057 | |
f1008e52 RE |
2058 | #define ARM_INDEX_REGISTER_RTX_P(X) \ |
2059 | (GET_CODE (X) == REG && ARM_REG_OK_FOR_INDEX_P (X)) | |
35d965d5 RS |
2060 | |
2061 | /* A C statement (sans semicolon) to jump to LABEL for legitimate index RTXs | |
2062 | used by the macro GO_IF_LEGITIMATE_ADDRESS. Floating point indices can | |
2063 | only be small constants. */ | |
f1008e52 RE |
2064 | #define ARM_GO_IF_LEGITIMATE_INDEX(MODE, BASE_REGNO, INDEX, LABEL) \ |
2065 | do \ | |
35d965d5 | 2066 | { \ |
f1008e52 RE |
2067 | HOST_WIDE_INT range; \ |
2068 | enum rtx_code code = GET_CODE (INDEX); \ | |
35d965d5 | 2069 | \ |
f1008e52 RE |
2070 | if (TARGET_HARD_FLOAT && GET_MODE_CLASS (MODE) == MODE_FLOAT) \ |
2071 | { \ | |
2072 | if (code == CONST_INT && INTVAL (INDEX) < 1024 \ | |
2073 | && INTVAL (INDEX) > -1024 \ | |
2074 | && (INTVAL (INDEX) & 3) == 0) \ | |
2075 | goto LABEL; \ | |
2076 | } \ | |
2077 | else \ | |
2078 | { \ | |
2079 | if (ARM_INDEX_REGISTER_RTX_P (INDEX) \ | |
2080 | && GET_MODE_SIZE (MODE) <= 4) \ | |
2081 | goto LABEL; \ | |
2082 | if (GET_MODE_SIZE (MODE) <= 4 && code == MULT \ | |
2083 | && (! arm_arch4 || (MODE) != HImode)) \ | |
2084 | { \ | |
2085 | rtx xiop0 = XEXP (INDEX, 0); \ | |
2086 | rtx xiop1 = XEXP (INDEX, 1); \ | |
2087 | if (ARM_INDEX_REGISTER_RTX_P (xiop0) \ | |
2088 | && power_of_two_operand (xiop1, SImode)) \ | |
2089 | goto LABEL; \ | |
2090 | if (ARM_INDEX_REGISTER_RTX_P (xiop1) \ | |
2091 | && power_of_two_operand (xiop0, SImode)) \ | |
2092 | goto LABEL; \ | |
2093 | } \ | |
2094 | if (GET_MODE_SIZE (MODE) <= 4 \ | |
2095 | && (code == LSHIFTRT || code == ASHIFTRT \ | |
2096 | || code == ASHIFT || code == ROTATERT) \ | |
2097 | && (! arm_arch4 || (MODE) != HImode)) \ | |
2098 | { \ | |
2099 | rtx op = XEXP (INDEX, 1); \ | |
2100 | if (ARM_INDEX_REGISTER_RTX_P (XEXP (INDEX, 0)) \ | |
2101 | && GET_CODE (op) == CONST_INT && INTVAL (op) > 0 \ | |
2102 | && INTVAL (op) <= 31) \ | |
2103 | goto LABEL; \ | |
2104 | } \ | |
2105 | /* NASTY: Since this limits the addressing of unsigned \ | |
2106 | byte loads. */ \ | |
2107 | range = ((MODE) == HImode || (MODE) == QImode) \ | |
2108 | ? (arm_arch4 ? 256 : 4095) : 4096; \ | |
2109 | if (code == CONST_INT && INTVAL (INDEX) < range \ | |
2110 | && INTVAL (INDEX) > -range) \ | |
2111 | goto LABEL; \ | |
2112 | } \ | |
35d965d5 | 2113 | } \ |
f1008e52 RE |
2114 | while (0) |
2115 | ||
2116 | /* Jump to LABEL if X is a valid address RTX. This must take | |
2117 | REG_OK_STRICT into account when deciding about valid registers. | |
2118 | ||
2119 | Allow REG, REG+REG, REG+INDEX, INDEX+REG, REG-INDEX, and non | |
2120 | floating SYMBOL_REF to the constant pool. Allow REG-only and | |
2121 | AUTINC-REG if handling TImode or HImode. Other symbol refs must be | |
2122 | forced though a static cell to ensure addressability. */ | |
d19fb8e3 NC |
2123 | #define ARM_GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \ |
2124 | { \ | |
2125 | if (ARM_BASE_REGISTER_RTX_P (X)) \ | |
2126 | goto LABEL; \ | |
2127 | else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \ | |
2128 | && GET_CODE (XEXP (X, 0)) == REG \ | |
2129 | && ARM_REG_OK_FOR_BASE_P (XEXP (X, 0))) \ | |
2130 | goto LABEL; \ | |
2131 | else if (GET_MODE_SIZE (MODE) >= 4 && reload_completed \ | |
2132 | && (GET_CODE (X) == LABEL_REF \ | |
2133 | || (GET_CODE (X) == CONST \ | |
2134 | && GET_CODE (XEXP ((X), 0)) == PLUS \ | |
2135 | && GET_CODE (XEXP (XEXP ((X), 0), 0)) == LABEL_REF \ | |
2136 | && GET_CODE (XEXP (XEXP ((X), 0), 1)) == CONST_INT)))\ | |
2137 | goto LABEL; \ | |
2138 | else if ((MODE) == TImode) \ | |
2139 | ; \ | |
2140 | else if ((MODE) == DImode || (TARGET_SOFT_FLOAT && (MODE) == DFmode)) \ | |
2141 | { \ | |
2142 | if (GET_CODE (X) == PLUS && ARM_BASE_REGISTER_RTX_P (XEXP (X, 0)) \ | |
2143 | && GET_CODE (XEXP (X, 1)) == CONST_INT) \ | |
2144 | { \ | |
2145 | HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \ | |
2146 | if (val == 4 || val == -4 || val == -8) \ | |
2147 | goto LABEL; \ | |
2148 | } \ | |
2149 | } \ | |
2150 | else if (GET_CODE (X) == PLUS) \ | |
2151 | { \ | |
2152 | rtx xop0 = XEXP (X, 0); \ | |
2153 | rtx xop1 = XEXP (X, 1); \ | |
2154 | \ | |
2155 | if (ARM_BASE_REGISTER_RTX_P (xop0)) \ | |
2156 | ARM_GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop0), xop1, LABEL); \ | |
2157 | else if (ARM_BASE_REGISTER_RTX_P (xop1)) \ | |
2158 | ARM_GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop1), xop0, LABEL); \ | |
2159 | } \ | |
2160 | /* Reload currently can't handle MINUS, so disable this for now */ \ | |
2161 | /* else if (GET_CODE (X) == MINUS) \ | |
2162 | { \ | |
2163 | rtx xop0 = XEXP (X,0); \ | |
2164 | rtx xop1 = XEXP (X,1); \ | |
2165 | \ | |
2166 | if (ARM_BASE_REGISTER_RTX_P (xop0)) \ | |
2167 | ARM_GO_IF_LEGITIMATE_INDEX (MODE, -1, xop1, LABEL); \ | |
2168 | } */ \ | |
2169 | else if (GET_MODE_CLASS (MODE) != MODE_FLOAT \ | |
2170 | && GET_CODE (X) == SYMBOL_REF \ | |
2171 | && CONSTANT_POOL_ADDRESS_P (X) \ | |
2172 | && ! (flag_pic \ | |
2173 | && symbol_mentioned_p (get_pool_constant (X)))) \ | |
2174 | goto LABEL; \ | |
2175 | else if ((GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_DEC) \ | |
2176 | && (GET_MODE_SIZE (MODE) <= 4) \ | |
2177 | && GET_CODE (XEXP (X, 0)) == REG \ | |
2178 | && ARM_REG_OK_FOR_BASE_P (XEXP (X, 0))) \ | |
2179 | goto LABEL; \ | |
35d965d5 | 2180 | } |
d5b7b3ae RE |
2181 | |
2182 | /* ---------------------thumb version----------------------------------*/ | |
f1008e52 | 2183 | #define THUMB_LEGITIMATE_OFFSET(MODE, VAL) \ |
d5b7b3ae RE |
2184 | (GET_MODE_SIZE (MODE) == 1 ? ((unsigned HOST_WIDE_INT) (VAL) < 32) \ |
2185 | : GET_MODE_SIZE (MODE) == 2 ? ((unsigned HOST_WIDE_INT) (VAL) < 64 \ | |
2186 | && ((VAL) & 1) == 0) \ | |
2187 | : ((VAL) >= 0 && ((VAL) + GET_MODE_SIZE (MODE)) <= 128 \ | |
2188 | && ((VAL) & 3) == 0)) | |
2189 | ||
2190 | /* The AP may be eliminated to either the SP or the FP, so we use the | |
2191 | least common denominator, e.g. SImode, and offsets from 0 to 64. */ | |
2192 | ||
2193 | /* ??? Verify whether the above is the right approach. */ | |
2194 | ||
2195 | /* ??? Also, the FP may be eliminated to the SP, so perhaps that | |
2196 | needs special handling also. */ | |
2197 | ||
2198 | /* ??? Look at how the mips16 port solves this problem. It probably uses | |
2199 | better ways to solve some of these problems. */ | |
2200 | ||
2201 | /* Although it is not incorrect, we don't accept QImode and HImode | |
f1008e52 RE |
2202 | addresses based on the frame pointer or arg pointer until the |
2203 | reload pass starts. This is so that eliminating such addresses | |
2204 | into stack based ones won't produce impossible code. */ | |
d5b7b3ae RE |
2205 | #define THUMB_GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \ |
2206 | { \ | |
2207 | /* ??? Not clear if this is right. Experiment. */ \ | |
2208 | if (GET_MODE_SIZE (MODE) < 4 \ | |
2209 | && ! (reload_in_progress || reload_completed) \ | |
2210 | && ( reg_mentioned_p (frame_pointer_rtx, X) \ | |
2211 | || reg_mentioned_p (arg_pointer_rtx, X) \ | |
2212 | || reg_mentioned_p (virtual_incoming_args_rtx, X) \ | |
2213 | || reg_mentioned_p (virtual_outgoing_args_rtx, X) \ | |
2214 | || reg_mentioned_p (virtual_stack_dynamic_rtx, X) \ | |
2215 | || reg_mentioned_p (virtual_stack_vars_rtx, X))) \ | |
2216 | ; \ | |
2217 | /* Accept any base register. SP only in SImode or larger. */ \ | |
f1008e52 RE |
2218 | else if (GET_CODE (X) == REG \ |
2219 | && THUMB_REG_MODE_OK_FOR_BASE_P (X, MODE)) \ | |
d5b7b3ae RE |
2220 | goto WIN; \ |
2221 | /* This is PC relative data before MACHINE_DEPENDENT_REORG runs. */ \ | |
2222 | else if (GET_MODE_SIZE (MODE) >= 4 && CONSTANT_P (X) \ | |
2223 | && CONSTANT_POOL_ADDRESS_P (X) && ! flag_pic) \ | |
2224 | goto WIN; \ | |
2225 | /* This is PC relative data after MACHINE_DEPENDENT_REORG runs. */ \ | |
2226 | else if (GET_MODE_SIZE (MODE) >= 4 && reload_completed \ | |
2227 | && (GET_CODE (X) == LABEL_REF \ | |
2228 | || (GET_CODE (X) == CONST \ | |
2229 | && GET_CODE (XEXP (X, 0)) == PLUS \ | |
2230 | && GET_CODE (XEXP (XEXP (X, 0), 0)) == LABEL_REF \ | |
2231 | && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT))) \ | |
2232 | goto WIN; \ | |
2233 | /* Post-inc indexing only supported for SImode and larger. */ \ | |
2234 | else if (GET_CODE (X) == POST_INC && GET_MODE_SIZE (MODE) >= 4 \ | |
2235 | && GET_CODE (XEXP (X, 0)) == REG \ | |
f1008e52 | 2236 | && THUMB_REG_OK_FOR_INDEX_P (XEXP (X, 0))) \ |
d5b7b3ae RE |
2237 | goto WIN; \ |
2238 | else if (GET_CODE (X) == PLUS) \ | |
2239 | { \ | |
2240 | /* REG+REG address can be any two index registers. */ \ | |
2241 | /* We disallow FRAME+REG addressing since we know that FRAME \ | |
2242 | will be replaced with STACK, and SP relative addressing only \ | |
2243 | permits SP+OFFSET. */ \ | |
2244 | if (GET_MODE_SIZE (MODE) <= 4 \ | |
2245 | && GET_CODE (XEXP (X, 0)) == REG \ | |
2246 | && GET_CODE (XEXP (X, 1)) == REG \ | |
2247 | && XEXP (X, 0) != frame_pointer_rtx \ | |
2248 | && XEXP (X, 1) != frame_pointer_rtx \ | |
2249 | && XEXP (X, 0) != virtual_stack_vars_rtx \ | |
2250 | && XEXP (X, 1) != virtual_stack_vars_rtx \ | |
f1008e52 RE |
2251 | && THUMB_REG_OK_FOR_INDEX_P (XEXP (X, 0)) \ |
2252 | && THUMB_REG_OK_FOR_INDEX_P (XEXP (X, 1))) \ | |
d5b7b3ae RE |
2253 | goto WIN; \ |
2254 | /* REG+const has 5-7 bit offset for non-SP registers. */ \ | |
2255 | else if (GET_CODE (XEXP (X, 0)) == REG \ | |
f1008e52 | 2256 | && (THUMB_REG_OK_FOR_INDEX_P (XEXP (X, 0)) \ |
d5b7b3ae RE |
2257 | || XEXP (X, 0) == arg_pointer_rtx) \ |
2258 | && GET_CODE (XEXP (X, 1)) == CONST_INT \ | |
f1008e52 | 2259 | && THUMB_LEGITIMATE_OFFSET (MODE, INTVAL (XEXP (X, 1)))) \ |
d5b7b3ae RE |
2260 | goto WIN; \ |
2261 | /* REG+const has 10 bit offset for SP, but only SImode and \ | |
2262 | larger is supported. */ \ | |
2263 | /* ??? Should probably check for DI/DFmode overflow here \ | |
2264 | just like GO_IF_LEGITIMATE_OFFSET does. */ \ | |
2265 | else if (GET_CODE (XEXP (X, 0)) == REG \ | |
2266 | && REGNO (XEXP (X, 0)) == STACK_POINTER_REGNUM \ | |
2267 | && GET_MODE_SIZE (MODE) >= 4 \ | |
2268 | && GET_CODE (XEXP (X, 1)) == CONST_INT \ | |
2269 | && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (X, 1)) \ | |
2270 | + GET_MODE_SIZE (MODE)) <= 1024 \ | |
2271 | && (INTVAL (XEXP (X, 1)) & 3) == 0) \ | |
2272 | goto WIN; \ | |
2273 | else if (GET_CODE (XEXP (X, 0)) == REG \ | |
2274 | && REGNO (XEXP (X, 0)) == FRAME_POINTER_REGNUM \ | |
2275 | && GET_MODE_SIZE (MODE) >= 4 \ | |
2276 | && GET_CODE (XEXP (X, 1)) == CONST_INT \ | |
2277 | && (INTVAL (XEXP (X, 1)) & 3) == 0) \ | |
2278 | goto WIN; \ | |
2279 | } \ | |
2280 | else if (GET_MODE_CLASS (MODE) != MODE_FLOAT \ | |
2281 | && GET_CODE (X) == SYMBOL_REF \ | |
2282 | && CONSTANT_POOL_ADDRESS_P (X) \ | |
2283 | && ! (flag_pic \ | |
2284 | && symbol_mentioned_p (get_pool_constant (X)))) \ | |
2285 | goto WIN; \ | |
2286 | } | |
2287 | ||
2288 | /* ------------------------------------------------------------------- */ | |
2289 | #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \ | |
2290 | if (TARGET_ARM) \ | |
2291 | ARM_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN) \ | |
2292 | else /* if (TARGET_THUMB) */ \ | |
2293 | THUMB_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN) | |
2294 | /* ------------------------------------------------------------------- */ | |
35d965d5 RS |
2295 | \f |
2296 | /* Try machine-dependent ways of modifying an illegitimate address | |
2297 | to be legitimate. If we find one, return the new, valid address. | |
2298 | This macro is used in only one place: `memory_address' in explow.c. | |
2299 | ||
2300 | OLDX is the address as it was before break_out_memory_refs was called. | |
2301 | In some cases it is useful to look at this to decide what needs to be done. | |
2302 | ||
2303 | MODE and WIN are passed so that this macro can use | |
2304 | GO_IF_LEGITIMATE_ADDRESS. | |
2305 | ||
2306 | It is always safe for this macro to do nothing. It exists to recognize | |
2307 | opportunities to optimize the output. | |
2308 | ||
2309 | On the ARM, try to convert [REG, #BIGCONST] | |
2310 | into ADD BASE, REG, #UPPERCONST and [BASE, #VALIDCONST], | |
2311 | where VALIDCONST == 0 in case of TImode. */ | |
d5b7b3ae | 2312 | #define ARM_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \ |
3967692c RE |
2313 | { \ |
2314 | if (GET_CODE (X) == PLUS) \ | |
2315 | { \ | |
2316 | rtx xop0 = XEXP (X, 0); \ | |
2317 | rtx xop1 = XEXP (X, 1); \ | |
2318 | \ | |
11c1a207 | 2319 | if (CONSTANT_P (xop0) && ! symbol_mentioned_p (xop0)) \ |
3967692c | 2320 | xop0 = force_reg (SImode, xop0); \ |
11c1a207 | 2321 | if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1)) \ |
3967692c | 2322 | xop1 = force_reg (SImode, xop1); \ |
f1008e52 RE |
2323 | if (ARM_BASE_REGISTER_RTX_P (xop0) \ |
2324 | && GET_CODE (xop1) == CONST_INT) \ | |
3967692c RE |
2325 | { \ |
2326 | HOST_WIDE_INT n, low_n; \ | |
2327 | rtx base_reg, val; \ | |
2328 | n = INTVAL (xop1); \ | |
2329 | \ | |
11c1a207 | 2330 | if (MODE == DImode || (TARGET_SOFT_FLOAT && MODE == DFmode)) \ |
3967692c RE |
2331 | { \ |
2332 | low_n = n & 0x0f; \ | |
2333 | n &= ~0x0f; \ | |
2334 | if (low_n > 4) \ | |
2335 | { \ | |
2336 | n += 16; \ | |
2337 | low_n -= 16; \ | |
2338 | } \ | |
2339 | } \ | |
2340 | else \ | |
2341 | { \ | |
2342 | low_n = ((MODE) == TImode ? 0 \ | |
2343 | : n >= 0 ? (n & 0xfff) : -((-n) & 0xfff)); \ | |
2344 | n -= low_n; \ | |
2345 | } \ | |
2346 | base_reg = gen_reg_rtx (SImode); \ | |
43cffd11 RE |
2347 | val = force_operand (gen_rtx_PLUS (SImode, xop0, \ |
2348 | GEN_INT (n)), NULL_RTX); \ | |
3967692c RE |
2349 | emit_move_insn (base_reg, val); \ |
2350 | (X) = (low_n == 0 ? base_reg \ | |
43cffd11 | 2351 | : gen_rtx_PLUS (SImode, base_reg, GEN_INT (low_n))); \ |
3967692c RE |
2352 | } \ |
2353 | else if (xop0 != XEXP (X, 0) || xop1 != XEXP (x, 1)) \ | |
43cffd11 | 2354 | (X) = gen_rtx_PLUS (SImode, xop0, xop1); \ |
3967692c RE |
2355 | } \ |
2356 | else if (GET_CODE (X) == MINUS) \ | |
2357 | { \ | |
2358 | rtx xop0 = XEXP (X, 0); \ | |
2359 | rtx xop1 = XEXP (X, 1); \ | |
2360 | \ | |
2361 | if (CONSTANT_P (xop0)) \ | |
2362 | xop0 = force_reg (SImode, xop0); \ | |
11c1a207 | 2363 | if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1)) \ |
3967692c RE |
2364 | xop1 = force_reg (SImode, xop1); \ |
2365 | if (xop0 != XEXP (X, 0) || xop1 != XEXP (X, 1)) \ | |
43cffd11 | 2366 | (X) = gen_rtx_MINUS (SImode, xop0, xop1); \ |
3967692c | 2367 | } \ |
7a801826 RE |
2368 | if (flag_pic) \ |
2369 | (X) = legitimize_pic_address (OLDX, MODE, NULL_RTX); \ | |
3967692c RE |
2370 | if (memory_address_p (MODE, X)) \ |
2371 | goto WIN; \ | |
35d965d5 RS |
2372 | } |
2373 | ||
d5b7b3ae RE |
2374 | #define THUMB_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \ |
2375 | if (flag_pic) \ | |
2376 | (X) = legitimize_pic_address (OLDX, MODE, NULL_RTX); | |
2377 | ||
2378 | #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \ | |
2379 | if (TARGET_ARM) \ | |
2380 | ARM_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN) \ | |
2381 | else \ | |
2382 | THUMB_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN) | |
2383 | ||
35d965d5 RS |
2384 | /* Go to LABEL if ADDR (a legitimate address expression) |
2385 | has an effect that depends on the machine mode it is used for. */ | |
d5b7b3ae | 2386 | #define ARM_GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \ |
35d965d5 | 2387 | { \ |
d5b7b3ae RE |
2388 | if ( GET_CODE (ADDR) == PRE_DEC || GET_CODE (ADDR) == POST_DEC \ |
2389 | || GET_CODE (ADDR) == PRE_INC || GET_CODE (ADDR) == POST_INC) \ | |
35d965d5 RS |
2390 | goto LABEL; \ |
2391 | } | |
d5b7b3ae RE |
2392 | |
2393 | /* Nothing helpful to do for the Thumb */ | |
2394 | #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \ | |
2395 | if (TARGET_ARM) \ | |
2396 | ARM_GO_IF_MODE_DEPENDENT_ADDRESS (ADDR, LABEL) | |
35d965d5 | 2397 | \f |
d5b7b3ae | 2398 | |
35d965d5 RS |
2399 | /* Specify the machine mode that this machine uses |
2400 | for the index in the tablejump instruction. */ | |
d5b7b3ae | 2401 | #define CASE_VECTOR_MODE Pmode |
35d965d5 | 2402 | |
18543a22 ILT |
2403 | /* Define as C expression which evaluates to nonzero if the tablejump |
2404 | instruction expects the table to contain offsets from the address of the | |
2405 | table. | |
2406 | Do not define this if the table should contain absolute addresses. */ | |
2407 | /* #define CASE_VECTOR_PC_RELATIVE 1 */ | |
35d965d5 RS |
2408 | |
2409 | /* Specify the tree operation to be used to convert reals to integers. */ | |
2410 | #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR | |
2411 | ||
2412 | /* This is the kind of divide that is easiest to do in the general case. */ | |
2413 | #define EASY_DIV_EXPR TRUNC_DIV_EXPR | |
2414 | ||
ff9940b0 RE |
2415 | /* signed 'char' is most compatible, but RISC OS wants it unsigned. |
2416 | unsigned is probably best, but may break some code. */ | |
2417 | #ifndef DEFAULT_SIGNED_CHAR | |
3967692c | 2418 | #define DEFAULT_SIGNED_CHAR 0 |
35d965d5 RS |
2419 | #endif |
2420 | ||
2421 | /* Don't cse the address of the function being compiled. */ | |
2422 | #define NO_RECURSIVE_FUNCTION_CSE 1 | |
2423 | ||
2424 | /* Max number of bytes we can move from memory to memory | |
d17ce9af TG |
2425 | in one reasonably fast instruction. */ |
2426 | #define MOVE_MAX 4 | |
35d965d5 | 2427 | |
d19fb8e3 NC |
2428 | #undef MOVE_RATIO |
2429 | #define MOVE_RATIO (arm_is_xscale ? 4 : 2) | |
2430 | ||
ff9940b0 RE |
2431 | /* Define if operations between registers always perform the operation |
2432 | on the full register even if a narrower mode is specified. */ | |
2433 | #define WORD_REGISTER_OPERATIONS | |
2434 | ||
2435 | /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD | |
2436 | will either zero-extend or sign-extend. The value of this macro should | |
2437 | be the code that says which one of the two operations is implicitly | |
2438 | done, NIL if none. */ | |
9c872872 | 2439 | #define LOAD_EXTEND_OP(MODE) \ |
d5b7b3ae RE |
2440 | (TARGET_THUMB ? ZERO_EXTEND : \ |
2441 | ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \ | |
2442 | : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : NIL))) | |
ff9940b0 | 2443 | |
35d965d5 RS |
2444 | /* Define this if zero-extension is slow (more than one real instruction). |
2445 | On the ARM, it is more than one instruction only if not fetching from | |
2446 | memory. */ | |
2447 | /* #define SLOW_ZERO_EXTEND */ | |
2448 | ||
2449 | /* Nonzero if access to memory by bytes is slow and undesirable. */ | |
2450 | #define SLOW_BYTE_ACCESS 0 | |
2451 | ||
d5b7b3ae RE |
2452 | #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1 |
2453 | ||
35d965d5 RS |
2454 | /* Immediate shift counts are truncated by the output routines (or was it |
2455 | the assembler?). Shift counts in a register are truncated by ARM. Note | |
2456 | that the native compiler puts too large (> 32) immediate shift counts | |
2457 | into a register and shifts by the register, letting the ARM decide what | |
2458 | to do instead of doing that itself. */ | |
ff9940b0 RE |
2459 | /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that |
2460 | code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y). | |
2461 | On the arm, Y in a register is used modulo 256 for the shift. Only for | |
2462 | rotates is modulo 32 used. */ | |
2463 | /* #define SHIFT_COUNT_TRUNCATED 1 */ | |
35d965d5 | 2464 | |
35d965d5 | 2465 | /* All integers have the same format so truncation is easy. */ |
d5b7b3ae | 2466 | #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 |
35d965d5 RS |
2467 | |
2468 | /* Calling from registers is a massive pain. */ | |
2469 | #define NO_FUNCTION_CSE 1 | |
2470 | ||
2471 | /* Chars and shorts should be passed as ints. */ | |
2472 | #define PROMOTE_PROTOTYPES 1 | |
2473 | ||
35d965d5 RS |
2474 | /* The machine modes of pointers and functions */ |
2475 | #define Pmode SImode | |
2476 | #define FUNCTION_MODE Pmode | |
2477 | ||
d5b7b3ae RE |
2478 | #define ARM_FRAME_RTX(X) \ |
2479 | ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \ | |
3967692c RE |
2480 | || (X) == arg_pointer_rtx) |
2481 | ||
62b10bbc | 2482 | #define DEFAULT_RTX_COSTS(X, CODE, OUTER_CODE) \ |
d5b7b3ae | 2483 | return arm_rtx_costs (X, CODE, OUTER_CODE); |
ff9940b0 RE |
2484 | |
2485 | /* Moves to and from memory are quite expensive */ | |
d5b7b3ae RE |
2486 | #define MEMORY_MOVE_COST(M, CLASS, IN) \ |
2487 | (TARGET_ARM ? 10 : \ | |
2488 | ((GET_MODE_SIZE (M) < 4 ? 8 : 2 * GET_MODE_SIZE (M)) \ | |
2489 | * (CLASS == LO_REGS ? 1 : 2))) | |
2490 | ||
3967692c | 2491 | /* All address computations that can be done are free, but rtx cost returns |
ddd5a7c1 | 2492 | the same for practically all of them. So we weight the different types |
3967692c RE |
2493 | of address here in the order (most pref first): |
2494 | PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */ | |
d5b7b3ae | 2495 | #define ARM_ADDRESS_COST(X) \ |
3967692c RE |
2496 | (10 - ((GET_CODE (X) == MEM || GET_CODE (X) == LABEL_REF \ |
2497 | || GET_CODE (X) == SYMBOL_REF) \ | |
2498 | ? 0 \ | |
2499 | : ((GET_CODE (X) == PRE_INC || GET_CODE (X) == PRE_DEC \ | |
2500 | || GET_CODE (X) == POST_INC || GET_CODE (X) == POST_DEC) \ | |
2501 | ? 10 \ | |
2502 | : (((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS) \ | |
2503 | ? 6 + (GET_CODE (XEXP (X, 1)) == CONST_INT ? 2 \ | |
2504 | : ((GET_RTX_CLASS (GET_CODE (XEXP (X, 0))) == '2' \ | |
2505 | || GET_RTX_CLASS (GET_CODE (XEXP (X, 0))) == 'c' \ | |
2506 | || GET_RTX_CLASS (GET_CODE (XEXP (X, 1))) == '2' \ | |
2507 | || GET_RTX_CLASS (GET_CODE (XEXP (X, 1))) == 'c') \ | |
2508 | ? 1 : 0)) \ | |
2509 | : 4))))) | |
d5b7b3ae RE |
2510 | |
2511 | #define THUMB_ADDRESS_COST(X) \ | |
2512 | ((GET_CODE (X) == REG \ | |
2513 | || (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == REG \ | |
2514 | && GET_CODE (XEXP (X, 1)) == CONST_INT)) \ | |
2515 | ? 1 : 2) | |
2516 | ||
2517 | #define ADDRESS_COST(X) \ | |
2518 | (TARGET_ARM ? ARM_ADDRESS_COST (X) : THUMB_ADDRESS_COST (X)) | |
2519 | ||
ff9940b0 RE |
2520 | /* Try to generate sequences that don't involve branches, we can then use |
2521 | conditional instructions */ | |
d5b7b3ae RE |
2522 | #define BRANCH_COST \ |
2523 | (TARGET_ARM ? 4 : (optimize > 1 ? 1 : 0)) | |
7a801826 RE |
2524 | |
2525 | /* A C statement to update the variable COST based on the relationship | |
2526 | between INSN that is dependent on DEP through dependence LINK. */ | |
6cfc7210 NC |
2527 | #define ADJUST_COST(INSN, LINK, DEP, COST) \ |
2528 | (COST) = arm_adjust_cost (INSN, LINK, DEP, COST) | |
7a801826 RE |
2529 | \f |
2530 | /* Position Independent Code. */ | |
2531 | /* We decide which register to use based on the compilation options and | |
2532 | the assembler in use; this is more general than the APCS restriction of | |
2533 | using sb (r9) all the time. */ | |
2534 | extern int arm_pic_register; | |
2535 | ||
ed0e6530 PB |
2536 | /* Used when parsing command line option -mpic-register=. */ |
2537 | extern const char * arm_pic_register_string; | |
2538 | ||
7a801826 RE |
2539 | /* The register number of the register used to address a table of static |
2540 | data addresses in memory. */ | |
2541 | #define PIC_OFFSET_TABLE_REGNUM arm_pic_register | |
2542 | ||
2543 | #define FINALIZE_PIC arm_finalize_pic () | |
2544 | ||
f5a1b0d2 NC |
2545 | /* We can't directly access anything that contains a symbol, |
2546 | nor can we indirect via the constant pool. */ | |
82e9d970 PB |
2547 | #define LEGITIMATE_PIC_OPERAND_P(X) \ |
2548 | ( ! symbol_mentioned_p (X) \ | |
2549 | && ! label_mentioned_p (X) \ | |
2550 | && (! CONSTANT_POOL_ADDRESS_P (X) \ | |
c27ba912 DM |
2551 | || ( ! symbol_mentioned_p (get_pool_constant (X)) \ |
2552 | && ! label_mentioned_p (get_pool_constant (X))))) | |
13bd191d PB |
2553 | |
2554 | /* We need to know when we are making a constant pool; this determines | |
2555 | whether data needs to be in the GOT or can be referenced via a GOT | |
2556 | offset. */ | |
2557 | extern int making_const_table; | |
82e9d970 PB |
2558 | \f |
2559 | /* If defined, a C expression whose value is nonzero if IDENTIFIER | |
2560 | with arguments ARGS is a valid machine specific attribute for TYPE. | |
2561 | The attributes in ATTRIBUTES have previously been assigned to TYPE. */ | |
2562 | #define VALID_MACHINE_TYPE_ATTRIBUTE(TYPE, ATTRIBUTES, NAME, ARGS) \ | |
2563 | (arm_valid_type_attribute_p (TYPE, ATTRIBUTES, NAME, ARGS)) | |
2564 | ||
2565 | /* If defined, a C expression whose value is zero if the attributes on | |
2566 | TYPE1 and TYPE2 are incompatible, one if they are compatible, and | |
2567 | two if they are nearly compatible (which causes a warning to be | |
2568 | generated). */ | |
2569 | #define COMP_TYPE_ATTRIBUTES(TYPE1, TYPE2) \ | |
2570 | (arm_comp_type_attributes (TYPE1, TYPE2)) | |
c27ba912 DM |
2571 | |
2572 | /* If defined, a C statement that assigns default attributes to newly | |
2573 | defined TYPE. */ | |
2574 | #define SET_DEFAULT_TYPE_ATTRIBUTES(TYPE) \ | |
2575 | arm_set_default_type_attributes (TYPE) | |
2576 | ||
2577 | /* Handle pragmas for compatibility with Intel's compilers. */ | |
8b97c5f8 ZW |
2578 | #define REGISTER_TARGET_PRAGMAS(PFILE) do { \ |
2579 | cpp_register_pragma (PFILE, 0, "long_calls", arm_pr_long_calls); \ | |
2580 | cpp_register_pragma (PFILE, 0, "no_long_calls", arm_pr_no_long_calls); \ | |
2581 | cpp_register_pragma (PFILE, 0, "long_calls_off", arm_pr_long_calls_off); \ | |
2582 | } while (0) | |
2583 | ||
ff9940b0 RE |
2584 | /* Condition code information. */ |
2585 | /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, | |
2586 | return the mode to be used for the comparison. | |
ddd5a7c1 | 2587 | CCFPEmode should be used with floating inequalities, |
ff9940b0 | 2588 | CCFPmode should be used with floating equalities. |
ddd5a7c1 | 2589 | CC_NOOVmode should be used with SImode integer equalities. |
69fcc21d | 2590 | CC_Zmode should be used if only the Z flag is set correctly |
ff9940b0 RE |
2591 | CCmode should be used otherwise. */ |
2592 | ||
d5b7b3ae RE |
2593 | #define EXTRA_CC_MODES \ |
2594 | CC(CC_NOOVmode, "CC_NOOV") \ | |
2595 | CC(CC_Zmode, "CC_Z") \ | |
2596 | CC(CC_SWPmode, "CC_SWP") \ | |
2597 | CC(CCFPmode, "CCFP") \ | |
2598 | CC(CCFPEmode, "CCFPE") \ | |
2599 | CC(CC_DNEmode, "CC_DNE") \ | |
2600 | CC(CC_DEQmode, "CC_DEQ") \ | |
2601 | CC(CC_DLEmode, "CC_DLE") \ | |
2602 | CC(CC_DLTmode, "CC_DLT") \ | |
2603 | CC(CC_DGEmode, "CC_DGE") \ | |
2604 | CC(CC_DGTmode, "CC_DGT") \ | |
2605 | CC(CC_DLEUmode, "CC_DLEU") \ | |
2606 | CC(CC_DLTUmode, "CC_DLTU") \ | |
2607 | CC(CC_DGEUmode, "CC_DGEU") \ | |
2608 | CC(CC_DGTUmode, "CC_DGTU") \ | |
2609 | CC(CC_Cmode, "CC_C") | |
2610 | ||
2611 | #define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y) | |
ff9940b0 | 2612 | |
008cf58a RE |
2613 | #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode) |
2614 | ||
62b10bbc NC |
2615 | #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \ |
2616 | do \ | |
2617 | { \ | |
2618 | if (GET_CODE (OP1) == CONST_INT \ | |
2619 | && ! (const_ok_for_arm (INTVAL (OP1)) \ | |
2620 | || (const_ok_for_arm (- INTVAL (OP1))))) \ | |
2621 | { \ | |
2622 | rtx const_op = OP1; \ | |
2623 | CODE = arm_canonicalize_comparison ((CODE), &const_op); \ | |
2624 | OP1 = const_op; \ | |
2625 | } \ | |
2626 | } \ | |
2627 | while (0) | |
62dd06ea | 2628 | |
ff9940b0 RE |
2629 | #define STORE_FLAG_VALUE 1 |
2630 | ||
35d965d5 | 2631 | \f |
35d965d5 | 2632 | |
11c1a207 RE |
2633 | /* Gcc puts the pool in the wrong place for ARM, since we can only |
2634 | load addresses a limited distance around the pc. We do some | |
2635 | special munging to move the constant pool values to the correct | |
2636 | point in the code. */ | |
d5b7b3ae RE |
2637 | #define MACHINE_DEPENDENT_REORG(INSN) \ |
2638 | arm_reorg (INSN); \ | |
2639 | ||
2640 | #undef ASM_APP_OFF | |
2641 | #define ASM_APP_OFF (TARGET_THUMB ? "\t.code\t16\n" : "") | |
35d965d5 | 2642 | |
35d965d5 | 2643 | /* Output an internal label definition. */ |
b355a481 | 2644 | #ifndef ASM_OUTPUT_INTERNAL_LABEL |
62b10bbc NC |
2645 | #define ASM_OUTPUT_INTERNAL_LABEL(STREAM, PREFIX, NUM) \ |
2646 | do \ | |
2647 | { \ | |
2a5307b1 | 2648 | char * s = (char *) alloca (40 + strlen (PREFIX)); \ |
62b10bbc NC |
2649 | \ |
2650 | if (arm_ccfsm_state == 3 && arm_target_label == (NUM) \ | |
2651 | && !strcmp (PREFIX, "L")) \ | |
18543a22 | 2652 | { \ |
62b10bbc | 2653 | arm_ccfsm_state = 0; \ |
18543a22 ILT |
2654 | arm_target_insn = NULL; \ |
2655 | } \ | |
62b10bbc NC |
2656 | ASM_GENERATE_INTERNAL_LABEL (s, (PREFIX), (NUM)); \ |
2657 | ASM_OUTPUT_LABEL (STREAM, s); \ | |
2658 | } \ | |
2659 | while (0) | |
b355a481 | 2660 | #endif |
2a5307b1 | 2661 | |
35d965d5 | 2662 | /* Output a push or a pop instruction (only used when profiling). */ |
d5b7b3ae RE |
2663 | #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \ |
2664 | if (TARGET_ARM) \ | |
2665 | asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", \ | |
2666 | STACK_POINTER_REGNUM, REGNO); \ | |
2667 | else \ | |
2668 | asm_fprintf (STREAM, "\tpush {%r}\n", REGNO) | |
2669 | ||
2670 | ||
2671 | #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \ | |
2672 | if (TARGET_ARM) \ | |
2673 | asm_fprintf (STREAM, "\tldmfd\t%r!,{%r}\n", \ | |
2674 | STACK_POINTER_REGNUM, REGNO); \ | |
2675 | else \ | |
2676 | asm_fprintf (STREAM, "\tpop {%r}\n", REGNO) | |
2677 | ||
2678 | /* This is how to output a label which precedes a jumptable. Since | |
2679 | Thumb instructions are 2 bytes, we may need explicit alignment here. */ | |
2680 | #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, JUMPTABLE) \ | |
2681 | do \ | |
2682 | { \ | |
2683 | if (TARGET_THUMB) \ | |
2684 | ASM_OUTPUT_ALIGN (FILE, 2); \ | |
2685 | ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM); \ | |
2686 | } \ | |
2687 | while (0) | |
35d965d5 | 2688 | |
6cfc7210 NC |
2689 | #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \ |
2690 | do \ | |
2691 | { \ | |
d5b7b3ae RE |
2692 | if (TARGET_THUMB) \ |
2693 | { \ | |
2694 | if (is_called_in_ARM_mode (DECL)) \ | |
2695 | fprintf (STREAM, "\t.code 32\n") ; \ | |
2696 | else \ | |
2697 | fprintf (STREAM, "\t.thumb_func\n") ; \ | |
2698 | } \ | |
6cfc7210 | 2699 | if (TARGET_POKE_FUNCTION_NAME) \ |
6354dc9b | 2700 | arm_poke_function_name (STREAM, (char *) NAME); \ |
6cfc7210 NC |
2701 | } \ |
2702 | while (0) | |
35d965d5 | 2703 | |
d5b7b3ae RE |
2704 | /* For aliases of functions we use .thumb_set instead. */ |
2705 | #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \ | |
2706 | do \ | |
2707 | { \ | |
2708 | char * LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \ | |
2709 | char * LABEL2 = IDENTIFIER_POINTER (DECL2); \ | |
2710 | \ | |
2711 | if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \ | |
2712 | { \ | |
2713 | fprintf (FILE, "\t.thumb_set "); \ | |
2714 | assemble_name (FILE, LABEL1); \ | |
2715 | fprintf (FILE, ","); \ | |
2716 | assemble_name (FILE, LABEL2); \ | |
2717 | fprintf (FILE, "\n"); \ | |
2718 | } \ | |
2719 | else \ | |
2720 | ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \ | |
2721 | } \ | |
2722 | while (0) | |
2723 | ||
35d965d5 RS |
2724 | /* Target characters. */ |
2725 | #define TARGET_BELL 007 | |
2726 | #define TARGET_BS 010 | |
2727 | #define TARGET_TAB 011 | |
2728 | #define TARGET_NEWLINE 012 | |
2729 | #define TARGET_VT 013 | |
2730 | #define TARGET_FF 014 | |
2731 | #define TARGET_CR 015 | |
2732 | \f | |
35d965d5 RS |
2733 | /* Only perform branch elimination (by making instructions conditional) if |
2734 | we're optimising. Otherwise it's of no use anyway. */ | |
d5b7b3ae RE |
2735 | #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \ |
2736 | if (TARGET_ARM && optimize) \ | |
2737 | arm_final_prescan_insn (INSN); \ | |
2738 | else if (TARGET_THUMB) \ | |
2739 | thumb_final_prescan_insn (INSN) | |
35d965d5 | 2740 | |
7bc7696c | 2741 | #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ |
d5b7b3ae RE |
2742 | (CODE == '@' || CODE == '|' \ |
2743 | || (TARGET_ARM && (CODE == '?')) \ | |
2744 | || (TARGET_THUMB && (CODE == '_'))) | |
6cfc7210 | 2745 | |
7bc7696c | 2746 | /* Output an operand of an instruction. */ |
35d965d5 | 2747 | #define PRINT_OPERAND(STREAM, X, CODE) \ |
7bc7696c RE |
2748 | arm_print_operand (STREAM, X, CODE) |
2749 | ||
e5951263 NC |
2750 | /* Create an [unsigned] host sized integer declaration that |
2751 | avoids compiler warnings. */ | |
2752 | #ifdef __STDC__ | |
2753 | #define HOST_INT(x) ((signed HOST_WIDE_INT) x##UL) | |
2754 | #define HOST_UINT(x) ((unsigned HOST_WIDE_INT) x##UL) | |
2755 | #else | |
2756 | #define HOST_INT(x) ((HOST_WIDE_INT) x) | |
2757 | #define HOST_UINT(x) ((unsigned HOST_WIDE_INT) x) | |
2758 | #endif | |
2759 | ||
2760 | #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \ | |
2761 | (HOST_BITS_PER_WIDE_INT <= 32 ? (x) \ | |
2762 | : (((x) & HOST_UINT (0xffffffff)) | \ | |
2763 | (((x) & HOST_UINT (0x80000000)) \ | |
2764 | ? ((~ HOST_INT (0)) \ | |
2765 | & ~ HOST_UINT(0xffffffff)) \ | |
7bc7696c | 2766 | : 0)))) |
35d965d5 RS |
2767 | |
2768 | /* Output the address of an operand. */ | |
d5b7b3ae RE |
2769 | #define ARM_PRINT_OPERAND_ADDRESS(STREAM, X) \ |
2770 | { \ | |
2771 | int is_minus = GET_CODE (X) == MINUS; \ | |
2772 | \ | |
2773 | if (GET_CODE (X) == REG) \ | |
2774 | asm_fprintf (STREAM, "[%r, #0]", REGNO (X)); \ | |
2775 | else if (GET_CODE (X) == PLUS || is_minus) \ | |
2776 | { \ | |
2777 | rtx base = XEXP (X, 0); \ | |
2778 | rtx index = XEXP (X, 1); \ | |
2779 | HOST_WIDE_INT offset = 0; \ | |
2780 | if (GET_CODE (base) != REG) \ | |
2781 | { \ | |
2782 | /* Ensure that BASE is a register */ \ | |
2783 | /* (one of them must be). */ \ | |
2784 | rtx temp = base; \ | |
2785 | base = index; \ | |
2786 | index = temp; \ | |
2787 | } \ | |
2788 | switch (GET_CODE (index)) \ | |
2789 | { \ | |
2790 | case CONST_INT: \ | |
2791 | offset = INTVAL (index); \ | |
2792 | if (is_minus) \ | |
2793 | offset = -offset; \ | |
2794 | asm_fprintf (STREAM, "[%r, #%d]", \ | |
2795 | REGNO (base), offset); \ | |
2796 | break; \ | |
2797 | \ | |
2798 | case REG: \ | |
2799 | asm_fprintf (STREAM, "[%r, %s%r]", \ | |
2800 | REGNO (base), is_minus ? "-" : "", \ | |
2801 | REGNO (index)); \ | |
2802 | break; \ | |
2803 | \ | |
2804 | case MULT: \ | |
2805 | case ASHIFTRT: \ | |
2806 | case LSHIFTRT: \ | |
2807 | case ASHIFT: \ | |
2808 | case ROTATERT: \ | |
2809 | { \ | |
2810 | asm_fprintf (STREAM, "[%r, %s%r", \ | |
2811 | REGNO (base), is_minus ? "-" : "", \ | |
2812 | REGNO (XEXP (index, 0))); \ | |
2813 | arm_print_operand (STREAM, index, 'S'); \ | |
2814 | fputs ("]", STREAM); \ | |
2815 | break; \ | |
2816 | } \ | |
2817 | \ | |
2818 | default: \ | |
2819 | abort(); \ | |
2820 | } \ | |
2821 | } \ | |
2822 | else if ( GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC\ | |
2823 | || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC)\ | |
2824 | { \ | |
2825 | extern int output_memory_reference_mode; \ | |
2826 | \ | |
2827 | if (GET_CODE (XEXP (X, 0)) != REG) \ | |
2828 | abort (); \ | |
2829 | \ | |
2830 | if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \ | |
2831 | asm_fprintf (STREAM, "[%r, #%s%d]!", \ | |
2832 | REGNO (XEXP (X, 0)), \ | |
2833 | GET_CODE (X) == PRE_DEC ? "-" : "", \ | |
2834 | GET_MODE_SIZE (output_memory_reference_mode));\ | |
2835 | else \ | |
2836 | asm_fprintf (STREAM, "[%r], #%s%d", \ | |
2837 | REGNO (XEXP (X, 0)), \ | |
2838 | GET_CODE (X) == POST_DEC ? "-" : "", \ | |
2839 | GET_MODE_SIZE (output_memory_reference_mode));\ | |
2840 | } \ | |
2841 | else output_addr_const (STREAM, X); \ | |
35d965d5 | 2842 | } |
62dd06ea | 2843 | |
d5b7b3ae RE |
2844 | #define THUMB_PRINT_OPERAND_ADDRESS(STREAM, X) \ |
2845 | { \ | |
2846 | if (GET_CODE (X) == REG) \ | |
2847 | asm_fprintf (STREAM, "[%r]", REGNO (X)); \ | |
2848 | else if (GET_CODE (X) == POST_INC) \ | |
2849 | asm_fprintf (STREAM, "%r!", REGNO (XEXP (X, 0))); \ | |
2850 | else if (GET_CODE (X) == PLUS) \ | |
2851 | { \ | |
2852 | if (GET_CODE (XEXP (X, 1)) == CONST_INT) \ | |
2853 | asm_fprintf (STREAM, "[%r, #%d]", \ | |
2854 | REGNO (XEXP (X, 0)), \ | |
2855 | (int) INTVAL (XEXP (X, 1))); \ | |
2856 | else \ | |
2857 | asm_fprintf (STREAM, "[%r, %r]", \ | |
2858 | REGNO (XEXP (X, 0)), \ | |
2859 | REGNO (XEXP (X, 1))); \ | |
2860 | } \ | |
2861 | else \ | |
2862 | output_addr_const (STREAM, X); \ | |
2863 | } | |
2864 | ||
2865 | #define PRINT_OPERAND_ADDRESS(STREAM, X) \ | |
2866 | if (TARGET_ARM) \ | |
2867 | ARM_PRINT_OPERAND_ADDRESS (STREAM, X) \ | |
2868 | else \ | |
2869 | THUMB_PRINT_OPERAND_ADDRESS (STREAM, X) | |
2870 | ||
7a801826 | 2871 | /* Handles PIC addr specially */ |
d5b7b3ae | 2872 | #define OUTPUT_INT_ADDR_CONST(STREAM, X) \ |
7a801826 | 2873 | { \ |
13bd191d | 2874 | if (flag_pic && GET_CODE (X) == CONST && is_pic (X)) \ |
7a801826 | 2875 | { \ |
13bd191d PB |
2876 | output_addr_const (STREAM, XEXP (XEXP (XEXP (X, 0), 0), 0)); \ |
2877 | fputs (" - (", STREAM); \ | |
2878 | output_addr_const (STREAM, XEXP (XEXP (XEXP (X, 0), 1), 0)); \ | |
2879 | fputs (")", STREAM); \ | |
7a801826 | 2880 | } \ |
d5b7b3ae RE |
2881 | else \ |
2882 | output_addr_const (STREAM, X); \ | |
687f77a1 NC |
2883 | \ |
2884 | /* Mark symbols as position independent. We only do this in the \ | |
2885 | .text segment, not in the .data segment. */ \ | |
ed0e6530 | 2886 | if (NEED_GOT_RELOC && flag_pic && making_const_table && \ |
687f77a1 NC |
2887 | (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == LABEL_REF)) \ |
2888 | { \ | |
2889 | if (GET_CODE (X) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (X)) \ | |
2890 | fprintf (STREAM, "(GOTOFF)"); \ | |
2891 | else if (GET_CODE (X) == LABEL_REF) \ | |
2892 | fprintf (STREAM, "(GOTOFF)"); \ | |
2893 | else \ | |
2894 | fprintf (STREAM, "(GOT)"); \ | |
2895 | } \ | |
7a801826 RE |
2896 | } |
2897 | ||
62dd06ea RE |
2898 | /* Output code to add DELTA to the first argument, and then jump to FUNCTION. |
2899 | Used for C++ multiple inheritance. */ | |
62b10bbc NC |
2900 | #define ASM_OUTPUT_MI_THUNK(FILE, THUNK_FNDECL, DELTA, FUNCTION) \ |
2901 | do \ | |
2902 | { \ | |
2903 | int mi_delta = (DELTA); \ | |
6354dc9b | 2904 | const char * mi_op = mi_delta < 0 ? "sub" : "add"; \ |
62b10bbc NC |
2905 | int shift = 0; \ |
2906 | int this_regno = (aggregate_value_p (TREE_TYPE (TREE_TYPE (FUNCTION))) \ | |
2907 | ? 1 : 0); \ | |
b1801c02 NC |
2908 | if (mi_delta < 0) \ |
2909 | mi_delta = - mi_delta; \ | |
62b10bbc NC |
2910 | while (mi_delta != 0) \ |
2911 | { \ | |
b1801c02 | 2912 | if ((mi_delta & (3 << shift)) == 0) \ |
62b10bbc NC |
2913 | shift += 2; \ |
2914 | else \ | |
2915 | { \ | |
dd18ae56 NC |
2916 | asm_fprintf (FILE, "\t%s\t%r, %r, #%d\n", \ |
2917 | mi_op, this_regno, this_regno, \ | |
6cfc7210 | 2918 | mi_delta & (0xff << shift)); \ |
62b10bbc NC |
2919 | mi_delta &= ~(0xff << shift); \ |
2920 | shift += 8; \ | |
2921 | } \ | |
2922 | } \ | |
2923 | fputs ("\tb\t", FILE); \ | |
2924 | assemble_name (FILE, XSTR (XEXP (DECL_RTL (FUNCTION), 0), 0)); \ | |
dd18ae56 | 2925 | if (NEED_PLT_RELOC) \ |
62b10bbc NC |
2926 | fputs ("(PLT)", FILE); \ |
2927 | fputc ('\n', FILE); \ | |
2928 | } \ | |
2929 | while (0) | |
39950dff | 2930 | |
6a5d7526 MS |
2931 | /* A C expression whose value is RTL representing the value of the return |
2932 | address for the frame COUNT steps up from the current frame. */ | |
2933 | ||
d5b7b3ae RE |
2934 | #define RETURN_ADDR_RTX(COUNT, FRAME) \ |
2935 | arm_return_addr (COUNT, FRAME) | |
2936 | ||
2937 | /* Mask of the bits in the PC that contain the real return address | |
2938 | when running in 26-bit mode. */ | |
2939 | #define RETURN_ADDR_MASK26 (0x03fffffc) | |
6a5d7526 | 2940 | |
2c849145 JM |
2941 | /* Pick up the return address upon entry to a procedure. Used for |
2942 | dwarf2 unwind information. This also enables the table driven | |
2943 | mechanism. */ | |
2c849145 JM |
2944 | #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM) |
2945 | #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM) | |
2946 | ||
39950dff MS |
2947 | /* Used to mask out junk bits from the return address, such as |
2948 | processor state, interrupt status, condition codes and the like. */ | |
2949 | #define MASK_RETURN_ADDR \ | |
2950 | /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \ | |
2951 | in 26 bit mode, the condition codes must be masked out of the \ | |
2952 | return address. This does not apply to ARM6 and later processors \ | |
2953 | when running in 32 bit mode. */ \ | |
d5b7b3ae RE |
2954 | ((!TARGET_APCS_32) ? (GEN_INT (RETURN_ADDR_MASK26)) \ |
2955 | : (GEN_INT ((unsigned long)0xffffffff))) | |
2956 | ||
2957 | \f | |
2958 | /* Define the codes that are matched by predicates in arm.c */ | |
2959 | #define PREDICATE_CODES \ | |
2960 | {"s_register_operand", {SUBREG, REG}}, \ | |
2961 | {"f_register_operand", {SUBREG, REG}}, \ | |
2962 | {"arm_add_operand", {SUBREG, REG, CONST_INT}}, \ | |
2963 | {"fpu_add_operand", {SUBREG, REG, CONST_DOUBLE}}, \ | |
2964 | {"fpu_rhs_operand", {SUBREG, REG, CONST_DOUBLE}}, \ | |
2965 | {"arm_rhs_operand", {SUBREG, REG, CONST_INT}}, \ | |
2966 | {"arm_not_operand", {SUBREG, REG, CONST_INT}}, \ | |
2967 | {"reg_or_int_operand", {SUBREG, REG, CONST_INT}}, \ | |
2968 | {"index_operand", {SUBREG, REG, CONST_INT}}, \ | |
2969 | {"thumb_cmp_operand", {SUBREG, REG, CONST_INT}}, \ | |
2970 | {"offsettable_memory_operand", {MEM}}, \ | |
2971 | {"bad_signed_byte_operand", {MEM}}, \ | |
2972 | {"alignable_memory_operand", {MEM}}, \ | |
2973 | {"shiftable_operator", {PLUS, MINUS, AND, IOR, XOR}}, \ | |
2974 | {"minmax_operator", {SMIN, SMAX, UMIN, UMAX}}, \ | |
2975 | {"shift_operator", {ASHIFT, ASHIFTRT, LSHIFTRT, ROTATERT, MULT}}, \ | |
2976 | {"di_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE, MEM}}, \ | |
2977 | {"nonimmediate_di_operand", {SUBREG, REG, MEM}}, \ | |
2978 | {"soft_df_operand", {SUBREG, REG, CONST_DOUBLE, MEM}}, \ | |
2979 | {"nonimmediate_soft_df_operand", {SUBREG, REG, MEM}}, \ | |
2980 | {"load_multiple_operation", {PARALLEL}}, \ | |
2981 | {"store_multiple_operation", {PARALLEL}}, \ | |
2982 | {"equality_operator", {EQ, NE}}, \ | |
e45b72c4 RE |
2983 | {"arm_comparison_operator", {EQ, NE, LE, LT, GE, GT, GEU, GTU, LEU, \ |
2984 | LTU, UNORDERED, ORDERED, UNLT, UNLE, \ | |
2985 | UNGE, UNGT}}, \ | |
d5b7b3ae RE |
2986 | {"arm_rhsm_operand", {SUBREG, REG, CONST_INT, MEM}}, \ |
2987 | {"const_shift_operand", {CONST_INT}}, \ | |
2988 | {"multi_register_push", {PARALLEL}}, \ | |
2989 | {"cc_register", {REG}}, \ | |
2990 | {"logical_binary_operator", {AND, IOR, XOR}}, \ | |
2991 | {"dominant_cc_register", {REG}}, | |
71791e16 | 2992 | |
ad027eae RE |
2993 | /* Define this if you have special predicates that know special things |
2994 | about modes. Genrecog will warn about certain forms of | |
2995 | match_operand without a mode; if the operand predicate is listed in | |
2996 | SPECIAL_MODE_PREDICATES, the warning will be suppressed. */ | |
2997 | #define SPECIAL_MODE_PREDICATES \ | |
2998 | "cc_register", "dominant_cc_register", | |
2999 | ||
d19fb8e3 NC |
3000 | enum arm_builtins |
3001 | { | |
3002 | ARM_BUILTIN_CLZ, | |
3003 | ARM_BUILTIN_PREFETCH, | |
3004 | ARM_BUILTIN_MAX | |
3005 | }; | |
3006 | ||
3007 | #define MD_INIT_BUILTINS \ | |
3008 | do \ | |
3009 | { \ | |
3010 | arm_init_builtins (); \ | |
3011 | } \ | |
3012 | while (0) | |
3013 | ||
3014 | #define MD_EXPAND_BUILTIN(EXP, TARGET, SUBTARGET, MODE, IGNORE) \ | |
3015 | arm_expand_builtin ((EXP), (TARGET), (SUBTARGET), (MODE), (IGNORE)) | |
b355a481 | 3016 | #endif /* __ARM_H__ */ |