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f5a1b0d2 | 1 | /* Definitions of target machine for GNU compiler, for ARM. |
cf011243 | 2 | Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, |
18f0fe6b | 3 | 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012 |
bf98ec6c | 4 | Free Software Foundation, Inc. |
35d965d5 | 5 | Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl) |
8b109b37 | 6 | and Martin Simmons (@harleqn.co.uk). |
949d79eb | 7 | More major hacks by Richard Earnshaw (rearnsha@arm.com) |
6cfc7210 NC |
8 | Minor hacks by Nick Clifton (nickc@cygnus.com) |
9 | ||
4f448245 | 10 | This file is part of GCC. |
35d965d5 | 11 | |
4f448245 NC |
12 | GCC is free software; you can redistribute it and/or modify it |
13 | under the terms of the GNU General Public License as published | |
2f83c7d6 | 14 | by the Free Software Foundation; either version 3, or (at your |
4f448245 | 15 | option) any later version. |
35d965d5 | 16 | |
4f448245 NC |
17 | GCC is distributed in the hope that it will be useful, but WITHOUT |
18 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
19 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
20 | License for more details. | |
35d965d5 | 21 | |
4f448245 | 22 | You should have received a copy of the GNU General Public License |
2f83c7d6 NC |
23 | along with GCC; see the file COPYING3. If not see |
24 | <http://www.gnu.org/licenses/>. */ | |
35d965d5 | 25 | |
88657302 RH |
26 | #ifndef GCC_ARM_H |
27 | #define GCC_ARM_H | |
b355a481 | 28 | |
46107b99 RE |
29 | /* We can't use enum machine_mode inside a generator file because it |
30 | hasn't been created yet; we shouldn't be using any code that | |
31 | needs the real definition though, so this ought to be safe. */ | |
32 | #ifdef GENERATOR_FILE | |
33 | #define MACHMODE int | |
34 | #else | |
35 | #include "insn-modes.h" | |
36 | #define MACHMODE enum machine_mode | |
37 | #endif | |
38 | ||
9403b7f7 RS |
39 | #include "config/vxworks-dummy.h" |
40 | ||
35fd3193 | 41 | /* The architecture define. */ |
78011587 PB |
42 | extern char arm_arch_name[]; |
43 | ||
e6471be6 NB |
44 | /* Target CPU builtins. */ |
45 | #define TARGET_CPU_CPP_BUILTINS() \ | |
46 | do \ | |
47 | { \ | |
c884924f JG |
48 | if (TARGET_DSP_MULTIPLY) \ |
49 | builtin_define ("__ARM_FEATURE_DSP"); \ | |
5d248b41 JG |
50 | if (unaligned_access) \ |
51 | builtin_define ("__ARM_FEATURE_UNALIGNED"); \ | |
9b66ebb1 PB |
52 | /* Define __arm__ even when in thumb mode, for \ |
53 | consistency with armcc. */ \ | |
54 | builtin_define ("__arm__"); \ | |
61f0ccff | 55 | builtin_define ("__APCS_32__"); \ |
9b66ebb1 | 56 | if (TARGET_THUMB) \ |
e6471be6 | 57 | builtin_define ("__thumb__"); \ |
5b3e6663 PB |
58 | if (TARGET_THUMB2) \ |
59 | builtin_define ("__thumb2__"); \ | |
e6471be6 NB |
60 | \ |
61 | if (TARGET_BIG_END) \ | |
62 | { \ | |
63 | builtin_define ("__ARMEB__"); \ | |
64 | if (TARGET_THUMB) \ | |
65 | builtin_define ("__THUMBEB__"); \ | |
66 | if (TARGET_LITTLE_WORDS) \ | |
67 | builtin_define ("__ARMWEL__"); \ | |
68 | } \ | |
69 | else \ | |
70 | { \ | |
71 | builtin_define ("__ARMEL__"); \ | |
72 | if (TARGET_THUMB) \ | |
73 | builtin_define ("__THUMBEL__"); \ | |
74 | } \ | |
75 | \ | |
e6471be6 NB |
76 | if (TARGET_SOFT_FLOAT) \ |
77 | builtin_define ("__SOFTFP__"); \ | |
78 | \ | |
9b66ebb1 | 79 | if (TARGET_VFP) \ |
b5b620a4 JT |
80 | builtin_define ("__VFP_FP__"); \ |
81 | \ | |
88f77cba JB |
82 | if (TARGET_NEON) \ |
83 | builtin_define ("__ARM_NEON__"); \ | |
84 | \ | |
e6471be6 NB |
85 | /* Add a define for interworking. \ |
86 | Needed when building libgcc.a. */ \ | |
2ad4dcf9 | 87 | if (arm_cpp_interwork) \ |
e6471be6 NB |
88 | builtin_define ("__THUMB_INTERWORK__"); \ |
89 | \ | |
90 | builtin_assert ("cpu=arm"); \ | |
91 | builtin_assert ("machine=arm"); \ | |
78011587 PB |
92 | \ |
93 | builtin_define (arm_arch_name); \ | |
94 | if (arm_arch_cirrus) \ | |
95 | builtin_define ("__MAVERICK__"); \ | |
96 | if (arm_arch_xscale) \ | |
97 | builtin_define ("__XSCALE__"); \ | |
98 | if (arm_arch_iwmmxt) \ | |
99 | builtin_define ("__IWMMXT__"); \ | |
4adf3e34 | 100 | if (TARGET_AAPCS_BASED) \ |
12ffc7d5 CLT |
101 | { \ |
102 | if (arm_pcs_default == ARM_PCS_AAPCS_VFP) \ | |
103 | builtin_define ("__ARM_PCS_VFP"); \ | |
104 | else if (arm_pcs_default == ARM_PCS_AAPCS) \ | |
105 | builtin_define ("__ARM_PCS"); \ | |
106 | builtin_define ("__ARM_EABI__"); \ | |
107 | } \ | |
572070ef PB |
108 | if (TARGET_IDIV) \ |
109 | builtin_define ("__ARM_ARCH_EXT_IDIV__"); \ | |
e6471be6 NB |
110 | } while (0) |
111 | ||
ad7be009 | 112 | #include "config/arm/arm-opts.h" |
9b66ebb1 | 113 | |
78011587 PB |
114 | enum target_cpus |
115 | { | |
d98a72fd RE |
116 | #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \ |
117 | TARGET_CPU_##IDENT, | |
78011587 PB |
118 | #include "arm-cores.def" |
119 | #undef ARM_CORE | |
120 | TARGET_CPU_generic | |
121 | }; | |
122 | ||
9b66ebb1 PB |
123 | /* The processor for which instructions should be scheduled. */ |
124 | extern enum processor_type arm_tune; | |
125 | ||
d5b7b3ae | 126 | typedef enum arm_cond_code |
89c7ca52 RE |
127 | { |
128 | ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC, | |
129 | ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV | |
d5b7b3ae RE |
130 | } |
131 | arm_cc; | |
6cfc7210 | 132 | |
d5b7b3ae | 133 | extern arm_cc arm_current_cc; |
ff9940b0 | 134 | |
d5b7b3ae | 135 | #define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1)) |
89c7ca52 | 136 | |
6cfc7210 NC |
137 | extern int arm_target_label; |
138 | extern int arm_ccfsm_state; | |
e2500fed | 139 | extern GTY(()) rtx arm_target_insn; |
d5b7b3ae | 140 | /* The label of the current constant pool. */ |
e2500fed | 141 | extern rtx pool_vector_label; |
d5b7b3ae | 142 | /* Set to 1 when a return insn is output, this means that the epilogue |
d6b4baa4 | 143 | is not needed. */ |
d5b7b3ae | 144 | extern int return_used_this_function; |
b76c3c4b PB |
145 | /* Callback to output language specific object attributes. */ |
146 | extern void (*arm_lang_output_object_attributes_hook)(void); | |
35d965d5 | 147 | \f |
d6b4baa4 | 148 | /* Just in case configure has failed to define anything. */ |
7a801826 RE |
149 | #ifndef TARGET_CPU_DEFAULT |
150 | #define TARGET_CPU_DEFAULT TARGET_CPU_generic | |
151 | #endif | |
152 | ||
7a801826 | 153 | |
5742588d | 154 | #undef CPP_SPEC |
78011587 | 155 | #define CPP_SPEC "%(subtarget_cpp_spec) \ |
5e1b4d5a JM |
156 | %{mfloat-abi=soft:%{mfloat-abi=hard: \ |
157 | %e-mfloat-abi=soft and -mfloat-abi=hard may not be used together}} \ | |
e6471be6 NB |
158 | %{mbig-endian:%{mlittle-endian: \ |
159 | %e-mbig-endian and -mlittle-endian may not be used together}}" | |
7a801826 | 160 | |
be393ecf | 161 | #ifndef CC1_SPEC |
dfa08768 | 162 | #define CC1_SPEC "" |
be393ecf | 163 | #endif |
7a801826 RE |
164 | |
165 | /* This macro defines names of additional specifications to put in the specs | |
166 | that can be used in various specifications like CC1_SPEC. Its definition | |
167 | is an initializer with a subgrouping for each command option. | |
168 | ||
169 | Each subgrouping contains a string constant, that defines the | |
4f448245 | 170 | specification name, and a string constant that used by the GCC driver |
7a801826 RE |
171 | program. |
172 | ||
173 | Do not define this macro if it does not need to do anything. */ | |
174 | #define EXTRA_SPECS \ | |
38fc909b | 175 | { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \ |
54e73f88 | 176 | { "asm_cpu_spec", ASM_CPU_SPEC }, \ |
7a801826 RE |
177 | SUBTARGET_EXTRA_SPECS |
178 | ||
914a3b8c | 179 | #ifndef SUBTARGET_EXTRA_SPECS |
7a801826 | 180 | #define SUBTARGET_EXTRA_SPECS |
914a3b8c DM |
181 | #endif |
182 | ||
6cfc7210 | 183 | #ifndef SUBTARGET_CPP_SPEC |
38fc909b | 184 | #define SUBTARGET_CPP_SPEC "" |
6cfc7210 | 185 | #endif |
35d965d5 RS |
186 | \f |
187 | /* Run-time Target Specification. */ | |
9b66ebb1 | 188 | #define TARGET_SOFT_FLOAT (arm_float_abi == ARM_FLOAT_ABI_SOFT) |
72cdc543 PB |
189 | /* Use hardware floating point instructions. */ |
190 | #define TARGET_HARD_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT) | |
191 | /* Use hardware floating point calling convention. */ | |
192 | #define TARGET_HARD_FLOAT_ABI (arm_float_abi == ARM_FLOAT_ABI_HARD) | |
d79f3032 PB |
193 | #define TARGET_FPA (arm_fpu_desc->model == ARM_FP_MODEL_FPA) |
194 | #define TARGET_MAVERICK (arm_fpu_desc->model == ARM_FP_MODEL_MAVERICK) | |
195 | #define TARGET_VFP (arm_fpu_desc->model == ARM_FP_MODEL_VFP) | |
5a9335ef | 196 | #define TARGET_IWMMXT (arm_arch_iwmmxt) |
5b3e6663 PB |
197 | #define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_32BIT) |
198 | #define TARGET_IWMMXT_ABI (TARGET_32BIT && arm_abi == ARM_ABI_IWMMXT) | |
d5b7b3ae RE |
199 | #define TARGET_ARM (! TARGET_THUMB) |
200 | #define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */ | |
c54c7322 RS |
201 | #define TARGET_BACKTRACE (leaf_function_p () \ |
202 | ? TARGET_TPCS_LEAF_FRAME \ | |
203 | : TARGET_TPCS_FRAME) | |
fdd695fd | 204 | #define TARGET_LDRD (arm_arch5e && ARM_DOUBLEWORD_ALIGN) |
b6685939 PB |
205 | #define TARGET_AAPCS_BASED \ |
206 | (arm_abi != ARM_ABI_APCS && arm_abi != ARM_ABI_ATPCS) | |
3ada8e17 | 207 | |
d3585b76 DJ |
208 | #define TARGET_HARD_TP (target_thread_pointer == TP_CP15) |
209 | #define TARGET_SOFT_TP (target_thread_pointer == TP_SOFT) | |
ccdc2164 | 210 | #define TARGET_GNU2_TLS (target_tls_dialect == TLS_GNU2) |
d3585b76 | 211 | |
5b3e6663 PB |
212 | /* Only 16-bit thumb code. */ |
213 | #define TARGET_THUMB1 (TARGET_THUMB && !arm_arch_thumb2) | |
214 | /* Arm or Thumb-2 32-bit code. */ | |
215 | #define TARGET_32BIT (TARGET_ARM || arm_arch_thumb2) | |
216 | /* 32-bit Thumb-2 code. */ | |
217 | #define TARGET_THUMB2 (TARGET_THUMB && arm_arch_thumb2) | |
bf98ec6c PB |
218 | /* Thumb-1 only. */ |
219 | #define TARGET_THUMB1_ONLY (TARGET_THUMB1 && !arm_arch_notm) | |
d79f3032 PB |
220 | /* FPA emulator without LFM. */ |
221 | #define TARGET_FPA_EMU2 (TARGET_FPA && arm_fpu_desc->rev == 2) | |
5b3e6663 | 222 | |
88f77cba | 223 | /* The following two macros concern the ability to execute coprocessor |
302c3d8e PB |
224 | instructions for VFPv3 or NEON. TARGET_VFP3/TARGET_VFPD32 are currently |
225 | only ever tested when we know we are generating for VFP hardware; we need | |
226 | to be more careful with TARGET_NEON as noted below. */ | |
88f77cba | 227 | |
302c3d8e | 228 | /* FPU is has the full VFPv3/NEON register file of 32 D registers. */ |
d79f3032 | 229 | #define TARGET_VFPD32 (TARGET_VFP && arm_fpu_desc->regs == VFP_REG_D32) |
302c3d8e PB |
230 | |
231 | /* FPU supports VFPv3 instructions. */ | |
d79f3032 | 232 | #define TARGET_VFP3 (TARGET_VFP && arm_fpu_desc->rev >= 3) |
302c3d8e | 233 | |
e0dc3601 PB |
234 | /* FPU only supports VFP single-precision instructions. */ |
235 | #define TARGET_VFP_SINGLE (TARGET_VFP && arm_fpu_desc->regs == VFP_REG_SINGLE) | |
236 | ||
237 | /* FPU supports VFP double-precision instructions. */ | |
238 | #define TARGET_VFP_DOUBLE (TARGET_VFP && arm_fpu_desc->regs != VFP_REG_SINGLE) | |
239 | ||
240 | /* FPU supports half-precision floating-point with NEON element load/store. */ | |
d79f3032 PB |
241 | #define TARGET_NEON_FP16 \ |
242 | (TARGET_VFP && arm_fpu_desc->neon && arm_fpu_desc->fp16) | |
0fd8c3ad | 243 | |
e0dc3601 PB |
244 | /* FPU supports VFP half-precision floating-point. */ |
245 | #define TARGET_FP16 (TARGET_VFP && arm_fpu_desc->fp16) | |
246 | ||
88f77cba JB |
247 | /* FPU supports Neon instructions. The setting of this macro gets |
248 | revealed via __ARM_NEON__ so we add extra guards upon TARGET_32BIT | |
249 | and TARGET_HARD_FLOAT to ensure that NEON instructions are | |
250 | available. */ | |
251 | #define TARGET_NEON (TARGET_32BIT && TARGET_HARD_FLOAT \ | |
d79f3032 | 252 | && TARGET_VFP && arm_fpu_desc->neon) |
f1adb0a9 | 253 | |
5b3e6663 PB |
254 | /* "DSP" multiply instructions, eg. SMULxy. */ |
255 | #define TARGET_DSP_MULTIPLY \ | |
60bd3528 | 256 | (TARGET_32BIT && arm_arch5e && (arm_arch_notm || arm_arch7em)) |
5b3e6663 PB |
257 | /* Integer SIMD instructions, and extend-accumulate instructions. */ |
258 | #define TARGET_INT_SIMD \ | |
60bd3528 | 259 | (TARGET_32BIT && arm_arch6 && (arm_arch_notm || arm_arch7em)) |
5b3e6663 | 260 | |
571191af | 261 | /* Should MOVW/MOVT be used in preference to a constant pool. */ |
7ec70105 JB |
262 | #define TARGET_USE_MOVT \ |
263 | (arm_arch_thumb2 && !optimize_size && !current_tune->prefer_constant_pool) | |
571191af | 264 | |
5b3e6663 PB |
265 | /* We could use unified syntax for arm mode, but for now we just use it |
266 | for Thumb-2. */ | |
267 | #define TARGET_UNIFIED_ASM TARGET_THUMB2 | |
268 | ||
029e79eb MS |
269 | /* Nonzero if this chip provides the DMB instruction. */ |
270 | #define TARGET_HAVE_DMB (arm_arch7) | |
271 | ||
272 | /* Nonzero if this chip implements a memory barrier via CP15. */ | |
80651d8e DAG |
273 | #define TARGET_HAVE_DMB_MCR (arm_arch6 && ! TARGET_HAVE_DMB \ |
274 | && ! TARGET_THUMB1) | |
029e79eb MS |
275 | |
276 | /* Nonzero if this chip implements a memory barrier instruction. */ | |
277 | #define TARGET_HAVE_MEMORY_BARRIER (TARGET_HAVE_DMB || TARGET_HAVE_DMB_MCR) | |
278 | ||
279 | /* Nonzero if this chip supports ldrex and strex */ | |
280 | #define TARGET_HAVE_LDREX ((arm_arch6 && TARGET_ARM) || arm_arch7) | |
281 | ||
cfe52743 DAG |
282 | /* Nonzero if this chip supports ldrex{bh} and strex{bh}. */ |
283 | #define TARGET_HAVE_LDREXBH ((arm_arch6k && TARGET_ARM) || arm_arch7) | |
284 | ||
285 | /* Nonzero if this chip supports ldrexd and strexd. */ | |
286 | #define TARGET_HAVE_LDREXD (((arm_arch6k && TARGET_ARM) || arm_arch7) \ | |
287 | && arm_arch_notm) | |
5b3e6663 | 288 | |
572070ef PB |
289 | /* Nonzero if integer division instructions supported. */ |
290 | #define TARGET_IDIV ((TARGET_ARM && arm_arch_arm_hwdiv) \ | |
291 | || (TARGET_THUMB2 && arm_arch_thumb_hwdiv)) | |
292 | ||
b3f8d95d MM |
293 | /* True iff the full BPABI is being used. If TARGET_BPABI is true, |
294 | then TARGET_AAPCS_BASED must be true -- but the converse does not | |
295 | hold. TARGET_BPABI implies the use of the BPABI runtime library, | |
296 | etc., in addition to just the AAPCS calling conventions. */ | |
297 | #ifndef TARGET_BPABI | |
298 | #define TARGET_BPABI false | |
f676971a | 299 | #endif |
b3f8d95d | 300 | |
7816bea0 DJ |
301 | /* Support for a compile-time default CPU, et cetera. The rules are: |
302 | --with-arch is ignored if -march or -mcpu are specified. | |
303 | --with-cpu is ignored if -march or -mcpu are specified, and is overridden | |
304 | by --with-arch. | |
305 | --with-tune is ignored if -mtune or -mcpu are specified (but not affected | |
306 | by -march). | |
5e1b4d5a | 307 | --with-float is ignored if -mfloat-abi is specified. |
5848830f | 308 | --with-fpu is ignored if -mfpu is specified. |
ccdc2164 NS |
309 | --with-abi is ignored if -mabi is specified. |
310 | --with-tls is ignored if -mtls-dialect is specified. */ | |
7816bea0 DJ |
311 | #define OPTION_DEFAULT_SPECS \ |
312 | {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \ | |
313 | {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \ | |
314 | {"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}" }, \ | |
5e1b4d5a | 315 | {"float", "%{!mfloat-abi=*:-mfloat-abi=%(VALUE)}" }, \ |
5848830f | 316 | {"fpu", "%{!mfpu=*:-mfpu=%(VALUE)}"}, \ |
3cf94279 | 317 | {"abi", "%{!mabi=*:-mabi=%(VALUE)}"}, \ |
ccdc2164 | 318 | {"mode", "%{!marm:%{!mthumb:-m%(VALUE)}}"}, \ |
7cf13d1f | 319 | {"tls", "%{!mtls-dialect=*:-mtls-dialect=%(VALUE)}"}, |
7816bea0 | 320 | |
9b66ebb1 PB |
321 | /* Which floating point model to use. */ |
322 | enum arm_fp_model | |
323 | { | |
324 | ARM_FP_MODEL_UNKNOWN, | |
325 | /* FPA model (Hardware or software). */ | |
326 | ARM_FP_MODEL_FPA, | |
327 | /* Cirrus Maverick floating point model. */ | |
328 | ARM_FP_MODEL_MAVERICK, | |
329 | /* VFP floating point model. */ | |
330 | ARM_FP_MODEL_VFP | |
331 | }; | |
332 | ||
d79f3032 | 333 | enum vfp_reg_type |
24f0c1b4 | 334 | { |
70dd156a | 335 | VFP_NONE = 0, |
d79f3032 PB |
336 | VFP_REG_D16, |
337 | VFP_REG_D32, | |
338 | VFP_REG_SINGLE | |
24f0c1b4 RE |
339 | }; |
340 | ||
d79f3032 PB |
341 | extern const struct arm_fpu_desc |
342 | { | |
343 | const char *name; | |
344 | enum arm_fp_model model; | |
345 | int rev; | |
346 | enum vfp_reg_type regs; | |
347 | int neon; | |
348 | int fp16; | |
349 | } *arm_fpu_desc; | |
350 | ||
351 | /* Which floating point hardware to schedule for. */ | |
352 | extern int arm_fpu_attr; | |
71791e16 | 353 | |
3d8532aa PB |
354 | #ifndef TARGET_DEFAULT_FLOAT_ABI |
355 | #define TARGET_DEFAULT_FLOAT_ABI ARM_FLOAT_ABI_SOFT | |
356 | #endif | |
357 | ||
0fd8c3ad SL |
358 | #define LARGEST_EXPONENT_IS_NORMAL(bits) \ |
359 | ((bits) == 16 && arm_fp16_format == ARM_FP16_FORMAT_ALTERNATIVE) | |
360 | ||
5848830f PB |
361 | #ifndef ARM_DEFAULT_ABI |
362 | #define ARM_DEFAULT_ABI ARM_ABI_APCS | |
363 | #endif | |
364 | ||
9b66ebb1 PB |
365 | /* Nonzero if this chip supports the ARM Architecture 3M extensions. */ |
366 | extern int arm_arch3m; | |
11c1a207 | 367 | |
9b66ebb1 | 368 | /* Nonzero if this chip supports the ARM Architecture 4 extensions. */ |
11c1a207 RE |
369 | extern int arm_arch4; |
370 | ||
68d560d4 RE |
371 | /* Nonzero if this chip supports the ARM Architecture 4T extensions. */ |
372 | extern int arm_arch4t; | |
373 | ||
9b66ebb1 | 374 | /* Nonzero if this chip supports the ARM Architecture 5 extensions. */ |
62b10bbc NC |
375 | extern int arm_arch5; |
376 | ||
9b66ebb1 | 377 | /* Nonzero if this chip supports the ARM Architecture 5E extensions. */ |
b15bca31 RE |
378 | extern int arm_arch5e; |
379 | ||
9b66ebb1 PB |
380 | /* Nonzero if this chip supports the ARM Architecture 6 extensions. */ |
381 | extern int arm_arch6; | |
382 | ||
029e79eb MS |
383 | /* Nonzero if this chip supports the ARM Architecture 6k extensions. */ |
384 | extern int arm_arch6k; | |
385 | ||
386 | /* Nonzero if this chip supports the ARM Architecture 7 extensions. */ | |
387 | extern int arm_arch7; | |
388 | ||
5b3e6663 PB |
389 | /* Nonzero if instructions not present in the 'M' profile can be used. */ |
390 | extern int arm_arch_notm; | |
391 | ||
60bd3528 PB |
392 | /* Nonzero if instructions present in ARMv7E-M can be used. */ |
393 | extern int arm_arch7em; | |
394 | ||
f5a1b0d2 NC |
395 | /* Nonzero if this chip can benefit from load scheduling. */ |
396 | extern int arm_ld_sched; | |
397 | ||
906668bb | 398 | /* Nonzero if generating Thumb code, either Thumb-1 or Thumb-2. */ |
0616531f RE |
399 | extern int thumb_code; |
400 | ||
906668bb BS |
401 | /* Nonzero if generating Thumb-1 code. */ |
402 | extern int thumb1_code; | |
403 | ||
f5a1b0d2 | 404 | /* Nonzero if this chip is a StrongARM. */ |
abac3b49 | 405 | extern int arm_tune_strongarm; |
f5a1b0d2 | 406 | |
9b6b54e2 | 407 | /* Nonzero if this chip is a Cirrus variant. */ |
78011587 | 408 | extern int arm_arch_cirrus; |
9b6b54e2 | 409 | |
5a9335ef NC |
410 | /* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */ |
411 | extern int arm_arch_iwmmxt; | |
412 | ||
d19fb8e3 | 413 | /* Nonzero if this chip is an XScale. */ |
4b3c2e48 PB |
414 | extern int arm_arch_xscale; |
415 | ||
abac3b49 | 416 | /* Nonzero if tuning for XScale. */ |
4b3c2e48 | 417 | extern int arm_tune_xscale; |
d19fb8e3 | 418 | |
abac3b49 RE |
419 | /* Nonzero if tuning for stores via the write buffer. */ |
420 | extern int arm_tune_wbuf; | |
f5a1b0d2 | 421 | |
7612f14d PB |
422 | /* Nonzero if tuning for Cortex-A9. */ |
423 | extern int arm_tune_cortex_a9; | |
424 | ||
2ad4dcf9 | 425 | /* Nonzero if we should define __THUMB_INTERWORK__ in the |
f676971a | 426 | preprocessor. |
2ad4dcf9 RE |
427 | XXX This is a bit of a hack, it's intended to help work around |
428 | problems in GLD which doesn't understand that armv5t code is | |
429 | interworking clean. */ | |
430 | extern int arm_cpp_interwork; | |
431 | ||
5b3e6663 PB |
432 | /* Nonzero if chip supports Thumb 2. */ |
433 | extern int arm_arch_thumb2; | |
434 | ||
572070ef PB |
435 | /* Nonzero if chip supports integer division instruction in ARM mode. */ |
436 | extern int arm_arch_arm_hwdiv; | |
437 | ||
438 | /* Nonzero if chip supports integer division instruction in Thumb mode. */ | |
439 | extern int arm_arch_thumb_hwdiv; | |
5b3e6663 | 440 | |
2ce9c1b9 | 441 | #ifndef TARGET_DEFAULT |
c54c7322 | 442 | #define TARGET_DEFAULT (MASK_APCS_FRAME) |
2ce9c1b9 | 443 | #endif |
35d965d5 | 444 | |
86efdc8e PB |
445 | /* Nonzero if PIC code requires explicit qualifiers to generate |
446 | PLT and GOT relocs rather than the assembler doing so implicitly. | |
ed0e6530 PB |
447 | Subtargets can override these if required. */ |
448 | #ifndef NEED_GOT_RELOC | |
449 | #define NEED_GOT_RELOC 0 | |
450 | #endif | |
451 | #ifndef NEED_PLT_RELOC | |
452 | #define NEED_PLT_RELOC 0 | |
e2723c62 | 453 | #endif |
84306176 PB |
454 | |
455 | /* Nonzero if we need to refer to the GOT with a PC-relative | |
456 | offset. In other words, generate | |
457 | ||
f676971a | 458 | .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)] |
84306176 PB |
459 | |
460 | rather than | |
461 | ||
462 | .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8) | |
463 | ||
f676971a | 464 | The default is true, which matches NetBSD. Subtargets can |
84306176 PB |
465 | override this if required. */ |
466 | #ifndef GOT_PCREL | |
467 | #define GOT_PCREL 1 | |
468 | #endif | |
35d965d5 RS |
469 | \f |
470 | /* Target machine storage Layout. */ | |
471 | ||
ff9940b0 RE |
472 | |
473 | /* Define this macro if it is advisable to hold scalars in registers | |
474 | in a wider mode than that declared by the program. In such cases, | |
475 | the value is constrained to be within the bounds of the declared | |
476 | type, but kept valid in the wider mode. The signedness of the | |
477 | extension may differ from that of the type. */ | |
478 | ||
479 | /* It is far faster to zero extend chars than to sign extend them */ | |
480 | ||
6cfc7210 | 481 | #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ |
2ce9c1b9 RE |
482 | if (GET_MODE_CLASS (MODE) == MODE_INT \ |
483 | && GET_MODE_SIZE (MODE) < 4) \ | |
484 | { \ | |
485 | if (MODE == QImode) \ | |
486 | UNSIGNEDP = 1; \ | |
487 | else if (MODE == HImode) \ | |
61f0ccff | 488 | UNSIGNEDP = 1; \ |
2ce9c1b9 | 489 | (MODE) = SImode; \ |
ff9940b0 RE |
490 | } |
491 | ||
35d965d5 RS |
492 | /* Define this if most significant bit is lowest numbered |
493 | in instructions that operate on numbered bit-fields. */ | |
494 | #define BITS_BIG_ENDIAN 0 | |
495 | ||
f676971a | 496 | /* Define this if most significant byte of a word is the lowest numbered. |
3ada8e17 DE |
497 | Most ARM processors are run in little endian mode, so that is the default. |
498 | If you want to have it run-time selectable, change the definition in a | |
499 | cover file to be TARGET_BIG_ENDIAN. */ | |
11c1a207 | 500 | #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0) |
35d965d5 RS |
501 | |
502 | /* Define this if most significant word of a multiword number is the lowest | |
11c1a207 RE |
503 | numbered. |
504 | This is always false, even when in big-endian mode. */ | |
ddee6aba RE |
505 | #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS) |
506 | ||
11c1a207 | 507 | /* Define this if most significant word of doubles is the lowest numbered. |
f0375c66 NC |
508 | The rules are different based on whether or not we use FPA-format, |
509 | VFP-format or some other floating point co-processor's format doubles. */ | |
b5b620a4 | 510 | #define FLOAT_WORDS_BIG_ENDIAN (arm_float_words_big_endian ()) |
7fc6c9f0 | 511 | |
35d965d5 RS |
512 | #define UNITS_PER_WORD 4 |
513 | ||
5848830f | 514 | /* True if natural alignment is used for doubleword types. */ |
b6685939 PB |
515 | #define ARM_DOUBLEWORD_ALIGN TARGET_AAPCS_BASED |
516 | ||
5848830f | 517 | #define DOUBLEWORD_ALIGNMENT 64 |
35d965d5 | 518 | |
5848830f | 519 | #define PARM_BOUNDARY 32 |
5a9335ef | 520 | |
5848830f | 521 | #define STACK_BOUNDARY (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32) |
35d965d5 | 522 | |
5848830f PB |
523 | #define PREFERRED_STACK_BOUNDARY \ |
524 | (arm_abi == ARM_ABI_ATPCS ? 64 : STACK_BOUNDARY) | |
0977774b | 525 | |
f711a87a | 526 | #define FUNCTION_BOUNDARY ((TARGET_THUMB && optimize_size) ? 16 : 32) |
35d965d5 | 527 | |
92928d71 AO |
528 | /* The lowest bit is used to indicate Thumb-mode functions, so the |
529 | vbit must go into the delta field of pointers to member | |
530 | functions. */ | |
531 | #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta | |
532 | ||
35d965d5 RS |
533 | #define EMPTY_FIELD_BOUNDARY 32 |
534 | ||
5848830f | 535 | #define BIGGEST_ALIGNMENT (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32) |
5a9335ef | 536 | |
27847754 NC |
537 | /* XXX Blah -- this macro is used directly by libobjc. Since it |
538 | supports no vector modes, cut out the complexity and fall back | |
539 | on BIGGEST_FIELD_ALIGNMENT. */ | |
540 | #ifdef IN_TARGET_LIBS | |
8fca31a2 | 541 | #define BIGGEST_FIELD_ALIGNMENT 64 |
27847754 | 542 | #endif |
5a9335ef | 543 | |
ff9940b0 | 544 | /* Make strings word-aligned so strcpy from constants will be faster. */ |
591af218 | 545 | #define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_tune_xscale ? 1 : 2) |
f676971a | 546 | |
d19fb8e3 | 547 | #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ |
5848830f | 548 | ((TREE_CODE (EXP) == STRING_CST \ |
36b15ad0 | 549 | && !optimize_size \ |
5848830f PB |
550 | && (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \ |
551 | ? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN)) | |
ff9940b0 | 552 | |
96339268 RE |
553 | /* Align definitions of arrays, unions and structures so that |
554 | initializations and copies can be made more efficient. This is not | |
555 | ABI-changing, so it only affects places where we can see the | |
0c86e0dd CLT |
556 | definition. Increasing the alignment tends to introduce padding, |
557 | so don't do this when optimizing for size/conserving stack space. */ | |
558 | #define ARM_EXPAND_ALIGNMENT(COND, EXP, ALIGN) \ | |
559 | (((COND) && ((ALIGN) < BITS_PER_WORD) \ | |
96339268 RE |
560 | && (TREE_CODE (EXP) == ARRAY_TYPE \ |
561 | || TREE_CODE (EXP) == UNION_TYPE \ | |
562 | || TREE_CODE (EXP) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN)) | |
563 | ||
0c86e0dd CLT |
564 | /* Align global data. */ |
565 | #define DATA_ALIGNMENT(EXP, ALIGN) \ | |
566 | ARM_EXPAND_ALIGNMENT(!optimize_size, EXP, ALIGN) | |
567 | ||
96339268 | 568 | /* Similarly, make sure that objects on the stack are sensibly aligned. */ |
0c86e0dd CLT |
569 | #define LOCAL_ALIGNMENT(EXP, ALIGN) \ |
570 | ARM_EXPAND_ALIGNMENT(!flag_conserve_stack, EXP, ALIGN) | |
96339268 | 571 | |
723ae7c1 NC |
572 | /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the |
573 | value set in previous versions of this toolchain was 8, which produces more | |
574 | compact structures. The command line option -mstructure_size_boundary=<n> | |
f710504c | 575 | can be used to change this value. For compatibility with the ARM SDK |
723ae7c1 | 576 | however the value should be left at 32. ARM SDT Reference Manual (ARM DUI |
5848830f PB |
577 | 0020D) page 2-20 says "Structures are aligned on word boundaries". |
578 | The AAPCS specifies a value of 8. */ | |
6ead9ba5 | 579 | #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary |
723ae7c1 | 580 | |
4912a07c | 581 | /* This is the value used to initialize arm_structure_size_boundary. If a |
723ae7c1 | 582 | particular arm target wants to change the default value it should change |
6bc82793 | 583 | the definition of this macro, not STRUCTURE_SIZE_BOUNDARY. See netbsd.h |
723ae7c1 NC |
584 | for an example of this. */ |
585 | #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY | |
586 | #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32 | |
b355a481 | 587 | #endif |
2a5307b1 | 588 | |
825dda42 | 589 | /* Nonzero if move instructions will actually fail to work |
ff9940b0 | 590 | when given unaligned data. */ |
35d965d5 | 591 | #define STRICT_ALIGNMENT 1 |
b6685939 PB |
592 | |
593 | /* wchar_t is unsigned under the AAPCS. */ | |
594 | #ifndef WCHAR_TYPE | |
595 | #define WCHAR_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "int") | |
596 | ||
597 | #define WCHAR_TYPE_SIZE BITS_PER_WORD | |
598 | #endif | |
599 | ||
655b30bf JB |
600 | /* Sized for fixed-point types. */ |
601 | ||
602 | #define SHORT_FRACT_TYPE_SIZE 8 | |
603 | #define FRACT_TYPE_SIZE 16 | |
604 | #define LONG_FRACT_TYPE_SIZE 32 | |
605 | #define LONG_LONG_FRACT_TYPE_SIZE 64 | |
606 | ||
607 | #define SHORT_ACCUM_TYPE_SIZE 16 | |
608 | #define ACCUM_TYPE_SIZE 32 | |
609 | #define LONG_ACCUM_TYPE_SIZE 64 | |
610 | #define LONG_LONG_ACCUM_TYPE_SIZE 64 | |
611 | ||
612 | #define MAX_FIXED_MODE_SIZE 64 | |
613 | ||
b6685939 PB |
614 | #ifndef SIZE_TYPE |
615 | #define SIZE_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "long unsigned int") | |
616 | #endif | |
d81d0bdd | 617 | |
077fc835 KH |
618 | #ifndef PTRDIFF_TYPE |
619 | #define PTRDIFF_TYPE (TARGET_AAPCS_BASED ? "int" : "long int") | |
620 | #endif | |
621 | ||
d81d0bdd PB |
622 | /* AAPCS requires that structure alignment is affected by bitfields. */ |
623 | #ifndef PCC_BITFIELD_TYPE_MATTERS | |
624 | #define PCC_BITFIELD_TYPE_MATTERS TARGET_AAPCS_BASED | |
625 | #endif | |
626 | ||
35d965d5 RS |
627 | \f |
628 | /* Standard register usage. */ | |
629 | ||
630 | /* Register allocation in ARM Procedure Call Standard (as used on RISCiX): | |
631 | (S - saved over call). | |
632 | ||
633 | r0 * argument word/integer result | |
634 | r1-r3 argument word | |
635 | ||
636 | r4-r8 S register variable | |
637 | r9 S (rfp) register variable (real frame pointer) | |
f676971a | 638 | |
f5a1b0d2 | 639 | r10 F S (sl) stack limit (used by -mapcs-stack-check) |
35d965d5 RS |
640 | r11 F S (fp) argument pointer |
641 | r12 (ip) temp workspace | |
642 | r13 F S (sp) lower end of current stack frame | |
643 | r14 (lr) link address/workspace | |
644 | r15 F (pc) program counter | |
645 | ||
646 | f0 floating point result | |
647 | f1-f3 floating point scratch | |
648 | ||
649 | f4-f7 S floating point variable | |
650 | ||
ff9940b0 RE |
651 | cc This is NOT a real register, but is used internally |
652 | to represent things that use or set the condition | |
653 | codes. | |
654 | sfp This isn't either. It is used during rtl generation | |
655 | since the offset between the frame pointer and the | |
656 | auto's isn't known until after register allocation. | |
657 | afp Nor this, we only need this because of non-local | |
658 | goto. Without it fp appears to be used and the | |
659 | elimination code won't get rid of sfp. It tracks | |
660 | fp exactly at all times. | |
661 | ||
5efd84c5 | 662 | *: See TARGET_CONDITIONAL_REGISTER_USAGE */ |
35d965d5 | 663 | |
9b6b54e2 NC |
664 | /* |
665 | mvf0 Cirrus floating point result | |
666 | mvf1-mvf3 Cirrus floating point scratch | |
667 | mvf4-mvf15 S Cirrus floating point variable. */ | |
668 | ||
9b66ebb1 PB |
669 | /* s0-s15 VFP scratch (aka d0-d7). |
670 | s16-s31 S VFP variable (aka d8-d15). | |
671 | vfpcc Not a real register. Represents the VFP condition | |
672 | code flags. */ | |
673 | ||
ff9940b0 RE |
674 | /* The stack backtrace structure is as follows: |
675 | fp points to here: | save code pointer | [fp] | |
676 | | return link value | [fp, #-4] | |
677 | | return sp value | [fp, #-8] | |
678 | | return fp value | [fp, #-12] | |
679 | [| saved r10 value |] | |
680 | [| saved r9 value |] | |
681 | [| saved r8 value |] | |
682 | [| saved r7 value |] | |
683 | [| saved r6 value |] | |
684 | [| saved r5 value |] | |
685 | [| saved r4 value |] | |
686 | [| saved r3 value |] | |
687 | [| saved r2 value |] | |
688 | [| saved r1 value |] | |
689 | [| saved r0 value |] | |
690 | [| saved f7 value |] three words | |
691 | [| saved f6 value |] three words | |
692 | [| saved f5 value |] three words | |
693 | [| saved f4 value |] three words | |
694 | r0-r3 are not normally saved in a C function. */ | |
695 | ||
35d965d5 RS |
696 | /* 1 for registers that have pervasive standard uses |
697 | and are not available for the register allocator. */ | |
9b66ebb1 PB |
698 | #define FIXED_REGISTERS \ |
699 | { \ | |
700 | 0,0,0,0,0,0,0,0, \ | |
701 | 0,0,0,0,0,1,0,1, \ | |
702 | 0,0,0,0,0,0,0,0, \ | |
9b6b54e2 NC |
703 | 1,1,1, \ |
704 | 1,1,1,1,1,1,1,1, \ | |
9b66ebb1 PB |
705 | 1,1,1,1,1,1,1,1, \ |
706 | 1,1,1,1,1,1,1,1, \ | |
707 | 1,1,1,1,1,1,1,1, \ | |
708 | 1,1,1,1, \ | |
709 | 1,1,1,1,1,1,1,1, \ | |
710 | 1,1,1,1,1,1,1,1, \ | |
711 | 1,1,1,1,1,1,1,1, \ | |
712 | 1,1,1,1,1,1,1,1, \ | |
f1adb0a9 JB |
713 | 1,1,1,1,1,1,1,1, \ |
714 | 1,1,1,1,1,1,1,1, \ | |
715 | 1,1,1,1,1,1,1,1, \ | |
716 | 1,1,1,1,1,1,1,1, \ | |
9b66ebb1 | 717 | 1 \ |
35d965d5 RS |
718 | } |
719 | ||
720 | /* 1 for registers not available across function calls. | |
721 | These must include the FIXED_REGISTERS and also any | |
722 | registers that can be used without being saved. | |
723 | The latter must include the registers where values are returned | |
724 | and the register where structure-value addresses are passed. | |
ff9940b0 | 725 | Aside from that, you can include as many other registers as you like. |
f676971a | 726 | The CC is not preserved over function calls on the ARM 6, so it is |
d6b4baa4 | 727 | easier to assume this for all. SFP is preserved, since FP is. */ |
35d965d5 RS |
728 | #define CALL_USED_REGISTERS \ |
729 | { \ | |
730 | 1,1,1,1,0,0,0,0, \ | |
d5b7b3ae | 731 | 0,0,0,0,1,1,1,1, \ |
ff9940b0 | 732 | 1,1,1,1,0,0,0,0, \ |
9b6b54e2 NC |
733 | 1,1,1, \ |
734 | 1,1,1,1,1,1,1,1, \ | |
5a9335ef NC |
735 | 1,1,1,1,1,1,1,1, \ |
736 | 1,1,1,1,1,1,1,1, \ | |
737 | 1,1,1,1,1,1,1,1, \ | |
9b66ebb1 PB |
738 | 1,1,1,1, \ |
739 | 1,1,1,1,1,1,1,1, \ | |
740 | 1,1,1,1,1,1,1,1, \ | |
741 | 1,1,1,1,1,1,1,1, \ | |
742 | 1,1,1,1,1,1,1,1, \ | |
f1adb0a9 JB |
743 | 1,1,1,1,1,1,1,1, \ |
744 | 1,1,1,1,1,1,1,1, \ | |
745 | 1,1,1,1,1,1,1,1, \ | |
746 | 1,1,1,1,1,1,1,1, \ | |
9b66ebb1 | 747 | 1 \ |
35d965d5 RS |
748 | } |
749 | ||
6cc8c0b3 NC |
750 | #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE |
751 | #define SUBTARGET_CONDITIONAL_REGISTER_USAGE | |
752 | #endif | |
753 | ||
6bc82793 | 754 | /* These are a couple of extensions to the formats accepted |
dd18ae56 NC |
755 | by asm_fprintf: |
756 | %@ prints out ASM_COMMENT_START | |
757 | %r prints out REGISTER_PREFIX reg_names[arg] */ | |
758 | #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \ | |
759 | case '@': \ | |
760 | fputs (ASM_COMMENT_START, FILE); \ | |
761 | break; \ | |
762 | \ | |
763 | case 'r': \ | |
764 | fputs (REGISTER_PREFIX, FILE); \ | |
765 | fputs (reg_names [va_arg (ARGS, int)], FILE); \ | |
766 | break; | |
767 | ||
d5b7b3ae | 768 | /* Round X up to the nearest word. */ |
0c2ca901 | 769 | #define ROUND_UP_WORD(X) (((X) + 3) & ~3) |
d5b7b3ae | 770 | |
6cfc7210 | 771 | /* Convert fron bytes to ints. */ |
e9d7b180 | 772 | #define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) |
6cfc7210 | 773 | |
9b66ebb1 PB |
774 | /* The number of (integer) registers required to hold a quantity of type MODE. |
775 | Also used for VFP registers. */ | |
e9d7b180 JD |
776 | #define ARM_NUM_REGS(MODE) \ |
777 | ARM_NUM_INTS (GET_MODE_SIZE (MODE)) | |
6cfc7210 NC |
778 | |
779 | /* The number of (integer) registers required to hold a quantity of TYPE MODE. */ | |
e9d7b180 JD |
780 | #define ARM_NUM_REGS2(MODE, TYPE) \ |
781 | ARM_NUM_INTS ((MODE) == BLKmode ? \ | |
d5b7b3ae | 782 | int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE)) |
6cfc7210 NC |
783 | |
784 | /* The number of (integer) argument register available. */ | |
d5b7b3ae | 785 | #define NUM_ARG_REGS 4 |
6cfc7210 | 786 | |
390b17c2 RE |
787 | /* And similarly for the VFP. */ |
788 | #define NUM_VFP_ARG_REGS 16 | |
789 | ||
093354e0 | 790 | /* Return the register number of the N'th (integer) argument. */ |
d5b7b3ae | 791 | #define ARG_REGISTER(N) (N - 1) |
6cfc7210 | 792 | |
d5b7b3ae RE |
793 | /* Specify the registers used for certain standard purposes. |
794 | The values of these macros are register numbers. */ | |
35d965d5 | 795 | |
d5b7b3ae RE |
796 | /* The number of the last argument register. */ |
797 | #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS) | |
35d965d5 | 798 | |
c769a35d RE |
799 | /* The numbers of the Thumb register ranges. */ |
800 | #define FIRST_LO_REGNUM 0 | |
6d3d9133 | 801 | #define LAST_LO_REGNUM 7 |
c769a35d RE |
802 | #define FIRST_HI_REGNUM 8 |
803 | #define LAST_HI_REGNUM 11 | |
6d3d9133 | 804 | |
f0a0390e RH |
805 | /* Overridden by config/arm/bpabi.h. */ |
806 | #ifndef ARM_UNWIND_INFO | |
807 | #define ARM_UNWIND_INFO 0 | |
617a1b71 PB |
808 | #endif |
809 | ||
c9ca9b88 PB |
810 | /* Use r0 and r1 to pass exception handling information. */ |
811 | #define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? N : INVALID_REGNUM) | |
812 | ||
6d3d9133 | 813 | /* The register that holds the return address in exception handlers. */ |
c9ca9b88 PB |
814 | #define ARM_EH_STACKADJ_REGNUM 2 |
815 | #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (SImode, ARM_EH_STACKADJ_REGNUM) | |
35d965d5 | 816 | |
1e874273 PB |
817 | #ifndef ARM_TARGET2_DWARF_FORMAT |
818 | #define ARM_TARGET2_DWARF_FORMAT DW_EH_PE_pcrel | |
819 | ||
820 | /* ttype entries (the only interesting data references used) | |
821 | use TARGET2 relocations. */ | |
822 | #define ASM_PREFERRED_EH_DATA_FORMAT(code, data) \ | |
823 | (((code) == 0 && (data) == 1 && ARM_UNWIND_INFO) ? ARM_TARGET2_DWARF_FORMAT \ | |
824 | : DW_EH_PE_absptr) | |
825 | #endif | |
826 | ||
d5b7b3ae RE |
827 | /* The native (Norcroft) Pascal compiler for the ARM passes the static chain |
828 | as an invisible last argument (possible since varargs don't exist in | |
829 | Pascal), so the following is not true. */ | |
5b3e6663 | 830 | #define STATIC_CHAIN_REGNUM 12 |
35d965d5 | 831 | |
d5b7b3ae RE |
832 | /* Define this to be where the real frame pointer is if it is not possible to |
833 | work out the offset between the frame pointer and the automatic variables | |
834 | until after register allocation has taken place. FRAME_POINTER_REGNUM | |
835 | should point to a special register that we will make sure is eliminated. | |
836 | ||
837 | For the Thumb we have another problem. The TPCS defines the frame pointer | |
6bc82793 | 838 | as r11, and GCC believes that it is always possible to use the frame pointer |
d5b7b3ae RE |
839 | as base register for addressing purposes. (See comments in |
840 | find_reloads_address()). But - the Thumb does not allow high registers, | |
841 | including r11, to be used as base address registers. Hence our problem. | |
842 | ||
843 | The solution used here, and in the old thumb port is to use r7 instead of | |
844 | r11 as the hard frame pointer and to have special code to generate | |
845 | backtrace structures on the stack (if required to do so via a command line | |
6bc82793 | 846 | option) using r11. This is the only 'user visible' use of r11 as a frame |
d5b7b3ae RE |
847 | pointer. */ |
848 | #define ARM_HARD_FRAME_POINTER_REGNUM 11 | |
849 | #define THUMB_HARD_FRAME_POINTER_REGNUM 7 | |
35d965d5 | 850 | |
b15bca31 RE |
851 | #define HARD_FRAME_POINTER_REGNUM \ |
852 | (TARGET_ARM \ | |
853 | ? ARM_HARD_FRAME_POINTER_REGNUM \ | |
854 | : THUMB_HARD_FRAME_POINTER_REGNUM) | |
d5b7b3ae | 855 | |
e3339d0f JM |
856 | #define HARD_FRAME_POINTER_IS_FRAME_POINTER 0 |
857 | #define HARD_FRAME_POINTER_IS_ARG_POINTER 0 | |
858 | ||
b15bca31 | 859 | #define FP_REGNUM HARD_FRAME_POINTER_REGNUM |
d5b7b3ae | 860 | |
b15bca31 RE |
861 | /* Register to use for pushing function arguments. */ |
862 | #define STACK_POINTER_REGNUM SP_REGNUM | |
d5b7b3ae RE |
863 | |
864 | /* ARM floating pointer registers. */ | |
9b66ebb1 PB |
865 | #define FIRST_FPA_REGNUM 16 |
866 | #define LAST_FPA_REGNUM 23 | |
2fa330b2 PB |
867 | #define IS_FPA_REGNUM(REGNUM) \ |
868 | (((REGNUM) >= FIRST_FPA_REGNUM) && ((REGNUM) <= LAST_FPA_REGNUM)) | |
d5b7b3ae | 869 | |
5a9335ef NC |
870 | #define FIRST_IWMMXT_GR_REGNUM 43 |
871 | #define LAST_IWMMXT_GR_REGNUM 46 | |
872 | #define FIRST_IWMMXT_REGNUM 47 | |
873 | #define LAST_IWMMXT_REGNUM 62 | |
874 | #define IS_IWMMXT_REGNUM(REGNUM) \ | |
875 | (((REGNUM) >= FIRST_IWMMXT_REGNUM) && ((REGNUM) <= LAST_IWMMXT_REGNUM)) | |
876 | #define IS_IWMMXT_GR_REGNUM(REGNUM) \ | |
877 | (((REGNUM) >= FIRST_IWMMXT_GR_REGNUM) && ((REGNUM) <= LAST_IWMMXT_GR_REGNUM)) | |
878 | ||
35d965d5 | 879 | /* Base register for access to local variables of the function. */ |
ff9940b0 RE |
880 | #define FRAME_POINTER_REGNUM 25 |
881 | ||
d5b7b3ae RE |
882 | /* Base register for access to arguments of the function. */ |
883 | #define ARG_POINTER_REGNUM 26 | |
62b10bbc | 884 | |
9b6b54e2 NC |
885 | #define FIRST_CIRRUS_FP_REGNUM 27 |
886 | #define LAST_CIRRUS_FP_REGNUM 42 | |
887 | #define IS_CIRRUS_REGNUM(REGNUM) \ | |
888 | (((REGNUM) >= FIRST_CIRRUS_FP_REGNUM) && ((REGNUM) <= LAST_CIRRUS_FP_REGNUM)) | |
889 | ||
9b66ebb1 | 890 | #define FIRST_VFP_REGNUM 63 |
f1adb0a9 JB |
891 | #define D7_VFP_REGNUM 78 /* Registers 77 and 78 == VFP reg D7. */ |
892 | #define LAST_VFP_REGNUM \ | |
302c3d8e | 893 | (TARGET_VFPD32 ? LAST_HI_VFP_REGNUM : LAST_LO_VFP_REGNUM) |
f1adb0a9 | 894 | |
9b66ebb1 PB |
895 | #define IS_VFP_REGNUM(REGNUM) \ |
896 | (((REGNUM) >= FIRST_VFP_REGNUM) && ((REGNUM) <= LAST_VFP_REGNUM)) | |
897 | ||
f1adb0a9 JB |
898 | /* VFP registers are split into two types: those defined by VFP versions < 3 |
899 | have D registers overlaid on consecutive pairs of S registers. VFP version 3 | |
900 | defines 16 new D registers (d16-d31) which, for simplicity and correctness | |
901 | in various parts of the backend, we implement as "fake" single-precision | |
902 | registers (which would be S32-S63, but cannot be used in that way). The | |
903 | following macros define these ranges of registers. */ | |
904 | #define LAST_LO_VFP_REGNUM 94 | |
905 | #define FIRST_HI_VFP_REGNUM 95 | |
906 | #define LAST_HI_VFP_REGNUM 126 | |
907 | ||
908 | #define VFP_REGNO_OK_FOR_SINGLE(REGNUM) \ | |
909 | ((REGNUM) <= LAST_LO_VFP_REGNUM) | |
910 | ||
911 | /* DFmode values are only valid in even register pairs. */ | |
912 | #define VFP_REGNO_OK_FOR_DOUBLE(REGNUM) \ | |
913 | ((((REGNUM) - FIRST_VFP_REGNUM) & 1) == 0) | |
914 | ||
88f77cba JB |
915 | /* Neon Quad values must start at a multiple of four registers. */ |
916 | #define NEON_REGNO_OK_FOR_QUAD(REGNUM) \ | |
917 | ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0) | |
918 | ||
919 | /* Neon structures of vectors must be in even register pairs and there | |
920 | must be enough registers available. Because of various patterns | |
921 | requiring quad registers, we require them to start at a multiple of | |
922 | four. */ | |
923 | #define NEON_REGNO_OK_FOR_NREGS(REGNUM, N) \ | |
924 | ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0 \ | |
925 | && (LAST_VFP_REGNUM - (REGNUM) >= 2 * (N) - 1)) | |
926 | ||
6f8c9bd1 NC |
927 | /* The number of hard registers is 16 ARM + 8 FPA + 1 CC + 1 SFP + 1 AFP. */ |
928 | /* + 16 Cirrus registers take us up to 43. */ | |
5a9335ef | 929 | /* Intel Wireless MMX Technology registers add 16 + 4 more. */ |
f1adb0a9 JB |
930 | /* VFP (VFP3) adds 32 (64) + 1 more. */ |
931 | #define FIRST_PSEUDO_REGISTER 128 | |
62b10bbc | 932 | |
2fa330b2 PB |
933 | #define DBX_REGISTER_NUMBER(REGNO) arm_dbx_register_number (REGNO) |
934 | ||
35d965d5 RS |
935 | /* Value should be nonzero if functions must have frame pointers. |
936 | Zero means the frame pointer need not be set up (and parms may be accessed | |
f676971a | 937 | via the stack pointer) in functions that seem suitable. |
ff9940b0 RE |
938 | If we have to have a frame pointer we might as well make use of it. |
939 | APCS says that the frame pointer does not need to be pushed in leaf | |
2a5307b1 | 940 | functions, or simple tail call functions. */ |
a15900b5 DJ |
941 | |
942 | #ifndef SUBTARGET_FRAME_POINTER_REQUIRED | |
943 | #define SUBTARGET_FRAME_POINTER_REQUIRED 0 | |
944 | #endif | |
945 | ||
d5b7b3ae RE |
946 | /* Return number of consecutive hard regs needed starting at reg REGNO |
947 | to hold something of mode MODE. | |
948 | This is ordinarily the length in words of a value of mode MODE | |
949 | but can be less for certain modes in special long registers. | |
35d965d5 | 950 | |
3b684012 | 951 | On the ARM regs are UNITS_PER_WORD bits wide; FPA regs can hold any FP |
d5b7b3ae RE |
952 | mode. */ |
953 | #define HARD_REGNO_NREGS(REGNO, MODE) \ | |
5b3e6663 | 954 | ((TARGET_32BIT \ |
9b66ebb1 | 955 | && REGNO >= FIRST_FPA_REGNUM \ |
d5b7b3ae RE |
956 | && REGNO != FRAME_POINTER_REGNUM \ |
957 | && REGNO != ARG_POINTER_REGNUM) \ | |
9b66ebb1 | 958 | && !IS_VFP_REGNUM (REGNO) \ |
e9d7b180 | 959 | ? 1 : ARM_NUM_REGS (MODE)) |
35d965d5 | 960 | |
4b02997f | 961 | /* Return true if REGNO is suitable for holding a quantity of type MODE. */ |
d5b7b3ae | 962 | #define HARD_REGNO_MODE_OK(REGNO, MODE) \ |
4b02997f | 963 | arm_hard_regno_mode_ok ((REGNO), (MODE)) |
35d965d5 | 964 | |
2af8e257 | 965 | #define MODES_TIEABLE_P(MODE1, MODE2) arm_modes_tieable_p (MODE1, MODE2) |
ff9940b0 | 966 | |
5a9335ef | 967 | #define VALID_IWMMXT_REG_MODE(MODE) \ |
f676971a | 968 | (arm_vector_mode_supported_p (MODE) || (MODE) == DImode) |
5a9335ef | 969 | |
88f77cba JB |
970 | /* Modes valid for Neon D registers. */ |
971 | #define VALID_NEON_DREG_MODE(MODE) \ | |
972 | ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode \ | |
973 | || (MODE) == V2SFmode || (MODE) == DImode) | |
974 | ||
975 | /* Modes valid for Neon Q registers. */ | |
976 | #define VALID_NEON_QREG_MODE(MODE) \ | |
977 | ((MODE) == V4SImode || (MODE) == V8HImode || (MODE) == V16QImode \ | |
978 | || (MODE) == V4SFmode || (MODE) == V2DImode) | |
979 | ||
980 | /* Structure modes valid for Neon registers. */ | |
981 | #define VALID_NEON_STRUCT_MODE(MODE) \ | |
982 | ((MODE) == TImode || (MODE) == EImode || (MODE) == OImode \ | |
983 | || (MODE) == CImode || (MODE) == XImode) | |
984 | ||
37119410 BS |
985 | /* The register numbers in sequence, for passing to arm_gen_load_multiple. */ |
986 | extern int arm_regs_in_sequence[]; | |
987 | ||
35d965d5 | 988 | /* The order in which register should be allocated. It is good to use ip |
ff9940b0 RE |
989 | since no saving is required (though calls clobber it) and it never contains |
990 | function parameters. It is quite good to use lr since other calls may | |
f676971a | 991 | clobber it anyway. Allocate r0 through r3 in reverse order since r3 is |
ff9940b0 | 992 | least likely to contain a function parameter; in addition results are |
f1adb0a9 JB |
993 | returned in r0. |
994 | For VFP/VFPv3, allocate D16-D31 first, then caller-saved registers (D0-D7), | |
995 | then D8-D15. The reason for doing this is to attempt to reduce register | |
996 | pressure when both single- and double-precision registers are used in a | |
997 | function. */ | |
998 | ||
999 | #define REG_ALLOC_ORDER \ | |
1000 | { \ | |
1001 | 3, 2, 1, 0, 12, 14, 4, 5, \ | |
1002 | 6, 7, 8, 10, 9, 11, 13, 15, \ | |
1003 | 16, 17, 18, 19, 20, 21, 22, 23, \ | |
1004 | 27, 28, 29, 30, 31, 32, 33, 34, \ | |
1005 | 35, 36, 37, 38, 39, 40, 41, 42, \ | |
1006 | 43, 44, 45, 46, 47, 48, 49, 50, \ | |
1007 | 51, 52, 53, 54, 55, 56, 57, 58, \ | |
1008 | 59, 60, 61, 62, \ | |
1009 | 24, 25, 26, \ | |
1010 | 95, 96, 97, 98, 99, 100, 101, 102, \ | |
1011 | 103, 104, 105, 106, 107, 108, 109, 110, \ | |
1012 | 111, 112, 113, 114, 115, 116, 117, 118, \ | |
1013 | 119, 120, 121, 122, 123, 124, 125, 126, \ | |
1014 | 78, 77, 76, 75, 74, 73, 72, 71, \ | |
1015 | 70, 69, 68, 67, 66, 65, 64, 63, \ | |
1016 | 79, 80, 81, 82, 83, 84, 85, 86, \ | |
1017 | 87, 88, 89, 90, 91, 92, 93, 94, \ | |
1018 | 127 \ | |
35d965d5 | 1019 | } |
9338ffe6 | 1020 | |
795dc4fc | 1021 | /* Use different register alloc ordering for Thumb. */ |
5a733826 BS |
1022 | #define ADJUST_REG_ALLOC_ORDER arm_order_regs_for_local_alloc () |
1023 | ||
1024 | /* Tell IRA to use the order we define rather than messing it up with its | |
1025 | own cost calculations. */ | |
1026 | #define HONOR_REG_ALLOC_ORDER | |
795dc4fc | 1027 | |
9338ffe6 PB |
1028 | /* Interrupt functions can only use registers that have already been |
1029 | saved by the prologue, even if they would normally be | |
1030 | call-clobbered. */ | |
1031 | #define HARD_REGNO_RENAME_OK(SRC, DST) \ | |
1032 | (! IS_INTERRUPT (cfun->machine->func_type) || \ | |
6fb5fa3c | 1033 | df_regs_ever_live_p (DST)) |
35d965d5 RS |
1034 | \f |
1035 | /* Register and constant classes. */ | |
1036 | ||
3b684012 | 1037 | /* Register classes: used to be simple, just all ARM regs or all FPA regs |
d6a7951f | 1038 | Now that the Thumb is involved it has become more complicated. */ |
35d965d5 RS |
1039 | enum reg_class |
1040 | { | |
1041 | NO_REGS, | |
3b684012 | 1042 | FPA_REGS, |
9b6b54e2 | 1043 | CIRRUS_REGS, |
f1adb0a9 JB |
1044 | VFP_D0_D7_REGS, |
1045 | VFP_LO_REGS, | |
1046 | VFP_HI_REGS, | |
9b66ebb1 | 1047 | VFP_REGS, |
5a9335ef NC |
1048 | IWMMXT_GR_REGS, |
1049 | IWMMXT_REGS, | |
d5b7b3ae RE |
1050 | LO_REGS, |
1051 | STACK_REG, | |
1052 | BASE_REGS, | |
1053 | HI_REGS, | |
1054 | CC_REG, | |
9b66ebb1 | 1055 | VFPCC_REG, |
35d965d5 | 1056 | GENERAL_REGS, |
f5c630c3 | 1057 | CORE_REGS, |
35d965d5 RS |
1058 | ALL_REGS, |
1059 | LIM_REG_CLASSES | |
1060 | }; | |
1061 | ||
1062 | #define N_REG_CLASSES (int) LIM_REG_CLASSES | |
1063 | ||
d6b4baa4 | 1064 | /* Give names of register classes as strings for dump file. */ |
35d965d5 RS |
1065 | #define REG_CLASS_NAMES \ |
1066 | { \ | |
1067 | "NO_REGS", \ | |
3b684012 | 1068 | "FPA_REGS", \ |
9b6b54e2 | 1069 | "CIRRUS_REGS", \ |
f1adb0a9 JB |
1070 | "VFP_D0_D7_REGS", \ |
1071 | "VFP_LO_REGS", \ | |
1072 | "VFP_HI_REGS", \ | |
9b66ebb1 | 1073 | "VFP_REGS", \ |
5a9335ef NC |
1074 | "IWMMXT_GR_REGS", \ |
1075 | "IWMMXT_REGS", \ | |
d5b7b3ae RE |
1076 | "LO_REGS", \ |
1077 | "STACK_REG", \ | |
1078 | "BASE_REGS", \ | |
1079 | "HI_REGS", \ | |
1080 | "CC_REG", \ | |
5384443a | 1081 | "VFPCC_REG", \ |
35d965d5 | 1082 | "GENERAL_REGS", \ |
f5c630c3 | 1083 | "CORE_REGS", \ |
35d965d5 RS |
1084 | "ALL_REGS", \ |
1085 | } | |
1086 | ||
1087 | /* Define which registers fit in which classes. | |
1088 | This is an initializer for a vector of HARD_REG_SET | |
1089 | of length N_REG_CLASSES. */ | |
f1adb0a9 JB |
1090 | #define REG_CLASS_CONTENTS \ |
1091 | { \ | |
1092 | { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \ | |
1093 | { 0x00FF0000, 0x00000000, 0x00000000, 0x00000000 }, /* FPA_REGS */ \ | |
1094 | { 0xF8000000, 0x000007FF, 0x00000000, 0x00000000 }, /* CIRRUS_REGS */ \ | |
1095 | { 0x00000000, 0x80000000, 0x00007FFF, 0x00000000 }, /* VFP_D0_D7_REGS */ \ | |
1096 | { 0x00000000, 0x80000000, 0x7FFFFFFF, 0x00000000 }, /* VFP_LO_REGS */ \ | |
1097 | { 0x00000000, 0x00000000, 0x80000000, 0x7FFFFFFF }, /* VFP_HI_REGS */ \ | |
1098 | { 0x00000000, 0x80000000, 0xFFFFFFFF, 0x7FFFFFFF }, /* VFP_REGS */ \ | |
1099 | { 0x00000000, 0x00007800, 0x00000000, 0x00000000 }, /* IWMMXT_GR_REGS */ \ | |
1100 | { 0x00000000, 0x7FFF8000, 0x00000000, 0x00000000 }, /* IWMMXT_REGS */ \ | |
1101 | { 0x000000FF, 0x00000000, 0x00000000, 0x00000000 }, /* LO_REGS */ \ | |
1102 | { 0x00002000, 0x00000000, 0x00000000, 0x00000000 }, /* STACK_REG */ \ | |
1103 | { 0x000020FF, 0x00000000, 0x00000000, 0x00000000 }, /* BASE_REGS */ \ | |
f5c630c3 | 1104 | { 0x0000DF00, 0x00000000, 0x00000000, 0x00000000 }, /* HI_REGS */ \ |
f1adb0a9 JB |
1105 | { 0x01000000, 0x00000000, 0x00000000, 0x00000000 }, /* CC_REG */ \ |
1106 | { 0x00000000, 0x00000000, 0x00000000, 0x80000000 }, /* VFPCC_REG */ \ | |
565d018d JB |
1107 | { 0x0000DFFF, 0x00000000, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \ |
1108 | { 0x0000FFFF, 0x00000000, 0x00000000, 0x00000000 }, /* CORE_REGS */ \ | |
f1adb0a9 | 1109 | { 0xFAFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x7FFFFFFF } /* ALL_REGS */ \ |
35d965d5 | 1110 | } |
4b02997f | 1111 | |
f1adb0a9 JB |
1112 | /* Any of the VFP register classes. */ |
1113 | #define IS_VFP_CLASS(X) \ | |
1114 | ((X) == VFP_D0_D7_REGS || (X) == VFP_LO_REGS \ | |
1115 | || (X) == VFP_HI_REGS || (X) == VFP_REGS) | |
1116 | ||
35d965d5 RS |
1117 | /* The same information, inverted: |
1118 | Return the class number of the smallest class containing | |
1119 | reg number REGNO. This could be a conditional expression | |
1120 | or could index an array. */ | |
d5b7b3ae | 1121 | #define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO) |
35d965d5 | 1122 | |
9b66ebb1 | 1123 | /* FPA registers can't do subreg as all values are reformatted to internal |
75f6ec9a RS |
1124 | precision. In VFPv1, VFP registers could only be accessed in the mode |
1125 | they were set, so subregs would be invalid there too. However, we don't | |
1126 | support VFPv1 at the moment, and the restriction was lifted in VFPv2. */ | |
1127 | #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ | |
1128 | (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \ | |
1129 | ? reg_classes_intersect_p (FPA_REGS, (CLASS)) \ | |
9b66ebb1 | 1130 | : 0) |
75d2580c | 1131 | |
35d965d5 | 1132 | /* The class value for index registers, and the one for base regs. */ |
5b3e6663 | 1133 | #define INDEX_REG_CLASS (TARGET_THUMB1 ? LO_REGS : GENERAL_REGS) |
f5c630c3 | 1134 | #define BASE_REG_CLASS (TARGET_THUMB1 ? LO_REGS : CORE_REGS) |
d5b7b3ae | 1135 | |
b93a0fe6 | 1136 | /* For the Thumb the high registers cannot be used as base registers |
6bc82793 | 1137 | when addressing quantities in QI or HI mode; if we don't know the |
888d2cd6 | 1138 | mode, then we must be conservative. */ |
3dcc68a4 | 1139 | #define MODE_BASE_REG_CLASS(MODE) \ |
9adc580c | 1140 | (TARGET_ARM || (TARGET_THUMB2 && !optimize_size) ? CORE_REGS : \ |
888d2cd6 DJ |
1141 | (((MODE) == SImode) ? BASE_REGS : LO_REGS)) |
1142 | ||
1143 | /* For Thumb we can not support SP+reg addressing, so we return LO_REGS | |
1144 | instead of BASE_REGS. */ | |
1145 | #define MODE_BASE_REG_REG_CLASS(MODE) BASE_REG_CLASS | |
3dcc68a4 | 1146 | |
42db504c | 1147 | /* When this hook returns true for MODE, the compiler allows |
d5b7b3ae RE |
1148 | registers explicitly used in the rtl to be used as spill registers |
1149 | but prevents the compiler from extending the lifetime of these | |
d6b4baa4 | 1150 | registers. */ |
42db504c SB |
1151 | #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \ |
1152 | arm_small_register_classes_for_mode_p | |
35d965d5 | 1153 | |
d5b7b3ae RE |
1154 | /* Must leave BASE_REGS reloads alone */ |
1155 | #define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \ | |
1156 | ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \ | |
1157 | ? ((true_regnum (X) == -1 ? LO_REGS \ | |
1158 | : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \ | |
1159 | : NO_REGS)) \ | |
1160 | : NO_REGS) | |
1161 | ||
1162 | #define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \ | |
97358092 | 1163 | ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \ |
d5b7b3ae RE |
1164 | ? ((true_regnum (X) == -1 ? LO_REGS \ |
1165 | : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \ | |
1166 | : NO_REGS)) \ | |
1167 | : NO_REGS) | |
35d965d5 | 1168 | |
ff9940b0 RE |
1169 | /* Return the register class of a scratch register needed to copy IN into |
1170 | or out of a register in CLASS in MODE. If it can be done directly, | |
1171 | NO_REGS is returned. */ | |
d5b7b3ae | 1172 | #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \ |
fe2d934b | 1173 | /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \ |
9b66ebb1 | 1174 | ((TARGET_VFP && TARGET_HARD_FLOAT \ |
f1adb0a9 | 1175 | && IS_VFP_CLASS (CLASS)) \ |
fe2d934b PB |
1176 | ? coproc_secondary_reload_class (MODE, X, FALSE) \ |
1177 | : (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) \ | |
1178 | ? coproc_secondary_reload_class (MODE, X, TRUE) \ | |
5b3e6663 | 1179 | : TARGET_32BIT \ |
9b66ebb1 | 1180 | ? (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \ |
d5b7b3ae RE |
1181 | ? GENERAL_REGS : NO_REGS) \ |
1182 | : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X)) | |
f676971a | 1183 | |
d6b4baa4 | 1184 | /* If we need to load shorts byte-at-a-time, then we need a scratch. */ |
d5b7b3ae | 1185 | #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \ |
fe2d934b | 1186 | /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \ |
9b66ebb1 | 1187 | ((TARGET_VFP && TARGET_HARD_FLOAT \ |
f1adb0a9 | 1188 | && IS_VFP_CLASS (CLASS)) \ |
fe2d934b PB |
1189 | ? coproc_secondary_reload_class (MODE, X, FALSE) : \ |
1190 | (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) ? \ | |
1191 | coproc_secondary_reload_class (MODE, X, TRUE) : \ | |
9b6b54e2 | 1192 | /* Cannot load constants into Cirrus registers. */ \ |
9b66ebb1 | 1193 | (TARGET_MAVERICK && TARGET_HARD_FLOAT \ |
9b6b54e2 NC |
1194 | && (CLASS) == CIRRUS_REGS \ |
1195 | && (CONSTANT_P (X) || GET_CODE (X) == SYMBOL_REF)) \ | |
1196 | ? GENERAL_REGS : \ | |
5b3e6663 | 1197 | (TARGET_32BIT ? \ |
5a9335ef NC |
1198 | (((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \ |
1199 | && CONSTANT_P (X)) \ | |
1200 | ? GENERAL_REGS : \ | |
61f0ccff | 1201 | (((MODE) == HImode && ! arm_arch4 \ |
d5b7b3ae RE |
1202 | && (GET_CODE (X) == MEM \ |
1203 | || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \ | |
1204 | && true_regnum (X) == -1))) \ | |
1205 | ? GENERAL_REGS : NO_REGS) \ | |
9b6b54e2 | 1206 | : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X))) |
2ce9c1b9 | 1207 | |
6f734908 RE |
1208 | /* Try a machine-dependent way of reloading an illegitimate address |
1209 | operand. If we find one, push the reload and jump to WIN. This | |
1210 | macro is used in only one place: `find_reloads_address' in reload.c. | |
1211 | ||
1212 | For the ARM, we wish to handle large displacements off a base | |
1213 | register by splitting the addend across a MOV and the mem insn. | |
d5b7b3ae RE |
1214 | This can cut the number of reloads needed. */ |
1215 | #define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN) \ | |
1216 | do \ | |
1217 | { \ | |
0cd98787 JZ |
1218 | if (arm_legitimize_reload_address (&X, MODE, OPNUM, TYPE, IND)) \ |
1219 | goto WIN; \ | |
d5b7b3ae | 1220 | } \ |
62b10bbc | 1221 | while (0) |
6f734908 | 1222 | |
27847754 | 1223 | /* XXX If an HImode FP+large_offset address is converted to an HImode |
d5b7b3ae RE |
1224 | SP+large_offset address, then reload won't know how to fix it. It sees |
1225 | only that SP isn't valid for HImode, and so reloads the SP into an index | |
1226 | register, but the resulting address is still invalid because the offset | |
1227 | is too big. We fix it here instead by reloading the entire address. */ | |
1228 | /* We could probably achieve better results by defining PROMOTE_MODE to help | |
1229 | cope with the variances between the Thumb's signed and unsigned byte and | |
1230 | halfword load instructions. */ | |
5b3e6663 | 1231 | /* ??? This should be safe for thumb2, but we may be able to do better. */ |
a132dad6 RE |
1232 | #define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_L, WIN) \ |
1233 | do { \ | |
1234 | rtx new_x = thumb_legitimize_reload_address (&X, MODE, OPNUM, TYPE, IND_L); \ | |
1235 | if (new_x) \ | |
1236 | { \ | |
1237 | X = new_x; \ | |
1238 | goto WIN; \ | |
1239 | } \ | |
1240 | } while (0) | |
d5b7b3ae RE |
1241 | |
1242 | #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \ | |
1243 | if (TARGET_ARM) \ | |
1244 | ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \ | |
1245 | else \ | |
1246 | THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) | |
f676971a | 1247 | |
35d965d5 RS |
1248 | /* Return the maximum number of consecutive registers |
1249 | needed to represent mode MODE in a register of class CLASS. | |
3b684012 | 1250 | ARM regs are UNITS_PER_WORD bits while FPA regs can hold any FP mode */ |
35d965d5 | 1251 | #define CLASS_MAX_NREGS(CLASS, MODE) \ |
3b684012 | 1252 | (((CLASS) == FPA_REGS || (CLASS) == CIRRUS_REGS) ? 1 : ARM_NUM_REGS (MODE)) |
9b6b54e2 NC |
1253 | |
1254 | /* If defined, gives a class of registers that cannot be used as the | |
1255 | operand of a SUBREG that changes the mode of the object illegally. */ | |
35d965d5 RS |
1256 | \f |
1257 | /* Stack layout; function entry, exit and calling. */ | |
1258 | ||
1259 | /* Define this if pushing a word on the stack | |
1260 | makes the stack pointer a smaller address. */ | |
1261 | #define STACK_GROWS_DOWNWARD 1 | |
1262 | ||
a4d05547 | 1263 | /* Define this to nonzero if the nominal address of the stack frame |
35d965d5 RS |
1264 | is at the high-address end of the local variables; |
1265 | that is, each additional local variable allocated | |
1266 | goes at a more negative offset in the frame. */ | |
1267 | #define FRAME_GROWS_DOWNWARD 1 | |
1268 | ||
a2503645 RS |
1269 | /* The amount of scratch space needed by _interwork_{r7,r11}_call_via_rN(). |
1270 | When present, it is one word in size, and sits at the top of the frame, | |
1271 | between the soft frame pointer and either r7 or r11. | |
1272 | ||
1273 | We only need _interwork_rM_call_via_rN() for -mcaller-super-interworking, | |
1274 | and only then if some outgoing arguments are passed on the stack. It would | |
1275 | be tempting to also check whether the stack arguments are passed by indirect | |
1276 | calls, but there seems to be no reason in principle why a post-reload pass | |
1277 | couldn't convert a direct call into an indirect one. */ | |
1278 | #define CALLER_INTERWORKING_SLOT_SIZE \ | |
1279 | (TARGET_CALLER_INTERWORKING \ | |
38173d38 | 1280 | && crtl->outgoing_args_size != 0 \ |
a2503645 RS |
1281 | ? UNITS_PER_WORD : 0) |
1282 | ||
35d965d5 RS |
1283 | /* Offset within stack frame to start allocating local variables at. |
1284 | If FRAME_GROWS_DOWNWARD, this is the offset to the END of the | |
1285 | first local allocated. Otherwise, it is the offset to the BEGINNING | |
1286 | of the first local allocated. */ | |
1287 | #define STARTING_FRAME_OFFSET 0 | |
1288 | ||
1289 | /* If we generate an insn to push BYTES bytes, | |
1290 | this says how many the stack pointer really advances by. */ | |
d5b7b3ae | 1291 | /* The push insns do not do this rounding implicitly. |
d6b4baa4 | 1292 | So don't define this. */ |
0c2ca901 | 1293 | /* #define PUSH_ROUNDING(NPUSHED) ROUND_UP_WORD (NPUSHED) */ |
18543a22 ILT |
1294 | |
1295 | /* Define this if the maximum size of all the outgoing args is to be | |
1296 | accumulated and pushed during the prologue. The amount can be | |
38173d38 | 1297 | found in the variable crtl->outgoing_args_size. */ |
6cfc7210 | 1298 | #define ACCUMULATE_OUTGOING_ARGS 1 |
35d965d5 RS |
1299 | |
1300 | /* Offset of first parameter from the argument pointer register value. */ | |
d5b7b3ae | 1301 | #define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0) |
35d965d5 | 1302 | |
9f7bf991 RE |
1303 | /* Amount of memory needed for an untyped call to save all possible return |
1304 | registers. */ | |
1305 | #define APPLY_RESULT_SIZE arm_apply_result_size() | |
1306 | ||
11c1a207 RE |
1307 | /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return |
1308 | values must be in memory. On the ARM, they need only do so if larger | |
d6b4baa4 | 1309 | than a word, or if they contain elements offset from zero in the struct. */ |
11c1a207 RE |
1310 | #define DEFAULT_PCC_STRUCT_RETURN 0 |
1311 | ||
6d3d9133 | 1312 | /* These bits describe the different types of function supported |
112cdef5 | 1313 | by the ARM backend. They are exclusive. i.e. a function cannot be both a |
6d3d9133 NC |
1314 | normal function and an interworked function, for example. Knowing the |
1315 | type of a function is important for determining its prologue and | |
1316 | epilogue sequences. | |
1317 | Note value 7 is currently unassigned. Also note that the interrupt | |
1318 | function types all have bit 2 set, so that they can be tested for easily. | |
1319 | Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the | |
4912a07c | 1320 | machine_function structure is initialized (to zero) func_type will |
6d3d9133 NC |
1321 | default to unknown. This will force the first use of arm_current_func_type |
1322 | to call arm_compute_func_type. */ | |
1323 | #define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */ | |
1324 | #define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */ | |
1325 | #define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */ | |
6d3d9133 NC |
1326 | #define ARM_FT_ISR 4 /* An interrupt service routine. */ |
1327 | #define ARM_FT_FIQ 5 /* A fast interrupt service routine. */ | |
1328 | #define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */ | |
1329 | ||
1330 | #define ARM_FT_TYPE_MASK ((1 << 3) - 1) | |
1331 | ||
1332 | /* In addition functions can have several type modifiers, | |
1333 | outlined by these bit masks: */ | |
1334 | #define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */ | |
1335 | #define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */ | |
1336 | #define ARM_FT_VOLATILE (1 << 4) /* Does not return. */ | |
d6b4baa4 | 1337 | #define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */ |
5b3e6663 | 1338 | #define ARM_FT_STACKALIGN (1 << 6) /* Called with misaligned stack. */ |
6d3d9133 NC |
1339 | |
1340 | /* Some macros to test these flags. */ | |
1341 | #define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK) | |
1342 | #define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT) | |
1343 | #define IS_VOLATILE(t) (t & ARM_FT_VOLATILE) | |
1344 | #define IS_NAKED(t) (t & ARM_FT_NAKED) | |
1345 | #define IS_NESTED(t) (t & ARM_FT_NESTED) | |
5b3e6663 | 1346 | #define IS_STACKALIGN(t) (t & ARM_FT_STACKALIGN) |
6d3d9133 | 1347 | |
5848830f PB |
1348 | |
1349 | /* Structure used to hold the function stack frame layout. Offsets are | |
1350 | relative to the stack pointer on function entry. Positive offsets are | |
1351 | in the direction of stack growth. | |
1352 | Only soft_frame is used in thumb mode. */ | |
1353 | ||
d1b38208 | 1354 | typedef struct GTY(()) arm_stack_offsets |
5848830f PB |
1355 | { |
1356 | int saved_args; /* ARG_POINTER_REGNUM. */ | |
1357 | int frame; /* ARM_HARD_FRAME_POINTER_REGNUM. */ | |
1358 | int saved_regs; | |
1359 | int soft_frame; /* FRAME_POINTER_REGNUM. */ | |
2591db65 | 1360 | int locals_base; /* THUMB_HARD_FRAME_POINTER_REGNUM. */ |
5848830f | 1361 | int outgoing_args; /* STACK_POINTER_REGNUM. */ |
954954d1 | 1362 | unsigned int saved_regs_mask; |
5848830f PB |
1363 | } |
1364 | arm_stack_offsets; | |
1365 | ||
906668bb | 1366 | #ifndef GENERATOR_FILE |
6d3d9133 NC |
1367 | /* A C structure for machine-specific, per-function data. |
1368 | This is added to the cfun structure. */ | |
d1b38208 | 1369 | typedef struct GTY(()) machine_function |
d5b7b3ae | 1370 | { |
6bc82793 | 1371 | /* Additional stack adjustment in __builtin_eh_throw. */ |
e2500fed | 1372 | rtx eh_epilogue_sp_ofs; |
d5b7b3ae RE |
1373 | /* Records if LR has to be saved for far jumps. */ |
1374 | int far_jump_used; | |
1375 | /* Records if ARG_POINTER was ever live. */ | |
1376 | int arg_pointer_live; | |
6f7ebcbb NC |
1377 | /* Records if the save of LR has been eliminated. */ |
1378 | int lr_save_eliminated; | |
0977774b | 1379 | /* The size of the stack frame. Only valid after reload. */ |
5848830f | 1380 | arm_stack_offsets stack_offsets; |
6d3d9133 NC |
1381 | /* Records the type of the current function. */ |
1382 | unsigned long func_type; | |
3cb66fd7 NC |
1383 | /* Record if the function has a variable argument list. */ |
1384 | int uses_anonymous_args; | |
5a9335ef NC |
1385 | /* Records if sibcalls are blocked because an argument |
1386 | register is needed to preserve stack alignment. */ | |
1387 | int sibcall_blocked; | |
020a4035 RE |
1388 | /* The PIC register for this function. This might be a pseudo. */ |
1389 | rtx pic_reg; | |
b12a00f1 | 1390 | /* Labels for per-function Thumb call-via stubs. One per potential calling |
57ecec57 PB |
1391 | register. We can never call via LR or PC. We can call via SP if a |
1392 | trampoline happens to be on the top of the stack. */ | |
1393 | rtx call_via[14]; | |
934c2060 RR |
1394 | /* Set to 1 when a return insn is output, this means that the epilogue |
1395 | is not needed. */ | |
1396 | int return_used_this_function; | |
906668bb BS |
1397 | /* When outputting Thumb-1 code, record the last insn that provides |
1398 | information about condition codes, and the comparison operands. */ | |
1399 | rtx thumb1_cc_insn; | |
1400 | rtx thumb1_cc_op0; | |
1401 | rtx thumb1_cc_op1; | |
1402 | /* Also record the CC mode that is supported. */ | |
1403 | enum machine_mode thumb1_cc_mode; | |
6d3d9133 NC |
1404 | } |
1405 | machine_function; | |
906668bb | 1406 | #endif |
d5b7b3ae | 1407 | |
b12a00f1 | 1408 | /* As in the machine_function, a global set of call-via labels, for code |
d6b5193b | 1409 | that is in text_section. */ |
57ecec57 | 1410 | extern GTY(()) rtx thumb_call_via_label[14]; |
b12a00f1 | 1411 | |
390b17c2 RE |
1412 | /* The number of potential ways of assigning to a co-processor. */ |
1413 | #define ARM_NUM_COPROC_SLOTS 1 | |
1414 | ||
1415 | /* Enumeration of procedure calling standard variants. We don't really | |
1416 | support all of these yet. */ | |
1417 | enum arm_pcs | |
1418 | { | |
1419 | ARM_PCS_AAPCS, /* Base standard AAPCS. */ | |
1420 | ARM_PCS_AAPCS_VFP, /* Use VFP registers for floating point values. */ | |
1421 | ARM_PCS_AAPCS_IWMMXT, /* Use iWMMXT registers for vectors. */ | |
1422 | /* This must be the last AAPCS variant. */ | |
1423 | ARM_PCS_AAPCS_LOCAL, /* Private call within this compilation unit. */ | |
1424 | ARM_PCS_ATPCS, /* ATPCS. */ | |
1425 | ARM_PCS_APCS, /* APCS (legacy Linux etc). */ | |
1426 | ARM_PCS_UNKNOWN | |
1427 | }; | |
1428 | ||
12ffc7d5 CLT |
1429 | /* Default procedure calling standard of current compilation unit. */ |
1430 | extern enum arm_pcs arm_pcs_default; | |
1431 | ||
82e9d970 | 1432 | /* A C type for declaring a variable that is used as the first argument of |
390b17c2 | 1433 | `FUNCTION_ARG' and other related values. */ |
82e9d970 PB |
1434 | typedef struct |
1435 | { | |
d5b7b3ae | 1436 | /* This is the number of registers of arguments scanned so far. */ |
82e9d970 | 1437 | int nregs; |
5a9335ef NC |
1438 | /* This is the number of iWMMXt register arguments scanned so far. */ |
1439 | int iwmmxt_nregs; | |
1440 | int named_count; | |
1441 | int nargs; | |
390b17c2 RE |
1442 | /* Which procedure call variant to use for this call. */ |
1443 | enum arm_pcs pcs_variant; | |
1444 | ||
1445 | /* AAPCS related state tracking. */ | |
1446 | int aapcs_arg_processed; /* No need to lay out this argument again. */ | |
1447 | int aapcs_cprc_slot; /* Index of co-processor rules to handle | |
1448 | this argument, or -1 if using core | |
1449 | registers. */ | |
1450 | int aapcs_ncrn; | |
1451 | int aapcs_next_ncrn; | |
1452 | rtx aapcs_reg; /* Register assigned to this argument. */ | |
1453 | int aapcs_partial; /* How many bytes are passed in regs (if | |
1454 | split between core regs and stack. | |
1455 | Zero otherwise. */ | |
1456 | int aapcs_cprc_failed[ARM_NUM_COPROC_SLOTS]; | |
1457 | int can_split; /* Argument can be split between core regs | |
1458 | and the stack. */ | |
1459 | /* Private data for tracking VFP register allocation */ | |
1460 | unsigned aapcs_vfp_regs_free; | |
1461 | unsigned aapcs_vfp_reg_alloc; | |
1462 | int aapcs_vfp_rcount; | |
46107b99 | 1463 | MACHMODE aapcs_vfp_rmode; |
d5b7b3ae | 1464 | } CUMULATIVE_ARGS; |
82e9d970 | 1465 | |
866af8a9 JB |
1466 | #define FUNCTION_ARG_PADDING(MODE, TYPE) \ |
1467 | (arm_pad_arg_upward (MODE, TYPE) ? upward : downward) | |
1468 | ||
1469 | #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \ | |
1470 | (arm_pad_reg_upward (MODE, TYPE, FIRST) ? upward : downward) | |
1471 | ||
1472 | /* For AAPCS, padding should never be below the argument. For other ABIs, | |
1473 | * mimic the default. */ | |
1474 | #define PAD_VARARGS_DOWN \ | |
1475 | ((TARGET_AAPCS_BASED) ? 0 : BYTES_BIG_ENDIAN) | |
1476 | ||
35d965d5 RS |
1477 | /* Initialize a variable CUM of type CUMULATIVE_ARGS |
1478 | for a call to a function whose data type is FNTYPE. | |
1479 | For a library call, FNTYPE is 0. | |
1480 | On the ARM, the offset starts at 0. */ | |
0f6937fe | 1481 | #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ |
563a317a | 1482 | arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL)) |
35d965d5 | 1483 | |
35d965d5 RS |
1484 | /* 1 if N is a possible register number for function argument passing. |
1485 | On the ARM, r0-r3 are used to pass args. */ | |
390b17c2 RE |
1486 | #define FUNCTION_ARG_REGNO_P(REGNO) \ |
1487 | (IN_RANGE ((REGNO), 0, 3) \ | |
1488 | || (TARGET_AAPCS_BASED && TARGET_VFP && TARGET_HARD_FLOAT \ | |
1489 | && IN_RANGE ((REGNO), FIRST_VFP_REGNUM, FIRST_VFP_REGNUM + 15)) \ | |
1490 | || (TARGET_IWMMXT_ABI \ | |
5848830f | 1491 | && IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9))) |
35d965d5 | 1492 | |
f99fce0c | 1493 | \f |
afef3d7a | 1494 | /* If your target environment doesn't prefix user functions with an |
96a3900d | 1495 | underscore, you may wish to re-define this to prevent any conflicts. */ |
afef3d7a NC |
1496 | #ifndef ARM_MCOUNT_NAME |
1497 | #define ARM_MCOUNT_NAME "*mcount" | |
1498 | #endif | |
1499 | ||
1500 | /* Call the function profiler with a given profile label. The Acorn | |
1501 | compiler puts this BEFORE the prolog but gcc puts it afterwards. | |
1502 | On the ARM the full profile code will look like: | |
1503 | .data | |
1504 | LP1 | |
1505 | .word 0 | |
1506 | .text | |
1507 | mov ip, lr | |
1508 | bl mcount | |
1509 | .word LP1 | |
1510 | ||
1511 | profile_function() in final.c outputs the .data section, FUNCTION_PROFILER | |
1512 | will output the .text section. | |
1513 | ||
1514 | The ``mov ip,lr'' seems like a good idea to stick with cc convention. | |
59be6073 AN |
1515 | ``prof'' doesn't seem to mind about this! |
1516 | ||
1517 | Note - this version of the code is designed to work in both ARM and | |
1518 | Thumb modes. */ | |
be393ecf | 1519 | #ifndef ARM_FUNCTION_PROFILER |
d5b7b3ae | 1520 | #define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \ |
6cfc7210 NC |
1521 | { \ |
1522 | char temp[20]; \ | |
1523 | rtx sym; \ | |
1524 | \ | |
dd18ae56 | 1525 | asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \ |
d5b7b3ae | 1526 | IP_REGNUM, LR_REGNUM); \ |
6cfc7210 NC |
1527 | assemble_name (STREAM, ARM_MCOUNT_NAME); \ |
1528 | fputc ('\n', STREAM); \ | |
1529 | ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \ | |
f1c25d3b | 1530 | sym = gen_rtx_SYMBOL_REF (Pmode, temp); \ |
301d03af | 1531 | assemble_aligned_integer (UNITS_PER_WORD, sym); \ |
35d965d5 | 1532 | } |
be393ecf | 1533 | #endif |
35d965d5 | 1534 | |
59be6073 | 1535 | #ifdef THUMB_FUNCTION_PROFILER |
d5b7b3ae RE |
1536 | #define FUNCTION_PROFILER(STREAM, LABELNO) \ |
1537 | if (TARGET_ARM) \ | |
1538 | ARM_FUNCTION_PROFILER (STREAM, LABELNO) \ | |
1539 | else \ | |
1540 | THUMB_FUNCTION_PROFILER (STREAM, LABELNO) | |
59be6073 AN |
1541 | #else |
1542 | #define FUNCTION_PROFILER(STREAM, LABELNO) \ | |
1543 | ARM_FUNCTION_PROFILER (STREAM, LABELNO) | |
1544 | #endif | |
d5b7b3ae | 1545 | |
35d965d5 RS |
1546 | /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, |
1547 | the stack pointer does not matter. The value is tested only in | |
1548 | functions that have frame pointers. | |
1549 | No definition is equivalent to always zero. | |
1550 | ||
1551 | On the ARM, the function epilogue recovers the stack pointer from the | |
1552 | frame. */ | |
1553 | #define EXIT_IGNORE_STACK 1 | |
1554 | ||
6fb5fa3c | 1555 | #define EPILOGUE_USES(REGNO) ((REGNO) == LR_REGNUM) |
c7861455 | 1556 | |
35d965d5 RS |
1557 | /* Determine if the epilogue should be output as RTL. |
1558 | You should override this if you define FUNCTION_EXTRA_EPILOGUE. */ | |
d5b7b3ae | 1559 | #define USE_RETURN_INSN(ISCOND) \ |
7c19c715 | 1560 | (TARGET_32BIT ? use_return_insn (ISCOND, NULL) : 0) |
ff9940b0 RE |
1561 | |
1562 | /* Definitions for register eliminations. | |
1563 | ||
1564 | This is an array of structures. Each structure initializes one pair | |
1565 | of eliminable registers. The "from" register number is given first, | |
1566 | followed by "to". Eliminations of the same "from" register are listed | |
1567 | in order of preference. | |
1568 | ||
1569 | We have two registers that can be eliminated on the ARM. First, the | |
1570 | arg pointer register can often be eliminated in favor of the stack | |
1571 | pointer register. Secondly, the pseudo frame pointer register can always | |
1572 | be eliminated; it is replaced with either the stack or the real frame | |
d5b7b3ae | 1573 | pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM |
d6a7951f | 1574 | because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */ |
ff9940b0 | 1575 | |
d5b7b3ae RE |
1576 | #define ELIMINABLE_REGS \ |
1577 | {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\ | |
1578 | { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\ | |
1579 | { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\ | |
1580 | { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\ | |
1581 | { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\ | |
1582 | { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\ | |
1583 | { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }} | |
ff9940b0 | 1584 | |
d5b7b3ae RE |
1585 | /* Define the offset between two registers, one to be eliminated, and the |
1586 | other its replacement, at the start of a routine. */ | |
d5b7b3ae RE |
1587 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ |
1588 | if (TARGET_ARM) \ | |
5848830f | 1589 | (OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \ |
d5b7b3ae | 1590 | else \ |
5848830f PB |
1591 | (OFFSET) = thumb_compute_initial_elimination_offset (FROM, TO) |
1592 | ||
d5b7b3ae RE |
1593 | /* Special case handling of the location of arguments passed on the stack. */ |
1594 | #define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr) | |
f676971a | 1595 | |
d5b7b3ae RE |
1596 | /* Initialize data used by insn expanders. This is called from insn_emit, |
1597 | once for every function before code is generated. */ | |
1598 | #define INIT_EXPANDERS arm_init_expanders () | |
1599 | ||
35d965d5 | 1600 | /* Length in units of the trampoline for entering a nested function. */ |
5b3e6663 | 1601 | #define TRAMPOLINE_SIZE (TARGET_32BIT ? 16 : 20) |
35d965d5 | 1602 | |
006946e4 JM |
1603 | /* Alignment required for a trampoline in bits. */ |
1604 | #define TRAMPOLINE_ALIGNMENT 32 | |
35d965d5 RS |
1605 | \f |
1606 | /* Addressing modes, and classification of registers for them. */ | |
3cd45774 | 1607 | #define HAVE_POST_INCREMENT 1 |
5b3e6663 PB |
1608 | #define HAVE_PRE_INCREMENT TARGET_32BIT |
1609 | #define HAVE_POST_DECREMENT TARGET_32BIT | |
1610 | #define HAVE_PRE_DECREMENT TARGET_32BIT | |
1611 | #define HAVE_PRE_MODIFY_DISP TARGET_32BIT | |
1612 | #define HAVE_POST_MODIFY_DISP TARGET_32BIT | |
1613 | #define HAVE_PRE_MODIFY_REG TARGET_32BIT | |
1614 | #define HAVE_POST_MODIFY_REG TARGET_32BIT | |
35d965d5 | 1615 | |
8875e939 RR |
1616 | enum arm_auto_incmodes |
1617 | { | |
1618 | ARM_POST_INC, | |
1619 | ARM_PRE_INC, | |
1620 | ARM_POST_DEC, | |
1621 | ARM_PRE_DEC | |
1622 | }; | |
1623 | ||
1624 | #define ARM_AUTOINC_VALID_FOR_MODE_P(mode, code) \ | |
1625 | (TARGET_32BIT && arm_autoinc_modes_ok_p (mode, code)) | |
1626 | #define USE_LOAD_POST_INCREMENT(mode) \ | |
1627 | ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_POST_INC) | |
1628 | #define USE_LOAD_PRE_INCREMENT(mode) \ | |
1629 | ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_PRE_INC) | |
1630 | #define USE_LOAD_POST_DECREMENT(mode) \ | |
1631 | ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_POST_DEC) | |
1632 | #define USE_LOAD_PRE_DECREMENT(mode) \ | |
1633 | ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_PRE_DEC) | |
1634 | ||
1635 | #define USE_STORE_PRE_DECREMENT(mode) USE_LOAD_PRE_DECREMENT(mode) | |
1636 | #define USE_STORE_PRE_INCREMENT(mode) USE_LOAD_PRE_INCREMENT(mode) | |
1637 | #define USE_STORE_POST_DECREMENT(mode) USE_LOAD_POST_DECREMENT(mode) | |
1638 | #define USE_STORE_POST_INCREMENT(mode) USE_LOAD_POST_INCREMENT(mode) | |
1639 | ||
35d965d5 RS |
1640 | /* Macros to check register numbers against specific register classes. */ |
1641 | ||
1642 | /* These assume that REGNO is a hard or pseudo reg number. | |
1643 | They give nonzero only if REGNO is a hard reg of the suitable class | |
1644 | or a pseudo reg currently allocated to a suitable hard reg. | |
1645 | Since they use reg_renumber, they are safe only once reg_renumber | |
d6b4baa4 | 1646 | has been allocated, which happens in local-alloc.c. */ |
d5b7b3ae RE |
1647 | #define TEST_REGNO(R, TEST, VALUE) \ |
1648 | ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE)) | |
1649 | ||
5b3e6663 | 1650 | /* Don't allow the pc to be used. */ |
f1008e52 RE |
1651 | #define ARM_REGNO_OK_FOR_BASE_P(REGNO) \ |
1652 | (TEST_REGNO (REGNO, <, PC_REGNUM) \ | |
1653 | || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \ | |
1654 | || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM)) | |
1655 | ||
5b3e6663 | 1656 | #define THUMB1_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \ |
f1008e52 RE |
1657 | (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \ |
1658 | || (GET_MODE_SIZE (MODE) >= 4 \ | |
1659 | && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM))) | |
1660 | ||
1661 | #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \ | |
5b3e6663 PB |
1662 | (TARGET_THUMB1 \ |
1663 | ? THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \ | |
f1008e52 RE |
1664 | : ARM_REGNO_OK_FOR_BASE_P (REGNO)) |
1665 | ||
888d2cd6 DJ |
1666 | /* Nonzero if X can be the base register in a reg+reg addressing mode. |
1667 | For Thumb, we can not use SP + reg, so reject SP. */ | |
1668 | #define REGNO_MODE_OK_FOR_REG_BASE_P(X, MODE) \ | |
f5c630c3 | 1669 | REGNO_MODE_OK_FOR_BASE_P (X, QImode) |
888d2cd6 | 1670 | |
f1008e52 RE |
1671 | /* For ARM code, we don't care about the mode, but for Thumb, the index |
1672 | must be suitable for use in a QImode load. */ | |
d5b7b3ae | 1673 | #define REGNO_OK_FOR_INDEX_P(REGNO) \ |
f5c630c3 PB |
1674 | (REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode) \ |
1675 | && !TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)) | |
35d965d5 RS |
1676 | |
1677 | /* Maximum number of registers that can appear in a valid memory address. | |
d6b4baa4 | 1678 | Shifts in addresses can't be by a register. */ |
ff9940b0 | 1679 | #define MAX_REGS_PER_ADDRESS 2 |
35d965d5 RS |
1680 | |
1681 | /* Recognize any constant value that is a valid address. */ | |
1682 | /* XXX We can address any constant, eventually... */ | |
5b3e6663 | 1683 | /* ??? Should the TARGET_ARM here also apply to thumb2? */ |
008cf58a RE |
1684 | #define CONSTANT_ADDRESS_P(X) \ |
1685 | (GET_CODE (X) == SYMBOL_REF \ | |
1686 | && (CONSTANT_POOL_ADDRESS_P (X) \ | |
d5b7b3ae | 1687 | || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X)))) |
35d965d5 | 1688 | |
8426b956 RS |
1689 | /* True if SYMBOL + OFFSET constants must refer to something within |
1690 | SYMBOL's section. */ | |
1691 | #define ARM_OFFSETS_MUST_BE_WITHIN_SECTIONS_P 0 | |
1692 | ||
571191af PB |
1693 | /* Nonzero if all target requires all absolute relocations be R_ARM_ABS32. */ |
1694 | #ifndef TARGET_DEFAULT_WORD_RELOCATIONS | |
1695 | #define TARGET_DEFAULT_WORD_RELOCATIONS 0 | |
1696 | #endif | |
1697 | ||
c27ba912 DM |
1698 | #ifndef SUBTARGET_NAME_ENCODING_LENGTHS |
1699 | #define SUBTARGET_NAME_ENCODING_LENGTHS | |
1700 | #endif | |
1701 | ||
6bc82793 | 1702 | /* This is a C fragment for the inside of a switch statement. |
c27ba912 DM |
1703 | Each case label should return the number of characters to |
1704 | be stripped from the start of a function's name, if that | |
1705 | name starts with the indicated character. */ | |
1706 | #define ARM_NAME_ENCODING_LENGTHS \ | |
00fdafef | 1707 | case '*': return 1; \ |
f676971a | 1708 | SUBTARGET_NAME_ENCODING_LENGTHS |
c27ba912 | 1709 | |
c27ba912 DM |
1710 | /* This is how to output a reference to a user-level label named NAME. |
1711 | `assemble_name' uses this. */ | |
e5951263 | 1712 | #undef ASM_OUTPUT_LABELREF |
c27ba912 | 1713 | #define ASM_OUTPUT_LABELREF(FILE, NAME) \ |
e1944073 | 1714 | arm_asm_output_labelref (FILE, NAME) |
c27ba912 | 1715 | |
7a085dce | 1716 | /* Output IT instructions for conditionally executed Thumb-2 instructions. */ |
5b3e6663 PB |
1717 | #define ASM_OUTPUT_OPCODE(STREAM, PTR) \ |
1718 | if (TARGET_THUMB2) \ | |
1719 | thumb2_asm_output_opcode (STREAM); | |
1720 | ||
7abc66b1 JB |
1721 | /* The EABI specifies that constructors should go in .init_array. |
1722 | Other targets use .ctors for compatibility. */ | |
88c6057f | 1723 | #ifndef ARM_EABI_CTORS_SECTION_OP |
7abc66b1 JB |
1724 | #define ARM_EABI_CTORS_SECTION_OP \ |
1725 | "\t.section\t.init_array,\"aw\",%init_array" | |
88c6057f MM |
1726 | #endif |
1727 | #ifndef ARM_EABI_DTORS_SECTION_OP | |
7abc66b1 JB |
1728 | #define ARM_EABI_DTORS_SECTION_OP \ |
1729 | "\t.section\t.fini_array,\"aw\",%fini_array" | |
88c6057f | 1730 | #endif |
7abc66b1 JB |
1731 | #define ARM_CTORS_SECTION_OP \ |
1732 | "\t.section\t.ctors,\"aw\",%progbits" | |
1733 | #define ARM_DTORS_SECTION_OP \ | |
1734 | "\t.section\t.dtors,\"aw\",%progbits" | |
1735 | ||
1736 | /* Define CTORS_SECTION_ASM_OP. */ | |
1737 | #undef CTORS_SECTION_ASM_OP | |
1738 | #undef DTORS_SECTION_ASM_OP | |
1739 | #ifndef IN_LIBGCC2 | |
1740 | # define CTORS_SECTION_ASM_OP \ | |
1741 | (TARGET_AAPCS_BASED ? ARM_EABI_CTORS_SECTION_OP : ARM_CTORS_SECTION_OP) | |
1742 | # define DTORS_SECTION_ASM_OP \ | |
1743 | (TARGET_AAPCS_BASED ? ARM_EABI_DTORS_SECTION_OP : ARM_DTORS_SECTION_OP) | |
1744 | #else /* !defined (IN_LIBGCC2) */ | |
1745 | /* In libgcc, CTORS_SECTION_ASM_OP must be a compile-time constant, | |
1746 | so we cannot use the definition above. */ | |
1747 | # ifdef __ARM_EABI__ | |
1748 | /* The .ctors section is not part of the EABI, so we do not define | |
1749 | CTORS_SECTION_ASM_OP when in libgcc; that prevents crtstuff | |
1750 | from trying to use it. We do define it when doing normal | |
1751 | compilation, as .init_array can be used instead of .ctors. */ | |
1752 | /* There is no need to emit begin or end markers when using | |
1753 | init_array; the dynamic linker will compute the size of the | |
1754 | array itself based on special symbols created by the static | |
1755 | linker. However, we do need to arrange to set up | |
1756 | exception-handling here. */ | |
1757 | # define CTOR_LIST_BEGIN asm (ARM_EABI_CTORS_SECTION_OP) | |
1758 | # define CTOR_LIST_END /* empty */ | |
1759 | # define DTOR_LIST_BEGIN asm (ARM_EABI_DTORS_SECTION_OP) | |
1760 | # define DTOR_LIST_END /* empty */ | |
1761 | # else /* !defined (__ARM_EABI__) */ | |
1762 | # define CTORS_SECTION_ASM_OP ARM_CTORS_SECTION_OP | |
1763 | # define DTORS_SECTION_ASM_OP ARM_DTORS_SECTION_OP | |
1764 | # endif /* !defined (__ARM_EABI__) */ | |
1765 | #endif /* !defined (IN_LIBCC2) */ | |
1766 | ||
1e731102 MM |
1767 | /* True if the operating system can merge entities with vague linkage |
1768 | (e.g., symbols in COMDAT group) during dynamic linking. */ | |
1769 | #ifndef TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P | |
1770 | #define TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P true | |
1771 | #endif | |
1772 | ||
617a1b71 PB |
1773 | #define ARM_OUTPUT_FN_UNWIND(F, PROLOGUE) arm_output_fn_unwind (F, PROLOGUE) |
1774 | ||
35d965d5 RS |
1775 | /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx |
1776 | and check its validity for a certain class. | |
1777 | We have two alternate definitions for each of them. | |
1778 | The usual definition accepts all pseudo regs; the other rejects | |
1779 | them unless they have been allocated suitable hard regs. | |
5b3e6663 | 1780 | The symbol REG_OK_STRICT causes the latter definition to be used. |
7a085dce | 1781 | Thumb-2 has the same restrictions as arm. */ |
35d965d5 | 1782 | #ifndef REG_OK_STRICT |
ff9940b0 | 1783 | |
f1008e52 RE |
1784 | #define ARM_REG_OK_FOR_BASE_P(X) \ |
1785 | (REGNO (X) <= LAST_ARM_REGNUM \ | |
1786 | || REGNO (X) >= FIRST_PSEUDO_REGISTER \ | |
1787 | || REGNO (X) == FRAME_POINTER_REGNUM \ | |
1788 | || REGNO (X) == ARG_POINTER_REGNUM) | |
ff9940b0 | 1789 | |
f5c630c3 PB |
1790 | #define ARM_REG_OK_FOR_INDEX_P(X) \ |
1791 | ((REGNO (X) <= LAST_ARM_REGNUM \ | |
1792 | && REGNO (X) != STACK_POINTER_REGNUM) \ | |
1793 | || REGNO (X) >= FIRST_PSEUDO_REGISTER \ | |
1794 | || REGNO (X) == FRAME_POINTER_REGNUM \ | |
1795 | || REGNO (X) == ARG_POINTER_REGNUM) | |
1796 | ||
5b3e6663 | 1797 | #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \ |
f1008e52 RE |
1798 | (REGNO (X) <= LAST_LO_REGNUM \ |
1799 | || REGNO (X) >= FIRST_PSEUDO_REGISTER \ | |
1800 | || (GET_MODE_SIZE (MODE) >= 4 \ | |
1801 | && (REGNO (X) == STACK_POINTER_REGNUM \ | |
1802 | || (X) == hard_frame_pointer_rtx \ | |
1803 | || (X) == arg_pointer_rtx))) | |
ff9940b0 | 1804 | |
76a318e9 RE |
1805 | #define REG_STRICT_P 0 |
1806 | ||
d5b7b3ae | 1807 | #else /* REG_OK_STRICT */ |
ff9940b0 | 1808 | |
f1008e52 RE |
1809 | #define ARM_REG_OK_FOR_BASE_P(X) \ |
1810 | ARM_REGNO_OK_FOR_BASE_P (REGNO (X)) | |
ff9940b0 | 1811 | |
f5c630c3 PB |
1812 | #define ARM_REG_OK_FOR_INDEX_P(X) \ |
1813 | ARM_REGNO_OK_FOR_INDEX_P (REGNO (X)) | |
1814 | ||
5b3e6663 PB |
1815 | #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \ |
1816 | THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE) | |
ff9940b0 | 1817 | |
76a318e9 RE |
1818 | #define REG_STRICT_P 1 |
1819 | ||
d5b7b3ae | 1820 | #endif /* REG_OK_STRICT */ |
f1008e52 RE |
1821 | |
1822 | /* Now define some helpers in terms of the above. */ | |
1823 | ||
1824 | #define REG_MODE_OK_FOR_BASE_P(X, MODE) \ | |
5b3e6663 PB |
1825 | (TARGET_THUMB1 \ |
1826 | ? THUMB1_REG_MODE_OK_FOR_BASE_P (X, MODE) \ | |
f1008e52 RE |
1827 | : ARM_REG_OK_FOR_BASE_P (X)) |
1828 | ||
5b3e6663 | 1829 | /* For 16-bit Thumb, a valid index register is anything that can be used in |
f1008e52 | 1830 | a byte load instruction. */ |
5b3e6663 PB |
1831 | #define THUMB1_REG_OK_FOR_INDEX_P(X) \ |
1832 | THUMB1_REG_MODE_OK_FOR_BASE_P (X, QImode) | |
f1008e52 RE |
1833 | |
1834 | /* Nonzero if X is a hard reg that can be used as an index | |
1835 | or if it is a pseudo reg. On the Thumb, the stack pointer | |
1836 | is not suitable. */ | |
1837 | #define REG_OK_FOR_INDEX_P(X) \ | |
5b3e6663 PB |
1838 | (TARGET_THUMB1 \ |
1839 | ? THUMB1_REG_OK_FOR_INDEX_P (X) \ | |
f1008e52 RE |
1840 | : ARM_REG_OK_FOR_INDEX_P (X)) |
1841 | ||
888d2cd6 DJ |
1842 | /* Nonzero if X can be the base register in a reg+reg addressing mode. |
1843 | For Thumb, we can not use SP + reg, so reject SP. */ | |
1844 | #define REG_MODE_OK_FOR_REG_BASE_P(X, MODE) \ | |
1845 | REG_OK_FOR_INDEX_P (X) | |
35d965d5 | 1846 | \f |
f1008e52 RE |
1847 | #define ARM_BASE_REGISTER_RTX_P(X) \ |
1848 | (GET_CODE (X) == REG && ARM_REG_OK_FOR_BASE_P (X)) | |
35d965d5 | 1849 | |
f1008e52 RE |
1850 | #define ARM_INDEX_REGISTER_RTX_P(X) \ |
1851 | (GET_CODE (X) == REG && ARM_REG_OK_FOR_INDEX_P (X)) | |
35d965d5 | 1852 | \f |
35d965d5 RS |
1853 | /* Specify the machine mode that this machine uses |
1854 | for the index in the tablejump instruction. */ | |
d5b7b3ae | 1855 | #define CASE_VECTOR_MODE Pmode |
35d965d5 | 1856 | |
907dd0c7 | 1857 | #define CASE_VECTOR_PC_RELATIVE (TARGET_THUMB2 \ |
83c3a2d8 | 1858 | || (TARGET_THUMB1 \ |
907dd0c7 RE |
1859 | && (optimize_size || flag_pic))) |
1860 | ||
1861 | #define CASE_VECTOR_SHORTEN_MODE(min, max, body) \ | |
83c3a2d8 | 1862 | (TARGET_THUMB1 \ |
907dd0c7 RE |
1863 | ? (min >= 0 && max < 512 \ |
1864 | ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 1, QImode) \ | |
1865 | : min >= -256 && max < 256 \ | |
1866 | ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, QImode) \ | |
1867 | : min >= 0 && max < 8192 \ | |
1868 | ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 1, HImode) \ | |
1869 | : min >= -4096 && max < 4096 \ | |
1870 | ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, HImode) \ | |
1871 | : SImode) \ | |
10c241af | 1872 | : ((min < 0 || max >= 0x20000 || !TARGET_THUMB2) ? SImode \ |
907dd0c7 RE |
1873 | : (max >= 0x200) ? HImode \ |
1874 | : QImode)) | |
5b3e6663 | 1875 | |
ff9940b0 RE |
1876 | /* signed 'char' is most compatible, but RISC OS wants it unsigned. |
1877 | unsigned is probably best, but may break some code. */ | |
1878 | #ifndef DEFAULT_SIGNED_CHAR | |
3967692c | 1879 | #define DEFAULT_SIGNED_CHAR 0 |
35d965d5 RS |
1880 | #endif |
1881 | ||
35d965d5 | 1882 | /* Max number of bytes we can move from memory to memory |
d17ce9af TG |
1883 | in one reasonably fast instruction. */ |
1884 | #define MOVE_MAX 4 | |
35d965d5 | 1885 | |
d19fb8e3 | 1886 | #undef MOVE_RATIO |
e04ad03d | 1887 | #define MOVE_RATIO(speed) (arm_tune_xscale ? 4 : 2) |
d19fb8e3 | 1888 | |
ff9940b0 RE |
1889 | /* Define if operations between registers always perform the operation |
1890 | on the full register even if a narrower mode is specified. */ | |
1891 | #define WORD_REGISTER_OPERATIONS | |
1892 | ||
1893 | /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD | |
1894 | will either zero-extend or sign-extend. The value of this macro should | |
1895 | be the code that says which one of the two operations is implicitly | |
f822d252 | 1896 | done, UNKNOWN if none. */ |
9c872872 | 1897 | #define LOAD_EXTEND_OP(MODE) \ |
d5b7b3ae RE |
1898 | (TARGET_THUMB ? ZERO_EXTEND : \ |
1899 | ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \ | |
f822d252 | 1900 | : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : UNKNOWN))) |
ff9940b0 | 1901 | |
35d965d5 RS |
1902 | /* Nonzero if access to memory by bytes is slow and undesirable. */ |
1903 | #define SLOW_BYTE_ACCESS 0 | |
1904 | ||
d5b7b3ae | 1905 | #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1 |
f676971a | 1906 | |
35d965d5 RS |
1907 | /* Immediate shift counts are truncated by the output routines (or was it |
1908 | the assembler?). Shift counts in a register are truncated by ARM. Note | |
1909 | that the native compiler puts too large (> 32) immediate shift counts | |
1910 | into a register and shifts by the register, letting the ARM decide what | |
1911 | to do instead of doing that itself. */ | |
ff9940b0 RE |
1912 | /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that |
1913 | code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y). | |
1914 | On the arm, Y in a register is used modulo 256 for the shift. Only for | |
d6b4baa4 | 1915 | rotates is modulo 32 used. */ |
ff9940b0 | 1916 | /* #define SHIFT_COUNT_TRUNCATED 1 */ |
35d965d5 | 1917 | |
35d965d5 | 1918 | /* All integers have the same format so truncation is easy. */ |
d5b7b3ae | 1919 | #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 |
35d965d5 RS |
1920 | |
1921 | /* Calling from registers is a massive pain. */ | |
1922 | #define NO_FUNCTION_CSE 1 | |
1923 | ||
35d965d5 RS |
1924 | /* The machine modes of pointers and functions */ |
1925 | #define Pmode SImode | |
1926 | #define FUNCTION_MODE Pmode | |
1927 | ||
d5b7b3ae RE |
1928 | #define ARM_FRAME_RTX(X) \ |
1929 | ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \ | |
3967692c RE |
1930 | || (X) == arg_pointer_rtx) |
1931 | ||
ff9940b0 RE |
1932 | /* Try to generate sequences that don't involve branches, we can then use |
1933 | conditional instructions */ | |
3a4fd356 | 1934 | #define BRANCH_COST(speed_p, predictable_p) \ |
153668ec JB |
1935 | (current_tune->branch_cost (speed_p, predictable_p)) |
1936 | ||
7a801826 RE |
1937 | \f |
1938 | /* Position Independent Code. */ | |
1939 | /* We decide which register to use based on the compilation options and | |
1940 | the assembler in use; this is more general than the APCS restriction of | |
1941 | using sb (r9) all the time. */ | |
020a4035 | 1942 | extern unsigned arm_pic_register; |
7a801826 RE |
1943 | |
1944 | /* The register number of the register used to address a table of static | |
1945 | data addresses in memory. */ | |
1946 | #define PIC_OFFSET_TABLE_REGNUM arm_pic_register | |
1947 | ||
f5a1b0d2 | 1948 | /* We can't directly access anything that contains a symbol, |
d3585b76 DJ |
1949 | nor can we indirect via the constant pool. One exception is |
1950 | UNSPEC_TLS, which is always PIC. */ | |
82e9d970 | 1951 | #define LEGITIMATE_PIC_OPERAND_P(X) \ |
1575c31e JD |
1952 | (!(symbol_mentioned_p (X) \ |
1953 | || label_mentioned_p (X) \ | |
1954 | || (GET_CODE (X) == SYMBOL_REF \ | |
1955 | && CONSTANT_POOL_ADDRESS_P (X) \ | |
1956 | && (symbol_mentioned_p (get_pool_constant (X)) \ | |
d3585b76 DJ |
1957 | || label_mentioned_p (get_pool_constant (X))))) \ |
1958 | || tls_mentioned_p (X)) | |
1575c31e | 1959 | |
13bd191d PB |
1960 | /* We need to know when we are making a constant pool; this determines |
1961 | whether data needs to be in the GOT or can be referenced via a GOT | |
1962 | offset. */ | |
1963 | extern int making_const_table; | |
82e9d970 | 1964 | \f |
c27ba912 | 1965 | /* Handle pragmas for compatibility with Intel's compilers. */ |
b76c3c4b | 1966 | /* Also abuse this to register additional C specific EABI attributes. */ |
c58b209a NB |
1967 | #define REGISTER_TARGET_PRAGMAS() do { \ |
1968 | c_register_pragma (0, "long_calls", arm_pr_long_calls); \ | |
1969 | c_register_pragma (0, "no_long_calls", arm_pr_no_long_calls); \ | |
1970 | c_register_pragma (0, "long_calls_off", arm_pr_long_calls_off); \ | |
b76c3c4b | 1971 | arm_lang_object_attributes_init(); \ |
8b97c5f8 ZW |
1972 | } while (0) |
1973 | ||
d6b4baa4 | 1974 | /* Condition code information. */ |
ff9940b0 | 1975 | /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, |
a5381466 | 1976 | return the mode to be used for the comparison. */ |
d5b7b3ae RE |
1977 | |
1978 | #define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y) | |
ff9940b0 | 1979 | |
880873be RE |
1980 | #define REVERSIBLE_CC_MODE(MODE) 1 |
1981 | ||
1982 | #define REVERSE_CONDITION(CODE,MODE) \ | |
1983 | (((MODE) == CCFPmode || (MODE) == CCFPEmode) \ | |
1984 | ? reverse_condition_maybe_unordered (code) \ | |
1985 | : reverse_condition (code)) | |
008cf58a | 1986 | |
62b10bbc | 1987 | #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \ |
73160ba9 | 1988 | (CODE) = arm_canonicalize_comparison (CODE, &(OP0), &(OP1)) |
62dd06ea | 1989 | |
7dba8395 RH |
1990 | /* The arm5 clz instruction returns 32. */ |
1991 | #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1) | |
ca96ed43 | 1992 | #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1) |
35d965d5 | 1993 | \f |
906668bb BS |
1994 | #define CC_STATUS_INIT \ |
1995 | do { cfun->machine->thumb1_cc_insn = NULL_RTX; } while (0) | |
1996 | ||
d5b7b3ae | 1997 | #undef ASM_APP_OFF |
5b3e6663 PB |
1998 | #define ASM_APP_OFF (TARGET_THUMB1 ? "\t.code\t16\n" : \ |
1999 | TARGET_THUMB2 ? "\t.thumb\n" : "") | |
35d965d5 | 2000 | |
2ee67fbb JB |
2001 | /* Output a push or a pop instruction (only used when profiling). |
2002 | We can't push STATIC_CHAIN_REGNUM (r12) directly with Thumb-1. We know | |
2003 | that ASM_OUTPUT_REG_PUSH will be matched with ASM_OUTPUT_REG_POP, and | |
2004 | that r7 isn't used by the function profiler, so we can use it as a | |
2005 | scratch reg. WARNING: This isn't safe in the general case! It may be | |
2006 | sensitive to future changes in final.c:profile_function. */ | |
d5b7b3ae | 2007 | #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \ |
8a81cc45 RE |
2008 | do \ |
2009 | { \ | |
2010 | if (TARGET_ARM) \ | |
2011 | asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", \ | |
2012 | STACK_POINTER_REGNUM, REGNO); \ | |
2ee67fbb JB |
2013 | else if (TARGET_THUMB1 \ |
2014 | && (REGNO) == STATIC_CHAIN_REGNUM) \ | |
2015 | { \ | |
2016 | asm_fprintf (STREAM, "\tpush\t{r7}\n"); \ | |
2017 | asm_fprintf (STREAM, "\tmov\tr7, %r\n", REGNO);\ | |
2018 | asm_fprintf (STREAM, "\tpush\t{r7}\n"); \ | |
2019 | } \ | |
8a81cc45 RE |
2020 | else \ |
2021 | asm_fprintf (STREAM, "\tpush {%r}\n", REGNO); \ | |
2022 | } while (0) | |
d5b7b3ae RE |
2023 | |
2024 | ||
2ee67fbb | 2025 | /* See comment for ASM_OUTPUT_REG_PUSH concerning Thumb-1 issue. */ |
d5b7b3ae | 2026 | #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \ |
8a81cc45 RE |
2027 | do \ |
2028 | { \ | |
2029 | if (TARGET_ARM) \ | |
2030 | asm_fprintf (STREAM, "\tldmfd\t%r!,{%r}\n", \ | |
2031 | STACK_POINTER_REGNUM, REGNO); \ | |
2ee67fbb JB |
2032 | else if (TARGET_THUMB1 \ |
2033 | && (REGNO) == STATIC_CHAIN_REGNUM) \ | |
2034 | { \ | |
2035 | asm_fprintf (STREAM, "\tpop\t{r7}\n"); \ | |
2036 | asm_fprintf (STREAM, "\tmov\t%r, r7\n", REGNO);\ | |
2037 | asm_fprintf (STREAM, "\tpop\t{r7}\n"); \ | |
2038 | } \ | |
8a81cc45 RE |
2039 | else \ |
2040 | asm_fprintf (STREAM, "\tpop {%r}\n", REGNO); \ | |
2041 | } while (0) | |
d5b7b3ae | 2042 | |
5b3e6663 PB |
2043 | /* Jump table alignment is explicit in ASM_OUTPUT_CASE_LABEL. */ |
2044 | #define ADDR_VEC_ALIGN(JUMPTABLE) 0 | |
2045 | ||
d5b7b3ae RE |
2046 | /* This is how to output a label which precedes a jumptable. Since |
2047 | Thumb instructions are 2 bytes, we may need explicit alignment here. */ | |
be393ecf | 2048 | #undef ASM_OUTPUT_CASE_LABEL |
5b3e6663 PB |
2049 | #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, JUMPTABLE) \ |
2050 | do \ | |
2051 | { \ | |
2052 | if (TARGET_THUMB && GET_MODE (PATTERN (JUMPTABLE)) == SImode) \ | |
2053 | ASM_OUTPUT_ALIGN (FILE, 2); \ | |
2054 | (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \ | |
2055 | } \ | |
2056 | while (0) | |
2057 | ||
2058 | /* Make sure subsequent insns are aligned after a TBB. */ | |
2059 | #define ASM_OUTPUT_CASE_END(FILE, NUM, JUMPTABLE) \ | |
2060 | do \ | |
2061 | { \ | |
2062 | if (GET_MODE (PATTERN (JUMPTABLE)) == QImode) \ | |
2063 | ASM_OUTPUT_ALIGN (FILE, 1); \ | |
2064 | } \ | |
d5b7b3ae | 2065 | while (0) |
35d965d5 | 2066 | |
6cfc7210 NC |
2067 | #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \ |
2068 | do \ | |
2069 | { \ | |
d5b7b3ae RE |
2070 | if (TARGET_THUMB) \ |
2071 | { \ | |
5b3e6663 | 2072 | if (is_called_in_ARM_mode (DECL) \ |
bf98ec6c | 2073 | || (TARGET_THUMB1 && !TARGET_THUMB1_ONLY \ |
3c072c6b | 2074 | && cfun->is_thunk)) \ |
d5b7b3ae | 2075 | fprintf (STREAM, "\t.code 32\n") ; \ |
5b3e6663 PB |
2076 | else if (TARGET_THUMB1) \ |
2077 | fprintf (STREAM, "\t.code\t16\n\t.thumb_func\n") ; \ | |
d5b7b3ae | 2078 | else \ |
5b3e6663 | 2079 | fprintf (STREAM, "\t.thumb\n\t.thumb_func\n") ; \ |
d5b7b3ae | 2080 | } \ |
6cfc7210 | 2081 | if (TARGET_POKE_FUNCTION_NAME) \ |
586de218 | 2082 | arm_poke_function_name (STREAM, (const char *) NAME); \ |
6cfc7210 NC |
2083 | } \ |
2084 | while (0) | |
35d965d5 | 2085 | |
d5b7b3ae RE |
2086 | /* For aliases of functions we use .thumb_set instead. */ |
2087 | #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \ | |
2088 | do \ | |
2089 | { \ | |
91ea4f8d KG |
2090 | const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \ |
2091 | const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \ | |
d5b7b3ae RE |
2092 | \ |
2093 | if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \ | |
2094 | { \ | |
2095 | fprintf (FILE, "\t.thumb_set "); \ | |
2096 | assemble_name (FILE, LABEL1); \ | |
2097 | fprintf (FILE, ","); \ | |
2098 | assemble_name (FILE, LABEL2); \ | |
2099 | fprintf (FILE, "\n"); \ | |
2100 | } \ | |
2101 | else \ | |
2102 | ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \ | |
2103 | } \ | |
2104 | while (0) | |
2105 | ||
fdc2d3b0 NC |
2106 | #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN |
2107 | /* To support -falign-* switches we need to use .p2align so | |
2108 | that alignment directives in code sections will be padded | |
2109 | with no-op instructions, rather than zeroes. */ | |
5a9335ef | 2110 | #define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE, LOG, MAX_SKIP) \ |
fdc2d3b0 NC |
2111 | if ((LOG) != 0) \ |
2112 | { \ | |
2113 | if ((MAX_SKIP) == 0) \ | |
5a9335ef | 2114 | fprintf ((FILE), "\t.p2align %d\n", (int) (LOG)); \ |
fdc2d3b0 NC |
2115 | else \ |
2116 | fprintf ((FILE), "\t.p2align %d,,%d\n", \ | |
5a9335ef | 2117 | (int) (LOG), (int) (MAX_SKIP)); \ |
fdc2d3b0 NC |
2118 | } |
2119 | #endif | |
35d965d5 | 2120 | \f |
5b3e6663 PB |
2121 | /* Add two bytes to the length of conditionally executed Thumb-2 |
2122 | instructions for the IT instruction. */ | |
2123 | #define ADJUST_INSN_LENGTH(insn, length) \ | |
2124 | if (TARGET_THUMB2 && GET_CODE (PATTERN (insn)) == COND_EXEC) \ | |
2125 | length += 2; | |
2126 | ||
35d965d5 | 2127 | /* Only perform branch elimination (by making instructions conditional) if |
5b3e6663 PB |
2128 | we're optimizing. For Thumb-2 check if any IT instructions need |
2129 | outputting. */ | |
d5b7b3ae RE |
2130 | #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \ |
2131 | if (TARGET_ARM && optimize) \ | |
2132 | arm_final_prescan_insn (INSN); \ | |
5b3e6663 PB |
2133 | else if (TARGET_THUMB2) \ |
2134 | thumb2_final_prescan_insn (INSN); \ | |
2135 | else if (TARGET_THUMB1) \ | |
2136 | thumb1_final_prescan_insn (INSN) | |
35d965d5 | 2137 | |
7b8b8ade NC |
2138 | #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \ |
2139 | (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \ | |
30cf4896 KG |
2140 | : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\ |
2141 | ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \ | |
2142 | ? ((~ (unsigned HOST_WIDE_INT) 0) \ | |
2143 | & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \ | |
7bc7696c | 2144 | : 0)))) |
35d965d5 | 2145 | |
6a5d7526 MS |
2146 | /* A C expression whose value is RTL representing the value of the return |
2147 | address for the frame COUNT steps up from the current frame. */ | |
2148 | ||
d5b7b3ae RE |
2149 | #define RETURN_ADDR_RTX(COUNT, FRAME) \ |
2150 | arm_return_addr (COUNT, FRAME) | |
2151 | ||
f676971a | 2152 | /* Mask of the bits in the PC that contain the real return address |
d5b7b3ae RE |
2153 | when running in 26-bit mode. */ |
2154 | #define RETURN_ADDR_MASK26 (0x03fffffc) | |
6a5d7526 | 2155 | |
2c849145 JM |
2156 | /* Pick up the return address upon entry to a procedure. Used for |
2157 | dwarf2 unwind information. This also enables the table driven | |
2158 | mechanism. */ | |
2c849145 JM |
2159 | #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM) |
2160 | #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM) | |
2161 | ||
39950dff MS |
2162 | /* Used to mask out junk bits from the return address, such as |
2163 | processor state, interrupt status, condition codes and the like. */ | |
2164 | #define MASK_RETURN_ADDR \ | |
2165 | /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \ | |
2166 | in 26 bit mode, the condition codes must be masked out of the \ | |
2167 | return address. This does not apply to ARM6 and later processors \ | |
2168 | when running in 32 bit mode. */ \ | |
61f0ccff RE |
2169 | ((arm_arch4 || TARGET_THUMB) \ |
2170 | ? (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \ | |
fcd53748 | 2171 | : arm_gen_return_addr_mask ()) |
d5b7b3ae RE |
2172 | |
2173 | \f | |
978e411f CD |
2174 | /* Do not emit .note.GNU-stack by default. */ |
2175 | #ifndef NEED_INDICATE_EXEC_STACK | |
2176 | #define NEED_INDICATE_EXEC_STACK 0 | |
2177 | #endif | |
2178 | ||
93b338c3 BS |
2179 | /* The maximum number of parallel loads or stores we support in an ldm/stm |
2180 | instruction. */ | |
2181 | #define MAX_LDM_STM_OPS 4 | |
2182 | ||
54e73f88 AS |
2183 | #define ASM_CPU_SPEC \ |
2184 | " %{mcpu=generic-*:-march=%*;" \ | |
2185 | " :%{mcpu=*:-mcpu=%*} %{march=*:-march=%*}}" | |
2186 | ||
58e9ddb1 NC |
2187 | /* This macro is used to emit an EABI tag and its associated value. |
2188 | We emit the numerical value of the tag in case the assembler does not | |
2189 | support textual tags. (Eg gas prior to 2.20). If requested we include | |
2190 | the tag name in a comment so that anyone reading the assembler output | |
2191 | will know which tag is being set. */ | |
2192 | #define EMIT_EABI_ATTRIBUTE(NAME,NUM,VAL) \ | |
2193 | do \ | |
2194 | { \ | |
2195 | asm_fprintf (asm_out_file, "\t.eabi_attribute %d, %d", NUM, VAL); \ | |
2196 | if (flag_verbose_asm || flag_debug_asm) \ | |
2197 | asm_fprintf (asm_out_file, "\t%s " #NAME, ASM_COMMENT_START); \ | |
2198 | asm_fprintf (asm_out_file, "\n"); \ | |
2199 | } \ | |
2200 | while (0) | |
2201 | ||
33aa08b3 AS |
2202 | /* -mcpu=native handling only makes sense with compiler running on |
2203 | an ARM chip. */ | |
2204 | #if defined(__arm__) | |
2205 | extern const char *host_detect_local_cpu (int argc, const char **argv); | |
2206 | # define EXTRA_SPEC_FUNCTIONS \ | |
2207 | { "local_cpu_detect", host_detect_local_cpu }, | |
2208 | ||
2209 | # define MCPU_MTUNE_NATIVE_SPECS \ | |
2210 | " %{march=native:%<march=native %:local_cpu_detect(arch)}" \ | |
2211 | " %{mcpu=native:%<mcpu=native %:local_cpu_detect(cpu)}" \ | |
2212 | " %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}" | |
2213 | #else | |
2214 | # define MCPU_MTUNE_NATIVE_SPECS "" | |
2215 | #endif | |
2216 | ||
2217 | #define DRIVER_SELF_SPECS MCPU_MTUNE_NATIVE_SPECS | |
2218 | ||
88657302 | 2219 | #endif /* ! GCC_ARM_H */ |