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35d965d5 | 1 | /* Definitions of target machine for GNU compiler, for Acorn RISC Machine. |
89c7ca52 | 2 | Copyright (C) 1991, 1993, 1994, 1995, 1996 Free Software Foundation, Inc. |
35d965d5 | 3 | Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl) |
8b109b37 | 4 | and Martin Simmons (@harleqn.co.uk). |
ff9940b0 RE |
5 | More major hacks by Richard Earnshaw (rwe11@cl.cam.ac.uk) |
6 | ||
35d965d5 RS |
7 | This file is part of GNU CC. |
8 | ||
9 | GNU CC is free software; you can redistribute it and/or modify | |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 2, or (at your option) | |
12 | any later version. | |
13 | ||
14 | GNU CC is distributed in the hope that it will be useful, | |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License | |
20 | along with GNU CC; see the file COPYING. If not, write to | |
8fb289e7 RK |
21 | the Free Software Foundation, 59 Temple Place - Suite 330, |
22 | Boston, MA 02111-1307, USA. */ | |
35d965d5 | 23 | |
52a02435 DE |
24 | /* Configuration triples for ARM ports work as follows: |
25 | arm-*-*: little endian | |
26 | armel-*-*: little endian | |
27 | armeb-*-*: big endian | |
5da4dc2c DE |
28 | If a non-embedded environment (ie: "real" OS) is specified, `arm' |
29 | should default to that used by the OS. | |
52a02435 DE |
30 | */ |
31 | ||
7bc7696c RE |
32 | extern void output_func_prologue (); |
33 | extern void output_func_epilogue (); | |
35d965d5 RS |
34 | extern char *output_add_immediate (); |
35 | extern char *output_call (); | |
ff9940b0 | 36 | extern char *output_call_mem (); |
35d965d5 RS |
37 | extern char *output_move_double (); |
38 | extern char *output_mov_double_fpu_from_arm (); | |
39 | extern char *output_mov_double_arm_from_fpu (); | |
7fc6c9f0 RK |
40 | extern char *output_mov_long_double_fpu_from_arm (); |
41 | extern char *output_mov_long_double_arm_from_fpu (); | |
42 | extern char *output_mov_long_double_arm_from_arm (); | |
35d965d5 RS |
43 | extern char *output_mov_immediate (); |
44 | extern char *output_multi_immediate (); | |
ff9940b0 RE |
45 | extern char *output_return_instruction (); |
46 | extern char *output_load_symbol (); | |
89c7ca52 RE |
47 | extern char *emit_ldm_seq (); |
48 | extern char *emit_stm_seq (); | |
ff9940b0 RE |
49 | extern char *fp_immediate_constant (); |
50 | extern struct rtx_def *gen_compare_reg (); | |
51 | extern struct rtx_def *arm_gen_store_multiple (); | |
52 | extern struct rtx_def *arm_gen_load_multiple (); | |
89c7ca52 | 53 | extern struct rtx_def *gen_rotated_half_load (); |
ff9940b0 | 54 | |
89c7ca52 RE |
55 | enum arm_cond_code |
56 | { | |
57 | ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC, | |
58 | ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV | |
59 | }; | |
60 | extern enum arm_cond_code arm_current_cc; | |
ff9940b0 RE |
61 | extern char *arm_condition_codes[]; |
62 | ||
89c7ca52 RE |
63 | #define ARM_INVERSE_CONDITION_CODE(X) ((enum arm_cond_code) (((int)X) ^ 1)) |
64 | ||
ff9940b0 RE |
65 | /* This is needed by the tail-calling peepholes */ |
66 | extern int frame_pointer_needed; | |
67 | ||
35d965d5 | 68 | \f |
ff9940b0 RE |
69 | #ifndef CPP_PREDEFINES |
70 | #define CPP_PREDEFINES "-Darm -Acpu(arm) -Amachine(arm)" | |
71 | #endif | |
35d965d5 | 72 | |
ff9940b0 | 73 | #ifndef CPP_SPEC |
11c1a207 RE |
74 | #define CPP_SPEC "%{m6:-D__arm6__} \ |
75 | %{mcpu-*:-D__%*} \ | |
76 | %{mcpu=*:-D__%*} \ | |
77 | %{mapcs-32:-D__APCS_32__ -U__APCS_26__} \ | |
78 | %{mapcs-26:-D__APCS_26__ -U__APCS_32__} \ | |
79 | %{!mapcs-32: %{!mapcs-26:-D__APCS_26__}} \ | |
80 | %{msoft-float:-D__SOFTFP__} \ | |
81 | %{mhard-float:-U__SOFTFP__} \ | |
82 | %{!mhard-float: %{!msoft-float:-U__SOFTFP__}} \ | |
ddee6aba RE |
83 | %{mbig-endian:-D__ARMEB__ %{mwords-little-endian:-D__ARMWEL__}} \ |
84 | %{mbe:-D__ARMEB__ %{mwords-little-endian:-D__ARMWEL__}} \ | |
85 | %{!mbe: %{!mbig-endian:-D__ARMEL__}} \ | |
11c1a207 | 86 | " |
35d965d5 RS |
87 | #endif |
88 | \f | |
89 | /* Run-time Target Specification. */ | |
ff9940b0 | 90 | #ifndef TARGET_VERSION |
35d965d5 | 91 | #define TARGET_VERSION \ |
ff9940b0 RE |
92 | fputs (" (ARM/generic)", stderr); |
93 | #endif | |
35d965d5 | 94 | |
11c1a207 | 95 | /* Run-time compilation parameters selecting different hardware subsets. */ |
35d965d5 RS |
96 | extern int target_flags; |
97 | ||
11c1a207 | 98 | /* These two are used by TARGET_OPTIONS, they are parsed in OVERRIDE_OPTIONS */ |
11c1a207 RE |
99 | extern char *target_fpe_name; |
100 | ||
35d965d5 RS |
101 | /* Nonzero if the function prologue (and epilogue) should obey |
102 | the ARM Procedure Call Standard. */ | |
11c1a207 | 103 | #define ARM_FLAG_APCS_FRAME (0x0001) |
35d965d5 RS |
104 | |
105 | /* Nonzero if the function prologue should output the function name to enable | |
106 | the post mortem debugger to print a backtrace (very useful on RISCOS, | |
11c1a207 RE |
107 | unused on RISCiX). Specifying this flag also enables |
108 | -fno-omit-frame-pointer. | |
35d965d5 | 109 | XXX Must still be implemented in the prologue. */ |
11c1a207 | 110 | #define ARM_FLAG_POKE (0x0002) |
35d965d5 RS |
111 | |
112 | /* Nonzero if floating point instructions are emulated by the FPE, in which | |
113 | case instruction scheduling becomes very uninteresting. */ | |
11c1a207 | 114 | #define ARM_FLAG_FPE (0x0004) |
35d965d5 | 115 | |
ff9940b0 RE |
116 | /* Nonzero if destined for an ARM6xx. Takes out bits that assume restoration |
117 | of condition flags when returning from a branch & link (ie. a function) */ | |
11c1a207 RE |
118 | /* ********* DEPRECATED ******** */ |
119 | #define ARM_FLAG_ARM6 (0x0008) | |
120 | ||
121 | /* ********* DEPRECATED ******** */ | |
122 | #define ARM_FLAG_ARM3 (0x0010) | |
123 | ||
124 | /* Nonzero if destined for a processor in 32-bit program mode. Takes out bit | |
125 | that assume restoration of the condition flags when returning from a | |
126 | branch and link (ie a function). */ | |
127 | #define ARM_FLAG_APCS_32 (0x0020) | |
128 | ||
129 | /* Nonzero if stack checking should be performed on entry to each function | |
130 | which allocates temporary variables on the stack. */ | |
131 | #define ARM_FLAG_APCS_STACK (0x0040) | |
132 | ||
133 | /* Nonzero if floating point parameters should be passed to functions in | |
134 | floating point registers. */ | |
135 | #define ARM_FLAG_APCS_FLOAT (0x0080) | |
136 | ||
137 | /* Nonzero if re-entrant, position independent code should be generated. | |
138 | This is equivalent to -fpic. */ | |
139 | #define ARM_FLAG_APCS_REENT (0x0100) | |
140 | ||
141 | /* Nonzero if the MMU will trap unaligned word accesses, so shorts must be | |
142 | loaded byte-at-a-time. */ | |
143 | #define ARM_FLAG_SHORT_BYTE (0x0200) | |
144 | ||
145 | /* Nonzero if all floating point instructions are missing (and there is no | |
146 | emulator either). Generate function calls for all ops in this case. */ | |
147 | #define ARM_FLAG_SOFT_FLOAT (0x0400) | |
148 | ||
149 | /* Nonzero if we should compile with BYTES_BIG_ENDIAN set to 1. */ | |
150 | #define ARM_FLAG_BIG_END (0x0800) | |
151 | ||
152 | /* Nonzero if we should compile for Thumb interworking. */ | |
153 | #define ARM_FLAG_THUMB (0x1000) | |
154 | ||
ddee6aba RE |
155 | /* Nonzero if we should have little-endian words even when compiling for |
156 | big-endian (for backwards compatibility with older versions of GCC). */ | |
157 | #define ARM_FLAG_LITTLE_WORDS (0x2000) | |
158 | ||
11c1a207 RE |
159 | #define TARGET_APCS (target_flags & ARM_FLAG_APCS_FRAME) |
160 | #define TARGET_POKE_FUNCTION_NAME (target_flags & ARM_FLAG_POKE) | |
161 | #define TARGET_FPE (target_flags & ARM_FLAG_FPE) | |
162 | #define TARGET_6 (target_flags & ARM_FLAG_ARM6) | |
163 | #define TARGET_3 (target_flags & ARM_FLAG_ARM3) | |
164 | #define TARGET_APCS_32 (target_flags & ARM_FLAG_APCS_32) | |
165 | #define TARGET_APCS_STACK (target_flags & ARM_FLAG_APCS_STACK) | |
166 | #define TARGET_APCS_FLOAT (target_flags & ARM_FLAG_APCS_FLOAT) | |
167 | #define TARGET_APCS_REENT (target_flags & ARM_FLAG_APCS_REENT) | |
168 | #define TARGET_SHORT_BY_BYTES (target_flags & ARM_FLAG_SHORT_BYTE) | |
169 | #define TARGET_SOFT_FLOAT (target_flags & ARM_FLAG_SOFT_FLOAT) | |
170 | #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT) | |
171 | #define TARGET_BIG_END (target_flags & ARM_FLAG_BIG_END) | |
172 | #define TARGET_THUMB_INTERWORK (target_flags & ARM_FLAG_THUMB) | |
ddee6aba | 173 | #define TARGET_LITTLE_WORDS (target_flags & ARM_FLAG_LITTLE_WORDS) |
3ada8e17 DE |
174 | |
175 | /* SUBTARGET_SWITCHES is used to add flags on a per-config basis. | |
176 | Bit 31 is reserved. See riscix.h. */ | |
177 | #ifndef SUBTARGET_SWITCHES | |
178 | #define SUBTARGET_SWITCHES | |
ff9940b0 RE |
179 | #endif |
180 | ||
2ce9c1b9 RE |
181 | #define TARGET_SWITCHES \ |
182 | { \ | |
11c1a207 RE |
183 | {"apcs", ARM_FLAG_APCS_FRAME}, \ |
184 | {"apcs-frame", ARM_FLAG_APCS_FRAME}, \ | |
185 | {"no-apcs-frame", -ARM_FLAG_APCS_FRAME}, \ | |
186 | {"poke-function-name", ARM_FLAG_POKE}, \ | |
187 | {"fpe", ARM_FLAG_FPE}, \ | |
188 | {"6", ARM_FLAG_ARM6}, \ | |
189 | {"2", ARM_FLAG_ARM3}, \ | |
190 | {"3", ARM_FLAG_ARM3}, \ | |
191 | {"apcs-32", ARM_FLAG_APCS_32}, \ | |
192 | {"apcs-26", -ARM_FLAG_APCS_32}, \ | |
193 | {"apcs-stack-check", ARM_FLAG_APCS_STACK}, \ | |
194 | {"no-apcs-stack-check", -ARM_FLAG_APCS_STACK}, \ | |
195 | {"apcs-float", ARM_FLAG_APCS_FLOAT}, \ | |
196 | {"no-apcs-float", -ARM_FLAG_APCS_FLOAT}, \ | |
197 | {"apcs-reentrant", ARM_FLAG_APCS_REENT}, \ | |
198 | {"no-apcs-rentrant", -ARM_FLAG_APCS_REENT}, \ | |
199 | {"short-load-bytes", ARM_FLAG_SHORT_BYTE}, \ | |
200 | {"no-short-load-bytes", -ARM_FLAG_SHORT_BYTE}, \ | |
201 | {"short-load-words", -ARM_FLAG_SHORT_BYTE}, \ | |
202 | {"no-short-load-words", ARM_FLAG_SHORT_BYTE}, \ | |
203 | {"soft-float", ARM_FLAG_SOFT_FLOAT}, \ | |
204 | {"hard-float", -ARM_FLAG_SOFT_FLOAT}, \ | |
205 | {"big-endian", ARM_FLAG_BIG_END}, \ | |
11c1a207 | 206 | {"little-endian", -ARM_FLAG_BIG_END}, \ |
11c1a207 RE |
207 | {"thumb-interwork", ARM_FLAG_THUMB}, \ |
208 | {"no-thumb-interwork", -ARM_FLAG_THUMB}, \ | |
ddee6aba | 209 | {"words-little-endian", ARM_FLAG_LITTLE_WORDS}, \ |
3ada8e17 | 210 | SUBTARGET_SWITCHES \ |
11c1a207 | 211 | {"", TARGET_DEFAULT } \ |
35d965d5 RS |
212 | } |
213 | ||
62dd06ea RE |
214 | #define TARGET_OPTIONS \ |
215 | { \ | |
216 | {"cpu=", &arm_select[1].string}, \ | |
217 | {"tune=", &arm_select[2].string}, \ | |
218 | {"fpe=", &target_fpe_name} \ | |
11c1a207 | 219 | } |
ff9940b0 | 220 | |
62dd06ea RE |
221 | /* arm_select[0] is reserved for the default cpu. */ |
222 | struct arm_cpu_select | |
223 | { | |
224 | char *string; | |
225 | char *name; | |
226 | int set_tune_p; | |
227 | int set_arch_p; | |
228 | }; | |
229 | ||
230 | extern struct arm_cpu_select arm_select[]; | |
231 | ||
232 | #ifndef PROCESSOR_DEFAULT | |
233 | #define PROCESSOR_DEFAULT PROCESSOR_ARM2 | |
234 | #endif | |
235 | ||
236 | #ifndef TARGET_CPU_DEFAULT | |
237 | #define TARGET_CPU_DEFAULT ((char *) 0) | |
238 | #endif | |
239 | ||
11c1a207 | 240 | /* Which processor we are running on. */ |
ff9940b0 RE |
241 | enum processor_type |
242 | { | |
243 | PROCESSOR_ARM2, | |
244 | PROCESSOR_ARM3, | |
11c1a207 RE |
245 | PROCESSOR_ARM6, |
246 | PROCESSOR_ARM7 | |
ff9940b0 RE |
247 | }; |
248 | ||
249 | /* Recast the cpu class to be the cpu attribute. */ | |
250 | ||
251 | /* Recast the cpu class to be the cpu attribute. */ | |
252 | #define arm_cpu_attr ((enum attr_cpu)arm_cpu) | |
253 | ||
254 | extern enum processor_type arm_cpu; | |
255 | ||
11c1a207 RE |
256 | enum prog_mode_type |
257 | { | |
258 | prog_mode26, | |
259 | prog_mode32 | |
260 | }; | |
261 | ||
262 | /* Recast the program mode class to be the prog_mode attribute */ | |
263 | #define arm_prog_mode ((enum attr_prog_mode) arm_prgmode) | |
264 | ||
265 | extern enum prog_mode_type arm_prgmode; | |
266 | ||
267 | /* What sort of floating point unit do we have? Hardware or software. | |
268 | If software, is it issue 2 or issue 3? */ | |
24f0c1b4 RE |
269 | enum floating_point_type |
270 | { | |
271 | FP_HARD, | |
11c1a207 RE |
272 | FP_SOFT2, |
273 | FP_SOFT3 | |
24f0c1b4 RE |
274 | }; |
275 | ||
276 | /* Recast the floating point class to be the floating point attribute. */ | |
277 | #define arm_fpu_attr ((enum attr_fpu) arm_fpu) | |
278 | ||
279 | extern enum floating_point_type arm_fpu; | |
280 | ||
11c1a207 RE |
281 | /* Nonzero if the processor has a fast multiply insn, and one that does |
282 | a 64-bit multiply of two 32-bit values. */ | |
283 | extern int arm_fast_multiply; | |
284 | ||
285 | /* Nonzero if this chip support the ARM Architecture 4 extensions */ | |
286 | extern int arm_arch4; | |
287 | ||
2ce9c1b9 | 288 | #ifndef TARGET_DEFAULT |
35d965d5 | 289 | #define TARGET_DEFAULT 0 |
2ce9c1b9 | 290 | #endif |
35d965d5 | 291 | |
11c1a207 RE |
292 | /* A particular target can define this to a particular cpu name, eg "arm710dmi" |
293 | and the code generated should then be appropriate for that processor. */ | |
294 | #ifndef ARM_CPU_NAME | |
295 | #define ARM_CPU_NAME NULL | |
296 | #endif | |
35d965d5 | 297 | |
11c1a207 RE |
298 | /* The frame pointer register used in gcc has nothing to do with debugging; |
299 | that is controlled by the APCS-FRAME option. */ | |
300 | /* Not fully implemented yet */ | |
301 | /* #define CAN_DEBUG_WITHOUT_FP 1 */ | |
35d965d5 | 302 | |
11c1a207 RE |
303 | #define TARGET_MEM_FUNCTIONS 1 |
304 | ||
305 | #define OVERRIDE_OPTIONS arm_override_options () | |
35d965d5 RS |
306 | \f |
307 | /* Target machine storage Layout. */ | |
308 | ||
ff9940b0 RE |
309 | |
310 | /* Define this macro if it is advisable to hold scalars in registers | |
311 | in a wider mode than that declared by the program. In such cases, | |
312 | the value is constrained to be within the bounds of the declared | |
313 | type, but kept valid in the wider mode. The signedness of the | |
314 | extension may differ from that of the type. */ | |
315 | ||
316 | /* It is far faster to zero extend chars than to sign extend them */ | |
317 | ||
318 | #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \ | |
2ce9c1b9 RE |
319 | if (GET_MODE_CLASS (MODE) == MODE_INT \ |
320 | && GET_MODE_SIZE (MODE) < 4) \ | |
321 | { \ | |
322 | if (MODE == QImode) \ | |
323 | UNSIGNEDP = 1; \ | |
324 | else if (MODE == HImode) \ | |
325 | UNSIGNEDP = TARGET_SHORT_BY_BYTES != 0; \ | |
326 | (MODE) = SImode; \ | |
ff9940b0 RE |
327 | } |
328 | ||
329 | /* Define for XFmode extended real floating point support. | |
330 | This will automatically cause REAL_ARITHMETIC to be defined. */ | |
331 | /* For the ARM: | |
332 | I think I have added all the code to make this work. Unfortunately, | |
333 | early releases of the floating point emulation code on RISCiX used a | |
334 | different format for extended precision numbers. On my RISCiX box there | |
335 | is a bug somewhere which causes the machine to lock up when running enquire | |
336 | with long doubles. There is the additional aspect that Norcroft C | |
337 | treats long doubles as doubles and we ought to remain compatible. | |
338 | Perhaps someone with an FPA coprocessor and not running RISCiX would like | |
339 | to try this someday. */ | |
340 | /* #define LONG_DOUBLE_TYPE_SIZE 96 */ | |
341 | ||
342 | /* Disable XFmode patterns in md file */ | |
343 | #define ENABLE_XF_PATTERNS 0 | |
344 | ||
345 | /* Define if you don't want extended real, but do want to use the | |
346 | software floating point emulator for REAL_ARITHMETIC and | |
347 | decimal <-> binary conversion. */ | |
348 | /* See comment above */ | |
349 | #define REAL_ARITHMETIC | |
350 | ||
35d965d5 RS |
351 | /* Define this if most significant bit is lowest numbered |
352 | in instructions that operate on numbered bit-fields. */ | |
353 | #define BITS_BIG_ENDIAN 0 | |
354 | ||
9c872872 | 355 | /* Define this if most significant byte of a word is the lowest numbered. |
3ada8e17 DE |
356 | Most ARM processors are run in little endian mode, so that is the default. |
357 | If you want to have it run-time selectable, change the definition in a | |
358 | cover file to be TARGET_BIG_ENDIAN. */ | |
11c1a207 | 359 | #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0) |
35d965d5 RS |
360 | |
361 | /* Define this if most significant word of a multiword number is the lowest | |
11c1a207 RE |
362 | numbered. |
363 | This is always false, even when in big-endian mode. */ | |
ddee6aba RE |
364 | #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS) |
365 | ||
366 | /* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based | |
367 | on processor pre-defineds when compiling libgcc2.c. */ | |
368 | #if defined(__ARMEB__) && !defined(__ARMWEL__) | |
369 | #define LIBGCC2_WORDS_BIG_ENDIAN 1 | |
370 | #else | |
371 | #define LIBGCC2_WORDS_BIG_ENDIAN 0 | |
372 | #endif | |
35d965d5 | 373 | |
11c1a207 RE |
374 | /* Define this if most significant word of doubles is the lowest numbered. |
375 | This is always true, even when in little-endian mode. */ | |
7fc6c9f0 RK |
376 | #define FLOAT_WORDS_BIG_ENDIAN 1 |
377 | ||
b4ac57ab | 378 | /* Number of bits in an addressable storage unit */ |
35d965d5 RS |
379 | #define BITS_PER_UNIT 8 |
380 | ||
381 | #define BITS_PER_WORD 32 | |
382 | ||
383 | #define UNITS_PER_WORD 4 | |
384 | ||
385 | #define POINTER_SIZE 32 | |
386 | ||
387 | #define PARM_BOUNDARY 32 | |
388 | ||
389 | #define STACK_BOUNDARY 32 | |
390 | ||
391 | #define FUNCTION_BOUNDARY 32 | |
392 | ||
393 | #define EMPTY_FIELD_BOUNDARY 32 | |
394 | ||
395 | #define BIGGEST_ALIGNMENT 32 | |
396 | ||
ff9940b0 RE |
397 | /* Make strings word-aligned so strcpy from constants will be faster. */ |
398 | #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ | |
399 | (TREE_CODE (EXP) == STRING_CST \ | |
400 | && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN)) | |
401 | ||
b4ac57ab | 402 | /* Every structures size must be a multiple of 32 bits. */ |
7d94bb81 DE |
403 | /* This is for compatibility with ARMCC. ARM SDT Reference Manual |
404 | (ARM DUI 0020D) page 2-20 says "Structures are aligned on word | |
405 | boundaries". */ | |
b4ac57ab RS |
406 | #define STRUCTURE_SIZE_BOUNDARY 32 |
407 | ||
ff9940b0 RE |
408 | /* Non-zero if move instructions will actually fail to work |
409 | when given unaligned data. */ | |
35d965d5 RS |
410 | #define STRICT_ALIGNMENT 1 |
411 | ||
ff9940b0 RE |
412 | #define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT |
413 | ||
35d965d5 RS |
414 | \f |
415 | /* Standard register usage. */ | |
416 | ||
417 | /* Register allocation in ARM Procedure Call Standard (as used on RISCiX): | |
418 | (S - saved over call). | |
419 | ||
420 | r0 * argument word/integer result | |
421 | r1-r3 argument word | |
422 | ||
423 | r4-r8 S register variable | |
424 | r9 S (rfp) register variable (real frame pointer) | |
425 | ||
426 | r10 F S (sl) stack limit (not currently used) | |
427 | r11 F S (fp) argument pointer | |
428 | r12 (ip) temp workspace | |
429 | r13 F S (sp) lower end of current stack frame | |
430 | r14 (lr) link address/workspace | |
431 | r15 F (pc) program counter | |
432 | ||
433 | f0 floating point result | |
434 | f1-f3 floating point scratch | |
435 | ||
436 | f4-f7 S floating point variable | |
437 | ||
ff9940b0 RE |
438 | cc This is NOT a real register, but is used internally |
439 | to represent things that use or set the condition | |
440 | codes. | |
441 | sfp This isn't either. It is used during rtl generation | |
442 | since the offset between the frame pointer and the | |
443 | auto's isn't known until after register allocation. | |
444 | afp Nor this, we only need this because of non-local | |
445 | goto. Without it fp appears to be used and the | |
446 | elimination code won't get rid of sfp. It tracks | |
447 | fp exactly at all times. | |
448 | ||
35d965d5 RS |
449 | *: See CONDITIONAL_REGISTER_USAGE */ |
450 | ||
ff9940b0 RE |
451 | /* The stack backtrace structure is as follows: |
452 | fp points to here: | save code pointer | [fp] | |
453 | | return link value | [fp, #-4] | |
454 | | return sp value | [fp, #-8] | |
455 | | return fp value | [fp, #-12] | |
456 | [| saved r10 value |] | |
457 | [| saved r9 value |] | |
458 | [| saved r8 value |] | |
459 | [| saved r7 value |] | |
460 | [| saved r6 value |] | |
461 | [| saved r5 value |] | |
462 | [| saved r4 value |] | |
463 | [| saved r3 value |] | |
464 | [| saved r2 value |] | |
465 | [| saved r1 value |] | |
466 | [| saved r0 value |] | |
467 | [| saved f7 value |] three words | |
468 | [| saved f6 value |] three words | |
469 | [| saved f5 value |] three words | |
470 | [| saved f4 value |] three words | |
471 | r0-r3 are not normally saved in a C function. */ | |
472 | ||
473 | /* The number of hard registers is 16 ARM + 8 FPU + 1 CC + 1 SFP. */ | |
474 | #define FIRST_PSEUDO_REGISTER 27 | |
35d965d5 RS |
475 | |
476 | /* 1 for registers that have pervasive standard uses | |
477 | and are not available for the register allocator. */ | |
478 | #define FIXED_REGISTERS \ | |
479 | { \ | |
480 | 0,0,0,0,0,0,0,0, \ | |
481 | 0,0,1,1,0,1,0,1, \ | |
ff9940b0 RE |
482 | 0,0,0,0,0,0,0,0, \ |
483 | 1,1,1 \ | |
35d965d5 RS |
484 | } |
485 | ||
486 | /* 1 for registers not available across function calls. | |
487 | These must include the FIXED_REGISTERS and also any | |
488 | registers that can be used without being saved. | |
489 | The latter must include the registers where values are returned | |
490 | and the register where structure-value addresses are passed. | |
ff9940b0 RE |
491 | Aside from that, you can include as many other registers as you like. |
492 | The CC is not preserved over function calls on the ARM 6, so it is | |
493 | easier to assume this for all. SFP is preserved, since FP is. */ | |
35d965d5 RS |
494 | #define CALL_USED_REGISTERS \ |
495 | { \ | |
496 | 1,1,1,1,0,0,0,0, \ | |
497 | 0,0,1,1,1,1,1,1, \ | |
ff9940b0 RE |
498 | 1,1,1,1,0,0,0,0, \ |
499 | 1,1,1 \ | |
35d965d5 RS |
500 | } |
501 | ||
502 | /* If doing stupid life analysis, avoid a bug causing a return value r0 to be | |
503 | trampled. This effectively reduces the number of available registers by 1. | |
504 | XXX It is a hack, I know. | |
505 | XXX Is this still needed? */ | |
506 | #define CONDITIONAL_REGISTER_USAGE \ | |
3ada8e17 DE |
507 | { \ |
508 | if (obey_regdecls) \ | |
509 | fixed_regs[0] = 1; \ | |
510 | if (TARGET_SOFT_FLOAT) \ | |
511 | { \ | |
512 | int regno; \ | |
513 | for (regno = 16; regno < 24; ++regno) \ | |
514 | fixed_regs[regno] = call_used_regs[regno] = 1; \ | |
515 | } \ | |
35d965d5 RS |
516 | } |
517 | ||
518 | /* Return number of consecutive hard regs needed starting at reg REGNO | |
519 | to hold something of mode MODE. | |
520 | This is ordinarily the length in words of a value of mode MODE | |
521 | but can be less for certain modes in special long registers. | |
522 | ||
523 | On the ARM regs are UNITS_PER_WORD bits wide; FPU regs can hold any FP | |
524 | mode. */ | |
ff9940b0 RE |
525 | #define HARD_REGNO_NREGS(REGNO, MODE) \ |
526 | (((REGNO) >= 16 && REGNO != FRAME_POINTER_REGNUM \ | |
527 | && (REGNO) != ARG_POINTER_REGNUM) ? 1 \ | |
35d965d5 RS |
528 | : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) |
529 | ||
530 | /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. | |
531 | This is TRUE for ARM regs since they can hold anything, and TRUE for FPU | |
532 | regs holding FP. */ | |
ff9940b0 RE |
533 | #define HARD_REGNO_MODE_OK(REGNO, MODE) \ |
534 | ((GET_MODE_CLASS (MODE) == MODE_CC) ? (REGNO == CC_REGNUM) : \ | |
535 | ((REGNO) < 16 || REGNO == FRAME_POINTER_REGNUM \ | |
536 | || REGNO == ARG_POINTER_REGNUM \ | |
537 | || GET_MODE_CLASS (MODE) == MODE_FLOAT)) | |
35d965d5 RS |
538 | |
539 | /* Value is 1 if it is a good idea to tie two pseudo registers | |
540 | when one has mode MODE1 and one has mode MODE2. | |
541 | If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, | |
542 | for any hard reg, then this must be 0 for correct output. */ | |
543 | #define MODES_TIEABLE_P(MODE1, MODE2) \ | |
3967692c | 544 | (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2)) |
35d965d5 RS |
545 | |
546 | /* Specify the registers used for certain standard purposes. | |
547 | The values of these macros are register numbers. */ | |
548 | ||
549 | /* Define this if the program counter is overloaded on a register. */ | |
550 | #define PC_REGNUM 15 | |
551 | ||
552 | /* Register to use for pushing function arguments. */ | |
553 | #define STACK_POINTER_REGNUM 13 | |
554 | ||
555 | /* Base register for access to local variables of the function. */ | |
ff9940b0 RE |
556 | #define FRAME_POINTER_REGNUM 25 |
557 | ||
558 | /* Define this to be where the real frame pointer is if it is not possible to | |
559 | work out the offset between the frame pointer and the automatic variables | |
560 | until after register allocation has taken place. FRAME_POINTER_REGNUM | |
561 | should point to a special register that we will make sure is eliminated. */ | |
562 | #define HARD_FRAME_POINTER_REGNUM 11 | |
35d965d5 RS |
563 | |
564 | /* Value should be nonzero if functions must have frame pointers. | |
565 | Zero means the frame pointer need not be set up (and parms may be accessed | |
ff9940b0 RE |
566 | via the stack pointer) in functions that seem suitable. |
567 | If we have to have a frame pointer we might as well make use of it. | |
568 | APCS says that the frame pointer does not need to be pushed in leaf | |
569 | functions. */ | |
688743e7 RE |
570 | #define FRAME_POINTER_REQUIRED \ |
571 | (current_function_has_nonlocal_label || (TARGET_APCS && !leaf_function_p ())) | |
35d965d5 RS |
572 | |
573 | /* Base register for access to arguments of the function. */ | |
ff9940b0 | 574 | #define ARG_POINTER_REGNUM 26 |
35d965d5 RS |
575 | |
576 | /* The native (Norcroft) Pascal compiler for the ARM passes the static chain | |
577 | as an invisible last argument (possible since varargs don't exist in | |
578 | Pascal), so the following is not true. */ | |
579 | #define STATIC_CHAIN_REGNUM 8 | |
580 | ||
581 | /* Register in which address to store a structure value | |
582 | is passed to a function. */ | |
583 | #define STRUCT_VALUE_REGNUM 0 | |
584 | ||
ff9940b0 RE |
585 | /* Internal, so that we don't need to refer to a raw number */ |
586 | #define CC_REGNUM 24 | |
587 | ||
35d965d5 | 588 | /* The order in which register should be allocated. It is good to use ip |
ff9940b0 RE |
589 | since no saving is required (though calls clobber it) and it never contains |
590 | function parameters. It is quite good to use lr since other calls may | |
591 | clobber it anyway. Allocate r0 through r3 in reverse order since r3 is | |
592 | least likely to contain a function parameter; in addition results are | |
593 | returned in r0. | |
594 | */ | |
35d965d5 RS |
595 | #define REG_ALLOC_ORDER \ |
596 | { \ | |
ff9940b0 | 597 | 3, 2, 1, 0, 12, 14, 4, 5, \ |
35d965d5 | 598 | 6, 7, 8, 10, 9, 11, 13, 15, \ |
ff9940b0 RE |
599 | 16, 17, 18, 19, 20, 21, 22, 23, \ |
600 | 24, 25 \ | |
35d965d5 RS |
601 | } |
602 | \f | |
603 | /* Register and constant classes. */ | |
604 | ||
605 | /* Register classes: all ARM regs or all FPU regs---simple! */ | |
606 | enum reg_class | |
607 | { | |
608 | NO_REGS, | |
609 | FPU_REGS, | |
610 | GENERAL_REGS, | |
611 | ALL_REGS, | |
612 | LIM_REG_CLASSES | |
613 | }; | |
614 | ||
615 | #define N_REG_CLASSES (int) LIM_REG_CLASSES | |
616 | ||
617 | /* Give names of register classes as strings for dump file. */ | |
618 | #define REG_CLASS_NAMES \ | |
619 | { \ | |
620 | "NO_REGS", \ | |
621 | "FPU_REGS", \ | |
622 | "GENERAL_REGS", \ | |
623 | "ALL_REGS", \ | |
624 | } | |
625 | ||
626 | /* Define which registers fit in which classes. | |
627 | This is an initializer for a vector of HARD_REG_SET | |
628 | of length N_REG_CLASSES. */ | |
629 | #define REG_CLASS_CONTENTS \ | |
630 | { \ | |
ff9940b0 RE |
631 | 0x0000000, /* NO_REGS */ \ |
632 | 0x0FF0000, /* FPU_REGS */ \ | |
633 | 0x200FFFF, /* GENERAL_REGS */ \ | |
634 | 0x2FFFFFF /* ALL_REGS */ \ | |
35d965d5 RS |
635 | } |
636 | ||
637 | /* The same information, inverted: | |
638 | Return the class number of the smallest class containing | |
639 | reg number REGNO. This could be a conditional expression | |
640 | or could index an array. */ | |
ff9940b0 RE |
641 | #define REGNO_REG_CLASS(REGNO) \ |
642 | (((REGNO) < 16 || REGNO == FRAME_POINTER_REGNUM \ | |
643 | || REGNO == ARG_POINTER_REGNUM) \ | |
644 | ? GENERAL_REGS : (REGNO) == CC_REGNUM \ | |
645 | ? NO_REGS : FPU_REGS) | |
35d965d5 RS |
646 | |
647 | /* The class value for index registers, and the one for base regs. */ | |
648 | #define INDEX_REG_CLASS GENERAL_REGS | |
649 | #define BASE_REG_CLASS GENERAL_REGS | |
650 | ||
651 | /* Get reg_class from a letter such as appears in the machine description. | |
652 | We only need constraint `f' for FPU_REGS (`r' == GENERAL_REGS). */ | |
653 | #define REG_CLASS_FROM_LETTER(C) \ | |
654 | ((C)=='f' ? FPU_REGS : NO_REGS) | |
655 | ||
656 | /* The letters I, J, K, L and M in a register constraint string | |
657 | can be used to stand for particular ranges of immediate operands. | |
658 | This macro defines what the ranges are. | |
659 | C is the letter, and VALUE is a constant value. | |
660 | Return 1 if VALUE is in the range specified by C. | |
b4ac57ab | 661 | I: immediate arithmetic operand (i.e. 8 bits shifted as required). |
ff9940b0 | 662 | J: valid indexing constants. |
aef1764c | 663 | K: ~value ok in rhs argument of data operand. |
3967692c RE |
664 | L: -value ok in rhs argument of data operand. |
665 | M: 0..32, or a power of 2 (for shifts, or mult done by shift). */ | |
aef1764c RE |
666 | #define CONST_OK_FOR_LETTER_P(VALUE, C) \ |
667 | ((C) == 'I' ? const_ok_for_arm (VALUE) : \ | |
668 | (C) == 'J' ? ((VALUE) < 4096 && (VALUE) > -4096) : \ | |
669 | (C) == 'K' ? (const_ok_for_arm (~(VALUE))) : \ | |
3967692c RE |
670 | (C) == 'L' ? (const_ok_for_arm (-(VALUE))) : \ |
671 | (C) == 'M' ? (((VALUE >= 0 && VALUE <= 32)) \ | |
672 | || (((VALUE) & ((VALUE) - 1)) == 0)) \ | |
673 | : 0) | |
ff9940b0 RE |
674 | |
675 | /* For the ARM, `Q' means that this is a memory operand that is just | |
676 | an offset from a register. | |
677 | `S' means any symbol that has the SYMBOL_REF_FLAG set or a CONSTANT_POOL | |
678 | address. This means that the symbol is in the text segment and can be | |
679 | accessed without using a load. */ | |
680 | ||
681 | #define EXTRA_CONSTRAINT(OP, C) \ | |
682 | ((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG \ | |
008cf58a RE |
683 | : (C) == 'R' ? (GET_CODE (OP) == MEM \ |
684 | && GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \ | |
685 | && CONSTANT_POOL_ADDRESS_P (XEXP (OP, 0))) \ | |
686 | : (C) == 'S' ? (optimize > 0 && CONSTANT_ADDRESS_P (OP)) : 0) | |
ff9940b0 RE |
687 | |
688 | /* Constant letter 'G' for the FPU immediate constants. | |
689 | 'H' means the same constant negated. */ | |
690 | #define CONST_DOUBLE_OK_FOR_LETTER_P(X,C) \ | |
691 | ((C) == 'G' ? const_double_rtx_ok_for_fpu (X) \ | |
692 | : (C) == 'H' ? neg_const_double_rtx_ok_for_fpu (X) : 0) | |
35d965d5 RS |
693 | |
694 | /* Given an rtx X being reloaded into a reg required to be | |
695 | in class CLASS, return the class of reg to actually use. | |
696 | In general this is just CLASS; but on some machines | |
697 | in some cases it is preferable to use a more restrictive class. */ | |
698 | #define PREFERRED_RELOAD_CLASS(X, CLASS) (CLASS) | |
699 | ||
ff9940b0 RE |
700 | /* Return the register class of a scratch register needed to copy IN into |
701 | or out of a register in CLASS in MODE. If it can be done directly, | |
702 | NO_REGS is returned. */ | |
11c1a207 RE |
703 | #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,X) \ |
704 | (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \ | |
705 | ? GENERAL_REGS : NO_REGS) | |
ff9940b0 | 706 | |
2ce9c1b9 RE |
707 | /* If we need to load shorts byte-at-a-time, then we need a scratch. */ |
708 | #define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,X) \ | |
709 | (((MODE) == HImode && TARGET_SHORT_BY_BYTES && true_regnum (X) == -1) \ | |
710 | ? GENERAL_REGS : NO_REGS) | |
711 | ||
35d965d5 RS |
712 | /* Return the maximum number of consecutive registers |
713 | needed to represent mode MODE in a register of class CLASS. | |
714 | ARM regs are UNITS_PER_WORD bits while FPU regs can hold any FP mode */ | |
715 | #define CLASS_MAX_NREGS(CLASS, MODE) \ | |
716 | ((CLASS) == FPU_REGS ? 1 \ | |
717 | : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) | |
718 | ||
ff9940b0 | 719 | /* Moves between FPU_REGS and GENERAL_REGS are two memory insns. */ |
35d965d5 RS |
720 | #define REGISTER_MOVE_COST(CLASS1, CLASS2) \ |
721 | ((((CLASS1) == FPU_REGS && (CLASS2) != FPU_REGS) \ | |
722 | || ((CLASS2) == FPU_REGS && (CLASS1) != FPU_REGS)) \ | |
ff9940b0 | 723 | ? 20 : 2) |
35d965d5 RS |
724 | \f |
725 | /* Stack layout; function entry, exit and calling. */ | |
726 | ||
727 | /* Define this if pushing a word on the stack | |
728 | makes the stack pointer a smaller address. */ | |
729 | #define STACK_GROWS_DOWNWARD 1 | |
730 | ||
731 | /* Define this if the nominal address of the stack frame | |
732 | is at the high-address end of the local variables; | |
733 | that is, each additional local variable allocated | |
734 | goes at a more negative offset in the frame. */ | |
735 | #define FRAME_GROWS_DOWNWARD 1 | |
736 | ||
737 | /* Offset within stack frame to start allocating local variables at. | |
738 | If FRAME_GROWS_DOWNWARD, this is the offset to the END of the | |
739 | first local allocated. Otherwise, it is the offset to the BEGINNING | |
740 | of the first local allocated. */ | |
741 | #define STARTING_FRAME_OFFSET 0 | |
742 | ||
743 | /* If we generate an insn to push BYTES bytes, | |
744 | this says how many the stack pointer really advances by. */ | |
745 | #define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3) | |
746 | ||
747 | /* Offset of first parameter from the argument pointer register value. */ | |
748 | #define FIRST_PARM_OFFSET(FNDECL) 4 | |
749 | ||
750 | /* Value is the number of byte of arguments automatically | |
751 | popped when returning from a subroutine call. | |
8b109b37 | 752 | FUNDECL is the declaration node of the function (as a tree), |
35d965d5 RS |
753 | FUNTYPE is the data type of the function (as a tree), |
754 | or for a library call it is an identifier node for the subroutine name. | |
755 | SIZE is the number of bytes of arguments passed on the stack. | |
756 | ||
757 | On the ARM, the caller does not pop any of its arguments that were passed | |
758 | on the stack. */ | |
8b109b37 | 759 | #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0 |
35d965d5 RS |
760 | |
761 | /* Define how to find the value returned by a function. | |
762 | VALTYPE is the data type of the value (as a tree). | |
763 | If the precise function being called is known, FUNC is its FUNCTION_DECL; | |
764 | otherwise, FUNC is 0. */ | |
765 | #define FUNCTION_VALUE(VALTYPE, FUNC) \ | |
3ada8e17 DE |
766 | (GET_MODE_CLASS (TYPE_MODE (VALTYPE)) == MODE_FLOAT && TARGET_HARD_FLOAT \ |
767 | ? gen_rtx (REG, TYPE_MODE (VALTYPE), 16) \ | |
35d965d5 RS |
768 | : gen_rtx (REG, TYPE_MODE (VALTYPE), 0)) |
769 | ||
770 | /* Define how to find the value returned by a library function | |
771 | assuming the value has mode MODE. */ | |
772 | #define LIBCALL_VALUE(MODE) \ | |
3ada8e17 DE |
773 | (GET_MODE_CLASS (MODE) == MODE_FLOAT && TARGET_HARD_FLOAT \ |
774 | ? gen_rtx (REG, MODE, 16) \ | |
35d965d5 RS |
775 | : gen_rtx (REG, MODE, 0)) |
776 | ||
777 | /* 1 if N is a possible register number for a function value. | |
778 | On the ARM, only r0 and f0 can return results. */ | |
779 | #define FUNCTION_VALUE_REGNO_P(REGNO) \ | |
3ada8e17 | 780 | ((REGNO) == 0 || ((REGNO) == 16) && TARGET_HARD_FLOAT) |
35d965d5 | 781 | |
11c1a207 RE |
782 | /* How large values are returned */ |
783 | /* A C expression which can inhibit the returning of certain function values | |
784 | in registers, based on the type of value. */ | |
785 | #define RETURN_IN_MEMORY(TYPE) \ | |
786 | (TYPE_MODE ((TYPE)) == BLKmode || \ | |
787 | (AGGREGATE_TYPE_P ((TYPE)) && arm_return_in_memory ((TYPE)))) | |
788 | ||
789 | /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return | |
790 | values must be in memory. On the ARM, they need only do so if larger | |
791 | than a word, or if they contain elements offset from zero in the struct. */ | |
792 | #define DEFAULT_PCC_STRUCT_RETURN 0 | |
793 | ||
35d965d5 RS |
794 | /* Define where to put the arguments to a function. |
795 | Value is zero to push the argument on the stack, | |
796 | or a hard register in which to store the argument. | |
797 | ||
798 | MODE is the argument's machine mode. | |
799 | TYPE is the data type of the argument (as a tree). | |
800 | This is null for libcalls where that information may | |
801 | not be available. | |
802 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
803 | the preceding args and about the function being called. | |
804 | NAMED is nonzero if this argument is a named parameter | |
805 | (otherwise it is an extra parameter matching an ellipsis). | |
806 | ||
807 | On the ARM, normally the first 16 bytes are passed in registers r0-r3; all | |
808 | other arguments are passed on the stack. If (NAMED == 0) (which happens | |
809 | only in assign_parms, since SETUP_INCOMING_VARARGS is defined), say it is | |
810 | passed in the stack (function_prologue will indeed make it pass in the | |
811 | stack if necessary). */ | |
812 | #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ | |
813 | ((NAMED) \ | |
814 | ? ((CUM) >= 16 ? 0 : gen_rtx (REG, MODE, (CUM) / 4)) \ | |
815 | : 0) | |
816 | ||
817 | /* For an arg passed partly in registers and partly in memory, | |
818 | this is the number of registers used. | |
819 | For args passed entirely in registers or entirely in memory, zero. */ | |
820 | #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \ | |
821 | ((CUM) < 16 && 16 < (CUM) + ((MODE) != BLKmode \ | |
822 | ? GET_MODE_SIZE (MODE) \ | |
823 | : int_size_in_bytes (TYPE)) \ | |
824 | ? 4 - (CUM) / 4 : 0) | |
825 | ||
826 | /* A C type for declaring a variable that is used as the first argument of | |
827 | `FUNCTION_ARG' and other related values. For some target machines, the | |
828 | type `int' suffices and can hold the number of bytes of argument so far. | |
829 | ||
830 | On the ARM, this is the number of bytes of arguments scanned so far. */ | |
831 | #define CUMULATIVE_ARGS int | |
832 | ||
833 | /* Initialize a variable CUM of type CUMULATIVE_ARGS | |
834 | for a call to a function whose data type is FNTYPE. | |
835 | For a library call, FNTYPE is 0. | |
836 | On the ARM, the offset starts at 0. */ | |
2c7ee1a6 | 837 | #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \ |
ff9940b0 | 838 | ((CUM) = (((FNTYPE) && aggregate_value_p (TREE_TYPE ((FNTYPE)))) ? 4 : 0)) |
35d965d5 RS |
839 | |
840 | /* Update the data in CUM to advance over an argument | |
841 | of mode MODE and data type TYPE. | |
842 | (TYPE is null for libcalls where that information may not be available.) */ | |
843 | #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ | |
844 | (CUM) += ((MODE) != BLKmode \ | |
845 | ? (GET_MODE_SIZE (MODE) + 3) & ~3 \ | |
846 | : (int_size_in_bytes (TYPE) + 3) & ~3) \ | |
847 | ||
848 | /* 1 if N is a possible register number for function argument passing. | |
849 | On the ARM, r0-r3 are used to pass args. */ | |
850 | #define FUNCTION_ARG_REGNO_P(REGNO) \ | |
851 | ((REGNO) >= 0 && (REGNO) <= 3) | |
852 | ||
853 | /* Perform any actions needed for a function that is receiving a variable | |
854 | number of arguments. CUM is as above. MODE and TYPE are the mode and type | |
855 | of the current parameter. PRETEND_SIZE is a variable that should be set to | |
856 | the amount of stack that must be pushed by the prolog to pretend that our | |
857 | caller pushed it. | |
858 | ||
859 | Normally, this macro will push all remaining incoming registers on the | |
860 | stack and set PRETEND_SIZE to the length of the registers pushed. | |
861 | ||
862 | On the ARM, PRETEND_SIZE is set in order to have the prologue push the last | |
863 | named arg and all anonymous args onto the stack. | |
864 | XXX I know the prologue shouldn't be pushing registers, but it is faster | |
865 | that way. */ | |
866 | #define SETUP_INCOMING_VARARGS(CUM, MODE, TYPE, PRETEND_SIZE, NO_RTL) \ | |
867 | { \ | |
868 | extern int current_function_anonymous_args; \ | |
869 | current_function_anonymous_args = 1; \ | |
870 | if ((CUM) < 16) \ | |
871 | (PRETEND_SIZE) = 16 - (CUM); \ | |
872 | } | |
873 | ||
874 | /* Generate assembly output for the start of a function. */ | |
875 | #define FUNCTION_PROLOGUE(STREAM, SIZE) \ | |
008cf58a | 876 | output_func_prologue ((STREAM), (SIZE)) |
35d965d5 RS |
877 | |
878 | /* Call the function profiler with a given profile label. The Acorn compiler | |
879 | puts this BEFORE the prolog but gcc pust it afterwards. The ``mov ip,lr'' | |
880 | seems like a good idea to stick with cc convention. ``prof'' doesn't seem | |
881 | to mind about this! */ | |
4eda77ec RE |
882 | #define FUNCTION_PROFILER(STREAM,LABELNO) \ |
883 | { \ | |
c383667d | 884 | fprintf(STREAM, "\tmov\t%sip, %slr\n", REGISTER_PREFIX, REGISTER_PREFIX); \ |
4eda77ec RE |
885 | fprintf(STREAM, "\tbl\tmcount\n"); \ |
886 | fprintf(STREAM, "\t.word\tLP%d\n", (LABELNO)); \ | |
35d965d5 RS |
887 | } |
888 | ||
889 | /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, | |
890 | the stack pointer does not matter. The value is tested only in | |
891 | functions that have frame pointers. | |
892 | No definition is equivalent to always zero. | |
893 | ||
894 | On the ARM, the function epilogue recovers the stack pointer from the | |
895 | frame. */ | |
896 | #define EXIT_IGNORE_STACK 1 | |
897 | ||
898 | /* Generate the assembly code for function exit. */ | |
899 | #define FUNCTION_EPILOGUE(STREAM, SIZE) \ | |
008cf58a | 900 | output_func_epilogue ((STREAM), (SIZE)) |
35d965d5 RS |
901 | |
902 | /* Determine if the epilogue should be output as RTL. | |
903 | You should override this if you define FUNCTION_EXTRA_EPILOGUE. */ | |
ff9940b0 RE |
904 | #define USE_RETURN_INSN use_return_insn () |
905 | ||
906 | /* Definitions for register eliminations. | |
907 | ||
908 | This is an array of structures. Each structure initializes one pair | |
909 | of eliminable registers. The "from" register number is given first, | |
910 | followed by "to". Eliminations of the same "from" register are listed | |
911 | in order of preference. | |
912 | ||
913 | We have two registers that can be eliminated on the ARM. First, the | |
914 | arg pointer register can often be eliminated in favor of the stack | |
915 | pointer register. Secondly, the pseudo frame pointer register can always | |
916 | be eliminated; it is replaced with either the stack or the real frame | |
917 | pointer. */ | |
918 | ||
919 | #define ELIMINABLE_REGS \ | |
920 | {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
921 | {ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ | |
922 | {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
923 | {FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} | |
924 | ||
925 | /* Given FROM and TO register numbers, say whether this elimination is allowed. | |
926 | Frame pointer elimination is automatically handled. | |
927 | ||
928 | All eliminations are permissible. Note that ARG_POINTER_REGNUM and | |
abc95ed3 | 929 | HARD_FRAME_POINTER_REGNUM are in fact the same thing. If we need a frame |
ff9940b0 RE |
930 | pointer, we must eliminate FRAME_POINTER_REGNUM into |
931 | HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM. */ | |
932 | #define CAN_ELIMINATE(FROM, TO) \ | |
933 | (((TO) == STACK_POINTER_REGNUM && frame_pointer_needed) ? 0 : 1) | |
934 | ||
935 | /* Define the offset between two registers, one to be eliminated, and the other | |
936 | its replacement, at the start of a routine. */ | |
937 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ | |
938 | { \ | |
3967692c | 939 | int volatile_func = arm_volatile_func (); \ |
ff9940b0 RE |
940 | if ((FROM) == ARG_POINTER_REGNUM && (TO) == HARD_FRAME_POINTER_REGNUM)\ |
941 | (OFFSET) = 0; \ | |
942 | else if ((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM)\ | |
943 | (OFFSET) = (get_frame_size () + 3 & ~3); \ | |
944 | else \ | |
945 | { \ | |
946 | int regno; \ | |
947 | int offset = 12; \ | |
008cf58a | 948 | int saved_hard_reg = 0; \ |
ff9940b0 | 949 | \ |
3967692c RE |
950 | if (! volatile_func) \ |
951 | { \ | |
952 | for (regno = 0; regno <= 10; regno++) \ | |
953 | if (regs_ever_live[regno] && ! call_used_regs[regno]) \ | |
954 | saved_hard_reg = 1, offset += 4; \ | |
955 | for (regno = 16; regno <=23; regno++) \ | |
956 | if (regs_ever_live[regno] && ! call_used_regs[regno]) \ | |
957 | offset += 12; \ | |
958 | } \ | |
ff9940b0 RE |
959 | if ((FROM) == FRAME_POINTER_REGNUM) \ |
960 | (OFFSET) = -offset; \ | |
961 | else \ | |
962 | { \ | |
bd4d60ce | 963 | if (! frame_pointer_needed) \ |
ff9940b0 | 964 | offset -= 16; \ |
3967692c | 965 | if (! volatile_func && (regs_ever_live[14] || saved_hard_reg)) \ |
ff9940b0 RE |
966 | offset += 4; \ |
967 | (OFFSET) = (get_frame_size () + 3 & ~3) + offset; \ | |
968 | } \ | |
969 | } \ | |
970 | } | |
35d965d5 | 971 | |
35d965d5 RS |
972 | /* Output assembler code for a block containing the constant parts |
973 | of a trampoline, leaving space for the variable parts. | |
974 | ||
975 | On the ARM, (if r8 is the static chain regnum, and remembering that | |
976 | referencing pc adds an offset of 8) the trampoline looks like: | |
977 | ldr r8, [pc, #0] | |
978 | ldr pc, [pc] | |
979 | .word static chain value | |
11c1a207 RE |
980 | .word function's address |
981 | ??? FIXME: When the trampoline returns, r8 will be clobbered. */ | |
4eda77ec RE |
982 | #define TRAMPOLINE_TEMPLATE(FILE) \ |
983 | { \ | |
c383667d DE |
984 | fprintf ((FILE), "\tldr\t%sr8, [%spc, #0]\n", \ |
985 | REGISTER_PREFIX, REGISTER_PREFIX); \ | |
986 | fprintf ((FILE), "\tldr\t%spc, [%spc, #0]\n", \ | |
987 | REGISTER_PREFIX, REGISTER_PREFIX); \ | |
4eda77ec RE |
988 | fprintf ((FILE), "\t.word\t0\n"); \ |
989 | fprintf ((FILE), "\t.word\t0\n"); \ | |
35d965d5 RS |
990 | } |
991 | ||
992 | /* Length in units of the trampoline for entering a nested function. */ | |
993 | #define TRAMPOLINE_SIZE 16 | |
994 | ||
995 | /* Alignment required for a trampoline in units. */ | |
996 | #define TRAMPOLINE_ALIGN 4 | |
997 | ||
998 | /* Emit RTL insns to initialize the variable parts of a trampoline. | |
999 | FNADDR is an RTX for the address of the function's pure code. | |
1000 | CXT is an RTX for the static chain value for the function. */ | |
1001 | #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ | |
1002 | { \ | |
1003 | emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 8)), \ | |
1004 | (CXT)); \ | |
1005 | emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 12)), \ | |
1006 | (FNADDR)); \ | |
1007 | } | |
1008 | ||
35d965d5 RS |
1009 | \f |
1010 | /* Addressing modes, and classification of registers for them. */ | |
1011 | ||
1012 | #define HAVE_POST_INCREMENT 1 | |
1013 | #define HAVE_PRE_INCREMENT 1 | |
1014 | #define HAVE_POST_DECREMENT 1 | |
1015 | #define HAVE_PRE_DECREMENT 1 | |
1016 | ||
1017 | /* Macros to check register numbers against specific register classes. */ | |
1018 | ||
1019 | /* These assume that REGNO is a hard or pseudo reg number. | |
1020 | They give nonzero only if REGNO is a hard reg of the suitable class | |
1021 | or a pseudo reg currently allocated to a suitable hard reg. | |
1022 | Since they use reg_renumber, they are safe only once reg_renumber | |
1023 | has been allocated, which happens in local-alloc.c. | |
1024 | ||
1025 | On the ARM, don't allow the pc to be used. */ | |
ff9940b0 RE |
1026 | #define REGNO_OK_FOR_BASE_P(REGNO) \ |
1027 | ((REGNO) < 15 || (REGNO) == FRAME_POINTER_REGNUM \ | |
1028 | || (REGNO) == ARG_POINTER_REGNUM \ | |
1029 | || (unsigned) reg_renumber[(REGNO)] < 15 \ | |
1030 | || (unsigned) reg_renumber[(REGNO)] == FRAME_POINTER_REGNUM \ | |
1031 | || (unsigned) reg_renumber[(REGNO)] == ARG_POINTER_REGNUM) | |
1032 | #define REGNO_OK_FOR_INDEX_P(REGNO) \ | |
35d965d5 RS |
1033 | REGNO_OK_FOR_BASE_P(REGNO) |
1034 | ||
1035 | /* Maximum number of registers that can appear in a valid memory address. | |
ff9940b0 RE |
1036 | Shifts in addresses can't be by a register. */ |
1037 | ||
1038 | #define MAX_REGS_PER_ADDRESS 2 | |
35d965d5 RS |
1039 | |
1040 | /* Recognize any constant value that is a valid address. */ | |
1041 | /* XXX We can address any constant, eventually... */ | |
11c1a207 RE |
1042 | |
1043 | #ifdef AOF_ASSEMBLER | |
1044 | ||
1045 | #define CONSTANT_ADDRESS_P(X) \ | |
1046 | (GET_CODE (X) == SYMBOL_REF \ | |
1047 | && CONSTANT_POOL_ADDRESS_P (X)) | |
1048 | ||
1049 | #else | |
35d965d5 | 1050 | |
008cf58a RE |
1051 | #define CONSTANT_ADDRESS_P(X) \ |
1052 | (GET_CODE (X) == SYMBOL_REF \ | |
1053 | && (CONSTANT_POOL_ADDRESS_P (X) \ | |
1054 | || (optimize > 0 && SYMBOL_REF_FLAG (X)))) | |
35d965d5 | 1055 | |
11c1a207 RE |
1056 | #endif /* AOF_ASSEMBLER */ |
1057 | ||
35d965d5 RS |
1058 | /* Nonzero if the constant value X is a legitimate general operand. |
1059 | It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. | |
1060 | ||
1061 | On the ARM, allow any integer (invalid ones are removed later by insn | |
1062 | patterns), nice doubles and symbol_refs which refer to the function's | |
1063 | constant pool XXX. */ | |
11c1a207 | 1064 | #define LEGITIMATE_CONSTANT_P(X) (! label_mentioned_p (X)) |
ff9940b0 RE |
1065 | |
1066 | /* Symbols in the text segment can be accessed without indirecting via the | |
1067 | constant pool; it may take an extra binary operation, but this is still | |
008cf58a RE |
1068 | faster than indirecting via memory. Don't do this when not optimizing, |
1069 | since we won't be calculating al of the offsets necessary to do this | |
1070 | simplification. */ | |
11c1a207 RE |
1071 | /* This doesn't work with AOF syntax, since the string table may be in |
1072 | a different AREA. */ | |
1073 | #ifndef AOF_ASSEMBLER | |
ff9940b0 RE |
1074 | #define ENCODE_SECTION_INFO(decl) \ |
1075 | { \ | |
008cf58a | 1076 | if (optimize > 0 && TREE_CONSTANT (decl) \ |
ff9940b0 | 1077 | && (!flag_writable_strings || TREE_CODE (decl) != STRING_CST)) \ |
228b6a3f RS |
1078 | { \ |
1079 | rtx rtl = (TREE_CODE_CLASS (TREE_CODE (decl)) != 'd' \ | |
1080 | ? TREE_CST_RTL (decl) : DECL_RTL (decl)); \ | |
1081 | SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1; \ | |
1082 | } \ | |
ff9940b0 | 1083 | } |
11c1a207 | 1084 | #endif |
35d965d5 RS |
1085 | /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx |
1086 | and check its validity for a certain class. | |
1087 | We have two alternate definitions for each of them. | |
1088 | The usual definition accepts all pseudo regs; the other rejects | |
1089 | them unless they have been allocated suitable hard regs. | |
1090 | The symbol REG_OK_STRICT causes the latter definition to be used. */ | |
1091 | #ifndef REG_OK_STRICT | |
ff9940b0 | 1092 | |
35d965d5 RS |
1093 | /* Nonzero if X is a hard reg that can be used as a base reg |
1094 | or if it is a pseudo reg. */ | |
ff9940b0 RE |
1095 | #define REG_OK_FOR_BASE_P(X) \ |
1096 | (REGNO (X) < 16 || REGNO (X) >= FIRST_PSEUDO_REGISTER \ | |
1097 | || REGNO (X) == FRAME_POINTER_REGNUM || REGNO (X) == ARG_POINTER_REGNUM) | |
1098 | ||
35d965d5 RS |
1099 | /* Nonzero if X is a hard reg that can be used as an index |
1100 | or if it is a pseudo reg. */ | |
1101 | #define REG_OK_FOR_INDEX_P(X) \ | |
1102 | REG_OK_FOR_BASE_P(X) | |
ff9940b0 RE |
1103 | |
1104 | #define REG_OK_FOR_PRE_POST_P(X) \ | |
1105 | (REGNO (X) < 16 || REGNO (X) >= FIRST_PSEUDO_REGISTER \ | |
1106 | || REGNO (X) == FRAME_POINTER_REGNUM || REGNO (X) == ARG_POINTER_REGNUM) | |
1107 | ||
35d965d5 | 1108 | #else |
ff9940b0 | 1109 | |
35d965d5 RS |
1110 | /* Nonzero if X is a hard reg that can be used as a base reg. */ |
1111 | #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) | |
ff9940b0 | 1112 | |
35d965d5 RS |
1113 | /* Nonzero if X is a hard reg that can be used as an index. */ |
1114 | #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) | |
ff9940b0 RE |
1115 | |
1116 | #define REG_OK_FOR_PRE_POST_P(X) \ | |
1117 | (REGNO (X) < 16 || (unsigned) reg_renumber[REGNO (X)] < 16 \ | |
1118 | || REGNO (X) == FRAME_POINTER_REGNUM || REGNO (X) == ARG_POINTER_REGNUM \ | |
1119 | || (unsigned) reg_renumber[REGNO (X)] == FRAME_POINTER_REGNUM \ | |
1120 | || (unsigned) reg_renumber[REGNO (X)] == ARG_POINTER_REGNUM) | |
1121 | ||
35d965d5 RS |
1122 | #endif |
1123 | \f | |
1124 | /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression | |
1125 | that is a valid memory address for an instruction. | |
1126 | The MODE argument is the machine mode for the MEM expression | |
1127 | that wants to use this address. | |
1128 | ||
1129 | The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */ | |
1130 | #define BASE_REGISTER_RTX_P(X) \ | |
1131 | (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) | |
1132 | ||
1133 | #define INDEX_REGISTER_RTX_P(X) \ | |
1134 | (GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) | |
1135 | ||
1136 | /* A C statement (sans semicolon) to jump to LABEL for legitimate index RTXs | |
1137 | used by the macro GO_IF_LEGITIMATE_ADDRESS. Floating point indices can | |
1138 | only be small constants. */ | |
ff9940b0 | 1139 | #define GO_IF_LEGITIMATE_INDEX(MODE, BASE_REGNO, INDEX, LABEL) \ |
4d01c30f RS |
1140 | do \ |
1141 | { \ | |
008cf58a RE |
1142 | HOST_WIDE_INT range; \ |
1143 | enum rtx_code code = GET_CODE (INDEX); \ | |
4d01c30f | 1144 | \ |
11c1a207 | 1145 | if (TARGET_HARD_FLOAT && GET_MODE_CLASS (MODE) == MODE_FLOAT) \ |
ff9940b0 RE |
1146 | { \ |
1147 | if (code == CONST_INT && INTVAL (INDEX) < 1024 \ | |
1148 | && INTVAL (INDEX) > -1024 \ | |
1149 | && (INTVAL (INDEX) & 3) == 0) \ | |
1150 | goto LABEL; \ | |
1151 | } \ | |
4d01c30f RS |
1152 | else \ |
1153 | { \ | |
ff9940b0 | 1154 | if (INDEX_REGISTER_RTX_P (INDEX) && GET_MODE_SIZE (MODE) <= 4) \ |
4d01c30f | 1155 | goto LABEL; \ |
11c1a207 RE |
1156 | if (GET_MODE_SIZE (MODE) <= 4 && code == MULT \ |
1157 | && (! arm_arch4 || (MODE) != HImode)) \ | |
4d01c30f RS |
1158 | { \ |
1159 | rtx xiop0 = XEXP (INDEX, 0); \ | |
1160 | rtx xiop1 = XEXP (INDEX, 1); \ | |
1161 | if (INDEX_REGISTER_RTX_P (xiop0) \ | |
1162 | && power_of_two_operand (xiop1, SImode)) \ | |
1163 | goto LABEL; \ | |
1164 | if (INDEX_REGISTER_RTX_P (xiop1) \ | |
1165 | && power_of_two_operand (xiop0, SImode)) \ | |
1166 | goto LABEL; \ | |
1167 | } \ | |
ff9940b0 | 1168 | if (GET_MODE_SIZE (MODE) <= 4 \ |
996a5f59 | 1169 | && (code == LSHIFTRT || code == ASHIFTRT \ |
11c1a207 RE |
1170 | || code == ASHIFT || code == ROTATERT) \ |
1171 | && (! arm_arch4 || (MODE) != HImode)) \ | |
ff9940b0 RE |
1172 | { \ |
1173 | rtx op = XEXP (INDEX, 1); \ | |
1174 | if (INDEX_REGISTER_RTX_P (XEXP (INDEX, 0)) \ | |
1175 | && GET_CODE (op) == CONST_INT && INTVAL (op) > 0 \ | |
1176 | && INTVAL (op) <= 31) \ | |
1177 | goto LABEL; \ | |
1178 | } \ | |
11c1a207 | 1179 | range = (MODE) == HImode ? (arm_arch4 ? 256 : 4095) : 4096; \ |
ff9940b0 RE |
1180 | if (code == CONST_INT && INTVAL (INDEX) < range \ |
1181 | && INTVAL (INDEX) > -range) \ | |
1182 | goto LABEL; \ | |
4d01c30f | 1183 | } \ |
35d965d5 RS |
1184 | } while (0) |
1185 | ||
1186 | /* Jump to LABEL if X is a valid address RTX. This must also take | |
1187 | REG_OK_STRICT into account when deciding about valid registers, but it uses | |
1188 | the above macros so we are in luck. Allow REG, REG+REG, REG+INDEX, | |
1189 | INDEX+REG, REG-INDEX, and non floating SYMBOL_REF to the constant pool. | |
ff9940b0 RE |
1190 | Allow REG-only and AUTINC-REG if handling TImode or HImode. Other symbol |
1191 | refs must be forced though a static cell to ensure addressability. */ | |
11c1a207 | 1192 | #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \ |
35d965d5 RS |
1193 | { \ |
1194 | if (BASE_REGISTER_RTX_P (X)) \ | |
1195 | goto LABEL; \ | |
1196 | else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \ | |
1197 | && GET_CODE (XEXP (X, 0)) == REG \ | |
1198 | && REG_OK_FOR_PRE_POST_P (XEXP (X, 0))) \ | |
1199 | goto LABEL; \ | |
11c1a207 RE |
1200 | else if (GET_MODE_SIZE (MODE) >= 4 && reload_completed \ |
1201 | && (GET_CODE (X) == LABEL_REF \ | |
1202 | || (GET_CODE (X) == CONST \ | |
1203 | && GET_CODE (XEXP ((X), 0)) == PLUS \ | |
1204 | && GET_CODE (XEXP (XEXP ((X), 0), 0)) == LABEL_REF \ | |
1205 | && GET_CODE (XEXP (XEXP ((X), 0), 1)) == CONST_INT)))\ | |
1206 | goto LABEL; \ | |
35d965d5 RS |
1207 | else if ((MODE) == TImode) \ |
1208 | ; \ | |
11c1a207 RE |
1209 | else if ((MODE) == DImode || (TARGET_SOFT_FLOAT && (MODE) == DFmode)) \ |
1210 | { \ | |
1211 | if (GET_CODE (X) == PLUS && BASE_REGISTER_RTX_P (XEXP (X, 0)) \ | |
1212 | && GET_CODE (XEXP (X, 1)) == CONST_INT) \ | |
1213 | { \ | |
1214 | HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \ | |
1215 | if (val == 4 || val == -4 || val == -8) \ | |
1216 | goto LABEL; \ | |
1217 | } \ | |
1218 | } \ | |
35d965d5 RS |
1219 | else if (GET_CODE (X) == PLUS) \ |
1220 | { \ | |
1221 | rtx xop0 = XEXP(X,0); \ | |
1222 | rtx xop1 = XEXP(X,1); \ | |
1223 | \ | |
1224 | if (BASE_REGISTER_RTX_P (xop0)) \ | |
1225 | GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop0), xop1, LABEL); \ | |
1226 | else if (BASE_REGISTER_RTX_P (xop1)) \ | |
1227 | GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop1), xop0, LABEL); \ | |
1228 | } \ | |
1229 | else if (GET_CODE (X) == MINUS) \ | |
1230 | { \ | |
1231 | rtx xop0 = XEXP (X,0); \ | |
1232 | rtx xop1 = XEXP (X,1); \ | |
1233 | \ | |
1234 | if (BASE_REGISTER_RTX_P (xop0)) \ | |
1235 | GO_IF_LEGITIMATE_INDEX (MODE, -1, xop1, LABEL); \ | |
1236 | } \ | |
1237 | else if (GET_MODE_CLASS (MODE) != MODE_FLOAT \ | |
1238 | && GET_CODE (X) == SYMBOL_REF \ | |
1239 | && CONSTANT_POOL_ADDRESS_P (X)) \ | |
1240 | goto LABEL; \ | |
1241 | else if ((GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_DEC) \ | |
11c1a207 | 1242 | && (GET_MODE_SIZE (MODE) <= 4) \ |
35d965d5 RS |
1243 | && GET_CODE (XEXP (X, 0)) == REG \ |
1244 | && REG_OK_FOR_PRE_POST_P (XEXP (X, 0))) \ | |
1245 | goto LABEL; \ | |
1246 | } | |
1247 | \f | |
1248 | /* Try machine-dependent ways of modifying an illegitimate address | |
1249 | to be legitimate. If we find one, return the new, valid address. | |
1250 | This macro is used in only one place: `memory_address' in explow.c. | |
1251 | ||
1252 | OLDX is the address as it was before break_out_memory_refs was called. | |
1253 | In some cases it is useful to look at this to decide what needs to be done. | |
1254 | ||
1255 | MODE and WIN are passed so that this macro can use | |
1256 | GO_IF_LEGITIMATE_ADDRESS. | |
1257 | ||
1258 | It is always safe for this macro to do nothing. It exists to recognize | |
1259 | opportunities to optimize the output. | |
1260 | ||
1261 | On the ARM, try to convert [REG, #BIGCONST] | |
1262 | into ADD BASE, REG, #UPPERCONST and [BASE, #VALIDCONST], | |
1263 | where VALIDCONST == 0 in case of TImode. */ | |
3967692c RE |
1264 | #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \ |
1265 | { \ | |
1266 | if (GET_CODE (X) == PLUS) \ | |
1267 | { \ | |
1268 | rtx xop0 = XEXP (X, 0); \ | |
1269 | rtx xop1 = XEXP (X, 1); \ | |
1270 | \ | |
11c1a207 | 1271 | if (CONSTANT_P (xop0) && ! symbol_mentioned_p (xop0)) \ |
3967692c | 1272 | xop0 = force_reg (SImode, xop0); \ |
11c1a207 | 1273 | if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1)) \ |
3967692c RE |
1274 | xop1 = force_reg (SImode, xop1); \ |
1275 | if (BASE_REGISTER_RTX_P (xop0) && GET_CODE (xop1) == CONST_INT) \ | |
1276 | { \ | |
1277 | HOST_WIDE_INT n, low_n; \ | |
1278 | rtx base_reg, val; \ | |
1279 | n = INTVAL (xop1); \ | |
1280 | \ | |
11c1a207 | 1281 | if (MODE == DImode || (TARGET_SOFT_FLOAT && MODE == DFmode)) \ |
3967692c RE |
1282 | { \ |
1283 | low_n = n & 0x0f; \ | |
1284 | n &= ~0x0f; \ | |
1285 | if (low_n > 4) \ | |
1286 | { \ | |
1287 | n += 16; \ | |
1288 | low_n -= 16; \ | |
1289 | } \ | |
1290 | } \ | |
1291 | else \ | |
1292 | { \ | |
1293 | low_n = ((MODE) == TImode ? 0 \ | |
1294 | : n >= 0 ? (n & 0xfff) : -((-n) & 0xfff)); \ | |
1295 | n -= low_n; \ | |
1296 | } \ | |
1297 | base_reg = gen_reg_rtx (SImode); \ | |
1298 | val = force_operand (gen_rtx (PLUS, SImode, xop0, \ | |
1299 | GEN_INT (n)), NULL_RTX); \ | |
1300 | emit_move_insn (base_reg, val); \ | |
1301 | (X) = (low_n == 0 ? base_reg \ | |
1302 | : gen_rtx (PLUS, SImode, base_reg, GEN_INT (low_n))); \ | |
1303 | } \ | |
1304 | else if (xop0 != XEXP (X, 0) || xop1 != XEXP (x, 1)) \ | |
1305 | (X) = gen_rtx (PLUS, SImode, xop0, xop1); \ | |
1306 | } \ | |
1307 | else if (GET_CODE (X) == MINUS) \ | |
1308 | { \ | |
1309 | rtx xop0 = XEXP (X, 0); \ | |
1310 | rtx xop1 = XEXP (X, 1); \ | |
1311 | \ | |
1312 | if (CONSTANT_P (xop0)) \ | |
1313 | xop0 = force_reg (SImode, xop0); \ | |
11c1a207 | 1314 | if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1)) \ |
3967692c RE |
1315 | xop1 = force_reg (SImode, xop1); \ |
1316 | if (xop0 != XEXP (X, 0) || xop1 != XEXP (X, 1)) \ | |
1317 | (X) = gen_rtx (MINUS, SImode, xop0, xop1); \ | |
1318 | } \ | |
1319 | if (memory_address_p (MODE, X)) \ | |
1320 | goto WIN; \ | |
35d965d5 RS |
1321 | } |
1322 | ||
1323 | /* Go to LABEL if ADDR (a legitimate address expression) | |
1324 | has an effect that depends on the machine mode it is used for. */ | |
1325 | #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \ | |
1326 | { \ | |
1327 | if (GET_CODE(ADDR) == PRE_DEC || GET_CODE(ADDR) == POST_DEC \ | |
1328 | || GET_CODE(ADDR) == PRE_INC || GET_CODE(ADDR) == POST_INC) \ | |
1329 | goto LABEL; \ | |
1330 | } | |
1331 | \f | |
1332 | /* Specify the machine mode that this machine uses | |
1333 | for the index in the tablejump instruction. */ | |
1334 | #define CASE_VECTOR_MODE SImode | |
1335 | ||
1336 | /* Define this if the tablejump instruction expects the table | |
1337 | to contain offsets from the address of the table. | |
1338 | Do not define this if the table should contain absolute addresses. */ | |
1339 | /* #define CASE_VECTOR_PC_RELATIVE */ | |
1340 | ||
1341 | /* Specify the tree operation to be used to convert reals to integers. */ | |
1342 | #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR | |
1343 | ||
1344 | /* This is the kind of divide that is easiest to do in the general case. */ | |
1345 | #define EASY_DIV_EXPR TRUNC_DIV_EXPR | |
1346 | ||
ff9940b0 RE |
1347 | /* signed 'char' is most compatible, but RISC OS wants it unsigned. |
1348 | unsigned is probably best, but may break some code. */ | |
1349 | #ifndef DEFAULT_SIGNED_CHAR | |
3967692c | 1350 | #define DEFAULT_SIGNED_CHAR 0 |
35d965d5 RS |
1351 | #endif |
1352 | ||
1353 | /* Don't cse the address of the function being compiled. */ | |
1354 | #define NO_RECURSIVE_FUNCTION_CSE 1 | |
1355 | ||
1356 | /* Max number of bytes we can move from memory to memory | |
d17ce9af TG |
1357 | in one reasonably fast instruction. */ |
1358 | #define MOVE_MAX 4 | |
35d965d5 | 1359 | |
ff9940b0 RE |
1360 | /* Define if operations between registers always perform the operation |
1361 | on the full register even if a narrower mode is specified. */ | |
1362 | #define WORD_REGISTER_OPERATIONS | |
1363 | ||
1364 | /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD | |
1365 | will either zero-extend or sign-extend. The value of this macro should | |
1366 | be the code that says which one of the two operations is implicitly | |
1367 | done, NIL if none. */ | |
9c872872 | 1368 | #define LOAD_EXTEND_OP(MODE) \ |
11c1a207 | 1369 | ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \ |
9c872872 | 1370 | : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : NIL)) |
ff9940b0 | 1371 | |
35d965d5 RS |
1372 | /* Define this if zero-extension is slow (more than one real instruction). |
1373 | On the ARM, it is more than one instruction only if not fetching from | |
1374 | memory. */ | |
1375 | /* #define SLOW_ZERO_EXTEND */ | |
1376 | ||
1377 | /* Nonzero if access to memory by bytes is slow and undesirable. */ | |
1378 | #define SLOW_BYTE_ACCESS 0 | |
1379 | ||
1380 | /* Immediate shift counts are truncated by the output routines (or was it | |
1381 | the assembler?). Shift counts in a register are truncated by ARM. Note | |
1382 | that the native compiler puts too large (> 32) immediate shift counts | |
1383 | into a register and shifts by the register, letting the ARM decide what | |
1384 | to do instead of doing that itself. */ | |
ff9940b0 RE |
1385 | /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that |
1386 | code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y). | |
1387 | On the arm, Y in a register is used modulo 256 for the shift. Only for | |
1388 | rotates is modulo 32 used. */ | |
1389 | /* #define SHIFT_COUNT_TRUNCATED 1 */ | |
35d965d5 | 1390 | |
35d965d5 RS |
1391 | /* All integers have the same format so truncation is easy. */ |
1392 | #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1 | |
1393 | ||
1394 | /* Calling from registers is a massive pain. */ | |
1395 | #define NO_FUNCTION_CSE 1 | |
1396 | ||
1397 | /* Chars and shorts should be passed as ints. */ | |
1398 | #define PROMOTE_PROTOTYPES 1 | |
1399 | ||
35d965d5 RS |
1400 | /* The machine modes of pointers and functions */ |
1401 | #define Pmode SImode | |
1402 | #define FUNCTION_MODE Pmode | |
1403 | ||
1404 | /* The structure type of the machine dependent info field of insns | |
1405 | No uses for this yet. */ | |
1406 | /* #define INSN_MACHINE_INFO struct machine_info */ | |
1407 | ||
1408 | /* The relative costs of various types of constants. Note that cse.c defines | |
1409 | REG = 1, SUBREG = 2, any node = (2 + sum of subnodes). */ | |
ff9940b0 RE |
1410 | #define CONST_COSTS(RTX, CODE, OUTER_CODE) \ |
1411 | case CONST_INT: \ | |
1412 | if (const_ok_for_arm (INTVAL (RTX))) \ | |
1413 | return (OUTER_CODE) == SET ? 2 : -1; \ | |
1414 | else if (OUTER_CODE == AND \ | |
1415 | && const_ok_for_arm (~INTVAL (RTX))) \ | |
1416 | return -1; \ | |
1417 | else if ((OUTER_CODE == COMPARE \ | |
1418 | || OUTER_CODE == PLUS || OUTER_CODE == MINUS) \ | |
1419 | && const_ok_for_arm (-INTVAL (RTX))) \ | |
1420 | return -1; \ | |
1421 | else \ | |
1422 | return 5; \ | |
1423 | case CONST: \ | |
1424 | case LABEL_REF: \ | |
1425 | case SYMBOL_REF: \ | |
1426 | return 6; \ | |
1427 | case CONST_DOUBLE: \ | |
1428 | if (const_double_rtx_ok_for_fpu (RTX)) \ | |
1429 | return (OUTER_CODE) == SET ? 2 : -1; \ | |
1430 | else if (((OUTER_CODE) == COMPARE || (OUTER_CODE) == PLUS) \ | |
1431 | && neg_const_double_rtx_ok_for_fpu (RTX)) \ | |
1432 | return -1; \ | |
1433 | return(7); | |
1434 | ||
3967692c RE |
1435 | #define ARM_FRAME_RTX(X) \ |
1436 | ((X) == frame_pointer_rtx || (X) == stack_pointer_rtx \ | |
1437 | || (X) == arg_pointer_rtx) | |
1438 | ||
11c1a207 RE |
1439 | #define RTX_COSTS(X,CODE,OUTER_CODE) \ |
1440 | default: \ | |
3967692c | 1441 | return arm_rtx_costs (X, CODE, OUTER_CODE); |
ff9940b0 RE |
1442 | |
1443 | /* Moves to and from memory are quite expensive */ | |
1444 | #define MEMORY_MOVE_COST(MODE) 10 | |
1445 | ||
3967692c | 1446 | /* All address computations that can be done are free, but rtx cost returns |
ddd5a7c1 | 1447 | the same for practically all of them. So we weight the different types |
3967692c RE |
1448 | of address here in the order (most pref first): |
1449 | PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */ | |
1450 | #define ADDRESS_COST(X) \ | |
1451 | (10 - ((GET_CODE (X) == MEM || GET_CODE (X) == LABEL_REF \ | |
1452 | || GET_CODE (X) == SYMBOL_REF) \ | |
1453 | ? 0 \ | |
1454 | : ((GET_CODE (X) == PRE_INC || GET_CODE (X) == PRE_DEC \ | |
1455 | || GET_CODE (X) == POST_INC || GET_CODE (X) == POST_DEC) \ | |
1456 | ? 10 \ | |
1457 | : (((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS) \ | |
1458 | ? 6 + (GET_CODE (XEXP (X, 1)) == CONST_INT ? 2 \ | |
1459 | : ((GET_RTX_CLASS (GET_CODE (XEXP (X, 0))) == '2' \ | |
1460 | || GET_RTX_CLASS (GET_CODE (XEXP (X, 0))) == 'c' \ | |
1461 | || GET_RTX_CLASS (GET_CODE (XEXP (X, 1))) == '2' \ | |
1462 | || GET_RTX_CLASS (GET_CODE (XEXP (X, 1))) == 'c') \ | |
1463 | ? 1 : 0)) \ | |
1464 | : 4))))) | |
1465 | ||
1466 | ||
ff9940b0 RE |
1467 | |
1468 | /* Try to generate sequences that don't involve branches, we can then use | |
1469 | conditional instructions */ | |
1470 | #define BRANCH_COST 4 | |
35d965d5 | 1471 | \f |
ff9940b0 RE |
1472 | /* Condition code information. */ |
1473 | /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, | |
1474 | return the mode to be used for the comparison. | |
ddd5a7c1 | 1475 | CCFPEmode should be used with floating inequalities, |
ff9940b0 | 1476 | CCFPmode should be used with floating equalities. |
ddd5a7c1 | 1477 | CC_NOOVmode should be used with SImode integer equalities. |
69fcc21d | 1478 | CC_Zmode should be used if only the Z flag is set correctly |
ff9940b0 RE |
1479 | CCmode should be used otherwise. */ |
1480 | ||
89c7ca52 RE |
1481 | #define EXTRA_CC_MODES CC_NOOVmode, CC_Zmode, CC_SWPmode, \ |
1482 | CCFPmode, CCFPEmode, CC_DNEmode, CC_DEQmode, CC_DLEmode, \ | |
1483 | CC_DLTmode, CC_DGEmode, CC_DGTmode, CC_DLEUmode, CC_DLTUmode, \ | |
62dd06ea | 1484 | CC_DGEUmode, CC_DGTUmode, CC_Cmode |
89c7ca52 RE |
1485 | |
1486 | #define EXTRA_CC_NAMES "CC_NOOV", "CC_Z", "CC_SWP", "CCFP", "CCFPE", \ | |
1487 | "CC_DNE", "CC_DEQ", "CC_DLE", "CC_DLT", "CC_DGE", "CC_DGT", "CC_DLEU", \ | |
62dd06ea | 1488 | "CC_DLTU", "CC_DGEU", "CC_DGTU", "CC_C" |
89c7ca52 RE |
1489 | |
1490 | enum machine_mode arm_select_cc_mode (); | |
1491 | #define SELECT_CC_MODE(OP,X,Y) arm_select_cc_mode ((OP), (X), (Y)) | |
ff9940b0 | 1492 | |
008cf58a RE |
1493 | #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode) |
1494 | ||
62dd06ea RE |
1495 | enum rtx_code arm_canonicalize_comparison (); |
1496 | #define CANONICALIZE_COMPARISON(CODE,OP0,OP1) \ | |
1497 | do \ | |
1498 | { \ | |
1499 | if (GET_CODE (OP1) == CONST_INT \ | |
1500 | && ! (const_ok_for_arm (INTVAL (OP1)) \ | |
1501 | || (const_ok_for_arm (- INTVAL (OP1))))) \ | |
1502 | { \ | |
1503 | rtx const_op = OP1; \ | |
1504 | CODE = arm_canonicalize_comparison ((CODE), &const_op); \ | |
1505 | } \ | |
1506 | } while (0) | |
1507 | ||
ff9940b0 RE |
1508 | #define STORE_FLAG_VALUE 1 |
1509 | ||
1510 | /* Define the information needed to generate branch insns. This is | |
1511 | stored from the compare operation. Note that we can't use "rtx" here | |
1512 | since it hasn't been defined! */ | |
1513 | ||
1514 | extern struct rtx_def *arm_compare_op0, *arm_compare_op1; | |
1515 | extern int arm_compare_fp; | |
1516 | ||
1517 | /* Define the codes that are matched by predicates in arm.c */ | |
1518 | #define PREDICATE_CODES \ | |
1519 | {"s_register_operand", {SUBREG, REG}}, \ | |
1520 | {"arm_add_operand", {SUBREG, REG, CONST_INT}}, \ | |
1521 | {"fpu_add_operand", {SUBREG, REG, CONST_DOUBLE}}, \ | |
1522 | {"arm_rhs_operand", {SUBREG, REG, CONST_INT}}, \ | |
1523 | {"fpu_rhs_operand", {SUBREG, REG, CONST_DOUBLE}}, \ | |
1524 | {"arm_not_operand", {SUBREG, REG, CONST_INT}}, \ | |
69fcc21d RE |
1525 | {"offsettable_memory_operand", {MEM}}, \ |
1526 | {"alignable_memory_operand", {MEM}}, \ | |
ff9940b0 RE |
1527 | {"shiftable_operator", {PLUS, MINUS, AND, IOR, XOR}}, \ |
1528 | {"minmax_operator", {SMIN, SMAX, UMIN, UMAX}}, \ | |
3967692c | 1529 | {"shift_operator", {ASHIFT, ASHIFTRT, LSHIFTRT, ROTATERT, MULT}}, \ |
ff9940b0 | 1530 | {"di_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE, MEM}}, \ |
c383667d | 1531 | {"soft_df_operand", {SUBREG, REG, CONST_DOUBLE, MEM}}, \ |
ff9940b0 RE |
1532 | {"load_multiple_operation", {PARALLEL}}, \ |
1533 | {"store_multiple_operation", {PARALLEL}}, \ | |
1534 | {"equality_operator", {EQ, NE}}, \ | |
1535 | {"arm_rhsm_operand", {SUBREG, REG, CONST_INT, MEM}}, \ | |
1536 | {"const_shift_operand", {CONST_INT}}, \ | |
1537 | {"index_operand", {SUBREG, REG, CONST_INT}}, \ | |
3967692c RE |
1538 | {"reg_or_int_operand", {SUBREG, REG, CONST_INT}}, \ |
1539 | {"multi_register_push", {PARALLEL}}, \ | |
31e6408a | 1540 | {"cc_register", {REG}}, \ |
89c7ca52 | 1541 | {"dominant_cc_register", {REG}}, |
ff9940b0 | 1542 | |
35d965d5 | 1543 | \f |
35d965d5 | 1544 | |
11c1a207 RE |
1545 | /* Gcc puts the pool in the wrong place for ARM, since we can only |
1546 | load addresses a limited distance around the pc. We do some | |
1547 | special munging to move the constant pool values to the correct | |
1548 | point in the code. */ | |
1549 | #define MACHINE_DEPENDENT_REORG(INSN) arm_reorg ((INSN)) | |
35d965d5 | 1550 | |
11c1a207 RE |
1551 | /* The pool is empty, since we have moved everything into the code. */ |
1552 | #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE,X,MODE,ALIGN,LABELNO,JUMPTO) \ | |
1553 | goto JUMPTO | |
35d965d5 RS |
1554 | |
1555 | /* Output an internal label definition. */ | |
1556 | #define ASM_OUTPUT_INTERNAL_LABEL(STREAM, PREFIX, NUM) \ | |
1557 | do \ | |
1558 | { \ | |
11c1a207 | 1559 | char *s = (char *) alloca (40 + strlen (PREFIX)); \ |
35d965d5 | 1560 | extern int arm_target_label, arm_ccfsm_state; \ |
26563586 | 1561 | extern rtx arm_target_insn; \ |
35d965d5 | 1562 | \ |
ff9940b0 RE |
1563 | if (arm_ccfsm_state == 3 && arm_target_label == (NUM) \ |
1564 | && !strcmp (PREFIX, "L")) \ | |
1565 | { \ | |
1566 | arm_ccfsm_state = 0; \ | |
26563586 | 1567 | arm_target_insn = NULL; \ |
ff9940b0 | 1568 | } \ |
11c1a207 | 1569 | ASM_GENERATE_INTERNAL_LABEL (s, (PREFIX), (NUM)); \ |
ff9940b0 | 1570 | arm_asm_output_label (STREAM, s); \ |
35d965d5 RS |
1571 | } while (0) |
1572 | ||
11c1a207 RE |
1573 | /* Output a label definition. */ |
1574 | #define ASM_OUTPUT_LABEL(STREAM,NAME) \ | |
1575 | arm_asm_output_label ((STREAM), (NAME)) | |
35d965d5 RS |
1576 | |
1577 | /* Output a push or a pop instruction (only used when profiling). */ | |
c383667d DE |
1578 | #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \ |
1579 | fprintf(STREAM,"\tstmfd\t%ssp!,{%s%s}\n", \ | |
1580 | REGISTER_PREFIX, REGISTER_PREFIX, reg_names[REGNO]) | |
35d965d5 | 1581 | |
c383667d DE |
1582 | #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \ |
1583 | fprintf(STREAM,"\tldmfd\t%ssp!,{%s%s}\n", \ | |
1584 | REGISTER_PREFIX, REGISTER_PREFIX, reg_names[REGNO]) | |
35d965d5 | 1585 | |
35d965d5 RS |
1586 | /* Target characters. */ |
1587 | #define TARGET_BELL 007 | |
1588 | #define TARGET_BS 010 | |
1589 | #define TARGET_TAB 011 | |
1590 | #define TARGET_NEWLINE 012 | |
1591 | #define TARGET_VT 013 | |
1592 | #define TARGET_FF 014 | |
1593 | #define TARGET_CR 015 | |
1594 | \f | |
35d965d5 RS |
1595 | /* Only perform branch elimination (by making instructions conditional) if |
1596 | we're optimising. Otherwise it's of no use anyway. */ | |
1597 | #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \ | |
1598 | if (optimize) \ | |
1599 | final_prescan_insn (INSN, OPVEC, NOPERANDS) | |
1600 | ||
7bc7696c RE |
1601 | #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ |
1602 | ((CODE) == '?' || (CODE) == '|' || (CODE) == '@') | |
1603 | /* Output an operand of an instruction. */ | |
35d965d5 | 1604 | #define PRINT_OPERAND(STREAM, X, CODE) \ |
7bc7696c RE |
1605 | arm_print_operand (STREAM, X, CODE) |
1606 | ||
1607 | #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \ | |
1608 | (HOST_BITS_PER_WIDE_INT <= 32 ? (x) \ | |
1609 | : (((x) & (unsigned HOST_WIDE_INT) 0xffffffff) | \ | |
1610 | (((x) & (unsigned HOST_WIDE_INT) 0x80000000) \ | |
1611 | ? ((~ (HOST_WIDE_INT) 0) \ | |
1612 | & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \ | |
1613 | : 0)))) | |
35d965d5 RS |
1614 | |
1615 | /* Output the address of an operand. */ | |
1616 | #define PRINT_OPERAND_ADDRESS(STREAM,X) \ | |
1617 | { \ | |
1618 | int is_minus = GET_CODE (X) == MINUS; \ | |
1619 | \ | |
1620 | if (GET_CODE (X) == REG) \ | |
c383667d | 1621 | fprintf (STREAM, "[%s%s, #0]", REGISTER_PREFIX, \ |
4eda77ec | 1622 | reg_names[REGNO (X)]); \ |
35d965d5 RS |
1623 | else if (GET_CODE (X) == PLUS || is_minus) \ |
1624 | { \ | |
1625 | rtx base = XEXP (X, 0); \ | |
1626 | rtx index = XEXP (X, 1); \ | |
1627 | char *base_reg_name; \ | |
7bc7696c | 1628 | HOST_WIDE_INT offset = 0; \ |
35d965d5 RS |
1629 | if (GET_CODE (base) != REG) \ |
1630 | { \ | |
1631 | /* Ensure that BASE is a register (one of them must be). */ \ | |
1632 | rtx temp = base; \ | |
1633 | base = index; \ | |
1634 | index = temp; \ | |
1635 | } \ | |
1636 | base_reg_name = reg_names[REGNO (base)]; \ | |
1637 | switch (GET_CODE (index)) \ | |
1638 | { \ | |
1639 | case CONST_INT: \ | |
1640 | offset = INTVAL (index); \ | |
1641 | if (is_minus) \ | |
1642 | offset = -offset; \ | |
c383667d | 1643 | fprintf (STREAM, "[%s%s, #%d]", REGISTER_PREFIX, \ |
4eda77ec | 1644 | base_reg_name, offset); \ |
35d965d5 RS |
1645 | break; \ |
1646 | \ | |
1647 | case REG: \ | |
c383667d | 1648 | fprintf (STREAM, "[%s%s, %s%s%s]", REGISTER_PREFIX, \ |
4eda77ec | 1649 | base_reg_name, is_minus ? "-" : "", \ |
c383667d | 1650 | REGISTER_PREFIX, reg_names[REGNO (index)] ); \ |
35d965d5 RS |
1651 | break; \ |
1652 | \ | |
1653 | case MULT: \ | |
ff9940b0 RE |
1654 | case ASHIFTRT: \ |
1655 | case LSHIFTRT: \ | |
1656 | case ASHIFT: \ | |
ff9940b0 RE |
1657 | case ROTATERT: \ |
1658 | { \ | |
c383667d DE |
1659 | fprintf (STREAM, "[%s%s, %s%s%s", REGISTER_PREFIX, \ |
1660 | base_reg_name, is_minus ? "-" : "", REGISTER_PREFIX,\ | |
7bc7696c RE |
1661 | reg_names[REGNO (XEXP (index, 0))]); \ |
1662 | arm_print_operand (STREAM, index, 'S'); \ | |
1663 | fputs ("]", STREAM); \ | |
ff9940b0 RE |
1664 | break; \ |
1665 | } \ | |
35d965d5 RS |
1666 | \ |
1667 | default: \ | |
1668 | abort(); \ | |
1669 | } \ | |
1670 | } \ | |
1671 | else if (GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC \ | |
1672 | || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC) \ | |
1673 | { \ | |
1674 | extern int output_memory_reference_mode; \ | |
1675 | \ | |
1676 | if (GET_CODE (XEXP (X, 0)) != REG) \ | |
1677 | abort (); \ | |
1678 | \ | |
1679 | if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \ | |
c383667d | 1680 | fprintf (STREAM, "[%s%s, #%s%d]!", REGISTER_PREFIX, \ |
4eda77ec | 1681 | reg_names[REGNO (XEXP (X, 0))], \ |
35d965d5 RS |
1682 | GET_CODE (X) == PRE_DEC ? "-" : "", \ |
1683 | GET_MODE_SIZE (output_memory_reference_mode)); \ | |
1684 | else \ | |
c383667d | 1685 | fprintf (STREAM, "[%s%s], #%s%d", REGISTER_PREFIX, \ |
4eda77ec | 1686 | reg_names[REGNO (XEXP (X, 0))], \ |
35d965d5 RS |
1687 | GET_CODE (X) == POST_DEC ? "-" : "", \ |
1688 | GET_MODE_SIZE (output_memory_reference_mode)); \ | |
1689 | } \ | |
1690 | else output_addr_const(STREAM, X); \ | |
1691 | } | |
62dd06ea RE |
1692 | |
1693 | /* Output code to add DELTA to the first argument, and then jump to FUNCTION. | |
1694 | Used for C++ multiple inheritance. */ | |
1695 | #define ASM_OUTPUT_MI_THUNK(FILE, THUNK_FNDECL, DELTA, FUNCTION) \ | |
1696 | do { \ | |
1697 | int mi_delta = (DELTA); \ | |
1698 | char *mi_op = mi_delta < 0 ? "sub" : "add"; \ | |
1699 | int shift = 0; \ | |
821581e4 DE |
1700 | int this_regno = (aggregate_value_p (TREE_TYPE (TREE_TYPE (FUNCTION))) \ |
1701 | ? 1 : 0); \ | |
62dd06ea RE |
1702 | if (mi_delta < 0) mi_delta = -mi_delta; \ |
1703 | while (mi_delta != 0) \ | |
1704 | { \ | |
1705 | if (mi_delta & (3 << shift) == 0) \ | |
1706 | shift += 2; \ | |
1707 | else \ | |
1708 | { \ | |
1709 | fprintf (FILE, "\t%s\t%s%s, %s%s, #%d\n", \ | |
821581e4 DE |
1710 | mi_op, REGISTER_PREFIX, reg_names[this_regno], \ |
1711 | REGISTER_PREFIX, reg_names[this_regno], \ | |
62dd06ea RE |
1712 | mi_delta & (0xff << shift)); \ |
1713 | arm_increase_location (4); \ | |
1714 | mi_delta &= ~(0xff << shift); \ | |
1715 | shift += 8; \ | |
1716 | } \ | |
1717 | } \ | |
1718 | fprintf (FILE, "\tldr\t%spc, [%spc, #-4]\n", REGISTER_PREFIX, \ | |
1719 | REGISTER_PREFIX); \ | |
1720 | arm_increase_location (4); \ | |
1721 | ASM_OUTPUT_INT (FILE, XEXP (DECL_RTL (FUNCTION), 0)); \ | |
1722 | } while (0) | |
39950dff MS |
1723 | |
1724 | /* Used to mask out junk bits from the return address, such as | |
1725 | processor state, interrupt status, condition codes and the like. */ | |
1726 | #define MASK_RETURN_ADDR \ | |
1727 | /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \ | |
1728 | in 26 bit mode, the condition codes must be masked out of the \ | |
1729 | return address. This does not apply to ARM6 and later processors \ | |
1730 | when running in 32 bit mode. */ \ | |
1731 | ((!TARGET_6) ? (GEN_INT (0x03fffffc)) : (GEN_INT (0xffffffff))) |