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f5a1b0d2 | 1 | /* Definitions of target machine for GNU compiler, for ARM. |
cf011243 | 2 | Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, |
66647d44 | 3 | 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009 |
bf98ec6c | 4 | Free Software Foundation, Inc. |
35d965d5 | 5 | Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl) |
8b109b37 | 6 | and Martin Simmons (@harleqn.co.uk). |
949d79eb | 7 | More major hacks by Richard Earnshaw (rearnsha@arm.com) |
6cfc7210 NC |
8 | Minor hacks by Nick Clifton (nickc@cygnus.com) |
9 | ||
4f448245 | 10 | This file is part of GCC. |
35d965d5 | 11 | |
4f448245 NC |
12 | GCC is free software; you can redistribute it and/or modify it |
13 | under the terms of the GNU General Public License as published | |
2f83c7d6 | 14 | by the Free Software Foundation; either version 3, or (at your |
4f448245 | 15 | option) any later version. |
35d965d5 | 16 | |
4f448245 NC |
17 | GCC is distributed in the hope that it will be useful, but WITHOUT |
18 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
19 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
20 | License for more details. | |
35d965d5 | 21 | |
4f448245 | 22 | You should have received a copy of the GNU General Public License |
2f83c7d6 NC |
23 | along with GCC; see the file COPYING3. If not see |
24 | <http://www.gnu.org/licenses/>. */ | |
35d965d5 | 25 | |
88657302 RH |
26 | #ifndef GCC_ARM_H |
27 | #define GCC_ARM_H | |
b355a481 | 28 | |
46107b99 RE |
29 | /* We can't use enum machine_mode inside a generator file because it |
30 | hasn't been created yet; we shouldn't be using any code that | |
31 | needs the real definition though, so this ought to be safe. */ | |
32 | #ifdef GENERATOR_FILE | |
33 | #define MACHMODE int | |
34 | #else | |
35 | #include "insn-modes.h" | |
36 | #define MACHMODE enum machine_mode | |
37 | #endif | |
38 | ||
9403b7f7 RS |
39 | #include "config/vxworks-dummy.h" |
40 | ||
35fd3193 | 41 | /* The architecture define. */ |
78011587 PB |
42 | extern char arm_arch_name[]; |
43 | ||
e6471be6 NB |
44 | /* Target CPU builtins. */ |
45 | #define TARGET_CPU_CPP_BUILTINS() \ | |
46 | do \ | |
47 | { \ | |
9b66ebb1 PB |
48 | /* Define __arm__ even when in thumb mode, for \ |
49 | consistency with armcc. */ \ | |
50 | builtin_define ("__arm__"); \ | |
61f0ccff | 51 | builtin_define ("__APCS_32__"); \ |
9b66ebb1 | 52 | if (TARGET_THUMB) \ |
e6471be6 | 53 | builtin_define ("__thumb__"); \ |
5b3e6663 PB |
54 | if (TARGET_THUMB2) \ |
55 | builtin_define ("__thumb2__"); \ | |
e6471be6 NB |
56 | \ |
57 | if (TARGET_BIG_END) \ | |
58 | { \ | |
59 | builtin_define ("__ARMEB__"); \ | |
60 | if (TARGET_THUMB) \ | |
61 | builtin_define ("__THUMBEB__"); \ | |
62 | if (TARGET_LITTLE_WORDS) \ | |
63 | builtin_define ("__ARMWEL__"); \ | |
64 | } \ | |
65 | else \ | |
66 | { \ | |
67 | builtin_define ("__ARMEL__"); \ | |
68 | if (TARGET_THUMB) \ | |
69 | builtin_define ("__THUMBEL__"); \ | |
70 | } \ | |
71 | \ | |
e6471be6 NB |
72 | if (TARGET_SOFT_FLOAT) \ |
73 | builtin_define ("__SOFTFP__"); \ | |
74 | \ | |
9b66ebb1 | 75 | if (TARGET_VFP) \ |
b5b620a4 JT |
76 | builtin_define ("__VFP_FP__"); \ |
77 | \ | |
88f77cba JB |
78 | if (TARGET_NEON) \ |
79 | builtin_define ("__ARM_NEON__"); \ | |
80 | \ | |
e6471be6 NB |
81 | /* Add a define for interworking. \ |
82 | Needed when building libgcc.a. */ \ | |
2ad4dcf9 | 83 | if (arm_cpp_interwork) \ |
e6471be6 NB |
84 | builtin_define ("__THUMB_INTERWORK__"); \ |
85 | \ | |
86 | builtin_assert ("cpu=arm"); \ | |
87 | builtin_assert ("machine=arm"); \ | |
78011587 PB |
88 | \ |
89 | builtin_define (arm_arch_name); \ | |
90 | if (arm_arch_cirrus) \ | |
91 | builtin_define ("__MAVERICK__"); \ | |
92 | if (arm_arch_xscale) \ | |
93 | builtin_define ("__XSCALE__"); \ | |
94 | if (arm_arch_iwmmxt) \ | |
95 | builtin_define ("__IWMMXT__"); \ | |
4adf3e34 PB |
96 | if (TARGET_AAPCS_BASED) \ |
97 | builtin_define ("__ARM_EABI__"); \ | |
e6471be6 NB |
98 | } while (0) |
99 | ||
9b66ebb1 PB |
100 | /* The various ARM cores. */ |
101 | enum processor_type | |
102 | { | |
d98a72fd RE |
103 | #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \ |
104 | IDENT, | |
9b66ebb1 PB |
105 | #include "arm-cores.def" |
106 | #undef ARM_CORE | |
107 | /* Used to indicate that no processor has been specified. */ | |
108 | arm_none | |
109 | }; | |
110 | ||
78011587 PB |
111 | enum target_cpus |
112 | { | |
d98a72fd RE |
113 | #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \ |
114 | TARGET_CPU_##IDENT, | |
78011587 PB |
115 | #include "arm-cores.def" |
116 | #undef ARM_CORE | |
117 | TARGET_CPU_generic | |
118 | }; | |
119 | ||
9b66ebb1 PB |
120 | /* The processor for which instructions should be scheduled. */ |
121 | extern enum processor_type arm_tune; | |
122 | ||
d5b7b3ae | 123 | typedef enum arm_cond_code |
89c7ca52 RE |
124 | { |
125 | ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC, | |
126 | ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV | |
d5b7b3ae RE |
127 | } |
128 | arm_cc; | |
6cfc7210 | 129 | |
d5b7b3ae | 130 | extern arm_cc arm_current_cc; |
ff9940b0 | 131 | |
d5b7b3ae | 132 | #define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1)) |
89c7ca52 | 133 | |
6cfc7210 NC |
134 | extern int arm_target_label; |
135 | extern int arm_ccfsm_state; | |
e2500fed | 136 | extern GTY(()) rtx arm_target_insn; |
d5b7b3ae | 137 | /* The label of the current constant pool. */ |
e2500fed | 138 | extern rtx pool_vector_label; |
d5b7b3ae | 139 | /* Set to 1 when a return insn is output, this means that the epilogue |
d6b4baa4 | 140 | is not needed. */ |
d5b7b3ae | 141 | extern int return_used_this_function; |
b76c3c4b PB |
142 | /* Callback to output language specific object attributes. */ |
143 | extern void (*arm_lang_output_object_attributes_hook)(void); | |
35d965d5 | 144 | \f |
d6b4baa4 | 145 | /* Just in case configure has failed to define anything. */ |
7a801826 RE |
146 | #ifndef TARGET_CPU_DEFAULT |
147 | #define TARGET_CPU_DEFAULT TARGET_CPU_generic | |
148 | #endif | |
149 | ||
7a801826 | 150 | |
5742588d | 151 | #undef CPP_SPEC |
78011587 | 152 | #define CPP_SPEC "%(subtarget_cpp_spec) \ |
e6471be6 NB |
153 | %{msoft-float:%{mhard-float: \ |
154 | %e-msoft-float and -mhard_float may not be used together}} \ | |
155 | %{mbig-endian:%{mlittle-endian: \ | |
156 | %e-mbig-endian and -mlittle-endian may not be used together}}" | |
7a801826 | 157 | |
be393ecf | 158 | #ifndef CC1_SPEC |
dfa08768 | 159 | #define CC1_SPEC "" |
be393ecf | 160 | #endif |
7a801826 RE |
161 | |
162 | /* This macro defines names of additional specifications to put in the specs | |
163 | that can be used in various specifications like CC1_SPEC. Its definition | |
164 | is an initializer with a subgrouping for each command option. | |
165 | ||
166 | Each subgrouping contains a string constant, that defines the | |
4f448245 | 167 | specification name, and a string constant that used by the GCC driver |
7a801826 RE |
168 | program. |
169 | ||
170 | Do not define this macro if it does not need to do anything. */ | |
171 | #define EXTRA_SPECS \ | |
38fc909b | 172 | { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \ |
7a801826 RE |
173 | SUBTARGET_EXTRA_SPECS |
174 | ||
914a3b8c | 175 | #ifndef SUBTARGET_EXTRA_SPECS |
7a801826 | 176 | #define SUBTARGET_EXTRA_SPECS |
914a3b8c DM |
177 | #endif |
178 | ||
6cfc7210 | 179 | #ifndef SUBTARGET_CPP_SPEC |
38fc909b | 180 | #define SUBTARGET_CPP_SPEC "" |
6cfc7210 | 181 | #endif |
35d965d5 RS |
182 | \f |
183 | /* Run-time Target Specification. */ | |
ff9940b0 | 184 | #ifndef TARGET_VERSION |
6cfc7210 | 185 | #define TARGET_VERSION fputs (" (ARM/generic)", stderr); |
ff9940b0 | 186 | #endif |
35d965d5 | 187 | |
9b66ebb1 | 188 | #define TARGET_SOFT_FLOAT (arm_float_abi == ARM_FLOAT_ABI_SOFT) |
72cdc543 PB |
189 | /* Use hardware floating point instructions. */ |
190 | #define TARGET_HARD_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT) | |
191 | /* Use hardware floating point calling convention. */ | |
192 | #define TARGET_HARD_FLOAT_ABI (arm_float_abi == ARM_FLOAT_ABI_HARD) | |
9b66ebb1 PB |
193 | #define TARGET_FPA (arm_fp_model == ARM_FP_MODEL_FPA) |
194 | #define TARGET_MAVERICK (arm_fp_model == ARM_FP_MODEL_MAVERICK) | |
195 | #define TARGET_VFP (arm_fp_model == ARM_FP_MODEL_VFP) | |
5a9335ef | 196 | #define TARGET_IWMMXT (arm_arch_iwmmxt) |
5b3e6663 PB |
197 | #define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_32BIT) |
198 | #define TARGET_IWMMXT_ABI (TARGET_32BIT && arm_abi == ARM_ABI_IWMMXT) | |
d5b7b3ae RE |
199 | #define TARGET_ARM (! TARGET_THUMB) |
200 | #define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */ | |
c54c7322 RS |
201 | #define TARGET_BACKTRACE (leaf_function_p () \ |
202 | ? TARGET_TPCS_LEAF_FRAME \ | |
203 | : TARGET_TPCS_FRAME) | |
fdd695fd | 204 | #define TARGET_LDRD (arm_arch5e && ARM_DOUBLEWORD_ALIGN) |
b6685939 PB |
205 | #define TARGET_AAPCS_BASED \ |
206 | (arm_abi != ARM_ABI_APCS && arm_abi != ARM_ABI_ATPCS) | |
3ada8e17 | 207 | |
d3585b76 DJ |
208 | #define TARGET_HARD_TP (target_thread_pointer == TP_CP15) |
209 | #define TARGET_SOFT_TP (target_thread_pointer == TP_SOFT) | |
210 | ||
5b3e6663 PB |
211 | /* Only 16-bit thumb code. */ |
212 | #define TARGET_THUMB1 (TARGET_THUMB && !arm_arch_thumb2) | |
213 | /* Arm or Thumb-2 32-bit code. */ | |
214 | #define TARGET_32BIT (TARGET_ARM || arm_arch_thumb2) | |
215 | /* 32-bit Thumb-2 code. */ | |
216 | #define TARGET_THUMB2 (TARGET_THUMB && arm_arch_thumb2) | |
bf98ec6c PB |
217 | /* Thumb-1 only. */ |
218 | #define TARGET_THUMB1_ONLY (TARGET_THUMB1 && !arm_arch_notm) | |
5b3e6663 | 219 | |
88f77cba | 220 | /* The following two macros concern the ability to execute coprocessor |
302c3d8e PB |
221 | instructions for VFPv3 or NEON. TARGET_VFP3/TARGET_VFPD32 are currently |
222 | only ever tested when we know we are generating for VFP hardware; we need | |
223 | to be more careful with TARGET_NEON as noted below. */ | |
88f77cba | 224 | |
302c3d8e PB |
225 | /* FPU is has the full VFPv3/NEON register file of 32 D registers. */ |
226 | #define TARGET_VFPD32 (arm_fp_model == ARM_FP_MODEL_VFP \ | |
227 | && (arm_fpu_arch == FPUTYPE_VFP3 \ | |
0fd8c3ad SL |
228 | || arm_fpu_arch == FPUTYPE_NEON \ |
229 | || arm_fpu_arch == FPUTYPE_NEON_FP16)) | |
302c3d8e PB |
230 | |
231 | /* FPU supports VFPv3 instructions. */ | |
f1adb0a9 | 232 | #define TARGET_VFP3 (arm_fp_model == ARM_FP_MODEL_VFP \ |
302c3d8e PB |
233 | && (arm_fpu_arch == FPUTYPE_VFP3D16 \ |
234 | || TARGET_VFPD32)) | |
235 | ||
0fd8c3ad SL |
236 | /* FPU supports NEON/VFP half-precision floating-point. */ |
237 | #define TARGET_NEON_FP16 (arm_fpu_arch == FPUTYPE_NEON_FP16) | |
238 | ||
88f77cba JB |
239 | /* FPU supports Neon instructions. The setting of this macro gets |
240 | revealed via __ARM_NEON__ so we add extra guards upon TARGET_32BIT | |
241 | and TARGET_HARD_FLOAT to ensure that NEON instructions are | |
242 | available. */ | |
243 | #define TARGET_NEON (TARGET_32BIT && TARGET_HARD_FLOAT \ | |
244 | && arm_fp_model == ARM_FP_MODEL_VFP \ | |
0fd8c3ad SL |
245 | && (arm_fpu_arch == FPUTYPE_NEON \ |
246 | || arm_fpu_arch == FPUTYPE_NEON_FP16)) | |
f1adb0a9 | 247 | |
5b3e6663 PB |
248 | /* "DSP" multiply instructions, eg. SMULxy. */ |
249 | #define TARGET_DSP_MULTIPLY \ | |
250 | (TARGET_32BIT && arm_arch5e && arm_arch_notm) | |
251 | /* Integer SIMD instructions, and extend-accumulate instructions. */ | |
252 | #define TARGET_INT_SIMD \ | |
253 | (TARGET_32BIT && arm_arch6 && arm_arch_notm) | |
254 | ||
571191af PB |
255 | /* Should MOVW/MOVT be used in preference to a constant pool. */ |
256 | #define TARGET_USE_MOVT (arm_arch_thumb2 && !optimize_size) | |
257 | ||
5b3e6663 PB |
258 | /* We could use unified syntax for arm mode, but for now we just use it |
259 | for Thumb-2. */ | |
260 | #define TARGET_UNIFIED_ASM TARGET_THUMB2 | |
261 | ||
262 | ||
b3f8d95d MM |
263 | /* True iff the full BPABI is being used. If TARGET_BPABI is true, |
264 | then TARGET_AAPCS_BASED must be true -- but the converse does not | |
265 | hold. TARGET_BPABI implies the use of the BPABI runtime library, | |
266 | etc., in addition to just the AAPCS calling conventions. */ | |
267 | #ifndef TARGET_BPABI | |
268 | #define TARGET_BPABI false | |
f676971a | 269 | #endif |
b3f8d95d | 270 | |
7816bea0 DJ |
271 | /* Support for a compile-time default CPU, et cetera. The rules are: |
272 | --with-arch is ignored if -march or -mcpu are specified. | |
273 | --with-cpu is ignored if -march or -mcpu are specified, and is overridden | |
274 | by --with-arch. | |
275 | --with-tune is ignored if -mtune or -mcpu are specified (but not affected | |
276 | by -march). | |
9b66ebb1 PB |
277 | --with-float is ignored if -mhard-float, -msoft-float or -mfloat-abi are |
278 | specified. | |
5848830f PB |
279 | --with-fpu is ignored if -mfpu is specified. |
280 | --with-abi is ignored is -mabi is specified. */ | |
7816bea0 DJ |
281 | #define OPTION_DEFAULT_SPECS \ |
282 | {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \ | |
283 | {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \ | |
284 | {"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}" }, \ | |
9b66ebb1 PB |
285 | {"float", \ |
286 | "%{!msoft-float:%{!mhard-float:%{!mfloat-abi=*:-mfloat-abi=%(VALUE)}}}" }, \ | |
5848830f | 287 | {"fpu", "%{!mfpu=*:-mfpu=%(VALUE)}"}, \ |
3cf94279 PB |
288 | {"abi", "%{!mabi=*:-mabi=%(VALUE)}"}, \ |
289 | {"mode", "%{!marm:%{!mthumb:-m%(VALUE)}}"}, | |
7816bea0 | 290 | |
9b66ebb1 PB |
291 | /* Which floating point model to use. */ |
292 | enum arm_fp_model | |
293 | { | |
294 | ARM_FP_MODEL_UNKNOWN, | |
295 | /* FPA model (Hardware or software). */ | |
296 | ARM_FP_MODEL_FPA, | |
297 | /* Cirrus Maverick floating point model. */ | |
298 | ARM_FP_MODEL_MAVERICK, | |
299 | /* VFP floating point model. */ | |
300 | ARM_FP_MODEL_VFP | |
301 | }; | |
302 | ||
303 | extern enum arm_fp_model arm_fp_model; | |
304 | ||
305 | /* Which floating point hardware is available. Also update | |
306 | fp_model_for_fpu in arm.c when adding entries to this list. */ | |
29ad9694 | 307 | enum fputype |
24f0c1b4 | 308 | { |
9b66ebb1 PB |
309 | /* No FP hardware. */ |
310 | FPUTYPE_NONE, | |
29ad9694 RE |
311 | /* Full FPA support. */ |
312 | FPUTYPE_FPA, | |
313 | /* Emulated FPA hardware, Issue 2 emulator (no LFM/SFM). */ | |
314 | FPUTYPE_FPA_EMU2, | |
315 | /* Emulated FPA hardware, Issue 3 emulator. */ | |
316 | FPUTYPE_FPA_EMU3, | |
317 | /* Cirrus Maverick floating point co-processor. */ | |
9b66ebb1 PB |
318 | FPUTYPE_MAVERICK, |
319 | /* VFP. */ | |
f1adb0a9 | 320 | FPUTYPE_VFP, |
302c3d8e PB |
321 | /* VFPv3-D16. */ |
322 | FPUTYPE_VFP3D16, | |
f1adb0a9 | 323 | /* VFPv3. */ |
88f77cba JB |
324 | FPUTYPE_VFP3, |
325 | /* Neon. */ | |
0fd8c3ad SL |
326 | FPUTYPE_NEON, |
327 | /* Neon with half-precision float extensions. */ | |
328 | FPUTYPE_NEON_FP16 | |
24f0c1b4 RE |
329 | }; |
330 | ||
331 | /* Recast the floating point class to be the floating point attribute. */ | |
29ad9694 | 332 | #define arm_fpu_attr ((enum attr_fpu) arm_fpu_tune) |
24f0c1b4 | 333 | |
71791e16 | 334 | /* What type of floating point to tune for */ |
29ad9694 | 335 | extern enum fputype arm_fpu_tune; |
24f0c1b4 | 336 | |
71791e16 | 337 | /* What type of floating point instructions are available */ |
29ad9694 | 338 | extern enum fputype arm_fpu_arch; |
71791e16 | 339 | |
9b66ebb1 PB |
340 | enum float_abi_type |
341 | { | |
342 | ARM_FLOAT_ABI_SOFT, | |
343 | ARM_FLOAT_ABI_SOFTFP, | |
344 | ARM_FLOAT_ABI_HARD | |
345 | }; | |
346 | ||
347 | extern enum float_abi_type arm_float_abi; | |
348 | ||
3d8532aa PB |
349 | #ifndef TARGET_DEFAULT_FLOAT_ABI |
350 | #define TARGET_DEFAULT_FLOAT_ABI ARM_FLOAT_ABI_SOFT | |
351 | #endif | |
352 | ||
0fd8c3ad SL |
353 | /* Which __fp16 format to use. |
354 | The enumeration values correspond to the numbering for the | |
355 | Tag_ABI_FP_16bit_format attribute. | |
356 | */ | |
357 | enum arm_fp16_format_type | |
358 | { | |
359 | ARM_FP16_FORMAT_NONE = 0, | |
360 | ARM_FP16_FORMAT_IEEE = 1, | |
361 | ARM_FP16_FORMAT_ALTERNATIVE = 2 | |
362 | }; | |
363 | ||
364 | extern enum arm_fp16_format_type arm_fp16_format; | |
365 | #define LARGEST_EXPONENT_IS_NORMAL(bits) \ | |
366 | ((bits) == 16 && arm_fp16_format == ARM_FP16_FORMAT_ALTERNATIVE) | |
367 | ||
5848830f PB |
368 | /* Which ABI to use. */ |
369 | enum arm_abi_type | |
370 | { | |
371 | ARM_ABI_APCS, | |
372 | ARM_ABI_ATPCS, | |
373 | ARM_ABI_AAPCS, | |
077fc835 KH |
374 | ARM_ABI_IWMMXT, |
375 | ARM_ABI_AAPCS_LINUX | |
5848830f PB |
376 | }; |
377 | ||
378 | extern enum arm_abi_type arm_abi; | |
379 | ||
380 | #ifndef ARM_DEFAULT_ABI | |
381 | #define ARM_DEFAULT_ABI ARM_ABI_APCS | |
382 | #endif | |
383 | ||
d3585b76 DJ |
384 | /* Which thread pointer access sequence to use. */ |
385 | enum arm_tp_type { | |
386 | TP_AUTO, | |
387 | TP_SOFT, | |
388 | TP_CP15 | |
389 | }; | |
390 | ||
391 | extern enum arm_tp_type target_thread_pointer; | |
392 | ||
9b66ebb1 PB |
393 | /* Nonzero if this chip supports the ARM Architecture 3M extensions. */ |
394 | extern int arm_arch3m; | |
11c1a207 | 395 | |
9b66ebb1 | 396 | /* Nonzero if this chip supports the ARM Architecture 4 extensions. */ |
11c1a207 RE |
397 | extern int arm_arch4; |
398 | ||
68d560d4 RE |
399 | /* Nonzero if this chip supports the ARM Architecture 4T extensions. */ |
400 | extern int arm_arch4t; | |
401 | ||
9b66ebb1 | 402 | /* Nonzero if this chip supports the ARM Architecture 5 extensions. */ |
62b10bbc NC |
403 | extern int arm_arch5; |
404 | ||
9b66ebb1 | 405 | /* Nonzero if this chip supports the ARM Architecture 5E extensions. */ |
b15bca31 RE |
406 | extern int arm_arch5e; |
407 | ||
9b66ebb1 PB |
408 | /* Nonzero if this chip supports the ARM Architecture 6 extensions. */ |
409 | extern int arm_arch6; | |
410 | ||
5b3e6663 PB |
411 | /* Nonzero if instructions not present in the 'M' profile can be used. */ |
412 | extern int arm_arch_notm; | |
413 | ||
f5a1b0d2 NC |
414 | /* Nonzero if this chip can benefit from load scheduling. */ |
415 | extern int arm_ld_sched; | |
416 | ||
0616531f RE |
417 | /* Nonzero if generating thumb code. */ |
418 | extern int thumb_code; | |
419 | ||
f5a1b0d2 | 420 | /* Nonzero if this chip is a StrongARM. */ |
abac3b49 | 421 | extern int arm_tune_strongarm; |
f5a1b0d2 | 422 | |
9b6b54e2 | 423 | /* Nonzero if this chip is a Cirrus variant. */ |
78011587 | 424 | extern int arm_arch_cirrus; |
9b6b54e2 | 425 | |
5a9335ef NC |
426 | /* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */ |
427 | extern int arm_arch_iwmmxt; | |
428 | ||
d19fb8e3 | 429 | /* Nonzero if this chip is an XScale. */ |
4b3c2e48 PB |
430 | extern int arm_arch_xscale; |
431 | ||
abac3b49 | 432 | /* Nonzero if tuning for XScale. */ |
4b3c2e48 | 433 | extern int arm_tune_xscale; |
d19fb8e3 | 434 | |
abac3b49 RE |
435 | /* Nonzero if tuning for stores via the write buffer. */ |
436 | extern int arm_tune_wbuf; | |
f5a1b0d2 | 437 | |
7612f14d PB |
438 | /* Nonzero if tuning for Cortex-A9. */ |
439 | extern int arm_tune_cortex_a9; | |
440 | ||
2ad4dcf9 | 441 | /* Nonzero if we should define __THUMB_INTERWORK__ in the |
f676971a | 442 | preprocessor. |
2ad4dcf9 RE |
443 | XXX This is a bit of a hack, it's intended to help work around |
444 | problems in GLD which doesn't understand that armv5t code is | |
445 | interworking clean. */ | |
446 | extern int arm_cpp_interwork; | |
447 | ||
5b3e6663 PB |
448 | /* Nonzero if chip supports Thumb 2. */ |
449 | extern int arm_arch_thumb2; | |
450 | ||
451 | /* Nonzero if chip supports integer division instruction. */ | |
452 | extern int arm_arch_hwdiv; | |
453 | ||
2ce9c1b9 | 454 | #ifndef TARGET_DEFAULT |
c54c7322 | 455 | #define TARGET_DEFAULT (MASK_APCS_FRAME) |
2ce9c1b9 | 456 | #endif |
35d965d5 | 457 | |
11c1a207 RE |
458 | /* The frame pointer register used in gcc has nothing to do with debugging; |
459 | that is controlled by the APCS-FRAME option. */ | |
d5b7b3ae | 460 | #define CAN_DEBUG_WITHOUT_FP |
35d965d5 | 461 | |
11c1a207 | 462 | #define OVERRIDE_OPTIONS arm_override_options () |
86efdc8e | 463 | |
f67358da PB |
464 | #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) \ |
465 | arm_optimization_options ((LEVEL), (SIZE)) | |
466 | ||
86efdc8e PB |
467 | /* Nonzero if PIC code requires explicit qualifiers to generate |
468 | PLT and GOT relocs rather than the assembler doing so implicitly. | |
ed0e6530 PB |
469 | Subtargets can override these if required. */ |
470 | #ifndef NEED_GOT_RELOC | |
471 | #define NEED_GOT_RELOC 0 | |
472 | #endif | |
473 | #ifndef NEED_PLT_RELOC | |
474 | #define NEED_PLT_RELOC 0 | |
e2723c62 | 475 | #endif |
84306176 PB |
476 | |
477 | /* Nonzero if we need to refer to the GOT with a PC-relative | |
478 | offset. In other words, generate | |
479 | ||
f676971a | 480 | .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)] |
84306176 PB |
481 | |
482 | rather than | |
483 | ||
484 | .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8) | |
485 | ||
f676971a | 486 | The default is true, which matches NetBSD. Subtargets can |
84306176 PB |
487 | override this if required. */ |
488 | #ifndef GOT_PCREL | |
489 | #define GOT_PCREL 1 | |
490 | #endif | |
35d965d5 RS |
491 | \f |
492 | /* Target machine storage Layout. */ | |
493 | ||
ff9940b0 RE |
494 | |
495 | /* Define this macro if it is advisable to hold scalars in registers | |
496 | in a wider mode than that declared by the program. In such cases, | |
497 | the value is constrained to be within the bounds of the declared | |
498 | type, but kept valid in the wider mode. The signedness of the | |
499 | extension may differ from that of the type. */ | |
500 | ||
501 | /* It is far faster to zero extend chars than to sign extend them */ | |
502 | ||
6cfc7210 | 503 | #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ |
2ce9c1b9 RE |
504 | if (GET_MODE_CLASS (MODE) == MODE_INT \ |
505 | && GET_MODE_SIZE (MODE) < 4) \ | |
506 | { \ | |
507 | if (MODE == QImode) \ | |
508 | UNSIGNEDP = 1; \ | |
509 | else if (MODE == HImode) \ | |
61f0ccff | 510 | UNSIGNEDP = 1; \ |
2ce9c1b9 | 511 | (MODE) = SImode; \ |
ff9940b0 RE |
512 | } |
513 | ||
35d965d5 RS |
514 | /* Define this if most significant bit is lowest numbered |
515 | in instructions that operate on numbered bit-fields. */ | |
516 | #define BITS_BIG_ENDIAN 0 | |
517 | ||
f676971a | 518 | /* Define this if most significant byte of a word is the lowest numbered. |
3ada8e17 DE |
519 | Most ARM processors are run in little endian mode, so that is the default. |
520 | If you want to have it run-time selectable, change the definition in a | |
521 | cover file to be TARGET_BIG_ENDIAN. */ | |
11c1a207 | 522 | #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0) |
35d965d5 RS |
523 | |
524 | /* Define this if most significant word of a multiword number is the lowest | |
11c1a207 RE |
525 | numbered. |
526 | This is always false, even when in big-endian mode. */ | |
ddee6aba RE |
527 | #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS) |
528 | ||
529 | /* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based | |
530 | on processor pre-defineds when compiling libgcc2.c. */ | |
531 | #if defined(__ARMEB__) && !defined(__ARMWEL__) | |
532 | #define LIBGCC2_WORDS_BIG_ENDIAN 1 | |
533 | #else | |
534 | #define LIBGCC2_WORDS_BIG_ENDIAN 0 | |
535 | #endif | |
35d965d5 | 536 | |
11c1a207 | 537 | /* Define this if most significant word of doubles is the lowest numbered. |
f0375c66 NC |
538 | The rules are different based on whether or not we use FPA-format, |
539 | VFP-format or some other floating point co-processor's format doubles. */ | |
b5b620a4 | 540 | #define FLOAT_WORDS_BIG_ENDIAN (arm_float_words_big_endian ()) |
7fc6c9f0 | 541 | |
35d965d5 RS |
542 | #define UNITS_PER_WORD 4 |
543 | ||
88f77cba JB |
544 | /* Use the option -mvectorize-with-neon-quad to override the use of doubleword |
545 | registers when autovectorizing for Neon, at least until multiple vector | |
546 | widths are supported properly by the middle-end. */ | |
9d3a9de1 | 547 | #define UNITS_PER_SIMD_WORD(MODE) \ |
88f77cba JB |
548 | (TARGET_NEON ? (TARGET_NEON_VECTORIZE_QUAD ? 16 : 8) : UNITS_PER_WORD) |
549 | ||
5848830f | 550 | /* True if natural alignment is used for doubleword types. */ |
b6685939 PB |
551 | #define ARM_DOUBLEWORD_ALIGN TARGET_AAPCS_BASED |
552 | ||
5848830f | 553 | #define DOUBLEWORD_ALIGNMENT 64 |
35d965d5 | 554 | |
5848830f | 555 | #define PARM_BOUNDARY 32 |
5a9335ef | 556 | |
5848830f | 557 | #define STACK_BOUNDARY (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32) |
35d965d5 | 558 | |
5848830f PB |
559 | #define PREFERRED_STACK_BOUNDARY \ |
560 | (arm_abi == ARM_ABI_ATPCS ? 64 : STACK_BOUNDARY) | |
0977774b | 561 | |
f711a87a | 562 | #define FUNCTION_BOUNDARY ((TARGET_THUMB && optimize_size) ? 16 : 32) |
35d965d5 | 563 | |
92928d71 AO |
564 | /* The lowest bit is used to indicate Thumb-mode functions, so the |
565 | vbit must go into the delta field of pointers to member | |
566 | functions. */ | |
567 | #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta | |
568 | ||
35d965d5 RS |
569 | #define EMPTY_FIELD_BOUNDARY 32 |
570 | ||
5848830f | 571 | #define BIGGEST_ALIGNMENT (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32) |
5a9335ef | 572 | |
27847754 NC |
573 | /* XXX Blah -- this macro is used directly by libobjc. Since it |
574 | supports no vector modes, cut out the complexity and fall back | |
575 | on BIGGEST_FIELD_ALIGNMENT. */ | |
576 | #ifdef IN_TARGET_LIBS | |
8fca31a2 | 577 | #define BIGGEST_FIELD_ALIGNMENT 64 |
27847754 | 578 | #endif |
5a9335ef | 579 | |
ff9940b0 | 580 | /* Make strings word-aligned so strcpy from constants will be faster. */ |
591af218 | 581 | #define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_tune_xscale ? 1 : 2) |
f676971a | 582 | |
d19fb8e3 | 583 | #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ |
5848830f | 584 | ((TREE_CODE (EXP) == STRING_CST \ |
36b15ad0 | 585 | && !optimize_size \ |
5848830f PB |
586 | && (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \ |
587 | ? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN)) | |
ff9940b0 | 588 | |
96339268 RE |
589 | /* Align definitions of arrays, unions and structures so that |
590 | initializations and copies can be made more efficient. This is not | |
591 | ABI-changing, so it only affects places where we can see the | |
592 | definition. */ | |
593 | #define DATA_ALIGNMENT(EXP, ALIGN) \ | |
594 | ((((ALIGN) < BITS_PER_WORD) \ | |
595 | && (TREE_CODE (EXP) == ARRAY_TYPE \ | |
596 | || TREE_CODE (EXP) == UNION_TYPE \ | |
597 | || TREE_CODE (EXP) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN)) | |
598 | ||
599 | /* Similarly, make sure that objects on the stack are sensibly aligned. */ | |
600 | #define LOCAL_ALIGNMENT(EXP, ALIGN) DATA_ALIGNMENT(EXP, ALIGN) | |
601 | ||
723ae7c1 NC |
602 | /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the |
603 | value set in previous versions of this toolchain was 8, which produces more | |
604 | compact structures. The command line option -mstructure_size_boundary=<n> | |
f710504c | 605 | can be used to change this value. For compatibility with the ARM SDK |
723ae7c1 | 606 | however the value should be left at 32. ARM SDT Reference Manual (ARM DUI |
5848830f PB |
607 | 0020D) page 2-20 says "Structures are aligned on word boundaries". |
608 | The AAPCS specifies a value of 8. */ | |
6ead9ba5 NC |
609 | #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary |
610 | extern int arm_structure_size_boundary; | |
723ae7c1 | 611 | |
4912a07c | 612 | /* This is the value used to initialize arm_structure_size_boundary. If a |
723ae7c1 | 613 | particular arm target wants to change the default value it should change |
6bc82793 | 614 | the definition of this macro, not STRUCTURE_SIZE_BOUNDARY. See netbsd.h |
723ae7c1 NC |
615 | for an example of this. */ |
616 | #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY | |
617 | #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32 | |
b355a481 | 618 | #endif |
2a5307b1 | 619 | |
825dda42 | 620 | /* Nonzero if move instructions will actually fail to work |
ff9940b0 | 621 | when given unaligned data. */ |
35d965d5 | 622 | #define STRICT_ALIGNMENT 1 |
b6685939 PB |
623 | |
624 | /* wchar_t is unsigned under the AAPCS. */ | |
625 | #ifndef WCHAR_TYPE | |
626 | #define WCHAR_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "int") | |
627 | ||
628 | #define WCHAR_TYPE_SIZE BITS_PER_WORD | |
629 | #endif | |
630 | ||
631 | #ifndef SIZE_TYPE | |
632 | #define SIZE_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "long unsigned int") | |
633 | #endif | |
d81d0bdd | 634 | |
077fc835 KH |
635 | #ifndef PTRDIFF_TYPE |
636 | #define PTRDIFF_TYPE (TARGET_AAPCS_BASED ? "int" : "long int") | |
637 | #endif | |
638 | ||
d81d0bdd PB |
639 | /* AAPCS requires that structure alignment is affected by bitfields. */ |
640 | #ifndef PCC_BITFIELD_TYPE_MATTERS | |
641 | #define PCC_BITFIELD_TYPE_MATTERS TARGET_AAPCS_BASED | |
642 | #endif | |
643 | ||
35d965d5 RS |
644 | \f |
645 | /* Standard register usage. */ | |
646 | ||
647 | /* Register allocation in ARM Procedure Call Standard (as used on RISCiX): | |
648 | (S - saved over call). | |
649 | ||
650 | r0 * argument word/integer result | |
651 | r1-r3 argument word | |
652 | ||
653 | r4-r8 S register variable | |
654 | r9 S (rfp) register variable (real frame pointer) | |
f676971a | 655 | |
f5a1b0d2 | 656 | r10 F S (sl) stack limit (used by -mapcs-stack-check) |
35d965d5 RS |
657 | r11 F S (fp) argument pointer |
658 | r12 (ip) temp workspace | |
659 | r13 F S (sp) lower end of current stack frame | |
660 | r14 (lr) link address/workspace | |
661 | r15 F (pc) program counter | |
662 | ||
663 | f0 floating point result | |
664 | f1-f3 floating point scratch | |
665 | ||
666 | f4-f7 S floating point variable | |
667 | ||
ff9940b0 RE |
668 | cc This is NOT a real register, but is used internally |
669 | to represent things that use or set the condition | |
670 | codes. | |
671 | sfp This isn't either. It is used during rtl generation | |
672 | since the offset between the frame pointer and the | |
673 | auto's isn't known until after register allocation. | |
674 | afp Nor this, we only need this because of non-local | |
675 | goto. Without it fp appears to be used and the | |
676 | elimination code won't get rid of sfp. It tracks | |
677 | fp exactly at all times. | |
678 | ||
35d965d5 RS |
679 | *: See CONDITIONAL_REGISTER_USAGE */ |
680 | ||
9b6b54e2 NC |
681 | /* |
682 | mvf0 Cirrus floating point result | |
683 | mvf1-mvf3 Cirrus floating point scratch | |
684 | mvf4-mvf15 S Cirrus floating point variable. */ | |
685 | ||
9b66ebb1 PB |
686 | /* s0-s15 VFP scratch (aka d0-d7). |
687 | s16-s31 S VFP variable (aka d8-d15). | |
688 | vfpcc Not a real register. Represents the VFP condition | |
689 | code flags. */ | |
690 | ||
ff9940b0 RE |
691 | /* The stack backtrace structure is as follows: |
692 | fp points to here: | save code pointer | [fp] | |
693 | | return link value | [fp, #-4] | |
694 | | return sp value | [fp, #-8] | |
695 | | return fp value | [fp, #-12] | |
696 | [| saved r10 value |] | |
697 | [| saved r9 value |] | |
698 | [| saved r8 value |] | |
699 | [| saved r7 value |] | |
700 | [| saved r6 value |] | |
701 | [| saved r5 value |] | |
702 | [| saved r4 value |] | |
703 | [| saved r3 value |] | |
704 | [| saved r2 value |] | |
705 | [| saved r1 value |] | |
706 | [| saved r0 value |] | |
707 | [| saved f7 value |] three words | |
708 | [| saved f6 value |] three words | |
709 | [| saved f5 value |] three words | |
710 | [| saved f4 value |] three words | |
711 | r0-r3 are not normally saved in a C function. */ | |
712 | ||
35d965d5 RS |
713 | /* 1 for registers that have pervasive standard uses |
714 | and are not available for the register allocator. */ | |
9b66ebb1 PB |
715 | #define FIXED_REGISTERS \ |
716 | { \ | |
717 | 0,0,0,0,0,0,0,0, \ | |
718 | 0,0,0,0,0,1,0,1, \ | |
719 | 0,0,0,0,0,0,0,0, \ | |
9b6b54e2 NC |
720 | 1,1,1, \ |
721 | 1,1,1,1,1,1,1,1, \ | |
9b66ebb1 PB |
722 | 1,1,1,1,1,1,1,1, \ |
723 | 1,1,1,1,1,1,1,1, \ | |
724 | 1,1,1,1,1,1,1,1, \ | |
725 | 1,1,1,1, \ | |
726 | 1,1,1,1,1,1,1,1, \ | |
727 | 1,1,1,1,1,1,1,1, \ | |
728 | 1,1,1,1,1,1,1,1, \ | |
729 | 1,1,1,1,1,1,1,1, \ | |
f1adb0a9 JB |
730 | 1,1,1,1,1,1,1,1, \ |
731 | 1,1,1,1,1,1,1,1, \ | |
732 | 1,1,1,1,1,1,1,1, \ | |
733 | 1,1,1,1,1,1,1,1, \ | |
9b66ebb1 | 734 | 1 \ |
35d965d5 RS |
735 | } |
736 | ||
737 | /* 1 for registers not available across function calls. | |
738 | These must include the FIXED_REGISTERS and also any | |
739 | registers that can be used without being saved. | |
740 | The latter must include the registers where values are returned | |
741 | and the register where structure-value addresses are passed. | |
ff9940b0 | 742 | Aside from that, you can include as many other registers as you like. |
f676971a | 743 | The CC is not preserved over function calls on the ARM 6, so it is |
d6b4baa4 | 744 | easier to assume this for all. SFP is preserved, since FP is. */ |
35d965d5 RS |
745 | #define CALL_USED_REGISTERS \ |
746 | { \ | |
747 | 1,1,1,1,0,0,0,0, \ | |
d5b7b3ae | 748 | 0,0,0,0,1,1,1,1, \ |
ff9940b0 | 749 | 1,1,1,1,0,0,0,0, \ |
9b6b54e2 NC |
750 | 1,1,1, \ |
751 | 1,1,1,1,1,1,1,1, \ | |
5a9335ef NC |
752 | 1,1,1,1,1,1,1,1, \ |
753 | 1,1,1,1,1,1,1,1, \ | |
754 | 1,1,1,1,1,1,1,1, \ | |
9b66ebb1 PB |
755 | 1,1,1,1, \ |
756 | 1,1,1,1,1,1,1,1, \ | |
757 | 1,1,1,1,1,1,1,1, \ | |
758 | 1,1,1,1,1,1,1,1, \ | |
759 | 1,1,1,1,1,1,1,1, \ | |
f1adb0a9 JB |
760 | 1,1,1,1,1,1,1,1, \ |
761 | 1,1,1,1,1,1,1,1, \ | |
762 | 1,1,1,1,1,1,1,1, \ | |
763 | 1,1,1,1,1,1,1,1, \ | |
9b66ebb1 | 764 | 1 \ |
35d965d5 RS |
765 | } |
766 | ||
6cc8c0b3 NC |
767 | #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE |
768 | #define SUBTARGET_CONDITIONAL_REGISTER_USAGE | |
769 | #endif | |
770 | ||
d5b7b3ae RE |
771 | #define CONDITIONAL_REGISTER_USAGE \ |
772 | { \ | |
4b02997f NC |
773 | int regno; \ |
774 | \ | |
5b3e6663 | 775 | if (TARGET_SOFT_FLOAT || TARGET_THUMB1 || !TARGET_FPA) \ |
d5b7b3ae | 776 | { \ |
9b66ebb1 PB |
777 | for (regno = FIRST_FPA_REGNUM; \ |
778 | regno <= LAST_FPA_REGNUM; ++regno) \ | |
d5b7b3ae RE |
779 | fixed_regs[regno] = call_used_regs[regno] = 1; \ |
780 | } \ | |
9b6b54e2 | 781 | \ |
c769a35d RE |
782 | if (TARGET_THUMB && optimize_size) \ |
783 | { \ | |
784 | /* When optimizing for size, it's better not to use \ | |
785 | the HI regs, because of the overhead of stacking \ | |
d6b4baa4 | 786 | them. */ \ |
5b3e6663 | 787 | /* ??? Is this still true for thumb2? */ \ |
c769a35d RE |
788 | for (regno = FIRST_HI_REGNUM; \ |
789 | regno <= LAST_HI_REGNUM; ++regno) \ | |
790 | fixed_regs[regno] = call_used_regs[regno] = 1; \ | |
791 | } \ | |
792 | \ | |
fb14bc89 RE |
793 | /* The link register can be clobbered by any branch insn, \ |
794 | but we have no way to track that at present, so mark \ | |
795 | it as unavailable. */ \ | |
5b3e6663 | 796 | if (TARGET_THUMB1) \ |
fb14bc89 RE |
797 | fixed_regs[LR_REGNUM] = call_used_regs[LR_REGNUM] = 1; \ |
798 | \ | |
5b3e6663 | 799 | if (TARGET_32BIT && TARGET_HARD_FLOAT) \ |
9b6b54e2 | 800 | { \ |
9b66ebb1 | 801 | if (TARGET_MAVERICK) \ |
9b6b54e2 | 802 | { \ |
9b66ebb1 PB |
803 | for (regno = FIRST_FPA_REGNUM; \ |
804 | regno <= LAST_FPA_REGNUM; ++ regno) \ | |
805 | fixed_regs[regno] = call_used_regs[regno] = 1; \ | |
806 | for (regno = FIRST_CIRRUS_FP_REGNUM; \ | |
807 | regno <= LAST_CIRRUS_FP_REGNUM; ++ regno) \ | |
808 | { \ | |
809 | fixed_regs[regno] = 0; \ | |
810 | call_used_regs[regno] = regno < FIRST_CIRRUS_FP_REGNUM + 4; \ | |
811 | } \ | |
812 | } \ | |
813 | if (TARGET_VFP) \ | |
814 | { \ | |
f1adb0a9 JB |
815 | /* VFPv3 registers are disabled when earlier VFP \ |
816 | versions are selected due to the definition of \ | |
817 | LAST_VFP_REGNUM. */ \ | |
9b66ebb1 PB |
818 | for (regno = FIRST_VFP_REGNUM; \ |
819 | regno <= LAST_VFP_REGNUM; ++ regno) \ | |
820 | { \ | |
821 | fixed_regs[regno] = 0; \ | |
f1adb0a9 JB |
822 | call_used_regs[regno] = regno < FIRST_VFP_REGNUM + 16 \ |
823 | || regno >= FIRST_VFP_REGNUM + 32; \ | |
9b66ebb1 | 824 | } \ |
9b6b54e2 NC |
825 | } \ |
826 | } \ | |
827 | \ | |
5a9335ef NC |
828 | if (TARGET_REALLY_IWMMXT) \ |
829 | { \ | |
830 | regno = FIRST_IWMMXT_GR_REGNUM; \ | |
831 | /* The 2002/10/09 revision of the XScale ABI has wCG0 \ | |
832 | and wCG1 as call-preserved registers. The 2002/11/21 \ | |
833 | revision changed this so that all wCG registers are \ | |
834 | scratch registers. */ \ | |
835 | for (regno = FIRST_IWMMXT_GR_REGNUM; \ | |
836 | regno <= LAST_IWMMXT_GR_REGNUM; ++ regno) \ | |
119bb233 | 837 | fixed_regs[regno] = 0; \ |
5a9335ef NC |
838 | /* The XScale ABI has wR0 - wR9 as scratch registers, \ |
839 | the rest as call-preserved registers. */ \ | |
840 | for (regno = FIRST_IWMMXT_REGNUM; \ | |
841 | regno <= LAST_IWMMXT_REGNUM; ++ regno) \ | |
842 | { \ | |
843 | fixed_regs[regno] = 0; \ | |
844 | call_used_regs[regno] = regno < FIRST_IWMMXT_REGNUM + 10; \ | |
845 | } \ | |
846 | } \ | |
847 | \ | |
fc555370 | 848 | if ((unsigned) PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \ |
d5b7b3ae RE |
849 | { \ |
850 | fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ | |
851 | call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ | |
852 | } \ | |
853 | else if (TARGET_APCS_STACK) \ | |
854 | { \ | |
855 | fixed_regs[10] = 1; \ | |
856 | call_used_regs[10] = 1; \ | |
857 | } \ | |
a2503645 RS |
858 | /* -mcaller-super-interworking reserves r11 for calls to \ |
859 | _interwork_r11_call_via_rN(). Making the register global \ | |
860 | is an easy way of ensuring that it remains valid for all \ | |
861 | calls. */ \ | |
685c9c11 | 862 | if (TARGET_APCS_FRAME || TARGET_CALLER_INTERWORKING \ |
c54c7322 | 863 | || TARGET_TPCS_FRAME || TARGET_TPCS_LEAF_FRAME) \ |
d5b7b3ae RE |
864 | { \ |
865 | fixed_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \ | |
866 | call_used_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \ | |
a2503645 RS |
867 | if (TARGET_CALLER_INTERWORKING) \ |
868 | global_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \ | |
d5b7b3ae RE |
869 | } \ |
870 | SUBTARGET_CONDITIONAL_REGISTER_USAGE \ | |
35d965d5 | 871 | } |
f676971a | 872 | |
6bc82793 | 873 | /* These are a couple of extensions to the formats accepted |
dd18ae56 NC |
874 | by asm_fprintf: |
875 | %@ prints out ASM_COMMENT_START | |
876 | %r prints out REGISTER_PREFIX reg_names[arg] */ | |
877 | #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \ | |
878 | case '@': \ | |
879 | fputs (ASM_COMMENT_START, FILE); \ | |
880 | break; \ | |
881 | \ | |
882 | case 'r': \ | |
883 | fputs (REGISTER_PREFIX, FILE); \ | |
884 | fputs (reg_names [va_arg (ARGS, int)], FILE); \ | |
885 | break; | |
886 | ||
d5b7b3ae | 887 | /* Round X up to the nearest word. */ |
0c2ca901 | 888 | #define ROUND_UP_WORD(X) (((X) + 3) & ~3) |
d5b7b3ae | 889 | |
6cfc7210 | 890 | /* Convert fron bytes to ints. */ |
e9d7b180 | 891 | #define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) |
6cfc7210 | 892 | |
9b66ebb1 PB |
893 | /* The number of (integer) registers required to hold a quantity of type MODE. |
894 | Also used for VFP registers. */ | |
e9d7b180 JD |
895 | #define ARM_NUM_REGS(MODE) \ |
896 | ARM_NUM_INTS (GET_MODE_SIZE (MODE)) | |
6cfc7210 NC |
897 | |
898 | /* The number of (integer) registers required to hold a quantity of TYPE MODE. */ | |
e9d7b180 JD |
899 | #define ARM_NUM_REGS2(MODE, TYPE) \ |
900 | ARM_NUM_INTS ((MODE) == BLKmode ? \ | |
d5b7b3ae | 901 | int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE)) |
6cfc7210 NC |
902 | |
903 | /* The number of (integer) argument register available. */ | |
d5b7b3ae | 904 | #define NUM_ARG_REGS 4 |
6cfc7210 | 905 | |
390b17c2 RE |
906 | /* And similarly for the VFP. */ |
907 | #define NUM_VFP_ARG_REGS 16 | |
908 | ||
093354e0 | 909 | /* Return the register number of the N'th (integer) argument. */ |
d5b7b3ae | 910 | #define ARG_REGISTER(N) (N - 1) |
6cfc7210 | 911 | |
d5b7b3ae RE |
912 | /* Specify the registers used for certain standard purposes. |
913 | The values of these macros are register numbers. */ | |
35d965d5 | 914 | |
d5b7b3ae RE |
915 | /* The number of the last argument register. */ |
916 | #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS) | |
35d965d5 | 917 | |
c769a35d RE |
918 | /* The numbers of the Thumb register ranges. */ |
919 | #define FIRST_LO_REGNUM 0 | |
6d3d9133 | 920 | #define LAST_LO_REGNUM 7 |
c769a35d RE |
921 | #define FIRST_HI_REGNUM 8 |
922 | #define LAST_HI_REGNUM 11 | |
6d3d9133 | 923 | |
617a1b71 | 924 | #ifndef TARGET_UNWIND_INFO |
c9ca9b88 PB |
925 | /* We use sjlj exceptions for backwards compatibility. */ |
926 | #define MUST_USE_SJLJ_EXCEPTIONS 1 | |
617a1b71 PB |
927 | #endif |
928 | ||
c9ca9b88 PB |
929 | /* We can generate DWARF2 Unwind info, even though we don't use it. */ |
930 | #define DWARF2_UNWIND_INFO 1 | |
f676971a | 931 | |
c9ca9b88 PB |
932 | /* Use r0 and r1 to pass exception handling information. */ |
933 | #define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? N : INVALID_REGNUM) | |
934 | ||
6d3d9133 | 935 | /* The register that holds the return address in exception handlers. */ |
c9ca9b88 PB |
936 | #define ARM_EH_STACKADJ_REGNUM 2 |
937 | #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (SImode, ARM_EH_STACKADJ_REGNUM) | |
35d965d5 | 938 | |
d5b7b3ae RE |
939 | /* The native (Norcroft) Pascal compiler for the ARM passes the static chain |
940 | as an invisible last argument (possible since varargs don't exist in | |
941 | Pascal), so the following is not true. */ | |
5b3e6663 | 942 | #define STATIC_CHAIN_REGNUM 12 |
35d965d5 | 943 | |
d5b7b3ae RE |
944 | /* Define this to be where the real frame pointer is if it is not possible to |
945 | work out the offset between the frame pointer and the automatic variables | |
946 | until after register allocation has taken place. FRAME_POINTER_REGNUM | |
947 | should point to a special register that we will make sure is eliminated. | |
948 | ||
949 | For the Thumb we have another problem. The TPCS defines the frame pointer | |
6bc82793 | 950 | as r11, and GCC believes that it is always possible to use the frame pointer |
d5b7b3ae RE |
951 | as base register for addressing purposes. (See comments in |
952 | find_reloads_address()). But - the Thumb does not allow high registers, | |
953 | including r11, to be used as base address registers. Hence our problem. | |
954 | ||
955 | The solution used here, and in the old thumb port is to use r7 instead of | |
956 | r11 as the hard frame pointer and to have special code to generate | |
957 | backtrace structures on the stack (if required to do so via a command line | |
6bc82793 | 958 | option) using r11. This is the only 'user visible' use of r11 as a frame |
d5b7b3ae RE |
959 | pointer. */ |
960 | #define ARM_HARD_FRAME_POINTER_REGNUM 11 | |
961 | #define THUMB_HARD_FRAME_POINTER_REGNUM 7 | |
35d965d5 | 962 | |
b15bca31 RE |
963 | #define HARD_FRAME_POINTER_REGNUM \ |
964 | (TARGET_ARM \ | |
965 | ? ARM_HARD_FRAME_POINTER_REGNUM \ | |
966 | : THUMB_HARD_FRAME_POINTER_REGNUM) | |
d5b7b3ae | 967 | |
b15bca31 | 968 | #define FP_REGNUM HARD_FRAME_POINTER_REGNUM |
d5b7b3ae | 969 | |
b15bca31 RE |
970 | /* Register to use for pushing function arguments. */ |
971 | #define STACK_POINTER_REGNUM SP_REGNUM | |
d5b7b3ae RE |
972 | |
973 | /* ARM floating pointer registers. */ | |
9b66ebb1 PB |
974 | #define FIRST_FPA_REGNUM 16 |
975 | #define LAST_FPA_REGNUM 23 | |
2fa330b2 PB |
976 | #define IS_FPA_REGNUM(REGNUM) \ |
977 | (((REGNUM) >= FIRST_FPA_REGNUM) && ((REGNUM) <= LAST_FPA_REGNUM)) | |
d5b7b3ae | 978 | |
5a9335ef NC |
979 | #define FIRST_IWMMXT_GR_REGNUM 43 |
980 | #define LAST_IWMMXT_GR_REGNUM 46 | |
981 | #define FIRST_IWMMXT_REGNUM 47 | |
982 | #define LAST_IWMMXT_REGNUM 62 | |
983 | #define IS_IWMMXT_REGNUM(REGNUM) \ | |
984 | (((REGNUM) >= FIRST_IWMMXT_REGNUM) && ((REGNUM) <= LAST_IWMMXT_REGNUM)) | |
985 | #define IS_IWMMXT_GR_REGNUM(REGNUM) \ | |
986 | (((REGNUM) >= FIRST_IWMMXT_GR_REGNUM) && ((REGNUM) <= LAST_IWMMXT_GR_REGNUM)) | |
987 | ||
35d965d5 | 988 | /* Base register for access to local variables of the function. */ |
ff9940b0 RE |
989 | #define FRAME_POINTER_REGNUM 25 |
990 | ||
d5b7b3ae RE |
991 | /* Base register for access to arguments of the function. */ |
992 | #define ARG_POINTER_REGNUM 26 | |
62b10bbc | 993 | |
9b6b54e2 NC |
994 | #define FIRST_CIRRUS_FP_REGNUM 27 |
995 | #define LAST_CIRRUS_FP_REGNUM 42 | |
996 | #define IS_CIRRUS_REGNUM(REGNUM) \ | |
997 | (((REGNUM) >= FIRST_CIRRUS_FP_REGNUM) && ((REGNUM) <= LAST_CIRRUS_FP_REGNUM)) | |
998 | ||
9b66ebb1 | 999 | #define FIRST_VFP_REGNUM 63 |
f1adb0a9 JB |
1000 | #define D7_VFP_REGNUM 78 /* Registers 77 and 78 == VFP reg D7. */ |
1001 | #define LAST_VFP_REGNUM \ | |
302c3d8e | 1002 | (TARGET_VFPD32 ? LAST_HI_VFP_REGNUM : LAST_LO_VFP_REGNUM) |
f1adb0a9 | 1003 | |
9b66ebb1 PB |
1004 | #define IS_VFP_REGNUM(REGNUM) \ |
1005 | (((REGNUM) >= FIRST_VFP_REGNUM) && ((REGNUM) <= LAST_VFP_REGNUM)) | |
1006 | ||
f1adb0a9 JB |
1007 | /* VFP registers are split into two types: those defined by VFP versions < 3 |
1008 | have D registers overlaid on consecutive pairs of S registers. VFP version 3 | |
1009 | defines 16 new D registers (d16-d31) which, for simplicity and correctness | |
1010 | in various parts of the backend, we implement as "fake" single-precision | |
1011 | registers (which would be S32-S63, but cannot be used in that way). The | |
1012 | following macros define these ranges of registers. */ | |
1013 | #define LAST_LO_VFP_REGNUM 94 | |
1014 | #define FIRST_HI_VFP_REGNUM 95 | |
1015 | #define LAST_HI_VFP_REGNUM 126 | |
1016 | ||
1017 | #define VFP_REGNO_OK_FOR_SINGLE(REGNUM) \ | |
1018 | ((REGNUM) <= LAST_LO_VFP_REGNUM) | |
1019 | ||
1020 | /* DFmode values are only valid in even register pairs. */ | |
1021 | #define VFP_REGNO_OK_FOR_DOUBLE(REGNUM) \ | |
1022 | ((((REGNUM) - FIRST_VFP_REGNUM) & 1) == 0) | |
1023 | ||
88f77cba JB |
1024 | /* Neon Quad values must start at a multiple of four registers. */ |
1025 | #define NEON_REGNO_OK_FOR_QUAD(REGNUM) \ | |
1026 | ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0) | |
1027 | ||
1028 | /* Neon structures of vectors must be in even register pairs and there | |
1029 | must be enough registers available. Because of various patterns | |
1030 | requiring quad registers, we require them to start at a multiple of | |
1031 | four. */ | |
1032 | #define NEON_REGNO_OK_FOR_NREGS(REGNUM, N) \ | |
1033 | ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0 \ | |
1034 | && (LAST_VFP_REGNUM - (REGNUM) >= 2 * (N) - 1)) | |
1035 | ||
6f8c9bd1 NC |
1036 | /* The number of hard registers is 16 ARM + 8 FPA + 1 CC + 1 SFP + 1 AFP. */ |
1037 | /* + 16 Cirrus registers take us up to 43. */ | |
5a9335ef | 1038 | /* Intel Wireless MMX Technology registers add 16 + 4 more. */ |
f1adb0a9 JB |
1039 | /* VFP (VFP3) adds 32 (64) + 1 more. */ |
1040 | #define FIRST_PSEUDO_REGISTER 128 | |
62b10bbc | 1041 | |
2fa330b2 PB |
1042 | #define DBX_REGISTER_NUMBER(REGNO) arm_dbx_register_number (REGNO) |
1043 | ||
35d965d5 RS |
1044 | /* Value should be nonzero if functions must have frame pointers. |
1045 | Zero means the frame pointer need not be set up (and parms may be accessed | |
f676971a | 1046 | via the stack pointer) in functions that seem suitable. |
ff9940b0 RE |
1047 | If we have to have a frame pointer we might as well make use of it. |
1048 | APCS says that the frame pointer does not need to be pushed in leaf | |
2a5307b1 | 1049 | functions, or simple tail call functions. */ |
a15900b5 DJ |
1050 | |
1051 | #ifndef SUBTARGET_FRAME_POINTER_REQUIRED | |
1052 | #define SUBTARGET_FRAME_POINTER_REQUIRED 0 | |
1053 | #endif | |
1054 | ||
d5b7b3ae RE |
1055 | /* Return number of consecutive hard regs needed starting at reg REGNO |
1056 | to hold something of mode MODE. | |
1057 | This is ordinarily the length in words of a value of mode MODE | |
1058 | but can be less for certain modes in special long registers. | |
35d965d5 | 1059 | |
3b684012 | 1060 | On the ARM regs are UNITS_PER_WORD bits wide; FPA regs can hold any FP |
d5b7b3ae RE |
1061 | mode. */ |
1062 | #define HARD_REGNO_NREGS(REGNO, MODE) \ | |
5b3e6663 | 1063 | ((TARGET_32BIT \ |
9b66ebb1 | 1064 | && REGNO >= FIRST_FPA_REGNUM \ |
d5b7b3ae RE |
1065 | && REGNO != FRAME_POINTER_REGNUM \ |
1066 | && REGNO != ARG_POINTER_REGNUM) \ | |
9b66ebb1 | 1067 | && !IS_VFP_REGNUM (REGNO) \ |
e9d7b180 | 1068 | ? 1 : ARM_NUM_REGS (MODE)) |
35d965d5 | 1069 | |
4b02997f | 1070 | /* Return true if REGNO is suitable for holding a quantity of type MODE. */ |
d5b7b3ae | 1071 | #define HARD_REGNO_MODE_OK(REGNO, MODE) \ |
4b02997f | 1072 | arm_hard_regno_mode_ok ((REGNO), (MODE)) |
35d965d5 | 1073 | |
d5b7b3ae RE |
1074 | /* Value is 1 if it is a good idea to tie two pseudo registers |
1075 | when one has mode MODE1 and one has mode MODE2. | |
1076 | If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, | |
1077 | for any hard reg, then this must be 0 for correct output. */ | |
1078 | #define MODES_TIEABLE_P(MODE1, MODE2) \ | |
1079 | (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2)) | |
ff9940b0 | 1080 | |
5a9335ef | 1081 | #define VALID_IWMMXT_REG_MODE(MODE) \ |
f676971a | 1082 | (arm_vector_mode_supported_p (MODE) || (MODE) == DImode) |
5a9335ef | 1083 | |
88f77cba JB |
1084 | /* Modes valid for Neon D registers. */ |
1085 | #define VALID_NEON_DREG_MODE(MODE) \ | |
1086 | ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode \ | |
1087 | || (MODE) == V2SFmode || (MODE) == DImode) | |
1088 | ||
1089 | /* Modes valid for Neon Q registers. */ | |
1090 | #define VALID_NEON_QREG_MODE(MODE) \ | |
1091 | ((MODE) == V4SImode || (MODE) == V8HImode || (MODE) == V16QImode \ | |
1092 | || (MODE) == V4SFmode || (MODE) == V2DImode) | |
1093 | ||
1094 | /* Structure modes valid for Neon registers. */ | |
1095 | #define VALID_NEON_STRUCT_MODE(MODE) \ | |
1096 | ((MODE) == TImode || (MODE) == EImode || (MODE) == OImode \ | |
1097 | || (MODE) == CImode || (MODE) == XImode) | |
1098 | ||
35d965d5 | 1099 | /* The order in which register should be allocated. It is good to use ip |
ff9940b0 RE |
1100 | since no saving is required (though calls clobber it) and it never contains |
1101 | function parameters. It is quite good to use lr since other calls may | |
f676971a | 1102 | clobber it anyway. Allocate r0 through r3 in reverse order since r3 is |
ff9940b0 | 1103 | least likely to contain a function parameter; in addition results are |
f1adb0a9 JB |
1104 | returned in r0. |
1105 | For VFP/VFPv3, allocate D16-D31 first, then caller-saved registers (D0-D7), | |
1106 | then D8-D15. The reason for doing this is to attempt to reduce register | |
1107 | pressure when both single- and double-precision registers are used in a | |
1108 | function. */ | |
1109 | ||
1110 | #define REG_ALLOC_ORDER \ | |
1111 | { \ | |
1112 | 3, 2, 1, 0, 12, 14, 4, 5, \ | |
1113 | 6, 7, 8, 10, 9, 11, 13, 15, \ | |
1114 | 16, 17, 18, 19, 20, 21, 22, 23, \ | |
1115 | 27, 28, 29, 30, 31, 32, 33, 34, \ | |
1116 | 35, 36, 37, 38, 39, 40, 41, 42, \ | |
1117 | 43, 44, 45, 46, 47, 48, 49, 50, \ | |
1118 | 51, 52, 53, 54, 55, 56, 57, 58, \ | |
1119 | 59, 60, 61, 62, \ | |
1120 | 24, 25, 26, \ | |
1121 | 95, 96, 97, 98, 99, 100, 101, 102, \ | |
1122 | 103, 104, 105, 106, 107, 108, 109, 110, \ | |
1123 | 111, 112, 113, 114, 115, 116, 117, 118, \ | |
1124 | 119, 120, 121, 122, 123, 124, 125, 126, \ | |
1125 | 78, 77, 76, 75, 74, 73, 72, 71, \ | |
1126 | 70, 69, 68, 67, 66, 65, 64, 63, \ | |
1127 | 79, 80, 81, 82, 83, 84, 85, 86, \ | |
1128 | 87, 88, 89, 90, 91, 92, 93, 94, \ | |
1129 | 127 \ | |
35d965d5 | 1130 | } |
9338ffe6 | 1131 | |
795dc4fc PB |
1132 | /* Use different register alloc ordering for Thumb. */ |
1133 | #define ORDER_REGS_FOR_LOCAL_ALLOC arm_order_regs_for_local_alloc () | |
1134 | ||
9338ffe6 PB |
1135 | /* Interrupt functions can only use registers that have already been |
1136 | saved by the prologue, even if they would normally be | |
1137 | call-clobbered. */ | |
1138 | #define HARD_REGNO_RENAME_OK(SRC, DST) \ | |
1139 | (! IS_INTERRUPT (cfun->machine->func_type) || \ | |
6fb5fa3c | 1140 | df_regs_ever_live_p (DST)) |
35d965d5 RS |
1141 | \f |
1142 | /* Register and constant classes. */ | |
1143 | ||
3b684012 | 1144 | /* Register classes: used to be simple, just all ARM regs or all FPA regs |
d6a7951f | 1145 | Now that the Thumb is involved it has become more complicated. */ |
35d965d5 RS |
1146 | enum reg_class |
1147 | { | |
1148 | NO_REGS, | |
3b684012 | 1149 | FPA_REGS, |
9b6b54e2 | 1150 | CIRRUS_REGS, |
f1adb0a9 JB |
1151 | VFP_D0_D7_REGS, |
1152 | VFP_LO_REGS, | |
1153 | VFP_HI_REGS, | |
9b66ebb1 | 1154 | VFP_REGS, |
5a9335ef NC |
1155 | IWMMXT_GR_REGS, |
1156 | IWMMXT_REGS, | |
d5b7b3ae RE |
1157 | LO_REGS, |
1158 | STACK_REG, | |
1159 | BASE_REGS, | |
1160 | HI_REGS, | |
1161 | CC_REG, | |
9b66ebb1 | 1162 | VFPCC_REG, |
35d965d5 | 1163 | GENERAL_REGS, |
f5c630c3 | 1164 | CORE_REGS, |
35d965d5 RS |
1165 | ALL_REGS, |
1166 | LIM_REG_CLASSES | |
1167 | }; | |
1168 | ||
1169 | #define N_REG_CLASSES (int) LIM_REG_CLASSES | |
1170 | ||
d6b4baa4 | 1171 | /* Give names of register classes as strings for dump file. */ |
35d965d5 RS |
1172 | #define REG_CLASS_NAMES \ |
1173 | { \ | |
1174 | "NO_REGS", \ | |
3b684012 | 1175 | "FPA_REGS", \ |
9b6b54e2 | 1176 | "CIRRUS_REGS", \ |
f1adb0a9 JB |
1177 | "VFP_D0_D7_REGS", \ |
1178 | "VFP_LO_REGS", \ | |
1179 | "VFP_HI_REGS", \ | |
9b66ebb1 | 1180 | "VFP_REGS", \ |
5a9335ef NC |
1181 | "IWMMXT_GR_REGS", \ |
1182 | "IWMMXT_REGS", \ | |
d5b7b3ae RE |
1183 | "LO_REGS", \ |
1184 | "STACK_REG", \ | |
1185 | "BASE_REGS", \ | |
1186 | "HI_REGS", \ | |
1187 | "CC_REG", \ | |
5384443a | 1188 | "VFPCC_REG", \ |
35d965d5 | 1189 | "GENERAL_REGS", \ |
f5c630c3 | 1190 | "CORE_REGS", \ |
35d965d5 RS |
1191 | "ALL_REGS", \ |
1192 | } | |
1193 | ||
1194 | /* Define which registers fit in which classes. | |
1195 | This is an initializer for a vector of HARD_REG_SET | |
1196 | of length N_REG_CLASSES. */ | |
f1adb0a9 JB |
1197 | #define REG_CLASS_CONTENTS \ |
1198 | { \ | |
1199 | { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \ | |
1200 | { 0x00FF0000, 0x00000000, 0x00000000, 0x00000000 }, /* FPA_REGS */ \ | |
1201 | { 0xF8000000, 0x000007FF, 0x00000000, 0x00000000 }, /* CIRRUS_REGS */ \ | |
1202 | { 0x00000000, 0x80000000, 0x00007FFF, 0x00000000 }, /* VFP_D0_D7_REGS */ \ | |
1203 | { 0x00000000, 0x80000000, 0x7FFFFFFF, 0x00000000 }, /* VFP_LO_REGS */ \ | |
1204 | { 0x00000000, 0x00000000, 0x80000000, 0x7FFFFFFF }, /* VFP_HI_REGS */ \ | |
1205 | { 0x00000000, 0x80000000, 0xFFFFFFFF, 0x7FFFFFFF }, /* VFP_REGS */ \ | |
1206 | { 0x00000000, 0x00007800, 0x00000000, 0x00000000 }, /* IWMMXT_GR_REGS */ \ | |
1207 | { 0x00000000, 0x7FFF8000, 0x00000000, 0x00000000 }, /* IWMMXT_REGS */ \ | |
1208 | { 0x000000FF, 0x00000000, 0x00000000, 0x00000000 }, /* LO_REGS */ \ | |
1209 | { 0x00002000, 0x00000000, 0x00000000, 0x00000000 }, /* STACK_REG */ \ | |
1210 | { 0x000020FF, 0x00000000, 0x00000000, 0x00000000 }, /* BASE_REGS */ \ | |
f5c630c3 | 1211 | { 0x0000DF00, 0x00000000, 0x00000000, 0x00000000 }, /* HI_REGS */ \ |
f1adb0a9 JB |
1212 | { 0x01000000, 0x00000000, 0x00000000, 0x00000000 }, /* CC_REG */ \ |
1213 | { 0x00000000, 0x00000000, 0x00000000, 0x80000000 }, /* VFPCC_REG */ \ | |
f5c630c3 PB |
1214 | { 0x0200DFFF, 0x00000000, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \ |
1215 | { 0x0200FFFF, 0x00000000, 0x00000000, 0x00000000 }, /* CORE_REGS */ \ | |
f1adb0a9 | 1216 | { 0xFAFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x7FFFFFFF } /* ALL_REGS */ \ |
35d965d5 | 1217 | } |
4b02997f | 1218 | |
f1adb0a9 JB |
1219 | /* Any of the VFP register classes. */ |
1220 | #define IS_VFP_CLASS(X) \ | |
1221 | ((X) == VFP_D0_D7_REGS || (X) == VFP_LO_REGS \ | |
1222 | || (X) == VFP_HI_REGS || (X) == VFP_REGS) | |
1223 | ||
35d965d5 RS |
1224 | /* The same information, inverted: |
1225 | Return the class number of the smallest class containing | |
1226 | reg number REGNO. This could be a conditional expression | |
1227 | or could index an array. */ | |
d5b7b3ae | 1228 | #define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO) |
35d965d5 | 1229 | |
058e97ec VM |
1230 | /* The following macro defines cover classes for Integrated Register |
1231 | Allocator. Cover classes is a set of non-intersected register | |
1232 | classes covering all hard registers used for register allocation | |
1233 | purpose. Any move between two registers of a cover class should be | |
1234 | cheaper than load or store of the registers. The macro value is | |
1235 | array of register classes with LIM_REG_CLASSES used as the end | |
1236 | marker. */ | |
1237 | ||
1238 | #define IRA_COVER_CLASSES \ | |
1239 | { \ | |
1240 | GENERAL_REGS, FPA_REGS, CIRRUS_REGS, VFP_REGS, IWMMXT_GR_REGS, IWMMXT_REGS,\ | |
1241 | LIM_REG_CLASSES \ | |
1242 | } | |
1243 | ||
9b66ebb1 | 1244 | /* FPA registers can't do subreg as all values are reformatted to internal |
59b9a953 | 1245 | precision. VFP registers may only be accessed in the mode they |
9b66ebb1 | 1246 | were set. */ |
75d2580c RE |
1247 | #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ |
1248 | (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \ | |
9b66ebb1 PB |
1249 | ? reg_classes_intersect_p (FPA_REGS, (CLASS)) \ |
1250 | || reg_classes_intersect_p (VFP_REGS, (CLASS)) \ | |
1251 | : 0) | |
75d2580c | 1252 | |
cc81dde8 PB |
1253 | /* We need to define this for LO_REGS on thumb. Otherwise we can end up |
1254 | using r0-r4 for function arguments, r7 for the stack frame and don't | |
1255 | have enough left over to do doubleword arithmetic. */ | |
1256 | #define CLASS_LIKELY_SPILLED_P(CLASS) \ | |
1257 | ((TARGET_THUMB && (CLASS) == LO_REGS) \ | |
1258 | || (CLASS) == CC_REG) | |
f676971a | 1259 | |
35d965d5 | 1260 | /* The class value for index registers, and the one for base regs. */ |
5b3e6663 | 1261 | #define INDEX_REG_CLASS (TARGET_THUMB1 ? LO_REGS : GENERAL_REGS) |
f5c630c3 | 1262 | #define BASE_REG_CLASS (TARGET_THUMB1 ? LO_REGS : CORE_REGS) |
d5b7b3ae | 1263 | |
b93a0fe6 | 1264 | /* For the Thumb the high registers cannot be used as base registers |
6bc82793 | 1265 | when addressing quantities in QI or HI mode; if we don't know the |
888d2cd6 | 1266 | mode, then we must be conservative. */ |
3dcc68a4 | 1267 | #define MODE_BASE_REG_CLASS(MODE) \ |
f5c630c3 | 1268 | (TARGET_32BIT ? CORE_REGS : \ |
888d2cd6 DJ |
1269 | (((MODE) == SImode) ? BASE_REGS : LO_REGS)) |
1270 | ||
1271 | /* For Thumb we can not support SP+reg addressing, so we return LO_REGS | |
1272 | instead of BASE_REGS. */ | |
1273 | #define MODE_BASE_REG_REG_CLASS(MODE) BASE_REG_CLASS | |
3dcc68a4 | 1274 | |
d5b7b3ae RE |
1275 | /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows |
1276 | registers explicitly used in the rtl to be used as spill registers | |
1277 | but prevents the compiler from extending the lifetime of these | |
d6b4baa4 | 1278 | registers. */ |
5b3e6663 | 1279 | #define SMALL_REGISTER_CLASSES TARGET_THUMB1 |
35d965d5 | 1280 | |
35d965d5 RS |
1281 | /* Given an rtx X being reloaded into a reg required to be |
1282 | in class CLASS, return the class of reg to actually use. | |
5b3e6663 PB |
1283 | In general this is just CLASS, but for the Thumb core registers and |
1284 | immediate constants we prefer a LO_REGS class or a subset. */ | |
1285 | #define PREFERRED_RELOAD_CLASS(X, CLASS) \ | |
1286 | (TARGET_ARM ? (CLASS) : \ | |
1287 | ((CLASS) == GENERAL_REGS || (CLASS) == HI_REGS \ | |
f5c630c3 PB |
1288 | || (CLASS) == NO_REGS || (CLASS) == STACK_REG \ |
1289 | ? LO_REGS : (CLASS))) | |
d5b7b3ae RE |
1290 | |
1291 | /* Must leave BASE_REGS reloads alone */ | |
1292 | #define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \ | |
1293 | ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \ | |
1294 | ? ((true_regnum (X) == -1 ? LO_REGS \ | |
1295 | : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \ | |
1296 | : NO_REGS)) \ | |
1297 | : NO_REGS) | |
1298 | ||
1299 | #define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \ | |
97358092 | 1300 | ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \ |
d5b7b3ae RE |
1301 | ? ((true_regnum (X) == -1 ? LO_REGS \ |
1302 | : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \ | |
1303 | : NO_REGS)) \ | |
1304 | : NO_REGS) | |
35d965d5 | 1305 | |
ff9940b0 RE |
1306 | /* Return the register class of a scratch register needed to copy IN into |
1307 | or out of a register in CLASS in MODE. If it can be done directly, | |
1308 | NO_REGS is returned. */ | |
d5b7b3ae | 1309 | #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \ |
fe2d934b | 1310 | /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \ |
9b66ebb1 | 1311 | ((TARGET_VFP && TARGET_HARD_FLOAT \ |
f1adb0a9 | 1312 | && IS_VFP_CLASS (CLASS)) \ |
fe2d934b PB |
1313 | ? coproc_secondary_reload_class (MODE, X, FALSE) \ |
1314 | : (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) \ | |
1315 | ? coproc_secondary_reload_class (MODE, X, TRUE) \ | |
5b3e6663 | 1316 | : TARGET_32BIT \ |
9b66ebb1 | 1317 | ? (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \ |
d5b7b3ae RE |
1318 | ? GENERAL_REGS : NO_REGS) \ |
1319 | : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X)) | |
f676971a | 1320 | |
d6b4baa4 | 1321 | /* If we need to load shorts byte-at-a-time, then we need a scratch. */ |
d5b7b3ae | 1322 | #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \ |
fe2d934b | 1323 | /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \ |
9b66ebb1 | 1324 | ((TARGET_VFP && TARGET_HARD_FLOAT \ |
f1adb0a9 | 1325 | && IS_VFP_CLASS (CLASS)) \ |
fe2d934b PB |
1326 | ? coproc_secondary_reload_class (MODE, X, FALSE) : \ |
1327 | (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) ? \ | |
1328 | coproc_secondary_reload_class (MODE, X, TRUE) : \ | |
9b6b54e2 | 1329 | /* Cannot load constants into Cirrus registers. */ \ |
9b66ebb1 | 1330 | (TARGET_MAVERICK && TARGET_HARD_FLOAT \ |
9b6b54e2 NC |
1331 | && (CLASS) == CIRRUS_REGS \ |
1332 | && (CONSTANT_P (X) || GET_CODE (X) == SYMBOL_REF)) \ | |
1333 | ? GENERAL_REGS : \ | |
5b3e6663 | 1334 | (TARGET_32BIT ? \ |
5a9335ef NC |
1335 | (((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \ |
1336 | && CONSTANT_P (X)) \ | |
1337 | ? GENERAL_REGS : \ | |
61f0ccff | 1338 | (((MODE) == HImode && ! arm_arch4 \ |
d5b7b3ae RE |
1339 | && (GET_CODE (X) == MEM \ |
1340 | || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \ | |
1341 | && true_regnum (X) == -1))) \ | |
1342 | ? GENERAL_REGS : NO_REGS) \ | |
9b6b54e2 | 1343 | : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X))) |
2ce9c1b9 | 1344 | |
6f734908 RE |
1345 | /* Try a machine-dependent way of reloading an illegitimate address |
1346 | operand. If we find one, push the reload and jump to WIN. This | |
1347 | macro is used in only one place: `find_reloads_address' in reload.c. | |
1348 | ||
1349 | For the ARM, we wish to handle large displacements off a base | |
1350 | register by splitting the addend across a MOV and the mem insn. | |
d5b7b3ae RE |
1351 | This can cut the number of reloads needed. */ |
1352 | #define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN) \ | |
1353 | do \ | |
1354 | { \ | |
1355 | if (GET_CODE (X) == PLUS \ | |
1356 | && GET_CODE (XEXP (X, 0)) == REG \ | |
1357 | && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \ | |
1358 | && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \ | |
1359 | && GET_CODE (XEXP (X, 1)) == CONST_INT) \ | |
1360 | { \ | |
1361 | HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \ | |
1362 | HOST_WIDE_INT low, high; \ | |
1363 | \ | |
de6f27a8 | 1364 | if (MODE == DImode || (MODE == DFmode && TARGET_SOFT_FLOAT)) \ |
d5b7b3ae | 1365 | low = ((val & 0xf) ^ 0x8) - 0x8; \ |
9b66ebb1 | 1366 | else if (TARGET_MAVERICK && TARGET_HARD_FLOAT) \ |
9b6b54e2 NC |
1367 | /* Need to be careful, -256 is not a valid offset. */ \ |
1368 | low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \ | |
d5b7b3ae | 1369 | else if (MODE == SImode \ |
de6f27a8 | 1370 | || (MODE == SFmode && TARGET_SOFT_FLOAT) \ |
d5b7b3ae RE |
1371 | || ((MODE == HImode || MODE == QImode) && ! arm_arch4)) \ |
1372 | /* Need to be careful, -4096 is not a valid offset. */ \ | |
1373 | low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff); \ | |
1374 | else if ((MODE == HImode || MODE == QImode) && arm_arch4) \ | |
1375 | /* Need to be careful, -256 is not a valid offset. */ \ | |
1376 | low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \ | |
1377 | else if (GET_MODE_CLASS (MODE) == MODE_FLOAT \ | |
9b66ebb1 | 1378 | && TARGET_HARD_FLOAT && TARGET_FPA) \ |
d5b7b3ae RE |
1379 | /* Need to be careful, -1024 is not a valid offset. */ \ |
1380 | low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \ | |
1381 | else \ | |
1382 | break; \ | |
1383 | \ | |
30cf4896 KG |
1384 | high = ((((val - low) & (unsigned HOST_WIDE_INT) 0xffffffff) \ |
1385 | ^ (unsigned HOST_WIDE_INT) 0x80000000) \ | |
1386 | - (unsigned HOST_WIDE_INT) 0x80000000); \ | |
d5b7b3ae RE |
1387 | /* Check for overflow or zero */ \ |
1388 | if (low == 0 || high == 0 || (high + low != val)) \ | |
1389 | break; \ | |
1390 | \ | |
1391 | /* Reload the high part into a base reg; leave the low part \ | |
1392 | in the mem. */ \ | |
1393 | X = gen_rtx_PLUS (GET_MODE (X), \ | |
1394 | gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \ | |
1395 | GEN_INT (high)), \ | |
1396 | GEN_INT (low)); \ | |
df4ae160 | 1397 | push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \ |
4a692617 NC |
1398 | MODE_BASE_REG_CLASS (MODE), GET_MODE (X), \ |
1399 | VOIDmode, 0, 0, OPNUM, TYPE); \ | |
d5b7b3ae RE |
1400 | goto WIN; \ |
1401 | } \ | |
1402 | } \ | |
62b10bbc | 1403 | while (0) |
6f734908 | 1404 | |
27847754 | 1405 | /* XXX If an HImode FP+large_offset address is converted to an HImode |
d5b7b3ae RE |
1406 | SP+large_offset address, then reload won't know how to fix it. It sees |
1407 | only that SP isn't valid for HImode, and so reloads the SP into an index | |
1408 | register, but the resulting address is still invalid because the offset | |
1409 | is too big. We fix it here instead by reloading the entire address. */ | |
1410 | /* We could probably achieve better results by defining PROMOTE_MODE to help | |
1411 | cope with the variances between the Thumb's signed and unsigned byte and | |
1412 | halfword load instructions. */ | |
5b3e6663 | 1413 | /* ??? This should be safe for thumb2, but we may be able to do better. */ |
a132dad6 RE |
1414 | #define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_L, WIN) \ |
1415 | do { \ | |
1416 | rtx new_x = thumb_legitimize_reload_address (&X, MODE, OPNUM, TYPE, IND_L); \ | |
1417 | if (new_x) \ | |
1418 | { \ | |
1419 | X = new_x; \ | |
1420 | goto WIN; \ | |
1421 | } \ | |
1422 | } while (0) | |
d5b7b3ae RE |
1423 | |
1424 | #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \ | |
1425 | if (TARGET_ARM) \ | |
1426 | ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \ | |
1427 | else \ | |
1428 | THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) | |
f676971a | 1429 | |
35d965d5 RS |
1430 | /* Return the maximum number of consecutive registers |
1431 | needed to represent mode MODE in a register of class CLASS. | |
3b684012 | 1432 | ARM regs are UNITS_PER_WORD bits while FPA regs can hold any FP mode */ |
35d965d5 | 1433 | #define CLASS_MAX_NREGS(CLASS, MODE) \ |
3b684012 | 1434 | (((CLASS) == FPA_REGS || (CLASS) == CIRRUS_REGS) ? 1 : ARM_NUM_REGS (MODE)) |
9b6b54e2 NC |
1435 | |
1436 | /* If defined, gives a class of registers that cannot be used as the | |
1437 | operand of a SUBREG that changes the mode of the object illegally. */ | |
35d965d5 | 1438 | |
356ecb15 DJ |
1439 | /* Moves between FPA_REGS and GENERAL_REGS are two memory insns. |
1440 | Moves between VFP_REGS and GENERAL_REGS are a single insn, but | |
1441 | it is typically more expensive than a single memory access. We set | |
1442 | the cost to less than two memory accesses so that floating | |
1443 | point to integer conversion does not go through memory. */ | |
cf011243 | 1444 | #define REGISTER_MOVE_COST(MODE, FROM, TO) \ |
5b3e6663 | 1445 | (TARGET_32BIT ? \ |
3b684012 RE |
1446 | ((FROM) == FPA_REGS && (TO) != FPA_REGS ? 20 : \ |
1447 | (FROM) != FPA_REGS && (TO) == FPA_REGS ? 20 : \ | |
356ecb15 DJ |
1448 | IS_VFP_CLASS (FROM) && !IS_VFP_CLASS (TO) ? 15 : \ |
1449 | !IS_VFP_CLASS (FROM) && IS_VFP_CLASS (TO) ? 15 : \ | |
5a9335ef NC |
1450 | (FROM) == IWMMXT_REGS && (TO) != IWMMXT_REGS ? 4 : \ |
1451 | (FROM) != IWMMXT_REGS && (TO) == IWMMXT_REGS ? 4 : \ | |
1452 | (FROM) == IWMMXT_GR_REGS || (TO) == IWMMXT_GR_REGS ? 20 : \ | |
9b6b54e2 NC |
1453 | (FROM) == CIRRUS_REGS && (TO) != CIRRUS_REGS ? 20 : \ |
1454 | (FROM) != CIRRUS_REGS && (TO) == CIRRUS_REGS ? 20 : \ | |
1455 | 2) \ | |
d5b7b3ae RE |
1456 | : \ |
1457 | ((FROM) == HI_REGS || (TO) == HI_REGS) ? 4 : 2) | |
35d965d5 RS |
1458 | \f |
1459 | /* Stack layout; function entry, exit and calling. */ | |
1460 | ||
1461 | /* Define this if pushing a word on the stack | |
1462 | makes the stack pointer a smaller address. */ | |
1463 | #define STACK_GROWS_DOWNWARD 1 | |
1464 | ||
a4d05547 | 1465 | /* Define this to nonzero if the nominal address of the stack frame |
35d965d5 RS |
1466 | is at the high-address end of the local variables; |
1467 | that is, each additional local variable allocated | |
1468 | goes at a more negative offset in the frame. */ | |
1469 | #define FRAME_GROWS_DOWNWARD 1 | |
1470 | ||
a2503645 RS |
1471 | /* The amount of scratch space needed by _interwork_{r7,r11}_call_via_rN(). |
1472 | When present, it is one word in size, and sits at the top of the frame, | |
1473 | between the soft frame pointer and either r7 or r11. | |
1474 | ||
1475 | We only need _interwork_rM_call_via_rN() for -mcaller-super-interworking, | |
1476 | and only then if some outgoing arguments are passed on the stack. It would | |
1477 | be tempting to also check whether the stack arguments are passed by indirect | |
1478 | calls, but there seems to be no reason in principle why a post-reload pass | |
1479 | couldn't convert a direct call into an indirect one. */ | |
1480 | #define CALLER_INTERWORKING_SLOT_SIZE \ | |
1481 | (TARGET_CALLER_INTERWORKING \ | |
38173d38 | 1482 | && crtl->outgoing_args_size != 0 \ |
a2503645 RS |
1483 | ? UNITS_PER_WORD : 0) |
1484 | ||
35d965d5 RS |
1485 | /* Offset within stack frame to start allocating local variables at. |
1486 | If FRAME_GROWS_DOWNWARD, this is the offset to the END of the | |
1487 | first local allocated. Otherwise, it is the offset to the BEGINNING | |
1488 | of the first local allocated. */ | |
1489 | #define STARTING_FRAME_OFFSET 0 | |
1490 | ||
1491 | /* If we generate an insn to push BYTES bytes, | |
1492 | this says how many the stack pointer really advances by. */ | |
d5b7b3ae | 1493 | /* The push insns do not do this rounding implicitly. |
d6b4baa4 | 1494 | So don't define this. */ |
0c2ca901 | 1495 | /* #define PUSH_ROUNDING(NPUSHED) ROUND_UP_WORD (NPUSHED) */ |
18543a22 ILT |
1496 | |
1497 | /* Define this if the maximum size of all the outgoing args is to be | |
1498 | accumulated and pushed during the prologue. The amount can be | |
38173d38 | 1499 | found in the variable crtl->outgoing_args_size. */ |
6cfc7210 | 1500 | #define ACCUMULATE_OUTGOING_ARGS 1 |
35d965d5 RS |
1501 | |
1502 | /* Offset of first parameter from the argument pointer register value. */ | |
d5b7b3ae | 1503 | #define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0) |
35d965d5 RS |
1504 | |
1505 | /* Value is the number of byte of arguments automatically | |
1506 | popped when returning from a subroutine call. | |
8b109b37 | 1507 | FUNDECL is the declaration node of the function (as a tree), |
35d965d5 RS |
1508 | FUNTYPE is the data type of the function (as a tree), |
1509 | or for a library call it is an identifier node for the subroutine name. | |
1510 | SIZE is the number of bytes of arguments passed on the stack. | |
1511 | ||
1512 | On the ARM, the caller does not pop any of its arguments that were passed | |
1513 | on the stack. */ | |
6cfc7210 | 1514 | #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0 |
35d965d5 RS |
1515 | |
1516 | /* Define how to find the value returned by a library function | |
1517 | assuming the value has mode MODE. */ | |
390b17c2 RE |
1518 | #define LIBCALL_VALUE(MODE) \ |
1519 | (TARGET_AAPCS_BASED ? aapcs_libcall_value (MODE) \ | |
1520 | : (TARGET_32BIT && TARGET_HARD_FLOAT_ABI && TARGET_FPA \ | |
1521 | && GET_MODE_CLASS (MODE) == MODE_FLOAT) \ | |
9b66ebb1 | 1522 | ? gen_rtx_REG (MODE, FIRST_FPA_REGNUM) \ |
5b3e6663 | 1523 | : TARGET_32BIT && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK \ |
9b66ebb1 | 1524 | && GET_MODE_CLASS (MODE) == MODE_FLOAT \ |
9b6b54e2 | 1525 | ? gen_rtx_REG (MODE, FIRST_CIRRUS_FP_REGNUM) \ |
f676971a | 1526 | : TARGET_IWMMXT_ABI && arm_vector_mode_supported_p (MODE) \ |
5a9335ef | 1527 | ? gen_rtx_REG (MODE, FIRST_IWMMXT_REGNUM) \ |
d5b7b3ae | 1528 | : gen_rtx_REG (MODE, ARG_REGISTER (1))) |
35d965d5 | 1529 | |
390b17c2 RE |
1530 | /* 1 if REGNO is a possible register number for a function value. */ |
1531 | #define FUNCTION_VALUE_REGNO_P(REGNO) \ | |
1532 | ((REGNO) == ARG_REGISTER (1) \ | |
1533 | || (TARGET_AAPCS_BASED && TARGET_32BIT \ | |
1534 | && TARGET_VFP && TARGET_HARD_FLOAT \ | |
1535 | && (REGNO) == FIRST_VFP_REGNUM) \ | |
1536 | || (TARGET_32BIT && ((REGNO) == FIRST_CIRRUS_FP_REGNUM) \ | |
1537 | && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK) \ | |
1538 | || ((REGNO) == FIRST_IWMMXT_REGNUM && TARGET_IWMMXT_ABI) \ | |
1539 | || (TARGET_32BIT && ((REGNO) == FIRST_FPA_REGNUM) \ | |
72cdc543 | 1540 | && TARGET_HARD_FLOAT_ABI && TARGET_FPA)) |
35d965d5 | 1541 | |
9f7bf991 RE |
1542 | /* Amount of memory needed for an untyped call to save all possible return |
1543 | registers. */ | |
1544 | #define APPLY_RESULT_SIZE arm_apply_result_size() | |
1545 | ||
11c1a207 RE |
1546 | /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return |
1547 | values must be in memory. On the ARM, they need only do so if larger | |
d6b4baa4 | 1548 | than a word, or if they contain elements offset from zero in the struct. */ |
11c1a207 RE |
1549 | #define DEFAULT_PCC_STRUCT_RETURN 0 |
1550 | ||
6d3d9133 | 1551 | /* These bits describe the different types of function supported |
112cdef5 | 1552 | by the ARM backend. They are exclusive. i.e. a function cannot be both a |
6d3d9133 NC |
1553 | normal function and an interworked function, for example. Knowing the |
1554 | type of a function is important for determining its prologue and | |
1555 | epilogue sequences. | |
1556 | Note value 7 is currently unassigned. Also note that the interrupt | |
1557 | function types all have bit 2 set, so that they can be tested for easily. | |
1558 | Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the | |
4912a07c | 1559 | machine_function structure is initialized (to zero) func_type will |
6d3d9133 NC |
1560 | default to unknown. This will force the first use of arm_current_func_type |
1561 | to call arm_compute_func_type. */ | |
1562 | #define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */ | |
1563 | #define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */ | |
1564 | #define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */ | |
6d3d9133 NC |
1565 | #define ARM_FT_ISR 4 /* An interrupt service routine. */ |
1566 | #define ARM_FT_FIQ 5 /* A fast interrupt service routine. */ | |
1567 | #define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */ | |
1568 | ||
1569 | #define ARM_FT_TYPE_MASK ((1 << 3) - 1) | |
1570 | ||
1571 | /* In addition functions can have several type modifiers, | |
1572 | outlined by these bit masks: */ | |
1573 | #define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */ | |
1574 | #define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */ | |
1575 | #define ARM_FT_VOLATILE (1 << 4) /* Does not return. */ | |
d6b4baa4 | 1576 | #define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */ |
5b3e6663 | 1577 | #define ARM_FT_STACKALIGN (1 << 6) /* Called with misaligned stack. */ |
6d3d9133 NC |
1578 | |
1579 | /* Some macros to test these flags. */ | |
1580 | #define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK) | |
1581 | #define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT) | |
1582 | #define IS_VOLATILE(t) (t & ARM_FT_VOLATILE) | |
1583 | #define IS_NAKED(t) (t & ARM_FT_NAKED) | |
1584 | #define IS_NESTED(t) (t & ARM_FT_NESTED) | |
5b3e6663 | 1585 | #define IS_STACKALIGN(t) (t & ARM_FT_STACKALIGN) |
6d3d9133 | 1586 | |
5848830f PB |
1587 | |
1588 | /* Structure used to hold the function stack frame layout. Offsets are | |
1589 | relative to the stack pointer on function entry. Positive offsets are | |
1590 | in the direction of stack growth. | |
1591 | Only soft_frame is used in thumb mode. */ | |
1592 | ||
d1b38208 | 1593 | typedef struct GTY(()) arm_stack_offsets |
5848830f PB |
1594 | { |
1595 | int saved_args; /* ARG_POINTER_REGNUM. */ | |
1596 | int frame; /* ARM_HARD_FRAME_POINTER_REGNUM. */ | |
1597 | int saved_regs; | |
1598 | int soft_frame; /* FRAME_POINTER_REGNUM. */ | |
2591db65 | 1599 | int locals_base; /* THUMB_HARD_FRAME_POINTER_REGNUM. */ |
5848830f | 1600 | int outgoing_args; /* STACK_POINTER_REGNUM. */ |
954954d1 | 1601 | unsigned int saved_regs_mask; |
5848830f PB |
1602 | } |
1603 | arm_stack_offsets; | |
1604 | ||
6d3d9133 NC |
1605 | /* A C structure for machine-specific, per-function data. |
1606 | This is added to the cfun structure. */ | |
d1b38208 | 1607 | typedef struct GTY(()) machine_function |
d5b7b3ae | 1608 | { |
6bc82793 | 1609 | /* Additional stack adjustment in __builtin_eh_throw. */ |
e2500fed | 1610 | rtx eh_epilogue_sp_ofs; |
d5b7b3ae RE |
1611 | /* Records if LR has to be saved for far jumps. */ |
1612 | int far_jump_used; | |
1613 | /* Records if ARG_POINTER was ever live. */ | |
1614 | int arg_pointer_live; | |
6f7ebcbb NC |
1615 | /* Records if the save of LR has been eliminated. */ |
1616 | int lr_save_eliminated; | |
0977774b | 1617 | /* The size of the stack frame. Only valid after reload. */ |
5848830f | 1618 | arm_stack_offsets stack_offsets; |
6d3d9133 NC |
1619 | /* Records the type of the current function. */ |
1620 | unsigned long func_type; | |
3cb66fd7 NC |
1621 | /* Record if the function has a variable argument list. */ |
1622 | int uses_anonymous_args; | |
5a9335ef NC |
1623 | /* Records if sibcalls are blocked because an argument |
1624 | register is needed to preserve stack alignment. */ | |
1625 | int sibcall_blocked; | |
020a4035 RE |
1626 | /* The PIC register for this function. This might be a pseudo. */ |
1627 | rtx pic_reg; | |
b12a00f1 | 1628 | /* Labels for per-function Thumb call-via stubs. One per potential calling |
57ecec57 PB |
1629 | register. We can never call via LR or PC. We can call via SP if a |
1630 | trampoline happens to be on the top of the stack. */ | |
1631 | rtx call_via[14]; | |
934c2060 RR |
1632 | /* Set to 1 when a return insn is output, this means that the epilogue |
1633 | is not needed. */ | |
1634 | int return_used_this_function; | |
6d3d9133 NC |
1635 | } |
1636 | machine_function; | |
d5b7b3ae | 1637 | |
b12a00f1 | 1638 | /* As in the machine_function, a global set of call-via labels, for code |
d6b5193b | 1639 | that is in text_section. */ |
57ecec57 | 1640 | extern GTY(()) rtx thumb_call_via_label[14]; |
b12a00f1 | 1641 | |
390b17c2 RE |
1642 | /* The number of potential ways of assigning to a co-processor. */ |
1643 | #define ARM_NUM_COPROC_SLOTS 1 | |
1644 | ||
1645 | /* Enumeration of procedure calling standard variants. We don't really | |
1646 | support all of these yet. */ | |
1647 | enum arm_pcs | |
1648 | { | |
1649 | ARM_PCS_AAPCS, /* Base standard AAPCS. */ | |
1650 | ARM_PCS_AAPCS_VFP, /* Use VFP registers for floating point values. */ | |
1651 | ARM_PCS_AAPCS_IWMMXT, /* Use iWMMXT registers for vectors. */ | |
1652 | /* This must be the last AAPCS variant. */ | |
1653 | ARM_PCS_AAPCS_LOCAL, /* Private call within this compilation unit. */ | |
1654 | ARM_PCS_ATPCS, /* ATPCS. */ | |
1655 | ARM_PCS_APCS, /* APCS (legacy Linux etc). */ | |
1656 | ARM_PCS_UNKNOWN | |
1657 | }; | |
1658 | ||
82e9d970 | 1659 | /* A C type for declaring a variable that is used as the first argument of |
390b17c2 | 1660 | `FUNCTION_ARG' and other related values. */ |
82e9d970 PB |
1661 | typedef struct |
1662 | { | |
d5b7b3ae | 1663 | /* This is the number of registers of arguments scanned so far. */ |
82e9d970 | 1664 | int nregs; |
5a9335ef NC |
1665 | /* This is the number of iWMMXt register arguments scanned so far. */ |
1666 | int iwmmxt_nregs; | |
1667 | int named_count; | |
1668 | int nargs; | |
390b17c2 RE |
1669 | /* Which procedure call variant to use for this call. */ |
1670 | enum arm_pcs pcs_variant; | |
1671 | ||
1672 | /* AAPCS related state tracking. */ | |
1673 | int aapcs_arg_processed; /* No need to lay out this argument again. */ | |
1674 | int aapcs_cprc_slot; /* Index of co-processor rules to handle | |
1675 | this argument, or -1 if using core | |
1676 | registers. */ | |
1677 | int aapcs_ncrn; | |
1678 | int aapcs_next_ncrn; | |
1679 | rtx aapcs_reg; /* Register assigned to this argument. */ | |
1680 | int aapcs_partial; /* How many bytes are passed in regs (if | |
1681 | split between core regs and stack. | |
1682 | Zero otherwise. */ | |
1683 | int aapcs_cprc_failed[ARM_NUM_COPROC_SLOTS]; | |
1684 | int can_split; /* Argument can be split between core regs | |
1685 | and the stack. */ | |
1686 | /* Private data for tracking VFP register allocation */ | |
1687 | unsigned aapcs_vfp_regs_free; | |
1688 | unsigned aapcs_vfp_reg_alloc; | |
1689 | int aapcs_vfp_rcount; | |
46107b99 | 1690 | MACHMODE aapcs_vfp_rmode; |
d5b7b3ae | 1691 | } CUMULATIVE_ARGS; |
82e9d970 | 1692 | |
35d965d5 RS |
1693 | /* Define where to put the arguments to a function. |
1694 | Value is zero to push the argument on the stack, | |
1695 | or a hard register in which to store the argument. | |
1696 | ||
1697 | MODE is the argument's machine mode. | |
1698 | TYPE is the data type of the argument (as a tree). | |
1699 | This is null for libcalls where that information may | |
1700 | not be available. | |
1701 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
1702 | the preceding args and about the function being called. | |
1703 | NAMED is nonzero if this argument is a named parameter | |
1704 | (otherwise it is an extra parameter matching an ellipsis). | |
1705 | ||
1706 | On the ARM, normally the first 16 bytes are passed in registers r0-r3; all | |
1707 | other arguments are passed on the stack. If (NAMED == 0) (which happens | |
1cc9f5f5 KH |
1708 | only in assign_parms, since TARGET_SETUP_INCOMING_VARARGS is |
1709 | defined), say it is passed in the stack (function_prologue will | |
1710 | indeed make it pass in the stack if necessary). */ | |
82e9d970 PB |
1711 | #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ |
1712 | arm_function_arg (&(CUM), (MODE), (TYPE), (NAMED)) | |
35d965d5 | 1713 | |
866af8a9 JB |
1714 | #define FUNCTION_ARG_PADDING(MODE, TYPE) \ |
1715 | (arm_pad_arg_upward (MODE, TYPE) ? upward : downward) | |
1716 | ||
1717 | #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \ | |
1718 | (arm_pad_reg_upward (MODE, TYPE, FIRST) ? upward : downward) | |
1719 | ||
1720 | /* For AAPCS, padding should never be below the argument. For other ABIs, | |
1721 | * mimic the default. */ | |
1722 | #define PAD_VARARGS_DOWN \ | |
1723 | ((TARGET_AAPCS_BASED) ? 0 : BYTES_BIG_ENDIAN) | |
1724 | ||
35d965d5 RS |
1725 | /* Initialize a variable CUM of type CUMULATIVE_ARGS |
1726 | for a call to a function whose data type is FNTYPE. | |
1727 | For a library call, FNTYPE is 0. | |
1728 | On the ARM, the offset starts at 0. */ | |
0f6937fe | 1729 | #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ |
563a317a | 1730 | arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL)) |
35d965d5 RS |
1731 | |
1732 | /* Update the data in CUM to advance over an argument | |
1733 | of mode MODE and data type TYPE. | |
1734 | (TYPE is null for libcalls where that information may not be available.) */ | |
6cfc7210 | 1735 | #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ |
390b17c2 | 1736 | arm_function_arg_advance (&(CUM), (MODE), (TYPE), (NAMED)) |
35d965d5 | 1737 | |
5a9335ef NC |
1738 | /* If defined, a C expression that gives the alignment boundary, in bits, of an |
1739 | argument with the specified mode and type. If it is not defined, | |
1740 | `PARM_BOUNDARY' is used for all arguments. */ | |
1741 | #define FUNCTION_ARG_BOUNDARY(MODE,TYPE) \ | |
5848830f PB |
1742 | ((ARM_DOUBLEWORD_ALIGN && arm_needs_doubleword_align (MODE, TYPE)) \ |
1743 | ? DOUBLEWORD_ALIGNMENT \ | |
1744 | : PARM_BOUNDARY ) | |
5a9335ef | 1745 | |
35d965d5 RS |
1746 | /* 1 if N is a possible register number for function argument passing. |
1747 | On the ARM, r0-r3 are used to pass args. */ | |
390b17c2 RE |
1748 | #define FUNCTION_ARG_REGNO_P(REGNO) \ |
1749 | (IN_RANGE ((REGNO), 0, 3) \ | |
1750 | || (TARGET_AAPCS_BASED && TARGET_VFP && TARGET_HARD_FLOAT \ | |
1751 | && IN_RANGE ((REGNO), FIRST_VFP_REGNUM, FIRST_VFP_REGNUM + 15)) \ | |
1752 | || (TARGET_IWMMXT_ABI \ | |
5848830f | 1753 | && IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9))) |
35d965d5 | 1754 | |
f99fce0c | 1755 | \f |
afef3d7a | 1756 | /* If your target environment doesn't prefix user functions with an |
96a3900d | 1757 | underscore, you may wish to re-define this to prevent any conflicts. */ |
afef3d7a NC |
1758 | #ifndef ARM_MCOUNT_NAME |
1759 | #define ARM_MCOUNT_NAME "*mcount" | |
1760 | #endif | |
1761 | ||
1762 | /* Call the function profiler with a given profile label. The Acorn | |
1763 | compiler puts this BEFORE the prolog but gcc puts it afterwards. | |
1764 | On the ARM the full profile code will look like: | |
1765 | .data | |
1766 | LP1 | |
1767 | .word 0 | |
1768 | .text | |
1769 | mov ip, lr | |
1770 | bl mcount | |
1771 | .word LP1 | |
1772 | ||
1773 | profile_function() in final.c outputs the .data section, FUNCTION_PROFILER | |
1774 | will output the .text section. | |
1775 | ||
1776 | The ``mov ip,lr'' seems like a good idea to stick with cc convention. | |
59be6073 AN |
1777 | ``prof'' doesn't seem to mind about this! |
1778 | ||
1779 | Note - this version of the code is designed to work in both ARM and | |
1780 | Thumb modes. */ | |
be393ecf | 1781 | #ifndef ARM_FUNCTION_PROFILER |
d5b7b3ae | 1782 | #define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \ |
6cfc7210 NC |
1783 | { \ |
1784 | char temp[20]; \ | |
1785 | rtx sym; \ | |
1786 | \ | |
dd18ae56 | 1787 | asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \ |
d5b7b3ae | 1788 | IP_REGNUM, LR_REGNUM); \ |
6cfc7210 NC |
1789 | assemble_name (STREAM, ARM_MCOUNT_NAME); \ |
1790 | fputc ('\n', STREAM); \ | |
1791 | ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \ | |
f1c25d3b | 1792 | sym = gen_rtx_SYMBOL_REF (Pmode, temp); \ |
301d03af | 1793 | assemble_aligned_integer (UNITS_PER_WORD, sym); \ |
35d965d5 | 1794 | } |
be393ecf | 1795 | #endif |
35d965d5 | 1796 | |
59be6073 | 1797 | #ifdef THUMB_FUNCTION_PROFILER |
d5b7b3ae RE |
1798 | #define FUNCTION_PROFILER(STREAM, LABELNO) \ |
1799 | if (TARGET_ARM) \ | |
1800 | ARM_FUNCTION_PROFILER (STREAM, LABELNO) \ | |
1801 | else \ | |
1802 | THUMB_FUNCTION_PROFILER (STREAM, LABELNO) | |
59be6073 AN |
1803 | #else |
1804 | #define FUNCTION_PROFILER(STREAM, LABELNO) \ | |
1805 | ARM_FUNCTION_PROFILER (STREAM, LABELNO) | |
1806 | #endif | |
d5b7b3ae | 1807 | |
35d965d5 RS |
1808 | /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, |
1809 | the stack pointer does not matter. The value is tested only in | |
1810 | functions that have frame pointers. | |
1811 | No definition is equivalent to always zero. | |
1812 | ||
1813 | On the ARM, the function epilogue recovers the stack pointer from the | |
1814 | frame. */ | |
1815 | #define EXIT_IGNORE_STACK 1 | |
1816 | ||
6fb5fa3c | 1817 | #define EPILOGUE_USES(REGNO) ((REGNO) == LR_REGNUM) |
c7861455 | 1818 | |
35d965d5 RS |
1819 | /* Determine if the epilogue should be output as RTL. |
1820 | You should override this if you define FUNCTION_EXTRA_EPILOGUE. */ | |
5b3e6663 PB |
1821 | /* This is disabled for Thumb-2 because it will confuse the |
1822 | conditional insn counter. */ | |
d5b7b3ae | 1823 | #define USE_RETURN_INSN(ISCOND) \ |
a72d4945 | 1824 | (TARGET_ARM ? use_return_insn (ISCOND, NULL) : 0) |
ff9940b0 RE |
1825 | |
1826 | /* Definitions for register eliminations. | |
1827 | ||
1828 | This is an array of structures. Each structure initializes one pair | |
1829 | of eliminable registers. The "from" register number is given first, | |
1830 | followed by "to". Eliminations of the same "from" register are listed | |
1831 | in order of preference. | |
1832 | ||
1833 | We have two registers that can be eliminated on the ARM. First, the | |
1834 | arg pointer register can often be eliminated in favor of the stack | |
1835 | pointer register. Secondly, the pseudo frame pointer register can always | |
1836 | be eliminated; it is replaced with either the stack or the real frame | |
d5b7b3ae | 1837 | pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM |
d6a7951f | 1838 | because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */ |
ff9940b0 | 1839 | |
d5b7b3ae RE |
1840 | #define ELIMINABLE_REGS \ |
1841 | {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\ | |
1842 | { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\ | |
1843 | { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\ | |
1844 | { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\ | |
1845 | { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\ | |
1846 | { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\ | |
1847 | { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }} | |
ff9940b0 | 1848 | |
d5b7b3ae RE |
1849 | /* Define the offset between two registers, one to be eliminated, and the |
1850 | other its replacement, at the start of a routine. */ | |
d5b7b3ae RE |
1851 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ |
1852 | if (TARGET_ARM) \ | |
5848830f | 1853 | (OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \ |
d5b7b3ae | 1854 | else \ |
5848830f PB |
1855 | (OFFSET) = thumb_compute_initial_elimination_offset (FROM, TO) |
1856 | ||
d5b7b3ae RE |
1857 | /* Special case handling of the location of arguments passed on the stack. */ |
1858 | #define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr) | |
f676971a | 1859 | |
d5b7b3ae RE |
1860 | /* Initialize data used by insn expanders. This is called from insn_emit, |
1861 | once for every function before code is generated. */ | |
1862 | #define INIT_EXPANDERS arm_init_expanders () | |
1863 | ||
35d965d5 | 1864 | /* Length in units of the trampoline for entering a nested function. */ |
5b3e6663 | 1865 | #define TRAMPOLINE_SIZE (TARGET_32BIT ? 16 : 20) |
35d965d5 | 1866 | |
006946e4 JM |
1867 | /* Alignment required for a trampoline in bits. */ |
1868 | #define TRAMPOLINE_ALIGNMENT 32 | |
35d965d5 RS |
1869 | \f |
1870 | /* Addressing modes, and classification of registers for them. */ | |
3cd45774 | 1871 | #define HAVE_POST_INCREMENT 1 |
5b3e6663 PB |
1872 | #define HAVE_PRE_INCREMENT TARGET_32BIT |
1873 | #define HAVE_POST_DECREMENT TARGET_32BIT | |
1874 | #define HAVE_PRE_DECREMENT TARGET_32BIT | |
1875 | #define HAVE_PRE_MODIFY_DISP TARGET_32BIT | |
1876 | #define HAVE_POST_MODIFY_DISP TARGET_32BIT | |
1877 | #define HAVE_PRE_MODIFY_REG TARGET_32BIT | |
1878 | #define HAVE_POST_MODIFY_REG TARGET_32BIT | |
35d965d5 RS |
1879 | |
1880 | /* Macros to check register numbers against specific register classes. */ | |
1881 | ||
1882 | /* These assume that REGNO is a hard or pseudo reg number. | |
1883 | They give nonzero only if REGNO is a hard reg of the suitable class | |
1884 | or a pseudo reg currently allocated to a suitable hard reg. | |
1885 | Since they use reg_renumber, they are safe only once reg_renumber | |
d6b4baa4 | 1886 | has been allocated, which happens in local-alloc.c. */ |
d5b7b3ae RE |
1887 | #define TEST_REGNO(R, TEST, VALUE) \ |
1888 | ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE)) | |
1889 | ||
5b3e6663 | 1890 | /* Don't allow the pc to be used. */ |
f1008e52 RE |
1891 | #define ARM_REGNO_OK_FOR_BASE_P(REGNO) \ |
1892 | (TEST_REGNO (REGNO, <, PC_REGNUM) \ | |
1893 | || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \ | |
1894 | || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM)) | |
1895 | ||
5b3e6663 | 1896 | #define THUMB1_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \ |
f1008e52 RE |
1897 | (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \ |
1898 | || (GET_MODE_SIZE (MODE) >= 4 \ | |
1899 | && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM))) | |
1900 | ||
1901 | #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \ | |
5b3e6663 PB |
1902 | (TARGET_THUMB1 \ |
1903 | ? THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \ | |
f1008e52 RE |
1904 | : ARM_REGNO_OK_FOR_BASE_P (REGNO)) |
1905 | ||
888d2cd6 DJ |
1906 | /* Nonzero if X can be the base register in a reg+reg addressing mode. |
1907 | For Thumb, we can not use SP + reg, so reject SP. */ | |
1908 | #define REGNO_MODE_OK_FOR_REG_BASE_P(X, MODE) \ | |
f5c630c3 | 1909 | REGNO_MODE_OK_FOR_BASE_P (X, QImode) |
888d2cd6 | 1910 | |
f1008e52 RE |
1911 | /* For ARM code, we don't care about the mode, but for Thumb, the index |
1912 | must be suitable for use in a QImode load. */ | |
d5b7b3ae | 1913 | #define REGNO_OK_FOR_INDEX_P(REGNO) \ |
f5c630c3 PB |
1914 | (REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode) \ |
1915 | && !TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)) | |
35d965d5 RS |
1916 | |
1917 | /* Maximum number of registers that can appear in a valid memory address. | |
d6b4baa4 | 1918 | Shifts in addresses can't be by a register. */ |
ff9940b0 | 1919 | #define MAX_REGS_PER_ADDRESS 2 |
35d965d5 RS |
1920 | |
1921 | /* Recognize any constant value that is a valid address. */ | |
1922 | /* XXX We can address any constant, eventually... */ | |
5b3e6663 | 1923 | /* ??? Should the TARGET_ARM here also apply to thumb2? */ |
008cf58a RE |
1924 | #define CONSTANT_ADDRESS_P(X) \ |
1925 | (GET_CODE (X) == SYMBOL_REF \ | |
1926 | && (CONSTANT_POOL_ADDRESS_P (X) \ | |
d5b7b3ae | 1927 | || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X)))) |
35d965d5 | 1928 | |
8426b956 RS |
1929 | /* True if SYMBOL + OFFSET constants must refer to something within |
1930 | SYMBOL's section. */ | |
1931 | #define ARM_OFFSETS_MUST_BE_WITHIN_SECTIONS_P 0 | |
1932 | ||
571191af PB |
1933 | /* Nonzero if all target requires all absolute relocations be R_ARM_ABS32. */ |
1934 | #ifndef TARGET_DEFAULT_WORD_RELOCATIONS | |
1935 | #define TARGET_DEFAULT_WORD_RELOCATIONS 0 | |
1936 | #endif | |
1937 | ||
35d965d5 RS |
1938 | /* Nonzero if the constant value X is a legitimate general operand. |
1939 | It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. | |
1940 | ||
1941 | On the ARM, allow any integer (invalid ones are removed later by insn | |
1942 | patterns), nice doubles and symbol_refs which refer to the function's | |
d5b7b3ae | 1943 | constant pool XXX. |
f676971a | 1944 | |
82e9d970 | 1945 | When generating pic allow anything. */ |
d5b7b3ae RE |
1946 | #define ARM_LEGITIMATE_CONSTANT_P(X) (flag_pic || ! label_mentioned_p (X)) |
1947 | ||
1948 | #define THUMB_LEGITIMATE_CONSTANT_P(X) \ | |
1949 | ( GET_CODE (X) == CONST_INT \ | |
1950 | || GET_CODE (X) == CONST_DOUBLE \ | |
7b8781c8 PB |
1951 | || CONSTANT_ADDRESS_P (X) \ |
1952 | || flag_pic) | |
d5b7b3ae | 1953 | |
d3585b76 | 1954 | #define LEGITIMATE_CONSTANT_P(X) \ |
8426b956 | 1955 | (!arm_cannot_force_const_mem (X) \ |
5b3e6663 PB |
1956 | && (TARGET_32BIT ? ARM_LEGITIMATE_CONSTANT_P (X) \ |
1957 | : THUMB_LEGITIMATE_CONSTANT_P (X))) | |
d5b7b3ae | 1958 | |
c27ba912 DM |
1959 | #ifndef SUBTARGET_NAME_ENCODING_LENGTHS |
1960 | #define SUBTARGET_NAME_ENCODING_LENGTHS | |
1961 | #endif | |
1962 | ||
6bc82793 | 1963 | /* This is a C fragment for the inside of a switch statement. |
c27ba912 DM |
1964 | Each case label should return the number of characters to |
1965 | be stripped from the start of a function's name, if that | |
1966 | name starts with the indicated character. */ | |
1967 | #define ARM_NAME_ENCODING_LENGTHS \ | |
00fdafef | 1968 | case '*': return 1; \ |
f676971a | 1969 | SUBTARGET_NAME_ENCODING_LENGTHS |
c27ba912 | 1970 | |
c27ba912 DM |
1971 | /* This is how to output a reference to a user-level label named NAME. |
1972 | `assemble_name' uses this. */ | |
e5951263 | 1973 | #undef ASM_OUTPUT_LABELREF |
c27ba912 | 1974 | #define ASM_OUTPUT_LABELREF(FILE, NAME) \ |
e1944073 | 1975 | arm_asm_output_labelref (FILE, NAME) |
c27ba912 | 1976 | |
7a085dce | 1977 | /* Output IT instructions for conditionally executed Thumb-2 instructions. */ |
5b3e6663 PB |
1978 | #define ASM_OUTPUT_OPCODE(STREAM, PTR) \ |
1979 | if (TARGET_THUMB2) \ | |
1980 | thumb2_asm_output_opcode (STREAM); | |
1981 | ||
7abc66b1 JB |
1982 | /* The EABI specifies that constructors should go in .init_array. |
1983 | Other targets use .ctors for compatibility. */ | |
88c6057f | 1984 | #ifndef ARM_EABI_CTORS_SECTION_OP |
7abc66b1 JB |
1985 | #define ARM_EABI_CTORS_SECTION_OP \ |
1986 | "\t.section\t.init_array,\"aw\",%init_array" | |
88c6057f MM |
1987 | #endif |
1988 | #ifndef ARM_EABI_DTORS_SECTION_OP | |
7abc66b1 JB |
1989 | #define ARM_EABI_DTORS_SECTION_OP \ |
1990 | "\t.section\t.fini_array,\"aw\",%fini_array" | |
88c6057f | 1991 | #endif |
7abc66b1 JB |
1992 | #define ARM_CTORS_SECTION_OP \ |
1993 | "\t.section\t.ctors,\"aw\",%progbits" | |
1994 | #define ARM_DTORS_SECTION_OP \ | |
1995 | "\t.section\t.dtors,\"aw\",%progbits" | |
1996 | ||
1997 | /* Define CTORS_SECTION_ASM_OP. */ | |
1998 | #undef CTORS_SECTION_ASM_OP | |
1999 | #undef DTORS_SECTION_ASM_OP | |
2000 | #ifndef IN_LIBGCC2 | |
2001 | # define CTORS_SECTION_ASM_OP \ | |
2002 | (TARGET_AAPCS_BASED ? ARM_EABI_CTORS_SECTION_OP : ARM_CTORS_SECTION_OP) | |
2003 | # define DTORS_SECTION_ASM_OP \ | |
2004 | (TARGET_AAPCS_BASED ? ARM_EABI_DTORS_SECTION_OP : ARM_DTORS_SECTION_OP) | |
2005 | #else /* !defined (IN_LIBGCC2) */ | |
2006 | /* In libgcc, CTORS_SECTION_ASM_OP must be a compile-time constant, | |
2007 | so we cannot use the definition above. */ | |
2008 | # ifdef __ARM_EABI__ | |
2009 | /* The .ctors section is not part of the EABI, so we do not define | |
2010 | CTORS_SECTION_ASM_OP when in libgcc; that prevents crtstuff | |
2011 | from trying to use it. We do define it when doing normal | |
2012 | compilation, as .init_array can be used instead of .ctors. */ | |
2013 | /* There is no need to emit begin or end markers when using | |
2014 | init_array; the dynamic linker will compute the size of the | |
2015 | array itself based on special symbols created by the static | |
2016 | linker. However, we do need to arrange to set up | |
2017 | exception-handling here. */ | |
2018 | # define CTOR_LIST_BEGIN asm (ARM_EABI_CTORS_SECTION_OP) | |
2019 | # define CTOR_LIST_END /* empty */ | |
2020 | # define DTOR_LIST_BEGIN asm (ARM_EABI_DTORS_SECTION_OP) | |
2021 | # define DTOR_LIST_END /* empty */ | |
2022 | # else /* !defined (__ARM_EABI__) */ | |
2023 | # define CTORS_SECTION_ASM_OP ARM_CTORS_SECTION_OP | |
2024 | # define DTORS_SECTION_ASM_OP ARM_DTORS_SECTION_OP | |
2025 | # endif /* !defined (__ARM_EABI__) */ | |
2026 | #endif /* !defined (IN_LIBCC2) */ | |
2027 | ||
1e731102 MM |
2028 | /* True if the operating system can merge entities with vague linkage |
2029 | (e.g., symbols in COMDAT group) during dynamic linking. */ | |
2030 | #ifndef TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P | |
2031 | #define TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P true | |
2032 | #endif | |
2033 | ||
617a1b71 PB |
2034 | #define ARM_OUTPUT_FN_UNWIND(F, PROLOGUE) arm_output_fn_unwind (F, PROLOGUE) |
2035 | ||
2036 | #ifdef TARGET_UNWIND_INFO | |
2037 | #define ARM_EABI_UNWIND_TABLES \ | |
2038 | ((!USING_SJLJ_EXCEPTIONS && flag_exceptions) || flag_unwind_tables) | |
2039 | #else | |
2040 | #define ARM_EABI_UNWIND_TABLES 0 | |
2041 | #endif | |
2042 | ||
35d965d5 RS |
2043 | /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx |
2044 | and check its validity for a certain class. | |
2045 | We have two alternate definitions for each of them. | |
2046 | The usual definition accepts all pseudo regs; the other rejects | |
2047 | them unless they have been allocated suitable hard regs. | |
5b3e6663 | 2048 | The symbol REG_OK_STRICT causes the latter definition to be used. |
7a085dce | 2049 | Thumb-2 has the same restrictions as arm. */ |
35d965d5 | 2050 | #ifndef REG_OK_STRICT |
ff9940b0 | 2051 | |
f1008e52 RE |
2052 | #define ARM_REG_OK_FOR_BASE_P(X) \ |
2053 | (REGNO (X) <= LAST_ARM_REGNUM \ | |
2054 | || REGNO (X) >= FIRST_PSEUDO_REGISTER \ | |
2055 | || REGNO (X) == FRAME_POINTER_REGNUM \ | |
2056 | || REGNO (X) == ARG_POINTER_REGNUM) | |
ff9940b0 | 2057 | |
f5c630c3 PB |
2058 | #define ARM_REG_OK_FOR_INDEX_P(X) \ |
2059 | ((REGNO (X) <= LAST_ARM_REGNUM \ | |
2060 | && REGNO (X) != STACK_POINTER_REGNUM) \ | |
2061 | || REGNO (X) >= FIRST_PSEUDO_REGISTER \ | |
2062 | || REGNO (X) == FRAME_POINTER_REGNUM \ | |
2063 | || REGNO (X) == ARG_POINTER_REGNUM) | |
2064 | ||
5b3e6663 | 2065 | #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \ |
f1008e52 RE |
2066 | (REGNO (X) <= LAST_LO_REGNUM \ |
2067 | || REGNO (X) >= FIRST_PSEUDO_REGISTER \ | |
2068 | || (GET_MODE_SIZE (MODE) >= 4 \ | |
2069 | && (REGNO (X) == STACK_POINTER_REGNUM \ | |
2070 | || (X) == hard_frame_pointer_rtx \ | |
2071 | || (X) == arg_pointer_rtx))) | |
ff9940b0 | 2072 | |
76a318e9 RE |
2073 | #define REG_STRICT_P 0 |
2074 | ||
d5b7b3ae | 2075 | #else /* REG_OK_STRICT */ |
ff9940b0 | 2076 | |
f1008e52 RE |
2077 | #define ARM_REG_OK_FOR_BASE_P(X) \ |
2078 | ARM_REGNO_OK_FOR_BASE_P (REGNO (X)) | |
ff9940b0 | 2079 | |
f5c630c3 PB |
2080 | #define ARM_REG_OK_FOR_INDEX_P(X) \ |
2081 | ARM_REGNO_OK_FOR_INDEX_P (REGNO (X)) | |
2082 | ||
5b3e6663 PB |
2083 | #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \ |
2084 | THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE) | |
ff9940b0 | 2085 | |
76a318e9 RE |
2086 | #define REG_STRICT_P 1 |
2087 | ||
d5b7b3ae | 2088 | #endif /* REG_OK_STRICT */ |
f1008e52 RE |
2089 | |
2090 | /* Now define some helpers in terms of the above. */ | |
2091 | ||
2092 | #define REG_MODE_OK_FOR_BASE_P(X, MODE) \ | |
5b3e6663 PB |
2093 | (TARGET_THUMB1 \ |
2094 | ? THUMB1_REG_MODE_OK_FOR_BASE_P (X, MODE) \ | |
f1008e52 RE |
2095 | : ARM_REG_OK_FOR_BASE_P (X)) |
2096 | ||
5b3e6663 | 2097 | /* For 16-bit Thumb, a valid index register is anything that can be used in |
f1008e52 | 2098 | a byte load instruction. */ |
5b3e6663 PB |
2099 | #define THUMB1_REG_OK_FOR_INDEX_P(X) \ |
2100 | THUMB1_REG_MODE_OK_FOR_BASE_P (X, QImode) | |
f1008e52 RE |
2101 | |
2102 | /* Nonzero if X is a hard reg that can be used as an index | |
2103 | or if it is a pseudo reg. On the Thumb, the stack pointer | |
2104 | is not suitable. */ | |
2105 | #define REG_OK_FOR_INDEX_P(X) \ | |
5b3e6663 PB |
2106 | (TARGET_THUMB1 \ |
2107 | ? THUMB1_REG_OK_FOR_INDEX_P (X) \ | |
f1008e52 RE |
2108 | : ARM_REG_OK_FOR_INDEX_P (X)) |
2109 | ||
888d2cd6 DJ |
2110 | /* Nonzero if X can be the base register in a reg+reg addressing mode. |
2111 | For Thumb, we can not use SP + reg, so reject SP. */ | |
2112 | #define REG_MODE_OK_FOR_REG_BASE_P(X, MODE) \ | |
2113 | REG_OK_FOR_INDEX_P (X) | |
35d965d5 | 2114 | \f |
f1008e52 RE |
2115 | #define ARM_BASE_REGISTER_RTX_P(X) \ |
2116 | (GET_CODE (X) == REG && ARM_REG_OK_FOR_BASE_P (X)) | |
35d965d5 | 2117 | |
f1008e52 RE |
2118 | #define ARM_INDEX_REGISTER_RTX_P(X) \ |
2119 | (GET_CODE (X) == REG && ARM_REG_OK_FOR_INDEX_P (X)) | |
35d965d5 | 2120 | \f |
360032ba JY |
2121 | /* Define this for compatibility reasons. */ |
2122 | #define HANDLE_PRAGMA_PACK_PUSH_POP | |
d5b7b3ae | 2123 | |
35d965d5 RS |
2124 | /* Specify the machine mode that this machine uses |
2125 | for the index in the tablejump instruction. */ | |
d5b7b3ae | 2126 | #define CASE_VECTOR_MODE Pmode |
35d965d5 | 2127 | |
907dd0c7 RE |
2128 | #define CASE_VECTOR_PC_RELATIVE (TARGET_THUMB2 \ |
2129 | || (TARGET_THUMB \ | |
2130 | && (optimize_size || flag_pic))) | |
2131 | ||
2132 | #define CASE_VECTOR_SHORTEN_MODE(min, max, body) \ | |
2133 | (TARGET_THUMB \ | |
2134 | ? (min >= 0 && max < 512 \ | |
2135 | ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 1, QImode) \ | |
2136 | : min >= -256 && max < 256 \ | |
2137 | ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, QImode) \ | |
2138 | : min >= 0 && max < 8192 \ | |
2139 | ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 1, HImode) \ | |
2140 | : min >= -4096 && max < 4096 \ | |
2141 | ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, HImode) \ | |
2142 | : SImode) \ | |
2143 | : ((min < 0 || max >= 0x2000 || !TARGET_THUMB2) ? SImode \ | |
2144 | : (max >= 0x200) ? HImode \ | |
2145 | : QImode)) | |
5b3e6663 | 2146 | |
ff9940b0 RE |
2147 | /* signed 'char' is most compatible, but RISC OS wants it unsigned. |
2148 | unsigned is probably best, but may break some code. */ | |
2149 | #ifndef DEFAULT_SIGNED_CHAR | |
3967692c | 2150 | #define DEFAULT_SIGNED_CHAR 0 |
35d965d5 RS |
2151 | #endif |
2152 | ||
35d965d5 | 2153 | /* Max number of bytes we can move from memory to memory |
d17ce9af TG |
2154 | in one reasonably fast instruction. */ |
2155 | #define MOVE_MAX 4 | |
35d965d5 | 2156 | |
d19fb8e3 | 2157 | #undef MOVE_RATIO |
e04ad03d | 2158 | #define MOVE_RATIO(speed) (arm_tune_xscale ? 4 : 2) |
d19fb8e3 | 2159 | |
ff9940b0 RE |
2160 | /* Define if operations between registers always perform the operation |
2161 | on the full register even if a narrower mode is specified. */ | |
2162 | #define WORD_REGISTER_OPERATIONS | |
2163 | ||
2164 | /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD | |
2165 | will either zero-extend or sign-extend. The value of this macro should | |
2166 | be the code that says which one of the two operations is implicitly | |
f822d252 | 2167 | done, UNKNOWN if none. */ |
9c872872 | 2168 | #define LOAD_EXTEND_OP(MODE) \ |
d5b7b3ae RE |
2169 | (TARGET_THUMB ? ZERO_EXTEND : \ |
2170 | ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \ | |
f822d252 | 2171 | : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : UNKNOWN))) |
ff9940b0 | 2172 | |
35d965d5 RS |
2173 | /* Nonzero if access to memory by bytes is slow and undesirable. */ |
2174 | #define SLOW_BYTE_ACCESS 0 | |
2175 | ||
d5b7b3ae | 2176 | #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1 |
f676971a | 2177 | |
35d965d5 RS |
2178 | /* Immediate shift counts are truncated by the output routines (or was it |
2179 | the assembler?). Shift counts in a register are truncated by ARM. Note | |
2180 | that the native compiler puts too large (> 32) immediate shift counts | |
2181 | into a register and shifts by the register, letting the ARM decide what | |
2182 | to do instead of doing that itself. */ | |
ff9940b0 RE |
2183 | /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that |
2184 | code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y). | |
2185 | On the arm, Y in a register is used modulo 256 for the shift. Only for | |
d6b4baa4 | 2186 | rotates is modulo 32 used. */ |
ff9940b0 | 2187 | /* #define SHIFT_COUNT_TRUNCATED 1 */ |
35d965d5 | 2188 | |
35d965d5 | 2189 | /* All integers have the same format so truncation is easy. */ |
d5b7b3ae | 2190 | #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 |
35d965d5 RS |
2191 | |
2192 | /* Calling from registers is a massive pain. */ | |
2193 | #define NO_FUNCTION_CSE 1 | |
2194 | ||
35d965d5 RS |
2195 | /* The machine modes of pointers and functions */ |
2196 | #define Pmode SImode | |
2197 | #define FUNCTION_MODE Pmode | |
2198 | ||
d5b7b3ae RE |
2199 | #define ARM_FRAME_RTX(X) \ |
2200 | ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \ | |
3967692c RE |
2201 | || (X) == arg_pointer_rtx) |
2202 | ||
ff9940b0 | 2203 | /* Moves to and from memory are quite expensive */ |
d5b7b3ae | 2204 | #define MEMORY_MOVE_COST(M, CLASS, IN) \ |
5b3e6663 | 2205 | (TARGET_32BIT ? 10 : \ |
d5b7b3ae RE |
2206 | ((GET_MODE_SIZE (M) < 4 ? 8 : 2 * GET_MODE_SIZE (M)) \ |
2207 | * (CLASS == LO_REGS ? 1 : 2))) | |
f676971a | 2208 | |
ff9940b0 RE |
2209 | /* Try to generate sequences that don't involve branches, we can then use |
2210 | conditional instructions */ | |
3a4fd356 | 2211 | #define BRANCH_COST(speed_p, predictable_p) \ |
5b3e6663 | 2212 | (TARGET_32BIT ? 4 : (optimize > 0 ? 2 : 0)) |
7a801826 RE |
2213 | \f |
2214 | /* Position Independent Code. */ | |
2215 | /* We decide which register to use based on the compilation options and | |
2216 | the assembler in use; this is more general than the APCS restriction of | |
2217 | using sb (r9) all the time. */ | |
020a4035 | 2218 | extern unsigned arm_pic_register; |
7a801826 RE |
2219 | |
2220 | /* The register number of the register used to address a table of static | |
2221 | data addresses in memory. */ | |
2222 | #define PIC_OFFSET_TABLE_REGNUM arm_pic_register | |
2223 | ||
f5a1b0d2 | 2224 | /* We can't directly access anything that contains a symbol, |
d3585b76 DJ |
2225 | nor can we indirect via the constant pool. One exception is |
2226 | UNSPEC_TLS, which is always PIC. */ | |
82e9d970 | 2227 | #define LEGITIMATE_PIC_OPERAND_P(X) \ |
1575c31e JD |
2228 | (!(symbol_mentioned_p (X) \ |
2229 | || label_mentioned_p (X) \ | |
2230 | || (GET_CODE (X) == SYMBOL_REF \ | |
2231 | && CONSTANT_POOL_ADDRESS_P (X) \ | |
2232 | && (symbol_mentioned_p (get_pool_constant (X)) \ | |
d3585b76 DJ |
2233 | || label_mentioned_p (get_pool_constant (X))))) \ |
2234 | || tls_mentioned_p (X)) | |
1575c31e | 2235 | |
13bd191d PB |
2236 | /* We need to know when we are making a constant pool; this determines |
2237 | whether data needs to be in the GOT or can be referenced via a GOT | |
2238 | offset. */ | |
2239 | extern int making_const_table; | |
82e9d970 | 2240 | \f |
c27ba912 | 2241 | /* Handle pragmas for compatibility with Intel's compilers. */ |
b76c3c4b | 2242 | /* Also abuse this to register additional C specific EABI attributes. */ |
c58b209a NB |
2243 | #define REGISTER_TARGET_PRAGMAS() do { \ |
2244 | c_register_pragma (0, "long_calls", arm_pr_long_calls); \ | |
2245 | c_register_pragma (0, "no_long_calls", arm_pr_no_long_calls); \ | |
2246 | c_register_pragma (0, "long_calls_off", arm_pr_long_calls_off); \ | |
b76c3c4b | 2247 | arm_lang_object_attributes_init(); \ |
8b97c5f8 ZW |
2248 | } while (0) |
2249 | ||
d6b4baa4 | 2250 | /* Condition code information. */ |
ff9940b0 | 2251 | /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, |
a5381466 | 2252 | return the mode to be used for the comparison. */ |
d5b7b3ae RE |
2253 | |
2254 | #define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y) | |
ff9940b0 | 2255 | |
880873be RE |
2256 | #define REVERSIBLE_CC_MODE(MODE) 1 |
2257 | ||
2258 | #define REVERSE_CONDITION(CODE,MODE) \ | |
2259 | (((MODE) == CCFPmode || (MODE) == CCFPEmode) \ | |
2260 | ? reverse_condition_maybe_unordered (code) \ | |
2261 | : reverse_condition (code)) | |
008cf58a | 2262 | |
62b10bbc NC |
2263 | #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \ |
2264 | do \ | |
2265 | { \ | |
2266 | if (GET_CODE (OP1) == CONST_INT \ | |
2267 | && ! (const_ok_for_arm (INTVAL (OP1)) \ | |
2268 | || (const_ok_for_arm (- INTVAL (OP1))))) \ | |
2269 | { \ | |
2270 | rtx const_op = OP1; \ | |
a14b88bb PB |
2271 | CODE = arm_canonicalize_comparison ((CODE), GET_MODE (OP0), \ |
2272 | &const_op); \ | |
62b10bbc NC |
2273 | OP1 = const_op; \ |
2274 | } \ | |
2275 | } \ | |
2276 | while (0) | |
62dd06ea | 2277 | |
7dba8395 RH |
2278 | /* The arm5 clz instruction returns 32. */ |
2279 | #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1) | |
ca96ed43 | 2280 | #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1) |
35d965d5 | 2281 | \f |
d5b7b3ae | 2282 | #undef ASM_APP_OFF |
5b3e6663 PB |
2283 | #define ASM_APP_OFF (TARGET_THUMB1 ? "\t.code\t16\n" : \ |
2284 | TARGET_THUMB2 ? "\t.thumb\n" : "") | |
35d965d5 | 2285 | |
35d965d5 | 2286 | /* Output a push or a pop instruction (only used when profiling). */ |
d5b7b3ae | 2287 | #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \ |
8a81cc45 RE |
2288 | do \ |
2289 | { \ | |
2290 | if (TARGET_ARM) \ | |
2291 | asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", \ | |
2292 | STACK_POINTER_REGNUM, REGNO); \ | |
2293 | else \ | |
2294 | asm_fprintf (STREAM, "\tpush {%r}\n", REGNO); \ | |
2295 | } while (0) | |
d5b7b3ae RE |
2296 | |
2297 | ||
2298 | #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \ | |
8a81cc45 RE |
2299 | do \ |
2300 | { \ | |
2301 | if (TARGET_ARM) \ | |
2302 | asm_fprintf (STREAM, "\tldmfd\t%r!,{%r}\n", \ | |
2303 | STACK_POINTER_REGNUM, REGNO); \ | |
2304 | else \ | |
2305 | asm_fprintf (STREAM, "\tpop {%r}\n", REGNO); \ | |
2306 | } while (0) | |
d5b7b3ae | 2307 | |
5b3e6663 PB |
2308 | /* Jump table alignment is explicit in ASM_OUTPUT_CASE_LABEL. */ |
2309 | #define ADDR_VEC_ALIGN(JUMPTABLE) 0 | |
2310 | ||
d5b7b3ae RE |
2311 | /* This is how to output a label which precedes a jumptable. Since |
2312 | Thumb instructions are 2 bytes, we may need explicit alignment here. */ | |
be393ecf | 2313 | #undef ASM_OUTPUT_CASE_LABEL |
5b3e6663 PB |
2314 | #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, JUMPTABLE) \ |
2315 | do \ | |
2316 | { \ | |
2317 | if (TARGET_THUMB && GET_MODE (PATTERN (JUMPTABLE)) == SImode) \ | |
2318 | ASM_OUTPUT_ALIGN (FILE, 2); \ | |
2319 | (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \ | |
2320 | } \ | |
2321 | while (0) | |
2322 | ||
2323 | /* Make sure subsequent insns are aligned after a TBB. */ | |
2324 | #define ASM_OUTPUT_CASE_END(FILE, NUM, JUMPTABLE) \ | |
2325 | do \ | |
2326 | { \ | |
2327 | if (GET_MODE (PATTERN (JUMPTABLE)) == QImode) \ | |
2328 | ASM_OUTPUT_ALIGN (FILE, 1); \ | |
2329 | } \ | |
d5b7b3ae | 2330 | while (0) |
35d965d5 | 2331 | |
6cfc7210 NC |
2332 | #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \ |
2333 | do \ | |
2334 | { \ | |
d5b7b3ae RE |
2335 | if (TARGET_THUMB) \ |
2336 | { \ | |
5b3e6663 | 2337 | if (is_called_in_ARM_mode (DECL) \ |
bf98ec6c | 2338 | || (TARGET_THUMB1 && !TARGET_THUMB1_ONLY \ |
3c072c6b | 2339 | && cfun->is_thunk)) \ |
d5b7b3ae | 2340 | fprintf (STREAM, "\t.code 32\n") ; \ |
5b3e6663 PB |
2341 | else if (TARGET_THUMB1) \ |
2342 | fprintf (STREAM, "\t.code\t16\n\t.thumb_func\n") ; \ | |
d5b7b3ae | 2343 | else \ |
5b3e6663 | 2344 | fprintf (STREAM, "\t.thumb\n\t.thumb_func\n") ; \ |
d5b7b3ae | 2345 | } \ |
6cfc7210 | 2346 | if (TARGET_POKE_FUNCTION_NAME) \ |
586de218 | 2347 | arm_poke_function_name (STREAM, (const char *) NAME); \ |
6cfc7210 NC |
2348 | } \ |
2349 | while (0) | |
35d965d5 | 2350 | |
d5b7b3ae RE |
2351 | /* For aliases of functions we use .thumb_set instead. */ |
2352 | #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \ | |
2353 | do \ | |
2354 | { \ | |
91ea4f8d KG |
2355 | const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \ |
2356 | const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \ | |
d5b7b3ae RE |
2357 | \ |
2358 | if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \ | |
2359 | { \ | |
2360 | fprintf (FILE, "\t.thumb_set "); \ | |
2361 | assemble_name (FILE, LABEL1); \ | |
2362 | fprintf (FILE, ","); \ | |
2363 | assemble_name (FILE, LABEL2); \ | |
2364 | fprintf (FILE, "\n"); \ | |
2365 | } \ | |
2366 | else \ | |
2367 | ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \ | |
2368 | } \ | |
2369 | while (0) | |
2370 | ||
fdc2d3b0 NC |
2371 | #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN |
2372 | /* To support -falign-* switches we need to use .p2align so | |
2373 | that alignment directives in code sections will be padded | |
2374 | with no-op instructions, rather than zeroes. */ | |
5a9335ef | 2375 | #define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE, LOG, MAX_SKIP) \ |
fdc2d3b0 NC |
2376 | if ((LOG) != 0) \ |
2377 | { \ | |
2378 | if ((MAX_SKIP) == 0) \ | |
5a9335ef | 2379 | fprintf ((FILE), "\t.p2align %d\n", (int) (LOG)); \ |
fdc2d3b0 NC |
2380 | else \ |
2381 | fprintf ((FILE), "\t.p2align %d,,%d\n", \ | |
5a9335ef | 2382 | (int) (LOG), (int) (MAX_SKIP)); \ |
fdc2d3b0 NC |
2383 | } |
2384 | #endif | |
35d965d5 | 2385 | \f |
5b3e6663 PB |
2386 | /* Add two bytes to the length of conditionally executed Thumb-2 |
2387 | instructions for the IT instruction. */ | |
2388 | #define ADJUST_INSN_LENGTH(insn, length) \ | |
2389 | if (TARGET_THUMB2 && GET_CODE (PATTERN (insn)) == COND_EXEC) \ | |
2390 | length += 2; | |
2391 | ||
35d965d5 | 2392 | /* Only perform branch elimination (by making instructions conditional) if |
5b3e6663 PB |
2393 | we're optimizing. For Thumb-2 check if any IT instructions need |
2394 | outputting. */ | |
d5b7b3ae RE |
2395 | #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \ |
2396 | if (TARGET_ARM && optimize) \ | |
2397 | arm_final_prescan_insn (INSN); \ | |
5b3e6663 PB |
2398 | else if (TARGET_THUMB2) \ |
2399 | thumb2_final_prescan_insn (INSN); \ | |
2400 | else if (TARGET_THUMB1) \ | |
2401 | thumb1_final_prescan_insn (INSN) | |
35d965d5 | 2402 | |
7bc7696c | 2403 | #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ |
5b3e6663 | 2404 | (CODE == '@' || CODE == '|' || CODE == '.' \ |
88f77cba | 2405 | || CODE == '(' || CODE == ')' || CODE == '#' \ |
5b3e6663 PB |
2406 | || (TARGET_32BIT && (CODE == '?')) \ |
2407 | || (TARGET_THUMB2 && (CODE == '!')) \ | |
d5b7b3ae | 2408 | || (TARGET_THUMB && (CODE == '_'))) |
6cfc7210 | 2409 | |
7bc7696c | 2410 | /* Output an operand of an instruction. */ |
35d965d5 | 2411 | #define PRINT_OPERAND(STREAM, X, CODE) \ |
7bc7696c RE |
2412 | arm_print_operand (STREAM, X, CODE) |
2413 | ||
7b8b8ade NC |
2414 | #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \ |
2415 | (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \ | |
30cf4896 KG |
2416 | : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\ |
2417 | ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \ | |
2418 | ? ((~ (unsigned HOST_WIDE_INT) 0) \ | |
2419 | & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \ | |
7bc7696c | 2420 | : 0)))) |
35d965d5 RS |
2421 | |
2422 | /* Output the address of an operand. */ | |
3cd45774 RE |
2423 | #define ARM_PRINT_OPERAND_ADDRESS(STREAM, X) \ |
2424 | { \ | |
2425 | int is_minus = GET_CODE (X) == MINUS; \ | |
2426 | \ | |
2427 | if (GET_CODE (X) == REG) \ | |
2428 | asm_fprintf (STREAM, "[%r, #0]", REGNO (X)); \ | |
2429 | else if (GET_CODE (X) == PLUS || is_minus) \ | |
2430 | { \ | |
2431 | rtx base = XEXP (X, 0); \ | |
2432 | rtx index = XEXP (X, 1); \ | |
2433 | HOST_WIDE_INT offset = 0; \ | |
f5c630c3 PB |
2434 | if (GET_CODE (base) != REG \ |
2435 | || (GET_CODE (index) == REG && REGNO (index) == SP_REGNUM)) \ | |
3cd45774 | 2436 | { \ |
d6b4baa4 KH |
2437 | /* Ensure that BASE is a register. */ \ |
2438 | /* (one of them must be). */ \ | |
f5c630c3 | 2439 | /* Also ensure the SP is not used as in index register. */ \ |
3cd45774 RE |
2440 | rtx temp = base; \ |
2441 | base = index; \ | |
2442 | index = temp; \ | |
2443 | } \ | |
2444 | switch (GET_CODE (index)) \ | |
2445 | { \ | |
2446 | case CONST_INT: \ | |
2447 | offset = INTVAL (index); \ | |
2448 | if (is_minus) \ | |
2449 | offset = -offset; \ | |
c53dddc2 | 2450 | asm_fprintf (STREAM, "[%r, #%wd]", \ |
3cd45774 RE |
2451 | REGNO (base), offset); \ |
2452 | break; \ | |
2453 | \ | |
2454 | case REG: \ | |
2455 | asm_fprintf (STREAM, "[%r, %s%r]", \ | |
2456 | REGNO (base), is_minus ? "-" : "", \ | |
2457 | REGNO (index)); \ | |
2458 | break; \ | |
2459 | \ | |
2460 | case MULT: \ | |
2461 | case ASHIFTRT: \ | |
2462 | case LSHIFTRT: \ | |
2463 | case ASHIFT: \ | |
2464 | case ROTATERT: \ | |
2465 | { \ | |
2466 | asm_fprintf (STREAM, "[%r, %s%r", \ | |
2467 | REGNO (base), is_minus ? "-" : "", \ | |
2468 | REGNO (XEXP (index, 0))); \ | |
2469 | arm_print_operand (STREAM, index, 'S'); \ | |
2470 | fputs ("]", STREAM); \ | |
2471 | break; \ | |
2472 | } \ | |
2473 | \ | |
2474 | default: \ | |
e6d29d15 | 2475 | gcc_unreachable (); \ |
3cd45774 RE |
2476 | } \ |
2477 | } \ | |
2478 | else if (GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC \ | |
2479 | || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC) \ | |
2480 | { \ | |
2481 | extern enum machine_mode output_memory_reference_mode; \ | |
2482 | \ | |
e6d29d15 | 2483 | gcc_assert (GET_CODE (XEXP (X, 0)) == REG); \ |
3cd45774 RE |
2484 | \ |
2485 | if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \ | |
2486 | asm_fprintf (STREAM, "[%r, #%s%d]!", \ | |
2487 | REGNO (XEXP (X, 0)), \ | |
2488 | GET_CODE (X) == PRE_DEC ? "-" : "", \ | |
2489 | GET_MODE_SIZE (output_memory_reference_mode)); \ | |
2490 | else \ | |
2491 | asm_fprintf (STREAM, "[%r], #%s%d", \ | |
2492 | REGNO (XEXP (X, 0)), \ | |
2493 | GET_CODE (X) == POST_DEC ? "-" : "", \ | |
2494 | GET_MODE_SIZE (output_memory_reference_mode)); \ | |
2495 | } \ | |
2496 | else if (GET_CODE (X) == PRE_MODIFY) \ | |
2497 | { \ | |
2498 | asm_fprintf (STREAM, "[%r, ", REGNO (XEXP (X, 0))); \ | |
2499 | if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \ | |
c53dddc2 | 2500 | asm_fprintf (STREAM, "#%wd]!", \ |
3cd45774 RE |
2501 | INTVAL (XEXP (XEXP (X, 1), 1))); \ |
2502 | else \ | |
2503 | asm_fprintf (STREAM, "%r]!", \ | |
2504 | REGNO (XEXP (XEXP (X, 1), 1))); \ | |
2505 | } \ | |
2506 | else if (GET_CODE (X) == POST_MODIFY) \ | |
2507 | { \ | |
2508 | asm_fprintf (STREAM, "[%r], ", REGNO (XEXP (X, 0))); \ | |
2509 | if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \ | |
c53dddc2 | 2510 | asm_fprintf (STREAM, "#%wd", \ |
3cd45774 RE |
2511 | INTVAL (XEXP (XEXP (X, 1), 1))); \ |
2512 | else \ | |
2513 | asm_fprintf (STREAM, "%r", \ | |
2514 | REGNO (XEXP (XEXP (X, 1), 1))); \ | |
2515 | } \ | |
2516 | else output_addr_const (STREAM, X); \ | |
35d965d5 | 2517 | } |
62dd06ea | 2518 | |
d5b7b3ae RE |
2519 | #define THUMB_PRINT_OPERAND_ADDRESS(STREAM, X) \ |
2520 | { \ | |
2521 | if (GET_CODE (X) == REG) \ | |
2522 | asm_fprintf (STREAM, "[%r]", REGNO (X)); \ | |
2523 | else if (GET_CODE (X) == POST_INC) \ | |
2524 | asm_fprintf (STREAM, "%r!", REGNO (XEXP (X, 0))); \ | |
2525 | else if (GET_CODE (X) == PLUS) \ | |
2526 | { \ | |
e6d29d15 | 2527 | gcc_assert (GET_CODE (XEXP (X, 0)) == REG); \ |
d5b7b3ae | 2528 | if (GET_CODE (XEXP (X, 1)) == CONST_INT) \ |
659bdc68 | 2529 | asm_fprintf (STREAM, "[%r, #%wd]", \ |
d5b7b3ae | 2530 | REGNO (XEXP (X, 0)), \ |
659bdc68 | 2531 | INTVAL (XEXP (X, 1))); \ |
d5b7b3ae RE |
2532 | else \ |
2533 | asm_fprintf (STREAM, "[%r, %r]", \ | |
2534 | REGNO (XEXP (X, 0)), \ | |
2535 | REGNO (XEXP (X, 1))); \ | |
2536 | } \ | |
2537 | else \ | |
2538 | output_addr_const (STREAM, X); \ | |
2539 | } | |
2540 | ||
2541 | #define PRINT_OPERAND_ADDRESS(STREAM, X) \ | |
5b3e6663 | 2542 | if (TARGET_32BIT) \ |
d5b7b3ae RE |
2543 | ARM_PRINT_OPERAND_ADDRESS (STREAM, X) \ |
2544 | else \ | |
2545 | THUMB_PRINT_OPERAND_ADDRESS (STREAM, X) | |
5a9335ef | 2546 | |
d3585b76 DJ |
2547 | #define OUTPUT_ADDR_CONST_EXTRA(file, x, fail) \ |
2548 | if (arm_output_addr_const_extra (file, x) == FALSE) \ | |
2549 | goto fail | |
5a9335ef | 2550 | |
6a5d7526 MS |
2551 | /* A C expression whose value is RTL representing the value of the return |
2552 | address for the frame COUNT steps up from the current frame. */ | |
2553 | ||
d5b7b3ae RE |
2554 | #define RETURN_ADDR_RTX(COUNT, FRAME) \ |
2555 | arm_return_addr (COUNT, FRAME) | |
2556 | ||
f676971a | 2557 | /* Mask of the bits in the PC that contain the real return address |
d5b7b3ae RE |
2558 | when running in 26-bit mode. */ |
2559 | #define RETURN_ADDR_MASK26 (0x03fffffc) | |
6a5d7526 | 2560 | |
2c849145 JM |
2561 | /* Pick up the return address upon entry to a procedure. Used for |
2562 | dwarf2 unwind information. This also enables the table driven | |
2563 | mechanism. */ | |
2c849145 JM |
2564 | #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM) |
2565 | #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM) | |
2566 | ||
39950dff MS |
2567 | /* Used to mask out junk bits from the return address, such as |
2568 | processor state, interrupt status, condition codes and the like. */ | |
2569 | #define MASK_RETURN_ADDR \ | |
2570 | /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \ | |
2571 | in 26 bit mode, the condition codes must be masked out of the \ | |
2572 | return address. This does not apply to ARM6 and later processors \ | |
2573 | when running in 32 bit mode. */ \ | |
61f0ccff RE |
2574 | ((arm_arch4 || TARGET_THUMB) \ |
2575 | ? (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \ | |
fcd53748 | 2576 | : arm_gen_return_addr_mask ()) |
d5b7b3ae RE |
2577 | |
2578 | \f | |
88f77cba JB |
2579 | /* Neon defines builtins from ARM_BUILTIN_MAX upwards, though they don't have |
2580 | symbolic names defined here (which would require too much duplication). | |
2581 | FIXME? */ | |
5a9335ef NC |
2582 | enum arm_builtins |
2583 | { | |
2584 | ARM_BUILTIN_GETWCX, | |
2585 | ARM_BUILTIN_SETWCX, | |
2586 | ||
2587 | ARM_BUILTIN_WZERO, | |
2588 | ||
2589 | ARM_BUILTIN_WAVG2BR, | |
2590 | ARM_BUILTIN_WAVG2HR, | |
2591 | ARM_BUILTIN_WAVG2B, | |
2592 | ARM_BUILTIN_WAVG2H, | |
2593 | ||
2594 | ARM_BUILTIN_WACCB, | |
2595 | ARM_BUILTIN_WACCH, | |
2596 | ARM_BUILTIN_WACCW, | |
2597 | ||
2598 | ARM_BUILTIN_WMACS, | |
2599 | ARM_BUILTIN_WMACSZ, | |
2600 | ARM_BUILTIN_WMACU, | |
2601 | ARM_BUILTIN_WMACUZ, | |
2602 | ||
2603 | ARM_BUILTIN_WSADB, | |
2604 | ARM_BUILTIN_WSADBZ, | |
2605 | ARM_BUILTIN_WSADH, | |
2606 | ARM_BUILTIN_WSADHZ, | |
2607 | ||
2608 | ARM_BUILTIN_WALIGN, | |
2609 | ||
2610 | ARM_BUILTIN_TMIA, | |
2611 | ARM_BUILTIN_TMIAPH, | |
2612 | ARM_BUILTIN_TMIABB, | |
2613 | ARM_BUILTIN_TMIABT, | |
2614 | ARM_BUILTIN_TMIATB, | |
2615 | ARM_BUILTIN_TMIATT, | |
2616 | ||
2617 | ARM_BUILTIN_TMOVMSKB, | |
2618 | ARM_BUILTIN_TMOVMSKH, | |
2619 | ARM_BUILTIN_TMOVMSKW, | |
2620 | ||
2621 | ARM_BUILTIN_TBCSTB, | |
2622 | ARM_BUILTIN_TBCSTH, | |
2623 | ARM_BUILTIN_TBCSTW, | |
2624 | ||
2625 | ARM_BUILTIN_WMADDS, | |
2626 | ARM_BUILTIN_WMADDU, | |
2627 | ||
2628 | ARM_BUILTIN_WPACKHSS, | |
2629 | ARM_BUILTIN_WPACKWSS, | |
2630 | ARM_BUILTIN_WPACKDSS, | |
2631 | ARM_BUILTIN_WPACKHUS, | |
2632 | ARM_BUILTIN_WPACKWUS, | |
2633 | ARM_BUILTIN_WPACKDUS, | |
2634 | ||
2635 | ARM_BUILTIN_WADDB, | |
2636 | ARM_BUILTIN_WADDH, | |
2637 | ARM_BUILTIN_WADDW, | |
2638 | ARM_BUILTIN_WADDSSB, | |
2639 | ARM_BUILTIN_WADDSSH, | |
2640 | ARM_BUILTIN_WADDSSW, | |
2641 | ARM_BUILTIN_WADDUSB, | |
2642 | ARM_BUILTIN_WADDUSH, | |
2643 | ARM_BUILTIN_WADDUSW, | |
2644 | ARM_BUILTIN_WSUBB, | |
2645 | ARM_BUILTIN_WSUBH, | |
2646 | ARM_BUILTIN_WSUBW, | |
2647 | ARM_BUILTIN_WSUBSSB, | |
2648 | ARM_BUILTIN_WSUBSSH, | |
2649 | ARM_BUILTIN_WSUBSSW, | |
2650 | ARM_BUILTIN_WSUBUSB, | |
2651 | ARM_BUILTIN_WSUBUSH, | |
2652 | ARM_BUILTIN_WSUBUSW, | |
2653 | ||
2654 | ARM_BUILTIN_WAND, | |
2655 | ARM_BUILTIN_WANDN, | |
2656 | ARM_BUILTIN_WOR, | |
2657 | ARM_BUILTIN_WXOR, | |
2658 | ||
2659 | ARM_BUILTIN_WCMPEQB, | |
2660 | ARM_BUILTIN_WCMPEQH, | |
2661 | ARM_BUILTIN_WCMPEQW, | |
2662 | ARM_BUILTIN_WCMPGTUB, | |
2663 | ARM_BUILTIN_WCMPGTUH, | |
2664 | ARM_BUILTIN_WCMPGTUW, | |
2665 | ARM_BUILTIN_WCMPGTSB, | |
2666 | ARM_BUILTIN_WCMPGTSH, | |
2667 | ARM_BUILTIN_WCMPGTSW, | |
2668 | ||
2669 | ARM_BUILTIN_TEXTRMSB, | |
2670 | ARM_BUILTIN_TEXTRMSH, | |
2671 | ARM_BUILTIN_TEXTRMSW, | |
2672 | ARM_BUILTIN_TEXTRMUB, | |
2673 | ARM_BUILTIN_TEXTRMUH, | |
2674 | ARM_BUILTIN_TEXTRMUW, | |
2675 | ARM_BUILTIN_TINSRB, | |
2676 | ARM_BUILTIN_TINSRH, | |
2677 | ARM_BUILTIN_TINSRW, | |
2678 | ||
2679 | ARM_BUILTIN_WMAXSW, | |
2680 | ARM_BUILTIN_WMAXSH, | |
2681 | ARM_BUILTIN_WMAXSB, | |
2682 | ARM_BUILTIN_WMAXUW, | |
2683 | ARM_BUILTIN_WMAXUH, | |
2684 | ARM_BUILTIN_WMAXUB, | |
2685 | ARM_BUILTIN_WMINSW, | |
2686 | ARM_BUILTIN_WMINSH, | |
2687 | ARM_BUILTIN_WMINSB, | |
2688 | ARM_BUILTIN_WMINUW, | |
2689 | ARM_BUILTIN_WMINUH, | |
2690 | ARM_BUILTIN_WMINUB, | |
2691 | ||
f07a6b21 BE |
2692 | ARM_BUILTIN_WMULUM, |
2693 | ARM_BUILTIN_WMULSM, | |
5a9335ef NC |
2694 | ARM_BUILTIN_WMULUL, |
2695 | ||
2696 | ARM_BUILTIN_PSADBH, | |
2697 | ARM_BUILTIN_WSHUFH, | |
2698 | ||
2699 | ARM_BUILTIN_WSLLH, | |
2700 | ARM_BUILTIN_WSLLW, | |
2701 | ARM_BUILTIN_WSLLD, | |
2702 | ARM_BUILTIN_WSRAH, | |
2703 | ARM_BUILTIN_WSRAW, | |
2704 | ARM_BUILTIN_WSRAD, | |
2705 | ARM_BUILTIN_WSRLH, | |
2706 | ARM_BUILTIN_WSRLW, | |
2707 | ARM_BUILTIN_WSRLD, | |
2708 | ARM_BUILTIN_WRORH, | |
2709 | ARM_BUILTIN_WRORW, | |
2710 | ARM_BUILTIN_WRORD, | |
2711 | ARM_BUILTIN_WSLLHI, | |
2712 | ARM_BUILTIN_WSLLWI, | |
2713 | ARM_BUILTIN_WSLLDI, | |
2714 | ARM_BUILTIN_WSRAHI, | |
2715 | ARM_BUILTIN_WSRAWI, | |
2716 | ARM_BUILTIN_WSRADI, | |
2717 | ARM_BUILTIN_WSRLHI, | |
2718 | ARM_BUILTIN_WSRLWI, | |
2719 | ARM_BUILTIN_WSRLDI, | |
2720 | ARM_BUILTIN_WRORHI, | |
2721 | ARM_BUILTIN_WRORWI, | |
2722 | ARM_BUILTIN_WRORDI, | |
2723 | ||
2724 | ARM_BUILTIN_WUNPCKIHB, | |
2725 | ARM_BUILTIN_WUNPCKIHH, | |
2726 | ARM_BUILTIN_WUNPCKIHW, | |
2727 | ARM_BUILTIN_WUNPCKILB, | |
2728 | ARM_BUILTIN_WUNPCKILH, | |
2729 | ARM_BUILTIN_WUNPCKILW, | |
2730 | ||
2731 | ARM_BUILTIN_WUNPCKEHSB, | |
2732 | ARM_BUILTIN_WUNPCKEHSH, | |
2733 | ARM_BUILTIN_WUNPCKEHSW, | |
2734 | ARM_BUILTIN_WUNPCKEHUB, | |
2735 | ARM_BUILTIN_WUNPCKEHUH, | |
2736 | ARM_BUILTIN_WUNPCKEHUW, | |
2737 | ARM_BUILTIN_WUNPCKELSB, | |
2738 | ARM_BUILTIN_WUNPCKELSH, | |
2739 | ARM_BUILTIN_WUNPCKELSW, | |
2740 | ARM_BUILTIN_WUNPCKELUB, | |
2741 | ARM_BUILTIN_WUNPCKELUH, | |
2742 | ARM_BUILTIN_WUNPCKELUW, | |
2743 | ||
d3585b76 DJ |
2744 | ARM_BUILTIN_THREAD_POINTER, |
2745 | ||
88f77cba JB |
2746 | ARM_BUILTIN_NEON_BASE, |
2747 | ||
2748 | ARM_BUILTIN_MAX = ARM_BUILTIN_NEON_BASE /* FIXME: Wrong! */ | |
5a9335ef | 2749 | }; |
978e411f CD |
2750 | |
2751 | /* Do not emit .note.GNU-stack by default. */ | |
2752 | #ifndef NEED_INDICATE_EXEC_STACK | |
2753 | #define NEED_INDICATE_EXEC_STACK 0 | |
2754 | #endif | |
2755 | ||
88657302 | 2756 | #endif /* ! GCC_ARM_H */ |