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[thirdparty/gcc.git] / gcc / config / arm / arm.h
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35d965d5 1/* Definitions of target machine for GNU compiler, for Acorn RISC Machine.
996a5f59 2 Copyright (C) 1991, 1993, 1994 Free Software Foundation, Inc.
35d965d5
RS		 3 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
4 and Martin Simmons (@harleqn.co.uk).
ff9940b0
RE		 5 More major hacks by Richard Earnshaw (rwe11@cl.cam.ac.uk)
6
35d965d5
RS		 7This file is part of GNU CC.
8
9GNU CC is free software; you can redistribute it and/or modify
10it under the terms of the GNU General Public License as published by
11the Free Software Foundation; either version 2, or (at your option)
12any later version.
13
14GNU CC is distributed in the hope that it will be useful,
15but WITHOUT ANY WARRANTY; without even the implied warranty of
16MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17GNU General Public License for more details.
18
19You should have received a copy of the GNU General Public License
20along with GNU CC; see the file COPYING. If not, write to
21the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
22
ea7273ae 23/* Sometimes the directive `riscos' is checked. This does not imply that this
35d965d5
RS		 24 tm file can be used unchanged to build a GCC for RISC OS.
25 (Since in fact, it can't.) */
26
7bc7696c
RE		 27extern void output_func_prologue ();
28extern void output_func_epilogue ();
35d965d5
RS		 29extern char *output_add_immediate ();
30extern char *output_call ();
ff9940b0 31extern char *output_call_mem ();
35d965d5
RS		 32extern char *output_move_double ();
33extern char *output_mov_double_fpu_from_arm ();
34extern char *output_mov_double_arm_from_fpu ();
7fc6c9f0
RK		 35extern char *output_mov_long_double_fpu_from_arm ();
36extern char *output_mov_long_double_arm_from_fpu ();
37extern char *output_mov_long_double_arm_from_arm ();
35d965d5
RS		 38extern char *output_mov_immediate ();
39extern char *output_multi_immediate ();
ff9940b0
RE		 40extern char *output_return_instruction ();
41extern char *output_load_symbol ();
42extern char *fp_immediate_constant ();
43extern struct rtx_def *gen_compare_reg ();
44extern struct rtx_def *arm_gen_store_multiple ();
45extern struct rtx_def *arm_gen_load_multiple ();
46
47extern char *arm_condition_codes[];
48
49/* This is needed by the tail-calling peepholes */
50extern int frame_pointer_needed;
51
35d965d5 52\f
ff9940b0
RE		 53#ifndef CPP_PREDEFINES
54#define CPP_PREDEFINES "-Darm -Acpu(arm) -Amachine(arm)"
55#endif
35d965d5 56
ff9940b0
RE		 57#ifndef CPP_SPEC
58#define CPP_SPEC "%{m6:-D__arm6__}"
35d965d5
RS		 59#endif
60\f
61/* Run-time Target Specification. */
ff9940b0 62#ifndef TARGET_VERSION
35d965d5 63#define TARGET_VERSION \
ff9940b0
RE		 64 fputs (" (ARM/generic)", stderr);
65#endif
35d965d5
RS		 66
67/* Run-time compilation parameters selecting different hardware subsets.
68 On the ARM, misuse it in a different way. */
69extern int target_flags;
70
71/* Nonzero if the function prologue (and epilogue) should obey
72 the ARM Procedure Call Standard. */
73#define TARGET_APCS (target_flags & 1)
74
75/* Nonzero if the function prologue should output the function name to enable
76 the post mortem debugger to print a backtrace (very useful on RISCOS,
77 unused on RISCiX). Specifying this flag also enables -mapcs.
78 XXX Must still be implemented in the prologue. */
79#define TARGET_POKE_FUNCTION_NAME (target_flags & 2)
80
81/* Nonzero if floating point instructions are emulated by the FPE, in which
82 case instruction scheduling becomes very uninteresting. */
83#define TARGET_FPE (target_flags & 4)
84
ff9940b0
RE		 85/* Nonzero if destined for an ARM6xx. Takes out bits that assume restoration
86 of condition flags when returning from a branch & link (ie. a function) */
87#define TARGET_6 (target_flags & 8)
88
89/* ARM_EXTRA_TARGET_SWITCHES is used in riscix.h to define some options which
90 are passed to the preprocessor and the assembler post-processor. They
91 aren't needed in the main pass of the compiler, but if we don't define
92 them in target switches cc1 complains about them. For the sake of
93 argument lets allocate bit 31 of target flags for such options. */
94
95#ifndef ARM_EXTRA_TARGET_SWITCHES
96#define ARM_EXTRA_TARGET_SWITCHES
97#endif
98
35d965d5
RS		 99#define TARGET_SWITCHES \
100{ \
101 {"apcs", 1}, \
102 {"poke-function-name", 2}, \
103 {"fpe", 4}, \
ff9940b0
RE		 104 {"6", 8}, \
105 {"2", -8}, \
106 {"3", -8}, \
107 ARM_EXTRA_TARGET_SWITCHES \
35d965d5
RS		 108 {"", TARGET_DEFAULT } \
109}
110
ff9940b0
RE		 111/* Which processor we are running on. Currently this is only used to
112 get the condition code clobbering attribute right when we are running on
113 an arm 6 */
114
115enum processor_type
116{
117 PROCESSOR_ARM2,
118 PROCESSOR_ARM3,
119 PROCESSOR_ARM6
120};
121
122/* Recast the cpu class to be the cpu attribute. */
123
124/* Recast the cpu class to be the cpu attribute. */
125#define arm_cpu_attr ((enum attr_cpu)arm_cpu)
126
127extern enum processor_type arm_cpu;
128
35d965d5
RS		 129#define TARGET_DEFAULT 0
130
131#define TARGET_MEM_FUNCTIONS 1
132
133/* OVERRIDE_OPTIONS takes care of the following:
134 - if -mpoke-function-name, then -mapcs.
135 - if doing debugging, then -mapcs; if RISCOS, then -mpoke-function-name.
136 - if floating point is done by emulation, forget about instruction
137 scheduling. Note that this only saves compilation time; it doesn't
138 matter for the final code. */
ff9940b0 139#ifndef TARGET_WHEN_DEBUGGING
b4ac57ab 140#define TARGET_WHEN_DEBUGGING 1
35d965d5
RS		 141#endif
142
143#define OVERRIDE_OPTIONS \
144{ \
ff9940b0
RE		 145 if (write_symbols != NO_DEBUG && flag_omit_frame_pointer) \
146 warning ("-g without a frame pointer may not give sensible debugging");\
147 if (TARGET_POKE_FUNCTION_NAME) \
35d965d5
RS		 148 target_flags |= 1; \
149 if (TARGET_FPE) \
150 flag_schedule_insns = flag_schedule_insns_after_reload = 0; \
ff9940b0 151 arm_cpu = TARGET_6 ? PROCESSOR_ARM6: PROCESSOR_ARM2; \
35d965d5 152}
35d965d5
RS		 153\f
154/* Target machine storage Layout. */
155
ff9940b0
RE		 156
157/* Define this macro if it is advisable to hold scalars in registers
158 in a wider mode than that declared by the program. In such cases,
159 the value is constrained to be within the bounds of the declared
160 type, but kept valid in the wider mode. The signedness of the
161 extension may differ from that of the type. */
162
163/* It is far faster to zero extend chars than to sign extend them */
164
165#define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
166 if (GET_MODE_CLASS (MODE) == MODE_INT \
167 && GET_MODE_SIZE (MODE) < 4) \
168 { \
169 if (MODE == QImode) \
170 UNSIGNEDP = 1; \
171 (MODE) = SImode; \
172 }
173
174/* Define for XFmode extended real floating point support.
175 This will automatically cause REAL_ARITHMETIC to be defined. */
176/* For the ARM:
177 I think I have added all the code to make this work. Unfortunately,
178 early releases of the floating point emulation code on RISCiX used a
179 different format for extended precision numbers. On my RISCiX box there
180 is a bug somewhere which causes the machine to lock up when running enquire
181 with long doubles. There is the additional aspect that Norcroft C
182 treats long doubles as doubles and we ought to remain compatible.
183 Perhaps someone with an FPA coprocessor and not running RISCiX would like
184 to try this someday. */
185/* #define LONG_DOUBLE_TYPE_SIZE 96 */
186
187/* Disable XFmode patterns in md file */
188#define ENABLE_XF_PATTERNS 0
189
190/* Define if you don't want extended real, but do want to use the
191 software floating point emulator for REAL_ARITHMETIC and
192 decimal <-> binary conversion. */
193/* See comment above */
194#define REAL_ARITHMETIC
195
35d965d5
RS		 196/* Define this if most significant bit is lowest numbered
197 in instructions that operate on numbered bit-fields. */
198#define BITS_BIG_ENDIAN 0
199
200/* Define this if most significant byte of a word is the lowest numbered. */
201#define BYTES_BIG_ENDIAN 0
202
203/* Define this if most significant word of a multiword number is the lowest
204 numbered. */
205#define WORDS_BIG_ENDIAN 0
206
7fc6c9f0
RK		 207/* Define this if most significant word of doubles is the lowest numbered */
208#define FLOAT_WORDS_BIG_ENDIAN 1
209
b4ac57ab 210/* Number of bits in an addressable storage unit */
35d965d5
RS		 211#define BITS_PER_UNIT 8
212
213#define BITS_PER_WORD 32
214
215#define UNITS_PER_WORD 4
216
217#define POINTER_SIZE 32
218
219#define PARM_BOUNDARY 32
220
221#define STACK_BOUNDARY 32
222
223#define FUNCTION_BOUNDARY 32
224
225#define EMPTY_FIELD_BOUNDARY 32
226
227#define BIGGEST_ALIGNMENT 32
228
ff9940b0
RE		 229/* Make strings word-aligned so strcpy from constants will be faster. */
230#define CONSTANT_ALIGNMENT(EXP, ALIGN) \
231 (TREE_CODE (EXP) == STRING_CST \
232 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
233
b4ac57ab
RS		 234/* Every structures size must be a multiple of 32 bits. */
235#define STRUCTURE_SIZE_BOUNDARY 32
236
ff9940b0
RE		 237/* Non-zero if move instructions will actually fail to work
238 when given unaligned data. */
35d965d5
RS		 239#define STRICT_ALIGNMENT 1
240
ff9940b0
RE		 241#define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
242
35d965d5
RS		 243/* Define number of bits in most basic integer type.
244 (If undefined, default is BITS_PER_WORD). */
245/* #define INT_TYPE_SIZE */
246\f
247/* Standard register usage. */
248
249/* Register allocation in ARM Procedure Call Standard (as used on RISCiX):
250 (S - saved over call).
251
252 r0 * argument word/integer result
253 r1-r3 argument word
254
255 r4-r8 S register variable
256 r9 S (rfp) register variable (real frame pointer)
257
258 r10 F S (sl) stack limit (not currently used)
259 r11 F S (fp) argument pointer
260 r12 (ip) temp workspace
261 r13 F S (sp) lower end of current stack frame
262 r14 (lr) link address/workspace
263 r15 F (pc) program counter
264
265 f0 floating point result
266 f1-f3 floating point scratch
267
268 f4-f7 S floating point variable
269
ff9940b0
RE		 270 cc This is NOT a real register, but is used internally
271 to represent things that use or set the condition
272 codes.
273 sfp This isn't either. It is used during rtl generation
274 since the offset between the frame pointer and the
275 auto's isn't known until after register allocation.
276 afp Nor this, we only need this because of non-local
277 goto. Without it fp appears to be used and the
278 elimination code won't get rid of sfp. It tracks
279 fp exactly at all times.
280
35d965d5
RS		 281 *: See CONDITIONAL_REGISTER_USAGE */
282
ff9940b0
RE		 283/* The stack backtrace structure is as follows:
284 fp points to here: | save code pointer | [fp]
285 | return link value | [fp, #-4]
286 | return sp value | [fp, #-8]
287 | return fp value | [fp, #-12]
288 [| saved r10 value |]
289 [| saved r9 value |]
290 [| saved r8 value |]
291 [| saved r7 value |]
292 [| saved r6 value |]
293 [| saved r5 value |]
294 [| saved r4 value |]
295 [| saved r3 value |]
296 [| saved r2 value |]
297 [| saved r1 value |]
298 [| saved r0 value |]
299 [| saved f7 value |] three words
300 [| saved f6 value |] three words
301 [| saved f5 value |] three words
302 [| saved f4 value |] three words
303 r0-r3 are not normally saved in a C function. */
304
305/* The number of hard registers is 16 ARM + 8 FPU + 1 CC + 1 SFP. */
306#define FIRST_PSEUDO_REGISTER 27
35d965d5
RS		 307
308/* 1 for registers that have pervasive standard uses
309 and are not available for the register allocator. */
310#define FIXED_REGISTERS \
311{ \
312 0,0,0,0,0,0,0,0, \
313 0,0,1,1,0,1,0,1, \
ff9940b0
RE		 314 0,0,0,0,0,0,0,0, \
315 1,1,1 \
35d965d5
RS		 316}
317
318/* 1 for registers not available across function calls.
319 These must include the FIXED_REGISTERS and also any
320 registers that can be used without being saved.
321 The latter must include the registers where values are returned
322 and the register where structure-value addresses are passed.
ff9940b0
RE		 323 Aside from that, you can include as many other registers as you like.
324 The CC is not preserved over function calls on the ARM 6, so it is
325 easier to assume this for all. SFP is preserved, since FP is. */
35d965d5
RS		 326#define CALL_USED_REGISTERS \
327{ \
328 1,1,1,1,0,0,0,0, \
329 0,0,1,1,1,1,1,1, \
ff9940b0
RE		 330 1,1,1,1,0,0,0,0, \
331 1,1,1 \
35d965d5
RS		 332}
333
334/* If doing stupid life analysis, avoid a bug causing a return value r0 to be
335 trampled. This effectively reduces the number of available registers by 1.
336 XXX It is a hack, I know.
337 XXX Is this still needed? */
338#define CONDITIONAL_REGISTER_USAGE \
339{ \
340 if (obey_regdecls) \
341 fixed_regs[0] = 1; \
342}
343
344/* Return number of consecutive hard regs needed starting at reg REGNO
345 to hold something of mode MODE.
346 This is ordinarily the length in words of a value of mode MODE
347 but can be less for certain modes in special long registers.
348
349 On the ARM regs are UNITS_PER_WORD bits wide; FPU regs can hold any FP
350 mode. */
ff9940b0
RE		 351#define HARD_REGNO_NREGS(REGNO, MODE) \
352 (((REGNO) >= 16 && REGNO != FRAME_POINTER_REGNUM \
353 && (REGNO) != ARG_POINTER_REGNUM) ? 1 \
35d965d5
RS		 354 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
355
356/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
357 This is TRUE for ARM regs since they can hold anything, and TRUE for FPU
358 regs holding FP. */
ff9940b0
RE		 359#define HARD_REGNO_MODE_OK(REGNO, MODE) \
360 ((GET_MODE_CLASS (MODE) == MODE_CC) ? (REGNO == CC_REGNUM) : \
361 ((REGNO) < 16 || REGNO == FRAME_POINTER_REGNUM \
362 || REGNO == ARG_POINTER_REGNUM \
363 || GET_MODE_CLASS (MODE) == MODE_FLOAT))
35d965d5
RS		 364
365/* Value is 1 if it is a good idea to tie two pseudo registers
366 when one has mode MODE1 and one has mode MODE2.
367 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
368 for any hard reg, then this must be 0 for correct output. */
369#define MODES_TIEABLE_P(MODE1, MODE2) \
370 (((MODE1) == SFmode || (MODE1) == DFmode) \
371 == ((MODE2) == SFmode || (MODE2) == DFmode))
372
373/* Specify the registers used for certain standard purposes.
374 The values of these macros are register numbers. */
375
376/* Define this if the program counter is overloaded on a register. */
377#define PC_REGNUM 15
378
379/* Register to use for pushing function arguments. */
380#define STACK_POINTER_REGNUM 13
381
382/* Base register for access to local variables of the function. */
ff9940b0
RE		 383#define FRAME_POINTER_REGNUM 25
384
385/* Define this to be where the real frame pointer is if it is not possible to
386 work out the offset between the frame pointer and the automatic variables
387 until after register allocation has taken place. FRAME_POINTER_REGNUM
388 should point to a special register that we will make sure is eliminated. */
389#define HARD_FRAME_POINTER_REGNUM 11
35d965d5
RS		 390
391/* Value should be nonzero if functions must have frame pointers.
392 Zero means the frame pointer need not be set up (and parms may be accessed
ff9940b0
RE		 393 via the stack pointer) in functions that seem suitable.
394 If we have to have a frame pointer we might as well make use of it.
395 APCS says that the frame pointer does not need to be pushed in leaf
396 functions. */
397#define FRAME_POINTER_REQUIRED (TARGET_APCS && !leaf_function_p ())
35d965d5
RS		 398
399/* Base register for access to arguments of the function. */
ff9940b0 400#define ARG_POINTER_REGNUM 26
35d965d5
RS		 401
402/* The native (Norcroft) Pascal compiler for the ARM passes the static chain
403 as an invisible last argument (possible since varargs don't exist in
404 Pascal), so the following is not true. */
405#define STATIC_CHAIN_REGNUM 8
406
407/* Register in which address to store a structure value
408 is passed to a function. */
409#define STRUCT_VALUE_REGNUM 0
410
ff9940b0
RE		 411/* Internal, so that we don't need to refer to a raw number */
412#define CC_REGNUM 24
413
35d965d5 414/* The order in which register should be allocated. It is good to use ip
ff9940b0
RE		 415 since no saving is required (though calls clobber it) and it never contains
416 function parameters. It is quite good to use lr since other calls may
417 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is
418 least likely to contain a function parameter; in addition results are
419 returned in r0.
420 */
35d965d5
RS		 421#define REG_ALLOC_ORDER \
422{ \
ff9940b0 423 3, 2, 1, 0, 12, 14, 4, 5, \
35d965d5 424 6, 7, 8, 10, 9, 11, 13, 15, \
ff9940b0
RE		 425 16, 17, 18, 19, 20, 21, 22, 23, \
426 24, 25 \
35d965d5
RS		 427}
428\f
429/* Register and constant classes. */
430
431/* Register classes: all ARM regs or all FPU regs---simple! */
432enum reg_class
433{
434 NO_REGS,
435 FPU_REGS,
436 GENERAL_REGS,
437 ALL_REGS,
438 LIM_REG_CLASSES
439};
440
441#define N_REG_CLASSES (int) LIM_REG_CLASSES
442
443/* Give names of register classes as strings for dump file. */
444#define REG_CLASS_NAMES \
445{ \
446 "NO_REGS", \
447 "FPU_REGS", \
448 "GENERAL_REGS", \
449 "ALL_REGS", \
450}
451
452/* Define which registers fit in which classes.
453 This is an initializer for a vector of HARD_REG_SET
454 of length N_REG_CLASSES. */
455#define REG_CLASS_CONTENTS \
456{ \
ff9940b0
RE		 457 0x0000000, /* NO_REGS */ \
458 0x0FF0000, /* FPU_REGS */ \
459 0x200FFFF, /* GENERAL_REGS */ \
460 0x2FFFFFF /* ALL_REGS */ \
35d965d5
RS		 461}
462
463/* The same information, inverted:
464 Return the class number of the smallest class containing
465 reg number REGNO. This could be a conditional expression
466 or could index an array. */
ff9940b0
RE		 467#define REGNO_REG_CLASS(REGNO) \
468 (((REGNO) < 16 || REGNO == FRAME_POINTER_REGNUM \
469 || REGNO == ARG_POINTER_REGNUM) \
470 ? GENERAL_REGS : (REGNO) == CC_REGNUM \
471 ? NO_REGS : FPU_REGS)
35d965d5
RS		 472
473/* The class value for index registers, and the one for base regs. */
474#define INDEX_REG_CLASS GENERAL_REGS
475#define BASE_REG_CLASS GENERAL_REGS
476
477/* Get reg_class from a letter such as appears in the machine description.
478 We only need constraint `f' for FPU_REGS (`r' == GENERAL_REGS). */
479#define REG_CLASS_FROM_LETTER(C) \
480 ((C)=='f' ? FPU_REGS : NO_REGS)
481
482/* The letters I, J, K, L and M in a register constraint string
483 can be used to stand for particular ranges of immediate operands.
484 This macro defines what the ranges are.
485 C is the letter, and VALUE is a constant value.
486 Return 1 if VALUE is in the range specified by C.
b4ac57ab 487 I: immediate arithmetic operand (i.e. 8 bits shifted as required).
ff9940b0 488 J: valid indexing constants.
aef1764c
RE		 489 K: ~value ok in rhs argument of data operand.
490 L: -value ok in rhs argument of data operand. */
491#define CONST_OK_FOR_LETTER_P(VALUE, C) \
492 ((C) == 'I' ? const_ok_for_arm (VALUE) : \
493 (C) == 'J' ? ((VALUE) < 4096 && (VALUE) > -4096) : \
494 (C) == 'K' ? (const_ok_for_arm (~(VALUE))) : \
495 (C) == 'L' ? (const_ok_for_arm (-(VALUE))) : 0)
ff9940b0
RE		 496
497/* For the ARM, `Q' means that this is a memory operand that is just
498 an offset from a register.
499 `S' means any symbol that has the SYMBOL_REF_FLAG set or a CONSTANT_POOL
500 address. This means that the symbol is in the text segment and can be
501 accessed without using a load. */
502
503#define EXTRA_CONSTRAINT(OP, C) \
504 ((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG \
008cf58a
RE		 505 : (C) == 'R' ? (GET_CODE (OP) == MEM \
506 && GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \
507 && CONSTANT_POOL_ADDRESS_P (XEXP (OP, 0))) \
508 : (C) == 'S' ? (optimize > 0 && CONSTANT_ADDRESS_P (OP)) : 0)
ff9940b0
RE		 509
510/* Constant letter 'G' for the FPU immediate constants.
511 'H' means the same constant negated. */
512#define CONST_DOUBLE_OK_FOR_LETTER_P(X,C) \
513 ((C) == 'G' ? const_double_rtx_ok_for_fpu (X) \
514 : (C) == 'H' ? neg_const_double_rtx_ok_for_fpu (X) : 0)
35d965d5
RS		 515
516/* Given an rtx X being reloaded into a reg required to be
517 in class CLASS, return the class of reg to actually use.
518 In general this is just CLASS; but on some machines
519 in some cases it is preferable to use a more restrictive class. */
520#define PREFERRED_RELOAD_CLASS(X, CLASS) (CLASS)
521
ff9940b0
RE		 522/* Return the register class of a scratch register needed to copy IN into
523 or out of a register in CLASS in MODE. If it can be done directly,
524 NO_REGS is returned. */
525#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,X) \
526 (((MODE) == DFmode && (CLASS) == GENERAL_REGS \
527 && true_regnum (X) == -1) ? GENERAL_REGS \
7fc6c9f0 528 : ((MODE) == HImode && true_regnum (X) == -1) ? GENERAL_REGS : NO_REGS)
ff9940b0 529
35d965d5
RS		 530/* Return the maximum number of consecutive registers
531 needed to represent mode MODE in a register of class CLASS.
532 ARM regs are UNITS_PER_WORD bits while FPU regs can hold any FP mode */
533#define CLASS_MAX_NREGS(CLASS, MODE) \
534 ((CLASS) == FPU_REGS ? 1 \
535 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
536
ff9940b0 537/* Moves between FPU_REGS and GENERAL_REGS are two memory insns. */
35d965d5
RS		 538#define REGISTER_MOVE_COST(CLASS1, CLASS2) \
539 ((((CLASS1) == FPU_REGS && (CLASS2) != FPU_REGS) \
540 || ((CLASS2) == FPU_REGS && (CLASS1) != FPU_REGS)) \
ff9940b0 541 ? 20 : 2)
35d965d5
RS		 542\f
543/* Stack layout; function entry, exit and calling. */
544
545/* Define this if pushing a word on the stack
546 makes the stack pointer a smaller address. */
547#define STACK_GROWS_DOWNWARD 1
548
549/* Define this if the nominal address of the stack frame
550 is at the high-address end of the local variables;
551 that is, each additional local variable allocated
552 goes at a more negative offset in the frame. */
553#define FRAME_GROWS_DOWNWARD 1
554
555/* Offset within stack frame to start allocating local variables at.
556 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
557 first local allocated. Otherwise, it is the offset to the BEGINNING
558 of the first local allocated. */
559#define STARTING_FRAME_OFFSET 0
560
561/* If we generate an insn to push BYTES bytes,
562 this says how many the stack pointer really advances by. */
563#define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3)
564
565/* Offset of first parameter from the argument pointer register value. */
566#define FIRST_PARM_OFFSET(FNDECL) 4
567
568/* Value is the number of byte of arguments automatically
569 popped when returning from a subroutine call.
570 FUNTYPE is the data type of the function (as a tree),
571 or for a library call it is an identifier node for the subroutine name.
572 SIZE is the number of bytes of arguments passed on the stack.
573
574 On the ARM, the caller does not pop any of its arguments that were passed
575 on the stack. */
576#define RETURN_POPS_ARGS(FUNTYPE, SIZE) 0
577
578/* Define how to find the value returned by a function.
579 VALTYPE is the data type of the value (as a tree).
580 If the precise function being called is known, FUNC is its FUNCTION_DECL;
581 otherwise, FUNC is 0. */
582#define FUNCTION_VALUE(VALTYPE, FUNC) \
583 (GET_MODE_CLASS (TYPE_MODE (VALTYPE)) == MODE_FLOAT \
584 ? gen_rtx (REG, TYPE_MODE (VALTYPE), 16) \
585 : gen_rtx (REG, TYPE_MODE (VALTYPE), 0))
586
587/* Define how to find the value returned by a library function
588 assuming the value has mode MODE. */
589#define LIBCALL_VALUE(MODE) \
590 (GET_MODE_CLASS (MODE) == MODE_FLOAT \
591 ? gen_rtx (REG, MODE, 16) \
592 : gen_rtx (REG, MODE, 0))
593
594/* 1 if N is a possible register number for a function value.
595 On the ARM, only r0 and f0 can return results. */
596#define FUNCTION_VALUE_REGNO_P(REGNO) \
597 ((REGNO) == 0 || (REGNO) == 16)
598
599/* Define where to put the arguments to a function.
600 Value is zero to push the argument on the stack,
601 or a hard register in which to store the argument.
602
603 MODE is the argument's machine mode.
604 TYPE is the data type of the argument (as a tree).
605 This is null for libcalls where that information may
606 not be available.
607 CUM is a variable of type CUMULATIVE_ARGS which gives info about
608 the preceding args and about the function being called.
609 NAMED is nonzero if this argument is a named parameter
610 (otherwise it is an extra parameter matching an ellipsis).
611
612 On the ARM, normally the first 16 bytes are passed in registers r0-r3; all
613 other arguments are passed on the stack. If (NAMED == 0) (which happens
614 only in assign_parms, since SETUP_INCOMING_VARARGS is defined), say it is
615 passed in the stack (function_prologue will indeed make it pass in the
616 stack if necessary). */
617#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
618 ((NAMED) \
619 ? ((CUM) >= 16 ? 0 : gen_rtx (REG, MODE, (CUM) / 4)) \
620 : 0)
621
622/* For an arg passed partly in registers and partly in memory,
623 this is the number of registers used.
624 For args passed entirely in registers or entirely in memory, zero. */
625#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
626 ((CUM) < 16 && 16 < (CUM) + ((MODE) != BLKmode \
627 ? GET_MODE_SIZE (MODE) \
628 : int_size_in_bytes (TYPE)) \
629 ? 4 - (CUM) / 4 : 0)
630
631/* A C type for declaring a variable that is used as the first argument of
632 `FUNCTION_ARG' and other related values. For some target machines, the
633 type `int' suffices and can hold the number of bytes of argument so far.
634
635 On the ARM, this is the number of bytes of arguments scanned so far. */
636#define CUMULATIVE_ARGS int
637
638/* Initialize a variable CUM of type CUMULATIVE_ARGS
639 for a call to a function whose data type is FNTYPE.
640 For a library call, FNTYPE is 0.
641 On the ARM, the offset starts at 0. */
642#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME) \
ff9940b0 643 ((CUM) = (((FNTYPE) && aggregate_value_p (TREE_TYPE ((FNTYPE)))) ? 4 : 0))
35d965d5
RS		 644
645/* Update the data in CUM to advance over an argument
646 of mode MODE and data type TYPE.
647 (TYPE is null for libcalls where that information may not be available.) */
648#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
649 (CUM) += ((MODE) != BLKmode \
650 ? (GET_MODE_SIZE (MODE) + 3) & ~3 \
651 : (int_size_in_bytes (TYPE) + 3) & ~3) \
652
653/* 1 if N is a possible register number for function argument passing.
654 On the ARM, r0-r3 are used to pass args. */
655#define FUNCTION_ARG_REGNO_P(REGNO) \
656 ((REGNO) >= 0 && (REGNO) <= 3)
657
658/* Perform any actions needed for a function that is receiving a variable
659 number of arguments. CUM is as above. MODE and TYPE are the mode and type
660 of the current parameter. PRETEND_SIZE is a variable that should be set to
661 the amount of stack that must be pushed by the prolog to pretend that our
662 caller pushed it.
663
664 Normally, this macro will push all remaining incoming registers on the
665 stack and set PRETEND_SIZE to the length of the registers pushed.
666
667 On the ARM, PRETEND_SIZE is set in order to have the prologue push the last
668 named arg and all anonymous args onto the stack.
669 XXX I know the prologue shouldn't be pushing registers, but it is faster
670 that way. */
671#define SETUP_INCOMING_VARARGS(CUM, MODE, TYPE, PRETEND_SIZE, NO_RTL) \
672{ \
673 extern int current_function_anonymous_args; \
674 current_function_anonymous_args = 1; \
675 if ((CUM) < 16) \
676 (PRETEND_SIZE) = 16 - (CUM); \
677}
678
679/* Generate assembly output for the start of a function. */
680#define FUNCTION_PROLOGUE(STREAM, SIZE) \
008cf58a 681 output_func_prologue ((STREAM), (SIZE))
35d965d5
RS		 682
683/* Call the function profiler with a given profile label. The Acorn compiler
684 puts this BEFORE the prolog but gcc pust it afterwards. The ``mov ip,lr''
685 seems like a good idea to stick with cc convention. ``prof'' doesn't seem
686 to mind about this! */
4eda77ec
RE		 687#define FUNCTION_PROFILER(STREAM,LABELNO) \
688{ \
689 fprintf(STREAM, "\tmov\t%sip, %slr\n", ARM_REG_PREFIX, ARM_REG_PREFIX); \
690 fprintf(STREAM, "\tbl\tmcount\n"); \
691 fprintf(STREAM, "\t.word\tLP%d\n", (LABELNO)); \
692 arm_increase_location (12); \
35d965d5
RS		 693}
694
695/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
696 the stack pointer does not matter. The value is tested only in
697 functions that have frame pointers.
698 No definition is equivalent to always zero.
699
700 On the ARM, the function epilogue recovers the stack pointer from the
701 frame. */
702#define EXIT_IGNORE_STACK 1
703
704/* Generate the assembly code for function exit. */
705#define FUNCTION_EPILOGUE(STREAM, SIZE) \
008cf58a 706 output_func_epilogue ((STREAM), (SIZE))
35d965d5
RS		 707
708/* Determine if the epilogue should be output as RTL.
709 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
ff9940b0
RE		 710#define USE_RETURN_INSN use_return_insn ()
711
712/* Definitions for register eliminations.
713
714 This is an array of structures. Each structure initializes one pair
715 of eliminable registers. The "from" register number is given first,
716 followed by "to". Eliminations of the same "from" register are listed
717 in order of preference.
718
719 We have two registers that can be eliminated on the ARM. First, the
720 arg pointer register can often be eliminated in favor of the stack
721 pointer register. Secondly, the pseudo frame pointer register can always
722 be eliminated; it is replaced with either the stack or the real frame
723 pointer. */
724
725#define ELIMINABLE_REGS \
726{{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
727 {ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
728 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
729 {FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}}
730
731/* Given FROM and TO register numbers, say whether this elimination is allowed.
732 Frame pointer elimination is automatically handled.
733
734 All eliminations are permissible. Note that ARG_POINTER_REGNUM and
735 HARD_FRAME_POINTER_REGNUM are infact the same thing. If we need a frame
736 pointer, we must eliminate FRAME_POINTER_REGNUM into
737 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM. */
738#define CAN_ELIMINATE(FROM, TO) \
739 (((TO) == STACK_POINTER_REGNUM && frame_pointer_needed) ? 0 : 1)
740
741/* Define the offset between two registers, one to be eliminated, and the other
742 its replacement, at the start of a routine. */
743#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
744{ \
745 if ((FROM) == ARG_POINTER_REGNUM && (TO) == HARD_FRAME_POINTER_REGNUM)\
746 (OFFSET) = 0; \
747 else if ((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM)\
748 (OFFSET) = (get_frame_size () + 3 & ~3); \
749 else \
750 { \
751 int regno; \
752 int offset = 12; \
008cf58a 753 int saved_hard_reg = 0; \
ff9940b0 754 \
008cf58a
RE		 755 for (regno = 0; regno <= 10; regno++) \
756 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
757 saved_hard_reg = 1, offset += 4; \
758 for (regno = 16; regno <=23; regno++) \
759 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
ff9940b0
RE		 760 offset += 12; \
761 if ((FROM) == FRAME_POINTER_REGNUM) \
762 (OFFSET) = -offset; \
763 else \
764 { \
765 if (! regs_ever_live[HARD_FRAME_POINTER_REGNUM]) \
766 offset -= 16; \
008cf58a 767 if (regs_ever_live[14] || saved_hard_reg) \
ff9940b0
RE		 768 offset += 4; \
769 (OFFSET) = (get_frame_size () + 3 & ~3) + offset; \
770 } \
771 } \
772}
35d965d5 773
35d965d5
RS		 774/* Output assembler code for a block containing the constant parts
775 of a trampoline, leaving space for the variable parts.
776
777 On the ARM, (if r8 is the static chain regnum, and remembering that
778 referencing pc adds an offset of 8) the trampoline looks like:
779 ldr r8, [pc, #0]
780 ldr pc, [pc]
781 .word static chain value
782 .word function's address */
4eda77ec
RE		 783#define TRAMPOLINE_TEMPLATE(FILE) \
784{ \
785 fprintf ((FILE), "\tldr\t%sr8, [%spc, #0]\n", ARM_REG_PREFIX, \
786 ARM_REG_PREFIX); \
787 fprintf ((FILE), "\tldr\t%spc, [%spc, #0]\n", ARM_REG_PREFIX, \
788 ARM_REG_PREFIX); \
789 fprintf ((FILE), "\t.word\t0\n"); \
790 fprintf ((FILE), "\t.word\t0\n"); \
35d965d5
RS		 791}
792
793/* Length in units of the trampoline for entering a nested function. */
794#define TRAMPOLINE_SIZE 16
795
796/* Alignment required for a trampoline in units. */
797#define TRAMPOLINE_ALIGN 4
798
799/* Emit RTL insns to initialize the variable parts of a trampoline.
800 FNADDR is an RTX for the address of the function's pure code.
801 CXT is an RTX for the static chain value for the function. */
802#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
803{ \
804 emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 8)), \
805 (CXT)); \
806 emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 12)), \
807 (FNADDR)); \
808}
809
35d965d5
RS		 810\f
811/* Addressing modes, and classification of registers for them. */
812
813#define HAVE_POST_INCREMENT 1
814#define HAVE_PRE_INCREMENT 1
815#define HAVE_POST_DECREMENT 1
816#define HAVE_PRE_DECREMENT 1
817
818/* Macros to check register numbers against specific register classes. */
819
820/* These assume that REGNO is a hard or pseudo reg number.
821 They give nonzero only if REGNO is a hard reg of the suitable class
822 or a pseudo reg currently allocated to a suitable hard reg.
823 Since they use reg_renumber, they are safe only once reg_renumber
824 has been allocated, which happens in local-alloc.c.
825
826 On the ARM, don't allow the pc to be used. */
ff9940b0
RE		 827#define REGNO_OK_FOR_BASE_P(REGNO) \
828 ((REGNO) < 15 || (REGNO) == FRAME_POINTER_REGNUM \
829 || (REGNO) == ARG_POINTER_REGNUM \
830 || (unsigned) reg_renumber[(REGNO)] < 15 \
831 || (unsigned) reg_renumber[(REGNO)] == FRAME_POINTER_REGNUM \
832 || (unsigned) reg_renumber[(REGNO)] == ARG_POINTER_REGNUM)
833#define REGNO_OK_FOR_INDEX_P(REGNO) \
35d965d5
RS		 834 REGNO_OK_FOR_BASE_P(REGNO)
835
836/* Maximum number of registers that can appear in a valid memory address.
ff9940b0
RE		 837 Shifts in addresses can't be by a register. */
838
839#define MAX_REGS_PER_ADDRESS 2
35d965d5
RS		 840
841/* Recognize any constant value that is a valid address. */
842/* XXX We can address any constant, eventually... */
843#if 0
844#define CONSTANT_ADDRESS_P(X) \
845 ( GET_CODE(X) == LABEL_REF \
846 || GET_CODE(X) == SYMBOL_REF \
847 || GET_CODE(X) == CONST_INT \
848 || GET_CODE(X) == CONST )
849#endif
850
008cf58a
RE		 851#define CONSTANT_ADDRESS_P(X) \
852 (GET_CODE (X) == SYMBOL_REF \
853 && (CONSTANT_POOL_ADDRESS_P (X) \
854 || (optimize > 0 && SYMBOL_REF_FLAG (X))))
35d965d5
RS		 855
856/* Nonzero if the constant value X is a legitimate general operand.
857 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
858
859 On the ARM, allow any integer (invalid ones are removed later by insn
860 patterns), nice doubles and symbol_refs which refer to the function's
861 constant pool XXX. */
862#define LEGITIMATE_CONSTANT_P(X) \
863 (GET_CODE (X) == CONST_INT \
864 || (GET_CODE (X) == CONST_DOUBLE \
ff9940b0
RE		 865 && (const_double_rtx_ok_for_fpu (X) \
866 || neg_const_double_rtx_ok_for_fpu (X))) \
867 || CONSTANT_ADDRESS_P (X))
868
869/* Symbols in the text segment can be accessed without indirecting via the
870 constant pool; it may take an extra binary operation, but this is still
008cf58a
RE		 871 faster than indirecting via memory. Don't do this when not optimizing,
872 since we won't be calculating al of the offsets necessary to do this
873 simplification. */
ff9940b0
RE		 874
875#define ENCODE_SECTION_INFO(decl) \
876{ \
008cf58a 877 if (optimize > 0 && TREE_CONSTANT (decl) \
ff9940b0 878 && (!flag_writable_strings || TREE_CODE (decl) != STRING_CST)) \
228b6a3f
RS		 879 { \
880 rtx rtl = (TREE_CODE_CLASS (TREE_CODE (decl)) != 'd' \
881 ? TREE_CST_RTL (decl) : DECL_RTL (decl)); \
882 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1; \
883 } \
ff9940b0 884}
35d965d5
RS		 885
886/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
887 and check its validity for a certain class.
888 We have two alternate definitions for each of them.
889 The usual definition accepts all pseudo regs; the other rejects
890 them unless they have been allocated suitable hard regs.
891 The symbol REG_OK_STRICT causes the latter definition to be used. */
892#ifndef REG_OK_STRICT
ff9940b0 893
35d965d5
RS		 894/* Nonzero if X is a hard reg that can be used as a base reg
895 or if it is a pseudo reg. */
ff9940b0
RE		 896#define REG_OK_FOR_BASE_P(X) \
897 (REGNO (X) < 16 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
898 || REGNO (X) == FRAME_POINTER_REGNUM || REGNO (X) == ARG_POINTER_REGNUM)
899
35d965d5
RS		 900/* Nonzero if X is a hard reg that can be used as an index
901 or if it is a pseudo reg. */
902#define REG_OK_FOR_INDEX_P(X) \
903 REG_OK_FOR_BASE_P(X)
ff9940b0
RE		 904
905#define REG_OK_FOR_PRE_POST_P(X) \
906 (REGNO (X) < 16 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
907 || REGNO (X) == FRAME_POINTER_REGNUM || REGNO (X) == ARG_POINTER_REGNUM)
908
35d965d5 909#else
ff9940b0 910
35d965d5
RS		 911/* Nonzero if X is a hard reg that can be used as a base reg. */
912#define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
ff9940b0 913
35d965d5
RS		 914/* Nonzero if X is a hard reg that can be used as an index. */
915#define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
ff9940b0
RE		 916
917#define REG_OK_FOR_PRE_POST_P(X) \
918 (REGNO (X) < 16 || (unsigned) reg_renumber[REGNO (X)] < 16 \
919 || REGNO (X) == FRAME_POINTER_REGNUM || REGNO (X) == ARG_POINTER_REGNUM \
920 || (unsigned) reg_renumber[REGNO (X)] == FRAME_POINTER_REGNUM \
921 || (unsigned) reg_renumber[REGNO (X)] == ARG_POINTER_REGNUM)
922
35d965d5
RS		 923#endif
924\f
925/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
926 that is a valid memory address for an instruction.
927 The MODE argument is the machine mode for the MEM expression
928 that wants to use this address.
929
930 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */
931#define BASE_REGISTER_RTX_P(X) \
932 (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X))
933
934#define INDEX_REGISTER_RTX_P(X) \
935 (GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X))
936
937/* A C statement (sans semicolon) to jump to LABEL for legitimate index RTXs
938 used by the macro GO_IF_LEGITIMATE_ADDRESS. Floating point indices can
939 only be small constants. */
ff9940b0 940#define GO_IF_LEGITIMATE_INDEX(MODE, BASE_REGNO, INDEX, LABEL) \
4d01c30f
RS		 941do \
942{ \
008cf58a
RE		 943 HOST_WIDE_INT range; \
944 enum rtx_code code = GET_CODE (INDEX); \
4d01c30f
RS		 945 \
946 if (GET_MODE_CLASS (MODE) == MODE_FLOAT) \
ff9940b0
RE		 947 { \
948 if (code == CONST_INT && INTVAL (INDEX) < 1024 \
949 && INTVAL (INDEX) > -1024 \
950 && (INTVAL (INDEX) & 3) == 0) \
951 goto LABEL; \
952 } \
4d01c30f
RS		 953 else \
954 { \
ff9940b0 955 if (INDEX_REGISTER_RTX_P (INDEX) && GET_MODE_SIZE (MODE) <= 4) \
4d01c30f 956 goto LABEL; \
ff9940b0 957 if (GET_MODE_SIZE (MODE) <= 4 && code == MULT) \
4d01c30f
RS		 958 { \
959 rtx xiop0 = XEXP (INDEX, 0); \
960 rtx xiop1 = XEXP (INDEX, 1); \
961 if (INDEX_REGISTER_RTX_P (xiop0) \
962 && power_of_two_operand (xiop1, SImode)) \
963 goto LABEL; \
964 if (INDEX_REGISTER_RTX_P (xiop1) \
965 && power_of_two_operand (xiop0, SImode)) \
966 goto LABEL; \
967 } \
ff9940b0 968 if (GET_MODE_SIZE (MODE) <= 4 \
996a5f59 969 && (code == LSHIFTRT || code == ASHIFTRT \
ff9940b0
RE		 970 || code == ASHIFT || code == ROTATERT)) \
971 { \
972 rtx op = XEXP (INDEX, 1); \
973 if (INDEX_REGISTER_RTX_P (XEXP (INDEX, 0)) \
974 && GET_CODE (op) == CONST_INT && INTVAL (op) > 0 \
975 && INTVAL (op) <= 31) \
976 goto LABEL; \
977 } \
978 range = (MODE) == HImode ? 4095 : 4096; \
979 if (code == CONST_INT && INTVAL (INDEX) < range \
980 && INTVAL (INDEX) > -range) \
981 goto LABEL; \
4d01c30f 982 } \
35d965d5
RS		 983} while (0)
984
985/* Jump to LABEL if X is a valid address RTX. This must also take
986 REG_OK_STRICT into account when deciding about valid registers, but it uses
987 the above macros so we are in luck. Allow REG, REG+REG, REG+INDEX,
988 INDEX+REG, REG-INDEX, and non floating SYMBOL_REF to the constant pool.
ff9940b0
RE		 989 Allow REG-only and AUTINC-REG if handling TImode or HImode. Other symbol
990 refs must be forced though a static cell to ensure addressability. */
35d965d5
RS		 991#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
992{ \
993 if (BASE_REGISTER_RTX_P (X)) \
994 goto LABEL; \
995 else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \
996 && GET_CODE (XEXP (X, 0)) == REG \
997 && REG_OK_FOR_PRE_POST_P (XEXP (X, 0))) \
998 goto LABEL; \
999 else if ((MODE) == TImode) \
1000 ; \
1001 else if (GET_CODE (X) == PLUS) \
1002 { \
1003 rtx xop0 = XEXP(X,0); \
1004 rtx xop1 = XEXP(X,1); \
1005 \
1006 if (BASE_REGISTER_RTX_P (xop0)) \
1007 GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop0), xop1, LABEL); \
1008 else if (BASE_REGISTER_RTX_P (xop1)) \
1009 GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop1), xop0, LABEL); \
1010 } \
1011 else if (GET_CODE (X) == MINUS) \
1012 { \
1013 rtx xop0 = XEXP (X,0); \
1014 rtx xop1 = XEXP (X,1); \
1015 \
1016 if (BASE_REGISTER_RTX_P (xop0)) \
1017 GO_IF_LEGITIMATE_INDEX (MODE, -1, xop1, LABEL); \
1018 } \
1019 else if (GET_MODE_CLASS (MODE) != MODE_FLOAT \
1020 && GET_CODE (X) == SYMBOL_REF \
1021 && CONSTANT_POOL_ADDRESS_P (X)) \
1022 goto LABEL; \
1023 else if ((GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_DEC) \
1024 && GET_CODE (XEXP (X, 0)) == REG \
1025 && REG_OK_FOR_PRE_POST_P (XEXP (X, 0))) \
1026 goto LABEL; \
1027}
1028\f
1029/* Try machine-dependent ways of modifying an illegitimate address
1030 to be legitimate. If we find one, return the new, valid address.
1031 This macro is used in only one place: `memory_address' in explow.c.
1032
1033 OLDX is the address as it was before break_out_memory_refs was called.
1034 In some cases it is useful to look at this to decide what needs to be done.
1035
1036 MODE and WIN are passed so that this macro can use
1037 GO_IF_LEGITIMATE_ADDRESS.
1038
1039 It is always safe for this macro to do nothing. It exists to recognize
1040 opportunities to optimize the output.
1041
1042 On the ARM, try to convert [REG, #BIGCONST]
1043 into ADD BASE, REG, #UPPERCONST and [BASE, #VALIDCONST],
1044 where VALIDCONST == 0 in case of TImode. */
1045#define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1046{ \
1047 if (GET_CODE (X) == PLUS) \
1048 { \
1049 rtx xop0 = XEXP (X, 0); \
1050 rtx xop1 = XEXP (X, 1); \
1051 \
1052 if (BASE_REGISTER_RTX_P (xop0) && GET_CODE (xop1) == CONST_INT) \
1053 { \
1054 int n = INTVAL (xop1); \
1055 int low_n = ((MODE) == TImode ? 0 \
1056 : n >= 0 ? (n & 0xFFF) : -((-n) & 0xFFF)); \
1057 rtx base_reg = gen_reg_rtx (SImode); \
1058 rtx val = force_operand (gen_rtx (PLUS, SImode, xop0, \
1059 gen_rtx (CONST_INT, \
1060 VOIDmode, n - low_n)), \
1061 0); \
1062 emit_move_insn (base_reg, val); \
1063 (X) = (low_n == 0 ? base_reg \
1064 : gen_rtx (PLUS, SImode, base_reg, \
1065 gen_rtx (CONST_INT, VOIDmode, low_n))); \
1066 } \
1067 else if (BASE_REGISTER_RTX_P (xop1) && GET_CODE (xop0) == CONST_INT) \
1068 { \
1069 int n = INTVAL (xop0); \
1070 int low_n = ((MODE) == TImode ? 0 \
1071 : n >= 0 ? (n & 0xFFF) : -((-n) & 0xFFF)); \
1072 rtx base_reg = gen_reg_rtx (SImode); \
1073 rtx val = force_operand (gen_rtx (PLUS, SImode, xop1, \
1074 gen_rtx (CONST_INT, \
1075 VOIDmode, n - low_n)), \
1076 0); \
1077 emit_move_insn (base_reg, val); \
1078 (X) = (low_n == 0 ? base_reg \
1079 : gen_rtx (PLUS, SImode, base_reg, \
1080 gen_rtx (CONST_INT, VOIDmode, low_n))); \
1081 } \
1082 } \
1083 if (memory_address_p (MODE, X)) \
1084 goto win; \
1085}
1086
1087/* Go to LABEL if ADDR (a legitimate address expression)
1088 has an effect that depends on the machine mode it is used for. */
1089#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
1090{ \
1091 if (GET_CODE(ADDR) == PRE_DEC || GET_CODE(ADDR) == POST_DEC \
1092 || GET_CODE(ADDR) == PRE_INC || GET_CODE(ADDR) == POST_INC) \
1093 goto LABEL; \
1094}
1095\f
1096/* Specify the machine mode that this machine uses
1097 for the index in the tablejump instruction. */
1098#define CASE_VECTOR_MODE SImode
1099
1100/* Define this if the tablejump instruction expects the table
1101 to contain offsets from the address of the table.
1102 Do not define this if the table should contain absolute addresses. */
1103/* #define CASE_VECTOR_PC_RELATIVE */
1104
1105/* Specify the tree operation to be used to convert reals to integers. */
1106#define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
1107
1108/* This is the kind of divide that is easiest to do in the general case. */
1109#define EASY_DIV_EXPR TRUNC_DIV_EXPR
1110
ff9940b0
RE		 1111/* signed 'char' is most compatible, but RISC OS wants it unsigned.
1112 unsigned is probably best, but may break some code. */
1113#ifndef DEFAULT_SIGNED_CHAR
35d965d5
RS		 1114#define DEFAULT_SIGNED_CHAR 1
1115#endif
1116
1117/* Don't cse the address of the function being compiled. */
1118#define NO_RECURSIVE_FUNCTION_CSE 1
1119
1120/* Max number of bytes we can move from memory to memory
d17ce9af
TG		 1121 in one reasonably fast instruction. */
1122#define MOVE_MAX 4
35d965d5 1123
ff9940b0
RE		 1124/* Define if operations between registers always perform the operation
1125 on the full register even if a narrower mode is specified. */
1126#define WORD_REGISTER_OPERATIONS
1127
1128/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1129 will either zero-extend or sign-extend. The value of this macro should
1130 be the code that says which one of the two operations is implicitly
1131 done, NIL if none. */
1132#define LOAD_EXTEND_OP(MODE) \
1133 ((MODE) == QImode ? ZERO_EXTEND : NIL)
1134
35d965d5
RS		 1135/* Define this if zero-extension is slow (more than one real instruction).
1136 On the ARM, it is more than one instruction only if not fetching from
1137 memory. */
1138/* #define SLOW_ZERO_EXTEND */
1139
1140/* Nonzero if access to memory by bytes is slow and undesirable. */
1141#define SLOW_BYTE_ACCESS 0
1142
1143/* Immediate shift counts are truncated by the output routines (or was it
1144 the assembler?). Shift counts in a register are truncated by ARM. Note
1145 that the native compiler puts too large (> 32) immediate shift counts
1146 into a register and shifts by the register, letting the ARM decide what
1147 to do instead of doing that itself. */
ff9940b0
RE		 1148/* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that
1149 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
1150 On the arm, Y in a register is used modulo 256 for the shift. Only for
1151 rotates is modulo 32 used. */
1152/* #define SHIFT_COUNT_TRUNCATED 1 */
35d965d5
RS		 1153
1154/* XX This is not true, is it? */
1155/* All integers have the same format so truncation is easy. */
1156#define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1
1157
1158/* Calling from registers is a massive pain. */
1159#define NO_FUNCTION_CSE 1
1160
1161/* Chars and shorts should be passed as ints. */
1162#define PROMOTE_PROTOTYPES 1
1163
35d965d5
RS		 1164/* The machine modes of pointers and functions */
1165#define Pmode SImode
1166#define FUNCTION_MODE Pmode
1167
1168/* The structure type of the machine dependent info field of insns
1169 No uses for this yet. */
1170/* #define INSN_MACHINE_INFO struct machine_info */
1171
1172/* The relative costs of various types of constants. Note that cse.c defines
1173 REG = 1, SUBREG = 2, any node = (2 + sum of subnodes). */
ff9940b0
RE		 1174#define CONST_COSTS(RTX, CODE, OUTER_CODE) \
1175 case CONST_INT: \
1176 if (const_ok_for_arm (INTVAL (RTX))) \
1177 return (OUTER_CODE) == SET ? 2 : -1; \
1178 else if (OUTER_CODE == AND \
1179 && const_ok_for_arm (~INTVAL (RTX))) \
1180 return -1; \
1181 else if ((OUTER_CODE == COMPARE \
1182 || OUTER_CODE == PLUS || OUTER_CODE == MINUS) \
1183 && const_ok_for_arm (-INTVAL (RTX))) \
1184 return -1; \
1185 else \
1186 return 5; \
1187 case CONST: \
1188 case LABEL_REF: \
1189 case SYMBOL_REF: \
1190 return 6; \
1191 case CONST_DOUBLE: \
1192 if (const_double_rtx_ok_for_fpu (RTX)) \
1193 return (OUTER_CODE) == SET ? 2 : -1; \
1194 else if (((OUTER_CODE) == COMPARE || (OUTER_CODE) == PLUS) \
1195 && neg_const_double_rtx_ok_for_fpu (RTX)) \
1196 return -1; \
1197 return(7);
1198
1199#define RTX_COSTS(X,CODE,OUTER_CODE) \
1200 case MEM: \
1201 { \
1202 int num_words = (GET_MODE_SIZE (GET_MODE (X)) > UNITS_PER_WORD) ? 2 : 1;\
1203 return (COSTS_N_INSNS (10*num_words)); \
1204 } \
1205 case MULT: \
1206 if (GET_CODE (XEXP (X, 1)) == CONST_INT \
1207 && exact_log2 (INTVAL (XEXP (X, 1))) >= 0) \
1208 return rtx_cost (XEXP (X, 0), GET_CODE (X))+1; \
1209 return COSTS_N_INSNS (9); \
ff9940b0
RE		 1210 case ASHIFT: \
1211 case LSHIFTRT: \
1212 case ASHIFTRT: \
1213 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
1214 return rtx_cost (XEXP (X, 0), GET_CODE (X))+1; \
1215 break; \
1216 case MINUS: \
1217 { \
1218 enum rtx_code code = GET_CODE (XEXP (X, 1)); \
1219 if (code == MULT) \
1220 { \
1221 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT \
1222 && exact_log2 (INTVAL (XEXP (XEXP (X, 0), 1))) >= 0) \
1223 return COSTS_N_INSNS (1); \
1224 break; \
1225 } \
996a5f59 1226 else if (code == ASHIFT || code == ASHIFTRT || code == LSHIFTRT) \
ff9940b0
RE		 1227 return COSTS_N_INSNS (1); \
1228 } /* fall through */ \
1229 case PLUS: \
1230 case IOR: \
1231 case XOR: \
1232 case AND: \
1233 { \
1234 enum rtx_code code = GET_CODE (XEXP (X, 0)); \
1235 if (code == MULT) \
1236 { \
1237 if (GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \
1238 && exact_log2 (INTVAL (XEXP (XEXP (X, 0), 1))) >= 0) \
1239 return COSTS_N_INSNS (1); \
1240 if (GET_CODE (X) == PLUS) \
1241 return COSTS_N_INSNS (12); \
1242 break; \
1243 } \
996a5f59 1244 else if (code == ASHIFT || code == ASHIFTRT || code == LSHIFTRT) \
ff9940b0
RE		 1245 return COSTS_N_INSNS (1); \
1246 break; \
1247 } \
1248 case NOT: \
1249 return rtx_cost (XEXP (X, 0), GET_CODE (XEXP (X, 0))); \
1250 case IF_THEN_ELSE: \
1251 { \
1252 if (GET_CODE (XEXP(X,1)) == PC || GET_CODE (XEXP(X,2)) == PC) \
1253 return COSTS_N_INSNS (4); \
1254 return COSTS_N_INSNS (1); \
1255 } \
1256 case SIGN_EXTEND: \
1257 return COSTS_N_INSNS (2); \
1258 case ZERO_EXTEND: \
1259 if (GET_MODE (XEXP (X, 0)) == QImode) \
1260 { \
1261 if (GET_CODE (XEXP (X, 0)) == MEM) \
1262 return COSTS_N_INSNS (10); \
1263 return COSTS_N_INSNS (1); \
1264 } \
1265 break; \
1266 case COMPARE: \
1267 if (GET_CODE (XEXP (X, 1)) == REG) \
1268 return 4; \
1269 case SMIN: \
1270 case SMAX: \
1271 case UMIN: \
1272 case UMAX: \
1273 return COSTS_N_INSNS (3); \
1274 case ABS: \
1275 if (GET_MODE (X) == SImode) \
1276 return COSTS_N_INSNS (2); \
1277 return COSTS_N_INSNS (1);
1278
1279/* Moves to and from memory are quite expensive */
1280#define MEMORY_MOVE_COST(MODE) 10
1281
1282/* All address computations that can be done are free */
1283#define ADDRESS_COST(x) 2
1284
1285/* Try to generate sequences that don't involve branches, we can then use
1286 conditional instructions */
1287#define BRANCH_COST 4
35d965d5 1288\f
ff9940b0
RE		 1289/* Condition code information. */
1290/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1291 return the mode to be used for the comparison.
1292 CCFPEmode should be used with floating inequalites,
1293 CCFPmode should be used with floating equalities.
1294 CC_NOOVmode should be used with SImode integer equalites
1295 CCmode should be used otherwise. */
1296
1297#define EXTRA_CC_MODES CC_NOOVmode, CCFPmode, CCFPEmode
1298
1299#define EXTRA_CC_NAMES "CC_NOOV", "CCFP", "CCFPE"
1300
1301#define SELECT_CC_MODE(OP,X,Y) \
1302 (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
1303 ? ((OP == EQ || OP == NE) ? CCFPmode : CCFPEmode) \
1304 : ((GET_MODE (X) == SImode) \
1305 && ((OP) == EQ || (OP) == NE) \
1306 && (GET_CODE (X) == PLUS || GET_CODE (X) == MINUS \
1307 || GET_CODE (X) == AND || GET_CODE (X) == IOR \
1308 || GET_CODE (X) == XOR || GET_CODE (X) == MULT \
1309 || GET_CODE (X) == NOT || GET_CODE (X) == NEG \
996a5f59 1310 || GET_CODE (X) == LSHIFTRT \
ff9940b0
RE		 1311 || GET_CODE (X) == ASHIFT || GET_CODE (X) == ASHIFTRT \
1312 || GET_CODE (X) == ROTATERT || GET_CODE (X) == ZERO_EXTRACT) \
1313 ? CC_NOOVmode \
1314 : GET_MODE (X) == QImode ? CC_NOOVmode : CCmode))
1315
008cf58a
RE		 1316#define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode)
1317
ff9940b0
RE		 1318#define STORE_FLAG_VALUE 1
1319
1320/* Define the information needed to generate branch insns. This is
1321 stored from the compare operation. Note that we can't use "rtx" here
1322 since it hasn't been defined! */
1323
1324extern struct rtx_def *arm_compare_op0, *arm_compare_op1;
1325extern int arm_compare_fp;
1326
1327/* Define the codes that are matched by predicates in arm.c */
1328#define PREDICATE_CODES \
1329 {"s_register_operand", {SUBREG, REG}}, \
1330 {"arm_add_operand", {SUBREG, REG, CONST_INT}}, \
1331 {"fpu_add_operand", {SUBREG, REG, CONST_DOUBLE}}, \
1332 {"arm_rhs_operand", {SUBREG, REG, CONST_INT}}, \
1333 {"fpu_rhs_operand", {SUBREG, REG, CONST_DOUBLE}}, \
1334 {"arm_not_operand", {SUBREG, REG, CONST_INT}}, \
1335 {"shiftable_operator", {PLUS, MINUS, AND, IOR, XOR}}, \
1336 {"minmax_operator", {SMIN, SMAX, UMIN, UMAX}}, \
996a5f59 1337 {"shift_operator", {ASHIFT, ASHIFTRT, LSHIFTRT, MULT}}, \
ff9940b0
RE		 1338 {"di_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE, MEM}}, \
1339 {"load_multiple_operation", {PARALLEL}}, \
1340 {"store_multiple_operation", {PARALLEL}}, \
1341 {"equality_operator", {EQ, NE}}, \
1342 {"arm_rhsm_operand", {SUBREG, REG, CONST_INT, MEM}}, \
1343 {"const_shift_operand", {CONST_INT}}, \
1344 {"index_operand", {SUBREG, REG, CONST_INT}}, \
1345 {"cc_register", {REG}},
1346
35d965d5
RS		 1347\f
1348/* Assembler output control */
1349
ff9940b0
RE		 1350#ifndef ARM_OS_NAME
1351#define ARM_OS_NAME "(generic)"
1352#endif
1353
35d965d5 1354/* The text to go at the start of the assembler file */
4eda77ec
RE		 1355#define ASM_FILE_START(STREAM) \
1356{ \
1357 extern char *version_string; \
1358 fprintf (STREAM,"%c Generated by gcc %s for ARM/%s\n", \
1359 ARM_COMMENT_CHAR, version_string, ARM_OS_NAME); \
1360 fprintf (STREAM,"%srfp\t.req\t%sr9\n", ARM_REG_PREFIX, ARM_REG_PREFIX); \
1361 fprintf (STREAM,"%ssl\t.req\t%sr10\n", ARM_REG_PREFIX, ARM_REG_PREFIX); \
1362 fprintf (STREAM,"%sfp\t.req\t%sr11\n", ARM_REG_PREFIX, ARM_REG_PREFIX); \
1363 fprintf (STREAM,"%sip\t.req\t%sr12\n", ARM_REG_PREFIX, ARM_REG_PREFIX); \
1364 fprintf (STREAM,"%ssp\t.req\t%sr13\n", ARM_REG_PREFIX, ARM_REG_PREFIX); \
1365 fprintf (STREAM,"%slr\t.req\t%sr14\n", ARM_REG_PREFIX, ARM_REG_PREFIX); \
1366 fprintf (STREAM,"%spc\t.req\t%sr15\n", ARM_REG_PREFIX, ARM_REG_PREFIX); \
35d965d5
RS		 1367}
1368
1369#define ASM_APP_ON ""
1370#define ASM_APP_OFF ""
1371
1372/* Switch to the text or data segment. */
8cf6b9ca
RS		 1373#define TEXT_SECTION_ASM_OP ".text"
1374#define DATA_SECTION_ASM_OP ".data"
35d965d5 1375
4eda77ec
RE		 1376/* The assembler's names for the registers. */
1377#ifndef REGISTER_NAMES
35d965d5
RS		 1378#define REGISTER_NAMES \
1379{ \
1380 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
4eda77ec 1381 "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc", \
ff9940b0
RE		 1382 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \
1383 "cc", "sfp", "afp" \
35d965d5 1384}
4eda77ec
RE		 1385#endif
1386
1387#ifndef ADDITIONAL_REGISTER_NAMES
1388#define ADDITIONAL_REGISTER_NAMES \
1389{ \
1390 {"a1", 0}, \
1391 {"a2", 1}, \
1392 {"a3", 2}, \
1393 {"a4", 3}, \
1394 {"v1", 4}, \
1395 {"v2", 5}, \
1396 {"v3", 6}, \
1397 {"v4", 7}, \
1398 {"v5", 8}, \
1399 {"v6", 9}, \
1400 {"rfp", 9}, /* Gcc used to call it this */ \
1401 {"sb", 9}, \
1402 {"v7", 10}, \
1403 {"r10", 10}, \
1404 {"r11", 11}, /* fp */ \
1405 {"r12", 12}, /* ip */ \
1406 {"r13", 13}, /* sp */ \
1407 {"r14", 14}, /* lr */ \
1408 {"r15", 15} /* pc */ \
1409}
1410#endif
35d965d5 1411
ff9940b0
RE		 1412/* Arm Assembler barfs on dollars */
1413#define DOLLARS_IN_IDENTIFIERS 0
1414
1415#define NO_DOLLAR_IN_LABEL
1416
35d965d5
RS		 1417/* DBX register number for a given compiler register number */
1418#define DBX_REGISTER_NUMBER(REGNO) (REGNO)
1419
ff9940b0
RE		 1420/* Generate DBX debugging information. riscix.h will undefine this because
1421 the native assembler does not support stabs. */
35d965d5
RS		 1422#define DBX_DEBUGGING_INFO 1
1423
1424/* Acorn dbx moans about continuation chars, so don't use any. */
1425#define DBX_CONTIN_LENGTH 0
1426
ff9940b0
RE		 1427/* Output a source filename for the debugger. RISCiX dbx insists that the
1428 ``desc'' field is set to compiler version number >= 315 (sic). */
1429#define DBX_OUTPUT_MAIN_SOURCE_FILENAME(STREAM,NAME) \
1430do { \
1431 fprintf (STREAM, ".stabs \"%s\",%d,0,315,%s\n", (NAME), N_SO, \
1432 &ltext_label_name[1]); \
1433 text_section (); \
1434 ASM_OUTPUT_INTERNAL_LABEL (STREAM, "Ltext", 0); \
1435} while (0)
1436
35d965d5
RS		 1437/* Output a label definition. */
1438#define ASM_OUTPUT_LABEL(STREAM,NAME) \
1439 arm_asm_output_label ((STREAM), (NAME))
1440
1441/* Output a function label definition. */
1442#define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL) \
1443 ASM_OUTPUT_LABEL(STREAM, NAME)
1444
1445/* Output a globalising directive for a label. */
1446#define ASM_GLOBALIZE_LABEL(STREAM,NAME) \
1447 (fprintf (STREAM, "\t.global\t"), \
1448 assemble_name (STREAM, NAME), \
1449 fputc ('\n',STREAM)) \
1450
1451/* Output a reference to a label. */
1452#define ASM_OUTPUT_LABELREF(STREAM,NAME) \
1453 fprintf (STREAM, "_%s", NAME)
1454
1455/* Make an internal label into a string. */
1456#define ASM_GENERATE_INTERNAL_LABEL(STRING, PREFIX, NUM) \
1457 sprintf (STRING, "*%s%d", PREFIX, NUM)
1458
1459/* Output an internal label definition. */
1460#define ASM_OUTPUT_INTERNAL_LABEL(STREAM, PREFIX, NUM) \
1461 do \
1462 { \
1463 char *s = (char *) alloca (11 + strlen (PREFIX)); \
1464 extern int arm_target_label, arm_ccfsm_state; \
26563586 1465 extern rtx arm_target_insn; \
35d965d5 1466 \
ff9940b0
RE		 1467 if (arm_ccfsm_state == 3 && arm_target_label == (NUM) \
1468 && !strcmp (PREFIX, "L")) \
1469 { \
1470 arm_ccfsm_state = 0; \
26563586 1471 arm_target_insn = NULL; \
ff9940b0
RE		 1472 } \
1473 strcpy (s, "*"); \
1474 sprintf (&s[strlen (s)], "%s%d", (PREFIX), (NUM)); \
1475 arm_asm_output_label (STREAM, s); \
35d965d5
RS		 1476 } while (0)
1477
1478/* Nothing special is done about jump tables */
1479/* #define ASM_OUTPUT_CASE_LABEL(STREAM,PREFIX,NUM,TABLE) */
1480/* #define ASM_OUTPUT_CASE_END(STREAM,NUM,TABLE) */
1481
1482/* Construct a private name. */
1483#define ASM_FORMAT_PRIVATE_NAME(OUTVAR,NAME,NUMBER) \
1484 ((OUTVAR) = (char *) alloca (strlen (NAME) + 10), \
1485 sprintf ((OUTVAR), "%s.%d", (NAME), (NUMBER)))
1486
1487/* Output a push or a pop instruction (only used when profiling). */
4eda77ec
RE		 1488#define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
1489 fprintf(STREAM,"\tstmfd\t%ssp!,{%s%s}\n", ARM_REG_PREFIX, ARM_REG_PREFIX, \
1490 reg_names[REGNO])
35d965d5 1491
4eda77ec
RE		 1492#define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
1493 fprintf(STREAM,"\tldmfd\t%ssp!,{%s%s}\n", ARM_REG_PREFIX, ARM_REG_PREFIX, \
1494 reg_names[REGNO])
35d965d5
RS		 1495
1496/* Output a relative address. Not needed since jump tables are absolute
1497 but we must define it anyway. */
1498#define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,VALUE,REL) \
1499 fputs ("- - - ASM_OUTPUT_ADDR_DIFF_ELT called!\n", STREAM)
1500
1501/* Output an element of a dispatch table. */
1502#define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \
008cf58a 1503 fprintf (STREAM, "\t.word\tL%d\n", VALUE)
35d965d5 1504
7fc6c9f0
RK		 1505/* Output various types of constants. For real numbers we output hex, with
1506 a comment containing the "human" value, this allows us to pass NaN's which
1507 the riscix assembler doesn't understand (it also makes cross-assembling
1508 less likely to fail). */
1509
ff9940b0 1510#define ASM_OUTPUT_LONG_DOUBLE(STREAM,VALUE) \
7fc6c9f0
RK		 1511do { char dstr[30]; \
1512 long l[3]; \
ff9940b0
RE		 1513 arm_increase_location (12); \
1514 REAL_VALUE_TO_TARGET_LONG_DOUBLE (VALUE, l); \
7fc6c9f0 1515 REAL_VALUE_TO_DECIMAL (VALUE, "%.20g", dstr); \
ff9940b0 1516 if (sizeof (int) == sizeof (long)) \
4eda77ec
RE		 1517 fprintf (STREAM, "\t.long 0x%x,0x%x,0x%x\t%c long double %s\n", \
1518 l[2], l[1], l[0], ARM_COMMENT_CHAR, dstr); \
ff9940b0 1519 else \
4eda77ec
RE		 1520 fprintf (STREAM, "\t.long 0x%lx,0x%lx,0x%lx\t%c long double %s\n",\
1521 l[0], l[1], l[2], ARM_COMMENT_CHAR, dstr); \
ff9940b0
RE		 1522 } while (0)
1523
1524
7fc6c9f0
RK		 1525#define ASM_OUTPUT_DOUBLE(STREAM, VALUE) \
1526do { char dstr[30]; \
1527 long l[2]; \
1528 arm_increase_location (8); \
1529 REAL_VALUE_TO_TARGET_DOUBLE (VALUE, l); \
1530 REAL_VALUE_TO_DECIMAL (VALUE, "%.14g", dstr); \
1531 if (sizeof (int) == sizeof (long)) \
4eda77ec
RE		 1532 fprintf (STREAM, "\t.long 0x%x, 0x%x\t%c double %s\n", l[0], \
1533 l[1], ARM_COMMENT_CHAR, dstr); \
7fc6c9f0 1534 else \
4eda77ec
RE		 1535 fprintf (STREAM, "\t.long 0x%lx, 0x%lx\t%c double %s\n", l[0], \
1536 l[1], ARM_COMMENT_CHAR, dstr); \
ff9940b0
RE		 1537 } while (0)
1538
7fc6c9f0
RK		 1539#define ASM_OUTPUT_FLOAT(STREAM, VALUE) \
1540do { char dstr[30]; \
1541 long l; \
1542 arm_increase_location (4); \
1543 REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \
1544 REAL_VALUE_TO_DECIMAL (VALUE, "%.7g", dstr); \
1545 if (sizeof (int) == sizeof (long)) \
4eda77ec
RE		 1546 fprintf (STREAM, "\t.word 0x%x\t%c float %s\n", l, \
1547 ARM_COMMENT_CHAR, dstr); \
7fc6c9f0 1548 else \
4eda77ec
RE		 1549 fprintf (STREAM, "\t.word 0x%lx\t%c float %s\n", l, \
1550 ARM_COMMENT_CHAR, dstr); \
ff9940b0 1551 } while (0);
35d965d5 1552
7fc6c9f0
RK		 1553#define ASM_OUTPUT_INT(STREAM, EXP) \
1554 (fprintf (STREAM, "\t.word\t"), \
1555 output_addr_const (STREAM, (EXP)), \
1556 arm_increase_location (4), \
35d965d5
RS		 1557 fputc ('\n', STREAM))
1558
1559#define ASM_OUTPUT_SHORT(STREAM, EXP) \
1560 (fprintf (STREAM, "\t.short\t"), \
1561 output_addr_const (STREAM, (EXP)), \
1562 arm_increase_location (2), \
1563 fputc ('\n', STREAM))
1564
1565#define ASM_OUTPUT_CHAR(STREAM, EXP) \
1566 (fprintf (STREAM, "\t.byte\t"), \
1567 output_addr_const (STREAM, (EXP)), \
1568 arm_increase_location (1), \
1569 fputc ('\n', STREAM))
1570
1571#define ASM_OUTPUT_BYTE(STREAM, VALUE) \
1572 (fprintf (STREAM, "\t.byte\t%d\n", VALUE), \
1573 arm_increase_location (1))
1574
1575#define ASM_OUTPUT_ASCII(STREAM, PTR, LEN) \
f70bf59e 1576 output_ascii_pseudo_op ((STREAM), (unsigned char *)(PTR), (LEN))
35d965d5
RS		 1577
1578/* Output a gap. In fact we fill it with nulls. */
1579#define ASM_OUTPUT_SKIP(STREAM, NBYTES) \
1580 (arm_increase_location (NBYTES), \
1581 fprintf (STREAM, "\t.space\t%d\n", NBYTES))
1582
1583/* Align output to a power of two. Horrible /bin/as. */
1584#define ASM_OUTPUT_ALIGN(STREAM, POWER) \
1585 do \
1586 { \
1587 register int amount = 1 << (POWER); \
1588 extern int arm_text_location; \
1589 \
1590 if (amount == 2) \
1591 fprintf (STREAM, "\t.even\n"); \
1592 else \
1593 fprintf (STREAM, "\t.align\t%d\n", amount - 4); \
1594 \
1595 if (in_text_section ()) \
1596 arm_text_location = ((arm_text_location + amount - 1) \
1597 & ~(amount - 1)); \
1598 } while (0)
1599
1600/* Output a common block */
4eda77ec
RE		 1601#define ASM_OUTPUT_COMMON(STREAM, NAME, SIZE, ROUNDED) \
1602 (fprintf (STREAM, "\t.comm\t"), \
1603 assemble_name ((STREAM), (NAME)), \
1604 fprintf(STREAM, ", %d\t%c%d\n", ROUNDED, ARM_COMMENT_CHAR, SIZE))
35d965d5
RS		 1605
1606/* Output a local common block. /bin/as can't do this, so hack a `.space' into
1607 the bss segment. Note that this is *bad* practice. */
1608#define ASM_OUTPUT_LOCAL(STREAM,NAME,SIZE,ROUNDED) \
1609 output_lcomm_directive (STREAM, NAME, SIZE, ROUNDED)
1610
35d965d5
RS		 1611/* Output a source line for the debugger. */
1612/* #define ASM_OUTPUT_SOURCE_LINE(STREAM,LINE) */
1613
1614/* Output a #ident directive. */
1615#define ASM_OUTPUT_IDENT(STREAM,STRING) \
1616 fprintf (STREAM,"- - - ident %s\n",STRING)
1617
1618/* The assembler's parentheses characters. */
1619#define ASM_OPEN_PAREN "("
1620#define ASM_CLOSE_PAREN ")"
1621
1622/* Target characters. */
1623#define TARGET_BELL 007
1624#define TARGET_BS 010
1625#define TARGET_TAB 011
1626#define TARGET_NEWLINE 012
1627#define TARGET_VT 013
1628#define TARGET_FF 014
1629#define TARGET_CR 015
1630\f
35d965d5
RS		 1631/* Only perform branch elimination (by making instructions conditional) if
1632 we're optimising. Otherwise it's of no use anyway. */
1633#define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
1634 if (optimize) \
1635 final_prescan_insn (INSN, OPVEC, NOPERANDS)
1636
7bc7696c
RE		 1637#ifndef ARM_COMMENT_CHAR
1638#define ARM_COMMENT_CHAR '@'
1639#endif
1640
1641/* Default is for register names not to have a prefix. */
1642#ifndef ARM_REG_PREFIX
1643#define ARM_REG_PREFIX ""
1644#endif
1645
1646#define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
1647 ((CODE) == '?' || (CODE) == '|' || (CODE) == '@')
1648/* Output an operand of an instruction. */
35d965d5 1649#define PRINT_OPERAND(STREAM, X, CODE) \
7bc7696c
RE		 1650 arm_print_operand (STREAM, X, CODE)
1651
1652#define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \
1653 (HOST_BITS_PER_WIDE_INT <= 32 ? (x) \
1654 : (((x) & (unsigned HOST_WIDE_INT) 0xffffffff) | \
1655 (((x) & (unsigned HOST_WIDE_INT) 0x80000000) \
1656 ? ((~ (HOST_WIDE_INT) 0) \
1657 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \
1658 : 0))))
35d965d5
RS		 1659
1660/* Output the address of an operand. */
1661#define PRINT_OPERAND_ADDRESS(STREAM,X) \
1662{ \
1663 int is_minus = GET_CODE (X) == MINUS; \
1664 \
1665 if (GET_CODE (X) == REG) \
4eda77ec
RE		 1666 fprintf (STREAM, "[%s%s, #0]", ARM_REG_PREFIX, \
1667 reg_names[REGNO (X)]); \
35d965d5
RS		 1668 else if (GET_CODE (X) == PLUS || is_minus) \
1669 { \
1670 rtx base = XEXP (X, 0); \
1671 rtx index = XEXP (X, 1); \
1672 char *base_reg_name; \
7bc7696c 1673 HOST_WIDE_INT offset = 0; \
35d965d5
RS		 1674 if (GET_CODE (base) != REG) \
1675 { \
1676 /* Ensure that BASE is a register (one of them must be). */ \
1677 rtx temp = base; \
1678 base = index; \
1679 index = temp; \
1680 } \
1681 base_reg_name = reg_names[REGNO (base)]; \
1682 switch (GET_CODE (index)) \
1683 { \
1684 case CONST_INT: \
1685 offset = INTVAL (index); \
1686 if (is_minus) \
1687 offset = -offset; \
4eda77ec
RE		 1688 fprintf (STREAM, "[%s%s, #%d]", ARM_REG_PREFIX, \
1689 base_reg_name, offset); \
35d965d5
RS		 1690 break; \
1691 \
1692 case REG: \
4eda77ec
RE		 1693 fprintf (STREAM, "[%s%s, %s%s%s]", ARM_REG_PREFIX, \
1694 base_reg_name, is_minus ? "-" : "", \
1695 ARM_REG_PREFIX, reg_names[REGNO (index)] ); \
35d965d5
RS		 1696 break; \
1697 \
1698 case MULT: \
ff9940b0
RE		 1699 case ASHIFTRT: \
1700 case LSHIFTRT: \
1701 case ASHIFT: \
ff9940b0
RE		 1702 case ROTATERT: \
1703 { \
4eda77ec
RE		 1704 fprintf (STREAM, "[%s%s, %s%s%s, ", ARM_REG_PREFIX, \
1705 base_reg_name, is_minus ? "-" : "", ARM_REG_PREFIX,\
7bc7696c
RE		 1706 reg_names[REGNO (XEXP (index, 0))]); \
1707 arm_print_operand (STREAM, index, 'S'); \
1708 fputs ("]", STREAM); \
ff9940b0
RE		 1709 break; \
1710 } \
35d965d5
RS		 1711 \
1712 default: \
1713 abort(); \
1714 } \
1715 } \
1716 else if (GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC \
1717 || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC) \
1718 { \
1719 extern int output_memory_reference_mode; \
1720 \
1721 if (GET_CODE (XEXP (X, 0)) != REG) \
1722 abort (); \
1723 \
1724 if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \
4eda77ec
RE		 1725 fprintf (STREAM, "[%s%s, #%s%d]!", ARM_REG_PREFIX, \
1726 reg_names[REGNO (XEXP (X, 0))], \
35d965d5
RS		 1727 GET_CODE (X) == PRE_DEC ? "-" : "", \
1728 GET_MODE_SIZE (output_memory_reference_mode)); \
1729 else \
4eda77ec
RE		 1730 fprintf (STREAM, "[%s%s], #%s%d", ARM_REG_PREFIX, \
1731 reg_names[REGNO (XEXP (X, 0))], \
35d965d5
RS		 1732 GET_CODE (X) == POST_DEC ? "-" : "", \
1733 GET_MODE_SIZE (output_memory_reference_mode)); \
1734 } \
1735 else output_addr_const(STREAM, X); \
1736}
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